| commit | e0d517eb8240278578efdb42366b167ce65ceaba | [log] [tgz] |
|---|---|---|
| author | Rupert Swarbrick <rswarbrick@lowrisc.org> | Tue Feb 02 10:46:25 2021 +0000 |
| committer | Rupert Swarbrick <rswarbrick@gmail.com> | Tue Feb 02 18:12:38 2021 +0000 |
| tree | a830492bde0c550e3e66edaf625d538e9be05ffe | |
| parent | 96c905b2473ea2ccbfd87e1eba8851ee5db64509 [diff] |
[topgen] Don't generate empty clock_reset_export entries The check_clk_rst_export function was essentially the same thing as setdefault(). Since topgen's merge.py is actually the only thing that reads this key, keep the same defaulting behaviour but don't actually generate extra entries. If we don't do this, we have to add clock_reset_export to the optional fields list for every type in topgen/validate.py to avoid a warning. Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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