[prim_rom] Propagate port changes to top level and FPGA scripts
Signed-off-by: Michael Schaffner <msf@opentitan.org>
diff --git a/hw/top_earlgrey/data/placement.xdc b/hw/top_earlgrey/data/placement.xdc
index 6a6b0dd..328c437 100644
--- a/hw/top_earlgrey/data/placement.xdc
+++ b/hw/top_earlgrey/data/placement.xdc
@@ -1,7 +1,7 @@
# Any change in ROM instances path should be updated in following two files
# 1. hw/top_earlgrey/data/placement.xdc and
# 2. hw/top_earlgrey/util/vivado_hook_opt_design_post.tcl
-set_property LOC RAMB36_X4Y18 [get_cells -hierarchical -filter { NAME =~ "*rom_rom*dout_o_reg_0" && PRIMITIVE_TYPE =~ BMEM.*.* }]
-set_property LOC RAMB36_X4Y19 [get_cells -hierarchical -filter { NAME =~ "*rom_rom*dout_o_reg_1" && PRIMITIVE_TYPE =~ BMEM.*.* }]
-set_property LOC RAMB36_X3Y14 [get_cells -hierarchical -filter { NAME =~ "*rom_rom*dout_o_reg_2" && PRIMITIVE_TYPE =~ BMEM.*.* }]
-set_property LOC RAMB36_X3Y15 [get_cells -hierarchical -filter { NAME =~ "*rom_rom*dout_o_reg_3" && PRIMITIVE_TYPE =~ BMEM.*.* }]
+set_property LOC RAMB36_X4Y18 [get_cells -hierarchical -filter { NAME =~ "*rom_rom*rdata_o_reg_0" && PRIMITIVE_TYPE =~ BMEM.*.* }]
+set_property LOC RAMB36_X4Y19 [get_cells -hierarchical -filter { NAME =~ "*rom_rom*rdata_o_reg_1" && PRIMITIVE_TYPE =~ BMEM.*.* }]
+set_property LOC RAMB36_X3Y14 [get_cells -hierarchical -filter { NAME =~ "*rom_rom*rdata_o_reg_2" && PRIMITIVE_TYPE =~ BMEM.*.* }]
+set_property LOC RAMB36_X3Y15 [get_cells -hierarchical -filter { NAME =~ "*rom_rom*rdata_o_reg_3" && PRIMITIVE_TYPE =~ BMEM.*.* }]
diff --git a/hw/top_earlgrey/data/top_earlgrey.sv.tpl b/hw/top_earlgrey/data/top_earlgrey.sv.tpl
index de44cca..168d09f 100644
--- a/hw/top_earlgrey/data/top_earlgrey.sv.tpl
+++ b/hw/top_earlgrey/data/top_earlgrey.sv.tpl
@@ -420,7 +420,7 @@
.rerror_i (2'b00)
);
- prim_rom #(
+ prim_rom_adv #(
.Width(${data_width}),
.Depth(${rom_depth}),
.MemInitFile(BootRomInitFile)
@@ -431,10 +431,11 @@
% for key in resets:
.${key} (${top["reset_paths"][resets[key]]}),
% endfor
- .cs_i (${m["name"]}_req),
+ .req_i (${m["name"]}_req),
.addr_i (${m["name"]}_addr),
- .dout_o (${m["name"]}_rdata),
- .dvalid_o (${m["name"]}_rvalid)
+ .rdata_o (${m["name"]}_rdata),
+ .rvalid_o (${m["name"]}_rvalid),
+ .cfg_i ('0) // tied off for now
);
% elif m["type"] == "eflash":
diff --git a/hw/top_earlgrey/dv/tb/tb.sv b/hw/top_earlgrey/dv/tb/tb.sv
index f5d209c..b489917 100644
--- a/hw/top_earlgrey/dv/tb/tb.sv
+++ b/hw/top_earlgrey/dv/tb/tb.sv
@@ -57,7 +57,7 @@
jtag_if jtag_if();
// backdoors
- bind `ROM_HIER mem_bkdr_if rom_mem_bkdr_if();
+ bind `ROM_HIER.u_prim_rom mem_bkdr_if rom_mem_bkdr_if();
bind `RAM_MAIN_HIER.u_mem mem_bkdr_if ram_mem_bkdr_if();
bind `FLASH0_MEM_HIER mem_bkdr_if flash0_mem_bkdr_if();
bind `FLASH1_MEM_HIER mem_bkdr_if flash1_mem_bkdr_if();
@@ -189,7 +189,7 @@
// Backdoors
uvm_config_db#(virtual mem_bkdr_if)::set(
- null, "*.env", "mem_bkdr_vifs[Rom]", `ROM_HIER.rom_mem_bkdr_if);
+ null, "*.env", "mem_bkdr_vifs[Rom]", `ROM_HIER.u_prim_rom.rom_mem_bkdr_if);
uvm_config_db#(virtual mem_bkdr_if)::set(
null, "*.env", "mem_bkdr_vifs[Ram]", `RAM_MAIN_HIER.u_mem.ram_mem_bkdr_if);
uvm_config_db#(virtual mem_bkdr_if)::set(
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index 6b8ac62..b852efa 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -370,17 +370,18 @@
.rerror_i (2'b00)
);
- prim_rom #(
+ prim_rom_adv #(
.Width(32),
.Depth(4096),
.MemInitFile(BootRomInitFile)
) u_rom_rom (
.clk_i (clkmgr_clocks.clk_main_infra),
.rst_ni (rstmgr_resets.rst_sys_n),
- .cs_i (rom_req),
+ .req_i (rom_req),
.addr_i (rom_addr),
- .dout_o (rom_rdata),
- .dvalid_o (rom_rvalid)
+ .rdata_o (rom_rdata),
+ .rvalid_o (rom_rvalid),
+ .cfg_i ('0) // tied off for now
);
// sram device
diff --git a/hw/top_earlgrey/top_earlgrey_verilator.cc b/hw/top_earlgrey/top_earlgrey_verilator.cc
index 5f5ad6a..82576c8 100644
--- a/hw/top_earlgrey/top_earlgrey_verilator.cc
+++ b/hw/top_earlgrey/top_earlgrey_verilator.cc
@@ -17,8 +17,8 @@
memutil.RegisterMemoryArea(
"rom",
- "TOP.top_earlgrey_verilator.top_earlgrey.u_rom_rom.gen_generic."
- "u_impl_generic");
+ "TOP.top_earlgrey_verilator.top_earlgrey.u_rom_rom.u_prim_rom."
+ "gen_generic.u_impl_generic");
memutil.RegisterMemoryArea(
"ram",
"TOP.top_earlgrey_verilator.top_earlgrey.u_ram1p_ram_main.u_mem."
diff --git a/hw/top_earlgrey/util/vivado_hook_opt_design_post.tcl b/hw/top_earlgrey/util/vivado_hook_opt_design_post.tcl
index a4aeab7..2045f1d 100644
--- a/hw/top_earlgrey/util/vivado_hook_opt_design_post.tcl
+++ b/hw/top_earlgrey/util/vivado_hook_opt_design_post.tcl
@@ -8,8 +8,8 @@
send_msg "Designcheck 2-1" INFO "Checking if ROM memory is mapped to BRAM memory."
-if {[catch [get_cells -hierarchical -filter { NAME =~ "*rom_rom*dout_o_reg_0" && PRIMITIVE_TYPE =~ BMEM.*.* }]]\
-&& [catch [get_cells -hierarchical -filter { NAME =~ "*rom_rom*dout_o_reg_1" && PRIMITIVE_TYPE =~ BMEM.*.* }]] } {
+if {[catch [get_cells -hierarchical -filter { NAME =~ "*rom_rom*rdata_o_reg_0" && PRIMITIVE_TYPE =~ BMEM.*.* }]]\
+&& [catch [get_cells -hierarchical -filter { NAME =~ "*rom_rom*rdata_o_reg_1" && PRIMITIVE_TYPE =~ BMEM.*.* }]] } {
send_msg "Designcheck 2-2" INFO "BRAM implementation found for ROM memory."
} else {
send_msg "Designcheck 2-3" ERROR "BRAM implementation not found for ROM memory."
