[reggen] Flake8 lint fix for reggen
As flake8 is chosen for python linter in OT, ran flake8 to check reggen
library. A few python codes in the reggen wasn't checked yet (gen_dv,
gen_fpv).
Signed-off-by: Eunchan Kim <eunchan@opentitan.org>
diff --git a/util/reggen/data.py b/util/reggen/data.py
index 794aa99..f933356 100644
--- a/util/reggen/data.py
+++ b/util/reggen/data.py
@@ -8,7 +8,6 @@
# helper funtion that strips trailing number from name
# TODO: this is a workaround, should solve this in validate.py
def _get_basename(name):
- outname = ""
for (k, c) in enumerate(name[::-1]):
if not str.isdigit(c):
return name[0:len(name) - k]
@@ -158,8 +157,8 @@
# or if this is the last multiregister level in a nested multiregister
if not isinstance(self, MultiReg):
dims = [len(self.get_fields_flat())]
- if isinstance(self, MultiReg) and \
- not isinstance(self.fields[0], MultiReg):
+ if isinstance(self, MultiReg) and\
+ not isinstance(self.fields[0], MultiReg):
if self.ishomog:
dims = [len(self.get_fields_flat())]
else:
diff --git a/util/reggen/gen_cfg_html.py b/util/reggen/gen_cfg_html.py
index 5170dab..13f6a63 100644
--- a/util/reggen/gen_cfg_html.py
+++ b/util/reggen/gen_cfg_html.py
@@ -5,15 +5,13 @@
Generate HTML documentation from validated configuration Hjson tree
"""
-import sys
-
def genout(outfile, msg):
outfile.write(msg)
def name_width(x):
- if not 'width' in x or x['width'] == '1':
+ if 'width' not in x or x['width'] == '1':
return x['name']
return x['name'] + '[' + str(int(x['width'], 0) - 1) + ':0]'
@@ -27,7 +25,8 @@
outfile,
"<a href=\"https://docs.opentitan.org/doc/rm/comportability_specification\">\n"
)
- genout(outfile, "Comportable guideline for peripheral device functionality</a>,\n")
+ genout(outfile,
+ "Comportable guideline for peripheral device functionality</a>,\n")
genout(outfile,
"the module <b><code>" + cfgs['name'] + "</code></b> has \n")
genout(outfile, "the following hardware interfaces defined.</p>\n")
diff --git a/util/reggen/gen_cheader.py b/util/reggen/gen_cheader.py
index 4c5d96d..5a50bf6 100644
--- a/util/reggen/gen_cheader.py
+++ b/util/reggen/gen_cheader.py
@@ -7,7 +7,6 @@
import io
import logging as log
-import re
import sys
import textwrap
import warnings
@@ -47,9 +46,10 @@
Arguments:
name - Name of the #define
args - List of arguments for the define, provide an empty list if there are
- none
+ none
body - Body of the #define
- existing_defines - set of already generated define names. Error if `name` is in `existing_defines`.
+ existing_defines - set of already generated define names.
+ Error if `name` is in `existing_defines`.
indent - Gives string to prepend on any new lines produced by
wrapping (default ' ')
@@ -245,29 +245,31 @@
existing_defines)
-def gen_cdefines_interrupt_field(outstr, interrupt, component, regwidth, existing_defines):
+def gen_cdefines_interrupt_field(outstr, interrupt, component, regwidth,
+ existing_defines):
fieldlsb = interrupt['bitinfo'][2]
iname = interrupt['name']
defname = as_define(component + '_INTR_COMMON_' + iname)
if interrupt['bitinfo'][1] == 1:
# single bit
- genout(outstr,
- gen_define(defname, [], str(fieldlsb), existing_defines))
+ genout(outstr, gen_define(defname, [], str(fieldlsb),
+ existing_defines))
else:
# multiple bits (unless it is the whole register)
if interrupt['bitinfo'][1] != regwidth:
mask = interrupt['bitinfo'][0] >> fieldlsb
genout(
outstr,
- gen_define(defname + '_MASK', [], hex(mask),
- existing_defines))
+ gen_define(defname + '_MASK', [], hex(mask), existing_defines))
genout(
outstr,
gen_define(defname + '_OFFSET', [], str(fieldlsb),
- existing_defines))
+ existing_defines))
-def gen_cdefines_interrupts(outstr, regs, component, regwidth, existing_defines):
+
+def gen_cdefines_interrupts(outstr, regs, component, regwidth,
+ existing_defines):
# no_auto_intr_regs controls whether interrupt registers are automatically
# generated from the interrupt_list. This key could be 'true' or 'false',
# but might also be True or False (the python booleans).
@@ -290,7 +292,8 @@
interrupts = regs.get('interrupt_list', [])
genout(outstr, format_comment(first_line("Common Interrupt Offsets")))
for intr in interrupts:
- gen_cdefines_interrupt_field(outstr, intr, component, regwidth, existing_defines)
+ gen_cdefines_interrupt_field(outstr, intr, component, regwidth,
+ existing_defines)
genout(outstr, '\n')
@@ -313,7 +316,8 @@
gen_cdefines_module_params(outstr, regs, component, regwidth,
existing_defines)
- gen_cdefines_interrupts(outstr, regs, component, regwidth, existing_defines)
+ gen_cdefines_interrupts(outstr, regs, component, regwidth,
+ existing_defines)
for x in registers:
if 'reserved' in x:
@@ -348,7 +352,7 @@
if src_copy != '':
genout(outfile, '// Copyright information found in source file:\n')
genout(outfile, '// ' + src_copy + '\n\n')
- if src_lic != None:
+ if src_lic is not None:
genout(outfile, '// Licensing information found in source file:\n')
for line in src_lic.splitlines():
genout(outfile, '// ' + line + '\n')
diff --git a/util/reggen/gen_html.py b/util/reggen/gen_html.py
index 5c2958c..0563c2f 100644
--- a/util/reggen/gen_html.py
+++ b/util/reggen/gen_html.py
@@ -7,7 +7,6 @@
import logging as log
import re
-import sys
def genout(outfile, msg):
@@ -108,7 +107,8 @@
gen_tbl_row(outfile, fieldmsb, hdrbits, True)
namelen = len(fname)
- if namelen == 0 or fname == ' ': fname = " "
+ if namelen == 0 or fname == ' ':
+ fname = " "
if (namelen > bsize * fieldwidth):
usestyle = (" style=\"font-size:" + str(
(bsize * 100 * fieldwidth) / namelen) + "%\"")
@@ -156,7 +156,7 @@
rname = reg['name']
offset = reg['genoffset']
- #in a multireg with multiple regs give anchor with base register name
+ # in a multireg with multiple regs give anchor with base register name
if 'genbasebits' in reg and rname[-1] == '0':
genout(outfile, "<div id=\"Reg_" + rname[:-1].lower() + "\"></div>\n")
regwen_string = ''
@@ -169,7 +169,7 @@
desc_expand(reg['desc'], rnames) + "</div>" + "<div>Reset default = " +
hex(reg['genresval']) + ", mask " + hex(reg['genresmask']) +
regwen_string + "</div></th></tr>\n")
- if toc != None:
+ if toc is not None:
toc.append((toclvl, comp + "." + rname, "Reg_" + rname.lower()))
genout(outfile, "<tr><td colspan=5>")
gen_html_reg_pic(outfile, reg, width)
@@ -185,7 +185,7 @@
mergebase = -1
for field in reg['fields']:
fcount += 1
- if not 'name' in field:
+ if 'name' not in field:
fname = "field " + str(fcount)
else:
fname = field['name']
@@ -229,7 +229,7 @@
if 'enum' in field:
genout(outfile, " <table>")
for enum in field['enum']:
- if (not 'name' in enum):
+ if 'name' not in enum:
ename = "enum for " + fname + " in " + rname
else:
ename = enum['name']
@@ -301,7 +301,7 @@
outfile, '<tr><td class="regde">' + desc_expand(win['desc'], rnames) +
'</td></tr>')
genout(outfile, "</table>\n<br><br>\n")
- if toc != None:
+ if toc is not None:
toc.append((toclvl, comp + "." + wname, "Reg_" + wname.lower()))
diff --git a/util/reggen/gen_rtl.py b/util/reggen/gen_rtl.py
index 59ae60b..c4a5991 100644
--- a/util/reggen/gen_rtl.py
+++ b/util/reggen/gen_rtl.py
@@ -5,15 +5,13 @@
"""
import logging as log
-import operator
-import sys
from mako.template import Template
from mako import exceptions
from pkg_resources import resource_filename
-from .data import *
-from .field_enums import HwAccess, SwAccess, SwRdAccess, SwWrAccess
+from .data import Field, Reg, MultiReg, Window, Block
+from .field_enums import HwAccess, SwRdAccess, SwWrAccess
def escape_name(name):
@@ -40,7 +38,6 @@
f.lsb = obj["bitinfo"][2]
f.msb = f.lsb + obj["bitinfo"][1] - 1
- #assert not 'swaccess' in obj, "R[%s] F[%s]: SwAccess in Field not supported" % (reg.name, f.name)
f.swaccess = obj["genswaccess"]
f.swrdaccess = obj["genswrdaccess"]
f.swwraccess = obj["genswwraccess"]
@@ -96,7 +93,7 @@
# Parsing Fields
for f in obj["fields"]:
field = parse_field(f, reg, len(obj["fields"]))
- if field != None:
+ if field is not None:
reg.fields.append(field)
reg.width = max(reg.width, field.msb + 1)
@@ -159,7 +156,7 @@
continue
elif 'window' in r:
win = parse_win(r['window'], block.width)
- if win != None:
+ if win is not None:
block.wins.append(win)
continue
@@ -195,7 +192,7 @@
HwAccess=HwAccess,
SwRdAccess=SwRdAccess,
SwWrAccess=SwWrAccess))
- except:
+ except: # noqa: F722 for template Exception handling
log.error(exceptions.text_error_template().render())
# Generate top.sv
@@ -207,5 +204,5 @@
HwAccess=HwAccess,
SwRdAccess=SwRdAccess,
SwWrAccess=SwWrAccess))
- except:
+ except: # noqa: F722 for template Exception handling
log.error(exceptions.text_error_template().render())
diff --git a/util/reggen/gen_selfdoc.py b/util/reggen/gen_selfdoc.py
index 7d80402..2c3cc29 100644
--- a/util/reggen/gen_selfdoc.py
+++ b/util/reggen/gen_selfdoc.py
@@ -5,8 +5,6 @@
Generates the documentation for the register tool
"""
-import sys
-
from reggen import validate
@@ -199,7 +197,7 @@
def doc_tbl_head(outfile, use):
- if (use != None):
+ if use is not None:
genout(outfile, "\nKey | Kind | Type | Description of Value\n")
genout(outfile, "--- | ---- | ---- | --------------------\n")
else:
@@ -208,7 +206,7 @@
def doc_tbl_line(outfile, key, use, desc):
- if use != None:
+ if use is not None:
genout(
outfile, key + " | " + validate.key_use[use] + " | " +
validate.val_types[desc[0]][0] + " | " + desc[1] + "\n")
@@ -233,9 +231,9 @@
for x in validate.hwaccess_permitted:
doc_tbl_line(outfile, x, None, validate.hwaccess_permitted[x][0])
- genout(outfile,
- "\n\nThe top level of the JSON is a group containing "\
- "the following keys:\n")
+ genout(
+ outfile, "\n\nThe top level of the JSON is a group containing "
+ "the following keys:\n")
doc_tbl_head(outfile, 1)
for x in validate.top_required:
doc_tbl_line(outfile, x, 'r', validate.top_required[x])
@@ -256,9 +254,9 @@
doc_tbl_line(outfile, x, 'a', validate.reg_added[x])
genout(outfile, register_example)
- genout(outfile,
- "\n\nIn the fields list each field definition is a group "\
- "containing:\n")
+ genout(
+ outfile, "\n\nIn the fields list each field definition is a group "
+ "containing:\n")
doc_tbl_head(outfile, 1)
for x in validate.field_required:
doc_tbl_line(outfile, x, 'r', validate.field_required[x])
@@ -278,8 +276,8 @@
doc_tbl_line(outfile, x, 'a', validate.enum_added[x])
genout(
- outfile, "\n\nThe list of registers may include single entry groups "\
- "to control the offset, open a window or generate registers:\n")
+ outfile, "\n\nThe list of registers may include single entry groups "
+ "to control the offset, open a window or generate registers:\n")
doc_tbl_head(outfile, 1)
for x in validate.list_optone:
doc_tbl_line(outfile, x, 'o', validate.list_optone[x])
diff --git a/util/reggen/validate.py b/util/reggen/validate.py
index 4090715..ee01f93 100644
--- a/util/reggen/validate.py
+++ b/util/reggen/validate.py
@@ -6,9 +6,8 @@
"""
import logging as log
-import sys
-from reggen.field_enums import *
+from reggen.field_enums import SwWrAccess, SwRdAccess, SwAccess, HwAccess
# Routine that can be used for Hjson object_pairs_hook
@@ -30,7 +29,7 @@
def check_count(top, mreg, err_prefix):
'''Checking mreg count if it is in param list
'''
- if not "param_list" in top:
+ if "param_list" not in top:
top["param_list"] = []
name_list = []
else:
@@ -81,7 +80,7 @@
": int must start digit, 0b, 0B, 0o, 0O, 0x or 0X")
return 0, True
for c in x[2:]:
- if not c in validch:
+ if c not in validch:
if not suppress_err_msg:
log.error(err_prefix + ": Bad character " + c + " in " + x)
return 0, True
@@ -140,7 +139,7 @@
error += check_keys(y, lp_required, lp_optional, {},
err_prefix + ' element ' + x)
# TODO: Check if PascalCase or ALL_CAPS
- if not "type" in y:
+ if "type" not in y:
y["type"] = "int"
if "local" in y:
@@ -185,7 +184,7 @@
def check_keys(obj, required_keys, optional_keys, added_keys, err_prefix):
error = 0
for x in required_keys:
- if not x in obj:
+ if x not in obj:
error += 1
log.error(err_prefix + " missing required key " + x)
for x in obj:
@@ -194,7 +193,7 @@
type = required_keys[x][0]
elif x in optional_keys:
type = optional_keys[x][0]
- elif not x in added_keys:
+ elif x not in added_keys:
log.warning(err_prefix + " contains extra key " + x)
if type[:2] == 'ln':
error += check_ln(obj, x, type == 'lnw', err_prefix)
@@ -245,8 +244,7 @@
msb = brange[0]
lsb = brange[2]
res = 0
- if ((not msb.isdecimal()) or (not lsb.isdecimal()) or
- (int(lsb) > int(msb))):
+ if not (msb.isdecimal() and lsb.isdecimal()) or int(lsb) > int(msb):
log.error("Bad bit range " + bfield + str(brange))
return (0, 0, 0)
else:
@@ -264,21 +262,27 @@
'd': ["int", "integer (binary 0b, octal 0o, decimal, hex 0x)"],
'x': ["xint", "x for undefined otherwise int"],
'b': [
- "bitrange", "bit number as decimal integer, \
- or bit-range as decimal integers msb:lsb"
+ "bitrange", "bit number as decimal integer, "
+ "or bit-range as decimal integers msb:lsb"
],
'l': ["list", "comma separated list enclosed in `[]`"],
- 'ln': ["name list", 'comma separated list enclosed in `[]` of '\
- 'one or more groups that have just name and dscr keys.'\
- ' e.g. `{ name: "name", desc: "description"}`'],
+ 'ln': [
+ "name list", 'comma separated list enclosed in `[]` of '
+ 'one or more groups that have just name and dscr keys.'
+ ' e.g. `{ name: "name", desc: "description"}`'
+ ],
'lnw': ["name list+", 'name list that optionally contains a width'],
'lp': ["parameter list", 'parameter list having default value optionally'],
'g': ["group", "comma separated group of key:value enclosed in `{}`"],
- 'lg': ["list of group", "comma separated group of key:value enclosed in `{}`"\
- " the second entry of the list is the sub group format"],
+ 'lg': [
+ "list of group", "comma separated group of key:value enclosed in `{}`"
+ " the second entry of the list is the sub group format"
+ ],
's': ["string", "string, typically short"],
- 't': ["text", "string, may be multi-line enclosed in `'''` "\
- "may use `**bold**`, `*italic*` or `!!Reg` markup"],
+ 't': [
+ "text", "string, may be multi-line enclosed in `'''` "
+ "may use `**bold**`, `*italic*` or `!!Reg` markup"
+ ],
'T': ["tuple", "tuple enclosed in ()"],
'pi': ["python int", "Native Python type int (generated)"],
'pb': ["python Bool", "Native Python type Bool (generated)"],
@@ -291,10 +295,9 @@
'name': ['s', "name of the component"],
'clock_primary': ['s', "name of the primary clock"],
'bus_device': ['s', "name of the bus interface for the device"],
- 'registers': [
- 'l', "list of register definition groups and \
- offset control groups"
- ]
+ 'registers':
+ ['l', "list of register definition groups and "
+ "offset control groups"]
}
top_optional = {
'bus_host': ['s', "name of the bus interface as host"],
@@ -303,25 +306,32 @@
'available_output_list': ['lnw', "list of available peripheral outputs"],
'available_inout_list': ['lnw', "list of available peripheral inouts"],
'interrupt_list': ['lnw', "list of peripheral interrupts"],
- 'no_auto_intr_regs': ['s', "Set to true to suppress automatic "\
- "generation of interrupt registers. " \
- "Defaults to false if not present."],
+ 'no_auto_intr_regs': [
+ 's', "Set to true to suppress automatic "
+ "generation of interrupt registers. "
+ "Defaults to false if not present."
+ ],
'alert_list': ['lnw', "list of peripheral alerts"],
'regwidth': ['d', "width of registers in bits (default 32)"],
'param_list': ['lp', "list of parameters of the IP"],
'scan': ['pb', 'Indicates the module have `scanmode_i`'],
- 'SPDX-License-Identifier': ['s', "License ientifier (if using pure json) "\
- "Only use this if unable to put this "\
- "information in a comment at the top of the "\
- "file."]
+ 'SPDX-License-Identifier': [
+ 's', "License ientifier (if using pure json) "
+ "Only use this if unable to put this "
+ "information in a comment at the top of the "
+ "file."
+ ]
}
-top_added = {'genrnames': ['pl', "list of register names"],
- 'genautoregs': ['pb', "Registers were generated from config info"],
- 'genwennames': ['pl', "list of registers used as write enables"],
- 'gennextoffset': ['pi', "offset next register would use"],
- 'gensize': ['pi', "address space size needed for registers. "\
- "Generated by tool as next power of 2."]
- }
+top_added = {
+ 'genrnames': ['pl', "list of register names"],
+ 'genautoregs': ['pb', "Registers were generated from config info"],
+ 'genwennames': ['pl', "list of registers used as write enables"],
+ 'gennextoffset': ['pi', "offset next register would use"],
+ 'gensize': [
+ 'pi', "address space size needed for registers. "
+ "Generated by tool as next power of 2."
+ ]
+}
# ln type has list of groups with only name and description
# (was called "subunit" in cfg_validate)
@@ -345,15 +355,20 @@
}
# Registers list may have embedded keys
-list_optone = {'reserved': ['d', "number of registers to reserve space for"],
- 'skipto': ['d', "set next register offset to value"],
- 'sameaddr': ['l', "list of register definition groups "\
- "that share the same offset"],
- 'window': ['g', "group defining an address range "\
- "for something other than standard registers"],
- 'multireg': ['g', "group defining registers generated "\
- "from a base instance."]
- }
+list_optone = {
+ 'reserved': ['d', "number of registers to reserve space for"],
+ 'skipto': ['d', "set next register offset to value"],
+ 'sameaddr':
+ ['l', "list of register definition groups "
+ "that share the same offset"],
+ 'window': [
+ 'g', "group defining an address range "
+ "for something other than standard registers"
+ ],
+ 'multireg':
+ ['g', "group defining registers generated "
+ "from a base instance."]
+}
# Register keys
reg_required = {
@@ -413,56 +428,74 @@
# TODO potential for additional optional to give more type info?
# eg sram-hw-port: "none", "sync", "async"
-window_optional = {'byte-write': ['s', "True if byte writes are supported. "\
- "Defaults to false if not present."],
- 'validbits': ['d', "Number of valid data bits within "\
- "regwidth sized word. "\
- "Defaults to regwidth. If "\
- "smaller than the regwidth then in each "\
- "word of the window bits "\
- "[regwidth-1:validbits] are unused and "\
- "bits [validbits-1:0] are valid."],
- 'noalign': ['s', "Set to True to prevent tool aligning "\
- "the base address of the window. "\
- "Defaults to false if not present."],
- 'unusual': ['s', "True if window has unusual parameters "\
- "(set to prevent Unusual: errors)."\
- "Defaults to false if not present."]
- }
+window_optional = {
+ 'byte-write': [
+ 's', "True if byte writes are supported. "
+ "Defaults to false if not present."
+ ],
+ 'validbits': [
+ 'd', "Number of valid data bits within "
+ "regwidth sized word. "
+ "Defaults to regwidth. If "
+ "smaller than the regwidth then in each "
+ "word of the window bits "
+ "[regwidth-1:validbits] are unused and "
+ "bits [validbits-1:0] are valid."
+ ],
+ 'noalign': [
+ 's', "Set to True to prevent tool aligning "
+ "the base address of the window. "
+ "Defaults to false if not present."
+ ],
+ 'unusual': [
+ 's', "True if window has unusual parameters "
+ "(set to prevent Unusual: errors)."
+ "Defaults to false if not present."
+ ]
+}
-window_added = {'genbyte-write': ['pb', "generated boolean for byte-write "],
- 'genvalidbits': ['pi', "vailid data width"],
- 'genoffset': ['pi', "base offset address of the window "\
- "(aligned for size)"],
- 'genswaccess': ['pe', "Software access (gen enum)"],
- 'genswwraccess': ['pe', "Software write access (gen enum)"],
- 'genswrdaccess': ['pe', "Software read access (gen enum)"]
- }
+window_added = {
+ 'genbyte-write': ['pb', "generated boolean for byte-write"],
+ 'genvalidbits': ['pi', "valid data width"],
+ 'genoffset':
+ ['pi', "base offset address of the window (aligned for size)"],
+ 'genswaccess': ['pe', "Software access (gen enum)"],
+ 'genswwraccess': ['pe', "Software write access (gen enum)"],
+ 'genswrdaccess': ['pe', "Software read access (gen enum)"]
+}
# Multireg keys
-multireg_required = {'name': ['s', "base name of the registers"],
- 'desc': ['t', "description of the registers"],
- 'count': ['s', "number of instances to generate."\
- " This field can be integer or string matching"\
- " from param_list"],
- 'cname': ['s', "base name for each instance, mostly "\
- "useful for refering to instance in messages"],
- 'fields': ['l', "list of register field description"\
- "groups. Describes bit positions used for"\
- " base instance."]
- }
+multireg_required = {
+ 'name': ['s', "base name of the registers"],
+ 'desc': ['t', "description of the registers"],
+ 'count': [
+ 's', "number of instances to generate."
+ " This field can be integer or string matching"
+ " from param_list."
+ ],
+ 'cname': [
+ 's', "base name for each instance, mostly"
+ " useful for refering to instance in messages."
+ ],
+ 'fields': [
+ 'l', "list of register field description"
+ " groups. Describes bit positions used for"
+ " base instance."
+ ]
+}
multireg_optional = reg_optional
multireg_optional.update({
'regwen_incr': [
- 's', "If true, regwen term increments along with current multireg " +
- "count "
+ 's', "If true, regwen term increments"
+ " along with current multireg count."
],
})
-multireg_added = {'genregs': ['l',
- "generated list of registers with required "\
- "and added keys"]
- }
+multireg_added = {
+ 'genregs':
+ ['l', "generated list of registers with required"
+ " and added keys"]
+}
# Field keys
# special case in the code, no name and no desc if only field
@@ -522,24 +555,26 @@
# swaccess permitted values
# text description, access enum, wr access enum, rd access enum, ok in window
+# flake8 doens't support noqa for a block.
+# So should choose between visually hard-to-redable and noqa comment every lines.
swaccess_permitted = {
- 'ro': ("Read Only",
- SwAccess.RO, SwWrAccess.NONE, SwRdAccess.RD, True),
- 'rc': ("Read Only, reading clears",
- SwAccess.RC, SwWrAccess.WR, SwRdAccess.RC, False),
- 'rw': ("Read/Write",
- SwAccess.RW, SwWrAccess.WR, SwRdAccess.RD, True),
- 'r0w1c': ("Read zero, Write with 1 clears",
- SwAccess.W1C, SwWrAccess.WR, SwRdAccess.NONE, False),
- 'rw1s': ("Read, Write with 1 sets",
- SwAccess.W1S, SwWrAccess.WR, SwRdAccess.RD, False),
- 'rw1c': ("Read, Write with 1 clears",
- SwAccess.W1C, SwWrAccess.WR, SwRdAccess.RD, False),
- 'rw0c': ("Read, Write with 0 clears",
- SwAccess.W0C, SwWrAccess.WR, SwRdAccess.RD, False),
- 'wo': ("Write Only",
- SwAccess.WO, SwWrAccess.WR, SwRdAccess.NONE, True)
-} # yapf: disable
+ 'ro': ("Read Only", # noqa: E241
+ SwAccess.RO, SwWrAccess.NONE, SwRdAccess.RD, True), # noqa: E241
+ 'rc': ("Read Only, reading clears", # noqa: E241
+ SwAccess.RC, SwWrAccess.WR, SwRdAccess.RC, False), # noqa: E241
+ 'rw': ("Read/Write", # noqa: E241
+ SwAccess.RW, SwWrAccess.WR, SwRdAccess.RD, True), # noqa: E241
+ 'r0w1c': ("Read zero, Write with 1 clears", # noqa: E241
+ SwAccess.W1C, SwWrAccess.WR, SwRdAccess.NONE, False), # noqa: E241
+ 'rw1s': ("Read, Write with 1 sets", # noqa: E241
+ SwAccess.W1S, SwWrAccess.WR, SwRdAccess.RD, False), # noqa: E241
+ 'rw1c': ("Read, Write with 1 clears", # noqa: E241
+ SwAccess.W1C, SwWrAccess.WR, SwRdAccess.RD, False), # noqa: E241
+ 'rw0c': ("Read, Write with 0 clears", # noqa: E241
+ SwAccess.W0C, SwWrAccess.WR, SwRdAccess.RD, False), # noqa: E241
+ 'wo': ("Write Only", # noqa: E241
+ SwAccess.WO, SwWrAccess.WR, SwRdAccess.NONE, True) # noqa: E241
+} # yapf: disable
# hwaccess permitted values
hwaccess_permitted = {
@@ -638,12 +673,12 @@
for field in fields:
fcount += 1
- if not 'name' in field:
+ if 'name' not in field:
fname = rname + ".field" + str(fcount)
if (len(fields) == 1):
field['name'] = rname
# only allow no desc if no name
- if not 'desc' in field:
+ if 'desc' not in field:
field['desc'] = ""
else:
fname = field['name']
@@ -666,11 +701,11 @@
error += ck_err
continue
- if not 'tags' in field:
+ if 'tags' not in field:
field['tags'] = []
- if not 'swaccess' in field:
- if (default_sw == None):
+ if 'swaccess' not in field:
+ if default_sw is None:
error += 1
log.error(fname + ":no swaccess or register default swaccess")
swaccess = "wo"
@@ -680,7 +715,7 @@
swaccess = default_sw
else:
swaccess = field['swaccess']
- if (not swaccess in swaccess_permitted):
+ if swaccess not in swaccess_permitted:
error += 1
log.error(fname + ": Bad field swaccess value " + swaccess)
swaccess = "wo"
@@ -689,8 +724,8 @@
field['genswwraccess'] = swacc_info[2]
field['genswrdaccess'] = swacc_info[3]
- if not 'hwaccess' in field:
- if (default_hw == None):
+ if 'hwaccess' not in field:
+ if default_hw is None:
error += 1
log.error(fname + ": no hwaccess or register default hwaccess")
hwaccess = "hro"
@@ -700,7 +735,7 @@
hwaccess = default_hw
else:
hwaccess = field['hwaccess']
- if (not hwaccess in hwaccess_permitted):
+ if hwaccess not in hwaccess_permitted:
error += 1
log.error(fname + ": Bad field hwaccess value " + hwaccess)
hwaccess = "hro"
@@ -753,7 +788,7 @@
hex(max_in_field) + ")")
resval &= max_in_field
- if ((full_resval != None) and
+ if (full_resval is not None and
(resval !=
((full_resval >> field_bits[2]) & max_in_field))):
error += 1
@@ -768,7 +803,7 @@
field['genresval'] = 0
field['genresvalx'] = True
else:
- if (full_resval != None):
+ if full_resval is not None:
resval = (full_resval >> field_bits[2]) & max_in_field
gen_resval |= resval << field_bits[2]
gen_resmask |= field_bits[0]
@@ -821,21 +856,20 @@
def parse_dvrights(field=None):
- if field == None:
+ if field is None:
return "RO"
- elif field in ['ro', 'rc']:
+ if field in ['ro', 'rc']:
return "RO"
- elif field in ['rw', 'r0w1c', 'rw1s', 'rw1c', 'rw0c']:
+ if field in ['rw', 'r0w1c', 'rw1s', 'rw1c', 'rw0c']:
return "RW"
- else:
- return "WO"
+ return "WO"
def validate_reg_defaults(reg, rname):
error = 0
if 'swaccess' in reg:
default_sw = reg['swaccess']
- if (not default_sw in swaccess_permitted):
+ if default_sw not in swaccess_permitted:
error += 1
log.error(rname + ": Bad register swaccess value " + default_sw)
default_sw = None
@@ -844,7 +878,7 @@
if 'hwaccess' in reg:
default_hw = reg['hwaccess']
- if (not default_hw in hwaccess_permitted):
+ if default_hw not in hwaccess_permitted:
error += 1
log.error(rname + ": Bad register hwaccess value " + default_hw)
default_hw = None
@@ -857,7 +891,7 @@
if ierr:
error += 1
reg['hwext'] = "false"
- elif hwext == True and default_hw == "hro" and (default_sw != "wo" and
+ elif hwext is True and default_hw == "hro" and (default_sw != "wo" and
default_sw != "r0w1c"):
log.warning(
rname +
@@ -873,13 +907,13 @@
if ierr:
error += 1
reg['hwqe'] = "false"
- elif hwqe == False and reg[
+ elif hwqe is False and reg[
'hwext'] == "true" and reg['swaccess'] != "ro":
log.warning(rname + ": hwqe must be true for hwext register. " +
"Changing it to true.")
reg['hwqe'] = "true"
elif reg['hwext'] == "true" and reg['swaccess'] != "ro":
- log.warning(rname + ": hwqe not provided but must be true for "\
+ log.warning(rname + ": hwqe not provided but must be true for "
"hwext not read-only register. Setting it to true.")
reg['hwqe'] = "true"
else:
@@ -891,7 +925,7 @@
if ierr:
error += 1
reg['hwre'] = "false"
- elif hwre == True and reg['hwext'] == "false":
+ elif hwre is True and reg['hwext'] == "false":
log.warning(rname + ": hwre cannot be used with hwext. " +
"Changing it to false.")
reg['hwre'] = "false"
@@ -918,7 +952,7 @@
def validate_register(reg, offset, width, top):
error = 0
- if not 'name' in reg:
+ if 'name' not in reg:
rname = "Register at +" + hex(offset)
else:
rname = reg['name']
@@ -971,7 +1005,7 @@
error = 0
bits_used = 0
- if not 'name' in mreg:
+ if 'name' not in mreg:
mrname = "MultiRegister at +" + hex(offset)
mreg["name"] = "MREG_" + hex(offset)
else:
@@ -1180,7 +1214,7 @@
newf['genhwre'] = False
newf['genresval'] = 0
newf['genresvalx'] = False
- if not 'tags' in bit:
+ if 'tags' not in bit:
newf['tags'] = []
else:
newf['tags'] = bit['tags']
@@ -1223,7 +1257,7 @@
def validate_window(win, offset, regwidth, top):
error = 0
- if not 'name' in win:
+ if 'name' not in win:
name = "Window at +" + hex(offset)
else:
name = win['name']
@@ -1298,7 +1332,7 @@
win['genoffset'] = genoff
swaccess = win['swaccess']
- if (not swaccess in swaccess_permitted):
+ if swaccess not in swaccess_permitted:
log.warn(name + ": Bad window swaccess value " + swaccess)
swaccess = "wo"
swacc_info = swaccess_permitted[swaccess]
@@ -1376,9 +1410,8 @@
if (sw_regwen + hw_regwen) == 0:
error += 1
log.error(
- x +
- " used as regwen fails requirement to be swaccess=W1C/W0C or swaccess=RO and hwaccess=HWO"
- )
+ "{x} used as regwen fails requirement to be "
+ "swaccess=W1C/W0C or swaccess=RO and hwaccess=HWO".format(x=x))
return error
@@ -1389,12 +1422,13 @@
else:
params = []
- if not 'name' in regs:
+ if 'name' not in regs:
log.error("Component has no name. Aborting.")
return 1
+
component = regs['name']
- if not 'param_list' in regs:
+ if 'param_list' not in regs:
regs['param_list'] = []
error = check_keys(regs, top_required, top_optional, top_added, component)
@@ -1433,7 +1467,7 @@
error += 1
else:
no_autoi = False
- if 'interrupt_list' in regs and not 'genautoregs' in regs and not no_autoi:
+ if 'interrupt_list' in regs and 'genautoregs' not in regs and not no_autoi:
iregs, err = make_intr_regs(regs, offset, addrsep, fullwidth)
error += err
autoregs.extend(iregs)
@@ -1525,7 +1559,8 @@
offset += addrsep
regs['gennextoffset'] = offset
# make the right thing happen if now exactly on power of 2
- if (offset > 0): offset -= 1
+ if offset > 0:
+ offset -= 1
regs['gensize'] = 1 << offset.bit_length()
error += check_wen_regs(regs)
diff --git a/util/regtool.py b/util/regtool.py
index cf7e03d..2c0072d 100755
--- a/util/regtool.py
+++ b/util/regtool.py
@@ -7,13 +7,11 @@
"""
import argparse
import logging as log
-import os
import re
import sys
from pathlib import PurePath
import hjson
-import pkg_resources
from reggen import (gen_cheader, gen_ctheader, gen_dv, gen_html, gen_json,
gen_rtl, gen_fpv, gen_selfdoc, validate, version)
@@ -70,9 +68,10 @@
parser.add_argument('-f',
action='store_true',
help='Output as FPV CSR rw assertion module')
- parser.add_argument('--outdir', '-t',
- help='Target directory for generated RTL, '\
- 'tool uses ../rtl if blank.')
+ parser.add_argument('--outdir',
+ '-t',
+ help='Target directory for generated RTL; '
+ 'tool uses ../rtl if blank.')
parser.add_argument('--outfile',
'-o',
type=argparse.FileType('w'),
@@ -107,15 +106,24 @@
verbose = args.verbose
- if args.j: format = 'json'
- elif args.c: format = 'compact'
- elif args.d: format = 'html'
- elif args.doc: format = 'doc'
- elif args.r: format = 'rtl'
- elif args.s: format = 'dv'
- elif args.f: format = 'fpv'
- elif args.cdefines: format = 'cdh'
- elif args.ctdefines: format = 'cth'
+ if args.j:
+ format = 'json'
+ elif args.c:
+ format = 'compact'
+ elif args.d:
+ format = 'html'
+ elif args.doc:
+ format = 'doc'
+ elif args.r:
+ format = 'rtl'
+ elif args.s:
+ format = 'dv'
+ elif args.f:
+ format = 'fpv'
+ elif args.cdefines:
+ format = 'cdh'
+ elif args.ctdefines:
+ format = 'cth'
if (verbose):
log.basicConfig(format="%(levelname)s: %(message)s", level=log.DEBUG)
@@ -197,13 +205,13 @@
lunder = re.compile(r'.*(Licensed under.+)', re.IGNORECASE)
for line in srcfull.splitlines():
mat = copy.match(line)
- if mat != None:
+ if mat is not None:
src_copy += mat.group(1)
mat = spdx.match(line)
- if mat != None:
+ if mat is not None:
found_spdx = mat.group(1)
mat = lunder.match(line)
- if mat != None:
+ if mat is not None:
found_lunder = mat.group(1)
if found_lunder:
src_lic = found_lunder
