| commit | 0a345f9331a47c2179b353259e288d12eab13cc1 | [log] [tgz] |
|---|---|---|
| author | Weicai Yang <weicai@google.com> | Mon Nov 01 11:44:58 2021 -0700 |
| committer | weicaiyang <49293026+weicaiyang@users.noreply.github.com> | Tue Nov 02 13:48:33 2021 -0700 |
| tree | f8ae2736d41fc5939419f04c3d4f925dcca768ea | |
| parent | 12f1bcfa85eaf4b17e77699ec2eba489d6f04326 [diff] |
[dv] Update TL intg testplan Merged tl_intg_err_mem_subword_cg into tl_intg_err_cg as memory doesn't exist in all IPs. This cg is only enabled when the IP contains memory. No need to have a separate entry for it. Signed-off-by: Weicai Yang <weicai@google.com>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
This repository contains hardware, software and utilities written as part of the OpenTitan project. It is structured as monolithic repository, or “monorepo”, where all components live in one repository. It exists to enable collaboration across partners participating in the OpenTitan project.
The project contains comprehensive documentation of all IPs and tools. You can access it online at docs.opentitan.org.
Have a look at CONTRIBUTING and our documentation on project organization and processes for guidelines on how to contribute code to this repository.
Unless otherwise noted, everything in this repository is covered by the Apache License, Version 2.0 (see LICENSE for full text).