| commit | 0909c4fca50b853e86f9a4a47fc7a227169a75a3 | [log] [tgz] |
|---|---|---|
| author | Philipp Wagner <phw@lowrisc.org> | Tue Jun 01 16:47:28 2021 +0100 |
| committer | Philipp Wagner <mail@philipp-wagner.com> | Mon Jun 07 15:52:49 2021 +0100 |
| tree | dcb8379ab608f484b74d6af0ee9327bb25199f11 | |
| parent | 78e0a4bd4ec19a154b33277bff9ae961de76bc33 [diff] |
[prim_clock_gating] Target 7series Xilinx devices Vivado warns about the BUFGCE module being instantiated with the wrong device type. Actually, we don't specify any device and it seems that SIM_DEVICE is just set to ULTRASCALE by default instead of to the actual device family we're using. This warning per se isn't troublesome, but we still want to get rid of it, as it hides more important warnings. This PR specifies 7 series devices, which we're using. We could also suppress the warning, but then we potentially have Xilinx simulation mismatches (not that anybody ever does netlist simulations for FPGA builds, AFAIK). Vivado message: ``` [Netlist 29-345] The value of SIM_DEVICE on instance 'top_earlgrey/u_clkmgr_aon/u_io_cg/i_cg/gen_xilinx.u_impl_xilinx/gen_gate.u_bufgce' of type 'BUFGCE' is 'ULTRASCALE'; it is being changed to match the current FPGA architecture, '7SERIES'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. ``` Signed-off-by: Philipp Wagner <phw@lowrisc.org>
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