| commit | 08a3506fdc43d3b0ecaa2ead6f6dd7f0f420ed00 | [log] [tgz] |
|---|---|---|
| author | Udi Jonnalagadda <udij@google.com> | Thu Jun 11 11:54:29 2020 -0700 |
| committer | udinator <udij@google.com> | Thu Jun 11 12:29:47 2020 -0700 |
| tree | 39fd7451149c24aceea840f829123bedf3458e4f | |
| parent | 6c6125159cde09add2c1307aaa7866d1a125c3ce [diff] |
Update lowrisc_ibex to lowRISC/ibex@5ecaa11 Update code from upstream repository https://github.com/lowRISC/ibex.git to revision 5ecaa11c635b259d644532c081a2c6818740f43c * [rtl] Fix writeback stage interrupt issue (Tom Roberts) * [rtl] Remove incorrect LSU assertion (Tom Roberts) * [doc] Clarify fetch_enable_i meaning (Tom Roberts) * [ibex/dv] Add several PMP tests (Udi) * Collect transaction functional coverage for ICache-Mem iface (Rupert Swarbrick) * Collect transaction functional coverage for ICache-Core iface (Rupert Swarbrick) * Wire in the branch_spec signal properly in ICache testbench (Rupert Swarbrick) * Add a "many_errors" icache test sequence (Rupert Swarbrick) * Add backward_line icache test sequence (Rupert Swarbrick) * Add missing dependency on python3-bitstring to python-requirements (Rupert Swarbrick) * [syn] Update path to prim_assert (Tom Roberts) * [rtl] Move some assertions around (Tom Roberts) * [rtl] Rewrite perf counters to be Yosys compatible (Tom Roberts) * Spelling fix: seperate -> separate (Rupert Swarbrick) * Add test to check that disabling doesn't invalidate the icache (Rupert Swarbrick) * Add the "invalidation" icache test sequence (Rupert Swarbrick) * Fix Writeback stage lint errors (Eunchan Kim) * Update lowrisc_ip to lowRISC/opentitan@d78da129 (Rupert Swarbrick) * Handle a seed change that clears a PMP error in icache memory driver (Rupert Swarbrick) * Spot repeated requests with same address in ICache memory monitor (Rupert Swarbrick) * Make sure we don't see multi-way hits in icache testbench (Rupert Swarbrick) * Reorder check in icache scoreboard for more helpful error messages (Rupert Swarbrick) * [sw] Fix typo in simple system exception handler (Greg Chadwick) * [rtl] Fix issue with ID/EX exceptions (Greg Chadwick) * [rtl] Fix exception priority for writeback stage (Greg Chadwick) * [rtl] Make speculative branch optional (Tom Roberts) * [rtl] Fix PMP NA4 address matching (Tom Roberts) * Add a "caching" sequence for ICache testing (Rupert Swarbrick) * Track how well the icache caches tight loops in the scoreboard (Rupert Swarbrick) * Change how enable/disable is configured in ICache core sequence (Rupert Swarbrick) * Move "enable" state into ICache core agent's sequence (Rupert Swarbrick) * Update google_riscv-dv to google/riscv-dv@1ad73cc (Udi) * [rtl] prefetch buffer performance fix (Tom Roberts) * Add missing Python dependency on premailer library (Rupert Swarbrick) * Add support for running Icache test with Riviera-PRO (Dawid Zimonczyk) * Update lowrisc_ip to lowRISC/opentitan@3f35d4e4 (Philipp Wagner) Signed-off-by: Udi Jonnalagadda <udij@google.com>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
This repository contains hardware, software and utilities written as part of the OpenTitan project. It is structured as monolithic repository, or “monorepo”, where all components live in one repository. It exists to enable collaboration across partners participating in the OpenTitan project.
The project contains comprehensive documentation of all IPs and tools. You can access it online at docs.opentitan.org.
Have a look at CONTRIBUTING for guidelines on how to contribute code to this repository.
Unless otherwise noted, everything in this repository is covered by the Apache License, Version 2.0 (see LICENSE for full text).