[doc] Update documentation in order to include OTP preload image
Signed-off-by: Michael Schaffner <msf@opentitan.org>
diff --git a/doc/ug/getting_started_fpga.md b/doc/ug/getting_started_fpga.md
index 18eade4..0d7539f 100644
--- a/doc/ug/getting_started_fpga.md
+++ b/doc/ug/getting_started_fpga.md
@@ -33,7 +33,7 @@
```console
$ cd $REPO_TOP
$ ./meson_init.sh
-$ ninja -C build-out sw/device/boot_rom/boot_rom_export_fpga_nexysvideo
+$ ninja -C build-out all
```
Since not all FPGAs are able to fit the full design, there is a separate script that can be invoked to reduce the size of the design.
@@ -54,7 +54,7 @@
$ cd $REPO_TOP
$ ./meson_init.sh
$ ./hw/top_earlgrey/util/top_earlgrey_reduce.py
-$ ninja -C build-out sw/device/boot_rom/boot_rom_export_fpga_nexysvideo
+$ ninja -C build-out all
$ fusesoc --cores-root . run --flag=fileset_top --target=synth lowrisc:systems:top_earlgrey_nexysvideo
```
The `fileset_top` flag used above is specific to the OpenTitan project to select the correct fileset.
