[doc] Update documentation in order to include OTP preload image
Signed-off-by: Michael Schaffner <msf@opentitan.org>
diff --git a/doc/ug/getting_started_fpga.md b/doc/ug/getting_started_fpga.md
index 18eade4..0d7539f 100644
--- a/doc/ug/getting_started_fpga.md
+++ b/doc/ug/getting_started_fpga.md
@@ -33,7 +33,7 @@
```console
$ cd $REPO_TOP
$ ./meson_init.sh
-$ ninja -C build-out sw/device/boot_rom/boot_rom_export_fpga_nexysvideo
+$ ninja -C build-out all
```
Since not all FPGAs are able to fit the full design, there is a separate script that can be invoked to reduce the size of the design.
@@ -54,7 +54,7 @@
$ cd $REPO_TOP
$ ./meson_init.sh
$ ./hw/top_earlgrey/util/top_earlgrey_reduce.py
-$ ninja -C build-out sw/device/boot_rom/boot_rom_export_fpga_nexysvideo
+$ ninja -C build-out all
$ fusesoc --cores-root . run --flag=fileset_top --target=synth lowrisc:systems:top_earlgrey_nexysvideo
```
The `fileset_top` flag used above is specific to the OpenTitan project to select the correct fileset.
diff --git a/doc/ug/getting_started_verilator.md b/doc/ug/getting_started_verilator.md
index f1a875e..30e8de9 100644
--- a/doc/ug/getting_started_verilator.md
+++ b/doc/ug/getting_started_verilator.md
@@ -38,6 +38,9 @@
$ ninja -C build-out all
```
+The above command also builds the OTP image that contains the root secrets and life cycle state.
+By default, the life cycle state will be moved into DEV, which enables debugging features such as the JTAG interface for the main processor.
+
Now the simulation can be run.
The programs listed after `--meminit` are loaded into the system's specified memory and execution is started immediately.
@@ -45,7 +48,8 @@
$ cd $REPO_TOP
$ build/lowrisc_systems_top_earlgrey_verilator_0.1/sim-verilator/Vtop_earlgrey_verilator \
--meminit=rom,build-bin/sw/device/boot_rom/boot_rom_sim_verilator.elf \
- --meminit=flash,build-bin/sw/device/examples/hello_world/hello_world_sim_verilator.elf
+ --meminit=flash,build-bin/sw/device/examples/hello_world/hello_world_sim_verilator.elf \
+ --meminit=otp,build-bin/sw/device/otp_img/otp_img_sim_verilator.vmem
```
To stop the simulation press CTRL-c.
@@ -102,6 +106,7 @@
$ build/lowrisc_systems_top_earlgrey_verilator_0.1/sim-verilator/Vtop_earlgrey_verilator \
--meminit=rom,build-bin/sw/device/boot_rom/boot_rom_sim_verilator.elf \
--meminit=flash,build-bin/sw/device/examples/hello_world/hello_world_sim_verilator.elf \
+ --meminit=otp,build-bin/sw/device/otp_img/otp_img_sim_verilator.vmem \
+UARTDPI_LOG_uart0=-
```
@@ -198,6 +203,7 @@
$ build/lowrisc_systems_top_earlgrey_verilator_0.1/sim-verilator/Vtop_earlgrey_verilator \
--meminit=rom,build-bin/sw/device/boot_rom/boot_rom_sim_verilator.elf \
--meminit=flash,build-bin/sw/device/examples/hello_world/hello_world_sim_verilator.elf \
+ --meminit=otp,build-bin/sw/device/otp_img/otp_img_sim_verilator.vmem \
--trace
$ gtkwave sim.fst
```
diff --git a/hw/ip/otbn/README.md b/hw/ip/otbn/README.md
index 16959a6..7e5c7be 100644
--- a/hw/ip/otbn/README.md
+++ b/hw/ip/otbn/README.md
@@ -107,6 +107,7 @@
build/lowrisc_systems_top_earlgrey_verilator_0.1/sim-verilator/Vtop_earlgrey_verilator \
--meminit=rom,build-bin/sw/device/boot_rom/boot_rom_sim_verilator.elf \
--meminit=flash,build-bin/sw/device/tests/dif_otbn_smoketest_sim_verilator.elf \
+ --meminit=otp,build-bin/sw/device/otp_img/otp_img_sim_verilator.vmem \
+UARTDPI_LOG_uart0=- \
+OTBN_USE_MODEL=1
```
