[keymgr/dv] Add stress_all test
also enable stress_all with reset
Fix some variables which are not re-initialized correctly after reset
Signed-off-by: Weicai Yang <weicai@google.com>
diff --git a/hw/ip/keymgr/dv/env/keymgr_env.core b/hw/ip/keymgr/dv/env/keymgr_env.core
index 00c41f8..d2d799b 100644
--- a/hw/ip/keymgr/dv/env/keymgr_env.core
+++ b/hw/ip/keymgr/dv/env/keymgr_env.core
@@ -28,6 +28,7 @@
- seq_lib/keymgr_direct_to_disabled_vseq.sv: {is_include_file: true}
- seq_lib/keymgr_lc_disable_vseq.sv: {is_include_file: true}
- seq_lib/keymgr_invalid_kmac_input_vseq.sv: {is_include_file: true}
+ - seq_lib/keymgr_stress_all_vseq.sv: {is_include_file: true}
file_type: systemVerilogSource
generate:
diff --git a/hw/ip/keymgr/dv/env/keymgr_if.sv b/hw/ip/keymgr/dv/env/keymgr_if.sv
index cc511b4..462ed52 100644
--- a/hw/ip/keymgr/dv/env/keymgr_if.sv
+++ b/hw/ip/keymgr/dv/env/keymgr_if.sv
@@ -17,22 +17,22 @@
keymgr_pkg::hw_key_req_t hmac_key;
keymgr_pkg::hw_key_req_t aes_key;
- keymgr_pkg::hw_key_req_t kmac_key_exp = '0;
- keymgr_pkg::hw_key_req_t hmac_key_exp = '0;
- keymgr_pkg::hw_key_req_t aes_key_exp = '0;
+ keymgr_pkg::hw_key_req_t kmac_key_exp;
+ keymgr_pkg::hw_key_req_t hmac_key_exp;
+ keymgr_pkg::hw_key_req_t aes_key_exp;
// connect KDF interface for assertion check
wire keymgr_pkg::kmac_data_req_t kmac_data_req;
wire keymgr_pkg::kmac_data_rsp_t kmac_data_rsp;
// indicate if check the key is same as expected or shouldn't match to any meaningful key
- bit is_kmac_key_good = 0;
- bit is_hmac_key_good = 0;
- bit is_aes_key_good = 0;
+ bit is_kmac_key_good;
+ bit is_hmac_key_good;
+ bit is_aes_key_good;
// when kmac sideload key is generated, kmac may be used to do other OP, but once the OP is done,
// it should automatically switch back to sideload key
- bit is_kmac_sideload_avail = 0;
+ bit is_kmac_sideload_avail;
keymgr_env_pkg::key_shares_t kmac_sideload_key_shares;
keymgr_env_pkg::key_shares_t keys_a_array[string][string];
@@ -46,6 +46,15 @@
// this sequencing is correct.
keymgr_en = lc_ctrl_pkg::lc_tx_t'($urandom);
+ // reset exp variables
+ kmac_key_exp = '0;
+ hmac_key_exp = '0;
+ aes_key_exp = '0;
+ is_kmac_key_good = 0;
+ is_hmac_key_good = 0;
+ is_aes_key_good = 0;
+ is_kmac_sideload_avail = 0;
+
// async delay as these signals are from different clock domain
#($urandom_range(1000, 0) * 1ns);
keymgr_en = lc_ctrl_pkg::On;
diff --git a/hw/ip/keymgr/dv/env/seq_lib/keymgr_base_vseq.sv b/hw/ip/keymgr/dv/env/seq_lib/keymgr_base_vseq.sv
index 26fb627..2712075 100644
--- a/hw/ip/keymgr/dv/env/seq_lib/keymgr_base_vseq.sv
+++ b/hw/ip/keymgr/dv/env/seq_lib/keymgr_base_vseq.sv
@@ -20,7 +20,7 @@
// save DUT returned current state here, rather than using it from RAL, it's needed info to
// predict operation result in seq
- keymgr_pkg::keymgr_working_state_e current_state;
+ keymgr_pkg::keymgr_working_state_e current_state = keymgr_pkg::StReset;
rand bit is_key_version_err;
@@ -52,8 +52,6 @@
// setup basic keymgr features
virtual task keymgr_init();
- current_state = keymgr_pkg::StReset;
-
// Any OP except advance at StReset will trigger OP error, test these OPs here
if (do_op_before_init) begin
repeat ($urandom_range(1, 5)) begin
diff --git a/hw/ip/keymgr/dv/env/seq_lib/keymgr_common_vseq.sv b/hw/ip/keymgr/dv/env/seq_lib/keymgr_common_vseq.sv
index 6b15d2a..9ab6270 100644
--- a/hw/ip/keymgr/dv/env/seq_lib/keymgr_common_vseq.sv
+++ b/hw/ip/keymgr/dv/env/seq_lib/keymgr_common_vseq.sv
@@ -10,6 +10,16 @@
}
`uvm_object_new
+ // override this delay for keymgr_stress_all_with_rand_reset, as most of vseq finishes less than
+ // 10k cycles
+ constraint delay_to_reset_c {
+ delay_to_reset dist {
+ [1 : 100] :/ 1,
+ [101 : 2_000] :/ 6,
+ [2_001 : 10_000] :/ 1
+ };
+ }
+
virtual task pre_start();
do_keymgr_init = 1'b0;
super.pre_start();
diff --git a/hw/ip/keymgr/dv/env/seq_lib/keymgr_stress_all_vseq.sv b/hw/ip/keymgr/dv/env/seq_lib/keymgr_stress_all_vseq.sv
new file mode 100644
index 0000000..4992e10
--- /dev/null
+++ b/hw/ip/keymgr/dv/env/seq_lib/keymgr_stress_all_vseq.sv
@@ -0,0 +1,54 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// combine all keymgr seqs (except below seqs) in one seq to run sequentially
+// 1. csr seq, which requires scb to be disabled
+// 2. keymgr_cfgen_vseq as it's very timing sensitive
+class keymgr_stress_all_vseq extends keymgr_base_vseq;
+ `uvm_object_utils(keymgr_stress_all_vseq)
+
+ `uvm_object_new
+
+ task body();
+ string seq_names[] = {"keymgr_smoke_vseq",
+ "keymgr_common_vseq", // for intr_test
+ "keymgr_sideload_vseq",
+ "keymgr_random_vseq",
+ "keymgr_direct_to_disabled_vseq",
+ // TODO, add this later
+ //"keymgr_lc_disable_vseq",
+ "keymgr_invalid_kmac_input_vseq"};
+ for (int i = 1; i <= num_trans; i++) begin
+ uvm_sequence seq;
+ keymgr_base_vseq keymgr_vseq;
+ uint seq_idx = $urandom_range(0, seq_names.size - 1);
+
+ seq = create_seq_by_name(seq_names[seq_idx]);
+ `downcast(keymgr_vseq, seq)
+
+ // at the end of each vseq, design has enterred StDisabled, need to reset to recover
+ // if upper seq disables do_dut_init for this seq, then can't issue reset
+ // as upper seq may drive reset
+ if (do_dut_init && i > 1) keymgr_vseq.do_dut_init = 1;
+ else keymgr_vseq.do_dut_init = 0;
+
+ keymgr_vseq.set_sequencer(p_sequencer);
+ `DV_CHECK_RANDOMIZE_FATAL(keymgr_vseq)
+ if (seq_names[seq_idx] == "keymgr_common_vseq") begin
+ keymgr_common_vseq common_vseq;
+ `downcast(common_vseq, keymgr_vseq);
+ common_vseq.common_seq_type = "intr_test";
+ end
+
+ keymgr_vseq.start(p_sequencer);
+
+ // this is for keymgr_stress_all_with_rand_reset
+ // we need to reset for each vseq, but in keymgr_stress_all_with_rand_reset, reset should be
+ // issued in upper seq. So, wait forever until reset is issued and this vseq is killed by
+ // upper seq
+ if (!do_dut_init) wait(0);
+ end
+ endtask : body
+
+endclass
diff --git a/hw/ip/keymgr/dv/env/seq_lib/keymgr_vseq_list.sv b/hw/ip/keymgr/dv/env/seq_lib/keymgr_vseq_list.sv
index 2de7de0..e451548 100644
--- a/hw/ip/keymgr/dv/env/seq_lib/keymgr_vseq_list.sv
+++ b/hw/ip/keymgr/dv/env/seq_lib/keymgr_vseq_list.sv
@@ -11,3 +11,4 @@
`include "keymgr_direct_to_disabled_vseq.sv"
`include "keymgr_lc_disable_vseq.sv"
`include "keymgr_invalid_kmac_input_vseq.sv"
+`include "keymgr_stress_all_vseq.sv"
diff --git a/hw/ip/keymgr/dv/keymgr_sim_cfg.hjson b/hw/ip/keymgr/dv/keymgr_sim_cfg.hjson
index 9bc47b9..814ddf8 100644
--- a/hw/ip/keymgr/dv/keymgr_sim_cfg.hjson
+++ b/hw/ip/keymgr/dv/keymgr_sim_cfg.hjson
@@ -33,8 +33,7 @@
"{proj_root}/hw/dv/tools/dvsim/tests/intr_test.hjson",
"{proj_root}/hw/dv/tools/dvsim/tests/alert_test.hjson",
"{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson",
- // TODO, enable it later
- // "{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson"
+ "{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson"
]
// Add additional tops for simulation.
@@ -85,6 +84,11 @@
name: keymgr_invalid_kmac_input
uvm_test_seq: keymgr_invalid_kmac_input_vseq
}
+
+ {
+ name: keymgr_stress_all
+ uvm_test_seq: keymgr_stress_all_vseq
+ }
]
// List of regressions.
