[doc] Prefer relative links in Markdown Relative links make it easier to relocate files, prefer using them where possible. Signed-off-by: Philipp Wagner <phw@lowrisc.org>
diff --git a/hw/ip/otbn/doc/_index.md b/hw/ip/otbn/doc/_index.md index 5a1085c..6a8e37a 100644 --- a/hw/ip/otbn/doc/_index.md +++ b/hw/ip/otbn/doc/_index.md
@@ -48,7 +48,7 @@ # Instruction Set OTBN is a processor with a custom instruction set. -The full ISA description can be found in our [ISA manual]({{< relref "hw/ip/otbn/doc/isa" >}}). +The full ISA description can be found in our [ISA manual]({{< relref "isa" >}}). The instruction set is split into two groups: * The **base instruction subset** operates on the 32b General Purpose Registers (GPRs). @@ -94,7 +94,7 @@ OTBN has an in-built call stack which is accessed through the `x1` GPR. This is intended to be used as a return address stack, containing return addresses for the current stack of function calls. -See the documentation for [`JAL`]({{< relref "hw/ip/otbn/doc/isa#jal" >}}) and [`JALR`]({{< relref "hw/ip/otbn/doc/isa#jalr" >}}) for a description of how to use it for this purpose. +See the documentation for [`JAL`]({{< relref "isa#jal" >}}) and [`JALR`]({{< relref "isa#jalr" >}}) for a description of how to use it for this purpose. The call stack has a maximum depth of 8 elements. Each instruction that reads from `x1` pops a single element from the stack. @@ -291,7 +291,7 @@ OTBN has 256b Wide Special purpose Registers (WSRs). These are analogous to the 32b CSRs, but are used by big number instructions. -They can be accessed with the [`BN.WSRRS`]({{< relref "hw/ip/otbn/doc/isa#bnwsrrs" >}}) and [`BN.WSRRW`]({{< relref "hw/ip/otbn/doc/isa#bnwsrrw" >}}) instructions. +They can be accessed with the [`BN.WSRRS`]({{< relref "isa#bnwsrrs" >}}) and [`BN.WSRRW`]({{< relref "isa#bnwsrrw" >}}) instructions. <table> <thead> @@ -309,7 +309,7 @@ <td>RW</td> <td> -The modulus used by the [`BN.ADDM`]({{< relref "hw/ip/otbn/doc/isa#bnaddm" >}}) and [`BN.SUBM`]({{< relref "hw/ip/otbn/doc/isa#bnsubm" >}}) instructions. +The modulus used by the [`BN.ADDM`]({{< relref "isa#bnaddm" >}}) and [`BN.SUBM`]({{< relref "isa#bnsubm" >}}) instructions. This WSR is also visible as CSRs `MOD0` through to `MOD7`. </td> @@ -356,7 +356,7 @@ ### Loop Stack -OTBN has two instructions for hardware-assisted loops: [`LOOP`]({{< relref "hw/ip/otbn/doc/isa#loop" >}}) and [`LOOPI`]({{< relref "hw/ip/otbn/doc/isa#loopi" >}}). +OTBN has two instructions for hardware-assisted loops: [`LOOP`]({{< relref "isa#loop" >}}) and [`LOOPI`]({{< relref "isa#loopi" >}}). Both use the same state for tracking control flow. This is a stack of tuples containing a loop count, start address and end address. The stack has a maximum depth of eight and the top of the stack is the current loop. @@ -468,7 +468,7 @@ Whenever OTBN observes an error, it will generate an alert. This gets sent to the alert manager. -The alert will either be fatal or recoverable, depending on the class of error: see [Alerts]({{< relref "hw/ip/otbn/doc#alerts" >}}) and {{< regref "ERR_BITS" >}} below for details. +The alert will either be fatal or recoverable, depending on the class of error: see [Alerts]({{< relref "#alerts" >}}) and {{< regref "ERR_BITS" >}} below for details. If OTBN was running when the alert occurred (this is true whenever {{< regref "STATUS.busy" >}} is high), it will also: - Immediately stop fetching and executing instructions. @@ -480,7 +480,7 @@ In this case, the {{< regref "ERR_BITS" >}} register will not change. This avoids race conditions with the host processor's error handling software. However, every error that OTBN detects when it isn't running causes a fatal alert. -This means that the cause will be reflected in {{< regref "FATAL_ALERT_CAUSE" >}}, as described below in [Alerts]({{< relref "hw/ip/otbn/doc#alerts" >}}). +This means that the cause will be reflected in {{< regref "FATAL_ALERT_CAUSE" >}}, as described below in [Alerts]({{< relref "#alerts" >}}). This way, no alert is generated without setting an error code somewhere. <div class="bd-callout bd-callout-warning"> @@ -556,7 +556,7 @@ # Writing OTBN applications {#writing-otbn-applications} OTBN applications are (small) pieces of software written in OTBN assembly. -The full instruction set is described in the [ISA manual]({{< relref "hw/ip/otbn/doc/isa" >}}), and example software is available in the `sw/otbn` directory of the OpenTitan source tree. +The full instruction set is described in the [ISA manual]({{< relref "isa" >}}), and example software is available in the `sw/otbn` directory of the OpenTitan source tree. A hands-on user guide to develop OTBN software can be found in the section [Writing and building software for OTBN]({{<relref "doc/ug/otbn_sw.md" >}}). @@ -580,7 +580,7 @@ ## Returning from an application -The software running on OTBN signals completion by executing the [`ECALL`]({{< relref "hw/ip/otbn/doc/isa#ecall" >}}) instruction. +The software running on OTBN signals completion by executing the [`ECALL`]({{< relref "isa#ecall" >}}) instruction. When it executes this instruction, OTBN: - Stops fetching and executing instructions.
diff --git a/hw/ip/otbn/doc/dv/index.md b/hw/ip/otbn/doc/dv/index.md index 2e15455..d1b7159 100644 --- a/hw/ip/otbn/doc/dv/index.md +++ b/hw/ip/otbn/doc/dv/index.md
@@ -18,7 +18,7 @@ ## Design features OTBN, the OpenTitan Big Number accelerator, is a cryptographic accelerator. -For detailed information on OTBN design features, see the [OTBN HWIP technical specification]({{< relref "hw/ip/otbn/doc" >}}). +For detailed information on OTBN design features, see the [OTBN HWIP technical specification]({{< relref ".." >}}). ## Testbench architecture
diff --git a/hw/ip/otbn/doc/isa.md b/hw/ip/otbn/doc/isa.md index 9d18d1d..0c267e2 100644 --- a/hw/ip/otbn/doc/isa.md +++ b/hw/ip/otbn/doc/isa.md
@@ -3,7 +3,7 @@ --- This document describes the instruction set for OTBN. -For more details about the processor itself, see the [OTBN Technical Specification]({{< relref "hw/ip/otbn/doc" >}}). +For more details about the processor itself, see the [OTBN Technical Specification]({{< relref "." >}}). In particular, this document assumes knowledge of the *Processor State* section from that guide. The instruction set is split into *base* and *big number* subsets.