commit 0746fead60d550021c2108fec1b1e195ecb0c26f
author Cindy Chen <chencindy@opentitan.org> Fri Sep 10 16:41:57 2021 -0700
committer cindychip <cindy.chen0316@gmail.com> Fri Sep 10 18:25:34 2021 -0700
tree 46f7021224a052d477908896db2969058b0e823d
parent d8383261d82ffe97410b3e6d9cfcf3bad88a3c62

[dv/alert-handler] add sequence to support new regs

This PR adds sequence to support read/write to new regs:
1). loc_alert_cause (originally only check loc_alert_casue_0)
2). crashdump_trigger_shadowed (newly added)

Signed-off-by: Cindy Chen <chencindy@opentitan.org>

hw/ip/alert_handler/dv/env/seq_lib/alert_handler_base_vseq.sv

diff --git a/hw/ip/alert_handler/dv/env/seq_lib/alert_handler_base_vseq.sv b/hw/ip/alert_handler/dv/env/seq_lib/alert_handler_base_vseq.sv
index ca9b45b..dc9fb75 100644
--- a/hw/ip/alert_handler/dv/env/seq_lib/alert_handler_base_vseq.sv
+++ b/hw/ip/alert_handler/dv/env/seq_lib/alert_handler_base_vseq.sv
@@ -148,8 +148,16 @@
   // checking for csr_rd is done in scb
   virtual task read_alert_cause();
     bit [TL_DW-1:0] alert_cause;
-    csr_rd(.ptr(ral.alert_cause[0]), .value(alert_cause));
-    csr_rd(.ptr(ral.loc_alert_cause[0]), .value(alert_cause));
+    foreach (ral.alert_cause[i]) begin
+      if ($urandom_range(0, 1)) begin
+        csr_rd(.ptr(ral.alert_cause[i]), .value(alert_cause));
+      end
+    end
+    foreach (ral.loc_alert_cause[i]) begin
+      if ($urandom_range(0, 1)) begin
+        csr_rd(.ptr(ral.loc_alert_cause[i]), .value(alert_cause));
+      end
+    end
   endtask
 
   virtual task read_esc_status();
@@ -227,6 +235,16 @@
     join
   endtask
 
+  virtual task alert_handler_crashdump_phases(bit [1:0] classa_phase = $urandom(),
+                                              bit [1:0] classb_phase = $urandom(),
+                                              bit [1:0] classc_phase = $urandom(),
+                                              bit [1:0] classd_phase = $urandom());
+    csr_wr(.ptr(ral.classa_crashdump_trigger_shadowed), .value(classa_phase));
+    csr_wr(.ptr(ral.classb_crashdump_trigger_shadowed), .value(classb_phase));
+    csr_wr(.ptr(ral.classc_crashdump_trigger_shadowed), .value(classc_phase));
+    csr_wr(.ptr(ral.classd_crashdump_trigger_shadowed), .value(classd_phase));
+  endtask
+
   virtual task wr_phases_cycle(int max_phase_cyc);
     `RAND_AND_WR_CLASS_PHASES_CYCLE(a);
     `RAND_AND_WR_CLASS_PHASES_CYCLE(b);

hw/ip/alert_handler/dv/env/seq_lib/alert_handler_smoke_vseq.sv

diff --git a/hw/ip/alert_handler/dv/env/seq_lib/alert_handler_smoke_vseq.sv b/hw/ip/alert_handler/dv/env/seq_lib/alert_handler_smoke_vseq.sv
index dabda7f..6940b12 100644
--- a/hw/ip/alert_handler/dv/env/seq_lib/alert_handler_smoke_vseq.sv
+++ b/hw/ip/alert_handler/dv/env/seq_lib/alert_handler_smoke_vseq.sv
@@ -125,6 +125,9 @@
       alert_handler_rand_wr_class_ctrl(lock_bit_en);
       alert_handler_wr_regwen_regs(clr_en);
 
+      // randomize crashdump triggered phases
+      alert_handler_crashdump_phases();
+
       // randomly write phase cycle registers
       // always set phase_cycle for the first iteration, in order to pass stress_all test
       if (do_wr_phases_cyc || i == 1) wr_phases_cycle(max_phase_cyc);