| commit | 0731d51b7a9e0a80b41eff9ebe93a2fe72c409f9 | [log] [tgz] |
|---|---|---|
| author | Stefan Wallentowitz <stefan.wallentowitz@gi-de.com> | Tue Jul 14 21:55:14 2020 +0200 |
| committer | Rupert Swarbrick <rswarbrick@gmail.com> | Wed Aug 26 15:00:42 2020 +0100 |
| tree | 8a16948f95892f4a4c65c054d7ce961a08a465af | |
| parent | fac8e2f97bcedfb8e71ec8a8ceed7696682d16f6 [diff] |
[otbn] Add some OTBN instructions to otbnsim
Add the variant, model and basic instruction support.
We also dump an execution trace to a file (/tmp/otbn_XXXXX/trace) and
print out the name of the trace directory, which should make debugging
rather easier.
As a sanity check, run it with the smoke test example as follows:
mkdir -p build-bin/otbn/smoke_test
hw/ip/otbn/util/build.sh \
hw/ip/otbn/dv/smoke/smoke_test.S \
build-bin/otbn/smoke_test/smoke
hw/ip/otbn/dv/otbnsim/standalone.py -v \
build-bin/otbn/smoke_test/smoke.elf
The trace looks like this:
lui x1, 855019 | [x1 = d0beb000]
addi x1, x1, 1299 | [x1 = d0beb513]
lui x2, 658409 | [x2 = a0be9000]
addi x2, x2, 282 | [x2 = a0be911a]
add x3, x1, x2 | [x3 = 717d462d, x1 = 00000000]
sub x4, x2, x1 | [x4 = a0be911a]
or x5, x1, x2 | [x5 = a0be911a]
and x6, x1, x2 | [x6 = 00000000]
xor x7, x1, x2 | [x7 = a0be911a]
ori x8, x1, 291 | [x8 = 00000123]
andi x9, x1, 1980 | [x9 = 00000000]
xori x10, x1, 1146 | [x10 = 0000047a]
slli x11, x1, 0x0a | [x11 = 00000000]
srli x12, x1, 0x0d | [x12 = 00000000]
srai x13, x1, 0x07 | [x13 = 00000000]
sll x14, x1, x2 | [x14 = 00000000]
srl x15, x1, x2 | [x15 = 00000000]
sra x16, x1, x2 | [x16 = 00000000]
Notice the updates to x1: the code is using it just like a normal
register, but we know better(!) and are treating it as a hardware call
stack.
This also behaves "as expected" when running the loop.S code snippet.
Generate that with
make -C hw/ip/otbn/util asm-sanity
hw/ip/otbn/dv/otbnsim/standalone.py -v \
build-bin/otbn/util/code-snippets/loop
Finally, note that we bump the required version of riscv-model. This
is because there's an API break between 0.6.2 and 0.6.4 (the module
exporting TerminateException changes from riscvmodel.isa to
riscvmodel.model).
Signed-off-by: Stefan Wallentowitz <stefan.wallentowitz@gi-de.com>
Co-authored-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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