| commit | 06fe080b7dcfc9a03aa5c66c83c99dee86da6c59 | [log] [tgz] |
|---|---|---|
| author | Rupert Swarbrick <rswarbrick@lowrisc.org> | Fri Oct 01 17:03:19 2021 +0100 |
| committer | Rupert Swarbrick <rswarbrick@gmail.com> | Mon Oct 04 09:29:32 2021 +0100 |
| tree | 6cd8252b43e47e790148aea76517c20daad0f0b8 | |
| parent | 8fce3aae01812ee0dc8da1fd699748034e64b50a [diff] |
[otbn,dv] Report IMEM fetch errors more helpfully in OTBN tracer
If we've seen an IMEM fetch error, this changes the trace from
something like
E PC: 0x00000b10, insn: 0x84d72c7b
to something like
E PC: 0x00000b10, insn: ??
Since the IMEM rdata is known to be bogus at this point, we don't
really want to display it. This also makes things easier on the ISS
side, where we don't need to model changes to the bits themselves
that are caused by 1- or 2-bit injected errors.
This patch also makes sure that we always print out an 'E' line.
Before, it was either 'E' or 'S', depending on whether the current
instruction was stalled or not. (Which would be very finicky to model
in the ISS and not really do anything useful).
Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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