[syn] Minor updates to align flow with foundry setup scripts
Signed-off-by: Michael Schaffner <msf@google.com>
diff --git a/hw/syn/tools/dc/run-syn.tcl b/hw/syn/tools/dc/run-syn.tcl
index 546bba3..86c1f32 100644
--- a/hw/syn/tools/dc/run-syn.tcl
+++ b/hw/syn/tools/dc/run-syn.tcl
@@ -84,7 +84,7 @@
set_verification_top
write_file -format ddc -hierarchy -output "${DDCDIR}/elab.ddc"
-write_file -format verilog -hierarchy -output "${DDCDIR}/elab.v"
+#write_file -format verilog -hierarchy -output "${DDCDIR}/elab.v"
#############################
## CLOCK GATING SETUP ##
@@ -138,9 +138,9 @@
## NETLIST ##
#################
-# change_names -rules verilog -hierarchy
-# define_name_rules fixbackslashes -allowed "A-Za-z0-9_" -first_restricted "\\" -remove_chars
-# change_names -rule fixbackslashes -h
+change_names -rules verilog -hierarchy
+define_name_rules fixbackslashes -allowed "A-Za-z0-9_" -first_restricted "\\" -remove_chars
+change_names -rule fixbackslashes -h
write_file -format ddc -hierarchy -output "${DDCDIR}/mapped.ddc"
write_file -format verilog -hierarchy -output "${VLOGDIR}/mapped.v"
diff --git a/hw/top_earlgrey/syn/constraints.sdc b/hw/top_earlgrey/syn/constraints.sdc
index 3e496d5..1f01d7b 100644
--- a/hw/top_earlgrey/syn/constraints.sdc
+++ b/hw/top_earlgrey/syn/constraints.sdc
@@ -186,8 +186,8 @@
#####################
# attach load and drivers to IOs to get a more realistic estimate
-set_driving_cell -no_design_rule -lib_cell ${DRIVING_CELL} -pin X [all_inputs]
-set_load [load_of ${LOAD_LIB}/${LOAD_CELL}/A] [all_outputs]
+set_driving_cell -no_design_rule -lib_cell ${DRIVING_CELL} -pin ${DRIVING_CELL_PIN} [all_inputs]
+set_load [load_of ${LOAD_CELL_LIB}/${LOAD_CELL}/${LOAD_CELL_PIN}] [all_outputs]
# set a nonzero critical range to be able to spot the violating paths better
# in the report
@@ -199,4 +199,4 @@
set_size_only -all_instances [get_cells -h *u_size_only*] true
-puts "Done applying constraints for top level"
\ No newline at end of file
+puts "Done applying constraints for top level"
