| commit | 067272a253f4eeed4ae58a9171ee266256528117 | [log] [tgz] |
|---|---|---|
| author | Srikrishna Iyer <sriyer@google.com> | Tue Jul 21 22:35:35 2020 -0700 |
| committer | sriyerg <46467186+sriyerg@users.noreply.github.com> | Wed Jul 22 20:59:45 2020 -0700 |
| tree | 43e71950ea2d656388ff343e7a71a191f708b509 | |
| parent | 0697e5f228c173ba05f5d2d34c5419f2f42d7052 [diff] |
[dv, dvsim] Support multiple fusesoc cores-root This PR adds ability to completely modify and customize the way fusesoc cores-root directories are presented to fusesoc. This is done to support Nuvoton so that they can pick and choose the 'right' dependencies from their closed source repo (swapping for the opensource fusesoc core with the same vlnv). The relevant discussion on this can be found here: https://docs.google.com/document/d/1r5KJ_GrY7XMy9ZITErrEhJMyFwnxOkke-1B-fc7x_D4/edit A sample `hw/top_earlgrey/dv/vendor_chip_sim_cfg_sample.hjson` is provided as an example that reuses the chip simulation cfg file (by importing it) and overridding the `fusesoc_cores_root_dirs` variable to set the fusesoc search paths as desired. Simulations can then be run with dvsim by supplying it with this modified simulation cfg hjson file. Signed-off-by: Srikrishna Iyer <sriyer@google.com>
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