Update lowrisc_ibex to lowRISC/ibex@1d2959e
Update code from upstream repository
https://github.com/lowRISC/ibex.git to revision
1d2959e00a85e7726347b29627ba568ba34440c1
* [dv] Record failure on log processing error (Greg Chadwick)
* [dv] Quit on UVM errors by default (Greg Chadwick)
* [rtl] Fix xprop issues in cs_registers (Greg Chadwick)
* [rtl] Modify ASSERT_KNOWN uses to work with xprop (Greg Chadwick)
* [dv] Define `UVM for DV sim compiles (Greg Chadwick)
* [dv] fix DSim simulation command options (lowRISC/ibex#760)
(udinator)
* [doc] Add Ibex Concierge documentation (Philipp Wagner)
* [dv] fix timing issue in single_step test (lowRISC/ibex#749)
(udinator)
* [ci] Mark configs using experimental features (Greg Chadwick)
* [ci] Add Ibex with RV32B to configurations (Greg Chadwick)
* [rtl] Add RV32B to various core files & top-levels (Greg Chadwick)
* Fix destination for dumped waves in dv/uvm (Rupert Swarbrick)
* [dv] move all SV interface includes into ibex_dv.f
(lowRISC/ibex#747) (udinator)
* [dv] initial icache testbench (lowRISC/ibex#711) (udinator)
* [rtl] Unify top-level parameter declaration (Tom Roberts)
* [doc/icache] Document the err_plus2_o signal (Tom Roberts)
* [rtl/pmp] Fix PMP error prioritization (Tom Roberts)
* [bitmanip] Add ZBB Instruction Group (ganoam)
* Clarify a couple of points in icache documentation (Rupert
Swarbrick)
* Factor out ibex_pkg.sv into a separate core file (Philipp Wagner)
* Fix description of ISA extensions in core file (Philipp Wagner)
* [ci] Introduce multiple-configuration CI (Greg Chadwick)
* [rtl] Lint fixes (Greg Chadwick)
* Update .core files to add full parameter support (Greg Chadwick)
* [dv] update mtvec alignment in Makefile (Udi)
* Remove unused ibex_pkg from tracer (lowRISC/ibex#737) (Philipp
Wagner)
* Correct PMP granularity equation (Philipp Wagner)
* Update google_riscv-dv to google/riscv-dv@7675315 (lowRISC/ibex#733)
(udinator)
* [dv] remove return value from the compare() step (lowRISC/ibex#732)
(udinator)
* [rtl] Branch signal timing fix (Tom Roberts)
* [rtl] Extend BT ALU to be used for all jumps (Tom Roberts)
* Fix incorrect indentation in sim.py (Rupert Swarbrick)
* correct passing argument for sim_opts (Dawid Zimonczyk)
* added simulation option, added sv_seed in sim cmd (Dawid Zimonczyk)
* Update GCC to include bitmanip patches (Philipp Wagner)
* [rtl/icache] Fix an inconsistency in data output (Tom Roberts)
* [rtl] Remove stall cycle with BT ALU (Tom Roberts)
* Update google_riscv-dv to google/riscv-dv@5baf82a (lowRISC/ibex#723)
(udinator)
* [dv] fix irq timing in irq_in_debug_mode_test (lowRISC/ibex#720)
(udinator)
* [rtl/icache] Fix a couple of icache bugs (Tom Roberts)
* [rtl] Instantiate instruction cache (Tom Roberts)
* [verilator] Fix --term-after-cycles (Luís Marques)
* [dv] workaround for dsim compile error (lowRISC/ibex#716) (udinator)
* [rtl] Fix mtval for unaligned instr errors (Tom Roberts)
* [rtl/icache] Fix PMP error logic (Tom Roberts)
* [rtl] Add Icache ECC (Tom Roberts)
* [rtl] Icache RAM primitive changes (Tom Roberts)
* [cov] remove unnecessary forward slash in makefile
(lowRISC/ibex#710) (udinator)
* Enable the use of Verible through fusesoc (Philipp Wagner)
* Add Verible lint as one lint option (Philipp Wagner)
* [dv] coverage generation (lowRISC/ibex#704) (udinator)
* [rtl/icache] Make age matrix more consistent (Tom Roberts)
* [CI] Add explicit trigger for branches/PRs (Greg Chadwick)
* [rtl/sw] Add multiply and divide wait counters (Greg Chadwick)
* Add missing dependencies in uvm/core_ibex/Makefile (Rupert
Swarbrick)
* Explicitly pass directory for waves to VCS's UCLI TCL (Rupert
Swarbrick)
* Explicitly use bash in UVM Makefile (Rupert Swarbrick)
* Notes on the ICache specification (Rupert Swarbrick)
* Resolve Questa: Defaulting port to var rather than wire (danghai)
* Ignore modelsim.ini generated from Questa tool (danghai)
* Remove property from assert message (Philipp Wagner)
* Align prim_assert.sv with OpenTitan (Philipp Wagner)
* Use a syntax compatible with Verible (Philipp Wagner)
* Questa qrun: Extra checking for conflicts with always_comb and
always_latch variables is done at vopt time. (danghai)
* Add missing space after code-block directive (Rupert Swarbrick)
* [syn] Place result directories in sub-directory (Greg Chadwick)
* Ignore Emacs backup files (Rupert Swarbrick)
* [doc] Fix paths in verification documentation (Philipp Wagner)
* [rtl] Fixes for single-cycle mutiply (Greg Chadwick)
* [rtl] Refactor some IF/ID stage registers (Tom Roberts)
* [rtl] IF stage timing fix (Tom Roberts)
* Fix typo in uvm/core_ibex/Makefile (Rupert Swarbrick)
* Add missing Makefile dependencies on testlist.yaml (Rupert
Swarbrick)
* update riscvOVPsim.ic for semihosting mode (lowRISC/ibex#681)
(udinator)
* Respect --lsf_cmd when compiling TB in sim.py (Rupert Swarbrick)
* Fixup module docstring in sim.py (Rupert Swarbrick)
* Tidy-ups in sim.py's compare function (Rupert Swarbrick)
* Remove unnecessary DV_DIR variable in dv/uvm/core_ibex/Makefile
(Rupert Swarbrick)
* Various cleanups in sim.py's rtl_sim function (Rupert Swarbrick)
* Pick a seed per run in sim.py (Rupert Swarbrick)
* Remove last use of re library in sim.py (Rupert Swarbrick)
* Remove --riscv-dv-root argument from sim.py (Rupert Swarbrick)
* Clean up --en_cov and --en_wave in sim.py (Rupert Swarbrick)
* Tidy up path name arguments in sim.py (Rupert Swarbrick)
* Tidy up command substitution in sim.py (Rupert Swarbrick)
* Move main program of sim.py into a function (Rupert Swarbrick)
* Tidy up imports in sim.py (Rupert Swarbrick)
* Re-indent sim.py (Rupert Swarbrick)
* It should give error message instead of info message for failure
(danghai)
* [ml] fix irq test for ML (lowRISC/ibex#675) (udinator)
* Update google_riscv-dv to google/riscv-dv@3f584ad (lowRISC/ibex#676)
(udinator)
* [dv] update timeout for INITIALIZED response (lowRISC/ibex#672)
(udinator)
* Update google_riscv-dv to google/riscv-dv@6344e95 (lowRISC/ibex#673)
(udinator)
* [ml] add condensed test targets for ML (lowRISC/ibex#659) (udinator)
* [syn] Synthesis fixes (Greg Chadwick)
* [sw] Add Coremark makefile and support files (Greg Chadwick)
* Update eembc_coremark to eembc/coremark@0c91314 (Greg Chadwick)
* [sw/simple_system] Add PCOUNT_READ macro (Greg Chadwick)
* [ci] Fix removal of vendored files from C/C++ lint (Greg Chadwick)
* Add support for Qrun Questa (danghai)
* [I-Cache] Initial commit of prototype RTL (Tom Roberts)
* [RTL] Add configurable third pipeline stage (Greg Chadwick)
Signed-off-by: Greg Chadwick <gac@lowrisc.org>
diff --git a/hw/vendor/lowrisc_ibex/syn/README.md b/hw/vendor/lowrisc_ibex/syn/README.md
index 889b851..d7150d8 100644
--- a/hw/vendor/lowrisc_ibex/syn/README.md
+++ b/hw/vendor/lowrisc_ibex/syn/README.md
@@ -56,11 +56,11 @@
# Running the synthesis flow
Once `syn_setup.sh` has been created the `syn_yosys.sh` will run the entire
-flow. All outputs are placed in a directory with the prefix `syn_out_` with the
-current date/time forming the rest of the name, e.g.
-`syn_out_06_01_2020_11_19_15`
+flow. All outputs are placed under the `syn/syn_out` directory with the prefix
+`ibex_` with the current date/time forming the rest of the name, e.g.
+`syn/syn_out/ibex_06_01_2020_11_19_15`
-- `syn_out_dir`
+- `syn/syn_out/ibex_date`
- `reports` - All of the generated reports
- area.rpt - Total area used and per cell instance counts
- `timing`
@@ -77,6 +77,9 @@
- ibex_core.[library-name].out.sdc - Generated .sdc timing constraints
file
+If you wish to change the results directory naming or location edit
+`syn_setup.sh` appropriately.
+
# Timing constraints
Two files specify the timing constraints and timing related settings for the
