Update lowrisc_ibex to lowRISC/ibex@1d2959e
Update code from upstream repository
https://github.com/lowRISC/ibex.git to revision
1d2959e00a85e7726347b29627ba568ba34440c1
* [dv] Record failure on log processing error (Greg Chadwick)
* [dv] Quit on UVM errors by default (Greg Chadwick)
* [rtl] Fix xprop issues in cs_registers (Greg Chadwick)
* [rtl] Modify ASSERT_KNOWN uses to work with xprop (Greg Chadwick)
* [dv] Define `UVM for DV sim compiles (Greg Chadwick)
* [dv] fix DSim simulation command options (lowRISC/ibex#760)
(udinator)
* [doc] Add Ibex Concierge documentation (Philipp Wagner)
* [dv] fix timing issue in single_step test (lowRISC/ibex#749)
(udinator)
* [ci] Mark configs using experimental features (Greg Chadwick)
* [ci] Add Ibex with RV32B to configurations (Greg Chadwick)
* [rtl] Add RV32B to various core files & top-levels (Greg Chadwick)
* Fix destination for dumped waves in dv/uvm (Rupert Swarbrick)
* [dv] move all SV interface includes into ibex_dv.f
(lowRISC/ibex#747) (udinator)
* [dv] initial icache testbench (lowRISC/ibex#711) (udinator)
* [rtl] Unify top-level parameter declaration (Tom Roberts)
* [doc/icache] Document the err_plus2_o signal (Tom Roberts)
* [rtl/pmp] Fix PMP error prioritization (Tom Roberts)
* [bitmanip] Add ZBB Instruction Group (ganoam)
* Clarify a couple of points in icache documentation (Rupert
Swarbrick)
* Factor out ibex_pkg.sv into a separate core file (Philipp Wagner)
* Fix description of ISA extensions in core file (Philipp Wagner)
* [ci] Introduce multiple-configuration CI (Greg Chadwick)
* [rtl] Lint fixes (Greg Chadwick)
* Update .core files to add full parameter support (Greg Chadwick)
* [dv] update mtvec alignment in Makefile (Udi)
* Remove unused ibex_pkg from tracer (lowRISC/ibex#737) (Philipp
Wagner)
* Correct PMP granularity equation (Philipp Wagner)
* Update google_riscv-dv to google/riscv-dv@7675315 (lowRISC/ibex#733)
(udinator)
* [dv] remove return value from the compare() step (lowRISC/ibex#732)
(udinator)
* [rtl] Branch signal timing fix (Tom Roberts)
* [rtl] Extend BT ALU to be used for all jumps (Tom Roberts)
* Fix incorrect indentation in sim.py (Rupert Swarbrick)
* correct passing argument for sim_opts (Dawid Zimonczyk)
* added simulation option, added sv_seed in sim cmd (Dawid Zimonczyk)
* Update GCC to include bitmanip patches (Philipp Wagner)
* [rtl/icache] Fix an inconsistency in data output (Tom Roberts)
* [rtl] Remove stall cycle with BT ALU (Tom Roberts)
* Update google_riscv-dv to google/riscv-dv@5baf82a (lowRISC/ibex#723)
(udinator)
* [dv] fix irq timing in irq_in_debug_mode_test (lowRISC/ibex#720)
(udinator)
* [rtl/icache] Fix a couple of icache bugs (Tom Roberts)
* [rtl] Instantiate instruction cache (Tom Roberts)
* [verilator] Fix --term-after-cycles (Luís Marques)
* [dv] workaround for dsim compile error (lowRISC/ibex#716) (udinator)
* [rtl] Fix mtval for unaligned instr errors (Tom Roberts)
* [rtl/icache] Fix PMP error logic (Tom Roberts)
* [rtl] Add Icache ECC (Tom Roberts)
* [rtl] Icache RAM primitive changes (Tom Roberts)
* [cov] remove unnecessary forward slash in makefile
(lowRISC/ibex#710) (udinator)
* Enable the use of Verible through fusesoc (Philipp Wagner)
* Add Verible lint as one lint option (Philipp Wagner)
* [dv] coverage generation (lowRISC/ibex#704) (udinator)
* [rtl/icache] Make age matrix more consistent (Tom Roberts)
* [CI] Add explicit trigger for branches/PRs (Greg Chadwick)
* [rtl/sw] Add multiply and divide wait counters (Greg Chadwick)
* Add missing dependencies in uvm/core_ibex/Makefile (Rupert
Swarbrick)
* Explicitly pass directory for waves to VCS's UCLI TCL (Rupert
Swarbrick)
* Explicitly use bash in UVM Makefile (Rupert Swarbrick)
* Notes on the ICache specification (Rupert Swarbrick)
* Resolve Questa: Defaulting port to var rather than wire (danghai)
* Ignore modelsim.ini generated from Questa tool (danghai)
* Remove property from assert message (Philipp Wagner)
* Align prim_assert.sv with OpenTitan (Philipp Wagner)
* Use a syntax compatible with Verible (Philipp Wagner)
* Questa qrun: Extra checking for conflicts with always_comb and
always_latch variables is done at vopt time. (danghai)
* Add missing space after code-block directive (Rupert Swarbrick)
* [syn] Place result directories in sub-directory (Greg Chadwick)
* Ignore Emacs backup files (Rupert Swarbrick)
* [doc] Fix paths in verification documentation (Philipp Wagner)
* [rtl] Fixes for single-cycle mutiply (Greg Chadwick)
* [rtl] Refactor some IF/ID stage registers (Tom Roberts)
* [rtl] IF stage timing fix (Tom Roberts)
* Fix typo in uvm/core_ibex/Makefile (Rupert Swarbrick)
* Add missing Makefile dependencies on testlist.yaml (Rupert
Swarbrick)
* update riscvOVPsim.ic for semihosting mode (lowRISC/ibex#681)
(udinator)
* Respect --lsf_cmd when compiling TB in sim.py (Rupert Swarbrick)
* Fixup module docstring in sim.py (Rupert Swarbrick)
* Tidy-ups in sim.py's compare function (Rupert Swarbrick)
* Remove unnecessary DV_DIR variable in dv/uvm/core_ibex/Makefile
(Rupert Swarbrick)
* Various cleanups in sim.py's rtl_sim function (Rupert Swarbrick)
* Pick a seed per run in sim.py (Rupert Swarbrick)
* Remove last use of re library in sim.py (Rupert Swarbrick)
* Remove --riscv-dv-root argument from sim.py (Rupert Swarbrick)
* Clean up --en_cov and --en_wave in sim.py (Rupert Swarbrick)
* Tidy up path name arguments in sim.py (Rupert Swarbrick)
* Tidy up command substitution in sim.py (Rupert Swarbrick)
* Move main program of sim.py into a function (Rupert Swarbrick)
* Tidy up imports in sim.py (Rupert Swarbrick)
* Re-indent sim.py (Rupert Swarbrick)
* It should give error message instead of info message for failure
(danghai)
* [ml] fix irq test for ML (lowRISC/ibex#675) (udinator)
* Update google_riscv-dv to google/riscv-dv@3f584ad (lowRISC/ibex#676)
(udinator)
* [dv] update timeout for INITIALIZED response (lowRISC/ibex#672)
(udinator)
* Update google_riscv-dv to google/riscv-dv@6344e95 (lowRISC/ibex#673)
(udinator)
* [ml] add condensed test targets for ML (lowRISC/ibex#659) (udinator)
* [syn] Synthesis fixes (Greg Chadwick)
* [sw] Add Coremark makefile and support files (Greg Chadwick)
* Update eembc_coremark to eembc/coremark@0c91314 (Greg Chadwick)
* [sw/simple_system] Add PCOUNT_READ macro (Greg Chadwick)
* [ci] Fix removal of vendored files from C/C++ lint (Greg Chadwick)
* Add support for Qrun Questa (danghai)
* [I-Cache] Initial commit of prototype RTL (Tom Roberts)
* [RTL] Add configurable third pipeline stage (Greg Chadwick)
Signed-off-by: Greg Chadwick <gac@lowrisc.org>
diff --git a/hw/vendor/lowrisc_ibex.lock.hjson b/hw/vendor/lowrisc_ibex.lock.hjson
index 55aabe1..aaf50cb 100644
--- a/hw/vendor/lowrisc_ibex.lock.hjson
+++ b/hw/vendor/lowrisc_ibex.lock.hjson
@@ -9,6 +9,6 @@
upstream:
{
url: https://github.com/lowRISC/ibex.git
- rev: e4b8851b4bf056444416dfcb0c91df04ffba74ab
+ rev: 1d2959e00a85e7726347b29627ba568ba34440c1
}
}
diff --git a/hw/vendor/lowrisc_ibex/.gitignore b/hw/vendor/lowrisc_ibex/.gitignore
index 4b60bf0..5594051 100644
--- a/hw/vendor/lowrisc_ibex/.gitignore
+++ b/hw/vendor/lowrisc_ibex/.gitignore
@@ -6,6 +6,7 @@
.vscode/
.sw[a-p]
tags
+*~
# ibex_tracer log file
trace_core_*.log
@@ -20,6 +21,13 @@
# This is generated by VCS when running DV simulations with WAVE=1.
/dv/uvm/core_ibex/ucli.key
+# This is generated by UVM when running simulations and doesn't seem
+# to be something you can disable.
+/dv/uvm/core_ibex/tr_db.log
+
# This is the default output directory in dv/uvm/core_ibex and
# contains auto-generated files from building and running tests.
/dv/uvm/core_ibex/out
+
+# This is generated by Questa tool when running DV simulations
+modelsim.ini
diff --git a/hw/vendor/lowrisc_ibex/Makefile b/hw/vendor/lowrisc_ibex/Makefile
index 1d928a0..65f2d1b 100644
--- a/hw/vendor/lowrisc_ibex/Makefile
+++ b/hw/vendor/lowrisc_ibex/Makefile
@@ -1,3 +1,7 @@
+IBEX_CONFIG ?= small-3cmult
+
+FUSESOC_CONFIG_OPTS = $(shell ./util/ibex_config.py $(IBEX_CONFIG) fusesoc_opts)
+
all: help
.PHONY: help
@@ -15,7 +19,8 @@
.PHONY: build-riscv-compliance
build-riscv-compliance:
fusesoc --cores-root=. run --target=sim --setup --build \
- lowrisc:ibex:ibex_riscv_compliance
+ lowrisc:ibex:ibex_riscv_compliance \
+ $(FUSESOC_CONFIG_OPTS)
# Simple system
@@ -25,7 +30,8 @@
.PHONY: build-simple-system
build-simple-system:
fusesoc --cores-root=. run --target=sim --setup --build \
- lowrisc:ibex:ibex_simple_system
+ lowrisc:ibex:ibex_simple_system \
+ $(FUSESOC_CONFIG_OPTS)
simple-system-program = examples/sw/simple_system/hello_test/hello_test.vmem
sw-simple-hello: $(simple-system-program)
@@ -77,7 +83,8 @@
# Lint check
.PHONY: lint-core-tracing
lint-core-tracing:
- fusesoc --cores-root . run --target=lint lowrisc:ibex:ibex_core_tracing
+ fusesoc --cores-root . run --target=lint lowrisc:ibex:ibex_core_tracing \
+ $(FUSESOC_CONFIG_OPTS)
# CS Registers testbench
@@ -99,3 +106,8 @@
run-csr-test: | $(Vtb_cs_registers)
fusesoc --cores-root=. run --target=sim --run \
--tool=verilator lowrisc:ibex:tb_cs_registers
+
+# Echo the parameters passed to fusesoc for the chosen IBEX_CONFIG
+.PHONY: test-cfg
+test-cfg:
+ @echo $(FUSESOC_CONFIG_OPTS)
diff --git a/hw/vendor/lowrisc_ibex/azure-pipelines.yml b/hw/vendor/lowrisc_ibex/azure-pipelines.yml
index 2dfc500..921d892 100644
--- a/hw/vendor/lowrisc_ibex/azure-pipelines.yml
+++ b/hw/vendor/lowrisc_ibex/azure-pipelines.yml
@@ -8,15 +8,22 @@
variables:
VERILATOR_VERSION: 4.028
VERILATOR_PATH: /opt/buildcache/verilator/$(VERILATOR_VERSION)
- RISCV_TOOLCHAIN_TAR_VERSION: 20190807-1
+ RISCV_TOOLCHAIN_TAR_VERSION: 20200323-1
RISCV_COMPLIANCE_GIT_VERSION: 844c6660ef3f0d9b96957991109dfd80cc4938e2
+ VERIBLE_VERSION: v0.0-266-g9e55307
trigger:
batch: true
branches:
-# Combine builds on master as long as another build is running
include:
- - master
+ - '*'
+ tags:
+ include:
+ - '*'
+pr:
+ branches:
+ include:
+ - '*'
# Note: All tests run as part of one job to avoid copying intermediate build
# artifacts around (e.g. Verilator and toolchain builds). Once more builds/tests
@@ -55,11 +62,21 @@
libelf-dev \
clang-format \
&& sudo pip3 install -U setuptools pip six \
- && sudo pip3 install -U fusesoc
+ && sudo pip3 install -U -r python-requirements.txt
displayName: Install dependencies
- bash: |
set -e
+ mkdir -p build/verible
+ cd build/verible
+ curl -Ls -o verible.tar.gz https://github.com/google/verible/releases/download/$(VERIBLE_VERSION)/verible-$(VERIBLE_VERSION)-Ubuntu-16.04-xenial-x86_64.tar.gz
+ sudo mkdir -p /tools/verible && sudo chmod 777 /tools/verible
+ tar -C /tools/verible -xf verible.tar.gz --strip-components=1
+ echo "##vso[task.setvariable variable=PATH]/tools/verible/bin:$PATH"
+ displayName: Install Verible
+
+ - bash: |
+ set -e
if [ ! -d $(VERILATOR_PATH) ]; then
echo "Building verilator (no cached build found)"
mkdir -p build/verilator
@@ -93,20 +110,38 @@
fusesoc --version
verilator --version
riscv32-unknown-elf-gcc --version
+ verilog_lint --version
displayName: Display environment
+ # Verible lint/format is experimental so only run on default config for now,
+ # will eventually become part of the per-config CI
- bash: |
- fusesoc --cores-root . run --target=lint lowrisc:ibex:ibex_core_tracing
+ fusesoc --cores-root . run --no-export --target=lint --tool=veriblelint lowrisc:ibex:ibex_core_tracing
if [ $? != 0 ]; then
echo -n "##vso[task.logissue type=error]"
- echo "Verilog lint failed. Run 'fusesoc --cores-root . run --target=lint lowrisc:ibex:ibex_core_tracing' to check and fix all errors."
+ echo "Verilog lint with Verible failed. Run 'fusesoc --cores-root . run --target=lint --tool=veriblelint lowrisc:ibex:ibex_core_tracing' to check and fix all errors."
+ echo "This flow is currently experimental and failures can be ignored."
exit 1
fi
- displayName: Lint Verilog source files with Verilator
+ continueOnError: true
+ displayName: Lint Verilog source files with Verible (experimental)
+
+ - bash: |
+ fusesoc --cores-root . run --no-export --target=format --tool=veribleformat lowrisc:ibex:ibex_core_tracing
+ if [ $? != 0 ]; then
+ echo -n "##vso[task.logissue type=error]"
+ echo "Verilog format with Verible failed. Run 'fusesoc --cores-root . run --no-export --target=format --tool=veribleformat lowrisc:ibex:ibex_core_tracing' to check and fix all errors."
+ echo "This flow is currently experimental and failures can be ignored."
+ fi
+ # Show diff of what verilog_format would have changed, and then revert.
+ git diff
+ git reset --hard HEAD
+ continueOnError: true
+ displayName: Format all source code with Verible format (experimental)
- bash: |
fork_origin=$(git merge-base --fork-point origin/master)
- changed_files=$(git diff --name-only $fork_origin | grep -v /vendor/ | grep -E '\.(cpp|cc|c|h)$')
+ changed_files=$(git diff --name-only $fork_origin | grep -v '^vendor' | grep -E '\.(cpp|cc|c|h)$')
test -z "$changed_files" || git diff -U0 $fork_origin $changed_files | clang-format-diff -p1 | tee clang-format-output
if [ -s clang-format-output ]; then
echo -n "##vso[task.logissue type=error]"
@@ -119,7 +154,8 @@
displayName: 'Use clang-format to check C/C++ coding style'
- bash: |
- # Build and run CSR testbench
+ # Build and run CSR testbench, chosen Ibex configuration does not effect
+ # this so doesn't need to be part of per-config CI
fusesoc --cores-root=. run --target=sim --tool=verilator lowrisc:ibex:tb_cs_registers
displayName: Build and run CSR testbench with Verilator
@@ -130,37 +166,10 @@
git checkout "$(RISCV_COMPLIANCE_GIT_VERSION)"
displayName: Get RISC-V Compliance test suite
- - bash: |
- # Build simulation model of Ibex
- fusesoc --cores-root=. run --target=sim --setup --build lowrisc:ibex:ibex_riscv_compliance --RV32M=1 --RV32E=0
- if [ $? != 0 ]; then
- echo -n "##vso[task.logissue type=error]"
- echo "Unable to build Verilator model of Ibex for compliance testing."
- exit 1
- fi
-
- # Run compliance test suite
- export TARGET_SIM=$PWD/build/lowrisc_ibex_ibex_riscv_compliance_0.1/sim-verilator/Vibex_riscv_compliance
- export RISCV_PREFIX=riscv32-unknown-elf-
- export RISCV_TARGET=ibex
- export RISCV_DEVICE=rv32imc
- fail=0
- for isa in rv32i rv32im rv32imc rv32Zicsr rv32Zifencei; do
- make -C build/riscv-compliance RISCV_ISA=$isa 2>&1 | tee run.log
- if [ ${PIPESTATUS[0]} != 0 ]; then
- echo -n "##vso[task.logissue type=error]"
- echo "The RISC-V compliance test suite failed for $isa"
-
- # There's no easy way to get the test results in machine-readable
- # form to properly exclude known-failing tests. Going with an
- # approximate solution for now.
- if [ $isa == rv32i ] && grep -q 'FAIL: 4/48' run.log; then
- echo -n "##vso[task.logissue type=error]"
- echo "Expected failure for rv32i, see lowrisc/ibex#100 more more information."
- else
- fail=1
- fi
- fi
- done
- exit $fail
- displayName: "Run RISC-V Compliance test for Ibex RV32IMC"
+ # Run Ibex RTL CI per supported configuration
+ - template : ci/ibex-rtl-ci-steps.yml
+ parameters:
+ ibex_configs:
+ - small-3cmult
+ - experimental-maxperf-1cmult
+ - experimental-maxperf-bm-1cmult
diff --git a/hw/vendor/lowrisc_ibex/ci/ibex-rtl-ci-steps.yml b/hw/vendor/lowrisc_ibex/ci/ibex-rtl-ci-steps.yml
new file mode 100644
index 0000000..aed784d
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/ci/ibex-rtl-ci-steps.yml
@@ -0,0 +1,55 @@
+parameters:
+ ibex_configs: []
+
+steps:
+ - ${{ each config in parameters.ibex_configs }}:
+ # ibex_config.py will exit with error code 1 on any error which will cause
+ # the CI to fail if there's an issue with the configuration file or an
+ # incorrect configuration name being used
+ - bash: |
+ ./util/ibex_config.py ${{ config }} fusesoc_opts
+ displayName: Display fusesoc config for ${{ config }}
+
+ - bash: |
+ fusesoc --cores-root . run --target=lint lowrisc:ibex:ibex_core_tracing $(./util/ibex_config.py ${{ parameters.ibex_config }} fusesoc_opts)
+ if [ $? != 0 ]; then
+ echo -n "##vso[task.logissue type=error]"
+ echo "Verilog lint failed. Run 'fusesoc --cores-root . run --target=lint lowrisc:ibex:ibex_core_tracing' to check and fix all errors."
+ exit 1
+ fi
+ displayName: Lint Verilog source files with Verilator for ${{ config }}
+
+ - bash: |
+ # Build simulation model of Ibex
+ fusesoc --cores-root=. run --target=sim --setup --build lowrisc:ibex:ibex_riscv_compliance $(./util/ibex_config.py ${{ parameters.ibex_config }} fusesoc_opts)
+ if [ $? != 0 ]; then
+ echo -n "##vso[task.logissue type=error]"
+ echo "Unable to build Verilator model of Ibex for compliance testing."
+ exit 1
+ fi
+
+ # Run compliance test suite
+ export TARGET_SIM=$PWD/build/lowrisc_ibex_ibex_riscv_compliance_0.1/sim-verilator/Vibex_riscv_compliance
+ export RISCV_PREFIX=riscv32-unknown-elf-
+ export RISCV_TARGET=ibex
+ export RISCV_DEVICE=rv32imc
+ fail=0
+ for isa in rv32i rv32im rv32imc rv32Zicsr rv32Zifencei; do
+ make -C build/riscv-compliance RISCV_ISA=$isa 2>&1 | tee run.log
+ if [ ${PIPESTATUS[0]} != 0 ]; then
+ echo -n "##vso[task.logissue type=error]"
+ echo "The RISC-V compliance test suite failed for $isa"
+
+ # There's no easy way to get the test results in machine-readable
+ # form to properly exclude known-failing tests. Going with an
+ # approximate solution for now.
+ if [ $isa == rv32i ] && grep -q 'FAIL: 4/48' run.log; then
+ echo -n "##vso[task.logissue type=error]"
+ echo "Expected failure for rv32i, see lowrisc/ibex#100 more more information."
+ else
+ fail=1
+ fi
+ fi
+ done
+ exit $fail
+ displayName: Run RISC-V Compliance test for Ibex RV32IMC for ${{ config }}
diff --git a/hw/vendor/lowrisc_ibex/doc/concierge.rst b/hw/vendor/lowrisc_ibex/doc/concierge.rst
new file mode 100644
index 0000000..74efc59
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/doc/concierge.rst
@@ -0,0 +1,73 @@
+.. _concierge:
+
+The Ibex Concierge
+==================
+
+.. figure:: https://upload.wikimedia.org/wikipedia/commons/8/80/France_in_XXI_Century._Concierge.jpg
+
+The Ibex Concierge is the friendly caretaker of the Ibex project.
+It's a rotating duty shared by experienced contributors to help newcomers find their way around the project, and to stay on top of the various small tasks necessary to keep the project going.
+
+The Ibex CPU project is a reasonably large open source project.
+Like all projects we experience two challenges:
+we want to lend a helping hand to new developers, answering their questions or helping them with code contributions.
+And we need to stay on top of our "caretaker" tasks, like fixing problems with our continuous integration setup, triaging issues and pull requests, etc.
+The Ibex Concierge combines these two duties in one person.
+
+Please reach out to the Ibex Concierge if you have trouble finding your way around the Ibex project.
+You can find today's Ibex Concierge in the calendar below.
+
+
+Who is Ibex Concierge today?
+----------------------------
+
+The concierge duties rotate between several core developers on a weekly basis.
+You can find today's concierge on duty in a `public calendar <https://calendar.google.com/calendar/embed?src=lowrisc.org_s0pdodkddnggdp40jusjij27h4%40group.calendar.google.com>`_.
+
+* Greg Chadwick (`@GregAC <https://github.com/gregac>`_)
+* Tom Roberts (`@tomroberts-lowrisc <https://github.com/tomroberts-lowrisc>`_)
+* Rupert Swarbrick (`@rswarbrick <https://github.com/rswarbrick>`_)
+* Pirmin Vogel (`@vogelpi <https://github.com/vogelpi>`_)
+* Philipp Wagner (`@imphil <https://github.com/imphil>`_)
+
+You can be Ibex Concierge, too.
+Please talk to any of the current concierges to discuss!
+
+.. raw:: html
+
+ <iframe src="https://calendar.google.com/calendar/embed?src=lowrisc.org_s0pdodkddnggdp40jusjij27h4%40group.calendar.google.com" style="border: 0" width="100%" height="600" frameborder="0" scrolling="no"></iframe>
+
+
+Ibex Concierge duties
+---------------------
+
+The Ibex Concierge is aware of what's happening in the Ibex project, and helps to ensure that everyone feels welcome and is able to work productively.
+The list of duties includes, but isn't strictly limited to the following tasks.
+
+* Triage incoming issues and pull requests.
+
+ * Assign labels to them.
+
+ * Give initial feedback with an indication of what the next steps are.
+
+ * Answer questions if possible.
+
+ * Ask for clarifications where necessary.
+
+ * Redirect to the right developers as needed.
+
+* Track progress of open issues and pull requests.
+ Ensure contributors always know what's going on, and are informed if things take longer.
+
+* Welcome new contributors, and provide (hands-on) help to get them up to speed.
+ For example, help them get their commits into good shape, etc.
+
+* Fix or coordinate fixes to necessary infrastructure, such as the continuous integration setup in a timely manner.
+
+* Go through the list of open pull requests: ping developers if information or action is needed, close abandoned pull requests, etc.
+
+* Assist with the review and update of open issues.
+
+* At the end of the week, hand over to the next Ibex Concierge on the rota.
+
+Note the obvious: it is not the job of the Ibex Concierge to fix all bugs, implement all incoming feature requests, or be available 24/7.
diff --git a/hw/vendor/lowrisc_ibex/doc/cs_registers.rst b/hw/vendor/lowrisc_ibex/doc/cs_registers.rst
index fdeb610..814d3e8 100644
--- a/hw/vendor/lowrisc_ibex/doc/cs_registers.rst
+++ b/hw/vendor/lowrisc_ibex/doc/cs_registers.rst
@@ -66,6 +66,8 @@
+---------+--------------------+--------+-----------------------------------------------+
| 0x7B3 | ``dscratch1`` | RW | Debug Scratch Register 1 |
+---------+--------------------+--------+-----------------------------------------------+
+| 0x7C0 | ``cpuctrl`` | RW | CPU Control Register (Custom CSR) |
++---------+--------------------+--------+-----------------------------------------------+
| 0xB00 | ``mcycle`` | RW | Machine Cycle Counter |
+---------+--------------------+--------+-----------------------------------------------+
| 0xB02 | ``minstret`` | RW | Machine Instructions-Retired Counter |
@@ -483,6 +485,26 @@
Scratch register to be used by the debug module.
Accessible in Debug Mode only.
+CPU Control Register (cpuctrl)
+------------------------------
+
+CSR Address: ``0x7C0``
+
+Reset Value: ``0x0000_0000``
+
+Custom CSR to control runtime configuration of CPU components.
+Accessible in Machine Mode only.
+Ibex implements the following bit fields.
+Other bit fields read as zero.
+
++-------+------+------------------------------------------------------------------+
+| Bit# | R/W | Description |
++-------+------+------------------------------------------------------------------+
+| 0 | WARL | **icache_enable:** Enable (1) or disable (0) the instruction |
+| | | cache. If the instruction cache has not been configured (ICache |
+| | | parameter == 0), this field will always read as zero. |
++-------+------+------------------------------------------------------------------+
+
Time Registers (time(h))
------------------------
diff --git a/hw/vendor/lowrisc_ibex/doc/icache.rst b/hw/vendor/lowrisc_ibex/doc/icache.rst
new file mode 100644
index 0000000..3e4f63c
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/doc/icache.rst
@@ -0,0 +1,261 @@
+.. _icache:
+
+Instruction Cache
+=================
+:file:`rtl/ibex_icache.sv.`
+
+NOTE - This module is currently DRAFT
+
+The optional Instruction Cache (I$) is designed to improve CPU performance in systems with high instruction memory latency.
+The I$ integrates into the CPU by replacing the prefetch buffer, interfacing directly between the bus and IF stage.
+
+High-level operation
+--------------------
+
+The I$ passes instructions to the core using a ready / valid interface.
+Inside the cache is an address counter, which increments for every instruction fetched (by 2 or 4 bytes, depending on whether the instruction contents show it to be compressed).
+When the core takes a branch, it resets the counter to a new address by raising the ``branch_i`` signal and supplying the new address on ``addr_i``.
+The next instruction returned by the cache will be the instruction at this new address.
+
+The I$ communicates with instruction memory using an interface that matches the IF stage (allowing the cache to be enabled or disabled without needing to change the Ibex toplevel's interface). For more details of this interface, see :ref:`instruction-fetch`.
+
+To avoid the cache fetching needlessly when the core is asleep (after a ``wfi`` instruction), it has a ``req_i`` input. Shortly after this goes low, the cache will stop making memory transactions.
+
+If the ``icache_enable_i`` input is low, the cache operates in pass-through mode, where every requested instruction is fetched from memory and no results are cached.
+
+In order to invalidate the cache, the core can raise the ``icache_inval_i`` line for one or more cycles, which will start an internal cache invalidation.
+No fetches are cached while the invalidation is taking place (behaving as if ``icache_enable_i`` is low).
+
+While the I$ is busy, either (pre)fetching data or invalidating its memory, it raises the ``busy_o`` signal.
+This can be used to avoid the cache's clock being gated when it is doing something.
+
+
+Configuration options
+---------------------
+
+The following table describes the available configuration parameters.
+
++-------------------------+-----------+-----------------------------------------------+
+| Parameter | Default | Description |
++=========================+===========+===============================================+
+| ``BusWidth`` | ``32`` | Width of instruction bus. Note, this is fixed |
+| | | at 32 for Ibex at the moment. |
++-------------------------+-----------+-----------------------------------------------+
+| ``CacheSizeBytes`` | ``4kB`` | Size of cache in bytes. |
++-------------------------+-----------+-----------------------------------------------+
+| ``CacheECC`` | ``1'b0`` | Enable SECDED ECC protection in tag and data |
+| | | RAMs. |
++-------------------------+-----------+-----------------------------------------------+
+| ``LineSize`` | ``64`` | The width of one cache line in bits. |
+| | | Line sizes smaller than 64 bits may give |
+| | | compilation errors. |
++-------------------------+-----------+-----------------------------------------------+
+| ``NumWays`` | ``2`` | The number of ways. |
++-------------------------+-----------+-----------------------------------------------+
+| ``SpecRequest`` | ``1'b0`` | When set, the system will attempt to |
+| | | speculatively request data from memory in |
+| | | parallel with the cache lookup. This can give |
+| | | improved performance for workloads which |
+| | | cache poorly (at the expense of power). |
+| | | When not set, only branches will make |
+| | | speculative requests. |
++-------------------------+-----------+-----------------------------------------------+
+| ``BranchCache`` | ``1'b0`` | When set, the cache will only allocate the |
+| | | targets of branches + two subsequent cache |
+| | | lines. This gives improved performance in |
+| | | systems with moderate latency by not |
+| | | polluting the cache with data that can be |
+| | | prefetched instead. |
+| | | When not set, all misses are allocated. |
++-------------------------+-----------+-----------------------------------------------+
+
+Performance notes
+-----------------
+
+Note that although larger cache line sizes allow for better area efficiency (lower tagram area overhead), there is a performance penalty.
+When the core branches to an address that is not aligned to the bottom of a cache line (and the request misses in the cache), the I$ will attempt to fetch this address first from the bus.
+The I$ will then fetch the rest of the remaining beats of data in wrapping address order to complete the cache line (in order to allocate it to the cache).
+While these lower addresses are being fetched, the core is starved of data.
+Based on current experimental results, a line size of 64 bits gives the best performance.
+
+In cases where the core branches to addresses currently being prefetched, the same line can end up allocated to the cache in multiple ways.
+This causes a minor performance inefficiency, but should not happen often in practice.
+
+RAM Arrangement
+---------------
+
+The data RAMs are arranged as ``NumWays`` banks of ``LineSize`` width.
+If ECC is configured, the tag and data banks will be wider to accomodate the extra checkbits.
+
+Indicative RAM sizes for common configurations are given in the table below:
+
++------------------------------+-----------------+------------------+
+| Cache config | Tag RAMs | Data RAMs |
++==============================+=================+==================+
+| 4kB, 2 way, 64bit line | 2 x 256 x 22bit | 2 x 256 x 64bit |
++------------------------------+-----------------+------------------+
+| 4kB, 2 way, 64bit line w/ECC | 2 x 256 x 28bit | 2 x 256 x 72bit |
++------------------------------+-----------------+------------------+
+| 4kB, 2 way, 128bit line | 2 x 128 x 22bit | 2 x 128 x 128bit |
++------------------------------+-----------------+------------------+
+| 4kB, 4 way, 64bit line | 4 x 128 x 22bit | 4 x 128 x 64bit |
++------------------------------+-----------------+------------------+
+
+Sub Unit Description
+--------------------
+
+.. figure:: images/icache_block.svg
+ :name: icache_block
+ :align: center
+
+ Instruction Cache Block Diagram
+
+Prefetch Address
+^^^^^^^^^^^^^^^^
+
+The prefetch address is updated to the branch target on every branch.
+This address is then updated in cache-line increments each time a cache lookup is issued to the cache pipeline.
+
+Cache Pipeline
+^^^^^^^^^^^^^^
+
+The cache pipeline consists of two stages, IC0 and IC1.
+
+In IC0, lookup requests are arbitrated against cache allocation requests.
+Lookup requests have highest priority since they naturally throttle themselves as fill buffer resources run out.
+The arbitrated request is made to the RAMs in IC0.
+
+In IC1, data from the RAMs are available and the cache hit status is determined.
+Hit data is multiplexed from the data RAMs based on the hitting way.
+If there was a cache miss, the victim way is chosen pseudo-randomly using a counter.
+
+Fill buffers
+^^^^^^^^^^^^
+
+The fill buffers perform several functions in the I$ and constitute most of it's complexity.
+
+* Since external requests can be made speculatively in parallel with the cache lookup, a fill buffer must be allocated in IC0 to track the request.
+* The fill buffers are used as data storage for hitting requests as well as for miss tracking so all lookup requests require a fill buffer.
+* A fill buffer makes multiple external requests to memory to fetch the required data to fill a cache line (tracked via ``fill_ext_cnt_q``).
+* Returning data is tracked via ``fill_rvd_cnt_q``.
+ Not all requests will fetch all their data, since requests can be cancelled due to a cache hit or an intervening branch.
+* If a fill buffer has not made any external requests it will be cancelled by an intervening branch, if it has made requests then the requests will be completed and the line allocated.
+* Beats of data are supplied to the IF stage, tracked via ``fill_out_cnt_q``.
+* If the line is due to be allocated into the cache, it will request for arbitration once all data has been received.
+* Once all required actions are complete, the fill buffer releases and becomes available for a new request.
+
+Since requests can perform actions out of order (cache hit in the shadow of an outstanding miss), and multiple requests can complete at the same time, the fill buffers are not a simple FIFO.
+Each fill buffer maintains a matrix of which requests are older than it, and this is used for arbitrating between the fill buffers.
+
+Data output
+^^^^^^^^^^^
+
+.. figure:: images/icache_mux.svg
+ :name: icache_mux
+ :align: center
+
+ Instruction Cache Data Multiplexing
+
+Data supplied to the IF stage are multiplexed between cache-hit data, fill buffer data, and incoming memory data.
+The fill buffers track which request should supply data, and where that data should come from.
+Data from the cache and the fill buffers are of cache line width, which is multiplexed down to 32 bits and then multiplexed against data from the bus.
+
+The fill buffers attempt to supply the relevant word of data to the IF stage as soon as possible.
+Hitting requests will supply the first word directly from the RAMs in IC1 while demand misses will supply data directly from the bus.
+The remaining data from hits is buffered in the fill buffer data storage and supplied to the IF stage as-required.
+
+To deal with misalignment caused by compressed instructions, there is a 16bit skid buffer to store the upper halfword.
+
+Cache ECC protection
+^^^^^^^^^^^^^^^^^^^^
+
+When ECC protection is enabled, extra checkbits are appended to the top of the tag and data RAM write data as follows:
+
+For the Tag RAMs (4kB cache):
+
++---------------+-----------+--------+
+| ECC checkbits | Valid bit | Tag |
++---------------+-----------+--------+
+| [27:22] | [21] | [20:0] |
++---------------+-----------+--------+
+
+For the Data RAMs (64bit line):
+
++---------------+--------+
+| ECC checkbits | Data |
++---------------+--------+
+| [71:64] | [63:0] |
++---------------+--------+
+
+The checkbits are generated by dedicated modules in IC0 before the RAMs are written.
+In IC1, the RAM read data and checkbits are fed into dedicated modules which output whether there was an error.
+Although the modules used have the required outputs to allow inline correction of single bit errors, the I$ does not make use of them since it never performs corrections.
+
+Any error (single or double bit) in any RAM will effectively cancel a cache hit in IC1.
+The request which observed an error will fetch it's data from the main instruction memory as normal for a cache miss.
+The cache index and way (or ways) with errors are stored in IC1, and a cache write is forced the next cycle to invalidate that line.
+Lookup requests will be blocked in IC0 while the invalidation write is performed.
+
+Cache invalidation
+^^^^^^^^^^^^^^^^^^
+
+After reset, and when requested by the core (due to a FENCE.I instruction), the whole cache is invalidated.
+Requests are inserted to invalidate the tag RAM for all ways in each cache line in sequence.
+While the invalidation is in-progress, lookups and instruction fetches can proceed, but nothing will be allocated to the cache.
+
+Detailed behaviour
+^^^^^^^^^^^^^^^^^^
+
+This section describes the expected behaviour of the cache, in order to allow functional verification.
+This isn't an attempt to describe the cache's performance characteristics.
+
+The I$ has a single clock (``clk_i``) and asynchronous reset (``rst_ni``).
+
+Data is requested from the instruction memory with the ports prefixed by ``instr_``. These work as described in :ref:`instruction-fetch`.
+Note that there's one extra port on the I$, which doesn't appear at the ``ibex_core`` top-level.
+This is ``instr_pmp_err_i``.
+If the PMP block disallows a fetch for a certain address, it will squash the outgoing memory request entirely and set ``instr_pmp_err_i``.
+If that happens, the cache drops ``instr_req_o`` and stops making any further requests for that cache line.
+Note that it is possible for ``instr_gnt_i`` and ``instr_pmp_err_i`` to be high on the same cycle.
+In that case, the error signal takes precedence.
+
+Fetched instructions are returned to the core using ports ``ready_i``, ``valid_o``, ``rdata_o``, ``addr_o`` and ``err_o``.
+This interface uses ready/valid handshaking in the usual way (a transaction is signalled by ready and valid being high; if valid goes high, it will remain high and the other output signals will remain stable until the transaction goes through).
+The one exception is if ``branch_i`` is asserted, which will cause ``valid_o`` to de-assert.
+The 32-bit wide ``rdata_o`` signal contains instruction data fetched from ``addr_o``.
+If there is a compressed instruction in the lower 16 bits, the upper 16 bits are unconstrained.
+This allows fetching an instruction from the top 16 bits of a memory, for example.
+The ``err_o`` signal will be high if the instruction fetch failed (either with ``instr_pmp_err_i`` or ``instr_err_i``); in this case ``rdata_o`` is not specified.
+
+The ``req_i`` signal tells the cache that the core is awake and will start requesting instructions soon.
+As well as the main cache memory, the I$ contains a prefetch buffer.
+The cache fills this buffer by issuing fetches when ``req_i`` is high.
+If ``req_i`` becomes false, the cache may do a few more instruction fetches to fill a cache line, but will stop fetching when that is done.
+The cache will not do any instruction fetches after this until ``req_i`` goes high again.
+A correctly behaving core should not not assert ``ready_i`` when ``req_i`` is low.
+
+Inside the cache is an address counter.
+If ``branch_i`` is asserted then the address counter will be set to ``addr_i`` and the next instruction that is passed to the core will be the one fetched from that address.
+The cache will also start reading into a new prefetch buffer, storing the current contents into the main cache memory or discarding it (see ``icache_enable_i`` below).
+On other cycles, the address counter will be incremented every time an instruction is passed to the core.
+This increment depends on the instruction data (visible at ``rdata_o``): if the bottom bits of the instruction are not ``2'b11``, the instruction is considered to be compressed and the address will be incremented by 2.
+If the bottom bits of the instruction are ``2'b11`` then the instruction is considered to be uncompressed and the address will be incremented by 4.
+Since the contents of ``rdata_o`` are not specified if an instruction fetch has caused an error, the core must signal a branch before accepting another instruction after it sees ``err_o``.
+
+Because a single instruction can span two 32bit memory addresses, an extra signal (``err_plus2_o``) indicates when an error is caused by the second half of an unaligned uncompressed instruction.
+This signal is only valid when ``valid_o`` and ``err_o`` are set, and will only be set for uncompressed instructions.
+The core uses this signal to record the correct address in the ``mtval`` CSR upon an error.
+
+Since the address counter is not initialised on reset, the behaviour of the I$ is unspecified unless ``branch_i`` is asserted on or before the first cycle that ``req_i`` is asserted after reset.
+If that is not true, there's nothing to stop the cache fetching from random addresses.
+
+The ``icache_enable_i`` signal controls whether the cache copies fetched data from the prefetch buffer to the main cache memory.
+If the signal is false, fetched data will be discarded on a branch or after enough instructions have been consumed by the core.
+On reset, or whenever ``icache_inval_i`` goes high, the cache will invalidate its stored data.
+While doing this, the cache behaves as if ``icache_enable_i`` is false and will not store any fetched data.
+
+.. note::
+ The rules for ``icache_enable_i`` and ``icache_inval_i`` mean that, in order to be completely sure of executing newly fetched code, the core should raise the ``icache_inval_i`` line for at least a cycle and then should branch. The Ibex core does this in response to a ``FENCE.I`` instruction, branching explicitly to the next PC.
+
+The ``busy_o`` signal is guaranteed to be high while the cache is invalidating its internal memories or whenever it has a pending fetch on the instruction bus.
+When the ``busy_o`` signal is low, it is safe to clock gate the cache.
diff --git a/hw/vendor/lowrisc_ibex/doc/images/icache_block.svg b/hw/vendor/lowrisc_ibex/doc/images/icache_block.svg
new file mode 100644
index 0000000..9106dc1
--- /dev/null
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diff --git a/hw/vendor/lowrisc_ibex/doc/index.rst b/hw/vendor/lowrisc_ibex/doc/index.rst
index 31dec10..c9350db 100644
--- a/hw/vendor/lowrisc_ibex/doc/index.rst
+++ b/hw/vendor/lowrisc_ibex/doc/index.rst
@@ -12,6 +12,7 @@
pipeline_details
instruction_fetch
instruction_decode_execute
+ icache
load_store_unit
register_file
cs_registers
@@ -23,6 +24,7 @@
rvfi
verification
examples
+ concierge
.. toctree::
diff --git a/hw/vendor/lowrisc_ibex/doc/instruction_decode_execute.rst b/hw/vendor/lowrisc_ibex/doc/instruction_decode_execute.rst
index 0d1be09..920edc4 100644
--- a/hw/vendor/lowrisc_ibex/doc/instruction_decode_execute.rst
+++ b/hw/vendor/lowrisc_ibex/doc/instruction_decode_execute.rst
@@ -64,6 +64,11 @@
* It computes memory addresses for loads and stores with a Reg + Imm calculation
* The LSU uses it to increment addresses when performing two accesses to handle an unaligned access
+Support for the RISC-V Bitmanipulation Extension is enabled via the parameter ``RV32B``.
+This feature is *EXPERIMENTAL* and the details of its impact are not yet documented here.
+Currently only the Zbb base extension is implemented.
+All instructions are carried out in a single clock cycle.
+
.. _mult-div:
Multiplier/Divider Block (MULT/DIV)
diff --git a/hw/vendor/lowrisc_ibex/doc/instruction_fetch.rst b/hw/vendor/lowrisc_ibex/doc/instruction_fetch.rst
index 82f0e62..e160c23 100644
--- a/hw/vendor/lowrisc_ibex/doc/instruction_fetch.rst
+++ b/hw/vendor/lowrisc_ibex/doc/instruction_fetch.rst
@@ -21,6 +21,11 @@
The top-level of the instruction fetch controls the prefetch buffer (in particular flushing it on branches/jumps/exception and beginning prefetching from the appropriate new PC) and supplies new instructions to the ID/EX stage along with their PC.
Compressed instructions are expanded by the IF stage so the decoder can always deal with uncompressed instructions (the ID stage still receives the compressed instruction for placing into ``mtval`` on an illegal instruction exception).
+If Ibex has been configured with an instruction cache (parameter ICache == 1), then the prefetch buffer is replaced by the icache module (:ref:`icache`).
+The interfaces of the icache module are the same as the prefetch buffer with two additions.
+Firstly, a signal to enable the cache which is driven from a custom CSR.
+Secondly a signal to the flush the cache which is set every time a ``fence.i`` instruction is executed.
+
Instruction-Side Memory Interface
---------------------------------
diff --git a/hw/vendor/lowrisc_ibex/doc/integration.rst b/hw/vendor/lowrisc_ibex/doc/integration.rst
index 8e2828a..59e6f55 100644
--- a/hw/vendor/lowrisc_ibex/doc/integration.rst
+++ b/hw/vendor/lowrisc_ibex/doc/integration.rst
@@ -19,7 +19,10 @@
.MHPMCounterWidth ( 40 ),
.RV32E ( 0 ),
.RV32M ( 1 ),
+ .RV32B ( 0 ),
.MultiplierImplementation ( "fast" ),
+ .ICache ( 0 ),
+ .ICacheECC ( 0 ),
.DbgTriggerEn ( 0 ),
.DmHaltAddr ( 32'h1A110800 ),
.DmExceptionAddr ( 32'h1A110808 )
@@ -87,14 +90,26 @@
+------------------------------+-------------+------------+-----------------------------------------------------------------+
| ``RV32M`` | bit | 1 | M(ultiply) extension enable |
+------------------------------+-------------+------------+-----------------------------------------------------------------+
+| ``RV32B`` | bit | 0 | *EXPERIMENTAL* - B(itmanipulation) extension enable: |
+| | | | Currently supported Z-extensions: Zbb (base) |
++------------------------------+-------------+------------+-----------------------------------------------------------------+
| ``BranchTargetALU`` | bit | 0 | *EXPERIMENTAL* - Enables branch target ALU removing a stall |
| | | | cycle from taken branches |
+------------------------------+-------------+------------+-----------------------------------------------------------------+
+| ``WritebackStage`` | bit | 0 | *EXPERIMENTAL* - Enables third pipeline stage (writeback) |
+| | | | improving performance of loads and stores |
++------------------------------+-------------+------------+-----------------------------------------------------------------+
| ``MultiplierImplementation`` | string | "fast" | Multiplicator type: |
| | | | "slow": multi-cycle slow, |
| | | | "fast": multi-cycle fast, |
| | | | "single-cycle": single-cycle |
+------------------------------+-------------+------------+-----------------------------------------------------------------+
+| ``ICache`` | bit | 0 | *EXPERIMENTAL* Enable instruction cache instead of prefetch |
+| | | | buffer |
++------------------------------+-------------+------------+-----------------------------------------------------------------+
+| ``ICacheECC`` | bit | 0 | *EXPERIMENTAL* Enable SECDED ECC protection in ICache (if |
+| | | | ICache == 1) |
++------------------------------+-------------+------------+-----------------------------------------------------------------+
| ``DbgTriggerEn`` | bit | 0 | Enable debug trigger support (one trigger only) |
+------------------------------+-------------+------------+-----------------------------------------------------------------+
| ``DmHaltAddr`` | int | 0x1A110800 | Address to jump to when entering Debug Mode |
diff --git a/hw/vendor/lowrisc_ibex/doc/introduction.rst b/hw/vendor/lowrisc_ibex/doc/introduction.rst
index cdfb43e..e0d8c0c 100644
--- a/hw/vendor/lowrisc_ibex/doc/introduction.rst
+++ b/hw/vendor/lowrisc_ibex/doc/introduction.rst
@@ -84,6 +84,7 @@
* :ref:`pipeline-details` described the overal pipeline structure.
* :ref:`instruction-decode-execute` describes how the Instruction Decode and Execute stage works.
* The instruction and data interfaces of Ibex are explained in :ref:`instruction-fetch` and :ref:`load-store-unit`, respectively.
+ * :ref:`icache` describes the optional Instruction Cache.
* The two register-file flavors are described in :ref:`register-file`.
* The control and status registers are explained in :ref:`cs-registers`.
* :ref:`performance-counters` gives an overview of the performance monitors and event counters available in Ibex.
diff --git a/hw/vendor/lowrisc_ibex/doc/performance_counters.rst b/hw/vendor/lowrisc_ibex/doc/performance_counters.rst
index fb4c1fb..d0ace8c 100644
--- a/hw/vendor/lowrisc_ibex/doc/performance_counters.rst
+++ b/hw/vendor/lowrisc_ibex/doc/performance_counters.rst
@@ -41,6 +41,10 @@
+--------------+------------------+---------------------------------------------------------+
| 10 | NumInstrRetC | Number of compressed instructions retired |
+--------------+------------------+---------------------------------------------------------+
+| 11 | NumCyclesMulWait | Cycles waiting for multiply to complete |
++--------------+------------------+---------------------------------------------------------+
+| 12 | NumCyclesDivWait | Cycles waiting for divide to complete |
++--------------+------------------+---------------------------------------------------------+
The event selector CSRs ``mhpmevent3`` - ``mhpmevent31`` define which of these events are counted by the event counters ``mhpmcounter3(h)`` - ``mhpmcounter31(h)``.
If a specific bit in an event selector CSR is set to 1, this means that events with this ID are being counted by the counter associated with that selector CSR.
@@ -99,6 +103,10 @@
+----------------------+----------------+--------------+------------------+
| ``mhpmcounter10(h)`` | 0xB0A (0xB8A) | 10 | NumInstrRetC |
+----------------------+----------------+--------------+------------------+
+| ``mhpmcounter11(h)`` | 0xB0B (0xB8B) | 11 | NumCyclesMulWait |
++----------------------+----------------+--------------+------------------+
+| ``mhpmcounter12(h)`` | 0xB0C (0xB8C) | 12 | NumCyclesDivWait |
++----------------------+----------------+--------------+------------------+
Similarly, the event selector CSRs are hardwired as follows.
The remaining event selector CSRs are tied to 0, i.e., no events are counted by the corresponding counters.
diff --git a/hw/vendor/lowrisc_ibex/doc/pipeline_details.rst b/hw/vendor/lowrisc_ibex/doc/pipeline_details.rst
index cb2a302..f08d930 100644
--- a/hw/vendor/lowrisc_ibex/doc/pipeline_details.rst
+++ b/hw/vendor/lowrisc_ibex/doc/pipeline_details.rst
@@ -23,6 +23,12 @@
This means the maximum IPC (Instructions per Cycle) Ibex can achieve is 1 when multi-cycle instructions aren't used.
See Multi- and Single-Cycle Instructions below for the details.
+Third Pipeline Stage
+--------------------
+Ibex can be configured to have a third pipeline stage (Writeback) which has major effects on performance and instruction behaviour.
+This feature is *EXPERIMENTAL* and the details of its impact are not yet documented here.
+All of the information presented below applies only to the two stage pipeline provided in the default configurations.
+
Multi- and Single-Cycle Instructions
------------------------------------
diff --git a/hw/vendor/lowrisc_ibex/doc/pmp.rst b/hw/vendor/lowrisc_ibex/doc/pmp.rst
index eaa69b4..fc8a246 100644
--- a/hw/vendor/lowrisc_ibex/doc/pmp.rst
+++ b/hw/vendor/lowrisc_ibex/doc/pmp.rst
@@ -6,15 +6,15 @@
The Physical Memory Protection (PMP) unit implements region-based memory access checking in-accordance with the RISC-V Privileged Specification, version 1.11.
The following configuration parameters are available to control PMP checking:
-+----------------+---------------+-------------------------------------------------+
-| Parameter | Default value | Description |
-+================+===============+=================================================+
-| PMPEnable | 0 | PMP support enabled |
-+----------------+---------------+-------------------------------------------------+
-| PMPNumRegions | 4 | Number of implemented regions (1 - 16) |
-+----------------+---------------+-------------------------------------------------+
-| PMPGranularity | 0 | Minimum match granularity 2^G\+2 bytes (0 - 31) |
-+----------------+---------------+-------------------------------------------------+
++----------------+---------------+----------------------------------------------------------+
+| Parameter | Default value | Description |
++================+===============+==========================================================+
+| PMPEnable | 0 | PMP support enabled |
++----------------+---------------+----------------------------------------------------------+
+| PMPNumRegions | 4 | Number of implemented regions (1 - 16) |
++----------------+---------------+----------------------------------------------------------+
+| PMPGranularity | 0 | Minimum match granularity :math:`2^{G+2}` bytes (0 - 31) |
++----------------+---------------+----------------------------------------------------------+
When PMPEnable is zero, the PMP module is not instantiated and all PMP registers read as zero (regardless of the value of PMPNumRegions)
@@ -30,4 +30,3 @@
The PMP granularity parameter is used to reduce the size of the address matching comparators by increasing the minimum region size.
When the granularity is greater than zero, NA4 mode is not available and will be treated as OFF mode.
-
diff --git a/hw/vendor/lowrisc_ibex/doc/verification.rst b/hw/vendor/lowrisc_ibex/doc/verification.rst
index 67e6aaa..4821f0b 100644
--- a/hw/vendor/lowrisc_ibex/doc/verification.rst
+++ b/hw/vendor/lowrisc_ibex/doc/verification.rst
@@ -1,17 +1,20 @@
Verification
============
-Overview
---------
+Ibex Core
+---------
-This is a SV/UVM testbench for verification of the Ibex core.
+Overview
+^^^^^^^^
+
+This is a SV/UVM testbench for verification of the Ibex core, located in `dv/uvm/core_ibex`.
At a high level, this testbench uses the open source `RISCV-DV random instruction generator
<https://github.com/google/riscv-dv>`_ to generate compiled instruction binaries, loads them into a
simple memory model, stimulates the Ibex core to run this program in memory, and then compares the
core trace log against a golden model ISS trace log to check for correctness of execution.
Testbench Architecture
-----------------------
+^^^^^^^^^^^^^^^^^^^^^^
As previously mentioned, this testbench has been constructed based on its usage of the RISCV-DV
random instruction generator developed by Google.
@@ -23,28 +26,28 @@
Architecture of the UVM testbench for Ibex core
Memory Interface Agents
-~~~~~~~~~~~~~~~~~~~~~~~
+"""""""""""""""""""""""
-The code can be found in the `dv/uvm/common/ibex_mem_intf_agent
-<https://github.com/lowRISC/ibex/tree/master/dv/uvm/common/ibex_mem_intf_agent>`_ directory.
+The code can be found in the `dv/uvm/core_ibex/common/ibex_mem_intf_agent
+<https://github.com/lowRISC/ibex/tree/master/dv/uvm/core_ibex/common/ibex_mem_intf_agent>`_ directory.
Two of these agents are instantiated within the testbench, one for the instruction fetch interface,
and the second for the LSU interface.
These agents run slave sequences that wait for memory requests from the core, and then grant the
requests for instructions or for data.
Interrupt Interface Agent
-~~~~~~~~~~~~~~~~~~~~~~~~~
+"""""""""""""""""""""""""
The code can be found in the
-`dv/uvm/common/irq_agent <https://github.com/lowRISC/ibex/tree/master/dv/uvm/common/irq_agent>`_ directory.
+`dv/uvm/core_ibex/common/irq_agent <https://github.com/lowRISC/ibex/tree/master/dv/uvm/core_ibex/common/irq_agent>`_ directory.
This agent is used to drive stimulus onto the Ibex core's interrupt pins randomly during test
execution.
Memory Model
-~~~~~~~~~~~~
+""""""""""""
The code can be found in the
-`dv/uvm/common/mem_model <https://github.com/lowRISC/ibex/tree/master/dv/uvm/common/mem_model>`_
+`dv/uvm/core_ibex/common/mem_model <https://github.com/lowRISC/ibex/tree/master/dv/uvm/core_ibex/common/mem_model>`_
directory.
The testbench instantiates a single instance of this memory model that it loads the compiled
assembly test program into at the beginning of each test.
@@ -52,10 +55,10 @@
memory interface agents.
Test and Sequence Library
-~~~~~~~~~~~~~~~~~~~~~~~~~
+"""""""""""""""""""""""""
The code can be found in the
-`dv/uvm/tests <https://github.com/lowRISC/ibex/tree/master/dv/uvm/tests>`_ directory.
+`dv/uvm/core_ibex/tests <https://github.com/lowRISC/ibex/tree/master/dv/uvm/core_ibex/tests>`_ directory.
The tests here are the main sources of external stimulus generation and checking for this testbench,
as the memory interface slave sequences simply serve the core's memory requests.
The tests here are all extended from ``core_ibex_base_test``, and coordinate the entire flow for a
@@ -64,21 +67,21 @@
The sequences here are used to drive interrupt and debug stimulus into the core.
Testplan
-~~~~~~~~
+""""""""
The goal of this bench is to fully verify the Ibex core with 100%
coverage. This includes testing all RV32IMC instructions, privileged
spec compliance, exception and interrupt testing, Debug Mode operation etc.
-The complete test list can be found in the file `dv/uvm/riscv_dv_extension/testlist.yaml
-<https://github.com/lowRISC/ibex/blob/master/dv/uvm/riscv_dv_extension/testlist.yaml>`_.
+The complete test list can be found in the file `dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml
+<https://github.com/lowRISC/ibex/blob/master/dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml>`_.
Please note that verification is still a work in progress.
Getting Started
----------------
+^^^^^^^^^^^^^^
Prerequisites & Environment Setup
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+"""""""""""""""""""""""""""""""""
In order to run the co-simulation flow, you'll need:
@@ -119,7 +122,7 @@
.. _riscv-toolchain-releases: https://github.com/lowRISC/lowrisc-toolchains/releases
End-to-end RTL/ISS co-simulation flow
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+"""""""""""""""""""""""""""""""""""""
.. figure:: images/dv-flow.png
:alt: RTL/ISS co-simulation flow chart
@@ -143,12 +146,12 @@
This mechanism is explained in detail at https://github.com/google/riscv-dv/blob/master/HANDSHAKE.md.
As a sidenote, the signature address that this testbench uses for the handshaking is ``0x8ffffffc``.
Additionally, as is mentioned in the RISCV-DV documentation of this handshake, a small set of API
-tasks are provided in `dv/uvm/tests/core_ibex_base_test.sv
-<https://github.com/lowRISC/ibex/blob/master/dv/uvm/tests/core_ibex_base_tests.sv>`_ to enable easy
+tasks are provided in `dv/uvm/core_ibex/tests/core_ibex_base_test.sv
+<https://github.com/lowRISC/ibex/blob/master/dv/uvm/core_ibex/tests/core_ibex_base_tests.sv>`_ to enable easy
and efficient integration and usage of this mechanism in this test environment.
To see how this handshake is used during real simulations, look in
-`dv/uvm/tests/core_ibex_test_lib.sv
-<https://github.com/lowRISC/ibex/blob/master/dv/uvm/tests/core_ibex_test_lib.sv>`_.
+`dv/uvm/core_ibex/tests/core_ibex_test_lib.sv
+<https://github.com/lowRISC/ibex/blob/master/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv>`_.
As can be seen, this mechanism is extensively used to provide runtime verification for situations involving external debug
requests, interrupt assertions, and memory faults.
To add another layer of correctness checking to the checking already provided by the handshake
@@ -160,10 +163,12 @@
register state in the rest of the program.
The entirety of this flow is controlled by the Makefile found at
-`dv/uvm/Makefile <https://github.com/lowRISC/ibex/blob/master/dv/uvm/Makefile>`_; here is a list of frequently used commands:
+`dv/uvm/core_ibex/Makefile <https://github.com/lowRISC/ibex/blob/master/dv/uvm/core_ibex/Makefile>`_; here is a list of frequently used commands:
.. code-block:: bash
+ cd dv/uvm/core_ibex
+
# Run a full regression
make
@@ -201,12 +206,55 @@
make COV=1
Run with a different RTL simulator
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+""""""""""""""""""""""""""""""""""
-You can add any compile/runtime options in `dv/uvm/yaml/simulator.yaml
-<https://github.com/lowRISC/ibex/blob/master/dv/uvm/yaml/rtl_simulation.yaml>`_.
+You can add any compile/runtime options in `dv/uvm/core_ibex/yaml/simulator.yaml
+<https://github.com/lowRISC/ibex/blob/master/dv/uvm/core_ibex/yaml/rtl_simulation.yaml>`_.
.. code-block:: bash
# Use the new RTL simulator to run
make ... SIMULATOR=xxx
+
+
+Instruction Cache
+-----------------
+
+Overview
+^^^^^^^^
+
+NOTE: Icache verification, as well as documentation, is still in very early stages.
+
+Due to the complexity of the instruction cache, a separate testbench is used to
+ensure that full verification and coverage closure is performed on this module.
+This testbench is located at `dv/uvm/icache/dv
+<https://github.com/lowRISC/ibex/blob/master/dv/uvm/icache/dv>`_.
+
+As Icache verification is being carried out as part of the OpenTitan open-source
+project, the testbench derives from the `dv_lib UVM class library
+<https://github.com/lowRISC/opentitan/tree/master/hw/dv/sv/dv_lib>`_, which is a set of extended UVM
+classes that provides basic UVM testbench functionality and components.
+
+This DV environment will be compiled and simulated using the `dvsim simulation tool
+<https://github.com/lowRISC/opentitan/tree/master/util/dvsim>`_.
+The master ``.hjson`` file that controls simulation with ``dvsim`` can be found
+at `dv/uvm/icache/dv/ibex_icache_sim_cfg.hjson
+<https://github.com/lowRISC/ibex/blob/master/dv/uvm/icache/dv/ibex_icache_sim_cfg.hjson>`_.
+The associated testplan ``.hjson`` file is located at `dv/uvm/icache/data/ibex_icache_testplan.hjson
+<https://github.com/lowRISC/ibex/blob/master/dv/uvm/icache/data/ibex_icache_testplan.hjson>`_.
+As this testbench is still in its infancy, it is currently only able to be compiled, as no tests or
+sequences are implemented, nor are there any entries in the testplan file.
+To build the testbench locally using the VCS simulator, run the following command from the root of
+the Ibex repository:
+
+.. code-block:: bash
+
+ ./vendor/lowrisc_ip/dvsim/dvsim.py dv/uvm/icache/dv/ibex_icache_sim_cfg.hjson --build-only
+ --skip-ral --purge --sr sim_out
+
+Specify the intended output directory using either the ``--sr`` or ``-scratch-root`` option.
+The ``--skip-ral`` option is mandatory for building/simulating the Icache testbench, as it does not
+have any CSRs, excluding this option will lead to build errors.
+``--purge`` directs the tool to ``rm -rf`` the output directory before running the tool, this can be
+removed if not desired.
+
diff --git a/hw/vendor/lowrisc_ibex/dv/cs_registers/reg_driver/reg_dpi.cc b/hw/vendor/lowrisc_ibex/dv/cs_registers/reg_driver/reg_dpi.cc
index 284a0b0..70b9406 100644
--- a/hw/vendor/lowrisc_ibex/dv/cs_registers/reg_driver/reg_dpi.cc
+++ b/hw/vendor/lowrisc_ibex/dv/cs_registers/reg_driver/reg_dpi.cc
@@ -21,13 +21,13 @@
void reg_deregister_intf(std::string name) { intfs.erase(name); }
void monitor_tick(const char *name, svBit rst_n, svBit illegal_csr,
- svBit csr_access, const svBitVecVal *csr_op,
+ svBit csr_access, const svBitVecVal *csr_op, svBit csr_op_en,
const svBitVecVal *csr_addr, const svBitVecVal *csr_wdata,
const svBitVecVal *csr_rdata) {
auto ptr = intfs.find(name);
if (ptr != intfs.end()) {
// Send inputs to monitor
- if (csr_access || !rst_n) {
+ if ((csr_access && (csr_op_en || illegal_csr)) || !rst_n) {
ptr->second->CaptureTransaction(rst_n, illegal_csr, *csr_op, *csr_addr,
*csr_rdata, *csr_wdata);
}
@@ -35,13 +35,15 @@
}
void driver_tick(const char *name, svBit *csr_access, svBitVecVal *csr_op,
- svBitVecVal *csr_addr, svBitVecVal *csr_wdata) {
+ svBit *csr_op_en, svBitVecVal *csr_addr,
+ svBitVecVal *csr_wdata) {
auto ptr = intfs.find(name);
if (ptr != intfs.end()) {
// Call OnClock method
ptr->second->OnClock();
// Drive outputs
- ptr->second->DriveOutputs(csr_access, csr_op, csr_addr, csr_wdata);
+ ptr->second->DriveOutputs(csr_access, csr_op, csr_op_en, csr_addr,
+ csr_wdata);
}
}
diff --git a/hw/vendor/lowrisc_ibex/dv/cs_registers/reg_driver/reg_dpi.sv b/hw/vendor/lowrisc_ibex/dv/cs_registers/reg_driver/reg_dpi.sv
index 13449ec..02aa469 100644
--- a/hw/vendor/lowrisc_ibex/dv/cs_registers/reg_driver/reg_dpi.sv
+++ b/hw/vendor/lowrisc_ibex/dv/cs_registers/reg_driver/reg_dpi.sv
@@ -11,6 +11,7 @@
input bit illegal_csr,
input bit csr_access,
input bit [1:0] csr_op,
+ input bit csr_op_en,
input bit [11:0] csr_addr,
input bit [31:0] csr_wdata,
input bit [31:0] csr_rdata);
@@ -20,6 +21,7 @@
input string name,
output bit csr_access,
output bit [1:0] csr_op,
+ output bit csr_op_en,
output bit [11:0] csr_addr,
output bit [31:0] csr_wdata);
diff --git a/hw/vendor/lowrisc_ibex/dv/cs_registers/reg_driver/register_driver.cc b/hw/vendor/lowrisc_ibex/dv/cs_registers/reg_driver/register_driver.cc
index d8a5144..e9e7bcb 100644
--- a/hw/vendor/lowrisc_ibex/dv/cs_registers/reg_driver/register_driver.cc
+++ b/hw/vendor/lowrisc_ibex/dv/cs_registers/reg_driver/register_driver.cc
@@ -56,8 +56,10 @@
}
void RegisterDriver::DriveOutputs(unsigned char *access, uint32_t *op,
- uint32_t *addr, uint32_t *wdata) {
+ unsigned char *csr_op_en, uint32_t *addr,
+ uint32_t *wdata) {
*access = reg_access_;
+ *csr_op_en = reg_access_;
*op = next_transaction_.csr_op;
*addr = next_transaction_.csr_addr;
*wdata = next_transaction_.csr_wdata;
diff --git a/hw/vendor/lowrisc_ibex/dv/cs_registers/reg_driver/register_driver.h b/hw/vendor/lowrisc_ibex/dv/cs_registers/reg_driver/register_driver.h
index 61dc442..d1b6d6c 100644
--- a/hw/vendor/lowrisc_ibex/dv/cs_registers/reg_driver/register_driver.h
+++ b/hw/vendor/lowrisc_ibex/dv/cs_registers/reg_driver/register_driver.h
@@ -26,8 +26,8 @@
void CaptureTransaction(unsigned char rst_n, unsigned char illegal_csr,
uint32_t op, uint32_t addr, uint32_t rdata,
uint32_t wdata);
- void DriveOutputs(unsigned char *access, uint32_t *op, uint32_t *addr,
- uint32_t *wdata);
+ void DriveOutputs(unsigned char *access, uint32_t *op, unsigned char *op_en,
+ uint32_t *addr, uint32_t *wdata);
private:
void Randomize();
diff --git a/hw/vendor/lowrisc_ibex/dv/cs_registers/tb/tb_cs_registers.sv b/hw/vendor/lowrisc_ibex/dv/cs_registers/tb/tb_cs_registers.sv
index ea2893f..e427935 100644
--- a/hw/vendor/lowrisc_ibex/dv/cs_registers/tb/tb_cs_registers.sv
+++ b/hw/vendor/lowrisc_ibex/dv/cs_registers/tb/tb_cs_registers.sv
@@ -4,6 +4,7 @@
module tb_cs_registers #(
parameter bit DbgTriggerEn = 0,
+ parameter bit ICache = 0,
parameter int unsigned MHPMCounterNum = 8,
parameter int unsigned MHPMCounterWidth = 40,
parameter bit PMPEnable = 0,
@@ -38,6 +39,7 @@
ibex_pkg::csr_num_e csr_addr_i;
logic [31:0] csr_wdata_i;
ibex_pkg::csr_op_e csr_op_i;
+ logic csr_op_en_i;
logic [31:0] csr_rdata_o;
// interrupts
@@ -67,9 +69,13 @@
logic [31:0] pc_if_i;
logic [31:0] pc_id_i;
+ logic [31:0] pc_wb_i;
+
+ logic icache_enable_o;
logic csr_save_if_i;
logic csr_save_id_i;
+ logic csr_save_wb_i;
logic csr_restore_mret_i;
logic csr_restore_dret_i;
logic csr_save_cause_i;
@@ -83,14 +89,16 @@
// Performance Counters
logic instr_ret_i; // instr retired in ID/EX stage
logic instr_ret_compressed_i; // compressed instr retired
- logic imiss_i; // instr fetch
+ logic iside_wait_i; // core waiting for the iside
logic pc_set_i; // PC was set to a new value
logic jump_i; // jump instr seen (j, jr, jal, jalr)
logic branch_i; // branch instr seen (bf, bnf)
logic branch_taken_i; // branch was taken
logic mem_load_i; // load from memory in this cycle
logic mem_store_i; // store to memory in this cycle
- logic lsu_busy_i;
+ logic dside_wait_i; // core waiting for the dside
+ logic mul_wait_i;
+ logic div_wait_i;
//-----------------
// Reset generation
@@ -162,12 +170,14 @@
illegal_csr_insn_o,
csr_access_i,
csr_op_i,
+ csr_op_en_i,
csr_addr_i,
csr_wdata_i,
csr_rdata_o);
reg_dpi::driver_tick("reg_driver",
csr_access_i,
csr_op_i,
+ csr_op_en_i,
csr_addr_i,
csr_wdata_i);
end
diff --git a/hw/vendor/lowrisc_ibex/dv/riscv_compliance/ibex_riscv_compliance.core b/hw/vendor/lowrisc_ibex/dv/riscv_compliance/ibex_riscv_compliance.core
index f17ca31..f68a80d 100644
--- a/hw/vendor/lowrisc_ibex/dv/riscv_compliance/ibex_riscv_compliance.core
+++ b/hw/vendor/lowrisc_ibex/dv/riscv_compliance/ibex_riscv_compliance.core
@@ -25,20 +25,35 @@
parameters:
RV32M:
- datatype: int
+ datatype: bool
paramtype: vlogparam
- default: 1
- description: Enable the M ISA extension (hardware multiply/divide) [0/1]
+ default: true
+ description: Enable the M ISA extension (hardware multiply/divide)
RV32E:
- datatype: int
+ datatype: bool
paramtype: vlogparam
- default: 0
- description: Enable the E ISA extension (reduced register set) [0/1]
+ default: false
+ description: Enable the E ISA extension (reduced register set)
+ RV32B:
+ datatype: bool
+ paramtype: vlogparam
+ default: false
+ description: Enable the B ISA extension (bit manipulation EXPERIMENTAL)
+ MultiplierImplementation:
+ datatype: str
+ paramtype: vlogparam
+ description: "Multiplier implementation. Valid values: fast, slow, single-cycle"
+ default: "fast"
BranchTargetALU:
- datatype: int
+ datatype: bool
paramtype: vlogparam
- default: 0
- description: Enables seperate branch target ALU (increasing branch performance EXPERIMENTAL) [0/1]
+ default: false
+ description: Enables seperate branch target ALU (increasing branch performance EXPERIMENTAL)
+ WritebackStage:
+ datatype: bool
+ paramtype: vlogparam
+ default: false
+ description: Enables third pipeline stage (EXPERIMENTAL)
targets:
sim:
@@ -49,7 +64,9 @@
parameters:
- RV32M
- RV32E
+ - MultiplierImplementation
- BranchTargetALU
+ - WritebackStage
toplevel: ibex_riscv_compliance
tools:
verilator:
diff --git a/hw/vendor/lowrisc_ibex/dv/riscv_compliance/rtl/ibex_riscv_compliance.sv b/hw/vendor/lowrisc_ibex/dv/riscv_compliance/rtl/ibex_riscv_compliance.sv
index 78879b1..3f5e22b 100644
--- a/hw/vendor/lowrisc_ibex/dv/riscv_compliance/rtl/ibex_riscv_compliance.sv
+++ b/hw/vendor/lowrisc_ibex/dv/riscv_compliance/rtl/ibex_riscv_compliance.sv
@@ -15,9 +15,12 @@
input IO_RST_N
);
- parameter bit RV32E = 1'b0;
- parameter bit RV32M = 1'b1;
- parameter bit BranchTargetALU = 1'b0;
+ parameter bit RV32E = 1'b0;
+ parameter bit RV32M = 1'b1;
+ parameter bit RV32B = 1'b0;
+ parameter MultiplierImplementation = "fast";
+ parameter bit BranchTargetALU = 1'b0;
+ parameter bit WritebackStage = 1'b0;
logic clk_sys, rst_sys_n;
@@ -106,7 +109,10 @@
.DmExceptionAddr(32'h00000000),
.RV32E(RV32E),
.RV32M(RV32M),
- .BranchTargetALU(BranchTargetALU)
+ .RV32B(RV32B),
+ .MultiplierImplementation(MultiplierImplementation),
+ .BranchTargetALU(BranchTargetALU),
+ .WritebackStage(WritebackStage)
) u_core (
.clk_i (clk_sys),
.rst_ni (rst_sys_n),
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/Makefile b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/Makefile
index 5c3e064..2c603f5 100644
--- a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/Makefile
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/Makefile
@@ -2,10 +2,12 @@
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
-DV_DIR := $(shell dirname $(realpath $(lastword $(MAKEFILE_LIST))))
-GEN_DIR := $(realpath ${DV_DIR}/../../../vendor/google_riscv-dv)
+GEN_DIR := $(realpath ../../../vendor/google_riscv-dv)
TOOLCHAIN := ${RISCV_TOOLCHAIN}
+# Explicitly ask for the bash shell
+SHELL := bash
+
# Seed for instruction generator and RTL simulation
#
# By default, SEED is set to a different value on each run by picking a random
@@ -18,7 +20,7 @@
# This is the top-level output directory. Everything we generate goes in
# here. Most generated stuff actually goes in $(OUT)/seed-$(SEED), which allows
# us to run multiple times without deleting existing results.
-OUT := ${DV_DIR}/out
+OUT := out
OUT-SEED := $(OUT)/seed-$(SEED)
# Run time options for the instruction generator
@@ -41,7 +43,7 @@
ISA := rv32imc
# Test name (default: full regression)
TEST := all
-TESTLIST := ${DV_DIR}/riscv_dv_extension/testlist.yaml
+TESTLIST := riscv_dv_extension/testlist.yaml
# Verbose logging
VERBOSE :=
# Number of iterations for each test, assign a non-zero value to override the
@@ -52,7 +54,7 @@
# Generator timeout limit in seconds
TIMEOUT := 1800
# Privileged CSR YAML description file
-CSR_FILE := ${DV_DIR}/riscv_dv_extension/csr_description.yaml
+CSR_FILE := riscv_dv_extension/csr_description.yaml
# Pass/fail signature address at the end of test
SIGNATURE_ADDR := 8ffffffc
@@ -76,18 +78,21 @@
else ifeq (${SIMULATOR},ius)
COMPILE_OPTS += -defparam core_ibex_tb_top.dut.PMPNumRegions=${PMP_REGIONS}
COMPILE_OPTS += -defparam core_ibex_tb_top.dut.PMPGranularity=${PMP_GRANULARITY}
-# TODO(udinator) - support dsim and riviera
+else ifeq (&{SIMULATOR},riviera)
+ SIM_OPTS +=-g/core_ibex_tb_top/dut/PMPNumRegions=${PMP_REGIONS}
+ SIM_OPTS +=-g/core_ibex_tb_top/dut/PMPGranularity=${PMP_GRANULARITY}
+# TODO(udinator) - support dsim
endif
SHELL=/bin/bash
-export PRJ_DIR:= $(realpath ${DV_DIR}/../../../..)
+export PRJ_DIR:= $(realpath ../../../..)
all: sim
instr: iss_sim
-sim: post_compare
+sim: post_compare cov
.PHONY: clean
clean:
@@ -99,7 +104,7 @@
# Options for all targets that depend on the tests we're running.
TEST_OPTS := $(COMMON_OPTS) \
--seed=${SEED} \
- --test"=${TEST}" \
+ --test="${TEST}" \
--testlist=${TESTLIST} \
--iterations=${ITERATIONS}
@@ -108,7 +113,7 @@
--isa="${ISA}" \
--end_signature_addr=${SIGNATURE_ADDR}
-RISCV_DV_OPTS=--custom_target=${DV_DIR}/riscv_dv_extension \
+RISCV_DV_OPTS=--custom_target=riscv_dv_extension \
--isa="${ISA}" \
--mabi=ilp32 \
@@ -219,7 +224,7 @@
# the (phony) FORCE target if any variables have changed. If the rule actually
# runs, it starts by deleting any existing contents of $(OUT-SEED)/instr_gen.
$(metadata)/instr_gen.gen.stamp: \
- $(gen-vars-prereq) $(risc-dv-files) | $(metadata)
+ $(gen-vars-prereq) $(risc-dv-files) $(TESTLIST) | $(metadata)
@rm -rf $(OUT-SEED)/instr_gen
@python3 ${GEN_DIR}/run.py \
--output=$(OUT-SEED)/instr_gen ${GEN_OPTS} \
@@ -232,7 +237,7 @@
${CSR_OPTS} \
--sim_opts="+uvm_set_inst_override=riscv_asm_program_gen,ibex_asm_program_gen,"uvm_test_top.asm_gen" \
+signature_addr=${SIGNATURE_ADDR} +pmp_num_regions=${PMP_REGIONS} \
- +pmp_granularity=${PMP_GRANULARITY}"
+ +pmp_granularity=${PMP_GRANULARITY} +tvec_alignment=8"
$(call dump-vars,$(metadata)/gen-vars.mk,gen,$(gen-var-deps))
@touch $@
@@ -244,7 +249,8 @@
#
# We don't explicitly track dependencies on the RISCV toolchain, so this
# doesn't depend on anything more than the instr_gen stage did.
-$(metadata)/instr_gen.compile.stamp: $(metadata)/instr_gen.gen.stamp
+$(metadata)/instr_gen.compile.stamp: \
+ $(metadata)/instr_gen.gen.stamp $(TESTLIST)
@python3 ${GEN_DIR}/run.py \
--o=$(OUT-SEED)/instr_gen ${GEN_OPTS} \
--steps=gcc_compile \
@@ -268,7 +274,7 @@
iss-vars-prereq = $(call vars-prereq,iss,running ISS,$(iss-var-deps))
$(metadata)/instr_gen.iss.stamp: \
- $(iss-vars-prereq) $(metadata)/instr_gen.compile.stamp
+ $(iss-vars-prereq) $(TESTLIST) $(metadata)/instr_gen.compile.stamp
@python3 ${GEN_DIR}/run.py \
--o=$(OUT-SEED)/instr_gen ${GEN_OPTS} \
--steps=iss_sim \
@@ -311,17 +317,20 @@
$(call dump-vars-match,$(compile-var-deps),comp)
+cov-arg := $(if $(call equal,$(COV),1),--en_cov,)
+wave-arg := $(if $(call equal,$(WAVES),1),--en_wave,)
+lsf-arg := $(if $(LSF_CMD),--lsf_cmd="$(LSF_CMD)",)
+
$(OUT)/rtl_sim/.compile.stamp: \
- $(compile-vars-prereq) $(all-verilog) $(risc-dv-files) | $(OUT)/rtl_sim
- @python3 ./sim.py \
- --o=${OUT} \
- --riscv_dv_root=${GEN_DIR} \
- --steps=compile \
- ${COMMON_OPTS} \
- --simulator="${SIMULATOR}" \
- --en_cov=${COV} \
- --en_wave=${WAVES} \
- --cmp_opts="${COMPILE_OPTS}"
+ $(compile-vars-prereq) $(all-verilog) $(risc-dv-files) \
+ sim.py yaml/rtl_simulation.yaml \
+ | $(OUT)/rtl_sim
+ @./sim.py \
+ --o=${OUT} \
+ --steps=compile \
+ ${COMMON_OPTS} \
+ --simulator="${SIMULATOR}" --simulator_yaml=yaml/rtl_simulation.yaml \
+ $(cov-arg) $(wave-arg) --cmp_opts="${COMPILE_OPTS}"
$(call dump-vars,$(OUT)/rtl_sim/.compile-vars.mk,comp,$(compile-var-deps))
@touch $@
@@ -348,18 +357,16 @@
# This rule actually runs the simulation. It depends on the copied-in testbench
# and also on us having already compiled the test programs.
$(metadata)/rtl_sim.run.stamp: \
- $(metadata)/rtl_sim.compile.stamp $(metadata)/instr_gen.compile.stamp
- @python3 ./sim.py \
- --o=$(OUT-SEED) \
- --riscv_dv_root=${GEN_DIR} \
- --steps=sim \
- ${TEST_OPTS} \
- --simulator="${SIMULATOR}" \
- --en_cov ${COV} \
- --en_wave ${WAVES} \
- --lsf_cmd="${LSF_CMD}" \
- --sim_opts="+signature_addr=${SIGNATURE_ADDR}" \
- ${SIM_OPTS}
+ $(metadata)/rtl_sim.compile.stamp \
+ $(metadata)/instr_gen.compile.stamp $(TESTLIST) \
+ sim.py yaml/rtl_simulation.yaml
+ @./sim.py \
+ --o=$(OUT-SEED) \
+ --steps=sim \
+ ${TEST_OPTS} \
+ --simulator="${SIMULATOR}" --simulator_yaml=yaml/rtl_simulation.yaml \
+ $(cov-arg) $(wave-arg) $(lsf-arg) \
+ --sim_opts="+signature_addr=${SIGNATURE_ADDR} ${SIM_OPTS}"
@touch $@
.PHONY: rtl_sim
@@ -369,9 +376,9 @@
# Compare ISS and RTL sim results
$(OUT-SEED)/regr.log: \
$(metadata)/instr_gen.iss.stamp \
- $(metadata)/rtl_sim.run.stamp
+ $(metadata)/rtl_sim.run.stamp $(TESTLIST)
@rm -f $@
- @python3 ./sim.py \
+ @./sim.py \
--o=$(OUT-SEED) \
--steps=compare \
${TEST_OPTS} \
@@ -382,21 +389,24 @@
post_compare: $(OUT-SEED)/regr.log
###############################################################################
-# Generate functional coverage
+# Generate RISCV-DV functional coverage
fcov:
python3 ${GEN_DIR}/cov.py \
--core ibex \
--dir ${OUT}/rtl_sim \
-o ${OUT}/fcov \
--isa rv32imc \
- --custom_target ${DV_DIR}/riscv_dv_extension \
+ --custom_target riscv_dv_extension
-# Load verdi to review coverage
-cov_vcs:
- cd ${OUT}/rtl_sim; verdi -cov -covdir test.vdb &
-
-cov_ius:
- if [ ! -d "${OUT}/rtl_sim/cov_work/scope/merged_cov" ]; \
- then imc -execcmd "merge -out ${OUT}/rtl_sim/cov_work/scope/merged_cov ${OUT}/rtl_sim/cov_work/scope/test_*"; \
- fi
- imc -load ${OUT}/rtl_sim/cov_work/scope/merged_cov &
+# Merge all output coverage directories into the <out>/rtl_sim directory
+cov:
+ @rm -rf ${OUT}/rtl_sim/test.vdb
+ @./sim.py \
+ --steps=cov \
+ ${TEST_OPTS} \
+ --simulator="${SIMULATOR}" \
+ --o="${OUT}" \
+ --lsf_cmd="${LSF_CMD}";
+ @if [ -d "test.vdb" ]; then \
+ mv -f test.vdb ${OUT}/rtl_sim/; \
+ fi
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_agent.core b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_agent.core
new file mode 100644
index 0000000..bc93fd3
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_agent.core
@@ -0,0 +1,27 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:dv:ibex_mem_intf_agent:0.1"
+description: "IBEX DV UVM environment"
+filesets:
+ files_dv:
+ depend:
+ - lowrisc:dv:mem_model
+ files:
+ - ibex_mem_intf.sv
+ - ibex_mem_intf_agent_pkg.sv
+ - ibex_mem_intf_master_agent.sv: {is_include_file: true}
+ - ibex_mem_intf_master_driver.sv: {is_include_file: true}
+ - ibex_mem_intf_monitor.sv: {is_include_file: true}
+ - ibex_mem_intf_seq_item.sv: {is_include_file: true}
+ - ibex_mem_intf_slave_agent.sv: {is_include_file: true}
+ - ibex_mem_intf_slave_driver.sv: {is_include_file: true}
+ - ibex_mem_intf_slave_seq_lib.sv: {is_include_file: true}
+ - ibex_mem_intf_slave_sequencer.sv: {is_include_file: true}
+ file_type: systemVerilogSource
+
+targets:
+ default:
+ filesets:
+ - files_dv
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_agent_pkg.sv b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_agent_pkg.sv
index e4a65e6..41f514a 100644
--- a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_agent_pkg.sv
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_agent_pkg.sv
@@ -2,8 +2,6 @@
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
-`include "ibex_mem_intf.sv"
-
package ibex_mem_intf_agent_pkg;
import uvm_pkg::*;
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/irq_agent/irq_agent_pkg.sv b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/irq_agent/irq_agent_pkg.sv
index 76c4cbb..5d40366 100644
--- a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/irq_agent/irq_agent_pkg.sv
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/irq_agent/irq_agent_pkg.sv
@@ -2,8 +2,6 @@
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
-`include "irq_if.sv"
-
package irq_agent_pkg;
import uvm_pkg::*;
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/mem_model/mem_model.core b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/mem_model/mem_model.core
new file mode 100644
index 0000000..890bab6
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/mem_model/mem_model.core
@@ -0,0 +1,20 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:dv:mem_model"
+description: "DV Memory Model"
+
+filesets:
+ files_dv:
+ depend:
+ - lowrisc:dv:dv_utils
+ files:
+ - mem_model_pkg.sv
+ - mem_model.sv: {is_include_file: true}
+ file_type: systemVerilogSource
+
+targets:
+ default:
+ filesets:
+ - files_dv
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/env/core_ibex_env_pkg.sv b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/env/core_ibex_env_pkg.sv
index 5f92321..437c96b 100644
--- a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/env/core_ibex_env_pkg.sv
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/env/core_ibex_env_pkg.sv
@@ -6,10 +6,6 @@
// Core ibex environment package
// ---------------------------------------------
-`include "core_ibex_dut_probe_if.sv"
-`include "core_ibex_rvfi_if.sv"
-`include "core_ibex_csr_if.sv"
-
package core_ibex_env_pkg;
import uvm_pkg::*;
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/ibex_dv.f b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/ibex_dv.f
index d25ae42..87fcca7 100644
--- a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/ibex_dv.f
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/ibex_dv.f
@@ -14,6 +14,11 @@
// ibex CORE RTL files
+incdir+${PRJ_DIR}/ibex/rtl
${PRJ_DIR}/ibex/shared/rtl/prim_assert.sv
+${PRJ_DIR}/ibex/shared/rtl/prim_generic_ram_1p.sv
+${PRJ_DIR}/ibex/shared/rtl/prim_secded_28_22_enc.sv
+${PRJ_DIR}/ibex/shared/rtl/prim_secded_28_22_dec.sv
+${PRJ_DIR}/ibex/shared/rtl/prim_secded_72_64_enc.sv
+${PRJ_DIR}/ibex/shared/rtl/prim_secded_72_64_dec.sv
${PRJ_DIR}/ibex/rtl/ibex_pkg.sv
${PRJ_DIR}/ibex/rtl/ibex_tracer_pkg.sv
${PRJ_DIR}/ibex/rtl/ibex_tracer.sv
@@ -24,7 +29,9 @@
${PRJ_DIR}/ibex/rtl/ibex_counters.sv
${PRJ_DIR}/ibex/rtl/ibex_decoder.sv
${PRJ_DIR}/ibex/rtl/ibex_ex_block.sv
+${PRJ_DIR}/ibex/rtl/ibex_wb_stage.sv
${PRJ_DIR}/ibex/rtl/ibex_id_stage.sv
+${PRJ_DIR}/ibex/rtl/ibex_icache.sv
${PRJ_DIR}/ibex/rtl/ibex_if_stage.sv
${PRJ_DIR}/ibex/rtl/ibex_load_store_unit.sv
${PRJ_DIR}/ibex/rtl/ibex_multdiv_slow.sv
@@ -47,8 +54,13 @@
${PRJ_DIR}/ibex/dv/uvm/core_ibex/common/utils/clk_if.sv
${PRJ_DIR}/ibex/dv/uvm/core_ibex/common/utils/dv_utils_pkg.sv
${PRJ_DIR}/ibex/dv/uvm/core_ibex/common/mem_model/mem_model_pkg.sv
+${PRJ_DIR}/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf.sv
${PRJ_DIR}/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_agent_pkg.sv
+${PRJ_DIR}/ibex/dv/uvm/core_ibex/common/irq_agent/irq_if.sv
${PRJ_DIR}/ibex/dv/uvm/core_ibex/common/irq_agent/irq_agent_pkg.sv
+${PRJ_DIR}/ibex/dv/uvm/core_ibex/env/core_ibex_dut_probe_if.sv
+${PRJ_DIR}/ibex/dv/uvm/core_ibex/env/core_ibex_rvfi_if.sv
+${PRJ_DIR}/ibex/dv/uvm/core_ibex/env/core_ibex_csr_if.sv
${PRJ_DIR}/ibex/dv/uvm/core_ibex/env/core_ibex_env_pkg.sv
${PRJ_DIR}/ibex/dv/uvm/core_ibex/tests/core_ibex_test_pkg.sv
${PRJ_DIR}/ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/riscv_dv_extension/ibex_log_to_trace_csv.py b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/riscv_dv_extension/ibex_log_to_trace_csv.py
index 329556f..c4cc5c7 100644
--- a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/riscv_dv_extension/ibex_log_to_trace_csv.py
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/riscv_dv_extension/ibex_log_to_trace_csv.py
@@ -89,14 +89,16 @@
log and save to a standard CSV format.
"""
logging.info("Processing ibex log : %s" % ibex_log)
- with open(ibex_log, "r") as log_fd, open(csv, "w") as csv_fd:
- count = _process_ibex_sim_log_fd(log_fd, csv_fd,
- True if full_trace else False)
+ try:
+ with open(ibex_log, "r") as log_fd, open(csv, "w") as csv_fd:
+ count = _process_ibex_sim_log_fd(log_fd, csv_fd,
+ True if full_trace else False)
+ except FileNotFoundError:
+ raise RuntimeError("Logfile %s not found" % ibex_log)
logging.info("Processed instruction count : %d" % count)
if not count:
- logging.error("No instructions in logfile: %s" % ibex_log)
- sys.exit(RET_FATAL)
+ raise RuntimeError("No instructions in logfile: %s" % ibex_log)
logging.info("CSV saved to : %s" % csv)
@@ -134,11 +136,13 @@
correctness
Args:
- uvm_log: the uvm simulation log
+ uvm_log: the uvm simulation log
core_name: the name of the core
test_name: name of the test being checked
- report: the output report file
- write: enables writing to the log file
+ report: the output report file
+ write: enables writing to the log file. If equal to 'onfail',
+ write when the test fails. Otherwise (true, but not the
+ string 'onfail'), write unconditionally.
Returns:
A boolean indicating whether the test passed or failed based on the
@@ -197,4 +201,8 @@
if __name__ == "__main__":
- main()
+ try:
+ main()
+ except RuntimeError as err:
+ sys.stderr.write('Error: {}\n'.format(err))
+ sys.exit(RET_FATAL)
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/riscv_dv_extension/ml_testlist.yaml b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/riscv_dv_extension/ml_testlist.yaml
index 231cac3..7c9adb5 100644
--- a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/riscv_dv_extension/ml_testlist.yaml
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/riscv_dv_extension/ml_testlist.yaml
@@ -30,6 +30,29 @@
# gcc_opts : gcc compile options
# --------------------------------------------------------------------------------
+
+# --------------------------------------------------------------------------------
+# ML Parameter Constraints - riscv_rand_test
+# --------------------------------------------------------------------------------
+# A description of each generation parameter can be found in the 'Configuration'
+# section of the RISC-DV documentation
+# (https://github.com/google/riscv-dv/blob/master/docs/source/configuration.rst)
+#
+# This section will provide some constraints that must be placed on the main
+# parameter set for the riscv_rand_test to avoid failures or unexpected results
+# These constraints apply to every test that is written or used.
+# --------------------------------------------------------------------------------
+# 1) +no_wfi must be 1 to prevent the core from hanging during tests.
+# 2) if +no_directed_instr is 1, any directed instruction streams specified by the
+# +stream_name_... parameters will be ignored and will not be generated.
+# 3) +no_data_page must be 0 (default) if there are any directed streams
+# involving memory loads and stores.
+# 4) The +enable_misaligned_instr parameter is only used by the riscv_jal_instr
+# directed stream, and will have no effect if this stream is disabled.
+# 5) The +enable_unaligned_load_store parameter is only used by load/store
+# directed instruction streams, and will have no effect if these streams
+# are disabled.
+
- test: riscv_rand_test
description: >
Random test with all useful knobs
@@ -38,6 +61,24 @@
+num_of_sub_program=5
+illegal_instr_ratio=5
+hint_instr_ratio=5
+ +no_ebreak=0
+ +no_dret=0
+ +no_wfi=1
+ +set_mstatus_tw=0
+ +no_branch_jump=0
+ +no_csr_instr=0
+ +fix_sp=0
+ +enable_illegal_csr_instruction=0
+ +enable_access_invalid_csr_level=0
+ +enable_misaligned_instr=0
+ +enable_dummy_csr_write=0
+ +no_data_page=0
+ +no_directed_instr=0
+ +no_fence=0
+ +enable_unaligned_load_store=1
+ +disable_compressed_instr=0
+ +randomize_csr=0
+ +boot_mode=u
+stream_name_0=riscv_load_store_rand_instr_stream
+stream_freq_0=4
+stream_name_1=riscv_loop_instr
@@ -52,16 +93,197 @@
+stream_freq_5=4
+stream_name_6=riscv_int_numeric_corner_stream
+stream_freq_6=4
- +dist_control_mode=1
- +dist_shift=10
- +dist_arithmetic=10
- +dist_logical=10
- +dist_compare=10
- +dist_branch=10
- +dist_synch=10
- +dist_csr=10
+ +stream_name_7=riscv_multi_page_load_store_instr_stream
+ +stream_freq_7=4
+ +stream_name_8=riscv_load_store_rand_addr_instr_stream
+ +stream_freq_8=4
+ +stream_name_9=riscv_single_load_store_instr_stream
+ +stream_freq_9=4
+ +stream_name_10=riscv_load_store_stress_instr_stream
+ +stream_freq_10=4
iterations: 1
gcc_opts: >
-mno-strict-align
gen_test: riscv_ml_test
rtl_test: core_ibex_base_test
+
+
+# --------------------------------------------------------------------------------
+# ML Parameter Constraints - riscv_rand_debug_test
+# --------------------------------------------------------------------------------
+# A description of each generation parameter can be found in the 'Configuration'
+# section of the RISC-DV documentation
+# (https://github.com/google/riscv-dv/blob/master/docs/source/configuration.rst)
+#
+# This section will provide some constraints that must be placed on the set of
+# parameters relating to debug ROM generation and RTL simulation to avoid
+# failures or unexpected results.
+# --------------------------------------------------------------------------------
+# 1) +require_signature_address must be 1.
+# 2) If +gen_debug_section is 0, none of the values of the other debug ROM
+# parameters will matter.
+# 3) At most 1 of the parameters +enable_ebreak_in_debug_rom, +set_dcsr_ebreak,
+# and +enable_debug_single_step may be enabled at once.
+# 4) +illegal_instr_ratio must be 0.
+# 5) +no_ebreak and +no_dret must be 1.
+# 6) +set_mstatus_tw must be 0.
+# 7) The RTL simulation plusarg +require_signature_addr under the sim_opts
+# section of the test entry must be enabled.
+# 8) The RTL simulation plusarg +enable_debug_seq must be enabled.
+# 9) The RTL simulation plusarg +max_interval controls the maximum interval
+# between debug request assertions.
+# NOTE: keep this value very large for the time being.
+# 10) While not a constraint, it is recommended to keep +num_debug_sub_program
+# fairly small, as larger values can easily cause frequent test timeouts.
+
+- test: riscv_rand_debug_test
+ description: >
+ Random debug test with all useful knobs
+ gen_opts: >
+ +require_signature_addr=1
+ +gen_debug_section=1
+ +num_debug_sub_program=1
+ +enable_ebreak_in_debug_rom=0
+ +set_dcsr_ebreak=0
+ +enable_debug_single_step=1
+ +instr_cnt=10000
+ +num_of_sub_program=5
+ +illegal_instr_ratio=0
+ +hint_instr_ratio=5
+ +no_ebreak=1
+ +no_dret=1
+ +no_wfi=0
+ +set_mstatus_tw=0
+ +no_branch_jump=0
+ +no_load_store=0
+ +no_csr_instr=0
+ +fix_sp=0
+ +enable_illegal_csr_instruction=0
+ +enable_access_invalid_csr_level=0
+ +enable_misaligned_instr=1
+ +enable_dummy_csr_write=0
+ +no_data_page=0
+ +no_directed_instr=0
+ +no_fence=0
+ +enable_unaligned_load_store=1
+ +disable_compressed_instr=0
+ +randomize_csr=0
+ +boot_mode=u
+ +stream_name_0=riscv_load_store_rand_instr_stream
+ +stream_freq_0=4
+ +stream_name_1=riscv_loop_instr
+ +stream_freq_1=4
+ +stream_name_2=riscv_hazard_instr_stream
+ +stream_freq_2=4
+ +stream_name_3=riscv_load_store_hazard_instr_stream
+ +stream_freq_3=4
+ +stream_name_4=riscv_mem_region_stress_test
+ +stream_freq_4=4
+ +stream_name_5=riscv_jal_instr
+ +stream_freq_5=4
+ +stream_name_6=riscv_int_numeric_corner_stream
+ +stream_freq_6=4
+ +stream_name_7=riscv_multi_page_load_store_instr_stream
+ +stream_freq_7=4
+ +stream_name_8=riscv_load_store_rand_addr_instr_stream
+ +stream_freq_8=4
+ +stream_name_9=riscv_single_load_store_instr_stream
+ +stream_freq_9=4
+ +stream_name_10=riscv_load_store_stress_instr_stream
+ +stream_freq_10=4
+ iterations: 1
+ gcc_opts: >
+ -mno-strict-align
+ gen_test: riscv_ml_test
+ sim_opts: >
+ +require_signature_addr=1
+ +max_interval=100000
+ +enable_debug_seq=1
+ rtl_test: core_ibex_debug_intr_basic_test
+ compare_opts:
+ compare_final_value_only: 1
+
+
+# --------------------------------------------------------------------------------
+# ML Parameter Constraints - riscv_rand_irq_test
+# --------------------------------------------------------------------------------
+# A description of each generation parameter can be found in the 'Configuration'
+# section of the RISC-DV documentation
+# (https://github.com/google/riscv-dv/blob/master/docs/source/configuration.rst)
+#
+# This section will provide some constraints that must be placed on the set of
+# parameters relating to simulations with external interrupts.
+# --------------------------------------------------------------------------------
+# 1) +enable_interrupt and +require_signature_addr must both be 1.
+# 2) If using Spike ISS, +enable_timer_irq must be 0, otherwise it can be
+# randomized at will.
+# 3) As before, +illegal_instr_ratio must be 0, +no_ebreak must be 1,
+# and +no_dret must be 1.
+# 4) +set_mstatus_tw must be 0.
+# 3) One of the RTL simulation options +enable_irq_single_seq or
+# +enable_irq_multiple_seq must be enabled.
+# 4) The RTL simulation option +require_signature_addr must be 1.
+
+- test: riscv_rand_irq_test
+ description: >
+ Random test with all useful knobs
+ gen_opts: >
+ +require_signature_addr=1
+ +enable_interrupt=1
+ +enable_timer_irq=1
+ +instr_cnt=10000
+ +num_of_sub_program=5
+ +illegal_instr_ratio=0
+ +hint_instr_ratio=5
+ +no_ebreak=1
+ +no_dret=1
+ +no_wfi=0
+ +set_mstatus_tw=0
+ +no_branch_jump=0
+ +no_load_store=0
+ +no_csr_instr=0
+ +fix_sp=0
+ +enable_illegal_csr_instruction=0
+ +enable_access_invalid_csr_level=0
+ +enable_misaligned_instr=0
+ +enable_dummy_csr_write=0
+ +no_data_page=0
+ +no_directed_instr=0
+ +no_fence=0
+ +enable_unaligned_load_store=1
+ +disable_compressed_instr=0
+ +randomize_csr=1
+ +boot_mode=u
+ +stream_name_0=riscv_load_store_rand_instr_stream
+ +stream_freq_0=4
+ +stream_name_1=riscv_loop_instr
+ +stream_freq_1=4
+ +stream_name_2=riscv_hazard_instr_stream
+ +stream_freq_2=4
+ +stream_name_3=riscv_load_store_hazard_instr_stream
+ +stream_freq_3=4
+ +stream_name_4=riscv_mem_region_stress_test
+ +stream_freq_4=4
+ +stream_name_5=riscv_jal_instr
+ +stream_freq_5=4
+ +stream_name_6=riscv_int_numeric_corner_stream
+ +stream_freq_6=4
+ +stream_name_7=riscv_multi_page_load_store_instr_stream
+ +stream_freq_7=4
+ +stream_name_8=riscv_load_store_rand_addr_instr_stream
+ +stream_freq_8=4
+ +stream_name_9=riscv_single_load_store_instr_stream
+ +stream_freq_9=4
+ +stream_name_10=riscv_load_store_stress_instr_stream
+ +stream_freq_10=4
+ iterations: 1
+ gcc_opts: >
+ -mno-strict-align
+ gen_test: riscv_ml_test
+ sim_opts: >
+ +require_signature_addr=1
+ +enable_irq_single_seq=1
+ +enable_irq_multiple_seq=0
+ rtl_test: core_ibex_debug_intr_basic_test
+ compare_opts:
+ compare_final_value_only: 1
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/riscv_dv_extension/riscvOVPsim.ic b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/riscv_dv_extension/riscvOVPsim.ic
index 5fd38b6..16f4020 100644
--- a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/riscv_dv_extension/riscvOVPsim.ic
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/riscv_dv_extension/riscvOVPsim.ic
@@ -17,5 +17,6 @@
--override riscvOVPsim/cpu/time_undefined=F
--override riscvOVPsim/cpu/reset_address=0x80000080
--override riscvOVPsim/cpu/simulateexceptions=T
+--override riscvOVPsim/cpu/defaultsemihost=F
--override riscvOVPsim/cpu/wfi_is_nop=T
--override riscvOVPsim/cpu/tval_ii_code=T
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/sim.py b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/sim.py
old mode 100644
new mode 100755
index 6321fc0..19915a4
--- a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/sim.py
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/sim.py
@@ -1,301 +1,580 @@
-"""
-Copyright 2019 Google LLC
+#!/usr/bin/env python3
-Licensed under the Apache License, Version 2.0 (the "License");
-you may not use this file except in compliance with the License.
-You may obtain a copy of the License at
+# Copyright 2019 Google LLC
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
- http://www.apache.org/licenses/LICENSE-2.0
-
-Unless required by applicable law or agreed to in writing, software
-distributed under the License is distributed on an "AS IS" BASIS,
-WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-See the License for the specific language governing permissions and
-limitations under the License.
-
-Regression script for RISC-V random instruction generator
-"""
+"""Regression script for running the Spike UVM testbench"""
import argparse
import os
import random
-import re
import subprocess
import sys
-sys.path.insert(0, "../../../vendor/google_riscv-dv/scripts")
-sys.path.insert(0, "./riscv_dv_extension")
+_CORE_IBEX = os.path.normpath(os.path.join(os.path.dirname(__file__)))
+_IBEX_ROOT = os.path.normpath(os.path.join(_CORE_IBEX, '../../..'))
+_RISCV_DV_ROOT = os.path.join(_IBEX_ROOT, 'vendor/google_riscv-dv')
+_OLD_SYS_PATH = sys.path
-from lib import *
-from ibex_log_to_trace_csv import *
-from spike_log_to_trace_csv import *
-from ovpsim_log_to_trace_csv import *
-from instr_trace_compare import *
+# Import riscv_trace_csv and lib from _DV_SCRIPTS before putting sys.path back
+# as it started.
+try:
+ sys.path = ([os.path.join(_CORE_IBEX, 'riscv_dv_extension'),
+ os.path.join(_RISCV_DV_ROOT, 'scripts')] +
+ sys.path)
+
+ from lib import (process_regression_list,
+ read_yaml, run_cmd, run_parallel_cmd,
+ setup_logging, RET_SUCCESS, RET_FAIL)
+ import logging
+
+ from spike_log_to_trace_csv import process_spike_sim_log
+ from ovpsim_log_to_trace_csv import process_ovpsim_sim_log
+ from instr_trace_compare import compare_trace_csv
+
+ from ibex_log_to_trace_csv import process_ibex_sim_log, check_ibex_uvm_log
+
+finally:
+ sys.path = _OLD_SYS_PATH
-def process_cmd(keyword, cmd, opts, enable):
- """ Process the compile and simulation command
+def subst_opt(string, name, enable, replacement):
+ '''Substitute the <name> option in string
- Args:
- keyword : Keyword to search
- cmd : Command to be processed
- opts : Options to replace the keyword
- enable : Option enable/disable
+ If enable is False, <name> is replaced by '' in string. If it is True,
+ <name> is replaced by replacement, which should be a string or None. If
+ replacement is None and <name> occurs in string, we throw an error.
- Returns:
- Processed command
- """
- if enable == "1":
- return re.sub(keyword, opts.rstrip(), cmd)
- else:
- return re.sub(keyword, "", cmd)
+ '''
+ needle = '<{}>'.format(name)
+ if not enable:
+ return string.replace(needle, '')
+
+ if replacement is None:
+ if needle in string:
+ raise RuntimeError('No replacement defined for {} '
+ '(used in string: {!r}).'
+ .format(needle, string))
+ return string
+
+ return string.replace(needle, replacement)
-def get_simulator_cmd(simulator, simulator_yaml, en_cov, en_wave):
- """ Setup the compile and simulation command for the generator
+def subst_env_vars(string, env_vars):
+ '''Substitute environment variables in string
- Args:
- simulator : RTL simulator used to run instruction generator
- simulator_yaml : RTL simulator configuration file in YAML format
- en_cov : Enable coverage dump
- en_wave : Enable waveform
+ env_vars should be a string with a comma-separated list of environment
+ variables to substitute. For each environment variable, V, in the list, any
+ occurrence of <V> in string will be replaced by the value of the
+ environment variable with that name. If <V> occurs in the string but $V is
+ not set in the environment, an error is raised.
- Returns:
- compile_cmd : RTL simulator command to compile the instruction generator
- sim_cmd : RTL simulator command to run the instruction generator
- """
- logging.info("Processing simulator setup file : %s" % simulator_yaml)
- yaml_data = read_yaml(simulator_yaml)
- # Search for matched simulator
- for entry in yaml_data:
- if entry['tool'] == simulator:
- logging.info("Found matching simulator: %s" % entry['tool'])
- compile_cmd = entry['compile']['cmd']
- for i in range(len(compile_cmd)):
- if 'cov_opts' in entry['compile']:
- compile_cmd[i] = process_cmd("<cov_opts>", compile_cmd[i],
- entry['compile']['cov_opts'], en_cov)
- if 'wave_opts' in entry['compile']:
- compile_cmd[i] = process_cmd("<wave_opts>", compile_cmd[i],
- entry['compile']['wave_opts'], en_wave)
- sim_cmd = entry['sim']['cmd']
- if 'cov_opts' in entry['sim']:
- sim_cmd = process_cmd("<cov_opts>", sim_cmd, entry['sim']['cov_opts'], en_cov)
- if 'wave_opts' in entry['sim']:
- sim_cmd = process_cmd("<wave_opts>", sim_cmd, entry['sim']['wave_opts'], en_wave)
- if 'env_var' in entry:
- for env_var in entry['env_var'].split(','):
- for i in range(len(compile_cmd)):
- compile_cmd[i] = re.sub("<"+env_var+">", get_env_var(env_var), compile_cmd[i])
- sim_cmd = re.sub("<"+env_var+">", get_env_var(env_var), sim_cmd)
- return compile_cmd, sim_cmd
- logging.info("Cannot find RTL simulator %0s" % simulator)
- sys.exit(1)
+ '''
+ env_vars = env_vars.strip()
+ if not env_vars:
+ return string
+
+ for env_var in env_vars.split(','):
+ env_var = env_var.strip()
+ needle = '<{}>'.format(env_var)
+ if needle in string:
+ value = os.environ.get(env_var)
+ if value is None:
+ raise RuntimeError('Cannot substitute {} in command because '
+ 'the environment variable ${} is not set.'
+ .format(needle, env_var))
+ string = string.replace(needle, value)
+
+ return string
-def rtl_compile(compile_cmd, output_dir, lsf_cmd, opts):
- """Run the instruction generator
+def subst_cmd(cmd, enable_dict, opts_dict, env_vars):
+ '''Substitute options and environment variables in cmd
- Args:
- compile_cmd : Compile command
- output_dir : Output directory of the ELF files
- lsf_cmd : LSF command to run compilation
- opts : Compile options for the generator
- """
- # Compile the TB
- logging.info("Compiling TB")
- for cmd in compile_cmd:
- cmd = re.sub("<out>", output_dir, cmd)
- cmd = re.sub("<cmp_opts>", opts, cmd)
- logging.debug("Compile command: %s" % cmd)
- run_cmd(cmd)
+ enable_dict should be a dict mapping names to bools. For each key, N, in
+ enable_dict, if enable_dict[N] is False, then all occurrences of <N> in cmd
+ will be replaced with ''. If enable_dict[N] is True, all occurrences of <N>
+ in cmd will be replaced with opts_dict[N].
+
+ If N is not a key in opts_dict, this is no problem unless cmd contains
+ <N>, in which case we throw a RuntimeError.
+
+ Finally, the environment variables are substituted as described in
+ subst_env_vars and any newlines are stripped out.
+
+ '''
+ for name, enable in enable_dict.items():
+ cmd = subst_opt(cmd, name, enable, opts_dict.get(name))
+
+ return subst_env_vars(cmd, env_vars).replace('\n', ' ')
-def rtl_sim(sim_cmd, simulator, test_list, output_dir, bin_dir,
- lsf_cmd, seed, opts):
- """Run the instruction generator
+def subst_vars(string, var_dict):
+ '''Apply substitutions in var_dict to string
- Args:
- sim_cmd : Simulation command
- simulator : Simulator being used
- test_list : List of assembly programs
- output_dir : Simulation output directory
- bin_dir : Directory of the ELF files
- lsf_cmd : LSF command to run simulation
- seed : Seed of RTL simulation
- opts : Simulation options
- """
- check_return_code = True
- # Don't check return code for IUS sims, as a failure will short circuit
- # the entire simulation flow
- if simulator == "ius":
- check_return_code = False
- logging.debug("Disable return code checking for %s simulator" % simulator)
- # Run the RTL simulation
- sim_cmd = re.sub("<out>", output_dir, sim_cmd)
- sim_cmd = re.sub("<sim_opts>", opts, sim_cmd)
- sim_cmd = re.sub("<cwd>", cwd, sim_cmd)
- logging.info("Running RTL simulation...")
- cmd_list = []
- for test in test_list:
- for i in range(test['iterations']):
- rand_seed = get_seed(seed)
- test_sim_cmd = re.sub("<seed>", str(rand_seed), sim_cmd)
- if "sim_opts" in test:
- test_sim_cmd += ' '
- test_sim_cmd += test['sim_opts']
- sim_dir = output_dir + ("/%s.%d" %(test['test'], i))
- run_cmd(("mkdir -p %s" % sim_dir))
- os.chdir(sim_dir)
- binary = ("%s/%s_%d.bin" % (bin_dir, test['test'], i))
- cmd = lsf_cmd + " " + test_sim_cmd + \
- (" +UVM_TESTNAME=%s " % test['rtl_test']) + \
- (" +bin=%s " % binary) + \
- (" -l sim.log ")
- cmd = re.sub('\n', '', cmd)
- if lsf_cmd == "":
- logging.info("Running %s with %s" % (test['rtl_test'], binary))
- run_cmd(cmd, 300, check_return_code = check_return_code)
- else:
- cmd_list.append(cmd)
- if lsf_cmd != "":
- logging.info("Running %0d simulation jobs." % len(cmd_list))
- run_parallel_cmd(cmd_list, 600, check_return_code = check_return_code)
+ If var_dict[K] = V, then <K> will be replaced with V in string.'''
+ for key, value in var_dict.items():
+ string = string.replace('<{}>'.format(key), value)
+ return string
-def compare(test_list, iss, output_dir, verbose):
- """Compare RTL & ISS simulation reult
+def get_yaml_for_simulator(simulator, yaml_path):
+ '''Read yaml at yaml_path and find entry for simulator'''
+ logging.info("Processing simulator setup file : %s" % yaml_path)
+ for entry in read_yaml(yaml_path):
+ if entry.get('tool') == simulator:
+ return entry
- Args:
- test_list : List of assembly programs to be compiled
- iss : List of instruction set simulators
- output_dir : Output directory of the ELF files
- verbose : Verbose logging
- """
- report = ("%s/regr.log" % output_dir).rstrip()
- for test in test_list:
- compare_opts = test.get('compare_opts', {})
- in_order_mode = compare_opts.get('in_order_mode', 1)
- coalescing_limit = compare_opts.get('coalescing_limit', 0)
- verbose = compare_opts.get('verbose', 0)
- mismatch = compare_opts.get('mismatch_print_limit', 5)
- compare_final = compare_opts.get('compare_final_value_only', 0)
- for i in range(0, test['iterations']):
- elf = ("%s/asm_tests/%s.%d.o" % (output_dir, test['test'], i))
- logging.info("Comparing %s/DUT sim result : %s" % (iss, elf))
- run_cmd(("echo 'Test binary: %s' >> %s" % (elf, report)))
- uvm_log = ("%s/rtl_sim/%s.%d/sim.log" % (output_dir, test['test'], i))
- rtl_log = ("%s/rtl_sim/%s.%d/trace_core_00000000.log" % (output_dir, test['test'], i))
- rtl_csv = ("%s/rtl_sim/%s.%d/trace_core_00000000.csv" % (output_dir, test['test'], i))
- test_name = "%s.%d" % (test['test'], i)
- process_ibex_sim_log(rtl_log, rtl_csv, 1)
- if 'no_post_compare' in test and test['no_post_compare'] == 1:
- check_ibex_uvm_log(uvm_log, "ibex", test_name, report)
- else:
- iss_log = ("%s/instr_gen/%s_sim/%s.%d.log" % (output_dir, iss, test['test'], i))
- iss_csv = ("%s/instr_gen/%s_sim/%s.%d.csv" % (output_dir, iss, test['test'], i))
- if iss == "spike":
- process_spike_sim_log(iss_log, iss_csv)
- elif iss == "ovpsim":
- process_ovpsim_sim_log(iss_log, iss_csv)
+ raise RuntimeError("Cannot find RTL simulator {}".format(simulator))
+
+
+def get_simulator_cmd(simulator, yaml_path, enables):
+ '''Get compile and run commands for the testbench
+
+ simulator is the name of the simulator to use. yaml_path is the path to a
+ yaml file describing various command line options. enables is a dictionary
+ keyed by option names with boolean values: true if the option is enabled.
+
+ Returns (compile_cmds, sim_cmd), which are the simulator commands to
+ compile and run the testbench, respectively. compile_cmd is a list of
+ strings (multiple commands); sim_cmd is a single string.
+
+ '''
+ entry = get_yaml_for_simulator(simulator, yaml_path)
+ env_vars = entry.get('env_var', '')
+
+ return ([subst_cmd(arg, enables, entry['compile'], env_vars)
+ for arg in entry['compile']['cmd']],
+ subst_cmd(entry['sim']['cmd'], enables, entry['sim'], env_vars))
+
+
+def rtl_compile(compile_cmds, output_dir, lsf_cmd, opts):
+ """Compile the testbench RTL
+
+ compile_cmds is a list of commands (each a string), which will have <out>
+ and <cmp_opts> substituted. Running them in sequence should compile the
+ testbench.
+
+ output_dir is the directory in which to generate the testbench (usually
+ something like 'out/rtl_sim'). This will be substituted for <out> in the
+ commands.
+
+ If lsf_cmd is not None, it should be a string to prefix onto commands to
+ run them through LSF. Here, this is not used for parallelism, but might
+ still be needed for licence servers.
+
+ opts is a string giving extra compilation options. This is substituted for
+ <cmp_opts> in the commands.
+
+ """
+ logging.info("Compiling TB")
+ for cmd in compile_cmds:
+ cmd = subst_vars(cmd,
+ {
+ 'out': output_dir,
+ 'cmp_opts': opts
+ })
+
+ if lsf_cmd is not None:
+ cmd = lsf_cmd + ' ' + cmd
+
+ logging.debug("Compile command: %s" % cmd)
+
+ # Note that we don't use run_parallel_cmd here: the commands in
+ # compile_cmds need to be run serially.
+ run_cmd(cmd)
+
+
+def get_test_sim_cmd(base_cmd, test, idx, output_dir, bin_dir, lsf_cmd):
+ '''Generate the command that runs a test iteration in the simulator
+
+ base_cmd is the command to use before any test-specific substitutions. test
+ is a dictionary describing the test (originally read from the testlist YAML
+ file). idx is the test iteration (an integer).
+
+ output_dir is the directory below which the test results will be written.
+ bin_dir is the directory containing compiled binaries. lsf_cmd (if not
+ None) is a string that runs bsub to submit the task on LSF.
+
+ Returns (desc, cmd, dirname) where desc is a description of the command,
+ cmd is the command to run and dirname is the directory in which to run it.
+
+ '''
+ sim_cmd = (base_cmd + ' ' + test['sim_opts'].replace('\n', ' ')
+ if "sim_opts" in test
+ else base_cmd)
+
+ test_name = test['test']
+
+ sim_dir = os.path.join(output_dir, '{}.{}'.format(test_name, idx))
+ binary = os.path.join(bin_dir, '{}_{}.bin'.format(test_name, idx))
+ desc = '{} with {}'.format(test['rtl_test'], binary)
+
+ # Do final interpolation into the test command for variables that depend on
+ # the test name or iteration number.
+ sim_cmd = subst_vars(sim_cmd,
+ {
+ 'sim_dir': sim_dir,
+ 'rtl_test': test['rtl_test'],
+ 'binary': binary,
+ 'test_name': test_name,
+ 'iteration': str(idx)
+ })
+
+ if not os.path.exists(binary):
+ raise RuntimeError('When computing simulation command for running '
+ 'iteration {} of test {}, cannot find the '
+ 'expected binary at {!r}.'
+ .format(idx, test_name, binary))
+
+ if lsf_cmd is not None:
+ sim_cmd = lsf_cmd + ' ' + sim_cmd
+
+ return (desc, sim_cmd, sim_dir)
+
+
+def run_sim_commands(command_list, use_lsf, check_return_code):
+ '''Run the given list of commands
+
+ command_list should be a list of tuples (desc, cmd, dirname) where desc is
+ a human-readable description of the test, cmd is a command to run and
+ dirname is the directory in which to run it (which will be created if
+ necessary).
+
+ If use_lsf is true, the commands in command_list begin with something like
+ 'bsub -Is'. It seems that we always use interactive bsub, so we'll have a
+ local process per job, which we track with run_parallel_cmd.
+
+ If check_return_code is true, we check that the commands pass and stop if
+ not.
+
+ '''
+ # If we're in LSF mode, we submit all the commands 'at once', which means
+ # we have to create the output directories in advance.
+ if use_lsf:
+ cmds = []
+ for cmd, dirname in command_list:
+ os.makedirs(dirname, exist_ok=True)
+ cmds.append(cmd)
+ run_parallel_cmd(cmds, 600, check_return_code=check_return_code)
+ return
+
+ # We're not in LSF mode, so we'll create the output directories as we go.
+ # That should make it a bit easier to see how far we got if there was an
+ # error.
+ for desc, cmd, dirname in command_list:
+ os.makedirs(dirname, exist_ok=True)
+ logging.info("Running " + desc)
+ run_cmd(cmd, 300, check_return_code=check_return_code)
+
+
+def rtl_sim(sim_cmd, test_list, seed, opts,
+ output_dir, bin_dir, lsf_cmd, check_return_code):
+ """Run the testbench in the simulator
+
+ sim_cmd is the base command (as returned by get_simulator_cmd). This will
+ still have placeholders for test-specific arguments. test_list is a list of
+ test objects read from the testlist YAML file which gives the tests to run.
+
+ seed is the seed to use in the simulations (controls things like random
+ delays on the bus). opts is a string of plusargs to give to the simulator.
+
+ output_dir is the output directory for simulation files (and the directory
+ in which the simulator gets run). bin_dir is the directory containing
+ binaries to be run.
+
+ If lsf_cmd is not None, it should be prefixed on each command, which will
+ be run in parallel.
+
+ check_return_code is True if we should check the return codes from
+ simulator executions.
+
+ """
+ logging.info("Running RTL simulation...")
+
+ sim_cmd = subst_vars(sim_cmd,
+ {
+ 'out': output_dir,
+ 'sim_opts': opts,
+ 'cwd': _CORE_IBEX,
+ 'seed': str(seed)
+ })
+
+ # Compute a list of pairs (cmd, dirname) where cmd is the command to run
+ # and dirname is the directory in which the command should be run.
+ cmd_list = []
+ for test in test_list:
+ for i in range(test['iterations']):
+ cmd_list.append(get_test_sim_cmd(sim_cmd, test, i,
+ output_dir, bin_dir, lsf_cmd))
+
+ run_sim_commands(cmd_list, lsf_cmd is not None, check_return_code)
+
+
+def compare_test_run(test, idx, iss, output_dir, report):
+ '''Compare results for a single run of a single test
+
+ Here, test is a dictionary describing the test (read from the testlist YAML
+ file). idx is the iteration index. iss is the chosen instruction set
+ simulator (currently supported: spike and ovpsim). output_dir is the base
+ output directory (which should contain logs from both the ISS and the test
+ run itself). report is the path to the regression report file we're
+ writing.
+
+ Returns True if the test run passed and False otherwise.
+
+ '''
+ test_name = test['test']
+ elf = os.path.join(output_dir,
+ 'instr_gen/asm_tests/{}.{}.o'.format(test_name, idx))
+
+ logging.info("Comparing %s/DUT sim result : %s" % (iss, elf))
+
+ with open(report, 'a') as report_fd:
+ report_fd.write('Test binary: {}\n'.format(elf))
+
+ rtl_dir = os.path.join(output_dir, 'rtl_sim',
+ '{}.{}'.format(test_name, idx))
+
+ rtl_log = os.path.join(rtl_dir, 'trace_core_00000000.log')
+ rtl_csv = os.path.join(rtl_dir, 'trace_core_00000000.csv')
+ uvm_log = os.path.join(rtl_dir, 'sim.log')
+
+ try:
+ # Convert the RTL log file to a trace CSV.
+ process_ibex_sim_log(rtl_log, rtl_csv, 1)
+ except RuntimeError as e:
+ with open(report, 'a') as report_fd:
+ report_fd.write('Log processing failed: {}\n'.format(e))
+
+ return False
+
+ # Have a look at the UVM log. We should write out a message on failure or
+ # if we are stopping at this point.
+ no_post_compare = test.get('no_post_compare')
+ if not check_ibex_uvm_log(uvm_log, "ibex", test_name, report,
+ write=(True if no_post_compare else 'onfail')):
+ return False
+
+ if no_post_compare:
+ return True
+
+ # There were no UVM errors. Process the log file from the ISS.
+ iss_dir = os.path.join(output_dir, 'instr_gen', '{}_sim'.format(iss))
+
+ iss_log = os.path.join(iss_dir, '{}.{}.log'.format(test_name, idx))
+ iss_csv = os.path.join(iss_dir, '{}.{}.csv'.format(test_name, idx))
+
+ if iss == "spike":
+ process_spike_sim_log(iss_log, iss_csv)
+ else:
+ assert iss == 'ovpsim' # (should be checked by argparse)
+ process_ovpsim_sim_log(iss_log, iss_csv)
+
+ compare_result = \
+ compare_trace_csv(rtl_csv, iss_csv, "ibex", iss, report,
+ **test.get('compare_opts', {}))
+
+ # Rather oddly, compare_result is a string. The comparison passed if it
+ # starts with '[PASSED]'.
+ return compare_result.startswith('[PASSED]')
+
+
+def compare(test_list, iss, output_dir):
+ """Compare RTL & ISS simulation reult
+
+ Here, test_list is a list of tests read from the testlist YAML file. iss is
+ the instruction set simulator that was used (must be 'spike' or 'ovpsim')
+ and output_dir is the output directory which contains the results and where
+ we'll write the regression log.
+
+ """
+ report = os.path.join(output_dir, 'regr.log')
+ passes = 0
+ fails = 0
+ for test in test_list:
+ for idx in range(test['iterations']):
+ if compare_test_run(test, idx, iss, output_dir, report):
+ passes += 1
+ else:
+ fails += 1
+
+ summary = "{} PASSED, {} FAILED".format(passes, fails)
+ with open(report, 'a') as report_fd:
+ report_fd.write(summary + '\n')
+
+ logging.info(summary)
+ logging.info("RTL & ISS regression report at {}".format(report))
+
+ return fails == 0
+
+
+#TODO(udinator) - support IUS, DSim, and Riviera
+def gen_cov(base_dir, simulator, lsf_cmd):
+ """Generate a merged coverage directory.
+
+ Args:
+ base_dir: the base simulation output directory (default: out/)
+ simulator: the chosen RTL simulator
+ lsf_cmd: command to run on LSF
+
+ """
+ # Compile a list of all output seed-###/rtl_sim/test.vdb directories
+ dir_list = []
+ for entry in os.scandir(base_dir):
+ vdb_path = "%s/%s/rtl_sim/test.vdb" % (base_dir, entry.name)
+ if 'seed' in entry.name:
+ logging.info("Searching %s/%s for coverage database" %
+ (base_dir, entry.name))
+ if os.path.exists(vdb_path):
+ dir_list.append(vdb_path)
+ if dir_list == []:
+ logging.info("No coverage data available, exiting...")
+ sys.exit(RET_SUCCESS)
+
+ if simulator == 'vcs':
+ cov_cmd = "urg -full64 -format both -dbname test.vdb " \
+ "-report %s/rtl_sim/urgReport -dir" % base_dir
+ for cov_dir in dir_list:
+ cov_cmd += " %s" % cov_dir
+ logging.info("Generating merged coverage directory")
+ if lsf_cmd is not None:
+ cov_cmd = lsf_cmd + ' ' + cov_cmd
+ run_cmd(cov_cmd)
+ else:
+ logging.error("%s is an unsuported simulator! Exiting..." % simulator)
+ sys.exit(RET_FAIL)
+
+
+def main():
+ '''Entry point when run as a script'''
+
+ # Parse input arguments
+ parser = argparse.ArgumentParser()
+
+ parser.add_argument("--o", type=str, default="out",
+ help="Output directory name")
+ parser.add_argument("--testlist", help="Regression testlist",
+ default=os.path.join(_CORE_IBEX,
+ 'riscv_dv_extension',
+ 'testlist.yaml'))
+ parser.add_argument("--test", type=str, default="all",
+ help="Test name, 'all' means all tests in the list")
+ parser.add_argument("--seed", type=int,
+ help=("Randomization seed; random if not specified"))
+ parser.add_argument("--iterations", type=int, default=0,
+ help="Override the iteration count in the test list")
+ parser.add_argument("--simulator", type=str, default="vcs",
+ help="RTL simulator to use (default: vcs)")
+ parser.add_argument("--simulator_yaml",
+ help="RTL simulator setting YAML",
+ default=os.path.join(_CORE_IBEX,
+ 'yaml',
+ 'rtl_simulation.yaml'))
+ parser.add_argument("--iss", default="spike",
+ choices=['spike', 'ovpsim'],
+ help="Instruction set simulator")
+ parser.add_argument("-v", "--verbose", dest="verbose", action="store_true",
+ help="Verbose logging")
+ parser.add_argument("--cmp_opts", type=str, default="",
+ help="Compile options for the generator")
+ parser.add_argument("--sim_opts", type=str, default="",
+ help="Simulation options for the generator")
+ parser.add_argument("--en_cov", action='store_true',
+ help="Enable coverage dump")
+ parser.add_argument("--en_wave", action='store_true',
+ help="Enable waveform dump")
+ parser.add_argument("--steps", type=str, default="all",
+ help="Run steps: compile,sim,compare,cov")
+ parser.add_argument("--lsf_cmd", type=str,
+ help=("LSF command. Run locally if lsf "
+ "command is not specified"))
+
+ args = parser.parse_args()
+ setup_logging(args.verbose)
+ parser.set_defaults(verbose=False)
+
+ # Create the output directory
+ output_dir = ("%s/rtl_sim" % args.o)
+ bin_dir = ("%s/instr_gen/asm_tests" % args.o)
+ subprocess.run(["mkdir", "-p", output_dir])
+
+ steps = {
+ 'compile': args.steps == "all" or 'compile' in args.steps,
+ 'sim': args.steps == "all" or 'sim' in args.steps,
+ 'compare': args.steps == "all" or 'compare' in args.steps,
+ 'cov': args.steps == "all" or 'cov' in args.steps
+ }
+
+ compile_cmds = []
+ sim_cmd = ""
+ matched_list = []
+ if steps['compile'] or steps['sim']:
+ enables = {
+ 'cov_opts': args.en_cov,
+ 'wave_opts': args.en_wave
+ }
+ compile_cmds, sim_cmd = get_simulator_cmd(args.simulator,
+ args.simulator_yaml, enables)
+
+ if steps['sim'] or steps['compare']:
+ process_regression_list(args.testlist, args.test, args.iterations,
+ matched_list, _RISCV_DV_ROOT)
+ if not matched_list:
+ raise RuntimeError("Cannot find %s in %s" %
+ (args.test, args.testlist))
+
+ # Compile TB
+ if steps['compile']:
+ rtl_compile(compile_cmds, output_dir, args.lsf_cmd, args.cmp_opts)
+
+ # Run RTL simulation
+ if steps['sim']:
+ check_return_code = True
+ # Don't check return code for IUS sims, as a failure will short circuit
+ # the entire simulation flow
+ check_return_code = True
+ if args.simulator == "ius":
+ check_return_code = False
+ logging.debug("Disable return code checking for %s simulator"
+ % args.simulator)
+
+ # Pick a seed: either the one we were given, or pick one at random. In
+ # the latter case, print it out so the user can see what's going on.
+ if args.seed is None or args.seed < 0:
+ seed = random.getrandbits(32)
+ logging.info("Random seed chosen: {}".format(seed))
else:
- logging.info("Unsupported ISS" % iss)
- sys.exit(1)
- uvm_result = check_ibex_uvm_log(uvm_log, "ibex", test_name, report, False)
- if not uvm_result:
- check_ibex_uvm_log(uvm_log, "ibex", test_name, report)
- else:
- if 'compare_opts' in test:
- compare_trace_csv(rtl_csv, iss_csv, "ibex", iss, report,
- in_order_mode, coalescing_limit, verbose,
- mismatch, compare_final)
- else:
- compare_trace_csv(rtl_csv, iss_csv, "ibex", iss, report)
- passed_cnt = run_cmd("grep PASSED %s | wc -l" % report).strip()
- failed_cnt = run_cmd("grep FAILED %s | wc -l" % report).strip()
- summary = ("%s PASSED, %s FAILED" % (passed_cnt, failed_cnt))
- logging.info(summary)
- run_cmd(("echo %s >> %s" % (summary, report)))
- logging.info("RTL & ISS regression report is saved to %s" % report)
+ seed = args.seed
+
+ rtl_sim(sim_cmd, matched_list, seed, args.sim_opts,
+ output_dir, bin_dir, args.lsf_cmd, check_return_code)
+
+ # Compare RTL & ISS simulation result.
+ if steps['compare']:
+ compare(matched_list, args.iss, args.o)
+
+ # Generate merged coverage directory and load it into appropriate GUI
+ if steps['cov']:
+ gen_cov(args.o, args.simulator, args.lsf_cmd)
+
+ return RET_SUCCESS
-# Parse input arguments
-parser = argparse.ArgumentParser()
-
-parser.add_argument("--o", type=str, default="./out",
- help="Output directory name")
-parser.add_argument("--riscv_dv_root", type=str, default="",
- help="Root directory of RISCV-DV")
-parser.add_argument("--testlist", type=str, default="riscv_dv_extension/testlist.yaml",
- help="Regression testlist")
-parser.add_argument("--test", type=str, default="all",
- help="Test name, 'all' means all tests in the list")
-parser.add_argument("--seed", type=int, default=-1,
- help="Randomization seed, default -1 means random seed")
-parser.add_argument("--iterations", type=int, default=0,
- help="Override the iteration count in the test list")
-parser.add_argument("--simulator", type=str, default="vcs",
- help="Simulator used to run the generator, default VCS")
-parser.add_argument("--simulator_yaml", type=str, default="yaml/rtl_simulation.yaml",
- help="RTL simulator setting YAML")
-parser.add_argument("--iss", type=str, default="spike",
- help="Instruction set simulator")
-parser.add_argument("-v", "--verbose", dest="verbose", action="store_true",
- help="Verbose logging")
-parser.add_argument("--cmp_opts", type=str, default="",
- help="Compile options for the generator")
-parser.add_argument("--sim_opts", type=str, default="",
- help="Simulation options for the generator")
-parser.add_argument("--en_cov", type=str, default=0,
- help="Enable coverage dump")
-parser.add_argument("--en_wave", type=str, default=0,
- help="Enable waveform dump")
-parser.add_argument("--steps", type=str, default="all",
- help="Run steps: compile,sim,compare")
-parser.add_argument("--lsf_cmd", type=str, default="",
- help="LSF command. Run in local sequentially if lsf \
- command is not specified")
-
-args = parser.parse_args()
-setup_logging(args.verbose)
-parser.set_defaults(verbose=False)
-cwd = os.path.dirname(os.path.realpath(__file__))
-
-# Create the output directory
-output_dir = ("%s/rtl_sim" % args.o)
-bin_dir = ("%s/instr_gen/asm_tests" % args.o)
-subprocess.run(["mkdir", "-p", output_dir])
-
-steps = {
- 'compile': args.steps == "all" or re.match("compile", args.steps),
- 'sim': args.steps == "all" or re.match("sim", args.steps),
- 'compare': args.steps == "all" or re.match("compare", args.steps)
-}
-
-compile_cmd = []
-sim_cmd = ""
-matched_list = []
-if steps['compile'] or steps['sim']:
- compile_cmd, sim_cmd = get_simulator_cmd(args.simulator, args.simulator_yaml,
- args.en_cov, args.en_wave)
-if steps['sim'] or steps['compare']:
- process_regression_list(args.testlist, args.test, args.iterations,
- matched_list, args.riscv_dv_root)
- if not matched_list:
- sys.exit("Cannot find %s in %s" % (args.test, args.testlist))
-
-
-# Compile TB
-if steps['compile']:
- rtl_compile(compile_cmd, output_dir, args.lsf_cmd, args.cmp_opts)
-
-
-# Run RTL simulation
-if steps['sim']:
- rtl_sim(sim_cmd, args.simulator, matched_list, output_dir, bin_dir,
- args.lsf_cmd, args.seed, args.sim_opts)
-
-
-# Compare RTL & ISS simulation result.;
-if steps['compare']:
- compare(matched_list, args.iss, args.o, args.verbose)
+if __name__ == '__main__':
+ try:
+ sys.exit(main())
+ except RuntimeError as err:
+ sys.stderr.write('Error: {}\n'.format(err))
+ sys.exit(RET_FAIL)
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv
index 2969521..9de3815 100644
--- a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv
@@ -12,7 +12,8 @@
mem_model_pkg::mem_model mem;
core_ibex_vseq vseq;
bit enable_irq_seq;
- int unsigned timeout_in_cycles = 10000000;
+ int unsigned timeout_in_cycles = 100000000;
+ int unsigned max_quit_count = 1;
// If no signature_addr handshake functionality is desired between the testbench and the generated
// code, the test will wait for the specifield number of cycles before starting stimulus
// sequences (irq and debug)
@@ -76,6 +77,12 @@
phase.drop_objection(this);
endtask
+ virtual function void end_of_elaboration_phase(uvm_phase phase);
+ super.end_of_elaboration_phase(phase);
+ void'($value$plusargs("max_quit_count=%0d", max_quit_count));
+ uvm_report_server::get_server().set_max_quit_count(max_quit_count);
+ endfunction
+
virtual function void report_phase(uvm_phase phase);
super.report_phase(phase);
endfunction
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv
index 10f60af..20ea406 100644
--- a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv
@@ -192,7 +192,7 @@
init_operating_mode = priv_lvl_e'(core_init_mstatus[12:11]);
wait_for_csr_write(CSR_MIE, 5000);
core_init_mie = signature_data;
- check_next_core_status(INITIALIZED, "Core initialization handshake failure", 500);
+ check_next_core_status(INITIALIZED, "Core initialization handshake failure", 5000);
endtask
virtual task send_irq_stimulus_start(input bit no_nmi,
@@ -316,7 +316,7 @@
forever begin
wait_for_core_status(IN_DEBUG_MODE);
check_priv_mode(PRIV_LVL_M);
- wait_ret("dret", 20000);
+ wait_ret("dret", 100000);
end
end
join_none
@@ -521,7 +521,7 @@
wait_for_csr_write(CSR_DCSR, 500);
check_dcsr_prv(operating_mode);
check_dcsr_cause(DBG_CAUSE_HALTREQ);
- clk_vif.wait_clks($urandom_range(50, 100));
+ clk_vif.wait_clks($urandom_range(25, 50));
// Raise interrupts while the core is in debug mode
vseq.start_irq_raise_seq();
fork
@@ -530,7 +530,7 @@
`uvm_fatal(`gfn, "Core is handling interrupt detected in debug mode")
end
begin
- clk_vif.wait_clks(500);
+ clk_vif.wait_clks(100);
disable wait_irq;
end
join
@@ -739,6 +739,7 @@
bit [ibex_mem_intf_agent_pkg::DATA_WIDTH-1:0] counter = 0;
bit [ibex_mem_intf_agent_pkg::DATA_WIDTH-1:0] next_counter = 0;
forever begin
+ clk_vif.wait_clks(2000);
vseq.start_debug_single_seq();
check_next_core_status(IN_DEBUG_MODE,
"Core did not enter debug mode after debug stimulus", 1000);
@@ -779,7 +780,6 @@
wait_ret("dret", 5000);
if (counter === 0) break;
end
- clk_vif.wait_clks(2000);
end
endtask
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/vcs.tcl b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/vcs.tcl
index 730d0d4..93cbb82 100644
--- a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/vcs.tcl
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/vcs.tcl
@@ -1,10 +1,20 @@
# TCL file invoked from VCS's simv at run-time using this: -ucli -do <this file>
+# Since we don't necessarily run each test in a different directory,
+# we have to tell VCS where to put the waves. We do this with a
+# SIM_DIR environment variable, which we prepend to the wave name. If
+# SIM_DIR is not set, we just dump to the current directory.
+if { [info exists ::env(SIM_DIR)] } {
+ set sim_dir $::env(SIM_DIR)
+} else {
+ set sim_dir "."
+}
+
if { [info exists ::env(VERDI_HOME)] } {
# Use FSDB for dumping data, but only if we have Verdi set up.
# Syntax: fsdbDumpfile FSDB_Name [Limit_Size]
- fsdbDumpfile "waves.fsdb"
+ fsdbDumpfile "${sim_dir}/waves.fsdb"
# Syntax: fsdbDumpvars [depth] [instance] [option]*
##############################################################################
@@ -28,7 +38,7 @@
fsdbDumpSVA 0 core_ibex_tb_top.dut
} else {
# We don't have VERDI set up, so use VCS's standard dumping format.
- dump -file "waves.vpd"
+ dump -file "${sim_dir}/waves.vpd"
dump -add { core_ibex_tb_top } -depth 0 -aggregates -scope "."
}
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/yaml/rtl_simulation.yaml b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/yaml/rtl_simulation.yaml
index bb6be56..a4deaea 100644
--- a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/yaml/rtl_simulation.yaml
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/yaml/rtl_simulation.yaml
@@ -18,6 +18,7 @@
- "vcs -f ibex_dv.f -full64
-l <out>/compile.log
-sverilog -ntb_opts uvm-1.2
+ +define+UVM
+define+UVM_REGEX_NO_DPI -timescale=1ns/10ps -licqueue
-LDFLAGS '-Wl,--no-as-needed'
-Mdir=<out>/vcs_simv.csrc
@@ -36,14 +37,17 @@
-debug_access+all -ucli -do vcs.tcl
sim:
cmd: >
- <out>/vcs_simv +vcs+lic+wait <sim_opts> <wave_opts> <cov_opts>
- +ntb_random_seed=<seed>
+ env SIM_DIR=<sim_dir>
+ <out>/vcs_simv +vcs+lic+wait <sim_opts> <wave_opts> <cov_opts>
+ +ntb_random_seed=<seed> +UVM_TESTNAME=<rtl_test> +bin=<binary>
+ +ibex_tracer_file_base=<sim_dir>/trace_core
+ -l <sim_dir>/sim.log
cov_opts: >
-cm line+tgl+assert+fsm+branch
-cm_dir <out>/test.vdb
-cm_log /dev/null
-assert nopostproc
- -cm_name test_<seed>
+ -cm_name test_<test_name>_<iteration>
wave_opts: >
-ucli -do <cwd>/vcs.tcl
@@ -56,13 +60,15 @@
-genimage image
+incdir+$UVM_HOME/src
$UVM_HOME/src/uvm_pkg.sv
+ +define+UVM
+define+DSIM
+acc+rwb
-f ibex_dv.f
- -l <out>/dsim/compile.log"
+ -l <out>/dsim/compile.log
+ -suppress EnumMustBePositive"
sim:
cmd: >
- <DSIM> <sim_opts> -sv_seed <seed> -pli_lib <DSIM_LIB_PATH>/libuvm_dpi.so +acc+rwb -image image -work <out>/dsim <wave_opts>
+ <DSIM> <sim_opts> -sv_seed <seed> -pli_lib <DSIM_LIB_PATH>/libuvm_dpi.so +acc+rwb -image image -work <out>/dsim <wave_opts> +UVM_TESTNAME=<rtl_test> +bin=<binary> +ibex_tracer_file_base=<sim_dir>/trace_core -l <sim_dir>/sim.log
wave_opts: >
-waves waves.vcd
@@ -74,6 +80,7 @@
-access +rwc
-nclibdirpath <out>/ius
-sv -uvm -uvmhome CDNS-1.2
+ +define+UVM
-f ibex_dv.f
-elaborate -licqueue
-l <out>/ius/compile.log <cov_opts>"
@@ -97,11 +104,30 @@
- "vlib <out>/work"
- "vlog -work <out>/work
+incdir+<ALDEC_PATH>/vlib/uvm-1.2/src
+ +define+UVM
-l uvm_1_2
-f ibex_dv.f"
sim:
cmd: >
- vsim -c <sim_opts> <cov_opts> -lib <out>/work +access +r+w -l <out>/logfile.log -do "run -all; endsim; quit -force" +ibex_tracer_file_base="trace_core"
+ vsim -c <sim_opts> <cov_opts> -sv_seed <seed> -lib <out>/work +access +r+w -l <out>/logfile.log -do "run -all; endsim; quit -force" +ibex_tracer_file_base="trace_core"
cov_opts: >
-acdb_file <out>/cov.acdb
+
+- tool: qrun
+ compile:
+ cmd:
+ - "qrun -f ibex_dv.f -uvmhome uvm-1.2
+ +define+UVM
+ -svinputport=net
+ -access=rw+/. -optimize
+ -suppress 2583
+ -mfcu -cuname design_cuname
+ -sv -o design_opt
+ -l <out>/qrun_compile_optimize.log
+ -outdir <out>/qrun.out"
+ sim:
+ cmd: >
+ qrun -simulate -snapshot design_opt <cov_opts> <sim_opts> -sv_seed <seed> -outdir <out>/qrun.out
+ cov_opts: >
+ -coverage -ucdb <out>/cov.ucdb
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/data/common_modes.hjson b/hw/vendor/lowrisc_ibex/dv/uvm/data/common_modes.hjson
new file mode 100644
index 0000000..2779acb
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/data/common_modes.hjson
@@ -0,0 +1,38 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+{
+ // Sim modes are collection of build_opts and run_opts
+ // These are only set on the command line
+ // These are different from the build modes in the sense that these collection of
+ // options are appended to actual build_modes
+ build_modes: [
+ {
+ name: waves
+ is_sim_mode: 1
+ en_build_modes: ["{tool}_waves"]
+ }
+ {
+ name: cov
+ is_sim_mode: 1
+ en_build_modes: ["{tool}_cov"]
+ }
+ {
+ name: profile
+ is_sim_mode: 1
+ en_build_modes: ["{tool}_profile"]
+ }
+ {
+ name: xprop
+ is_sim_mode: 1
+ en_build_modes: ["{tool}_xprop"]
+ }
+ ]
+
+ run_modes: [
+ {
+ name: uvm_trace
+ run_opts: ["+UVM_PHASE_TRACE", "+UVM_CONFIG_DB_TRACE", "+UVM_OBJECTION_TRACE"]
+ }
+ ]
+}
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/data/common_project_cfg.hjson b/hw/vendor/lowrisc_ibex/dv/uvm/data/common_project_cfg.hjson
new file mode 100644
index 0000000..f7160a9
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/data/common_project_cfg.hjson
@@ -0,0 +1,29 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+{
+ project: opentitan
+ doc_server: docs.opentitan.org
+ results_server: reports.opentitan.org
+
+ // Default directory structure for the output
+ scratch_base_path: "{scratch_root}/{dut}.{flow}.{tool}"
+ scratch_path: "{scratch_base_path}/{branch}"
+ tool_srcs_dir: "{scratch_path}/{tool}"
+
+ // Results server stuff - indicate what command to use to copy over the results.
+ // Workaround for gsutil to fall back to using python2.7.
+ results_server_prefix: "gs://"
+ results_server_url_prefix: "https://"
+ results_server_cmd: "CLOUDSDK_PYTHON=/usr/bin/python2.7 /usr/bin/gsutil"
+ results_server_css_path: "{results_server_url_prefix}{results_server}/css/style.css"
+
+ results_server_path: "{results_server_prefix}{results_server}/{rel_path}"
+ results_server_dir: "{results_server_path}/latest"
+
+ results_server_html: "results.html"
+ results_server_page: "{results_server_dir}/{results_server_html}"
+
+ results_summary_server_html: "summary.html"
+ results_summary_server_page: "{results_server_path}/{results_summary_server_html}"
+}
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/data/common_sim_cfg.hjson b/hw/vendor/lowrisc_ibex/dv/uvm/data/common_sim_cfg.hjson
new file mode 100644
index 0000000..610d463
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/data/common_sim_cfg.hjson
@@ -0,0 +1,108 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+{
+ project: opentitan
+ doc_server: docs.opentitan.org
+ results_server: reports.opentitan.org
+
+ flow: sim
+ flow_makefile: "{proj_root}/dv/uvm/data/sim.mk"
+
+ import_cfgs: ["{proj_root}/dv/uvm/data/common_project_cfg.hjson",
+ "{proj_root}/dv/uvm/data/common_modes.hjson",
+ "{proj_root}/dv/uvm/data/fusesoc.hjson",
+ "{proj_root}/dv/uvm/data/{tool}/{tool}.hjson"]
+
+ // Default directory structure for the output
+ build_dir: "{scratch_path}/{build_mode}"
+ run_dir_name: "{index}.{test}"
+ run_dir: "{scratch_path}/{run_dir_name}/out"
+ sw_build_dir: ""
+ sw_root_dir: ""
+
+ // pass and fail patterns
+ build_pass_patterns: []
+ build_fail_patterns: []
+ run_pass_patterns: ["^TEST PASSED (UVM_)?CHECKS$"]
+ run_fail_patterns: ["^UVM_ERROR\\s[^:].*$",
+ "^UVM_FATAL\\s[^:].*$",
+ "^Assert failed: ",
+ "^\\s*Offending '.*'",
+ "^TEST FAILED (UVM_)?CHECKS$"]
+
+ // Default TileLink widths
+ tl_aw: 32
+ tl_dw: 32
+ tl_dbw: 4
+
+ // Default UVM verbosity settings
+ n: UVM_NONE
+ l: UVM_LOW
+ m: UVM_MEDIUM
+ h: UVM_HIGH
+ d: UVM_DEBUG
+
+ // Default waves dump settings
+ dump_base: waves
+
+ // Top level simulation entities.
+ sim_tops: ["-top {tb}"]
+
+ // Default build and run opts
+ build_opts: [// List multiple tops for the simulation
+ "{sim_tops}",
+ // Standard UVM defines
+ "+define+UVM",
+ "+define+UVM_NO_DEPRECATED",
+ "+define+UVM_REGEX_NO_DPI",
+ "+define+UVM_REG_ADDR_WIDTH={tl_aw}",
+ "+define+UVM_REG_DATA_WIDTH={tl_dw}",
+ "+define+UVM_REG_BYTENABLE_WIDTH={tl_dbw}"]
+
+ run_opts: ["+UVM_NO_RELNOTES",
+ "+UVM_VERBOSITY={verbosity}"]
+
+ // Default list of things to export to shell
+ exports: [
+ DUMP_BASE: {dump_base}
+ WAVES: {waves}
+ DUT_TOP: {dut}
+ TB_TOP: {tb}
+ ]
+
+ // Regressions are tests that can be grouped together and run in one shot
+ // By default, two regressions are made available - "all" and "nightly". Both
+ // run all available tests for the DUT. "nightly" enables coverage as well.
+ // The 'tests' key is set to an empty list, which indicates "run everything".
+ // Test sets can enable sim modes, which are a set of build_opts and run_opts
+ // that are grouped together. These are appended to the build modes used by the
+ // tests.
+ regressions: [
+ {
+ name: sanity
+ reseed: 1
+ }
+
+ {
+ name: all
+ tests: []
+ }
+
+ {
+ name: all_once
+ reseed: 1
+ tests: []
+ }
+
+ {
+ name: nightly
+ tests: []
+ en_sim_modes: ["cov"]
+ }
+ ]
+
+ // Project defaults for VCS
+ vcs_cov_hier: "-cm_hier {tool_srcs_dir}/cover.cfg"
+ vcs_cov_excl_files: []
+}
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/data/fusesoc.hjson b/hw/vendor/lowrisc_ibex/dv/uvm/data/fusesoc.hjson
new file mode 100644
index 0000000..d2ca94b
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/data/fusesoc.hjson
@@ -0,0 +1,12 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+{
+ sv_flist_gen_cmd: fusesoc
+ fusesoc_core_: "{eval_cmd} echo \"{fusesoc_core}\" | tr ':' '_'"
+ sv_flist_gen_opts: ["--cores-root {proj_root}",
+ "run --target=sim --build-root={build_dir}",
+ "--setup {fusesoc_core}"]
+ sv_flist_gen_dir: "{build_dir}/sim-vcs"
+ sv_flist: "{sv_flist_gen_dir}/{fusesoc_core_}.scr"
+}
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/data/sim.mk b/hw/vendor/lowrisc_ibex/dv/uvm/data/sim.mk
new file mode 100644
index 0000000..65727a2
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/data/sim.mk
@@ -0,0 +1,95 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+.DEFAULT_GOAL := all
+
+all: build run
+
+########################
+## RAL target ##
+########################
+ral:
+ifneq (${skip_ral},1)
+ mkdir -p ${gen_ral_pkg_dir} && \
+ ${gen_ral_pkg_cmd} ${gen_ral_pkg_opts}
+endif
+
+
+###############################
+## sim build and run targets ##
+###############################
+build: compile_result
+
+pre_compile:
+ @echo "[make]: pre_compile"
+ mkdir -p ${build_dir} && env | sort > ${build_dir}/env_vars
+ mkdir -p ${tool_srcs_dir}
+ cp -Ru ${tool_srcs} ${tool_srcs_dir}/.
+
+gen_sv_flist: pre_compile ral
+ @echo "[make]: gen_sv_flist"
+ cd ${build_dir} && ${sv_flist_gen_cmd} ${sv_flist_gen_opts}
+
+compile: gen_sv_flist
+ @echo "[make]: compile"
+ cd ${sv_flist_gen_dir} && ${build_cmd} ${build_opts}
+
+post_compile: compile
+ @echo "[make]: post_compile"
+
+compile_result: post_compile
+ @echo "[make]: compile_result"
+
+run: run_result
+
+pre_run:
+ @echo "[make]: pre_run"
+ mkdir -p ${run_dir} && env | sort > ${run_dir}/env_vars
+
+simulate:
+ @echo "[make]: simulate"
+ cd ${run_dir} && ${run_cmd} ${run_opts}
+
+post_run: simulate
+ @echo "[make]: post_run"
+
+run_result: post_run
+ @echo "[make]: run_result"
+
+#######################
+## Load waves target ##
+#######################
+debug_waves:
+ ${debug_waves_cmd} ${debug_waves_opts}
+
+############################
+## coverage rated targets ##
+############################
+# Merge coverage if there are multiple builds.
+cov_merge:
+ ${cov_merge_cmd} ${cov_merge_opts}
+
+# Open coverage tool to review and create report or exclusion file.
+cov_analyze:
+ ${cov_analyze_cmd} ${cov_analyze_opts}
+
+# Generate coverage reports.
+cov_report:
+ ${cov_report_cmd} ${cov_report_opts}
+
+clean:
+ echo "[make]: clean"
+ rm -rf ${scratch_root}/${dut}/*
+
+.PHONY: build \
+ run \
+ reg \
+ pre_compile \
+ compile \
+ post_compile \
+ compile_result \
+ pre_run \
+ simulate \
+ post_run \
+ run_result
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/data/vcs/cover.cfg b/hw/vendor/lowrisc_ibex/dv/uvm/data/vcs/cover.cfg
new file mode 100644
index 0000000..875dd0f
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/data/vcs/cover.cfg
@@ -0,0 +1,5 @@
++tree tb.dut
+begin tgl(portsonly)
+ -tree tb
+ +tree tb.dut 1
+end
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/data/vcs/vcs.hjson b/hw/vendor/lowrisc_ibex/dv/uvm/data/vcs/vcs.hjson
new file mode 100644
index 0000000..6e48b19
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/data/vcs/vcs.hjson
@@ -0,0 +1,156 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+{
+ build_cmd: "{job_prefix} vcs"
+ build_ex: "{build_dir}/simv"
+ run_cmd: "{job_prefix} {build_ex}"
+
+ // Indicate the tool specific helper sources - these are copied over to the
+ // {tool_srcs_dir} before running the simulation.
+ tool_srcs: ["{proj_root}/dv/uvm/data/vcs/*"]
+
+ build_opts: ["-sverilog -full64 -licqueue -kdb -ntb_opts uvm-1.2",
+ "-timescale=1ns/1ps",
+ "-Mdir={build_ex}.csrc",
+ "-o {build_ex}",
+ "-f {sv_flist}",
+ "+incdir+{build_dir}",
+ // Turn on warnings for non-void functions called with return values ignored
+ "+warn=SV-NFIVC",
+ "+warn=noUII-L",
+ // Below option required for $error/$fatal system calls
+ "-assert svaext",
+ // Force DPI-C compilation in C99 mode
+ "-CFLAGS \"--std=c99\"",
+ // Without this magic LDFLAGS argument below, we get compile time errors with
+ // VCS on Google Linux machines that look like this:
+ // .../libvcsnew.so: undefined reference to `snpsReallocFunc'
+ // .../libvcsnew.so: undefined reference to `snpsCheckStrdupFunc'
+ // .../libvcsnew.so: undefined reference to `snpsGetMemBytes'
+ "-LDFLAGS \"-Wl,--no-as-needed\""]
+
+ run_opts: ["-licqueue",
+ "-ucli -do {tool_srcs_dir}/vcs_fsdb.tcl",
+ "+ntb_random_seed={seed}",
+ "+UVM_TESTNAME={uvm_test}",
+ "+UVM_TEST_SEQ={uvm_test_seq}"]
+
+ // Coverage related.
+ cov_db_dir: "{build_dir}/cov.vdb"
+
+ // Individual test specific coverage data - this will be deleted if the test fails
+ // so that coverage from failiing tests is not included in the final report.
+ cov_db_test_dir_name: "{run_dir_name}.{seed}"
+ cov_db_test_dir: "{cov_db_dir}/snps/coverage/db/testdata/{cov_db_test_dir_name}"
+
+ // Merging coverage.
+ // "cov_db_dirs" is a special variable that appends all build directories in use.
+ // It is constructed by the tool itself.
+ cov_merge_dir: "{scratch_base_path}/cov_merge"
+ cov_merge_db_dir: "{cov_merge_dir}/merged.vdb"
+ cov_merge_cmd: "{job_prefix} urg"
+ cov_merge_opts: ["-full64",
+ "+urg+lic+wait",
+ "-nocheck",
+ "-noreport",
+ "-flex_merge drop",
+ "-group merge_across_scopes",
+ "-parallel",
+ "-parallel_split 20",
+ // Use cov_db_dirs var for dir args; append -dir in front of each
+ '''{eval_cmd} dirs=`echo {cov_db_dirs}`; dir_args=; \
+ for d in $dirs; do dir_args="$dir_args -dir $d"; done; \
+ echo $dir_args
+ ''',
+ "-dbname {cov_merge_db_dir}"]
+
+ // Generate coverage reports in text as well as html.
+ cov_report_dir: "{scratch_base_path}/cov_report"
+ cov_report_cmd: "{job_prefix} urg"
+ cov_report_opts: ["-full64",
+ "+urg+lic+wait",
+ "-dir {cov_merge_db_dir}",
+ "-group instcov_for_score",
+ "-line nocasedef",
+ "-format both",
+ "-report {cov_report_dir}"]
+ cov_report_dashboard: "{cov_report_dir}/dashboard.txt"
+
+ // Analyzing coverage - this is done by invoking --cov-analyze switch. It opens up the
+ // GUI for visual analysis.
+ cov_analyze_dir: "{scratch_base_path}/cov_analyze"
+ cov_analyze_cmd: "{job_prefix} verdi"
+ cov_analyze_opts: ["-cov",
+ "-covdir {cov_merge_db_dir}",
+ "-line nocasedef"
+ "-elfile {vcs_cov_excl_files}"]
+
+ // Vars that need to exported to the env.
+ exports: [
+ VCS_ARCH_OVERRIDE: linux
+ VCS_LIC_EXPIRE_WARNING: 1
+ ]
+
+ // Defaults for VCS
+ cov_metrics: "line+cond+fsm+tgl+branch+assert"
+ vcs_cov_hier: ""
+ vcs_cov_assert_hier: ""
+ vcs_cov_excl_files: []
+
+ // pass and fail patterns
+ build_fail_patterns: ["^Error-.*$"]
+ run_fail_patterns: ["^Error-.*$"] // Null pointer error
+
+ build_modes: [
+ {
+ name: vcs_waves
+ is_sim_mode: 1
+ build_opts: ["-debug_access+all"]
+ }
+ {
+ name: vcs_cov
+ is_sim_mode: 1
+ build_opts: [// Enable the required cov metrics
+ "-cm {cov_metrics}",
+ // Set the coverage hierarchy
+ "{vcs_cov_hier}",
+ // Cover all continuous assignments
+ "-cm_line contassign",
+ // Dump toggle coverage on mdas, array of structs and on ports only
+ "-cm_tgl mda+structarr+portsonly",
+ // Ignore initial blocks for coverage
+ "-cm_report noinitial",
+ // Filter unreachable/statically constant blocks
+ "-cm_noconst",
+ // Don't count coverage that's coming from zero-time glitches
+ "-cm_glitch 0",
+ // Ignore warnings about not applying cm_glitch to path and FSM
+ "+warn=noVCM-OPTIGN",
+ // Coverage database output location
+ "-cm_dir {cov_db_dir}"]
+
+ run_opts: [// Enable the required cov metrics
+ "-cm {cov_metrics}",
+ // Same directory as build
+ "-cm_dir {build_dir}/cov.vdb",
+ // Don't output cm.log which can be quite large
+ "-cm_log /dev/null",
+ // Provide a name to the coverage collected for this test
+ "-cm_name {cov_db_test_dir_name}",
+ // Don't dump all the coverage assertion attempts at the end of simulation
+ "-assert nopostproc"]
+ }
+ {
+ name: vcs_xprop
+ is_sim_mode: 1
+ build_opts: ["-xprop={tool_srcs_dir}/xprop.cfg"]
+ }
+ {
+ name: vcs_profile
+ is_sim_mode: 1
+ build_opts: ["-simprofile"]
+ run_opts: ["-simprofile {profile}"]
+ }
+ ]
+}
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/data/vcs/vcs_fsdb.tcl b/hw/vendor/lowrisc_ibex/dv/uvm/data/vcs/vcs_fsdb.tcl
new file mode 100644
index 0000000..94e7846
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/data/vcs/vcs_fsdb.tcl
@@ -0,0 +1,44 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+# TCL file invoked from VCS's simv at run-time using this: -ucli -do <this file>
+
+set dump_waves 0
+if {[info exists ::env(WAVES)]} {
+ set dump_waves "$::env(WAVES)"
+}
+
+if {"$dump_waves" == 1} {
+ # The basename (without extension) of the file where we should dump waves.
+ # Defaults to "waves".
+ set dump_base "waves"
+ if {[info exists ::(DUMP_BASE)]} {
+ set dump_base "$::env(DUMP_BASE)"
+ }
+
+ # The name of the top-level testbench. Defaults to "tb" if not defined in
+ # environment
+ set tb_top "tb"
+ if {[info exists ::(TB_TOP)]} {
+ set tb_top "$::env(TB_TOP)"
+ }
+
+ if {[info exists ::env(VERDI_HOME)]} {
+ # Looks like we've got a Verdi licence. The fsdbDumpvars command tells
+ # VCS to dump everything: memories, MDA signals, structs, unions, power
+ # and packed structs.
+ puts "Dumping waves with VERDI to ${dump_base}.fsdb"
+ fsdbDumpfile "${dump_base}.fsdb"
+ fsdbDumpvars 0 $tb_top +all
+ fsdbDumpSVA 0 $tb_top
+ } else {
+ # We don't have Verdi, so use standard dumping format (VCD+)
+ puts "Dumping waves in VCD+ format to ${dump_base}.vpd"
+ dump -file "${dump_base}.vpd"
+ dump -add "$tb_top" -depth 0 -aggregates -scope "."
+ }
+}
+
+run
+quit
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/data/vcs/xprop.cfg b/hw/vendor/lowrisc_ibex/dv/uvm/data/vcs/xprop.cfg
new file mode 100644
index 0000000..552a184
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/data/vcs/xprop.cfg
@@ -0,0 +1,4 @@
+merge = xmerge;
+
+// Turn on xprop for dut only
+instance { tb.dut } { xpropOn };
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/data/xcelium/xcelium.hjson b/hw/vendor/lowrisc_ibex/dv/uvm/data/xcelium/xcelium.hjson
new file mode 100644
index 0000000..7326ad0
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/data/xcelium/xcelium.hjson
@@ -0,0 +1,84 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+{
+ build_cmd: "{job_prefix} xrun"
+ run_cmd: "{job_prefix} xrun"
+
+ // Indicate the tool specific helper sources - these are copied over to the
+ // {tool_srcs_dir} before running the simulation.
+ tool_srcs: ["{proj_root}/dv/uvm/data/xcelium/*"]
+
+ build_opts: [" -elaborate -64bit -access +r -sv",
+ "-messages -errormax 50",
+ "-timescale 1ns/1ps",
+ "-f {sv_flist}",
+ "-uvmhome {UVM_HOME}",
+ "-xmlibdirname {build_dir}/xcelium.d"]
+
+ run_opts: ["-input {tool_srcs_dir}/xcelium_{dump}.tcl",
+ "-64bit -xmlibdirname {build_dir}/xcelium.d -R",
+ "+SVSEED={seed}",
+ "+UVM_TESTNAME={uvm_test}",
+ "+UVM_TEST_SEQ={uvm_test_seq}"]
+
+ // Coverage related.
+ // TODO: These options have to be filled in.
+ cov_db_dir: ""
+
+ // Individual test specific coverage data - this will be deleted if the test fails
+ // so that coverage from failiing tests is not included in the final report.
+ cov_db_test_dir_name: "{run_dir_name}.{seed}"
+ cov_db_test_dir: ""
+
+ // Merging coverage.
+ // "cov_db_dirs" is a special variable that appends all build directories in use.
+ // It is constructed by the tool itself.
+ cov_merge_dir: "{scratch_base_path}/cov_merge"
+ cov_merge_db_dir: ""
+ cov_merge_cmd: ""
+ cov_merge_opts: []
+
+ // Generate covreage reports in text as well as html.
+ cov_report_dir: "{scratch_base_path}/cov_report"
+ cov_report_cmd: ""
+ cov_report_opts: []
+ cov_report_dashboard: ""
+
+ // Analyzing coverage - this is done by invoking --cov-analyze switch. It opens up the
+ // GUI for visual analysis.
+ cov_analyze_dir: "{scratch_base_path}/cov_analyze"
+ cov_analyze_cmd: ""
+ cov_analyze_opts: []
+
+ // pass and fail patterns
+ build_fail_patterns: ["\\*E.*$"]
+ run_fail_patterns: ["\\*E.*$"] // Null pointer error
+
+ build_modes: [
+ {
+ name: xcelium_waves
+ is_sim_mode: 1
+ }
+ // TODO support coverage for xcelium
+ {
+ name: xcelium_cov
+ is_sim_mode: 1
+ build_opts: []
+ run_opts: []
+ }
+ // TODO support profile for xcelium
+ {
+ name: xcelium_profile
+ is_sim_mode: 1
+ build_opts: []
+ run_opts: []
+ }
+ {
+ name: xcelium_xprop
+ is_sim_mode: 1
+ # -xverbose << add to see which modules does not have xprop enabled
+ build_opts: ["-xprop F"]
+ }
+ ]
+}
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/icache/data/ibex_icache_testplan.hjson b/hw/vendor/lowrisc_ibex/dv/uvm/icache/data/ibex_icache_testplan.hjson
new file mode 100644
index 0000000..11a8a16
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/icache/data/ibex_icache_testplan.hjson
@@ -0,0 +1,30 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+{
+ name: "ibex_icache"
+
+ entries: [
+ {
+ name: sanity
+ desc: '''**Goal**: Basic sanity test acessing a major datapath in IBEX_ICACHE.
+
+ **Stimulus**: Describe the stimulus procedure.
+
+ **Checks**": Describe the self-check procedure.
+ - add bullets as needed
+ - second bullet<br>
+ describe second bullet
+
+ Start a new paragraph.'''
+ milestone: V1
+ tests: ["ibex_icache_sanity"]
+ }
+ {
+ name: feature1
+ desc: '''Add more test entries here like above.'''
+ milestone: V1
+ tests: []
+ }
+ ]
+}
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/icache/doc/ibex_icache_dv_plan.md b/hw/vendor/lowrisc_ibex/dv/uvm/icache/doc/ibex_icache_dv_plan.md
new file mode 100644
index 0000000..851d175
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/icache/doc/ibex_icache_dv_plan.md
@@ -0,0 +1,99 @@
+---
+title: "IBEX_ICACHE DV Plan"
+---
+
+## Goals
+* **DV**
+ * Verify all IBEX_ICACHE IP features by running dynamic simulations with a SV/UVM based testbench
+ * Develop and run all tests based on the [testplan](#testplan) below towards closing code and functional coverage on the IP and all of its sub-modules
+* **FPV**
+
+## Current status
+<!-- TODO for now -->
+* [Design & verification stage]({{< relref "doc/project/hw_dashboard" >}})
+ * [HW development stages]({{< relref "doc/project/hw_stages" >}})
+* [Simulation results](https://reports.opentitan.org/hw/ip/ibex_icache/dv/latest/results.html)
+
+## Design features
+For detailed information on IBEX_ICACHE design features, please see the [IBEX_ICACHE technical specification]({{< relref "doc/icache.rst" >}}).
+
+## Testbench architecture
+IBEX_ICACHE testbench has been constructed based on the [DV_LIB testbench architecture]({{< relref "vendor/lowrisc_ip/dv_lib/" >}}).
+
+### Block diagram
+
+
+### Top level testbench
+Top level testbench is located at `dv/uvm/icache/dv/tb/tb.sv`. It instantiates the IBEX_ICACHE DUT module `rtl/ibex_icache.sv`.
+In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into `uvm_config_db`:
+* [Clock and reset interface]({{< relref "vendor/lowrisc_ip/common_ifs" >}})
+<!-- TODO -->
+* IBEX_ICACHE IOs
+
+### Common DV utility components
+The following utilities provide generic helper tasks and functions to perform activities that are common across the project:
+* [dv_utils_pkg]({{< relref "vendor/lowrisc_ip/dv_utils/README.md" >}})
+
+### Compile-time configurations
+[list compile time configurations, if any and what are they used for]
+
+### Global types & methods
+All common types and methods defined at the package level can be found in
+`ibex_icache_env_pkg`. Some of them in use are:
+```systemverilog
+[list a few parameters, types & methods; no need to mention all]
+```
+
+### IBEX_ICACHE Agent
+[Describe here or add link to its README]
+### IBEX_MEM_INTF_SLAVE Agent
+[Describe here or add link to its README]
+
+### UVC/agent 1
+[Describe here or add link to its README]
+
+### UVC/agent 2
+[Describe here or add link to its README]
+
+
+### Reference models
+[Describe reference models in use if applicable, example: SHA256/HMAC]
+
+### Stimulus strategy
+#### Test sequences
+All test sequences reside in `dv/uvm/icache/dv/env/seq_lib`.
+The `ibex_icache_base_vseq` virtual sequence is extended from `cip_base_vseq` and serves as a starting point.
+All test sequences are extended from `ibex_icache_base_vseq`.
+It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call.
+Some of the most commonly used tasks / functions are as follows:
+* task 1:
+* task 2:
+
+#### Functional coverage
+To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model.
+The following covergroups have been developed to prove that the test intent has been adequately met:
+* cg1:
+* cg2:
+
+### Self-checking strategy
+#### Scoreboard
+The `ibex_icache_scoreboard` is primarily used for end to end checking.
+It creates the following analysis ports to retrieve the data monitored by corresponding interface agents:
+* analysis port1:
+* analysis port2:
+<!-- explain inputs monitored, flow of data and outputs checked -->
+
+#### Assertions
+<!-- only keep this section if any FPV is done on icache -->
+
+## Building and running tests
+We are using our in-house developed [regression tool]({{< relref "vendor/lowrisc_ip/dvsim" >}}) for building and running our tests and regressions.
+Please take a look at the link for detailed information on the usage, capabilities, features and known issues.
+Here's how to run a basic sanity test:
+```console
+$ cd hw/ip/ibex_icache/dv
+$ make TEST_NAME=ibex_icache_sanity
+```
+
+## Testplan
+{{</* testplan "dv/uvm/icache/data/ibex_icache_testplan.hjson" */>}}
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/icache/doc/tb.svg b/hw/vendor/lowrisc_ibex/dv/uvm/icache/doc/tb.svg
new file mode 100644
index 0000000..233330d
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/icache/doc/tb.svg
@@ -0,0 +1 @@
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diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/env/ibex_icache_env.core b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/env/ibex_icache_env.core
new file mode 100644
index 0000000..885b2f5
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/env/ibex_icache_env.core
@@ -0,0 +1,29 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:dv:ibex_icache_env:0.1"
+description: "IBEX_ICACHE DV UVM environment"
+filesets:
+ files_dv:
+ depend:
+ - lowrisc:dv:dv_lib
+ - lowrisc:dv:ibex_icache_agent
+ - lowrisc:dv:ibex_mem_intf_agent
+ files:
+ - ibex_icache_env_pkg.sv
+ - ibex_icache_env_cfg.sv: {is_include_file: true}
+ - ibex_icache_env_cov.sv: {is_include_file: true}
+ - ibex_icache_virtual_sequencer.sv: {is_include_file: true}
+ - ibex_icache_scoreboard.sv: {is_include_file: true}
+ - ibex_icache_env.sv: {is_include_file: true}
+ - seq_lib/ibex_icache_vseq_list.sv: {is_include_file: true}
+ - seq_lib/ibex_icache_base_vseq.sv: {is_include_file: true}
+ - seq_lib/ibex_icache_common_vseq.sv: {is_include_file: true}
+ - seq_lib/ibex_icache_sanity_vseq.sv: {is_include_file: true}
+ file_type: systemVerilogSource
+
+targets:
+ default:
+ filesets:
+ - files_dv
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/env/ibex_icache_env.sv b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/env/ibex_icache_env.sv
new file mode 100644
index 0000000..1252116
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/env/ibex_icache_env.sv
@@ -0,0 +1,41 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+class ibex_icache_env extends dv_base_env #(
+ .CFG_T (ibex_icache_env_cfg),
+ .COV_T (ibex_icache_env_cov),
+ .VIRTUAL_SEQUENCER_T(ibex_icache_virtual_sequencer),
+ .SCOREBOARD_T (ibex_icache_scoreboard)
+ );
+ `uvm_component_utils(ibex_icache_env)
+
+ ibex_icache_agent m_ibex_icache_agent;
+ ibex_mem_intf_slave_agent m_ibex_mem_intf_slave_agent;
+
+ `uvm_component_new
+
+ function void build_phase(uvm_phase phase);
+ super.build_phase(phase);
+ // create components
+ m_ibex_icache_agent = ibex_icache_agent::type_id::create("m_ibex_icache_agent", this);
+ uvm_config_db#(ibex_icache_agent_cfg)::set(this, "m_ibex_icache_agent*", "cfg", cfg.m_ibex_icache_agent_cfg);
+ // create components
+ m_ibex_mem_intf_slave_agent = ibex_mem_intf_slave_agent::type_id::create("m_ibex_mem_intf_slave_agent", this);
+ endfunction
+
+ function void connect_phase(uvm_phase phase);
+ super.connect_phase(phase);
+ if (cfg.en_scb) begin
+ m_ibex_icache_agent.monitor.analysis_port.connect(scoreboard.ibex_icache_fifo.analysis_export);
+ m_ibex_mem_intf_slave_agent.monitor.addr_ph_port.connect(scoreboard.ibex_mem_intf_slave_fifo.analysis_export);
+ end
+ if (cfg.is_active && cfg.m_ibex_icache_agent_cfg.is_active) begin
+ virtual_sequencer.ibex_icache_sequencer_h = m_ibex_icache_agent.sequencer;
+ end
+ if (cfg.is_active && m_ibex_mem_intf_slave_agent.get_is_active()) begin
+ virtual_sequencer.ibex_mem_intf_slave_sequencer_h = m_ibex_mem_intf_slave_agent.sequencer;
+ end
+ endfunction
+
+endclass
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/env/ibex_icache_env_cfg.sv b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/env/ibex_icache_env_cfg.sv
new file mode 100644
index 0000000..c8b8dd1
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/env/ibex_icache_env_cfg.sv
@@ -0,0 +1,23 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+class ibex_icache_env_cfg extends dv_base_env_cfg;
+
+ // ext component cfgs
+ rand ibex_icache_agent_cfg m_ibex_icache_agent_cfg;
+
+ `uvm_object_utils_begin(ibex_icache_env_cfg)
+ `uvm_field_object(m_ibex_icache_agent_cfg, UVM_DEFAULT)
+ `uvm_object_utils_end
+
+ `uvm_object_new
+
+
+ virtual function void initialize(bit [TL_AW-1:0] csr_base_addr = '1);
+ // create ibex_icache agent config obj
+ m_ibex_icache_agent_cfg = ibex_icache_agent_cfg::type_id::create("m_ibex_icache_agent_cfg");
+ // create ibex_mem_intf_slave agent config obj
+ endfunction
+
+endclass
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/env/ibex_icache_env_cov.sv b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/env/ibex_icache_env_cov.sv
new file mode 100644
index 0000000..1ba1107
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/env/ibex_icache_env_cov.sv
@@ -0,0 +1,30 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+/**
+ * Covergoups that are dependent on run-time parameters that may be available
+ * only in build_phase can be defined here
+ * Covergroups may also be wrapped inside helper classes if needed.
+ */
+
+class ibex_icache_env_cov extends dv_base_env_cov #(.CFG_T(ibex_icache_env_cfg));
+ `uvm_component_utils(ibex_icache_env_cov)
+
+ // the base class provides the following handles for use:
+ // ibex_icache_env_cfg: cfg
+
+ // covergroups
+ // [add covergroups here]
+
+ function new(string name, uvm_component parent);
+ super.new(name, parent);
+ // [instantiate covergroups here]
+ endfunction : new
+
+ virtual function void build_phase(uvm_phase phase);
+ super.build_phase(phase);
+ // [or instantiate covergroups here]
+ endfunction
+
+endclass
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/env/ibex_icache_env_pkg.sv b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/env/ibex_icache_env_pkg.sv
new file mode 100644
index 0000000..eb941be
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/env/ibex_icache_env_pkg.sv
@@ -0,0 +1,33 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+package ibex_icache_env_pkg;
+ // dep packages
+ import uvm_pkg::*;
+ import top_pkg::*;
+ import dv_utils_pkg::*;
+ import ibex_icache_agent_pkg::*;
+ import ibex_mem_intf_agent_pkg::*;
+ import dv_lib_pkg::*;
+
+ // macro includes
+ `include "uvm_macros.svh"
+ `include "dv_macros.svh"
+
+ // parameters
+
+ // types
+ typedef dv_base_reg_block ibex_icache_reg_block;
+
+ // functions
+
+ // package sources
+ `include "ibex_icache_env_cfg.sv"
+ `include "ibex_icache_env_cov.sv"
+ `include "ibex_icache_virtual_sequencer.sv"
+ `include "ibex_icache_scoreboard.sv"
+ `include "ibex_icache_env.sv"
+ `include "ibex_icache_vseq_list.sv"
+
+endpackage
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/env/ibex_icache_scoreboard.sv b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/env/ibex_icache_scoreboard.sv
new file mode 100644
index 0000000..ac3a2a0
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/env/ibex_icache_scoreboard.sv
@@ -0,0 +1,67 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+class ibex_icache_scoreboard extends dv_base_scoreboard #(
+ .CFG_T(ibex_icache_env_cfg),
+ .COV_T(ibex_icache_env_cov)
+ );
+ `uvm_component_utils(ibex_icache_scoreboard)
+
+ // local variables
+
+ // TLM agent fifos
+ uvm_tlm_analysis_fifo #(ibex_icache_item) ibex_icache_fifo;
+ uvm_tlm_analysis_fifo #(ibex_mem_intf_seq_item) ibex_mem_intf_slave_fifo;
+
+ // local queues to hold incoming packets pending comparison
+ ibex_icache_item ibex_icache_q[$];
+ ibex_mem_intf_seq_item ibex_mem_intf_slave_q[$];
+
+ `uvm_component_new
+
+ function void build_phase(uvm_phase phase);
+ super.build_phase(phase);
+ ibex_icache_fifo = new("ibex_icache_fifo", this);
+ ibex_mem_intf_slave_fifo = new("ibex_mem_intf_slave_fifo", this);
+ endfunction
+
+ function void connect_phase(uvm_phase phase);
+ super.connect_phase(phase);
+ endfunction
+
+ task run_phase(uvm_phase phase);
+ super.run_phase(phase);
+ fork
+ process_ibex_icache_fifo();
+ process_ibex_mem_intf_slave_fifo();
+ join_none
+ endtask
+
+ virtual task process_ibex_icache_fifo();
+ ibex_icache_item item;
+ forever begin
+ ibex_icache_fifo.get(item);
+ `uvm_info(`gfn, $sformatf("received ibex_icache item:\n%0s", item.sprint()), UVM_HIGH)
+ end
+ endtask
+
+ virtual task process_ibex_mem_intf_slave_fifo();
+ ibex_mem_intf_seq_item item;
+ forever begin
+ ibex_mem_intf_slave_fifo.get(item);
+ `uvm_info(`gfn, $sformatf("received ibex_mem_intf_seq item:\n%0s", item.sprint()), UVM_HIGH)
+ end
+ endtask
+
+ virtual function void reset(string kind = "HARD");
+ super.reset(kind);
+ // reset local fifos queues and variables
+ endfunction
+
+ function void check_phase(uvm_phase phase);
+ super.check_phase(phase);
+ // post test checks - ensure that all local fifos and queues are empty
+ endfunction
+
+endclass
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/env/ibex_icache_virtual_sequencer.sv b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/env/ibex_icache_virtual_sequencer.sv
new file mode 100644
index 0000000..351398a
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/env/ibex_icache_virtual_sequencer.sv
@@ -0,0 +1,16 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+class ibex_icache_virtual_sequencer extends dv_base_virtual_sequencer #(
+ .CFG_T(ibex_icache_env_cfg),
+ .COV_T(ibex_icache_env_cov)
+ );
+ `uvm_component_utils(ibex_icache_virtual_sequencer)
+
+ ibex_icache_sequencer ibex_icache_sequencer_h;
+ ibex_mem_intf_slave_sequencer ibex_mem_intf_slave_sequencer_h;
+
+ `uvm_component_new
+
+endclass
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/env/seq_lib/ibex_icache_base_vseq.sv b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/env/seq_lib/ibex_icache_base_vseq.sv
new file mode 100644
index 0000000..e827e41
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/env/seq_lib/ibex_icache_base_vseq.sv
@@ -0,0 +1,32 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+class ibex_icache_base_vseq extends dv_base_vseq #(
+ .CFG_T (ibex_icache_env_cfg),
+ .COV_T (ibex_icache_env_cov),
+ .VIRTUAL_SEQUENCER_T (ibex_icache_virtual_sequencer)
+ );
+ `uvm_object_utils(ibex_icache_base_vseq)
+
+ // various knobs to enable certain routines
+ bit do_ibex_icache_init = 1'b1;
+
+ `uvm_object_new
+
+ virtual task dut_init(string reset_kind = "HARD");
+ super.dut_init();
+ if (do_ibex_icache_init) ibex_icache_init();
+ endtask
+
+ virtual task dut_shutdown();
+ // check for pending ibex_icache operations and wait for them to complete
+ // TODO
+ endtask
+
+ // setup basic ibex_icache features
+ virtual task ibex_icache_init();
+ `uvm_error(`gfn, "FIXME")
+ endtask
+
+endclass : ibex_icache_base_vseq
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/env/seq_lib/ibex_icache_common_vseq.sv b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/env/seq_lib/ibex_icache_common_vseq.sv
new file mode 100644
index 0000000..030f0a9
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/env/seq_lib/ibex_icache_common_vseq.sv
@@ -0,0 +1,18 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+class ibex_icache_common_vseq extends ibex_icache_base_vseq;
+ `uvm_object_utils(ibex_icache_common_vseq)
+
+ constraint num_trans_c {
+ num_trans inside {[1:2]};
+ }
+ `uvm_object_new
+
+ virtual task body();
+ // TODO: implement the body of the common virtual sequence
+ endtask : body
+
+
+endclass
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/env/seq_lib/ibex_icache_sanity_vseq.sv b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/env/seq_lib/ibex_icache_sanity_vseq.sv
new file mode 100644
index 0000000..0697d49
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/env/seq_lib/ibex_icache_sanity_vseq.sv
@@ -0,0 +1,15 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// basic sanity test vseq
+class ibex_icache_sanity_vseq extends ibex_icache_base_vseq;
+ `uvm_object_utils(ibex_icache_sanity_vseq)
+
+ `uvm_object_new
+
+ task body();
+ `uvm_error(`gfn, "FIXME")
+ endtask : body
+
+endclass : ibex_icache_sanity_vseq
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/env/seq_lib/ibex_icache_vseq_list.sv b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/env/seq_lib/ibex_icache_vseq_list.sv
new file mode 100644
index 0000000..4a8ece4
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/env/seq_lib/ibex_icache_vseq_list.sv
@@ -0,0 +1,7 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+`include "ibex_icache_base_vseq.sv"
+`include "ibex_icache_sanity_vseq.sv"
+`include "ibex_icache_common_vseq.sv"
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/ibex_icache_agent/README.md b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/ibex_icache_agent/README.md
new file mode 100644
index 0000000..4ee1f42
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/ibex_icache_agent/README.md
@@ -0,0 +1,3 @@
+# IBEX_ICACHE UVM Agent
+
+IBEX_ICACHE UVM Agent is extended from DV library agent classes.
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/ibex_icache_agent/ibex_icache_agent.core b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/ibex_icache_agent/ibex_icache_agent.core
new file mode 100644
index 0000000..5e7d41d
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/ibex_icache_agent/ibex_icache_agent.core
@@ -0,0 +1,28 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:dv:ibex_icache_agent:0.1"
+description: "IBEX_ICACHE DV UVM agent"
+filesets:
+ files_dv:
+ depend:
+ - lowrisc:dv:dv_utils
+ - lowrisc:dv:dv_lib
+ files:
+ - ibex_icache_if.sv
+ - ibex_icache_agent_pkg.sv
+ - ibex_icache_item.sv: {is_include_file: true}
+ - ibex_icache_agent_cfg.sv: {is_include_file: true}
+ - ibex_icache_agent_cov.sv: {is_include_file: true}
+ - ibex_icache_driver.sv: {is_include_file: true}
+ - ibex_icache_monitor.sv: {is_include_file: true}
+ - ibex_icache_agent.sv: {is_include_file: true}
+ - seq_lib/ibex_icache_base_seq.sv: {is_include_file: true}
+ - seq_lib/ibex_icache_seq_list.sv: {is_include_file: true}
+ file_type: systemVerilogSource
+
+targets:
+ default:
+ filesets:
+ - files_dv
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/ibex_icache_agent/ibex_icache_agent.sv b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/ibex_icache_agent/ibex_icache_agent.sv
new file mode 100644
index 0000000..832ce62
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/ibex_icache_agent/ibex_icache_agent.sv
@@ -0,0 +1,25 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+class ibex_icache_agent extends dv_base_agent #(
+ .CFG_T (ibex_icache_agent_cfg),
+ .DRIVER_T (ibex_icache_driver),
+ .SEQUENCER_T (ibex_icache_sequencer),
+ .MONITOR_T (ibex_icache_monitor),
+ .COV_T (ibex_icache_agent_cov)
+);
+
+ `uvm_component_utils(ibex_icache_agent)
+
+ `uvm_component_new
+
+ function void build_phase(uvm_phase phase);
+ super.build_phase(phase);
+ // get ibex_icache_if handle
+ if (!uvm_config_db#(virtual ibex_icache_if)::get(this, "", "vif", cfg.vif)) begin
+ `uvm_fatal(`gfn, "failed to get ibex_icache_if handle from uvm_config_db")
+ end
+ endfunction
+
+endclass
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/ibex_icache_agent/ibex_icache_agent_cfg.sv b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/ibex_icache_agent/ibex_icache_agent_cfg.sv
new file mode 100644
index 0000000..d5b5f12
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/ibex_icache_agent/ibex_icache_agent_cfg.sv
@@ -0,0 +1,15 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+class ibex_icache_agent_cfg extends dv_base_agent_cfg;
+
+ // interface handle used by driver, monitor & the sequencer, via cfg handle
+ virtual ibex_icache_if vif;
+
+ `uvm_object_utils_begin(ibex_icache_agent_cfg)
+ `uvm_object_utils_end
+
+ `uvm_object_new
+
+endclass
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/ibex_icache_agent/ibex_icache_agent_cov.sv b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/ibex_icache_agent/ibex_icache_agent_cov.sv
new file mode 100644
index 0000000..4176a0d
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/ibex_icache_agent/ibex_icache_agent_cov.sv
@@ -0,0 +1,18 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+class ibex_icache_agent_cov extends dv_base_agent_cov #(ibex_icache_agent_cfg);
+ `uvm_component_utils(ibex_icache_agent_cov)
+
+ // the base class provides the following handles for use:
+ // ibex_icache_agent_cfg: cfg
+
+ // covergroups
+
+ function new(string name, uvm_component parent);
+ super.new(name, parent);
+ // instantiate all covergroups here
+ endfunction : new
+
+endclass
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/ibex_icache_agent/ibex_icache_agent_pkg.sv b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/ibex_icache_agent/ibex_icache_agent_pkg.sv
new file mode 100644
index 0000000..d1d70ac
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/ibex_icache_agent/ibex_icache_agent_pkg.sv
@@ -0,0 +1,37 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+package ibex_icache_agent_pkg;
+ // dep packages
+ import uvm_pkg::*;
+ import dv_utils_pkg::*;
+ import dv_lib_pkg::*;
+
+ // macro includes
+ `include "uvm_macros.svh"
+ `include "dv_macros.svh"
+
+ // parameters
+
+ // local types
+ // forward declare classes to allow typedefs below
+ typedef class ibex_icache_item;
+ typedef class ibex_icache_agent_cfg;
+
+ // reuse dv_base_seqeuencer as is with the right parameter set
+ typedef dv_base_sequencer #(.ITEM_T(ibex_icache_item),
+ .CFG_T (ibex_icache_agent_cfg)) ibex_icache_sequencer;
+
+ // functions
+
+ // package sources
+ `include "ibex_icache_item.sv"
+ `include "ibex_icache_agent_cfg.sv"
+ `include "ibex_icache_agent_cov.sv"
+ `include "ibex_icache_driver.sv"
+ `include "ibex_icache_monitor.sv"
+ `include "ibex_icache_agent.sv"
+ `include "ibex_icache_seq_list.sv"
+
+endpackage: ibex_icache_agent_pkg
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/ibex_icache_agent/ibex_icache_driver.sv b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/ibex_icache_agent/ibex_icache_driver.sv
new file mode 100644
index 0000000..98d8d2b
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/ibex_icache_agent/ibex_icache_driver.sv
@@ -0,0 +1,37 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+class ibex_icache_driver extends dv_base_driver #(ibex_icache_item, ibex_icache_agent_cfg);
+ `uvm_component_utils(ibex_icache_driver)
+
+ // the base class provides the following handles for use:
+ // ibex_icache_agent_cfg: cfg
+
+ `uvm_component_new
+
+ virtual task run_phase(uvm_phase phase);
+ // base class forks off reset_signals() and get_and_drive() tasks
+ super.run_phase(phase);
+ endtask
+
+ // reset signals
+ virtual task reset_signals();
+ endtask
+
+ // drive trans received from sequencer
+ virtual task get_and_drive();
+ forever begin
+ seq_item_port.get_next_item(req);
+ $cast(rsp, req.clone());
+ rsp.set_id_info(req);
+ `uvm_info(`gfn, $sformatf("rcvd item:\n%0s", req.sprint()), UVM_HIGH)
+ // TODO: do the driving part
+ //
+ // send rsp back to seq
+ `uvm_info(`gfn, "item sent", UVM_HIGH)
+ seq_item_port.item_done(rsp);
+ end
+ endtask
+
+endclass
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/ibex_icache_agent/ibex_icache_if.sv b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/ibex_icache_agent/ibex_icache_if.sv
new file mode 100644
index 0000000..0c9ce9c
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/ibex_icache_agent/ibex_icache_if.sv
@@ -0,0 +1,11 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+interface ibex_icache_if ();
+
+ // interface pins
+
+ // debug signals
+
+endinterface
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/ibex_icache_agent/ibex_icache_item.sv b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/ibex_icache_agent/ibex_icache_item.sv
new file mode 100644
index 0000000..8e325f9
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/ibex_icache_agent/ibex_icache_item.sv
@@ -0,0 +1,14 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+class ibex_icache_item extends uvm_sequence_item;
+
+ // random variables
+
+ `uvm_object_utils_begin(ibex_icache_item)
+ `uvm_object_utils_end
+
+ `uvm_object_new
+
+endclass
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/ibex_icache_agent/ibex_icache_monitor.sv b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/ibex_icache_agent/ibex_icache_monitor.sv
new file mode 100644
index 0000000..19aaf87
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/ibex_icache_agent/ibex_icache_monitor.sv
@@ -0,0 +1,43 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+class ibex_icache_monitor extends dv_base_monitor #(
+ .ITEM_T (ibex_icache_item),
+ .CFG_T (ibex_icache_agent_cfg),
+ .COV_T (ibex_icache_agent_cov)
+ );
+ `uvm_component_utils(ibex_icache_monitor)
+
+ // the base class provides the following handles for use:
+ // ibex_icache_agent_cfg: cfg
+ // ibex_icache_agent_cov: cov
+ // uvm_analysis_port #(ibex_icache_item): analysis_port
+
+ `uvm_component_new
+
+ function void build_phase(uvm_phase phase);
+ super.build_phase(phase);
+ endfunction
+
+ task run_phase(uvm_phase phase);
+ super.run_phase(phase);
+ endtask
+
+ // collect transactions forever - already forked in dv_base_moditor::run_phase
+ virtual protected task collect_trans(uvm_phase phase);
+ forever begin
+ // TODO: detect event
+
+ // TODO: sample the interface
+
+ // TODO: sample the covergroups
+
+ // TODO: write trans to analysis_port
+
+ // TODO: remove the line below: it is added to prevent zero delay loop in template code
+ #1us;
+ end
+ endtask
+
+endclass
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/ibex_icache_agent/seq_lib/ibex_icache_base_seq.sv b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/ibex_icache_agent/seq_lib/ibex_icache_base_seq.sv
new file mode 100644
index 0000000..272b32b
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/ibex_icache_agent/seq_lib/ibex_icache_base_seq.sv
@@ -0,0 +1,18 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+class ibex_icache_base_seq extends dv_base_seq #(
+ .REQ (ibex_icache_item),
+ .CFG_T (ibex_icache_agent_cfg),
+ .SEQUENCER_T (ibex_icache_sequencer)
+ );
+ `uvm_object_utils(ibex_icache_base_seq)
+
+ `uvm_object_new
+
+ virtual task body();
+ `uvm_fatal(`gtn, "Need to override this when you extend from this class!")
+ endtask
+
+endclass
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/ibex_icache_agent/seq_lib/ibex_icache_seq_list.sv b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/ibex_icache_agent/seq_lib/ibex_icache_seq_list.sv
new file mode 100644
index 0000000..368e630
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/ibex_icache_agent/seq_lib/ibex_icache_seq_list.sv
@@ -0,0 +1,5 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+`include "ibex_icache_base_seq.sv"
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/ibex_icache_sim.core b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/ibex_icache_sim.core
new file mode 100644
index 0000000..1992b80
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/ibex_icache_sim.core
@@ -0,0 +1,25 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:dv:ibex_icache_sim:0.1"
+description: "IBEX_ICACHE DV sim target"
+filesets:
+ files_rtl:
+ depend:
+ - lowrisc:ibex:ibex_icache:0.1
+
+ files_dv:
+ depend:
+ - lowrisc:dv:ibex_icache_test
+ files:
+ - tb/tb.sv
+ file_type: systemVerilogSource
+
+targets:
+ sim:
+ filesets:
+ - files_rtl
+ - files_dv
+ toplevel: tb
+ default_tool: vcs
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/ibex_icache_sim_cfg.hjson b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/ibex_icache_sim_cfg.hjson
new file mode 100644
index 0000000..b2f94b4
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/ibex_icache_sim_cfg.hjson
@@ -0,0 +1,58 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+{
+ // Name of the sim cfg - typically same as the name of the DUT.
+ name: ibex_icache
+
+ // Top level dut name (sv module).
+ dut: ibex_icache
+
+ // Top level testbench name (sv module).
+ tb: tb
+
+ // Simulator used to sign off this block
+ tool: vcs
+
+ // Fusesoc core file used for building the file list.
+ fusesoc_core: lowrisc:dv:ibex_icache_sim:0.1
+
+ // Testplan hjson file.
+ testplan: "{proj_root}/dv/uvm/icache/data/ibex_icache_testplan.hjson"
+
+
+ // Import additional common sim cfg files.
+ // TODO: remove imported cfgs that do not apply.
+ import_cfgs: [// Project wide common sim cfg file
+ "{proj_root}/dv/uvm/data/common_sim_cfg.hjson"]
+
+ // Default iterations for all tests - each test entry can override this.
+ reseed: 50
+
+ gen_ral_pkg_cmd: ""
+ gen_ral_pkg_dir: ""
+ gen_ral_pkg_opts: []
+
+ // Default UVM test and seq class name.
+ uvm_test: ibex_icache_base_test
+ uvm_test_seq: ibex_icache_base_vseq
+
+ // List of test specifications.
+ tests: [
+ {
+ name: ibex_icache_sanity
+ uvm_test_seq: ibex_icache_sanity_vseq
+ }
+
+ // TODO: add more tests here
+ ]
+
+ // List of regressions.
+ regressions: [
+ {
+ name: sanity
+ tests: ["ibex_icache_sanity"]
+ }
+ ]
+}
+
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/tb/tb.sv b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/tb/tb.sv
new file mode 100644
index 0000000..253471e
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/tb/tb.sv
@@ -0,0 +1,41 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+module tb;
+ // dep packages
+ import uvm_pkg::*;
+ import dv_utils_pkg::*;
+ import ibex_icache_env_pkg::*;
+ import ibex_icache_test_pkg::*;
+
+ // macro includes
+ `include "uvm_macros.svh"
+ `include "dv_macros.svh"
+
+ wire clk, rst_n;
+
+ // interfaces
+ clk_rst_if clk_rst_if(.clk(clk), .rst_n(rst_n));
+ ibex_icache_if ibex_icache_if();
+ ibex_mem_intf ibex_mem_intf();
+
+ // dut
+ ibex_icache dut (
+ .clk_i (clk ),
+ .rst_ni (rst_n )
+
+ // TODO: add remaining IOs and hook them
+ );
+
+ initial begin
+ // drive clk and rst_n from clk_if
+ clk_rst_if.set_active();
+ uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "clk_rst_vif", clk_rst_if);
+ uvm_config_db#(virtual ibex_icache_if)::set(null, "*.env.m_ibex_icache_agent*", "vif", ibex_icache_if);
+ uvm_config_db#(virtual ibex_mem_intf)::set(null, "*.env.m_ibex_mem_intf_slave_agent*", "vif", ibex_mem_intf);
+ $timeformat(-12, 0, " ps", 12);
+ run_test();
+ end
+
+endmodule
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/tests/ibex_icache_base_test.sv b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/tests/ibex_icache_base_test.sv
new file mode 100644
index 0000000..7939614
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/tests/ibex_icache_base_test.sv
@@ -0,0 +1,26 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+class ibex_icache_base_test extends dv_base_test #(
+ .CFG_T(ibex_icache_env_cfg),
+ .ENV_T(ibex_icache_env)
+ );
+
+ `uvm_component_utils(ibex_icache_base_test)
+ `uvm_component_new
+
+ // the base class dv_base_test creates the following instances:
+ // ibex_icache_env_cfg: cfg
+ // ibex_icache_env: env
+
+ virtual function void build_phase(uvm_phase phase);
+ super.build_phase(phase);
+ cfg.has_ral = 1'b0;
+ endfunction
+
+ // the base class also looks up UVM_TEST_SEQ plusarg to create and run that seq in
+ // the run_phase; as such, nothing more needs to be done
+
+endclass : ibex_icache_base_test
+
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/tests/ibex_icache_test.core b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/tests/ibex_icache_test.core
new file mode 100644
index 0000000..a1a68a4
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/tests/ibex_icache_test.core
@@ -0,0 +1,19 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:dv:ibex_icache_test:0.1"
+description: "IBEX_ICACHE DV UVM test"
+filesets:
+ files_dv:
+ depend:
+ - lowrisc:dv:ibex_icache_env
+ files:
+ - ibex_icache_test_pkg.sv
+ - ibex_icache_base_test.sv: {is_include_file: true}
+ file_type: systemVerilogSource
+
+targets:
+ default:
+ filesets:
+ - files_dv
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/tests/ibex_icache_test_pkg.sv b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/tests/ibex_icache_test_pkg.sv
new file mode 100644
index 0000000..c00229a
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/tests/ibex_icache_test_pkg.sv
@@ -0,0 +1,22 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+package ibex_icache_test_pkg;
+ // dep packages
+ import uvm_pkg::*;
+ import dv_lib_pkg::*;
+ import ibex_icache_env_pkg::*;
+
+ // macro includes
+ `include "uvm_macros.svh"
+ `include "dv_macros.svh"
+
+ // local types
+
+ // functions
+
+ // package sources
+ `include "ibex_icache_base_test.sv"
+
+endpackage
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/top_pkg.core b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/top_pkg.core
new file mode 100644
index 0000000..b9aacee
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/top_pkg.core
@@ -0,0 +1,20 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+# XXX: This name is currently required as global identifier until we have
+# support for "interfaces" or a similar concept.
+# Tracked in https://github.com/olofk/fusesoc/issues/235
+name: "lowrisc:constants:top_pkg"
+description: "Toplevel-wide constants needed for dv_utils"
+filesets:
+ files_rtl:
+ files:
+ - top_pkg.sv
+ file_type: systemVerilogSource
+
+targets:
+ default:
+ filesets:
+ - files_rtl
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/top_pkg.sv b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/top_pkg.sv
new file mode 100644
index 0000000..01f6246
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/icache/dv/top_pkg.sv
@@ -0,0 +1,25 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+
+package top_pkg;
+
+localparam TL_AW=32;
+localparam TL_DW=32; // = TL_DBW * 8; TL_DBW must be a power-of-two
+localparam TL_AIW=8; // a_source, d_source
+localparam TL_DIW=1; // d_sink
+localparam TL_DUW=16; // d_user
+localparam TL_DBW=(TL_DW>>3);
+localparam TL_SZW=$clog2($clog2(TL_DBW)+1);
+localparam FLASH_BANKS=2;
+localparam FLASH_PAGES_PER_BANK=256;
+localparam FLASH_WORDS_PER_PAGE=256;
+localparam FLASH_BYTES_PER_WORD=4;
+localparam FLASH_BKW = $clog2(FLASH_BANKS);
+localparam FLASH_PGW = $clog2(FLASH_PAGES_PER_BANK);
+localparam FLASH_WDW = $clog2(FLASH_WORDS_PER_PAGE);
+localparam FLASH_AW = FLASH_BKW + FLASH_PGW + FLASH_WDW;
+localparam FLASH_DW = FLASH_BYTES_PER_WORD * 8;
+
+endpackage
diff --git a/hw/vendor/lowrisc_ibex/dv/verilator/pcount/cpp/ibex_pcounts.cc b/hw/vendor/lowrisc_ibex/dv/verilator/pcount/cpp/ibex_pcounts.cc
index 8f2cf69..e5629df 100644
--- a/hw/vendor/lowrisc_ibex/dv/verilator/pcount/cpp/ibex_pcounts.cc
+++ b/hw/vendor/lowrisc_ibex/dv/verilator/pcount/cpp/ibex_pcounts.cc
@@ -22,7 +22,9 @@
"Jumps",
"Conditional Branches",
"Taken Conditional Branches",
- "Compressed Instructions"};
+ "Compressed Instructions",
+ "Multiply Wait",
+ "Divide Wait"};
std::string ibex_pcount_string(uint64_t pcounts[], bool csv) {
char seperator = csv ? ',' : ':';
diff --git a/hw/vendor/lowrisc_ibex/dv/verilator/simutil_verilator/cpp/verilator_sim_ctrl.cc b/hw/vendor/lowrisc_ibex/dv/verilator/simutil_verilator/cpp/verilator_sim_ctrl.cc
index ceb27f9..545fa4a 100644
--- a/hw/vendor/lowrisc_ibex/dv/verilator/simutil_verilator/cpp/verilator_sim_ctrl.cc
+++ b/hw/vendor/lowrisc_ibex/dv/verilator/simutil_verilator/cpp/verilator_sim_ctrl.cc
@@ -283,10 +283,10 @@
UnsetReset();
Trace();
while (1) {
- if (time_ >= initial_reset_delay_cycles_ * 2) {
+ if (time_ / 2 >= initial_reset_delay_cycles_) {
SetReset();
}
- if (time_ >= reset_duration_cycles_ * 2 + initial_reset_delay_cycles_ * 2) {
+ if (time_ / 2 >= reset_duration_cycles_ + initial_reset_delay_cycles_) {
UnsetReset();
}
@@ -315,7 +315,7 @@
<< std::endl;
break;
}
- if (term_after_cycles_ && time_ > term_after_cycles_) {
+ if (term_after_cycles_ && (time_ / 2 >= term_after_cycles_)) {
std::cout << "Simulation timeout of " << term_after_cycles_
<< " cycles reached, shutting down simulation." << std::endl;
break;
diff --git a/hw/vendor/lowrisc_ibex/examples/simple_system/ibex_simple_system.core b/hw/vendor/lowrisc_ibex/examples/simple_system/ibex_simple_system.core
index 736367c..04ba021 100644
--- a/hw/vendor/lowrisc_ibex/examples/simple_system/ibex_simple_system.core
+++ b/hw/vendor/lowrisc_ibex/examples/simple_system/ibex_simple_system.core
@@ -24,24 +24,39 @@
parameters:
RV32M:
- datatype: int
+ datatype: bool
paramtype: vlogparam
- default: 1
+ default: true
description: Enable the M ISA extension (hardware multiply/divide) [0/1]
RV32E:
- datatype: int
+ datatype: bool
paramtype: vlogparam
- default: 0
+ default: false
description: Enable the E ISA extension (reduced register set) [0/1]
+ RV32B:
+ datatype: bool
+ paramtype: vlogparam
+ default: false
+ description: Enable the B ISA extension (bit manipulation EXPERIMENTAL) [0/1]
SRAM_INIT_FILE:
datatype: str
paramtype: vlogdefine
description: Path to a vmem file to initialize the RAM with
- BranchTargetALU:
- datatype: int
+ MultiplierImplementation:
+ datatype: str
paramtype: vlogparam
- default: 0
- description: Enables seperate branch target ALU (increasing branch performance EXPERIMENTAL) [0/1]
+ description: "Multiplier implementation. Valid values: fast, slow, single-cycle"
+ default: "fast"
+ BranchTargetALU:
+ datatype: bool
+ paramtype: vlogparam
+ default: false
+ description: Enables seperate branch target ALU (increasing branch performance EXPERIMENTAL)
+ WritebackStage:
+ datatype: bool
+ paramtype: vlogparam
+ default: false
+ description: Enables third pipeline stage (EXPERIMENTAL)
targets:
sim:
@@ -52,7 +67,9 @@
parameters:
- RV32M
- RV32E
+ - MultiplierImplementation
- BranchTargetALU
+ - WritebackStage
- SRAM_INIT_FILE
toplevel: ibex_simple_system
tools:
@@ -81,4 +98,7 @@
# XXX: Cleanup all warnings and remove this option
# (or make it more fine-grained at least)
- "-Wno-fatal"
+ # RAM primitives wider than 64bit (required for ECC) fail to build in
+ # Verilator without increasing the unroll count (see Verilator#1266)
+ - "--unroll-count 72"
diff --git a/hw/vendor/lowrisc_ibex/examples/simple_system/rtl/ibex_simple_system.sv b/hw/vendor/lowrisc_ibex/examples/simple_system/rtl/ibex_simple_system.sv
index fd4abcb..f6a1b30 100644
--- a/hw/vendor/lowrisc_ibex/examples/simple_system/rtl/ibex_simple_system.sv
+++ b/hw/vendor/lowrisc_ibex/examples/simple_system/rtl/ibex_simple_system.sv
@@ -13,14 +13,18 @@
* simulators, a small amount of work may be required to support the
* simulator_ctrl module.
*/
+
module ibex_simple_system (
input IO_CLK,
input IO_RST_N
);
- parameter bit RV32E = 1'b0;
- parameter bit RV32M = 1'b1;
- parameter bit BranchTargetALU = 1'b0;
+ parameter bit RV32E = 1'b0;
+ parameter bit RV32M = 1'b1;
+ parameter bit RV32B = 1'b0;
+ parameter bit BranchTargetALU = 1'b0;
+ parameter bit WritebackStage = 1'b0;
+ parameter MultiplierImplementation = "fast";
logic clk_sys = 1'b0, rst_sys_n;
@@ -102,10 +106,10 @@
assign device_err[SimCtrl] = 1'b0;
bus #(
- .NrDevices (NrDevices),
- .NrHosts (NrHosts ),
- .DataWidth (32 ),
- .AddressWidth(32 )
+ .NrDevices ( NrDevices ),
+ .NrHosts ( NrHosts ),
+ .DataWidth ( 32 ),
+ .AddressWidth ( 32 )
) u_bus (
.clk_i (clk_sys),
.rst_ni (rst_sys_n),
@@ -134,12 +138,15 @@
);
ibex_core_tracing #(
- .MHPMCounterNum(29),
- .DmHaltAddr(32'h00100000),
- .DmExceptionAddr(32'h00100000),
- .RV32E(RV32E),
- .RV32M(RV32M),
- .BranchTargetALU(BranchTargetALU)
+ .MHPMCounterNum ( 29 ),
+ .DmHaltAddr ( 32'h00100000 ),
+ .DmExceptionAddr ( 32'h00100000 ),
+ .RV32E ( RV32E ),
+ .RV32M ( RV32M ),
+ .RV32B ( RV32B ),
+ .BranchTargetALU ( BranchTargetALU ),
+ .WritebackStage ( WritebackStage ),
+ .MultiplierImplementation ( MultiplierImplementation )
) u_core (
.clk_i (clk_sys),
.rst_ni (rst_sys_n),
diff --git a/hw/vendor/lowrisc_ibex/examples/sw/benchmarks/README.md b/hw/vendor/lowrisc_ibex/examples/sw/benchmarks/README.md
new file mode 100644
index 0000000..2d9ecca
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/examples/sw/benchmarks/README.md
@@ -0,0 +1,91 @@
+# Benchmarks
+
+This directory contains benchmarks that can be run on ibex simple system.
+Benchmarks may rely on code external to this directory (e.g. it may be found in
+`vendor/`) see the specific benchmark information below for details on how to
+build and run each benchmark and where benchmark code is located.
+
+## Building Simulation
+
+All of these benchmarks run on Simple System. A verilator simulation suitable
+for running them can be built with:
+
+```
+fusesoc --cores-root=. run --target=sim --setup --build lowrisc:ibex:ibex_simple_system --RV32M=1 --RV32E=0
+```
+
+See examples/simple_system/README.md for full details.
+
+## Coremark
+
+Coremark (https://www.eembc.org/coremark/ https://github.com/eembc/coremark) is
+an industry standard benchmark with results available for a wide variety of
+systems.
+
+The Coremark source is vendored into the Ibex repository at
+`vendor/eembc_coremark`. Support structure and a makefile to build Coremark for
+running on simple system is found in `examples/sw/benchmarks/coremark`.
+
+To build Coremark:
+
+```
+make -C ./examples/sw/benchmarks/coremark/
+```
+
+To run Coremark (after building a suitable simulator binary, see above):
+
+```
+build/lowrisc_ibex_ibex_simple_system_0/sim-verilator/Vibex_simple_system --meminit=ram,examples/sw/benchmarks/coremark/coremark.elf
+```
+
+The simulator outputs the performance counter values observed for the benchmark
+(the counts do not include anything from pre or post benchmark loops).
+
+Coremark should output (to `ibex_simple_system.log`) something like the
+following:
+
+```
+2K performance run parameters for coremark.
+CoreMark Size : 666
+Total ticks : 4244465
+Total time (secs): 8
+Iterations/Sec : 1
+Iterations : 10
+Compiler version : GCC
+Compiler flags :
+Memory location :
+seedcrc : 0xe9f5
+[0]crclist : 0xe714
+[0]crcmatrix : 0x1fd7
+[0]crcstate : 0x8e3a
+[0]crcfinal : 0xfcaf
+Correct operation validated. See README.md for run and reporting rules.
+```
+
+A Coremark score is given as the number of iterations executed per second. The
+Coremark binary is hard-coded to execute 10 iterations (see
+`examples/sw/benchmarks/coremark/Makefile` if you wish to alter this). To obtain
+a useful Coremark score from the simulation you need to choose a clock speed the
+Ibex implementation you are interested in would run at, e.g. 100 MHz, taking
+the above example:
+
+* 10 iterations take 4244465 clock cycles
+* So at 100 MHz Ibex would execute (100 * 10^6) / (4244465 / 10) = 235.6
+ Iterations in 1 second.
+* Coremark (at 100 MHz) is 235.6
+
+Coremark/MHz is often used instead of a raw Coremark score. The example above
+gives a Coremark/MHz of 2.36 (235.6 / 100 rounded to 2 decimal places).
+
+To directly produce Coremark/MHz from the number of iterations (I) and total
+ticks (T) use the follow formula:
+
+```
+Coremark/MHz = (10 ^ 6) * I / T
+```
+
+Note that `core_main.c` from Coremark has had a minor modification to prevent it
+from reporting an error if it executes for less than 10 seconds. This violates
+the run reporting rules (though does not effect benchmark execution). It is
+trivial to restore `core_main.c` to the version supplied by EEMBC in the
+Coremark repository if an official result is desired.
diff --git a/hw/vendor/lowrisc_ibex/examples/sw/benchmarks/coremark/Makefile b/hw/vendor/lowrisc_ibex/examples/sw/benchmarks/coremark/Makefile
new file mode 100644
index 0000000..9c7f644
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/examples/sw/benchmarks/coremark/Makefile
@@ -0,0 +1,19 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Build coremark benchmark for Ibex Simple System
+
+COREMARK_DIR = ../../../../vendor/eembc_coremark
+
+export PORT_DIR = $(CURDIR)/ibex
+export ITERATIONS = 10
+export OPATH = $(CURDIR)/
+
+# Export OPATH above doesn't seem to work so need to explicitly give it on the
+# make command line
+all:
+ $(MAKE) -C $(COREMARK_DIR)
+
+clean:
+ $(MAKE) -C $(COREMARK_DIR) clean
diff --git a/hw/vendor/lowrisc_ibex/examples/sw/benchmarks/coremark/ibex/core_portme.c b/hw/vendor/lowrisc_ibex/examples/sw/benchmarks/coremark/ibex/core_portme.c
new file mode 100644
index 0000000..353c31b
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/examples/sw/benchmarks/coremark/ibex/core_portme.c
@@ -0,0 +1,187 @@
+// Copyright lowRISC contributors.
+// Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
+// Original Author: Shay Gal-on
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+#include "core_portme.h"
+
+#include "coremark.h"
+
+#include "simple_system_common.h"
+
+#if VALIDATION_RUN
+volatile ee_s32 seed1_volatile = 0x3415;
+volatile ee_s32 seed2_volatile = 0x3415;
+volatile ee_s32 seed3_volatile = 0x66;
+#endif
+#if PERFORMANCE_RUN
+volatile ee_s32 seed1_volatile = 0x0;
+volatile ee_s32 seed2_volatile = 0x0;
+volatile ee_s32 seed3_volatile = 0x66;
+#endif
+#if PROFILE_RUN
+volatile ee_s32 seed1_volatile = 0x8;
+volatile ee_s32 seed2_volatile = 0x8;
+volatile ee_s32 seed3_volatile = 0x8;
+#endif
+volatile ee_s32 seed4_volatile = ITERATIONS;
+volatile ee_s32 seed5_volatile = 0;
+/* Porting : Timing functions
+ How to capture time and convert to seconds must be ported to whatever is
+ supported by the platform. e.g. Read value from on board RTC, read value from
+ cpu clock cycles performance counter etc. Sample implementation for standard
+ time.h and windows.h definitions included.
+*/
+CORETIMETYPE barebones_clock() {
+ ee_u32 result;
+
+ PCOUNT_READ(mcycle, result);
+
+ return result;
+}
+
+/* Define : TIMER_RES_DIVIDER
+ Divider to trade off timer resolution and total time that can be
+ measured.
+
+ Use lower values to increase resolution, but make sure that overflow
+ does not occur. If there are issues with the return value overflowing,
+ increase this value.
+ */
+#define GETMYTIME(_t) (*_t = barebones_clock())
+#define MYTIMEDIFF(fin, ini) ((fin) - (ini))
+#define TIMER_RES_DIVIDER 1
+#define SAMPLE_TIME_IMPLEMENTATION 1
+#define CLOCKS_PER_SEC 500000
+#define EE_TICKS_PER_SEC (CLOCKS_PER_SEC / TIMER_RES_DIVIDER)
+
+void pcount_read(uint32_t pcount_out[]) {
+ PCOUNT_READ(minstret, pcount_out[0]);
+ PCOUNT_READ(mhpmcounter3, pcount_out[1]);
+ PCOUNT_READ(mhpmcounter4, pcount_out[2]);
+ PCOUNT_READ(mhpmcounter5, pcount_out[3]);
+ PCOUNT_READ(mhpmcounter6, pcount_out[4]);
+ PCOUNT_READ(mhpmcounter7, pcount_out[5]);
+ PCOUNT_READ(mhpmcounter8, pcount_out[6]);
+ PCOUNT_READ(mhpmcounter9, pcount_out[7]);
+ PCOUNT_READ(mhpmcounter10, pcount_out[8]);
+ PCOUNT_READ(mhpmcounter11, pcount_out[9]);
+ PCOUNT_READ(mhpmcounter12, pcount_out[10]);
+}
+
+const char *pcount_names[] = {"Instructions Retired",
+ "LSU Busy",
+ "IFetch wait",
+ "Loads",
+ "Stores",
+ "Jumps",
+ "Branches",
+ "Taken Branches",
+ "Compressed Instructions",
+ "Multiply Wait",
+ "Divide Wait"};
+
+const uint32_t pcount_num = sizeof(pcount_names) / sizeof(char *);
+
+void dump_pcounts() {
+ uint32_t pcounts[pcount_num];
+
+ pcount_read(pcounts);
+ ee_printf(
+ "Performance Counters\n"
+ "--------------------\n");
+ for (uint32_t i = 0; i < pcount_num; ++i) {
+ ee_printf("%s: %u\n", pcount_names[i], pcounts[i]);
+ }
+ ee_printf("\n");
+}
+
+/** Define Host specific (POSIX), or target specific global time variables. */
+static CORETIMETYPE start_time_val, stop_time_val;
+
+/* Function : start_time
+ This function will be called right before starting the timed portion of
+ the benchmark.
+
+ Implementation may be capturing a system timer (as implemented in the
+ example code) or zeroing some system parameters - e.g. setting the cpu clocks
+ cycles to 0.
+*/
+void start_time(void) {
+ pcount_enable(0);
+ pcount_reset();
+ pcount_enable(1);
+ GETMYTIME(&start_time_val);
+}
+
+/* Function : stop_time
+ This function will be called right after ending the timed portion of the
+ benchmark.
+
+ Implementation may be capturing a system timer (as implemented in the
+ example code) or other system parameters - e.g. reading the current value of
+ cpu cycles counter.
+*/
+void stop_time(void) {
+ GETMYTIME(&stop_time_val);
+ pcount_enable(0);
+}
+
+/* Function : get_time
+ Return an abstract "ticks" number that signifies time on the system.
+
+ Actual value returned may be cpu cycles, milliseconds or any other
+ value, as long as it can be converted to seconds by <time_in_secs>. This
+ methodology is taken to accomodate any hardware or simulated platform. The
+ sample implementation returns millisecs by default, and the resolution is
+ controlled by <TIMER_RES_DIVIDER>
+*/
+CORE_TICKS get_time(void) {
+ CORE_TICKS elapsed = (CORE_TICKS)(MYTIMEDIFF(stop_time_val, start_time_val));
+ return elapsed;
+}
+/* Function : time_in_secs
+ Convert the value returned by get_time to seconds.
+
+ The <secs_ret> type is used to accomodate systems with no support for
+ floating point. Default implementation implemented by the EE_TICKS_PER_SEC
+ macro above.
+*/
+secs_ret time_in_secs(CORE_TICKS ticks) {
+ secs_ret retval = ((secs_ret)ticks) / (secs_ret)EE_TICKS_PER_SEC;
+ return retval;
+}
+
+ee_u32 default_num_contexts = 1;
+
+/* Function : portable_init
+ Target specific initialization code
+ Test for some common mistakes.
+*/
+void portable_init(core_portable *p, int *argc, char *argv[]) {
+ ee_printf("Ibex coremark platform init...\n");
+ if (sizeof(ee_ptr_int) != sizeof(ee_u8 *)) {
+ ee_printf(
+ "ERROR! Please define ee_ptr_int to a type that holds a pointer!\n");
+ }
+ if (sizeof(ee_u32) != 4) {
+ ee_printf("ERROR! Please define ee_u32 to a 32b unsigned type!\n");
+ }
+ p->portable_id = 1;
+}
+/* Function : portable_fini
+ Target specific final code
+*/
+void portable_fini(core_portable *p) {
+ dump_pcounts();
+
+ CORE_TICKS elapsed = get_time();
+ float coremark_mhz;
+
+ coremark_mhz = (1000000.0f * (float)ITERATIONS) / elapsed;
+
+ ee_printf("Coremark / MHz: %f\n", coremark_mhz);
+
+ p->portable_id = 0;
+}
diff --git a/hw/vendor/lowrisc_ibex/examples/sw/benchmarks/coremark/ibex/core_portme.h b/hw/vendor/lowrisc_ibex/examples/sw/benchmarks/coremark/ibex/core_portme.h
new file mode 100644
index 0000000..894b880
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/examples/sw/benchmarks/coremark/ibex/core_portme.h
@@ -0,0 +1,201 @@
+// Copyright lowRISC contributors.
+// Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
+// Original Author: Shay Gal-on
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+/* Topic : Description
+ This file contains configuration constants required to execute on
+ different platforms
+*/
+
+#ifndef CORE_PORTME_H
+#define CORE_PORTME_H
+
+#include <sys/types.h>
+
+extern unsigned int _stack_start;
+
+/************************/
+/* Data types and settings */
+/************************/
+/* Configuration : HAS_FLOAT
+ Define to 1 if the platform supports floating point.
+*/
+#ifndef HAS_FLOAT
+#define HAS_FLOAT 1
+#endif
+/* Configuration : HAS_TIME_H
+ Define to 1 if platform has the time.h header file,
+ and implementation of functions thereof.
+*/
+#ifndef HAS_TIME_H
+#define HAS_TIME_H 0
+#endif
+/* Configuration : USE_CLOCK
+ Define to 1 if platform has the time.h header file,
+ and implementation of functions thereof.
+*/
+#ifndef USE_CLOCK
+#define USE_CLOCK 0
+#endif
+/* Configuration : HAS_STDIO
+ Define to 1 if the platform has stdio.h.
+*/
+#ifndef HAS_STDIO
+#define HAS_STDIO 0
+#endif
+/* Configuration : HAS_PRINTF
+ Define to 1 if the platform has stdio.h and implements the printf
+ function.
+*/
+#ifndef HAS_PRINTF
+#define HAS_PRINTF 0
+#endif
+
+/* Definitions : COMPILER_VERSION, COMPILER_FLAGS, MEM_LOCATION
+ Initialize these strings per platform
+*/
+#ifndef COMPILER_VERSION
+#ifdef __GNUC__
+#define COMPILER_VERSION "GCC"
+#else
+#define COMPILER_VERSION "unknown"
+#endif
+#endif
+#ifndef COMPILER_FLAGS
+#define COMPILER_FLAGS "" /* "Please put compiler flags here (e.g. -o3)" */
+#endif
+#ifndef MEM_LOCATION
+#define MEM_LOCATION "STACK"
+#endif
+
+/* Data Types :
+ To avoid compiler issues, define the data types that need to be used for
+ 8b, 16b and 32b in <core_portme.h>.
+
+ *Imprtant* :
+ ee_ptr_int needs to be the data type used to hold pointers, otherwise
+ coremark may fail!!!
+*/
+typedef signed short ee_s16;
+typedef unsigned short ee_u16;
+typedef signed int ee_s32;
+typedef double ee_f32;
+typedef unsigned char ee_u8;
+typedef unsigned int ee_u32;
+typedef ee_u32 ee_ptr_int;
+typedef size_t ee_size_t;
+#define NULL ((void *)0)
+/* align_mem :
+ This macro is used to align an offset to point to a 32b value. It is
+ used in the Matrix algorithm to initialize the input memory blocks.
+*/
+#define align_mem(x) (void *)(4 + (((ee_ptr_int)(x)-1) & ~3))
+
+/* Configuration : CORE_TICKS
+ Define type of return from the timing functions.
+ */
+#define CORETIMETYPE ee_u32
+typedef ee_u32 CORE_TICKS;
+
+/* Configuration : SEED_METHOD
+ Defines method to get seed values that cannot be computed at compile
+ time.
+
+ Valid values :
+ SEED_ARG - from command line.
+ SEED_FUNC - from a system function.
+ SEED_VOLATILE - from volatile variables.
+*/
+#ifndef SEED_METHOD
+#define SEED_METHOD SEED_VOLATILE
+#endif
+
+/* Configuration : MEM_METHOD
+ Defines method to get a block of memry.
+
+ Valid values :
+ MEM_MALLOC - for platforms that implement malloc and have malloc.h.
+ MEM_STATIC - to use a static memory array.
+ MEM_STACK - to allocate the data block on the stack (NYI).
+*/
+#ifndef MEM_METHOD
+#define MEM_METHOD MEM_STACK
+#endif
+
+/* Configuration : MULTITHREAD
+ Define for parallel execution
+
+ Valid values :
+ 1 - only one context (default).
+ N>1 - will execute N copies in parallel.
+
+ Note :
+ If this flag is defined to more then 1, an implementation for launching
+ parallel contexts must be defined.
+
+ Two sample implementations are provided. Use <USE_PTHREAD> or <USE_FORK>
+ to enable them.
+
+ It is valid to have a different implementation of <core_start_parallel>
+ and <core_end_parallel> in <core_portme.c>, to fit a particular architecture.
+*/
+#ifndef MULTITHREAD
+#define MULTITHREAD 1
+#define USE_PTHREAD 0
+#define USE_FORK 0
+#define USE_SOCKET 0
+#endif
+
+/* Configuration : MAIN_HAS_NOARGC
+ Needed if platform does not support getting arguments to main.
+
+ Valid values :
+ 0 - argc/argv to main is supported
+ 1 - argc/argv to main is not supported
+
+ Note :
+ This flag only matters if MULTITHREAD has been defined to a value
+ greater then 1.
+*/
+#ifndef MAIN_HAS_NOARGC
+#define MAIN_HAS_NOARGC 0
+#endif
+
+/* Configuration : MAIN_HAS_NORETURN
+ Needed if platform does not support returning a value from main.
+
+ Valid values :
+ 0 - main returns an int, and return value will be 0.
+ 1 - platform does not support returning a value from main
+*/
+#ifndef MAIN_HAS_NORETURN
+#define MAIN_HAS_NORETURN 0
+#endif
+
+/* Variable : default_num_contexts
+ Not used for this simple port, must cintain the value 1.
+*/
+extern ee_u32 default_num_contexts;
+
+typedef struct CORE_PORTABLE_S { ee_u8 portable_id; } core_portable;
+
+/* target specific init/fini */
+void portable_init(core_portable *p, int *argc, char *argv[]);
+void portable_fini(core_portable *p);
+
+#if !defined(PROFILE_RUN) && !defined(PERFORMANCE_RUN) && \
+ !defined(VALIDATION_RUN)
+#if (TOTAL_DATA_SIZE == 1200)
+#define PROFILE_RUN 1
+#elif (TOTAL_DATA_SIZE == 2000)
+#define PERFORMANCE_RUN 1
+#else
+#define VALIDATION_RUN 1
+#endif
+#endif
+
+int ee_printf(const char *fmt, ...);
+
+#endif /* CORE_PORTME_H */
diff --git a/hw/vendor/lowrisc_ibex/examples/sw/benchmarks/coremark/ibex/core_portme.mak b/hw/vendor/lowrisc_ibex/examples/sw/benchmarks/coremark/ibex/core_portme.mak
new file mode 100755
index 0000000..97dc316
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/examples/sw/benchmarks/coremark/ibex/core_portme.mak
@@ -0,0 +1,90 @@
+# Copyright lowRISC contributors.
+# Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
+# Original Author: Shay Gal-on
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+OUTFILES = $(OPATH)coremark.dis $(OPATH)coremark.map
+
+NAME = coremark
+PORT_CLEAN := $(OUTFILES)
+SIMPLE_SYSTEM_COMMON = ../../examples/sw/simple_system/common
+EXT_SRCS = $(wildcard $(SIMPLE_SYSTEM_COMMON)/*.c)
+CRT0 = $(SIMPLE_SYSTEM_COMMON)/crt0.S
+LINKER_SCRIPT = $(SIMPLE_SYSTEM_COMMON)/link.ld
+
+# Flag : OUTFLAG
+# Use this flag to define how to to get an executable (e.g -o)
+OUTFLAG = -o
+# Flag : CC
+# Use this flag to define compiler to use
+CC = riscv32-unknown-elf-gcc
+# Flag : LD
+# Use this flag to define compiler to use
+LD = riscv32-unknown-elf-ld
+# Flag : AS
+# Use this flag to define compiler to use
+AS = riscv32-unknown-elf-as
+# Flag : CFLAGS
+# Use this flag to define compiler options. Note, you can add compiler options from the command line using XCFLAGS="other flags"
+PORT_CFLAGS = -g -march=rv32imc -mabi=ilp32 -static -mcmodel=medlow -mtune=sifive-3-series \
+ -O3 -falign-functions=16 -funroll-all-loops \
+ -finline-functions -falign-jumps=4 \
+ -nostdlib -nostartfiles -ffreestanding -mstrict-align \
+ -DTOTAL_DATA_SIZE=2000 -DMAIN_HAS_NOARGC=1 \
+ -DPERFORMANCE_RUN=1
+
+FLAGS_STR = "$(PORT_CFLAGS) $(XCFLAGS) $(XLFLAGS) $(LFLAGS_END)"
+CFLAGS += $(PORT_CFLAGS) $(XCFLAGS) -I$(SIMPLE_SYSTEM_COMMON) -I$(PORT_DIR) -I.
+#Flag : LFLAGS_END
+# Define any libraries needed for linking or other flags that should come at the end of the link line (e.g. linker scripts).
+# Note : On certain platforms, the default clock_gettime implementation is supported but requires linking of librt.
+#SEPARATE_COMPILE=1
+# Flag : SEPARATE_COMPILE
+# You must also define below how to create an object file, and how to link.
+OBJOUT = -o
+LFLAGS =
+ASFLAGS =
+OFLAG = -o
+COUT = -c
+
+LFLAGS_END = -T $(LINKER_SCRIPT) -Xlinker -Map=$(OPATH)coremark.map -lm -lgcc
+# Flag : PORT_SRCS
+# Port specific source files can be added here
+# You may also need cvt.c if the fcvt functions are not provided as intrinsics by your compiler!
+PORT_SRCS = $(PORT_DIR)/core_portme.c $(PORT_DIR)/ee_printf.c ./barebones/cvt.c $(CRT0) $(EXT_SRCS)
+vpath %.c $(PORT_DIR)
+vpath %.s $(PORT_DIR)
+
+# Flag : LOAD
+# For a simple port, we assume self hosted compile and run, no load needed.
+
+# Flag : RUN
+# For a simple port, we assume self hosted compile and run, simple invocation of the executable
+
+LOAD = echo "Please set LOAD to the process of loading the executable to the flash"
+RUN = echo "Please set LOAD to the process of running the executable (e.g. via jtag, or board reset)"
+
+OEXT = .o
+EXE = .elf
+
+$(OPATH)$(PORT_DIR)/%$(OEXT) : %.c
+ $(CC) $(CFLAGS) $(XCFLAGS) $(COUT) $< $(OBJOUT) $@
+
+$(OPATH)%$(OEXT) : %.c
+ $(CC) $(CFLAGS) $(XCFLAGS) $(COUT) $< $(OBJOUT) $@
+
+$(OPATH)$(PORT_DIR)/%$(OEXT) : %.s
+ $(AS) $(ASFLAGS) $< $(OBJOUT) $@
+
+# Target : port_pre% and port_post%
+# For the purpose of this simple port, no pre or post steps needed.
+
+.PHONY : port_clean port_prebuild port_postbuild port_prerun port_postrun port_preload port_postload
+
+port_postbuild:
+ riscv32-unknown-elf-objdump -SD $(OPATH)coremark.elf > $(OPATH)coremark.dis
+
+# FLAG : OPATH
+# Path to the output folder. Default - current folder.
+MKDIR = mkdir -p
diff --git a/hw/vendor/lowrisc_ibex/examples/sw/benchmarks/coremark/ibex/ee_printf.c b/hw/vendor/lowrisc_ibex/examples/sw/benchmarks/coremark/ibex/ee_printf.c
new file mode 100644
index 0000000..913baef
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/examples/sw/benchmarks/coremark/ibex/ee_printf.c
@@ -0,0 +1,579 @@
+// Copyright lowRISC contributors.
+// Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
+// Original Author: Shay Gal-on
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+#include <coremark.h>
+#include <stdarg.h>
+
+#include "simple_system_common.h"
+
+#define ZEROPAD (1 << 0) /* Pad with zero */
+#define SIGN (1 << 1) /* Unsigned/signed long */
+#define PLUS (1 << 2) /* Show plus */
+#define SPACE (1 << 3) /* Spacer */
+#define LEFT (1 << 4) /* Left justified */
+#define HEX_PREP (1 << 5) /* 0x */
+#define UPPERCASE (1 << 6) /* 'ABCDEF' */
+
+#define is_digit(c) ((c) >= '0' && (c) <= '9')
+
+static char *digits = "0123456789abcdefghijklmnopqrstuvwxyz";
+static char *upper_digits = "0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ";
+static ee_size_t strnlen(const char *s, ee_size_t count);
+
+static ee_size_t strnlen(const char *s, ee_size_t count) {
+ const char *sc;
+ for (sc = s; *sc != '\0' && count--; ++sc)
+ ;
+ return sc - s;
+}
+
+static int skip_atoi(const char **s) {
+ int i = 0;
+ while (is_digit(**s))
+ i = i * 10 + *((*s)++) - '0';
+ return i;
+}
+
+static char *number(char *str, long num, int base, int size, int precision,
+ int type) {
+ char c, sign, tmp[66];
+ char *dig = digits;
+ int i;
+
+ if (type & UPPERCASE)
+ dig = upper_digits;
+ if (type & LEFT)
+ type &= ~ZEROPAD;
+ if (base < 2 || base > 36)
+ return 0;
+
+ c = (type & ZEROPAD) ? '0' : ' ';
+ sign = 0;
+ if (type & SIGN) {
+ if (num < 0) {
+ sign = '-';
+ num = -num;
+ size--;
+ } else if (type & PLUS) {
+ sign = '+';
+ size--;
+ } else if (type & SPACE) {
+ sign = ' ';
+ size--;
+ }
+ }
+
+ if (type & HEX_PREP) {
+ if (base == 16)
+ size -= 2;
+ else if (base == 8)
+ size--;
+ }
+
+ i = 0;
+
+ if (num == 0)
+ tmp[i++] = '0';
+ else {
+ while (num != 0) {
+ tmp[i++] = dig[((unsigned long)num) % (unsigned)base];
+ num = ((unsigned long)num) / (unsigned)base;
+ }
+ }
+
+ if (i > precision)
+ precision = i;
+ size -= precision;
+ if (!(type & (ZEROPAD | LEFT)))
+ while (size-- > 0)
+ *str++ = ' ';
+ if (sign)
+ *str++ = sign;
+
+ if (type & HEX_PREP) {
+ if (base == 8)
+ *str++ = '0';
+ else if (base == 16) {
+ *str++ = '0';
+ *str++ = digits[33];
+ }
+ }
+
+ if (!(type & LEFT))
+ while (size-- > 0)
+ *str++ = c;
+ while (i < precision--)
+ *str++ = '0';
+ while (i-- > 0)
+ *str++ = tmp[i];
+ while (size-- > 0)
+ *str++ = ' ';
+
+ return str;
+}
+
+static char *eaddr(char *str, unsigned char *addr, int size, int precision,
+ int type) {
+ char tmp[24];
+ char *dig = digits;
+ int i, len;
+
+ if (type & UPPERCASE)
+ dig = upper_digits;
+ len = 0;
+ for (i = 0; i < 6; i++) {
+ if (i != 0)
+ tmp[len++] = ':';
+ tmp[len++] = dig[addr[i] >> 4];
+ tmp[len++] = dig[addr[i] & 0x0F];
+ }
+
+ if (!(type & LEFT))
+ while (len < size--)
+ *str++ = ' ';
+ for (i = 0; i < len; ++i)
+ *str++ = tmp[i];
+ while (len < size--)
+ *str++ = ' ';
+
+ return str;
+}
+
+static char *iaddr(char *str, unsigned char *addr, int size, int precision,
+ int type) {
+ char tmp[24];
+ int i, n, len;
+
+ len = 0;
+ for (i = 0; i < 4; i++) {
+ if (i != 0)
+ tmp[len++] = '.';
+ n = addr[i];
+
+ if (n == 0)
+ tmp[len++] = digits[0];
+ else {
+ if (n >= 100) {
+ tmp[len++] = digits[n / 100];
+ n = n % 100;
+ tmp[len++] = digits[n / 10];
+ n = n % 10;
+ } else if (n >= 10) {
+ tmp[len++] = digits[n / 10];
+ n = n % 10;
+ }
+
+ tmp[len++] = digits[n];
+ }
+ }
+
+ if (!(type & LEFT))
+ while (len < size--)
+ *str++ = ' ';
+ for (i = 0; i < len; ++i)
+ *str++ = tmp[i];
+ while (len < size--)
+ *str++ = ' ';
+
+ return str;
+}
+
+#if HAS_FLOAT
+
+char *ecvtbuf(double arg, int ndigits, int *decpt, int *sign, char *buf);
+char *fcvtbuf(double arg, int ndigits, int *decpt, int *sign, char *buf);
+static void ee_bufcpy(char *d, char *s, int count);
+
+void ee_bufcpy(char *pd, char *ps, int count) {
+ char *pe = ps + count;
+ while (ps != pe)
+ *pd++ = *ps++;
+}
+
+static void parse_float(double value, char *buffer, char fmt, int precision) {
+ int decpt, sign, exp, pos;
+ char *digits = NULL;
+ char cvtbuf[80];
+ int capexp = 0;
+ int magnitude;
+
+ if (fmt == 'G' || fmt == 'E') {
+ capexp = 1;
+ fmt += 'a' - 'A';
+ }
+
+ if (fmt == 'g') {
+ digits = ecvtbuf(value, precision, &decpt, &sign, cvtbuf);
+ magnitude = decpt - 1;
+ if (magnitude < -4 || magnitude > precision - 1) {
+ fmt = 'e';
+ precision -= 1;
+ } else {
+ fmt = 'f';
+ precision -= decpt;
+ }
+ }
+
+ if (fmt == 'e') {
+ digits = ecvtbuf(value, precision + 1, &decpt, &sign, cvtbuf);
+
+ if (sign)
+ *buffer++ = '-';
+ *buffer++ = *digits;
+ if (precision > 0)
+ *buffer++ = '.';
+ ee_bufcpy(buffer, digits + 1, precision);
+ buffer += precision;
+ *buffer++ = capexp ? 'E' : 'e';
+
+ if (decpt == 0) {
+ if (value == 0.0)
+ exp = 0;
+ else
+ exp = -1;
+ } else
+ exp = decpt - 1;
+
+ if (exp < 0) {
+ *buffer++ = '-';
+ exp = -exp;
+ } else
+ *buffer++ = '+';
+
+ buffer[2] = (exp % 10) + '0';
+ exp = exp / 10;
+ buffer[1] = (exp % 10) + '0';
+ exp = exp / 10;
+ buffer[0] = (exp % 10) + '0';
+ buffer += 3;
+ } else if (fmt == 'f') {
+ digits = fcvtbuf(value, precision, &decpt, &sign, cvtbuf);
+ if (sign)
+ *buffer++ = '-';
+ if (*digits) {
+ if (decpt <= 0) {
+ *buffer++ = '0';
+ *buffer++ = '.';
+ for (pos = 0; pos < -decpt; pos++)
+ *buffer++ = '0';
+ while (*digits)
+ *buffer++ = *digits++;
+ } else {
+ pos = 0;
+ while (*digits) {
+ if (pos++ == decpt)
+ *buffer++ = '.';
+ *buffer++ = *digits++;
+ }
+ }
+ } else {
+ *buffer++ = '0';
+ if (precision > 0) {
+ *buffer++ = '.';
+ for (pos = 0; pos < precision; pos++)
+ *buffer++ = '0';
+ }
+ }
+ }
+
+ *buffer = '\0';
+}
+
+static void decimal_point(char *buffer) {
+ while (*buffer) {
+ if (*buffer == '.')
+ return;
+ if (*buffer == 'e' || *buffer == 'E')
+ break;
+ buffer++;
+ }
+
+ if (*buffer) {
+ int n = strnlen(buffer, 256);
+ while (n > 0) {
+ buffer[n + 1] = buffer[n];
+ n--;
+ }
+
+ *buffer = '.';
+ } else {
+ *buffer++ = '.';
+ *buffer = '\0';
+ }
+}
+
+static void cropzeros(char *buffer) {
+ char *stop;
+
+ while (*buffer && *buffer != '.')
+ buffer++;
+ if (*buffer++) {
+ while (*buffer && *buffer != 'e' && *buffer != 'E')
+ buffer++;
+ stop = buffer--;
+ while (*buffer == '0')
+ buffer--;
+ if (*buffer == '.')
+ buffer--;
+ while (buffer != stop)
+ *++buffer = 0;
+ }
+}
+
+static char *flt(char *str, double num, int size, int precision, char fmt,
+ int flags) {
+ char tmp[80];
+ char c, sign;
+ int n, i;
+
+ // Left align means no zero padding
+ if (flags & LEFT)
+ flags &= ~ZEROPAD;
+
+ // Determine padding and sign char
+ c = (flags & ZEROPAD) ? '0' : ' ';
+ sign = 0;
+ if (flags & SIGN) {
+ if (num < 0.0) {
+ sign = '-';
+ num = -num;
+ size--;
+ } else if (flags & PLUS) {
+ sign = '+';
+ size--;
+ } else if (flags & SPACE) {
+ sign = ' ';
+ size--;
+ }
+ }
+
+ // Compute the precision value
+ if (precision < 0)
+ precision = 6; // Default precision: 6
+
+ // Convert floating point number to text
+ parse_float(num, tmp, fmt, precision);
+
+ if ((flags & HEX_PREP) && precision == 0)
+ decimal_point(tmp);
+ if (fmt == 'g' && !(flags & HEX_PREP))
+ cropzeros(tmp);
+
+ n = strnlen(tmp, 256);
+
+ // Output number with alignment and padding
+ size -= n;
+ if (!(flags & (ZEROPAD | LEFT)))
+ while (size-- > 0)
+ *str++ = ' ';
+ if (sign)
+ *str++ = sign;
+ if (!(flags & LEFT))
+ while (size-- > 0)
+ *str++ = c;
+ for (i = 0; i < n; i++)
+ *str++ = tmp[i];
+ while (size-- > 0)
+ *str++ = ' ';
+
+ return str;
+}
+
+#endif
+
+static int ee_vsprintf(char *buf, const char *fmt, va_list args) {
+ int len;
+ unsigned long num;
+ int i, base;
+ char *str;
+ char *s;
+
+ int flags; // Flags to number()
+
+ int field_width; // Width of output field
+ int precision; // Min. # of digits for integers; max number of chars for from
+ // string
+ int qualifier; // 'h', 'l', or 'L' for integer fields
+
+ for (str = buf; *fmt; fmt++) {
+ if (*fmt != '%') {
+ *str++ = *fmt;
+ continue;
+ }
+
+ // Process flags
+ flags = 0;
+ repeat:
+ fmt++; // This also skips first '%'
+ switch (*fmt) {
+ case '-':
+ flags |= LEFT;
+ goto repeat;
+ case '+':
+ flags |= PLUS;
+ goto repeat;
+ case ' ':
+ flags |= SPACE;
+ goto repeat;
+ case '#':
+ flags |= HEX_PREP;
+ goto repeat;
+ case '0':
+ flags |= ZEROPAD;
+ goto repeat;
+ }
+
+ // Get field width
+ field_width = -1;
+ if (is_digit(*fmt))
+ field_width = skip_atoi(&fmt);
+ else if (*fmt == '*') {
+ fmt++;
+ field_width = va_arg(args, int);
+ if (field_width < 0) {
+ field_width = -field_width;
+ flags |= LEFT;
+ }
+ }
+
+ // Get the precision
+ precision = -1;
+ if (*fmt == '.') {
+ ++fmt;
+ if (is_digit(*fmt))
+ precision = skip_atoi(&fmt);
+ else if (*fmt == '*') {
+ ++fmt;
+ precision = va_arg(args, int);
+ }
+ if (precision < 0)
+ precision = 0;
+ }
+
+ // Get the conversion qualifier
+ qualifier = -1;
+ if (*fmt == 'l' || *fmt == 'L') {
+ qualifier = *fmt;
+ fmt++;
+ }
+
+ // Default base
+ base = 10;
+
+ switch (*fmt) {
+ case 'c':
+ if (!(flags & LEFT))
+ while (--field_width > 0)
+ *str++ = ' ';
+ *str++ = (unsigned char)va_arg(args, int);
+ while (--field_width > 0)
+ *str++ = ' ';
+ continue;
+
+ case 's':
+ s = va_arg(args, char *);
+ if (!s)
+ s = "<NULL>";
+ len = strnlen(s, precision);
+ if (!(flags & LEFT))
+ while (len < field_width--)
+ *str++ = ' ';
+ for (i = 0; i < len; ++i)
+ *str++ = *s++;
+ while (len < field_width--)
+ *str++ = ' ';
+ continue;
+
+ case 'p':
+ if (field_width == -1) {
+ field_width = 2 * sizeof(void *);
+ flags |= ZEROPAD;
+ }
+ str = number(str, (unsigned long)va_arg(args, void *), 16, field_width,
+ precision, flags);
+ continue;
+
+ case 'A':
+ flags |= UPPERCASE;
+
+ case 'a':
+ if (qualifier == 'l')
+ str = eaddr(str, va_arg(args, unsigned char *), field_width,
+ precision, flags);
+ else
+ str = iaddr(str, va_arg(args, unsigned char *), field_width,
+ precision, flags);
+ continue;
+
+ // Integer number formats - set up the flags and "break"
+ case 'o':
+ base = 8;
+ break;
+
+ case 'X':
+ flags |= UPPERCASE;
+
+ case 'x':
+ base = 16;
+ break;
+
+ case 'd':
+ case 'i':
+ flags |= SIGN;
+
+ case 'u':
+ break;
+
+#if HAS_FLOAT
+
+ case 'f':
+ str = flt(str, va_arg(args, double), field_width, precision, *fmt,
+ flags | SIGN);
+ continue;
+
+#endif
+
+ default:
+ if (*fmt != '%')
+ *str++ = '%';
+ if (*fmt)
+ *str++ = *fmt;
+ else
+ --fmt;
+ continue;
+ }
+
+ if (qualifier == 'l')
+ num = va_arg(args, unsigned long);
+ else if (flags & SIGN)
+ num = va_arg(args, int);
+ else
+ num = va_arg(args, unsigned int);
+
+ str = number(str, num, base, field_width, precision, flags);
+ }
+
+ *str = '\0';
+ return str - buf;
+}
+
+int ee_printf(const char *fmt, ...) {
+ char buf[256], *p;
+ va_list args;
+ int n = 0;
+
+ va_start(args, fmt);
+ ee_vsprintf(buf, fmt, args);
+ va_end(args);
+ p = buf;
+ while (*p) {
+ putchar(*p);
+ n++;
+ p++;
+ }
+
+ return n;
+}
diff --git a/hw/vendor/lowrisc_ibex/examples/sw/simple_system/common/simple_system_common.h b/hw/vendor/lowrisc_ibex/examples/sw/simple_system/common/simple_system_common.h
index 57e8778..fefdc9f 100644
--- a/hw/vendor/lowrisc_ibex/examples/sw/simple_system/common/simple_system_common.h
+++ b/hw/vendor/lowrisc_ibex/examples/sw/simple_system/common/simple_system_common.h
@@ -10,6 +10,7 @@
#define DEV_WRITE(addr, val) (*((volatile uint32_t *)(addr)) = val)
#define DEV_READ(addr, val) (*((volatile uint32_t *)(addr)))
+#define PCOUNT_READ(name, dst) asm volatile("csrr %0, " #name ";" : "=r"(dst))
/**
* Writes character to simulator out log. Signature matches c stdlib function
diff --git a/hw/vendor/lowrisc_ibex/ibex_configs.yaml b/hw/vendor/lowrisc_ibex/ibex_configs.yaml
new file mode 100644
index 0000000..5399cf2
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/ibex_configs.yaml
@@ -0,0 +1,40 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+# Ibex configurations files, holds the parameter sets that are tested under CI.
+# Each configuration must specify the same set of parameters
+
+# Two-stage pipeline without additional branch target ALU and 3 cycle multiplier
+# (4 cycles for mulh), resulting in 2 stall cycles for mul (3 for mulh)
+small-3cmult:
+ RV32E : False
+ RV32M : True
+ RV32B : False
+ BranchTargetALU : False
+ WritebackStage : False
+ MultiplierImplementation : "fast"
+
+# ===============================
+# * EXPERIMENTAL CONFIGURATIONS *
+# ===============================
+
+# Three-stage pipeline with additional branch traget ALU and 1 cycle multiplier
+# (2 cycles for mulh) so mul does not stall (mulh stall 1 cycles). This is the
+# maximum performance configuration.
+experimental-maxperf-1cmult:
+ RV32E : False
+ RV32M : True
+ RV32B : False
+ BranchTargetALU : True
+ WritebackStage : True
+ MultiplierImplementation : "single-cycle"
+
+# maxpref-1cmult config above with bitmanip extension
+experimental-maxperf-bm-1cmult:
+ RV32E : False
+ RV32M : True
+ RV32B : True
+ BranchTargetALU : True
+ WritebackStage : True
+ MultiplierImplementation : "single-cycle"
diff --git a/hw/vendor/lowrisc_ibex/ibex_core.core b/hw/vendor/lowrisc_ibex/ibex_core.core
index 09009ca..9c08757 100644
--- a/hw/vendor/lowrisc_ibex/ibex_core.core
+++ b/hw/vendor/lowrisc_ibex/ibex_core.core
@@ -3,14 +3,15 @@
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
name: "lowrisc:ibex:ibex_core:0.1"
-description: "CPU core with 2 stage pipeline implementing the RV32IMC_Zicsr ISA"
+description: "CPU core with 2 stage pipeline implementing the RV32IMC_Zicsr_Zifencei ISA"
filesets:
files_rtl:
depend:
- lowrisc:prim:assert
+ - lowrisc:ibex:ibex_pkg
+ - lowrisc:ibex:ibex_icache
files:
- - rtl/ibex_pkg.sv
- rtl/ibex_alu.sv
- rtl/ibex_compressed_decoder.sv
- rtl/ibex_controller.sv
@@ -26,6 +27,7 @@
- rtl/ibex_multdiv_slow.sv
- rtl/ibex_prefetch_buffer.sv
- rtl/ibex_pmp.sv
+ - rtl/ibex_wb_stage.sv
# XXX: Figure out the best way to switch these two implementations
# dynamically on the target.
# - rtl/ibex_register_file_latch.sv # ASIC
@@ -63,17 +65,40 @@
datatype: bool
paramtype: vlogparam
+ RV32B:
+ datatype: bool
+ default: false
+ paramtype: vlogparam
+
MultiplierImplementation:
datatype: str
paramtype: vlogparam
description: "Multiplier implementation. Valid values: fast, slow"
default: fast
- BranchTargetALU:
- datatype: int
+ ICache:
+ datatype: bool
paramtype: vlogparam
- default: 0
- description: "Enables seperate branch target ALU (increasing branch performance EXPERIMENTAL) [0/1]"
+ description: "Enable instruction cache"
+ default: false
+
+ ICacheECC:
+ datatype: bool
+ paramtype: vlogparam
+ description: "Enable ECC protection in instruction cache"
+ default: false
+
+ BranchTargetALU:
+ datatype: bool
+ paramtype: vlogparam
+ default: false
+ description: "Enables seperate branch target ALU (increasing branch performance EXPERIMENTAL)"
+
+ WritebackStage:
+ datatype: bool
+ paramtype: vlogparam
+ default: false
+ description: "Enables third pipeline stage (EXPERIMENTAL)"
targets:
default:
@@ -97,3 +122,22 @@
mode: lint-only
verilator_options:
- "-Wall"
+ # RAM primitives wider than 64bit (required for ECC) fail to build in
+ # Verilator without increasing the unroll count (see Verilator#1266)
+ - "--unroll-count 72"
+ veriblelint:
+ ruleset: default
+ rules:
+ - "-parameter-name-style"
+ format:
+ filesets:
+ - files_rtl
+ parameters:
+ - SYNTHESIS=true
+ - RVFI=true
+ default_tool: veribleformat
+ toplevel: ibex_core
+ tools:
+ veribleformat:
+ verible_format_args:
+ - "--inplace"
diff --git a/hw/vendor/lowrisc_ibex/ibex_core_tracing.core b/hw/vendor/lowrisc_ibex/ibex_core_tracing.core
index 9de7f13..6eac23f 100644
--- a/hw/vendor/lowrisc_ibex/ibex_core_tracing.core
+++ b/hw/vendor/lowrisc_ibex/ibex_core_tracing.core
@@ -34,25 +34,48 @@
RV32E:
datatype: bool
+ default: false
paramtype: vlogparam
RV32M:
datatype: bool
+ default: true
+ paramtype: vlogparam
+
+ RV32B:
+ datatype: bool
+ default: false
paramtype: vlogparam
MultiplierImplementation:
datatype: str
paramtype: vlogparam
- description: "Multiplier implementation. Valid values: fast, slow"
- default: fast
+ description: "Multiplier implementation. Valid values: fast, slow, single-cycle"
+ default: "fast"
+
+ ICache:
+ datatype: bool
+ paramtype: vlogparam
+ description: "Enable instruction cache"
+ default: false
+
+ ICacheECC:
+ datatype: bool
+ paramtype: vlogparam
+ description: "Enable ECC protection in instruction cache"
+ default: false
BranchTargetALU:
- datatype: int
+ datatype: bool
paramtype: vlogparam
- default: 0
+ default: false
description: "Enables seperate branch target ALU (increasing branch performance EXPERIMENTAL) [0/1]"
-
+ WritebackStage:
+ datatype: bool
+ paramtype: vlogparam
+ default: false
+ description: "Enables third pipeline stage (EXPERIMENTAL) [0/1]"
targets:
default:
@@ -72,6 +95,11 @@
parameters:
- RVFI=true
- SYNTHESIS=true
+ - RV32M
+ - RV32E
+ - BranchTargetALU
+ - WritebackStage
+ - MultiplierImplementation
default_tool: verilator
toplevel: ibex_core_tracing
tools:
@@ -79,3 +107,22 @@
mode: lint-only
verilator_options:
- "-Wall"
+ # RAM primitives wider than 64bit (required for ECC) fail to build in
+ # Verilator without increasing the unroll count (see Verilator#1266)
+ - "--unroll-count 72"
+ veriblelint:
+ ruleset: default
+ rules:
+ - "-parameter-name-style"
+ format:
+ filesets:
+ - files_rtl
+ parameters:
+ - SYNTHESIS=true
+ - RVFI=true
+ default_tool: veribleformat
+ toplevel: ibex_core
+ tools:
+ veribleformat:
+ verible_format_args:
+ - "--inplace"
diff --git a/hw/vendor/lowrisc_ibex/ibex_icache.core b/hw/vendor/lowrisc_ibex/ibex_icache.core
new file mode 100644
index 0000000..0ef0f33
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/ibex_icache.core
@@ -0,0 +1,20 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:ibex:ibex_icache:0.1"
+description: "IBEX_ICACHE DV sim target"
+filesets:
+ files_rtl:
+ depend:
+ - lowrisc:ibex:sim_shared
+ files:
+ - rtl/ibex_icache.sv
+ file_type: systemVerilogSource
+
+targets:
+ default: &default_target
+ filesets:
+ - files_rtl
+ toplevel: ibex_icache
+ default_tool: vcs
diff --git a/hw/vendor/lowrisc_ibex/ibex_pkg.core b/hw/vendor/lowrisc_ibex/ibex_pkg.core
new file mode 100644
index 0000000..17f47e0
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/ibex_pkg.core
@@ -0,0 +1,17 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:ibex:ibex_pkg:0.1"
+description: "Header package for Ibex"
+
+filesets:
+ files_rtl:
+ files:
+ - rtl/ibex_pkg.sv
+ file_type: systemVerilogSource
+
+targets:
+ default:
+ filesets:
+ - files_rtl
diff --git a/hw/vendor/lowrisc_ibex/ibex_tracer.core b/hw/vendor/lowrisc_ibex/ibex_tracer.core
index 7ed3109..582fc61 100644
--- a/hw/vendor/lowrisc_ibex/ibex_tracer.core
+++ b/hw/vendor/lowrisc_ibex/ibex_tracer.core
@@ -8,6 +8,7 @@
files_rtl:
depend:
- lowrisc:prim:assert
+ - lowrisc:ibex:ibex_pkg
files:
- rtl/ibex_tracer_pkg.sv
- rtl/ibex_tracer.sv
diff --git a/hw/vendor/lowrisc_ibex/lint/verilator_waiver.vlt b/hw/vendor/lowrisc_ibex/lint/verilator_waiver.vlt
index bc57bb3..f3b1f6e 100644
--- a/hw/vendor/lowrisc_ibex/lint/verilator_waiver.vlt
+++ b/hw/vendor/lowrisc_ibex/lint/verilator_waiver.vlt
@@ -12,6 +12,13 @@
`verilator_config
lint_off -rule PINCONNECTEMPTY
+// Operator expects 1 bit on initial value but initial value's CONST generates
+// 32 bits
+lint_off -rule WIDTH -file "*/rtl/ibex_core_tracing.sv" -match "*'RV32M'*"
+lint_off -rule WIDTH -file "*/rtl/ibex_core_tracing.sv" -match "*'RV32E'*"
+lint_off -rule WIDTH -file "*/rtl/ibex_core_tracing.sv" -match "*'BranchTargetALU'*"
+lint_off -rule WIDTH -file "*/rtl/ibex_core_tracing.sv" -match "*'WritebackStage'*"
+
// Filename 'ibex_register_file_ff' does not match MODULE name: ibex_register_file
// ibex_register_file_ff and ibex_register_file_latch provide two
// implementation choices for the same module.
@@ -23,17 +30,23 @@
// cleaner to write all bits even if not all are used
lint_off -rule UNUSED -file "*/rtl/ibex_if_stage.sv" -match "*'fetch_addr_n'[0]*"
-// Bits of signal are not used: shift_right_result_ext[32]
-// cleaner to write all bits even if not all are used
-lint_off -rule UNUSED -file "*/rtl/ibex_alu.sv" -match "*'shift_right_result_ext'[32]*"
+// Signal is not used, if RVB == 0: shift_result_ext_rvb
+// Needed if RVB == 1.
+lint_off -rule UNUSED -file "*/rtl/ibex_alu.sv" -match "*'shift_result_ext_rvb'*"
+
+// Signal is not used, if RVB == 1: shift_result_ext
+// Needed if RVB == 0.
+lint_off -rule UNUSED -file "*/rtl/ibex_alu.sv" -match "*'shift_result_ext'*"
// Bits of signal are not used: alu_adder_ext_i[0]
// Bottom bit is round, not needed
lint_off -rule UNUSED -file "*/rtl/ibex_multdiv_fast.sv" -match "*'alu_adder_ext_i'[0]*"
-// Bits of signal are not used: mac_res_ext[34]
+// Bits of signal are not used: mac_res_ext[34], mult1_res[33:32]
// cleaner to write all bits even if not all are used
lint_off -rule UNUSED -file "*/rtl/ibex_multdiv_fast.sv" -match "*mac_res_ext*"
+lint_off -rule UNUSED -file "*/rtl/ibex_multdiv_fast.sv" -match "*mult1_res*"
+
// Bits of signal are not used: res_adder_h[32]
// cleaner to write all bits even if not all are used
diff --git a/hw/vendor/lowrisc_ibex/python-requirements.txt b/hw/vendor/lowrisc_ibex/python-requirements.txt
new file mode 100644
index 0000000..03e049f
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/python-requirements.txt
@@ -0,0 +1,9 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+# Development version of edalize until all our changes are upstream
+git+https://github.com/lowRISC/edalize.git@ot
+
+# Development version with OT-specific changes
+git+https://github.com/lowRISC/fusesoc.git@ot
diff --git a/hw/vendor/lowrisc_ibex/rtl/ibex_alu.sv b/hw/vendor/lowrisc_ibex/rtl/ibex_alu.sv
index a7bf21a..24bf716 100644
--- a/hw/vendor/lowrisc_ibex/rtl/ibex_alu.sv
+++ b/hw/vendor/lowrisc_ibex/rtl/ibex_alu.sv
@@ -6,7 +6,9 @@
/**
* Arithmetic logic unit
*/
-module ibex_alu (
+module ibex_alu #(
+ parameter bit RV32B = 1'b0
+) (
input ibex_pkg::alu_op_e operator_i,
input logic [31:0] operand_a_i,
input logic [31:0] operand_b_i,
@@ -43,7 +45,6 @@
always_comb begin
adder_op_b_negate = 1'b0;
-
unique case (operator_i)
// Adder OPs
ALU_SUB,
@@ -52,7 +53,16 @@
ALU_EQ, ALU_NE,
ALU_GE, ALU_GEU,
ALU_LT, ALU_LTU,
- ALU_SLT, ALU_SLTU: adder_op_b_negate = 1'b1;
+ ALU_SLT, ALU_SLTU,
+
+ // MinMax OPs (RV32B Ops)
+ ALU_MIN, ALU_MINU,
+ ALU_MAX, ALU_MAXU,
+
+ // Logic-with-negate OPs (RV32B Ops)
+ ALU_XNOR,
+ ALU_ORN,
+ ALU_ANDN: adder_op_b_negate = 1'b1;
default:;
endcase
@@ -63,7 +73,7 @@
// prepare operand b
assign operand_b_neg = {operand_b_i,1'b0} ^ {33{adder_op_b_negate}};
- assign adder_in_b = multdiv_sel_i ? multdiv_operand_b_i : operand_b_neg ;
+ assign adder_in_b = multdiv_sel_i ? multdiv_operand_b_i : operand_b_neg;
// actual adder
assign adder_result_ext_o = $unsigned(adder_in_a) + $unsigned(adder_in_b);
@@ -76,43 +86,93 @@
// Shift //
///////////
- logic shift_left; // should we shift left
- logic shift_arithmetic;
+ logic shift_left;
+ logic shift_ones;
+ logic shift_arith;
+ logic shift_rot;
+ logic shift_none;
+ logic shift_op_rev;
+ logic shift_op_rev8;
+ logic shift_op_orc_b;
+ logic [4:0] shift_amt;
- logic [4:0] shift_amt; // amount of shift, to the right
- logic [31:0] shift_op_a; // input of the shifter
+ assign shift_amt = operand_b_i[4:0];
+
+ assign shift_left = RV32B ? (operator_i == ALU_ROL) || (operator_i == ALU_SLO) ||
+ (operator_i == ALU_SLL) :
+ (operator_i == ALU_SLL);
+ assign shift_ones = RV32B ? (operator_i == ALU_SLO) || (operator_i == ALU_SRO) : 1'b0;
+ assign shift_arith = (operator_i == ALU_SRA);
+ assign shift_rot = RV32B ? (operator_i == ALU_ROL) || (operator_i == ALU_ROR) : 1'b0;
+ assign shift_none = RV32B ? (operator_i == ALU_REV) || (operator_i == ALU_REV8) ||
+ (operator_i == ALU_ORCB) :
+ 1'b0;
+
+ assign shift_op_rev = RV32B ? (operator_i == ALU_REV) : 1'b0;
+ assign shift_op_rev8 = RV32B ? (operator_i == ALU_REV8) : 1'b0;
+ assign shift_op_orc_b = RV32B ? (operator_i == ALU_ORCB) : 1'b0;
+
logic [31:0] shift_result;
- logic [31:0] shift_right_result;
- logic [31:0] shift_left_result;
+ logic [31:0] shift_extension_rvb;
+ logic shift_extension;
+ logic [32:0] shift_result_ext;
+ logic [63:0] shift_result_ext_rvb;
- assign shift_amt = operand_b_i[4:0];
- assign shift_left = (operator_i == ALU_SLL);
+ always_comb begin
+ shift_result = operand_a_i;
- assign shift_arithmetic = (operator_i == ALU_SRA);
+ // select bit reversed or normal input
+ if (shift_op_rev || shift_left) begin
+ shift_result = operand_a_rev;
+ end
- // choose the bit reversed or the normal input for shift operand a
- assign shift_op_a = shift_left ? operand_a_rev : operand_a_i;
+ if (RV32B) begin
+ // rotation: extend with a copy of the operand
+ // shift-ones: extend with ones
+ // arithmetic shift: sign-extend.
+ // else: zero-extend.
+ shift_extension_rvb = shift_rot ?
+ shift_result :
+ {32{shift_ones || (shift_arith && operand_a_i[31])}};
- // right shifts, we let the synthesizer optimize this
- logic [32:0] shift_op_a_32;
- assign shift_op_a_32 = {shift_arithmetic & shift_op_a[31], shift_op_a};
+ shift_result_ext_rvb = {shift_extension_rvb, shift_result} >> shift_amt;
+ end else begin
+ shift_extension = (shift_arith && shift_result[31]);
+ shift_result_ext = $signed({shift_extension, shift_result}) >>> shift_amt;
+ end
- // The MSB of shift_right_result_ext can safely be ignored. We just extend the input to always
- // do arithmetic shifts.
- logic signed [32:0] shift_right_result_signed;
- logic [32:0] shift_right_result_ext;
- assign shift_right_result_signed = $signed(shift_op_a_32) >>> shift_amt[4:0];
- assign shift_right_result_ext = $unsigned(shift_right_result_signed);
- assign shift_right_result = shift_right_result_ext[31:0];
+ // shift, if this is a shift operation
+ if (!shift_none) begin
+ shift_result = RV32B ? shift_result_ext_rvb[31:0] : shift_result_ext[31:0];
+ end
- // bit reverse the shift_right_result for left shifts
- for (genvar j = 0; j < 32; j++) begin : gen_rev_shift_right_result
- assign shift_left_result[j] = shift_right_result[31-j];
+ // shift left: bytewise reverse. (orcomnine with '0)
+ // orc_b: bytewise reverse and orcombine.
+ if (shift_op_orc_b || shift_left) begin
+ shift_result = (shift_op_orc_b ? shift_result : 32'h 0) |
+ ((shift_result & 32'h 55555555) << 1) |
+ ((shift_result & 32'h AAAAAAAA) >> 1);
+
+ shift_result = (shift_op_orc_b ? shift_result : 32'h 0) |
+ ((shift_result & 32'h 33333333) << 2) |
+ ((shift_result & 32'h CCCCCCCC) >> 2);
+
+ shift_result = (shift_op_orc_b ? shift_result : 32'h 0) |
+ ((shift_result & 32'h 0F0F0F0F) << 4) |
+ ((shift_result & 32'h F0F0F0F0) >> 4);
+ end
+
+ // byte-swap
+ if (shift_op_rev8 || shift_left) begin
+ shift_result = ((shift_result & 32'h 00FF00FF) << 8) |
+ ((shift_result & 32'h FF00FF00) >> 8);
+
+ shift_result = ((shift_result & 32'h 0000FFFF) << 16) |
+ ((shift_result & 32'h FFFF0000) >> 16);
+ end
end
- assign shift_result = shift_left ? shift_left_result : shift_right_result;
-
////////////////
// Comparison //
////////////////
@@ -123,13 +183,13 @@
always_comb begin
cmp_signed = 1'b0;
-
unique case (operator_i)
ALU_GE,
ALU_LT,
- ALU_SLT: begin
- cmp_signed = 1'b1;
- end
+ ALU_SLT,
+ // RV32B only
+ ALU_MIN,
+ ALU_MAX: cmp_signed = 1'b1;
default:;
endcase
@@ -164,13 +224,14 @@
always_comb begin
cmp_result = is_equal;
-
unique case (operator_i)
- ALU_EQ: cmp_result = is_equal;
- ALU_NE: cmp_result = ~is_equal;
- ALU_GE, ALU_GEU: cmp_result = is_greater_equal;
- ALU_LT, ALU_LTU,
- ALU_SLT, ALU_SLTU: cmp_result = ~is_greater_equal;
+ ALU_EQ: cmp_result = is_equal;
+ ALU_NE: cmp_result = ~is_equal;
+ ALU_GE, ALU_GEU,
+ ALU_MAX, ALU_MAXU: cmp_result = is_greater_equal; // RV32B only
+ ALU_LT, ALU_LTU,
+ ALU_MIN, ALU_MINU, //RV32B only
+ ALU_SLT, ALU_SLTU: cmp_result = ~is_greater_equal;
default:;
endcase
@@ -178,6 +239,88 @@
assign comparison_result_o = cmp_result;
+ logic [31:0] minmax_result;
+ logic [5:0] bitcnt_result;
+ logic [31:0] bwlogic_result;
+ logic [31:0] pack_result;
+
+ ///////////////////
+ // Bitwise Logic //
+ ///////////////////
+
+ logic bwlogic_or;
+ logic bwlogic_and;
+ logic [31:0] bwlogic_operand_b;
+
+ assign bwlogic_or = (operator_i == ALU_OR) || (operator_i == ALU_ORN);
+ assign bwlogic_and = (operator_i == ALU_AND) || (operator_i == ALU_ANDN);
+ assign bwlogic_operand_b = RV32B ? operand_b_neg[32:1] : operand_b_i;
+
+ always_comb begin
+ unique case (1'b1)
+ bwlogic_or: bwlogic_result = operand_a_i | bwlogic_operand_b;
+ bwlogic_and: bwlogic_result = operand_a_i & bwlogic_operand_b;
+ default: bwlogic_result = operand_a_i ^ bwlogic_operand_b;
+ endcase
+ end
+
+ if (RV32B) begin : g_alu_rvb
+
+ ///////////////
+ // Min / Max //
+ ///////////////
+
+ assign minmax_result = (cmp_result ? operand_a_i : operand_b_i);
+
+ /////////////////
+ // Bitcounting //
+ /////////////////
+
+ logic bitcnt_ctz;
+ logic bitcnt_pcnt;
+ logic [31:0] bitcnt_bits;
+ logic [32:0] bitcnt_bit_enable;
+
+ assign bitcnt_ctz = (operator_i == ALU_CTZ);
+ assign bitcnt_pcnt = (operator_i == ALU_PCNT);
+
+ assign bitcnt_bits = bitcnt_pcnt ? operand_a_i : (bitcnt_ctz ? ~operand_a_i : ~operand_a_rev);
+
+ always_comb begin
+ bitcnt_result = '0;
+ bitcnt_bit_enable = {32'b0, 1'b1}; // bit 32 unused.
+ for (int unsigned i=0; i<32; i++) begin : gen_bitcnt_adder
+ // keep counting if all previous bits are 1
+ bitcnt_bit_enable[i+1] = bitcnt_pcnt || (bitcnt_bit_enable[i] && bitcnt_bits[i]);
+ if (bitcnt_bit_enable[i]) begin
+ bitcnt_result[5:0] = bitcnt_result[5:0] + {5'h0, bitcnt_bits[i]};
+ end
+ end
+ end
+
+ //////////
+ // Pack //
+ //////////
+
+ logic packu;
+ logic packh;
+ assign packu = (operator_i == ALU_PACKU);
+ assign packh = (operator_i == ALU_PACKH);
+
+ always_comb begin
+ unique case (1'b1)
+ packu: pack_result = {operand_b_i[31:16], operand_a_i[31:16]};
+ packh: pack_result = {16'h0, operand_b_i[7:0], operand_a_i[7:0]};
+ default: pack_result = {operand_b_i[15:0], operand_a_i[15:0]};
+ endcase
+ end
+ end else begin : g_no_alu_rvb
+ // Rvb result signals
+ assign minmax_result = '0;
+ assign bitcnt_result = '0;
+ assign pack_result = '0;
+ end
+
////////////////
// Result mux //
////////////////
@@ -186,17 +329,22 @@
result_o = '0;
unique case (operator_i)
- // Standard Operations
- ALU_AND: result_o = operand_a_i & operand_b_i;
- ALU_OR: result_o = operand_a_i | operand_b_i;
- ALU_XOR: result_o = operand_a_i ^ operand_b_i;
+ // Bitwise Logic Operations (negate: RV32B Ops)
+ ALU_XOR, ALU_XNOR,
+ ALU_OR, ALU_ORN,
+ ALU_AND, ALU_ANDN: result_o = bwlogic_result;
// Adder Operations
ALU_ADD, ALU_SUB: result_o = adder_result;
// Shift Operations
- ALU_SLL,
- ALU_SRL, ALU_SRA: result_o = shift_result;
+ ALU_SLL, ALU_SRL,
+ ALU_SRA,
+ // RV32B Ops
+ ALU_SLO, ALU_SRO,
+ ALU_ROL, ALU_ROR,
+ ALU_REV, ALU_REV8,
+ ALU_ORCB: result_o = shift_result;
// Comparison Operations
ALU_EQ, ALU_NE,
@@ -204,7 +352,19 @@
ALU_LT, ALU_LTU,
ALU_SLT, ALU_SLTU: result_o = {31'h0,cmp_result};
- default:;
+ // MinMax Operations (RV32B Ops)
+ ALU_MIN, ALU_MAX,
+ ALU_MINU, ALU_MAXU: result_o = minmax_result;
+
+ // Bitcount Operations (RV32B Ops)
+ ALU_CLZ, ALU_CTZ,
+ ALU_PCNT: result_o = {26'h0, bitcnt_result};
+
+ // Pack Operations (RV32B Ops)
+ ALU_PACK, ALU_PACKH,
+ ALU_PACKU: result_o = pack_result;
+
+ default: ;
endcase
end
diff --git a/hw/vendor/lowrisc_ibex/rtl/ibex_controller.sv b/hw/vendor/lowrisc_ibex/rtl/ibex_controller.sv
index 138800d..a256a33 100644
--- a/hw/vendor/lowrisc_ibex/rtl/ibex_controller.sv
+++ b/hw/vendor/lowrisc_ibex/rtl/ibex_controller.sv
@@ -9,7 +9,9 @@
`include "prim_assert.sv"
-module ibex_controller (
+module ibex_controller #(
+ parameter bit WritebackStage = 0
+ ) (
input logic clk_i,
input logic rst_ni,
@@ -17,50 +19,54 @@
output logic ctrl_busy_o, // core is busy processing instrs
// decoder related signals
- input logic illegal_insn_i, // decoder has an invalid instr
- input logic ecall_insn_i, // decoder has ECALL instr
- input logic mret_insn_i, // decoder has MRET instr
- input logic dret_insn_i, // decoder has DRET instr
- input logic wfi_insn_i, // decoder has WFI instr
- input logic ebrk_insn_i, // decoder has EBREAK instr
- input logic csr_pipe_flush_i, // do CSR-related pipeline flush
+ input logic illegal_insn_i, // decoder has an invalid instr
+ input logic ecall_insn_i, // decoder has ECALL instr
+ input logic mret_insn_i, // decoder has MRET instr
+ input logic dret_insn_i, // decoder has DRET instr
+ input logic wfi_insn_i, // decoder has WFI instr
+ input logic ebrk_insn_i, // decoder has EBREAK instr
+ input logic csr_pipe_flush_i, // do CSR-related pipeline flush
// from IF-ID pipeline stage
- input logic instr_valid_i, // instr from IF-ID reg is valid
- input logic [31:0] instr_i, // instr from IF-ID reg, for mtval
- input logic [15:0] instr_compressed_i, // instr from IF-ID reg, for mtval
- input logic instr_is_compressed_i, // instr from IF-ID reg is compressed
- input logic instr_fetch_err_i, // instr from IF-ID reg has error
- input logic [31:0] pc_id_i, // instr from IF-ID reg address
+ input logic instr_valid_i, // instr from IF-ID reg is valid
+ input logic [31:0] instr_i, // instr from IF-ID reg, for mtval
+ input logic [15:0] instr_compressed_i, // instr from IF-ID reg, for mtval
+ input logic instr_is_compressed_i, // instr from IF-ID reg is compressed
+ input logic instr_fetch_err_i, // instr from IF-ID reg has error
+ input logic instr_fetch_err_plus2_i, // instr from IF-ID reg error is x32
+ input logic [31:0] pc_id_i, // instr from IF-ID reg address
// to IF-ID pipeline stage
- output logic instr_valid_clear_o, // kill instr in IF-ID reg
- output logic id_in_ready_o, // ID stage is ready for new instr
+ output logic instr_valid_clear_o, // kill instr in IF-ID reg
+ output logic id_in_ready_o, // ID stage is ready for new instr
+ output logic controller_run_o, // Controller is in standard instruction
+ // run mode
// to prefetcher
- output logic instr_req_o, // start fetching instructions
- output logic pc_set_o, // jump to address set by pc_mux
- output ibex_pkg::pc_sel_e pc_mux_o, // IF stage fetch address selector
- // (boot, normal, exception...)
- output ibex_pkg::exc_pc_sel_e exc_pc_mux_o, // IF stage selector for exception PC
- output ibex_pkg::exc_cause_e exc_cause_o, // for IF stage, CSRs
+ output logic instr_req_o, // start fetching instructions
+ output logic pc_set_o, // jump to address set by pc_mux
+ output ibex_pkg::pc_sel_e pc_mux_o, // IF stage fetch address selector
+ // (boot, normal, exception...)
+ output ibex_pkg::exc_pc_sel_e exc_pc_mux_o, // IF stage selector for exception PC
+ output ibex_pkg::exc_cause_e exc_cause_o, // for IF stage, CSRs
// LSU
- input logic [31:0] lsu_addr_last_i, // for mtval
+ input logic [31:0] lsu_addr_last_i, // for mtval
input logic load_err_i,
input logic store_err_i,
+ output logic wb_exception_o, // Instruction in WB taking an exception
// jump/branch signals
- input logic branch_set_i, // branch taken set signal
- input logic jump_set_i, // jump taken set signal
+ input logic branch_set_i, // branch taken set signal
+ input logic jump_set_i, // jump taken set signal
// interrupt signals
- input logic csr_mstatus_mie_i, // M-mode interrupt enable bit
- input logic irq_pending_i, // interrupt request pending
- input ibex_pkg::irqs_t irqs_i, // interrupt requests qualified with
- // mie CSR
- input logic irq_nm_i, // non-maskeable interrupt
- output logic nmi_mode_o, // core executing NMI handler
+ input logic csr_mstatus_mie_i, // M-mode interrupt enable bit
+ input logic irq_pending_i, // interrupt request pending
+ input ibex_pkg::irqs_t irqs_i, // interrupt requests qualified with
+ // mie CSR
+ input logic irq_nm_i, // non-maskeable interrupt
+ output logic nmi_mode_o, // core executing NMI handler
// debug signals
input logic debug_req_i,
@@ -74,6 +80,7 @@
output logic csr_save_if_o,
output logic csr_save_id_o,
+ output logic csr_save_wb_o,
output logic csr_restore_mret_id_o,
output logic csr_restore_dret_id_o,
output logic csr_save_cause_o,
@@ -81,17 +88,16 @@
input ibex_pkg::priv_lvl_e priv_mode_i,
input logic csr_mstatus_tw_i,
- // stall signals
- input logic stall_lsu_i,
- input logic stall_multdiv_i,
- input logic stall_jump_i,
- input logic stall_branch_i,
+ // stall & flush signals
+ input logic stall_id_i,
+ input logic stall_wb_i,
+ output logic flush_id_o,
// performance monitors
- output logic perf_jump_o, // we are executing a jump
- // instruction (j, jr, jal, jalr)
- output logic perf_tbranch_o // we are executing a taken branch
- // instruction
+ output logic perf_jump_o, // we are executing a jump
+ // instruction (j, jr, jal, jalr)
+ output logic perf_tbranch_o // we are executing a taken branch
+ // instruction
);
import ibex_pkg::*;
@@ -203,7 +209,7 @@
exc_req_d | exc_req_lsu;
// special request that can specifically occur during branch instructions
- assign special_req_branch = (illegal_insn_d | instr_fetch_err) & (ctrl_fsm_cs != FLUSH);
+ assign special_req_branch = instr_fetch_err & (ctrl_fsm_cs != FLUSH);
`ASSERT(SpecialReqBranchGivesSpecialReqAll,
special_req_branch |-> special_req_all)
@@ -211,6 +217,13 @@
`ASSERT(SpecialReqAllGivesSpecialReqBranchIfBranchInst,
special_req_all && (branch_set_i || jump_set_i) |-> special_req_branch)
+ if (WritebackStage) begin
+ // Instruction in writeback is generating an exception so instruction in ID must not execute
+ assign wb_exception_o = load_err_q | store_err_q | load_err_i | store_err_i;
+ end else begin
+ assign wb_exception_o = 1'b0;
+ end
+
////////////////
// Interrupts //
////////////////
@@ -269,6 +282,7 @@
csr_save_if_o = 1'b0;
csr_save_id_o = 1'b0;
+ csr_save_wb_o = 1'b0;
csr_restore_mret_id_o = 1'b0;
csr_restore_dret_id_o = 1'b0;
csr_save_cause_o = 1'b0;
@@ -299,6 +313,8 @@
perf_tbranch_o = 1'b0;
perf_jump_o = 1'b0;
+ controller_run_o = 1'b0;
+
unique case (ctrl_fsm_cs)
RESET: begin
// just wait for fetch_enable
@@ -352,11 +368,12 @@
// handle interrupts
if (handle_irq) begin
- // This assumes that the pipeline is always flushed before
- // going to sleep.
+ // We are handling an interrupt. Set halt_if to tell IF not to give
+ // us any more instructions before it redirects to the handler, but
+ // don't set flush_id: we must allow this instruction to complete
+ // (since it might have outstanding loads or stores).
ctrl_fsm_ns = IRQ_TAKEN;
halt_if = 1'b1;
- flush_id = 1'b1;
end
// enter debug mode
@@ -375,6 +392,8 @@
// 2. debug requests
// 3. interrupt requests
+ controller_run_o = 1'b1;
+
// Set PC mux for branch and jump here to ease timing. Value is only relevant if pc_set_o is
// also set. Setting the mux value here avoids factoring in special_req and instr_valid_i
// which helps timing.
@@ -416,8 +435,12 @@
end else if (handle_irq) begin
// handle interrupt (not in debug mode)
ctrl_fsm_ns = IRQ_TAKEN;
+ // We are handling an interrupt (not in debug mode). Set halt_if to
+ // tell IF not to give us any more instructions before it redirects
+ // to the handler, but don't set flush_id: we must allow this
+ // instruction to complete (since it might have outstanding loads
+ // or stores).
halt_if = 1'b1;
- flush_id = 1'b1;
end
end
@@ -530,13 +553,23 @@
pc_set_o = 1'b1;
pc_mux_o = PC_EXC;
exc_pc_mux_o = debug_mode_q ? EXC_PC_DBG_EXC : EXC_PC_EXC;
- csr_save_id_o = 1'b1;
+
+ if (WritebackStage) begin : g_writeback_mepc_save
+ // With the writeback stage present whether an instruction accessing memory will cause
+ // an exception is only known when it is in writeback. So when taking such an exception
+ // epc must come from writeback.
+ csr_save_id_o = ~(store_err_q | load_err_q);
+ csr_save_wb_o = store_err_q | load_err_q;
+ end else begin : g_no_writeback_mepc_save
+ csr_save_id_o = 1'b0;
+ end
+
csr_save_cause_o = 1'b1;
// set exception registers, priorities according to Table 3.7 of Privileged Spec v1.11
if (instr_fetch_err) begin
exc_cause_o = EXC_CAUSE_INSTR_ACCESS_FAULT;
- csr_mtval_o = pc_id_i;
+ csr_mtval_o = instr_fetch_err_plus2_i ? (pc_id_i + 32'd2) : pc_id_i;
end else if (illegal_insn_q) begin
exc_cause_o = EXC_CAUSE_ILLEGAL_INSN;
@@ -628,6 +661,8 @@
endcase
end
+ assign flush_id_o = flush_id;
+
// signal to CSR when in debug mode
assign debug_mode_o = debug_mode_q;
@@ -638,10 +673,10 @@
// Stall control //
///////////////////
- // if high, current instr needs at least one more cycle to finish after the current cycle
- // if low, current instr finishes in current cycle
- // multicycle instructions have this set except during the last cycle
- assign stall = stall_lsu_i | stall_multdiv_i | stall_jump_i | stall_branch_i;
+ // If high current instruction cannot complete this cycle. Either because it needs more cycles to
+ // finish (stall_id_i) or because the writeback stage cannot accept it yet (stall_wb_i). If there
+ // is no writeback stage stall_wb_i is a constant 0.
+ assign stall = stall_id_i | stall_wb_i;
// signal to IF stage that ID stage is ready for next instr
assign id_in_ready_o = ~stall & ~halt_if;
diff --git a/hw/vendor/lowrisc_ibex/rtl/ibex_core.sv b/hw/vendor/lowrisc_ibex/rtl/ibex_core.sv
index b17c25d..5d3fe04 100644
--- a/hw/vendor/lowrisc_ibex/rtl/ibex_core.sv
+++ b/hw/vendor/lowrisc_ibex/rtl/ibex_core.sv
@@ -18,8 +18,12 @@
parameter int unsigned MHPMCounterWidth = 40,
parameter bit RV32E = 1'b0,
parameter bit RV32M = 1'b1,
+ parameter bit RV32B = 1'b0,
parameter bit BranchTargetALU = 1'b0,
+ parameter bit WritebackStage = 1'b0,
parameter MultiplierImplementation = "fast",
+ parameter bit ICache = 1'b0,
+ parameter bit ICacheECC = 1'b0,
parameter bit DbgTriggerEn = 1'b0,
parameter int unsigned DmHaltAddr = 32'h1A110800,
parameter int unsigned DmExceptionAddr = 32'h1A110808
@@ -106,10 +110,16 @@
logic [15:0] instr_rdata_c_id; // Compressed instruction sampled inside IF stage
logic instr_is_compressed_id;
logic instr_fetch_err; // Bus error on instr fetch
+ logic instr_fetch_err_plus2; // Instruction error is misaligned
logic illegal_c_insn_id; // Illegal compressed instruction sent to ID stage
logic [31:0] pc_if; // Program counter in IF stage
logic [31:0] pc_id; // Program counter in ID stage
+ logic [31:0] pc_wb; // Program counter in WB stage
+ logic icache_enable;
+ logic icache_inval;
+
+ logic instr_first_cycle_id;
logic instr_valid_clear;
logic pc_set;
pc_sel_e pc_mux_id; // Mux selector for next PC
@@ -124,25 +134,44 @@
logic [31:0] lsu_addr_last;
// Jump and branch target and decision (EX->IF)
- logic [31:0] jump_target_ex;
+ logic [31:0] branch_target_ex;
logic branch_decision;
// Core busy signals
logic ctrl_busy;
logic if_busy;
+ logic lsu_load;
logic lsu_busy;
logic core_busy_d, core_busy_q;
+ // Register File
+ logic [4:0] rf_raddr_a;
+ logic [31:0] rf_rdata_a;
+ logic [4:0] rf_raddr_b;
+ logic [31:0] rf_rdata_b;
+ logic [4:0] rf_waddr_wb;
+ logic [31:0] rf_wdata_wb;
+ // Writeback register write data that can be used on the forwarding path (doesn't factor in memory
+ // read data as this is too late for the forwarding path)
+ logic [31:0] rf_wdata_fwd_wb;
+ logic [31:0] rf_wdata_lsu;
+ logic rf_we_wb;
+ logic rf_we_lsu;
+
+ logic [4:0] rf_waddr_id;
+ logic [31:0] rf_wdata_id;
+ logic rf_we_id;
+
// ALU Control
alu_op_e alu_operator_ex;
logic [31:0] alu_operand_a_ex;
logic [31:0] alu_operand_b_ex;
- jt_mux_sel_e jt_mux_sel_ex;
- logic [11:0] bt_operand_imm_ex;
+ logic [31:0] bt_a_operand;
+ logic [31:0] bt_b_operand;
logic [31:0] alu_adder_result_ex; // Used to forward computed address to LSU
- logic [31:0] regfile_wdata_ex;
+ logic [31:0] result_ex;
// Multiplier Control
logic mult_en_ex;
@@ -152,11 +181,12 @@
logic [1:0] multdiv_signed_mode_ex;
logic [31:0] multdiv_operand_a_ex;
logic [31:0] multdiv_operand_b_ex;
+ logic multdiv_ready_id;
// CSR control
logic csr_access;
- logic valid_csr_id;
csr_op_e csr_op;
+ logic csr_op_en;
csr_num_e csr_addr;
logic [31:0] csr_rdata;
logic [31:0] csr_wdata;
@@ -165,12 +195,12 @@
// or missing write permissions
// Data Memory Control
- logic data_we_ex;
- logic [1:0] data_type_ex;
- logic data_sign_ext_ex;
- logic data_req_ex;
- logic [31:0] data_wdata_ex;
- logic [31:0] regfile_wdata_lsu;
+ logic lsu_we;
+ logic [1:0] lsu_type;
+ logic lsu_sign_ext;
+ logic lsu_req;
+ logic [31:0] lsu_wdata;
+ logic lsu_req_done;
// stall control
logic id_in_ready;
@@ -181,6 +211,14 @@
// Signals between instruction core interface and pipe (if and id stages)
logic instr_req_int; // Id stage asserts a req to instruction core interface
+ // Writeback stage
+ logic en_wb;
+ wb_instr_type_e instr_type_wb;
+ logic ready_wb;
+ logic rf_write_wb;
+ logic outstanding_load_wb;
+ logic outstanding_store_wb;
+
// Interrupts
logic irq_pending;
logic nmi_mode;
@@ -197,6 +235,7 @@
logic csr_save_if;
logic csr_save_id;
+ logic csr_save_wb;
logic csr_restore_mret_id;
logic csr_restore_dret_id;
logic csr_save_cause;
@@ -217,10 +256,16 @@
logic debug_ebreaku;
logic trigger_match;
- // performance counter related signals
- logic instr_ret;
- logic instr_ret_compressed;
- logic perf_imiss;
+ // signals relating to instruction movements between pipeline stages
+ // used by performance counters and RVFI
+ logic instr_id_done;
+ logic instr_id_done_compressed;
+ logic instr_done_wb;
+
+ logic perf_iside_wait;
+ logic perf_dside_wait;
+ logic perf_mul_wait;
+ logic perf_div_wait;
logic perf_jump;
logic perf_branch;
logic perf_tbranch;
@@ -232,7 +277,9 @@
// RISC-V Formal Interface signals
`ifdef RVFI
+ logic rvfi_instr_new_wb;
logic rvfi_intr_d;
+ logic rvfi_intr_q;
logic rvfi_set_trap_pc_d;
logic rvfi_set_trap_pc_q;
logic [31:0] rvfi_insn_id;
@@ -244,15 +291,13 @@
logic [31:0] rvfi_rs2_data_d;
logic [31:0] rvfi_rs2_data_id;
logic [31:0] rvfi_rs2_data_q;
- logic [4:0] rvfi_rd_addr_id;
+ logic [4:0] rvfi_rd_addr_wb;
logic [4:0] rvfi_rd_addr_q;
logic [4:0] rvfi_rd_addr_d;
- logic [31:0] rvfi_rd_wdata_id;
+ logic [31:0] rvfi_rd_wdata_wb;
logic [31:0] rvfi_rd_wdata_d;
logic [31:0] rvfi_rd_wdata_q;
- logic rvfi_rd_we_id;
- logic rvfi_insn_new_d;
- logic rvfi_insn_new_q;
+ logic rvfi_rd_we_wb;
logic [3:0] rvfi_mem_mask_int;
logic [31:0] rvfi_mem_rdata_d;
logic [31:0] rvfi_mem_rdata_q;
@@ -300,8 +345,10 @@
//////////////
ibex_if_stage #(
- .DmHaltAddr ( DmHaltAddr ),
- .DmExceptionAddr ( DmExceptionAddr )
+ .DmHaltAddr ( DmHaltAddr ),
+ .DmExceptionAddr ( DmExceptionAddr ),
+ .ICache ( ICache ),
+ .ICacheECC ( ICacheECC )
) if_stage_i (
.clk_i ( clk ),
.rst_ni ( rst_ni ),
@@ -326,6 +373,7 @@
.instr_rdata_c_id_o ( instr_rdata_c_id ),
.instr_is_compressed_id_o ( instr_is_compressed_id ),
.instr_fetch_err_o ( instr_fetch_err ),
+ .instr_fetch_err_plus2_o ( instr_fetch_err_plus2 ),
.illegal_c_insn_id_o ( illegal_c_insn_id ),
.pc_if_o ( pc_if ),
.pc_id_o ( pc_id ),
@@ -336,9 +384,11 @@
.pc_mux_i ( pc_mux_id ),
.exc_pc_mux_i ( exc_pc_mux_id ),
.exc_cause ( exc_cause ),
+ .icache_enable_i ( icache_enable ),
+ .icache_inval_i ( icache_inval ),
- // jump targets
- .jump_target_ex_i ( jump_target_ex ),
+ // branch targets
+ .branch_target_ex_i ( branch_target_ex ),
// CSRs
.csr_mepc_i ( csr_mepc ), // exception return address
@@ -349,10 +399,13 @@
// pipeline stalls
.id_in_ready_i ( id_in_ready ),
- .if_busy_o ( if_busy ),
- .perf_imiss_o ( perf_imiss )
+ .if_busy_o ( if_busy )
);
+ // Core is waiting for the ISide when ID/EX stage is ready for a new instruction but none are
+ // available
+ assign perf_iside_wait = id_in_ready & ~instr_valid_id;
+
// Qualify the instruction request with PMP error
assign instr_req_o = instr_req_out & ~pmp_req_err[PMP_I];
@@ -361,128 +414,146 @@
//////////////
ibex_id_stage #(
- .RV32E ( RV32E ),
- .RV32M ( RV32M ),
- .BranchTargetALU ( BranchTargetALU )
+ .RV32E ( RV32E ),
+ .RV32M ( RV32M ),
+ .RV32B ( RV32B ),
+ .BranchTargetALU ( BranchTargetALU ),
+ .WritebackStage ( WritebackStage )
) id_stage_i (
.clk_i ( clk ),
.rst_ni ( rst_ni ),
- .test_en_i ( test_en_i ),
-
// Processor Enable
.fetch_enable_i ( fetch_enable_i ),
.ctrl_busy_o ( ctrl_busy ),
.illegal_insn_o ( illegal_insn_id ),
// from/to IF-ID pipeline register
- .instr_valid_i ( instr_valid_id ),
- .instr_new_i ( instr_new_id ),
- .instr_rdata_i ( instr_rdata_id ),
- .instr_rdata_alu_i ( instr_rdata_alu_id ),
- .instr_rdata_c_i ( instr_rdata_c_id ),
- .instr_is_compressed_i ( instr_is_compressed_id ),
+ .instr_valid_i ( instr_valid_id ),
+ .instr_rdata_i ( instr_rdata_id ),
+ .instr_rdata_alu_i ( instr_rdata_alu_id ),
+ .instr_rdata_c_i ( instr_rdata_c_id ),
+ .instr_is_compressed_i ( instr_is_compressed_id ),
// Jumps and branches
- .branch_decision_i ( branch_decision ),
+ .branch_decision_i ( branch_decision ),
// IF and ID control signals
- .id_in_ready_o ( id_in_ready ),
- .instr_valid_clear_o ( instr_valid_clear ),
- .instr_req_o ( instr_req_int ),
- .pc_set_o ( pc_set ),
- .pc_mux_o ( pc_mux_id ),
- .exc_pc_mux_o ( exc_pc_mux_id ),
- .exc_cause_o ( exc_cause ),
+ .instr_first_cycle_id_o ( instr_first_cycle_id ),
+ .instr_valid_clear_o ( instr_valid_clear ),
+ .id_in_ready_o ( id_in_ready ),
+ .instr_req_o ( instr_req_int ),
+ .pc_set_o ( pc_set ),
+ .pc_mux_o ( pc_mux_id ),
+ .exc_pc_mux_o ( exc_pc_mux_id ),
+ .exc_cause_o ( exc_cause ),
+ .icache_inval_o ( icache_inval ),
- .instr_fetch_err_i ( instr_fetch_err ),
- .illegal_c_insn_i ( illegal_c_insn_id ),
+ .instr_fetch_err_i ( instr_fetch_err ),
+ .instr_fetch_err_plus2_i ( instr_fetch_err_plus2 ),
+ .illegal_c_insn_i ( illegal_c_insn_id ),
- .pc_id_i ( pc_id ),
+ .pc_id_i ( pc_id ),
// Stalls
- .ex_valid_i ( ex_valid ),
- .lsu_valid_i ( lsu_data_valid ),
+ .ex_valid_i ( ex_valid ),
+ .lsu_valid_i ( lsu_data_valid ),
+ .lsu_load_i ( lsu_load ),
+ .lsu_busy_i ( lsu_busy ),
- .alu_operator_ex_o ( alu_operator_ex ),
- .alu_operand_a_ex_o ( alu_operand_a_ex ),
- .alu_operand_b_ex_o ( alu_operand_b_ex ),
+ .alu_operator_ex_o ( alu_operator_ex ),
+ .alu_operand_a_ex_o ( alu_operand_a_ex ),
+ .alu_operand_b_ex_o ( alu_operand_b_ex ),
- .jt_mux_sel_ex_o ( jt_mux_sel_ex ),
- .bt_operand_imm_o ( bt_operand_imm_ex ),
+ .bt_a_operand_o ( bt_a_operand ),
+ .bt_b_operand_o ( bt_b_operand ),
- .mult_en_ex_o ( mult_en_ex ),
- .div_en_ex_o ( div_en_ex ),
- .multdiv_sel_ex_o ( multdiv_sel_ex ),
- .multdiv_operator_ex_o ( multdiv_operator_ex ),
- .multdiv_signed_mode_ex_o ( multdiv_signed_mode_ex ),
- .multdiv_operand_a_ex_o ( multdiv_operand_a_ex ),
- .multdiv_operand_b_ex_o ( multdiv_operand_b_ex ),
+ .mult_en_ex_o ( mult_en_ex ),
+ .div_en_ex_o ( div_en_ex ),
+ .multdiv_sel_ex_o ( multdiv_sel_ex ),
+ .multdiv_operator_ex_o ( multdiv_operator_ex ),
+ .multdiv_signed_mode_ex_o ( multdiv_signed_mode_ex ),
+ .multdiv_operand_a_ex_o ( multdiv_operand_a_ex ),
+ .multdiv_operand_b_ex_o ( multdiv_operand_b_ex ),
+ .multdiv_ready_id_o ( multdiv_ready_id ),
// CSR ID/EX
- .csr_access_o ( csr_access ),
- .csr_op_o ( csr_op ),
- .csr_save_if_o ( csr_save_if ), // control signal to save PC
- .csr_save_id_o ( csr_save_id ), // control signal to save PC
- .csr_restore_mret_id_o ( csr_restore_mret_id ), // restore mstatus upon DRET
- .csr_restore_dret_id_o ( csr_restore_dret_id ), // restore mstatus upon MRET
- .csr_save_cause_o ( csr_save_cause ),
- .csr_mtval_o ( csr_mtval ),
- .priv_mode_i ( priv_mode_id ),
- .csr_mstatus_tw_i ( csr_mstatus_tw ),
- .illegal_csr_insn_i ( illegal_csr_insn_id ),
+ .csr_access_o ( csr_access ),
+ .csr_op_o ( csr_op ),
+ .csr_op_en_o ( csr_op_en ),
+ .csr_save_if_o ( csr_save_if ), // control signal to save PC
+ .csr_save_id_o ( csr_save_id ), // control signal to save PC
+ .csr_save_wb_o ( csr_save_wb ), // control signal to save PC
+ .csr_restore_mret_id_o ( csr_restore_mret_id ), // restore mstatus upon MRET
+ .csr_restore_dret_id_o ( csr_restore_dret_id ), // restore mstatus upon MRET
+ .csr_save_cause_o ( csr_save_cause ),
+ .csr_mtval_o ( csr_mtval ),
+ .priv_mode_i ( priv_mode_id ),
+ .csr_mstatus_tw_i ( csr_mstatus_tw ),
+ .illegal_csr_insn_i ( illegal_csr_insn_id ),
// LSU
- .data_req_ex_o ( data_req_ex ), // to load store unit
- .data_we_ex_o ( data_we_ex ), // to load store unit
- .data_type_ex_o ( data_type_ex ), // to load store unit
- .data_sign_ext_ex_o ( data_sign_ext_ex ), // to load store unit
- .data_wdata_ex_o ( data_wdata_ex ), // to load store unit
+ .lsu_req_o ( lsu_req ), // to load store unit
+ .lsu_we_o ( lsu_we ), // to load store unit
+ .lsu_type_o ( lsu_type ), // to load store unit
+ .lsu_sign_ext_o ( lsu_sign_ext ), // to load store unit
+ .lsu_wdata_o ( lsu_wdata ), // to load store unit
+ .lsu_req_done_i ( lsu_req_done ), // from load store unit
- .lsu_addr_incr_req_i ( lsu_addr_incr_req ),
- .lsu_addr_last_i ( lsu_addr_last ),
+ .lsu_addr_incr_req_i ( lsu_addr_incr_req ),
+ .lsu_addr_last_i ( lsu_addr_last ),
- .lsu_load_err_i ( lsu_load_err ),
- .lsu_store_err_i ( lsu_store_err ),
+ .lsu_load_err_i ( lsu_load_err ),
+ .lsu_store_err_i ( lsu_store_err ),
// Interrupt Signals
- .csr_mstatus_mie_i ( csr_mstatus_mie ),
- .irq_pending_i ( irq_pending ),
- .irqs_i ( irqs ),
- .irq_nm_i ( irq_nm_i ),
- .nmi_mode_o ( nmi_mode ),
+ .csr_mstatus_mie_i ( csr_mstatus_mie ),
+ .irq_pending_i ( irq_pending ),
+ .irqs_i ( irqs ),
+ .irq_nm_i ( irq_nm_i ),
+ .nmi_mode_o ( nmi_mode ),
// Debug Signal
- .debug_mode_o ( debug_mode ),
- .debug_cause_o ( debug_cause ),
- .debug_csr_save_o ( debug_csr_save ),
- .debug_req_i ( debug_req_i ),
- .debug_single_step_i ( debug_single_step ),
- .debug_ebreakm_i ( debug_ebreakm ),
- .debug_ebreaku_i ( debug_ebreaku ),
- .trigger_match_i ( trigger_match ),
+ .debug_mode_o ( debug_mode ),
+ .debug_cause_o ( debug_cause ),
+ .debug_csr_save_o ( debug_csr_save ),
+ .debug_req_i ( debug_req_i ),
+ .debug_single_step_i ( debug_single_step ),
+ .debug_ebreakm_i ( debug_ebreakm ),
+ .debug_ebreaku_i ( debug_ebreaku ),
+ .trigger_match_i ( trigger_match ),
// write data to commit in the register file
- .regfile_wdata_lsu_i ( regfile_wdata_lsu ),
- .regfile_wdata_ex_i ( regfile_wdata_ex ),
- .csr_rdata_i ( csr_rdata ),
+ .result_ex_i ( result_ex ),
+ .csr_rdata_i ( csr_rdata ),
-`ifdef RVFI
- .rfvi_reg_raddr_ra_o ( rvfi_rs1_addr_id ),
- .rfvi_reg_rdata_ra_o ( rvfi_rs1_data_id ),
- .rfvi_reg_raddr_rb_o ( rvfi_rs2_addr_id ),
- .rfvi_reg_rdata_rb_o ( rvfi_rs2_data_id ),
- .rfvi_reg_waddr_rd_o ( rvfi_rd_addr_id ),
- .rfvi_reg_wdata_rd_o ( rvfi_rd_wdata_id ),
- .rfvi_reg_we_o ( rvfi_rd_we_id ),
-`endif
+ .rf_raddr_a_o ( rf_raddr_a ),
+ .rf_rdata_a_i ( rf_rdata_a ),
+ .rf_raddr_b_o ( rf_raddr_b ),
+ .rf_rdata_b_i ( rf_rdata_b ),
+ .rf_waddr_id_o ( rf_waddr_id ),
+ .rf_wdata_id_o ( rf_wdata_id ),
+ .rf_we_id_o ( rf_we_id ),
+
+ .rf_waddr_wb_i ( rf_waddr_wb ),
+ .rf_wdata_fwd_wb_i ( rf_wdata_fwd_wb ),
+ .rf_write_wb_i ( rf_write_wb ),
+
+ .en_wb_o ( en_wb ),
+ .instr_type_wb_o ( instr_type_wb ),
+ .ready_wb_i ( ready_wb ),
+ .outstanding_load_wb_i ( outstanding_load_wb ),
+ .outstanding_store_wb_i ( outstanding_store_wb ),
// Performance Counters
- .perf_jump_o ( perf_jump ),
- .perf_branch_o ( perf_branch ),
- .perf_tbranch_o ( perf_tbranch ),
- .instr_ret_o ( instr_ret ),
- .instr_ret_compressed_o ( instr_ret_compressed )
+ .perf_jump_o ( perf_jump ),
+ .perf_branch_o ( perf_branch ),
+ .perf_tbranch_o ( perf_tbranch ),
+ .perf_dside_wait_o ( perf_dside_wait ),
+ .perf_mul_wait_o ( perf_mul_wait ),
+ .perf_div_wait_o ( perf_div_wait ),
+ .instr_id_done_o ( instr_id_done ),
+ .instr_id_done_compressed_o ( instr_id_done_compressed )
);
// for RVFI only
@@ -490,21 +561,20 @@
ibex_ex_block #(
.RV32M ( RV32M ),
+ .RV32B ( RV32B ),
.BranchTargetALU ( BranchTargetALU ),
.MultiplierImplementation ( MultiplierImplementation )
) ex_block_i (
.clk_i ( clk ),
.rst_ni ( rst_ni ),
-
// ALU signal from ID stage
.alu_operator_i ( alu_operator_ex ),
.alu_operand_a_i ( alu_operand_a_ex ),
.alu_operand_b_i ( alu_operand_b_ex ),
// Branch target ALU signal from ID stage
- .jt_mux_sel_i ( jt_mux_sel_ex ),
- .bt_operand_imm_i ( bt_operand_imm_ex ),
- .pc_id_i ( pc_id ),
+ .bt_a_operand_i ( bt_a_operand ),
+ .bt_b_operand_i ( bt_b_operand ),
// Multipler/Divider signal from ID stage
.multdiv_operator_i ( multdiv_operator_ex ),
@@ -514,12 +584,13 @@
.multdiv_signed_mode_i ( multdiv_signed_mode_ex ),
.multdiv_operand_a_i ( multdiv_operand_a_ex ),
.multdiv_operand_b_i ( multdiv_operand_b_ex ),
+ .multdiv_ready_id_i ( multdiv_ready_id ),
// Outputs
.alu_adder_result_ex_o ( alu_adder_result_ex ), // to LSU
- .regfile_wdata_ex_o ( regfile_wdata_ex ), // to ID
+ .result_ex_o ( result_ex ), // to ID
- .jump_target_o ( jump_target_ex ), // to IF
+ .branch_target_o ( branch_target_ex ), // to IF
.branch_decision_o ( branch_decision ), // to ID
.ex_valid_o ( ex_valid )
@@ -531,7 +602,7 @@
assign data_req_o = data_req_out & ~pmp_req_err[PMP_D];
- ibex_load_store_unit load_store_unit_i (
+ ibex_load_store_unit load_store_unit_i (
.clk_i ( clk ),
.rst_ni ( rst_ni ),
@@ -549,30 +620,143 @@
.data_rdata_i ( data_rdata_i ),
// signals to/from ID/EX stage
- .data_we_ex_i ( data_we_ex ),
- .data_type_ex_i ( data_type_ex ),
- .data_wdata_ex_i ( data_wdata_ex ),
- .data_sign_ext_ex_i ( data_sign_ext_ex ),
+ .lsu_we_i ( lsu_we ),
+ .lsu_type_i ( lsu_type ),
+ .lsu_wdata_i ( lsu_wdata ),
+ .lsu_sign_ext_i ( lsu_sign_ext ),
- .data_rdata_ex_o ( regfile_wdata_lsu ),
- .data_req_ex_i ( data_req_ex ),
+ .lsu_rdata_o ( rf_wdata_lsu ),
+ .lsu_rdata_valid_o ( rf_we_lsu ),
+ .lsu_req_i ( lsu_req ),
+ .lsu_req_done_o ( lsu_req_done ),
.adder_result_ex_i ( alu_adder_result_ex ),
.addr_incr_req_o ( lsu_addr_incr_req ),
.addr_last_o ( lsu_addr_last ),
- .data_valid_o ( lsu_data_valid ),
+
+
+ .lsu_resp_valid_o ( lsu_data_valid ),
// exception signals
.load_err_o ( lsu_load_err ),
.store_err_o ( lsu_store_err ),
+ .load_o ( lsu_load ),
.busy_o ( lsu_busy ),
+ .perf_load_o ( perf_load ),
+ .perf_store_o ( perf_store ),
+
.illegal_insn_id_i ( illegal_insn_id ),
.instr_valid_id_i ( instr_valid_id )
);
+ ibex_wb_stage #(
+ .WritebackStage ( WritebackStage )
+ ) wb_stage_i (
+ .clk_i ( clk_i ),
+ .rst_ni ( rst_ni ),
+ .en_wb_i ( en_wb ),
+ .instr_type_wb_i ( instr_type_wb ),
+ .pc_id_i ( pc_id ),
+
+ .ready_wb_o ( ready_wb ),
+ .rf_write_wb_o ( rf_write_wb ),
+ .outstanding_load_wb_o ( outstanding_load_wb ),
+ .outstanding_store_wb_o ( outstanding_store_wb ),
+ .pc_wb_o ( pc_wb ),
+
+ .rf_waddr_id_i ( rf_waddr_id ),
+ .rf_wdata_id_i ( rf_wdata_id ),
+ .rf_we_id_i ( rf_we_id ),
+
+ .rf_wdata_lsu_i ( rf_wdata_lsu ),
+ .rf_we_lsu_i ( rf_we_lsu ),
+
+ .rf_wdata_fwd_wb_o ( rf_wdata_fwd_wb ),
+
+ .rf_waddr_wb_o ( rf_waddr_wb ),
+ .rf_wdata_wb_o ( rf_wdata_wb ),
+ .rf_we_wb_o ( rf_we_wb ),
+
+ .lsu_data_valid_i ( lsu_data_valid ),
+
+ .instr_done_wb_o ( instr_done_wb )
+ );
+
+ ibex_register_file #(
+ .RV32E(RV32E),
+ .DataWidth(32)
+ ) register_file_i (
+ .clk_i ( clk_i ),
+ .rst_ni ( rst_ni ),
+
+ .test_en_i ( test_en_i ),
+
+ // Read port a
+ .raddr_a_i ( rf_raddr_a ),
+ .rdata_a_o ( rf_rdata_a ),
+ // Read port b
+ .raddr_b_i ( rf_raddr_b ),
+ .rdata_b_o ( rf_rdata_b ),
+ // write port
+ .waddr_a_i ( rf_waddr_wb ),
+ .wdata_a_i ( rf_wdata_wb ),
+ .we_a_i ( rf_we_wb )
+ );
+
+ // Explict INC_ASSERT block to avoid unused signal lint warnings were asserts are not included
+ `ifdef INC_ASSERT
+ // Signals used for assertions only
+ logic outstanding_load_resp;
+ logic outstanding_store_resp;
+
+ logic outstanding_load_id;
+ logic outstanding_store_id;
+
+ assign outstanding_load_id = id_stage_i.instr_executing & id_stage_i.lsu_req_dec & ~id_stage_i.lsu_we;
+ assign outstanding_store_id = id_stage_i.instr_executing & id_stage_i.lsu_req_dec & id_stage_i.lsu_we;
+
+ if (WritebackStage) begin
+ // When the writeback stage is present a load/store could be in ID or WB. A Load/store in ID can
+ // see a response before it moves to WB when it is unaligned otherwise we should only see
+ // a response when load/store is in WB.
+ assign outstanding_load_resp = outstanding_load_wb |
+ (outstanding_load_id & load_store_unit_i.split_misaligned_access);
+
+ assign outstanding_store_resp = outstanding_store_wb |
+ (outstanding_store_id & load_store_unit_i.split_misaligned_access);
+
+ // When writing back the result of a load, the load must have made it to writeback
+ `ASSERT(NoMemRFWriteWithoutPendingLoad, rf_we_lsu |-> outstanding_load_wb, clk_i, !rst_ni)
+ end else begin
+ // Without writeback stage only look into whether load or store is in ID to determine if
+ // a response is expected.
+ assign outstanding_load_resp = outstanding_load_id;
+ assign outstanding_store_resp = outstanding_store_id;
+
+ `ASSERT(NoMemRFWriteWithoutPendingLoad, rf_we_lsu |-> outstanding_load_id, clk_i, !rst_ni)
+ end
+
+ `ASSERT(NoMemResponseWithoutPendingAccess,
+ data_rvalid_i |-> outstanding_load_resp | outstanding_store_resp, clk_i, !rst_ni)
+ `endif
+
+ ////////////////////////
+ // RF (Register File) //
+ ////////////////////////
+`ifdef RVFI
+ assign rvfi_rs1_addr_id = rf_raddr_a;
+ assign rvfi_rs1_data_id = id_stage_i.rf_rdata_a_fwd;
+ assign rvfi_rs2_addr_id = rf_raddr_b;
+ assign rvfi_rs2_data_id = id_stage_i.rf_rdata_b_fwd;
+
+ assign rvfi_rd_addr_wb = rf_waddr_wb;
+ assign rvfi_rd_wdata_wb = rf_we_wb ? rf_wdata_wb : rf_wdata_lsu;
+ assign rvfi_rd_we_wb = rf_we_wb | rf_we_lsu;
+`endif
+
/////////////////////////////////////////
// CSRs (Control and Status Registers) //
@@ -581,14 +765,9 @@
assign csr_wdata = alu_operand_a_ex;
assign csr_addr = csr_num_e'(csr_access ? alu_operand_b_ex[11:0] : 12'b0);
- assign perf_load = data_req_o & data_gnt_i & (~data_we_o);
- assign perf_store = data_req_o & data_gnt_i & data_we_o;
-
- // CSR access is qualified by instruction fetch error
- assign valid_csr_id = instr_new_id & ~instr_fetch_err;
-
ibex_cs_registers #(
.DbgTriggerEn ( DbgTriggerEn ),
+ .ICache ( ICache ),
.MHPMCounterNum ( MHPMCounterNum ),
.MHPMCounterWidth ( MHPMCounterWidth ),
.PMPEnable ( PMPEnable ),
@@ -597,80 +776,93 @@
.RV32E ( RV32E ),
.RV32M ( RV32M )
) cs_registers_i (
- .clk_i ( clk ),
- .rst_ni ( rst_ni ),
+ .clk_i ( clk ),
+ .rst_ni ( rst_ni ),
// Hart ID from outside
- .hart_id_i ( hart_id_i ),
- .priv_mode_id_o ( priv_mode_id ),
- .priv_mode_if_o ( priv_mode_if ),
- .priv_mode_lsu_o ( priv_mode_lsu ),
+ .hart_id_i ( hart_id_i ),
+ .priv_mode_id_o ( priv_mode_id ),
+ .priv_mode_if_o ( priv_mode_if ),
+ .priv_mode_lsu_o ( priv_mode_lsu ),
// mtvec
- .csr_mtvec_o ( csr_mtvec ),
- .csr_mtvec_init_i ( csr_mtvec_init ),
- .boot_addr_i ( boot_addr_i ),
+ .csr_mtvec_o ( csr_mtvec ),
+ .csr_mtvec_init_i ( csr_mtvec_init ),
+ .boot_addr_i ( boot_addr_i ),
- // Interface to CSRs (SRAM like)
- .csr_access_i ( csr_access ),
- .csr_addr_i ( csr_addr ),
- .csr_wdata_i ( csr_wdata ),
- .csr_op_i ( csr_op ),
- .csr_rdata_o ( csr_rdata ),
+ // Interface to CSRs ( SRAM like )
+ .csr_access_i ( csr_access ),
+ .csr_addr_i ( csr_addr ),
+ .csr_wdata_i ( csr_wdata ),
+ .csr_op_i ( csr_op ),
+ .csr_op_en_i ( csr_op_en ),
+ .csr_rdata_o ( csr_rdata ),
// Interrupt related control signals
- .irq_software_i ( irq_software_i ),
- .irq_timer_i ( irq_timer_i ),
- .irq_external_i ( irq_external_i ),
- .irq_fast_i ( irq_fast_i ),
- .nmi_mode_i ( nmi_mode ),
- .irq_pending_o ( irq_pending ),
- .irqs_o ( irqs ),
- .csr_mstatus_mie_o ( csr_mstatus_mie ),
- .csr_mstatus_tw_o ( csr_mstatus_tw ),
- .csr_mepc_o ( csr_mepc ),
+ .irq_software_i ( irq_software_i ),
+ .irq_timer_i ( irq_timer_i ),
+ .irq_external_i ( irq_external_i ),
+ .irq_fast_i ( irq_fast_i ),
+ .nmi_mode_i ( nmi_mode ),
+ .irq_pending_o ( irq_pending ),
+ .irqs_o ( irqs ),
+ .csr_mstatus_mie_o ( csr_mstatus_mie ),
+ .csr_mstatus_tw_o ( csr_mstatus_tw ),
+ .csr_mepc_o ( csr_mepc ),
// PMP
- .csr_pmp_cfg_o ( csr_pmp_cfg ),
- .csr_pmp_addr_o ( csr_pmp_addr ),
+ .csr_pmp_cfg_o ( csr_pmp_cfg ),
+ .csr_pmp_addr_o ( csr_pmp_addr ),
// debug
- .csr_depc_o ( csr_depc ),
- .debug_mode_i ( debug_mode ),
- .debug_cause_i ( debug_cause ),
- .debug_csr_save_i ( debug_csr_save ),
- .debug_single_step_o ( debug_single_step ),
- .debug_ebreakm_o ( debug_ebreakm ),
- .debug_ebreaku_o ( debug_ebreaku ),
- .trigger_match_o ( trigger_match ),
+ .csr_depc_o ( csr_depc ),
+ .debug_mode_i ( debug_mode ),
+ .debug_cause_i ( debug_cause ),
+ .debug_csr_save_i ( debug_csr_save ),
+ .debug_single_step_o ( debug_single_step ),
+ .debug_ebreakm_o ( debug_ebreakm ),
+ .debug_ebreaku_o ( debug_ebreaku ),
+ .trigger_match_o ( trigger_match ),
- .pc_if_i ( pc_if ),
- .pc_id_i ( pc_id ),
+ .pc_if_i ( pc_if ),
+ .pc_id_i ( pc_id ),
+ .pc_wb_i ( pc_wb ),
- .csr_save_if_i ( csr_save_if ),
- .csr_save_id_i ( csr_save_id ),
- .csr_restore_mret_i ( csr_restore_mret_id ),
- .csr_restore_dret_i ( csr_restore_dret_id ),
- .csr_save_cause_i ( csr_save_cause ),
- .csr_mcause_i ( exc_cause ),
- .csr_mtval_i ( csr_mtval ),
- .illegal_csr_insn_o ( illegal_csr_insn_id ),
+ .icache_enable_o ( icache_enable ),
- .instr_new_id_i ( valid_csr_id ),
+ .csr_save_if_i ( csr_save_if ),
+ .csr_save_id_i ( csr_save_id ),
+ .csr_save_wb_i ( csr_save_wb ),
+ .csr_restore_mret_i ( csr_restore_mret_id ),
+ .csr_restore_dret_i ( csr_restore_dret_id ),
+ .csr_save_cause_i ( csr_save_cause ),
+ .csr_mcause_i ( exc_cause ),
+ .csr_mtval_i ( csr_mtval ),
+ .illegal_csr_insn_o ( illegal_csr_insn_id ),
// performance counter related signals
- .instr_ret_i ( instr_ret ),
- .instr_ret_compressed_i ( instr_ret_compressed ),
- .imiss_i ( perf_imiss ),
- .pc_set_i ( pc_set ),
- .jump_i ( perf_jump ),
- .branch_i ( perf_branch ),
- .branch_taken_i ( perf_tbranch ),
- .mem_load_i ( perf_load ),
- .mem_store_i ( perf_store ),
- .lsu_busy_i ( lsu_busy )
+ .instr_ret_i ( instr_id_done ),
+ .instr_ret_compressed_i ( instr_id_done_compressed ),
+ .iside_wait_i ( perf_iside_wait ),
+ .jump_i ( perf_jump ),
+ .branch_i ( perf_branch ),
+ .branch_taken_i ( perf_tbranch ),
+ .mem_load_i ( perf_load ),
+ .mem_store_i ( perf_store ),
+ .dside_wait_i ( perf_dside_wait ),
+ .mul_wait_i ( perf_mul_wait ),
+ .div_wait_i ( perf_div_wait )
);
+ // These assertions are in top-level as instr_valid_id required as the enable term
+ `ASSERT(IbexCsrOpValid, instr_valid_id |-> csr_op inside {
+ CSR_OP_READ,
+ CSR_OP_WRITE,
+ CSR_OP_SET,
+ CSR_OP_CLEAR
+ })
+ `ASSERT_KNOWN_IF(IbexCsrWdataIntKnown, cs_registers_i.csr_wdata_int, csr_access & instr_valid_id)
+
if (PMPEnable) begin : g_pmp
logic [33:0] pmp_req_addr [PMP_NUM_CHAN];
pmp_req_e pmp_req_type [PMP_NUM_CHAN];
@@ -715,64 +907,195 @@
end
`ifdef RVFI
- always_ff @(posedge clk or negedge rst_ni) begin
- if (!rst_ni) begin
- rvfi_halt <= '0;
- rvfi_trap <= '0;
- rvfi_intr <= '0;
- rvfi_order <= '0;
- rvfi_insn <= '0;
- rvfi_mode <= {PRIV_LVL_M};
- rvfi_rs1_addr <= '0;
- rvfi_rs2_addr <= '0;
- rvfi_pc_rdata <= '0;
- rvfi_pc_wdata <= '0;
- rvfi_mem_rmask <= '0;
- rvfi_mem_wmask <= '0;
- rvfi_valid <= '0;
- rvfi_rs1_rdata <= '0;
- rvfi_rs2_rdata <= '0;
- rvfi_rd_wdata <= '0;
- rvfi_rd_addr <= '0;
- rvfi_mem_rdata <= '0;
- rvfi_mem_wdata <= '0;
- rvfi_mem_addr <= '0;
- end else begin
- rvfi_halt <= '0;
- rvfi_trap <= illegal_insn_id;
- rvfi_intr <= rvfi_intr_d;
- rvfi_order <= rvfi_order + 64'(rvfi_valid);
- rvfi_insn <= rvfi_insn_id;
- rvfi_mode <= {priv_mode_id};
- rvfi_rs1_addr <= rvfi_rs1_addr_id;
- rvfi_rs2_addr <= rvfi_rs2_addr_id;
- rvfi_pc_rdata <= pc_id;
- rvfi_pc_wdata <= pc_if;
- rvfi_mem_rmask <= rvfi_mem_mask_int;
- rvfi_mem_wmask <= data_we_o ? rvfi_mem_mask_int : 4'b0000;
- rvfi_valid <= instr_ret;
- rvfi_rs1_rdata <= rvfi_rs1_data_d;
- rvfi_rs2_rdata <= rvfi_rs2_data_d;
- rvfi_rd_wdata <= rvfi_rd_wdata_d;
- rvfi_rd_addr <= rvfi_rd_addr_d;
- rvfi_mem_rdata <= rvfi_mem_rdata_d;
- rvfi_mem_wdata <= rvfi_mem_wdata_d;
- rvfi_mem_addr <= rvfi_mem_addr_d;
+ // When writeback stage is present RVFI information is emitted when instruction is finished in
+ // third stage but some information must be captured whilst the instruction is in the second
+ // stage. Without writeback stage RVFI information is all emitted when instruction retires in
+ // second stage. RVFI outputs are all straight from flops. So 2 stage pipeline requires a single
+ // set of flops (instr_info => RVFI_out), 3 stage pipeline requires two sets (instr_info => wb
+ // => RVFI_out)
+ localparam RVFI_STAGES = WritebackStage ? 2 : 1;
+
+ logic rvfi_stage_valid [RVFI_STAGES-1:0];
+ logic [63:0] rvfi_stage_order [RVFI_STAGES-1:0];
+ logic [31:0] rvfi_stage_insn [RVFI_STAGES-1:0];
+ logic rvfi_stage_trap [RVFI_STAGES-1:0];
+ logic rvfi_stage_halt [RVFI_STAGES-1:0];
+ logic rvfi_stage_intr [RVFI_STAGES-1:0];
+ logic [ 1:0] rvfi_stage_mode [RVFI_STAGES-1:0];
+ logic [ 4:0] rvfi_stage_rs1_addr [RVFI_STAGES-1:0];
+ logic [ 4:0] rvfi_stage_rs2_addr [RVFI_STAGES-1:0];
+ logic [31:0] rvfi_stage_rs1_rdata [RVFI_STAGES-1:0];
+ logic [31:0] rvfi_stage_rs2_rdata [RVFI_STAGES-1:0];
+ logic [ 4:0] rvfi_stage_rd_addr [RVFI_STAGES-1:0];
+ logic [31:0] rvfi_stage_rd_wdata [RVFI_STAGES-1:0];
+ logic [31:0] rvfi_stage_pc_rdata [RVFI_STAGES-1:0];
+ logic [31:0] rvfi_stage_pc_wdata [RVFI_STAGES-1:0];
+ logic [31:0] rvfi_stage_mem_addr [RVFI_STAGES-1:0];
+ logic [ 3:0] rvfi_stage_mem_rmask [RVFI_STAGES-1:0];
+ logic [ 3:0] rvfi_stage_mem_wmask [RVFI_STAGES-1:0];
+ logic [31:0] rvfi_stage_mem_rdata [RVFI_STAGES-1:0];
+ logic [31:0] rvfi_stage_mem_wdata [RVFI_STAGES-1:0];
+
+ logic rvfi_stage_valid_d [RVFI_STAGES-1:0];
+
+ assign rvfi_valid = rvfi_stage_valid [RVFI_STAGES-1];
+ assign rvfi_order = rvfi_stage_order [RVFI_STAGES-1];
+ assign rvfi_insn = rvfi_stage_insn [RVFI_STAGES-1];
+ assign rvfi_trap = rvfi_stage_trap [RVFI_STAGES-1];
+ assign rvfi_halt = rvfi_stage_halt [RVFI_STAGES-1];
+ assign rvfi_intr = rvfi_stage_intr [RVFI_STAGES-1];
+ assign rvfi_mode = rvfi_stage_mode [RVFI_STAGES-1];
+ assign rvfi_rs1_addr = rvfi_stage_rs1_addr [RVFI_STAGES-1];
+ assign rvfi_rs2_addr = rvfi_stage_rs2_addr [RVFI_STAGES-1];
+ assign rvfi_rs1_rdata = rvfi_stage_rs1_rdata[RVFI_STAGES-1];
+ assign rvfi_rs2_rdata = rvfi_stage_rs2_rdata[RVFI_STAGES-1];
+ assign rvfi_rd_addr = rvfi_stage_rd_addr [RVFI_STAGES-1];
+ assign rvfi_rd_wdata = rvfi_stage_rd_wdata [RVFI_STAGES-1];
+ assign rvfi_pc_rdata = rvfi_stage_pc_rdata [RVFI_STAGES-1];
+ assign rvfi_pc_wdata = rvfi_stage_pc_wdata [RVFI_STAGES-1];
+ assign rvfi_mem_addr = rvfi_stage_mem_addr [RVFI_STAGES-1];
+ assign rvfi_mem_rmask = rvfi_stage_mem_rmask[RVFI_STAGES-1];
+ assign rvfi_mem_wmask = rvfi_stage_mem_wmask[RVFI_STAGES-1];
+ assign rvfi_mem_rdata = rvfi_stage_mem_rdata[RVFI_STAGES-1];
+ assign rvfi_mem_wdata = rvfi_stage_mem_wdata[RVFI_STAGES-1];
+
+ if (WritebackStage) begin
+ logic unused_instr_new_id;
+
+ assign unused_instr_new_id = instr_new_id;
+
+ // With writeback stage first RVFI stage buffers instruction information captured in ID/EX
+ // awaiting instruction retirement and RF Write data/Mem read data whilst instruction is in WB
+ // So first stage becomes valid when instruction leaves ID/EX stage and remains valid until
+ // instruction leaves WB
+ assign rvfi_stage_valid_d[0] = instr_id_done | (rvfi_stage_valid[0] & ~instr_done_wb);
+ // Second stage is output stage so simple valid cycle after instruction leaves WB (and so has
+ // retired)
+ assign rvfi_stage_valid_d[1] = instr_done_wb;
+
+ // Signal new instruction in WB cycle after instruction leaves ID/EX (to enter WB)
+ logic rvfi_instr_new_wb_q;
+
+ assign rvfi_instr_new_wb = rvfi_instr_new_wb_q;
+
+ always_ff @(posedge clk or negedge rst_ni) begin
+ if (~rst_ni) begin
+ rvfi_instr_new_wb_q <= 0;
+ end else begin
+ rvfi_instr_new_wb_q <= instr_id_done;
+ end
+ end
+ end else begin
+ // Without writeback stage first RVFI stage is output stage so simply valid the cycle after
+ // instruction leaves ID/EX (and so has retired)
+ assign rvfi_stage_valid_d[0] = instr_id_done;
+ // Without writeback stage signal new instr_new_wb when instruction enters ID/EX to correctly
+ // setup register write signals
+ assign rvfi_instr_new_wb = instr_new_id;
+ end
+
+ for (genvar i = 0;i < RVFI_STAGES; i = i + 1) begin : g_rvfi_stages
+ always_ff @(posedge clk or negedge rst_ni) begin
+ if (!rst_ni) begin
+ rvfi_stage_halt[i] <= '0;
+ rvfi_stage_trap[i] <= '0;
+ rvfi_stage_intr[i] <= '0;
+ rvfi_stage_order[i] <= '0;
+ rvfi_stage_insn[i] <= '0;
+ rvfi_stage_mode[i] <= {PRIV_LVL_M};
+ rvfi_stage_rs1_addr[i] <= '0;
+ rvfi_stage_rs2_addr[i] <= '0;
+ rvfi_stage_pc_rdata[i] <= '0;
+ rvfi_stage_pc_wdata[i] <= '0;
+ rvfi_stage_mem_rmask[i] <= '0;
+ rvfi_stage_mem_wmask[i] <= '0;
+ rvfi_stage_valid[i] <= '0;
+ rvfi_stage_rs1_rdata[i] <= '0;
+ rvfi_stage_rs2_rdata[i] <= '0;
+ rvfi_stage_rd_wdata[i] <= '0;
+ rvfi_stage_rd_addr[i] <= '0;
+ rvfi_stage_mem_rdata[i] <= '0;
+ rvfi_stage_mem_wdata[i] <= '0;
+ rvfi_stage_mem_addr[i] <= '0;
+ end else begin
+ rvfi_stage_valid[i] <= rvfi_stage_valid_d[i];
+
+ if (i == 0) begin
+ if(instr_id_done) begin
+ rvfi_stage_halt[i] <= '0;
+ rvfi_stage_trap[i] <= illegal_insn_id;
+ rvfi_stage_intr[i] <= rvfi_intr_d;
+ rvfi_stage_order[i] <= rvfi_order + 64'(rvfi_valid);
+ rvfi_stage_insn[i] <= rvfi_insn_id;
+ rvfi_stage_mode[i] <= {priv_mode_id};
+ rvfi_stage_rs1_addr[i] <= rvfi_rs1_addr_id;
+ rvfi_stage_rs2_addr[i] <= rvfi_rs2_addr_id;
+ rvfi_stage_pc_rdata[i] <= pc_id;
+ rvfi_stage_pc_wdata[i] <= pc_if;
+ rvfi_stage_mem_rmask[i] <= rvfi_mem_mask_int;
+ rvfi_stage_mem_wmask[i] <= data_we_o ? rvfi_mem_mask_int : 4'b0000;
+ rvfi_stage_rs1_rdata[i] <= rvfi_rs1_data_d;
+ rvfi_stage_rs2_rdata[i] <= rvfi_rs2_data_d;
+ rvfi_stage_rd_addr[i] <= rvfi_rd_addr_d;
+ rvfi_stage_rd_wdata[i] <= rvfi_rd_wdata_d;
+ rvfi_stage_mem_rdata[i] <= rvfi_mem_rdata_d;
+ rvfi_stage_mem_wdata[i] <= rvfi_mem_wdata_d;
+ rvfi_stage_mem_addr[i] <= rvfi_mem_addr_d;
+ end
+ end else begin
+ if(instr_done_wb) begin
+ rvfi_stage_halt[i] <= rvfi_stage_halt[i-1];
+ rvfi_stage_trap[i] <= rvfi_stage_trap[i-1];
+ rvfi_stage_intr[i] <= rvfi_stage_intr[i-1];
+ rvfi_stage_order[i] <= rvfi_stage_order[i-1];
+ rvfi_stage_insn[i] <= rvfi_stage_insn[i-1];
+ rvfi_stage_mode[i] <= rvfi_stage_mode[i-1];
+ rvfi_stage_rs1_addr[i] <= rvfi_stage_rs1_addr[i-1];
+ rvfi_stage_rs2_addr[i] <= rvfi_stage_rs2_addr[i-1];
+ rvfi_stage_pc_rdata[i] <= rvfi_stage_pc_rdata[i-1];
+ rvfi_stage_pc_wdata[i] <= rvfi_stage_pc_wdata[i-1];
+ rvfi_stage_mem_rmask[i] <= rvfi_stage_mem_rmask[i-1];
+ rvfi_stage_mem_wmask[i] <= rvfi_stage_mem_wmask[i-1];
+ rvfi_stage_rs1_rdata[i] <= rvfi_stage_rs1_rdata[i-1];
+ rvfi_stage_rs2_rdata[i] <= rvfi_stage_rs2_rdata[i-1];
+ rvfi_stage_rd_addr[i] <= rvfi_stage_rd_addr[i-1];
+ rvfi_stage_mem_wdata[i] <= rvfi_stage_mem_wdata[i-1];
+ rvfi_stage_mem_addr[i] <= rvfi_stage_mem_addr[i-1];
+
+ // For 2 RVFI_STAGES/Writeback Stage ignore first stage flops for rd_addr, rd_wdata and
+ // mem_rdata. For RF write addr/data actual write happens in writeback so capture
+ // address/data there. For mem_rdata that is only available from the writeback stage.
+ // Previous stage flops still exist in RTL as they are used by the non writeback config
+ rvfi_stage_rd_addr[i] <= rvfi_rd_addr_d;
+ rvfi_stage_rd_wdata[i] <= rvfi_rd_wdata_d;
+ rvfi_stage_mem_rdata[i] <= rvfi_mem_rdata_d;
+ end
+ end
+ end
end
end
- // Keep the mem data stable for each instruction cycle
+
+ // Memory adddress/write data available first cycle of ld/st instruction from register read
always_comb begin
- if (rvfi_insn_new_d && lsu_data_valid) begin
+ if (instr_first_cycle_id) begin
rvfi_mem_addr_d = alu_adder_result_ex;
- rvfi_mem_rdata_d = regfile_wdata_lsu;
- rvfi_mem_wdata_d = data_wdata_ex;
+ rvfi_mem_wdata_d = lsu_wdata;
end else begin
rvfi_mem_addr_d = rvfi_mem_addr_q;
- rvfi_mem_rdata_d = rvfi_mem_rdata_q;
rvfi_mem_wdata_d = rvfi_mem_wdata_q;
end
end
+
+ // Capture read data from LSU when it becomes valid
+ always_comb begin
+ if (lsu_data_valid) begin
+ rvfi_mem_rdata_d = rf_wdata_lsu;
+ end else begin
+ rvfi_mem_rdata_d = rvfi_mem_rdata_q;
+ end
+ end
+
always_ff @(posedge clk or negedge rst_ni) begin
if (!rst_ni) begin
rvfi_mem_addr_q <= '0;
@@ -786,7 +1109,7 @@
end
// Byte enable based on data type
always_comb begin
- unique case (data_type_ex)
+ unique case (lsu_type)
2'b00: rvfi_mem_mask_int = 4'b1111;
2'b01: rvfi_mem_mask_int = 4'b0011;
2'b10: rvfi_mem_mask_int = 4'b0001;
@@ -804,7 +1127,7 @@
// Source register data are kept stable for each instruction cycle
always_comb begin
- if (instr_new_id) begin
+ if (instr_first_cycle_id) begin
rvfi_rs1_data_d = rvfi_rs1_data_id;
rvfi_rs2_data_d = rvfi_rs2_data_id;
end else begin
@@ -822,26 +1145,30 @@
end
end
- // RD write register is refreshed only once per cycle and
- // then it is kept stable for the cycle.
always_comb begin
- if (rvfi_insn_new_d) begin
- if (!rvfi_rd_we_id) begin
- rvfi_rd_addr_d = '0;
- rvfi_rd_wdata_d = '0;
+ if(rvfi_rd_we_wb) begin
+ // Capture address/data of write to register file
+ rvfi_rd_addr_d = rvfi_rd_addr_wb;
+ // If writing to x0 zero write data as required by RVFI specification
+ if(rvfi_rd_addr_wb == 5'b0) begin
+ rvfi_rd_wdata_d = '0;
end else begin
- rvfi_rd_addr_d = rvfi_rd_addr_id;
- if (rvfi_rd_addr_id == 5'h0) begin
- rvfi_rd_wdata_d = '0;
- end else begin
- rvfi_rd_wdata_d = rvfi_rd_wdata_id;
- end
+ rvfi_rd_wdata_d = rvfi_rd_wdata_wb;
end
+ end else if(rvfi_instr_new_wb) begin
+ // If no RF write but new instruction in Writeback (when present) or ID/EX (when no writeback
+ // stage present) then zero RF write address/data as required by RVFI specification
+ rvfi_rd_addr_d = '0;
+ rvfi_rd_wdata_d = '0;
end else begin
- rvfi_rd_addr_d = rvfi_rd_addr_q;
- rvfi_rd_wdata_d = rvfi_rd_wdata_q;
+ // Otherwise maintain previous value
+ rvfi_rd_addr_d = rvfi_rd_addr_q;
+ rvfi_rd_wdata_d = rvfi_rd_wdata_q;
end
end
+
+ // RD write register is refreshed only once per cycle and
+ // then it is kept stable for the cycle.
always_ff @(posedge clk or negedge rst_ni) begin
if (!rst_ni) begin
rvfi_rd_addr_q <= '0;
@@ -852,27 +1179,10 @@
end
end
- always_comb begin
- if (instr_new_id) begin
- rvfi_insn_new_d = 1'b1;
- end else begin
- rvfi_insn_new_d = rvfi_insn_new_q;
- end
- end
- always_ff @(posedge clk or negedge rst_ni) begin
- if (!rst_ni) begin
- rvfi_insn_new_q <= 1'b0;
- end else begin
- if (instr_ret) begin
- rvfi_insn_new_q <= 1'b0;
- end else begin
- rvfi_insn_new_q <= rvfi_insn_new_d;
- end
- end
- end
-
- // generate rvfi_intr_d
- assign rvfi_intr_d = rvfi_set_trap_pc_q & rvfi_insn_new_d;
+ // rvfi_intr must be set for first instruction that is part of a trap handler.
+ // On the first cycle of a new instruction see if a trap PC was set by the previous instruction,
+ // otherwise maintain value.
+ assign rvfi_intr_d = instr_first_cycle_id ? rvfi_set_trap_pc_q : rvfi_intr_q;
always_comb begin
rvfi_set_trap_pc_d = rvfi_set_trap_pc_q;
@@ -881,7 +1191,7 @@
(exc_pc_mux_id == EXC_PC_EXC || exc_pc_mux_id == EXC_PC_IRQ)) begin
// PC is set to enter a trap handler
rvfi_set_trap_pc_d = 1'b1;
- end else if (rvfi_set_trap_pc_q && instr_ret) begin
+ end else if (rvfi_set_trap_pc_q && instr_id_done) begin
// first instruction has been executed after PC is set to trap handler
rvfi_set_trap_pc_d = 1'b0;
end
@@ -890,8 +1200,10 @@
always_ff @(posedge clk or negedge rst_ni) begin
if (!rst_ni) begin
rvfi_set_trap_pc_q <= 1'b0;
+ rvfi_intr_q <= 1'b0;
end else begin
rvfi_set_trap_pc_q <= rvfi_set_trap_pc_d;
+ rvfi_intr_q <= rvfi_intr_d;
end
end
diff --git a/hw/vendor/lowrisc_ibex/rtl/ibex_core_tracing.sv b/hw/vendor/lowrisc_ibex/rtl/ibex_core_tracing.sv
index b4ba19d..cbe63fc 100644
--- a/hw/vendor/lowrisc_ibex/rtl/ibex_core_tracing.sv
+++ b/hw/vendor/lowrisc_ibex/rtl/ibex_core_tracing.sv
@@ -10,12 +10,16 @@
parameter bit PMPEnable = 1'b0,
parameter int unsigned PMPGranularity = 0,
parameter int unsigned PMPNumRegions = 4,
- parameter int unsigned MHPMCounterNum = 8,
+ parameter int unsigned MHPMCounterNum = 0,
parameter int unsigned MHPMCounterWidth = 40,
parameter bit RV32E = 1'b0,
parameter bit RV32M = 1'b1,
+ parameter bit RV32B = 1'b0,
parameter bit BranchTargetALU = 1'b0,
+ parameter bit WritebackStage = 1'b0,
parameter MultiplierImplementation = "fast",
+ parameter bit ICache = 1'b0,
+ parameter bit ICacheECC = 1'b0,
parameter bit DbgTriggerEn = 1'b0,
parameter int unsigned DmHaltAddr = 32'h1A110800,
parameter int unsigned DmExceptionAddr = 32'h1A110808
@@ -100,9 +104,13 @@
.MHPMCounterWidth ( MHPMCounterWidth ),
.RV32E ( RV32E ),
.RV32M ( RV32M ),
+ .RV32B ( RV32B ),
.BranchTargetALU ( BranchTargetALU ),
- .DbgTriggerEn ( DbgTriggerEn ),
.MultiplierImplementation ( MultiplierImplementation ),
+ .ICache ( ICache ),
+ .ICacheECC ( ICacheECC ),
+ .DbgTriggerEn ( DbgTriggerEn ),
+ .WritebackStage ( WritebackStage ),
.DmHaltAddr ( DmHaltAddr ),
.DmExceptionAddr ( DmExceptionAddr )
) u_ibex_core (
diff --git a/hw/vendor/lowrisc_ibex/rtl/ibex_counters.sv b/hw/vendor/lowrisc_ibex/rtl/ibex_counters.sv
index 9a28b9a..2d9a4ef 100644
--- a/hw/vendor/lowrisc_ibex/rtl/ibex_counters.sv
+++ b/hw/vendor/lowrisc_ibex/rtl/ibex_counters.sv
@@ -54,17 +54,17 @@
// Set DSP pragma for supported xilinx FPGAs
localparam dsp_pragma = CounterWidth < 49 ? "yes" : "no";
(* use_dsp = dsp_pragma *) logic [CounterWidth-1:0] counter_q;
+
+ // DSP output register requires synchronous reset.
+ `define COUNTER_FLOP_RST posedge clk_i
`else
logic [CounterWidth-1:0] counter_q;
+
+ `define COUNTER_FLOP_RST posedge clk_i or negedge rst_ni
`endif
// Counter flop
-`ifdef FPGA_XILINX
- // DSP output register requires synchronous reset.
- always @(posedge clk_i) begin
-`else
- always @(posedge clk_i or negedge rst_ni) begin
-`endif
+ always @(`COUNTER_FLOP_RST) begin
if (!rst_ni) begin
counter_q <= '0;
end else begin
@@ -84,3 +84,6 @@
end
endmodule
+
+// Keep helper defines file-local.
+`undef COUNTER_FLOP_RST
diff --git a/hw/vendor/lowrisc_ibex/rtl/ibex_cs_registers.sv b/hw/vendor/lowrisc_ibex/rtl/ibex_cs_registers.sv
index e9fce05..a6a84ac 100644
--- a/hw/vendor/lowrisc_ibex/rtl/ibex_cs_registers.sv
+++ b/hw/vendor/lowrisc_ibex/rtl/ibex_cs_registers.sv
@@ -14,7 +14,8 @@
module ibex_cs_registers #(
parameter bit DbgTriggerEn = 0,
- parameter int unsigned MHPMCounterNum = 8,
+ parameter bit ICache = 1'b0,
+ parameter int unsigned MHPMCounterNum = 10,
parameter int unsigned MHPMCounterWidth = 40,
parameter bit PMPEnable = 0,
parameter int unsigned PMPGranularity = 0,
@@ -45,6 +46,7 @@
input ibex_pkg::csr_num_e csr_addr_i,
input logic [31:0] csr_wdata_i,
input ibex_pkg::csr_op_e csr_op_i,
+ input csr_op_en_i,
output logic [31:0] csr_rdata_o,
// interrupts
@@ -74,9 +76,15 @@
input logic [31:0] pc_if_i,
input logic [31:0] pc_id_i,
+ input logic [31:0] pc_wb_i,
+ // CPU control bits
+ output logic icache_enable_o,
+
+ // Exception save/restore
input logic csr_save_if_i,
input logic csr_save_id_i,
+ input logic csr_save_wb_i,
input logic csr_restore_mret_i,
input logic csr_restore_dret_i,
input logic csr_save_cause_i,
@@ -85,19 +93,18 @@
output logic illegal_csr_insn_o, // access to non-existent CSR,
// with wrong priviledge level, or
// missing write permissions
- input logic instr_new_id_i, // ID stage sees a new instr
-
// Performance Counters
input logic instr_ret_i, // instr retired in ID/EX stage
input logic instr_ret_compressed_i, // compressed instr retired
- input logic imiss_i, // instr fetch
- input logic pc_set_i, // PC was set to a new value
+ input logic iside_wait_i, // core waiting for the iside
input logic jump_i, // jump instr seen (j, jr, jal, jalr)
input logic branch_i, // branch instr seen (bf, bnf)
input logic branch_taken_i, // branch was taken
input logic mem_load_i, // load from memory in this cycle
input logic mem_store_i, // store to memory in this cycle
- input logic lsu_busy_i
+ input logic dside_wait_i, // core waiting for the dside
+ input logic mul_wait_i, // core waiting for multiply
+ input logic div_wait_i // core waiting for divide
);
import ibex_pkg::*;
@@ -149,6 +156,12 @@
priv_lvl_e prv;
} Dcsr_t;
+ // CPU control register fields
+ typedef struct packed {
+ logic [30:0] unused_ctrl;
+ logic icache_enable;
+ } CpuCtrl_t;
+
// Interrupt and exception control signals
logic [31:0] exception_pc;
@@ -198,6 +211,9 @@
logic [31:0] tmatch_control_rdata;
logic [31:0] tmatch_value_rdata;
+ // CPU control bits
+ CpuCtrl_t cpuctrl_rdata, cpuctrl_wdata;
+
// CSR update logic
logic [31:0] csr_wdata_int;
logic [31:0] csr_rdata_int;
@@ -396,6 +412,11 @@
illegal_csr = ~DbgTriggerEn;
end
+ // Custom CSR for controlling CPU features
+ CSR_CPUCTRL: begin
+ csr_rdata_int = {cpuctrl_rdata};
+ end
+
default: begin
illegal_csr = 1'b1;
end
@@ -538,6 +559,9 @@
csr_save_id_i: begin
exception_pc = pc_id_i;
end
+ csr_save_wb_i: begin
+ exception_pc = pc_wb_i;
+ end
default:;
endcase
@@ -596,25 +620,22 @@
// CSR operation logic
always_comb begin
- csr_wreq = 1'b1;
-
unique case (csr_op_i)
CSR_OP_WRITE: csr_wdata_int = csr_wdata_i;
CSR_OP_SET: csr_wdata_int = csr_wdata_i | csr_rdata_o;
CSR_OP_CLEAR: csr_wdata_int = ~csr_wdata_i & csr_rdata_o;
- CSR_OP_READ: begin
- csr_wdata_int = csr_wdata_i;
- csr_wreq = 1'b0;
- end
- default: begin
- csr_wdata_int = csr_wdata_i;
- csr_wreq = 1'b0;
- end
+ CSR_OP_READ: csr_wdata_int = csr_wdata_i;
+ default: csr_wdata_int = csr_wdata_i;
endcase
end
+ assign csr_wreq = csr_op_en_i &
+ (csr_op_i inside {CSR_OP_WRITE,
+ CSR_OP_SET,
+ CSR_OP_CLEAR});
+
// only write CSRs during one clock cycle
- assign csr_we_int = csr_wreq & ~illegal_csr_insn_o & instr_new_id_i;
+ assign csr_we_int = csr_wreq & ~illegal_csr_insn_o;
assign csr_rdata_o = csr_rdata_int;
@@ -844,15 +865,16 @@
mhpmcounter_incr[0] = 1'b1; // mcycle
mhpmcounter_incr[1] = 1'b0; // reserved
mhpmcounter_incr[2] = instr_ret_i; // minstret
- mhpmcounter_incr[3] = lsu_busy_i; // cycles waiting for data memory
- mhpmcounter_incr[4] = imiss_i & ~pc_set_i; // cycles waiting for instr fetches
- // excl. jump and branch set cycles
+ mhpmcounter_incr[3] = dside_wait_i; // cycles waiting for data memory
+ mhpmcounter_incr[4] = iside_wait_i; // cycles waiting for instr fetches
mhpmcounter_incr[5] = mem_load_i; // num of loads
mhpmcounter_incr[6] = mem_store_i; // num of stores
mhpmcounter_incr[7] = jump_i; // num of jumps (unconditional)
mhpmcounter_incr[8] = branch_i; // num of branches (conditional)
mhpmcounter_incr[9] = branch_taken_i; // num of taken branches (conditional)
mhpmcounter_incr[10] = instr_ret_compressed_i; // num of compressed instr
+ mhpmcounter_incr[11] = mul_wait_i; // cycles waiting for multiply
+ mhpmcounter_incr[12] = div_wait_i; // cycles waiting for divide
// inactive counters
for (int unsigned i=3+MHPMCounterNum; i<32; i++) begin : gen_mhpmcounter_incr_inactive
@@ -1010,17 +1032,48 @@
assign trigger_match_o = 'b0;
end
+ // CPU control fields
+ assign cpuctrl_rdata.unused_ctrl = '0;
+ // Cast register write data
+ assign cpuctrl_wdata = CpuCtrl_t'(csr_wdata_int);
+
+ // Generate icache enable bit
+ if (ICache) begin : gen_icache_enable
+ logic icache_enable_d, icache_enable_q;
+
+ // Update the value when cpuctrl register is written
+ assign icache_enable_d = (csr_we_int & (csr_addr == CSR_CPUCTRL)) ?
+ cpuctrl_wdata.icache_enable : icache_enable_q;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ icache_enable_q <= 1'b0; // disabled on reset
+ end else begin
+ icache_enable_q <= icache_enable_d;
+ end
+ end
+
+ assign cpuctrl_rdata.icache_enable = icache_enable_q;
+
+ end else begin : gen_no_icache
+ // tieoff for the unused icen bit
+ logic unused_icen;
+ assign unused_icen = cpuctrl_wdata.icache_enable;
+
+ // icen field will always read as zero if ICache not configured
+ assign cpuctrl_rdata.icache_enable = 1'b0;
+ end
+
+ // tieoff for the currently unused bits of cpuctrl
+ logic [31:1] unused_cpuctrl;
+ assign unused_cpuctrl = {cpuctrl_wdata[31:1]};
+
+ assign icache_enable_o = cpuctrl_rdata.icache_enable;
+
////////////////
// Assertions //
////////////////
- // Selectors must be known/valid.
- `ASSERT(IbexCsrOpValid, csr_op_i inside {
- CSR_OP_READ,
- CSR_OP_WRITE,
- CSR_OP_SET,
- CSR_OP_CLEAR
- })
- `ASSERT_KNOWN(IbexCsrWdataIntKnown, csr_wdata_int)
+ `ASSERT(IbexCsrOpEnRequiresAccess, csr_op_en_i |-> csr_access_i)
endmodule
diff --git a/hw/vendor/lowrisc_ibex/rtl/ibex_decoder.sv b/hw/vendor/lowrisc_ibex/rtl/ibex_decoder.sv
index 40a5b7b..c3c0d9c 100644
--- a/hw/vendor/lowrisc_ibex/rtl/ibex_decoder.sv
+++ b/hw/vendor/lowrisc_ibex/rtl/ibex_decoder.sv
@@ -20,6 +20,7 @@
module ibex_decoder #(
parameter bit RV32E = 0,
parameter bit RV32M = 1,
+ parameter bit RV32B = 0,
parameter bit BranchTargetALU = 0
) (
input logic clk_i,
@@ -34,9 +35,10 @@
output logic ecall_insn_o, // syscall instr encountered
output logic wfi_insn_o, // wait for interrupt instr encountered
output logic jump_set_o, // jump taken set signal
+ output logic icache_inval_o,
// from IF-ID pipeline register
- input logic instr_new_i, // instruction read is new
+ input logic instr_first_cycle_i, // instruction read is in its first cycle
input logic [31:0] instr_rdata_i, // instruction read from memory/cache
input logic [31:0] instr_rdata_alu_i, // instruction read from memory/cache
// replicated to ease fan-out)
@@ -46,7 +48,8 @@
// immediates
output ibex_pkg::imm_a_sel_e imm_a_mux_sel_o, // immediate selection for operand a
output ibex_pkg::imm_b_sel_e imm_b_mux_sel_o, // immediate selection for operand b
- output ibex_pkg::jt_mux_sel_e jt_mux_sel_o, // jump target selection
+ output ibex_pkg::op_a_sel_e bt_a_mux_sel_o, // branch target selection operand a
+ output ibex_pkg::imm_b_sel_e bt_b_mux_sel_o, // branch target selection operand b
output logic [31:0] imm_i_type_o,
output logic [31:0] imm_s_type_o,
output logic [31:0] imm_b_type_o,
@@ -55,11 +58,13 @@
output logic [31:0] zimm_rs1_type_o,
// register file
- output ibex_pkg::rf_wd_sel_e regfile_wdata_sel_o, // RF write data selection
- output logic regfile_we_o, // write enable for regfile
- output logic [4:0] regfile_raddr_a_o,
- output logic [4:0] regfile_raddr_b_o,
- output logic [4:0] regfile_waddr_o,
+ output ibex_pkg::rf_wd_sel_e rf_wdata_sel_o, // RF write data selection
+ output logic rf_we_o, // write enable for regfile
+ output logic [4:0] rf_raddr_a_o,
+ output logic [4:0] rf_raddr_b_o,
+ output logic [4:0] rf_waddr_o,
+ output logic rf_ren_a_o, // Instruction reads from RF addr A
+ output logic rf_ren_b_o, // Instruction reads from RF addr B
// ALU
output ibex_pkg::alu_op_e alu_operator_o, // ALU operation selection
@@ -80,7 +85,6 @@
// CSRs
output logic csr_access_o, // access to CSR
output ibex_pkg::csr_op_e csr_op_o, // operation to perform on CSR
- output logic csr_pipe_flush_o, // CSR-related pipeline flush
// LSU
output logic data_req_o, // start transaction to data memory
@@ -100,7 +104,7 @@
logic illegal_insn;
logic illegal_reg_rv32e;
logic csr_illegal;
- logic regfile_we;
+ logic rf_we;
logic [31:0] instr;
logic [31:0] instr_alu;
@@ -131,19 +135,19 @@
assign zimm_rs1_type_o = { 27'b0, instr[`REG_S1] }; // rs1
// source registers
- assign regfile_raddr_a_o = instr[`REG_S1]; // rs1
- assign regfile_raddr_b_o = instr[`REG_S2]; // rs2
+ assign rf_raddr_a_o = instr[`REG_S1]; // rs1
+ assign rf_raddr_b_o = instr[`REG_S2]; // rs2
// destination register
- assign regfile_waddr_o = instr[`REG_D]; // rd
+ assign rf_waddr_o = instr[`REG_D]; // rd
////////////////////
// Register check //
////////////////////
if (RV32E) begin : gen_rv32e_reg_check_active
- assign illegal_reg_rv32e = ((regfile_raddr_a_o[4] & (alu_op_a_mux_sel_o == OP_A_REG_A)) |
- (regfile_raddr_b_o[4] & (alu_op_b_mux_sel_o == OP_B_REG_B)) |
- (regfile_waddr_o[4] & regfile_we));
+ assign illegal_reg_rv32e = ((rf_raddr_a_o[4] & (alu_op_a_mux_sel_o == OP_A_REG_A)) |
+ (rf_raddr_b_o[4] & (alu_op_b_mux_sel_o == OP_B_REG_B)) |
+ (rf_waddr_o[4] & rf_we));
end else begin : gen_rv32e_reg_check_inactive
assign illegal_reg_rv32e = 1'b0;
end
@@ -162,32 +166,6 @@
end
end
- /////////////////////////////////
- // CSR-related pipline flushes //
- /////////////////////////////////
- always_comb begin : csr_pipeline_flushes
- csr_pipe_flush_o = 1'b0;
-
- // A pipeline flush is needed to let the controller react after modifying certain CSRs:
- // - When enabling interrupts, pending IRQs become visible to the controller only during
- // the next cycle. If during that cycle the core disables interrupts again, it does not
- // see any pending IRQs and consequently does not start to handle interrupts.
- // - When modifying debug CSRs - TODO: Check if this is really needed
- if (csr_access_o == 1'b1 && (csr_op_o == CSR_OP_WRITE || csr_op_o == CSR_OP_SET)) begin
- if (csr_num_e'(instr[31:20]) == CSR_MSTATUS ||
- csr_num_e'(instr[31:20]) == CSR_MIE) begin
- csr_pipe_flush_o = 1'b1;
- end
- end else if (csr_access_o == 1'b1 && csr_op_o != CSR_OP_READ) begin
- if (csr_num_e'(instr[31:20]) == CSR_DCSR ||
- csr_num_e'(instr[31:20]) == CSR_DPC ||
- csr_num_e'(instr[31:20]) == CSR_DSCRATCH0 ||
- csr_num_e'(instr[31:20]) == CSR_DSCRATCH1) begin
- csr_pipe_flush_o = 1'b1;
- end
- end
- end
-
/////////////
// Decoder //
/////////////
@@ -196,14 +174,17 @@
jump_in_dec_o = 1'b0;
jump_set_o = 1'b0;
branch_in_dec_o = 1'b0;
+ icache_inval_o = 1'b0;
mult_en_o = 1'b0;
div_en_o = 1'b0;
multdiv_operator_o = MD_OP_MULL;
multdiv_signed_mode_o = 2'b00;
- regfile_wdata_sel_o = RF_WD_EX;
- regfile_we = 1'b0;
+ rf_wdata_sel_o = RF_WD_EX;
+ rf_we = 1'b0;
+ rf_ren_a_o = 1'b0;
+ rf_ren_b_o = 1'b0;
csr_access_o = 1'b0;
csr_illegal = 1'b0;
@@ -230,32 +211,34 @@
///////////
OPCODE_JAL: begin // Jump and Link
- jump_in_dec_o = 1'b1;
+ jump_in_dec_o = 1'b1;
- if (instr_new_i) begin
- // Calculate jump target
- regfile_we = 1'b0;
- jump_set_o = 1'b1;
+ if (instr_first_cycle_i) begin
+ // Calculate jump target (and store PC + 4 if BranchTargetALU is configured)
+ rf_we = BranchTargetALU;
+ jump_set_o = 1'b1;
end else begin
// Calculate and store PC+4
- regfile_we = 1'b1;
+ rf_we = 1'b1;
end
end
OPCODE_JALR: begin // Jump and Link Register
- jump_in_dec_o = 1'b1;
+ jump_in_dec_o = 1'b1;
- if (instr_new_i) begin
- // Calculate jump target
- regfile_we = 1'b0;
- jump_set_o = 1'b1;
+ if (instr_first_cycle_i) begin
+ // Calculate jump target (and store PC + 4 if BranchTargetALU is configured)
+ rf_we = BranchTargetALU;
+ jump_set_o = 1'b1;
end else begin
// Calculate and store PC+4
- regfile_we = 1'b1;
+ rf_we = 1'b1;
end
if (instr[14:12] != 3'b0) begin
illegal_insn = 1'b1;
end
+
+ rf_ren_a_o = 1'b1;
end
OPCODE_BRANCH: begin // Branch
@@ -270,6 +253,9 @@
3'b111: illegal_insn = 1'b0;
default: illegal_insn = 1'b1;
endcase
+
+ rf_ren_a_o = 1'b1;
+ rf_ren_b_o = 1'b1;
end
////////////////
@@ -277,6 +263,8 @@
////////////////
OPCODE_STORE: begin
+ rf_ren_a_o = 1'b1;
+ rf_ren_b_o = 1'b1;
data_req_o = 1'b1;
data_we_o = 1'b1;
@@ -286,17 +274,16 @@
// store size
unique case (instr[13:12])
- 2'b00: data_type_o = 2'b10; // SB
- 2'b01: data_type_o = 2'b01; // SH
- 2'b10: data_type_o = 2'b00; // SW
+ 2'b00: data_type_o = 2'b10; // sb
+ 2'b01: data_type_o = 2'b01; // sh
+ 2'b10: data_type_o = 2'b00; // sw
default: illegal_insn = 1'b1;
endcase
end
OPCODE_LOAD: begin
+ rf_ren_a_o = 1'b1;
data_req_o = 1'b1;
- regfile_wdata_sel_o = RF_WD_LSU;
- regfile_we = 1'b1;
data_type_o = 2'b00;
// sign/zero extension
@@ -304,12 +291,12 @@
// load size
unique case (instr[13:12])
- 2'b00: data_type_o = 2'b10; // LB(U)
- 2'b01: data_type_o = 2'b01; // LH(U)
+ 2'b00: data_type_o = 2'b10; // lb(u)
+ 2'b01: data_type_o = 2'b01; // lh(u)
2'b10: begin
- data_type_o = 2'b00; // LW
+ data_type_o = 2'b00; // lw
if (instr[14]) begin
- illegal_insn = 1'b1; // LWU does not exist
+ illegal_insn = 1'b1; // lwu does not exist
end
end
default: begin
@@ -323,15 +310,16 @@
/////////
OPCODE_LUI: begin // Load Upper Immediate
- regfile_we = 1'b1;
+ rf_we = 1'b1;
end
OPCODE_AUIPC: begin // Add Upper Immediate to PC
- regfile_we = 1'b1;
+ rf_we = 1'b1;
end
OPCODE_OP_IMM: begin // Register-Immediate ALU Operations
- regfile_we = 1'b1;
+ rf_ren_a_o = 1'b1;
+ rf_we = 1'b1;
unique case (instr[14:12])
3'b000,
@@ -342,29 +330,50 @@
3'b111: illegal_insn = 1'b0;
3'b001: begin
- if (instr[31:25] != 7'b0) begin
- illegal_insn = 1'b1;
- end
+ unique case (instr[31:25])
+ 7'b000_0000: illegal_insn = 1'b0; // slli
+ 7'b001_0000: illegal_insn = RV32B ? 1'b0 : 1'b1; // sloi
+ 7'b011_0000: begin
+ unique case(instr[24:20])
+ 5'b00000, // clz
+ 5'b00001, // ctz
+ 5'b00010: illegal_insn = RV32B ? 1'b0 : 1'b1; // pcnt
+ default: illegal_insn = 1'b1;
+ endcase
+ end
+ default : illegal_insn = 1'b1;
+ endcase
end
3'b101: begin
- if (instr[31:25] == 7'b0) begin
- illegal_insn = 1'b0;
- end else if (instr[31:25] == 7'b010_0000) begin
- illegal_insn = 1'b0;
- end else begin
- illegal_insn = 1'b1;
- end
+ unique case (instr[31:25])
+ 7'b000_0000, // srli
+ 7'b010_0000: illegal_insn = 1'b0; // srai
+
+ 7'b001_0000, // sroi
+ 7'b011_0000: illegal_insn = RV32B ? 1'b0 : 1'b1; // rori
+
+ 7'b011_0100: begin
+ unique case(instr[24:20])
+ 5'b11111, // rev
+ 5'b11000, // rev8
+ 5'b00111: illegal_insn = RV32B ? 1'b0 : 1'b1; // orc.b
+
+ default: illegal_insn = 1'b1;
+ endcase
+ end
+ default: illegal_insn = 1'b1;
+ endcase
end
- default: begin
- illegal_insn = 1'b1;
- end
+ default: illegal_insn = 1'b1;
endcase
end
OPCODE_OP: begin // Register-Register ALU operation
- regfile_we = 1'b1;
+ rf_ren_a_o = 1'b1;
+ rf_ren_b_o = 1'b1;
+ rf_we = 1'b1;
if (instr[31]) begin
illegal_insn = 1'b1;
@@ -382,6 +391,22 @@
{6'b00_0000, 3'b101},
{6'b10_0000, 3'b101}: illegal_insn = 1'b0;
+ // supported RV32B instructions (zbb)
+ {6'b10_0000, 3'b111}, // andn
+ {6'b10_0000, 3'b110}, // orn
+ {6'b10_0000, 3'b100}, // xnor
+ {6'b01_0000, 3'b001}, // slo
+ {6'b01_0000, 3'b101}, // sro
+ {6'b11_0000, 3'b001}, // rol
+ {6'b11_0000, 3'b101}, // ror
+ {6'b00_0101, 3'b100}, // min
+ {6'b00_0101, 3'b101}, // max
+ {6'b00_0101, 3'b110}, // minu
+ {6'b00_0101, 3'b111}, // maxu
+ {6'b00_0100, 3'b100}, // pack
+ {6'b10_0100, 3'b100}, // packu
+ {6'b00_0100, 3'b111}: illegal_insn = RV32B ? 1'b0 : 1'b1; // packh
+
// supported RV32M instructions
{6'b00_0001, 3'b000}: begin // mul
multdiv_operator_o = MD_OP_MULL;
@@ -445,21 +470,23 @@
OPCODE_MISC_MEM: begin
// For now, treat the FENCE (funct3 == 000) instruction as a NOP. This may not be correct
// in a system with caches and should be revisited.
- // FENCE.I will flush the IF stage and prefetch buffer but nothing else.
+ // FENCE.I will flush the IF stage and prefetch buffer (or ICache) but nothing else.
unique case (instr[14:12])
3'b000: begin
- regfile_we = 1'b0;
+ rf_we = 1'b0;
end
3'b001: begin
// FENCE.I is implemented as a jump to the next PC, this gives the required flushing
// behaviour (iside prefetch buffer flushed and response to any outstanding iside
// requests will be ignored).
- jump_in_dec_o = 1'b1;
+ // If present, the ICache will also be flushed.
+ jump_in_dec_o = 1'b1;
- regfile_we = 1'b0;
+ rf_we = 1'b0;
- if (instr_new_i) begin
+ if (instr_first_cycle_i) begin
jump_set_o = 1'b1;
+ icache_inval_o = 1'b1;
end
end
default: begin
@@ -499,9 +526,13 @@
end
end else begin
// instruction to read/modify CSR
- csr_access_o = 1'b1;
- regfile_wdata_sel_o = RF_WD_CSR;
- regfile_we = 1'b1;
+ csr_access_o = 1'b1;
+ rf_wdata_sel_o = RF_WD_CSR;
+ rf_we = 1'b1;
+
+ if (~instr[14]) begin
+ rf_ren_a_o = 1'b1;
+ end
unique case (instr[13:12])
2'b01: csr_op = CSR_OP_WRITE;
@@ -530,7 +561,7 @@
// insufficient privileges), or when accessing non-available registers in RV32E,
// these cases are not handled here
if (illegal_insn) begin
- regfile_we = 1'b0;
+ rf_we = 1'b0;
data_req_o = 1'b0;
data_we_o = 1'b0;
mult_en_o = 1'b0;
@@ -554,7 +585,8 @@
imm_a_mux_sel_o = IMM_A_ZERO;
imm_b_mux_sel_o = IMM_B_I;
- jt_mux_sel_o = JT_ALU;
+ bt_a_mux_sel_o = OP_A_CURRPC;
+ bt_b_mux_sel_o = IMM_B_I;
multdiv_sel_o = 1'b0;
@@ -568,10 +600,12 @@
OPCODE_JAL: begin // Jump and Link
if (BranchTargetALU) begin
- jt_mux_sel_o = JT_ALU;
+ bt_a_mux_sel_o = OP_A_CURRPC;
+ bt_b_mux_sel_o = IMM_B_J;
end
- if (instr_new_i) begin
+ // Jumps take two cycles without the BTALU
+ if (instr_first_cycle_i && !BranchTargetALU) begin
// Calculate jump target
alu_op_a_mux_sel_o = OP_A_CURRPC;
alu_op_b_mux_sel_o = OP_B_IMM;
@@ -588,10 +622,12 @@
OPCODE_JALR: begin // Jump and Link Register
if (BranchTargetALU) begin
- jt_mux_sel_o = JT_ALU;
+ bt_a_mux_sel_o = OP_A_REG_A;
+ bt_b_mux_sel_o = IMM_B_I;
end
- if (instr_new_i) begin
+ // Jumps take two cycles without the BTALU
+ if (instr_first_cycle_i && !BranchTargetALU) begin
// Calculate jump target
alu_op_a_mux_sel_o = OP_A_REG_A;
alu_op_b_mux_sel_o = OP_B_IMM;
@@ -623,11 +659,12 @@
// target ALU calculates the target (which is controlled in a seperate block below)
alu_op_a_mux_sel_o = OP_A_REG_A;
alu_op_b_mux_sel_o = OP_B_REG_B;
- jt_mux_sel_o = JT_BT_ALU;
+ bt_a_mux_sel_o = OP_A_CURRPC;
+ bt_b_mux_sel_o = IMM_B_B;
end else begin
// Without branch target ALU, a branch is a two-stage operation using the Main ALU in both
// stages
- if (instr_new_i) begin
+ if (instr_first_cycle_i) begin
// First evaluate the branch condition
alu_op_a_mux_sel_o = OP_A_REG_A;
alu_op_b_mux_sel_o = OP_B_REG_B;
@@ -699,14 +736,60 @@
3'b111: alu_operator_o = ALU_AND; // And with Immediate
3'b001: begin
- alu_operator_o = ALU_SLL; // Shift Left Logical by Immediate
+ if (RV32B) begin
+ // We don't factor in instr[31] here to make the ALU decoder more symmetric for
+ // Reg-Reg and Reg-Imm ALU operations. Instr[31] is only needed to detect illegal
+ // encodings for Reg-Reg ALU operations (see non-ALU decoder).
+ unique case (instr[30:25])
+ 6'b00_0000: alu_operator_o = ALU_SLL; // Shift Left Logical by Immediate
+ 6'b01_0000: alu_operator_o = ALU_SLO; // Shift Left Ones by Immediate
+ 6'b11_0000: begin
+ unique case (instr[24:20])
+ 5'b00000: alu_operator_o = ALU_CLZ; // Count Leading Zeros
+ 5'b00001: alu_operator_o = ALU_CTZ; // Count Trailing Zeros
+ 5'b00010: alu_operator_o = ALU_PCNT; // Count Set Bits
+ default: ;
+ endcase
+ end
+
+ default: ;
+ endcase
+ end else begin
+ alu_operator_o = ALU_SLL; // Shift Left Logical by Immediate
+ end
end
3'b101: begin
- if (instr_alu[31:25] == 7'b0) begin
- alu_operator_o = ALU_SRL; // Shift Right Logical by Immediate
- end else if (instr_alu[31:25] == 7'b010_0000) begin
- alu_operator_o = ALU_SRA; // Shift Right Arithmetically by Immediate
+ if (RV32B) begin
+ // We don't factor in instr[31] here to make the ALU decoder more symmetric for
+ // Reg-Reg and Reg-Imm ALU operations. Instr[31] is only needed to detect illegal
+ // encodings for Reg-Reg ALU operations (see non-ALU decoder).
+ unique case (instr_alu[30:25])
+ 6'b00_0000: alu_operator_o = ALU_SRL; // Shift Right Logical by Immediate
+ 6'b10_0000: alu_operator_o = ALU_SRA; // Shift Right Arithmetically by Immediate
+ 6'b01_0000: alu_operator_o = ALU_SRO; // Shift Right Ones by Immediate
+ 6'b11_0000: alu_operator_o = ALU_ROR; // Rotate Right by Immediate
+ 6'b11_0100: begin
+ if (instr_alu[24:20] == 5'b11111) begin
+ alu_operator_o = ALU_REV; // Reverse
+ end else if (instr_alu[24:20] == 5'b11000) begin
+ alu_operator_o = ALU_REV8; // Byte-swap
+ end
+ end
+ 6'b01_0100: begin
+ if (instr_alu[24:20] == 5'b00111) begin
+ alu_operator_o = ALU_ORCB; // Byte-wise Reverse and Or-Combine
+ end
+ end
+ default: ;
+ endcase
+
+ end else begin
+ if (instr_alu[31:25] == 7'b0) begin
+ alu_operator_o = ALU_SRL; // Shift Right Logical by Immediate
+ end else if (instr_alu[31:25] == 7'b010_0000) begin
+ alu_operator_o = ALU_SRA; // Shift Right Arithmetically by Immediate
+ end
end
end
@@ -731,6 +814,25 @@
{6'b00_0000, 3'b101}: alu_operator_o = ALU_SRL; // Shift Right Logical
{6'b10_0000, 3'b101}: alu_operator_o = ALU_SRA; // Shift Right Arithmetic
+ // RV32B ALU Operations
+ {6'b01_0000, 3'b001}: if (RV32B) alu_operator_o = ALU_SLO; // Shift Left Ones
+ {6'b01_0000, 3'b101}: if (RV32B) alu_operator_o = ALU_SRO; // Shift Right Ones
+ {6'b11_0000, 3'b001}: if (RV32B) alu_operator_o = ALU_ROL; // Rotate Left
+ {6'b11_0000, 3'b101}: if (RV32B) alu_operator_o = ALU_ROR; // Rotate Right
+
+ {6'b00_0101, 3'b100}: if (RV32B) alu_operator_o = ALU_MIN; // Minimum
+ {6'b00_0101, 3'b101}: if (RV32B) alu_operator_o = ALU_MAX; // Maximum
+ {6'b00_0101, 3'b110}: if (RV32B) alu_operator_o = ALU_MINU; // Minimum Unsigned
+ {6'b00_0101, 3'b111}: if (RV32B) alu_operator_o = ALU_MAXU; // Maximum Unsigned
+
+ {6'b00_0100, 3'b100}: if (RV32B) alu_operator_o = ALU_PACK; // Pack Lower Halves
+ {6'b10_0100, 3'b100}: if (RV32B) alu_operator_o = ALU_PACKU; // Pack Upper Halves
+ {6'b00_0100, 3'b111}: if (RV32B) alu_operator_o = ALU_PACKH; // Pack LSB Bytes
+
+ {6'b10_0000, 3'b100}: if (RV32B) alu_operator_o = ALU_XNOR; // Xnor
+ {6'b10_0000, 3'b110}: if (RV32B) alu_operator_o = ALU_ORN; // Orn
+ {6'b10_0000, 3'b111}: if (RV32B) alu_operator_o = ALU_ANDN; // Andn
+
// supported RV32M instructions, all use the same ALU operation
{6'b00_0001, 3'b000}, // mul
{6'b00_0001, 3'b001}, // mulh
@@ -763,10 +865,15 @@
alu_op_b_mux_sel_o = OP_B_IMM;
end
3'b001: begin
- alu_op_a_mux_sel_o = OP_A_CURRPC;
- alu_op_b_mux_sel_o = OP_B_IMM;
- imm_b_mux_sel_o = IMM_B_INCR_PC;
- alu_operator_o = ALU_ADD;
+ if (BranchTargetALU) begin
+ bt_a_mux_sel_o = OP_A_CURRPC;
+ bt_b_mux_sel_o = IMM_B_INCR_PC;
+ end else begin
+ alu_op_a_mux_sel_o = OP_A_CURRPC;
+ alu_op_b_mux_sel_o = OP_B_IMM;
+ imm_b_mux_sel_o = IMM_B_INCR_PC;
+ alu_operator_o = ALU_ADD;
+ end
end
default: ;
endcase
@@ -801,7 +908,7 @@
assign illegal_insn_o = illegal_insn | illegal_reg_rv32e;
// do not propgate regfile write enable if non-available registers are accessed in RV32E
- assign regfile_we_o = regfile_we & ~illegal_reg_rv32e;
+ assign rf_we_o = rf_we & ~illegal_reg_rv32e;
////////////////
// Assertions //
diff --git a/hw/vendor/lowrisc_ibex/rtl/ibex_ex_block.sv b/hw/vendor/lowrisc_ibex/rtl/ibex_ex_block.sv
index 6928f54..fc42665 100644
--- a/hw/vendor/lowrisc_ibex/rtl/ibex_ex_block.sv
+++ b/hw/vendor/lowrisc_ibex/rtl/ibex_ex_block.sv
@@ -10,6 +10,7 @@
*/
module ibex_ex_block #(
parameter bit RV32M = 1,
+ parameter bit RV32B = 0,
parameter bit BranchTargetALU = 0,
parameter MultiplierImplementation = "fast"
) (
@@ -23,9 +24,8 @@
// Branch Target ALU
// All of these signals are unusued when BranchTargetALU == 0
- input ibex_pkg::jt_mux_sel_e jt_mux_sel_i,
- input logic [11:0] bt_operand_imm_i,
- input logic [31:0] pc_id_i,
+ input logic [31:0] bt_a_operand_i,
+ input logic [31:0] bt_b_operand_i,
// Multiplier/Divider
input ibex_pkg::md_op_e multdiv_operator_i,
@@ -35,11 +35,12 @@
input logic [1:0] multdiv_signed_mode_i,
input logic [31:0] multdiv_operand_a_i,
input logic [31:0] multdiv_operand_b_i,
+ input logic multdiv_ready_id_i,
// Outputs
output logic [31:0] alu_adder_result_ex_o, // to LSU
- output logic [31:0] regfile_wdata_ex_o,
- output logic [31:0] jump_target_o, // to IF
+ output logic [31:0] result_ex_o,
+ output logic [31:0] branch_target_o, // to IF
output logic branch_decision_o, // to ID
output logic ex_valid_o // EX has valid output
@@ -66,35 +67,36 @@
assign multdiv_en = 1'b0;
end
- assign regfile_wdata_ex_o = multdiv_en ? multdiv_result : alu_result;
+ assign result_ex_o = multdiv_en ? multdiv_result : alu_result;
// branch handling
assign branch_decision_o = alu_cmp_result;
if (BranchTargetALU) begin : g_branch_target_alu
logic [32:0] bt_alu_result;
+ logic unused_bt_carry;
- assign bt_alu_result = {{19{bt_operand_imm_i[11]}}, bt_operand_imm_i, 1'b0} + pc_id_i;
+ assign bt_alu_result = bt_a_operand_i + bt_b_operand_i;
- assign jump_target_o = (jt_mux_sel_i == JT_ALU) ? alu_adder_result_ex_o : bt_alu_result[31:0];
+ assign unused_bt_carry = bt_alu_result[32];
+ assign branch_target_o = bt_alu_result[31:0];
end else begin : g_no_branch_target_alu
- // Unused jt_mux_sel_i/bt_operand_imm_i/pc_id_i signals causes lint errors, this avoids them
- ibex_pkg::jt_mux_sel_e unused_jt_mux_sel;
- logic [11:0] unused_bt_operand_imm;
- logic [31:0] unused_pc_id;
+ // Unused bt_operand signals cause lint errors, this avoids them
+ logic [31:0] unused_bt_a_operand, unused_bt_b_operand;
- assign unused_jt_mux_sel = jt_mux_sel_i;
- assign unused_bt_operand_imm = bt_operand_imm_i;
- assign unused_pc_id = pc_id_i;
+ assign unused_bt_a_operand = bt_a_operand_i;
+ assign unused_bt_b_operand = bt_b_operand_i;
- assign jump_target_o = alu_adder_result_ex_o;
+ assign branch_target_o = alu_adder_result_ex_o;
end
/////////
// ALU //
/////////
- ibex_alu alu_i (
+ ibex_alu #(
+ .RV32B( RV32B )
+ ) alu_i (
.operator_i ( alu_operator_i ),
.operand_a_i ( alu_operand_a_i ),
.operand_b_i ( alu_operand_b_i ),
@@ -128,6 +130,7 @@
.valid_o ( multdiv_valid ),
.alu_operand_a_o ( multdiv_alu_operand_a ),
.alu_operand_b_o ( multdiv_alu_operand_b ),
+ .multdiv_ready_id_i ( multdiv_ready_id_i ),
.multdiv_result_o ( multdiv_result )
);
end else if (MultiplierImplementation == "fast") begin : gen_multdiv_fast
@@ -147,6 +150,7 @@
.alu_adder_ext_i ( alu_adder_result_ext ),
.alu_adder_i ( alu_adder_result_ex_o ),
.equal_to_zero ( alu_is_equal_result ),
+ .multdiv_ready_id_i ( multdiv_ready_id_i ),
.valid_o ( multdiv_valid ),
.multdiv_result_o ( multdiv_result )
);
@@ -167,6 +171,7 @@
.alu_adder_ext_i ( alu_adder_result_ext ),
.alu_adder_i ( alu_adder_result_ex_o ),
.equal_to_zero ( alu_is_equal_result ),
+ .multdiv_ready_id_i ( multdiv_ready_id_i ),
.valid_o ( multdiv_valid ),
.multdiv_result_o ( multdiv_result )
);
diff --git a/hw/vendor/lowrisc_ibex/rtl/ibex_fetch_fifo.sv b/hw/vendor/lowrisc_ibex/rtl/ibex_fetch_fifo.sv
index 2f15c7e..c9b4336 100644
--- a/hw/vendor/lowrisc_ibex/rtl/ibex_fetch_fifo.sv
+++ b/hw/vendor/lowrisc_ibex/rtl/ibex_fetch_fifo.sv
@@ -33,9 +33,12 @@
input logic out_ready_i,
output logic [31:0] out_addr_o,
output logic [31:0] out_rdata_o,
- output logic out_err_o
+ output logic out_err_o,
+ output logic out_err_plus2_o
);
+ // To gain extra performance DEPTH should be increased, this is due to some inefficiencies in the
+ // way the fetch fifo operates see issue #574 for more details
localparam int unsigned DEPTH = NUM_REQS+1;
// index 0 is used for output
@@ -48,7 +51,7 @@
logic pop_fifo;
logic [31:0] rdata, rdata_unaligned;
- logic err, err_unaligned;
+ logic err, err_unaligned, err_plus2;
logic valid, valid_unaligned;
logic aligned_is_compressed, unaligned_is_compressed;
@@ -90,6 +93,11 @@
((valid_q[0] & err_q[0]) |
(in_err_i & (~valid_q[0] | ~unaligned_is_compressed)));
+ // Record when an error is caused by the second half of an unaligned 32bit instruction.
+ // Only needs to be correct when unaligned and if err_unaligned is set
+ assign err_plus2 = valid_q[1] ? (err_q[1] & ~err_q[0]) :
+ (in_err_i & valid_q[0] & ~err_q[0]);
+
// An uncompressed unaligned instruction is only valid if both parts are available
assign valid_unaligned = valid_q[1] ? 1'b1 :
(valid_q[0] & in_valid_i);
@@ -104,8 +112,9 @@
always_comb begin
if (out_addr_o[1]) begin
// unaligned case
- out_rdata_o = rdata_unaligned;
- out_err_o = err_unaligned;
+ out_rdata_o = rdata_unaligned;
+ out_err_o = err_unaligned;
+ out_err_plus2_o = err_plus2;
if (unaligned_is_compressed) begin
out_valid_o = valid;
@@ -114,9 +123,10 @@
end
end else begin
// aligned case
- out_rdata_o = rdata;
- out_err_o = err;
- out_valid_o = valid;
+ out_rdata_o = rdata;
+ out_err_o = err;
+ out_err_plus2_o = 1'b0;
+ out_valid_o = valid;
end
end
diff --git a/hw/vendor/lowrisc_ibex/rtl/ibex_icache.sv b/hw/vendor/lowrisc_ibex/rtl/ibex_icache.sv
new file mode 100644
index 0000000..749dba6
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/rtl/ibex_icache.sv
@@ -0,0 +1,995 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+/**
+ * Instruction cache
+ *
+ * Provides an instruction cache along with cache management, instruction buffering and prefetching
+ */
+
+`include "prim_assert.sv"
+
+module ibex_icache #(
+ // Cache arrangement parameters
+ parameter int unsigned BusWidth = 32,
+ parameter int unsigned CacheSizeBytes = 4*1024,
+ parameter bit ICacheECC = 1'b0,
+ parameter int unsigned LineSize = 64,
+ parameter int unsigned NumWays = 2,
+ // Always make speculative bus requests in parallel with lookups
+ parameter bit SpecRequest = 1'b0,
+ // Only cache branch targets
+ parameter bit BranchCache = 1'b0
+) (
+ // Clock and reset
+ input logic clk_i,
+ input logic rst_ni,
+
+ // Signal that the core would like instructions
+ input logic req_i,
+
+ // Set the cache's address counter
+ input logic branch_i,
+ input logic [31:0] addr_i,
+
+ // IF stage interface: Pass fetched instructions to the core
+ input logic ready_i,
+ output logic valid_o,
+ output logic [31:0] rdata_o,
+ output logic [31:0] addr_o,
+ output logic err_o,
+ output logic err_plus2_o,
+
+ // Instruction memory / interconnect interface: Fetch instruction data from memory
+ output logic instr_req_o,
+ input logic instr_gnt_i,
+ output logic [31:0] instr_addr_o,
+ input logic [BusWidth-1:0] instr_rdata_i,
+ input logic instr_err_i,
+ input logic instr_pmp_err_i,
+ input logic instr_rvalid_i,
+
+ // Cache status
+ input logic icache_enable_i,
+ input logic icache_inval_i,
+ output logic busy_o
+);
+
+ // NOTE RTL IS DRAFT
+
+ // Local constants
+ localparam int unsigned ADDR_W = 32;
+ // Number of fill buffers (must be >= 2)
+ localparam int unsigned NUM_FB = 4;
+ // Request throttling threshold
+ localparam int unsigned FB_THRESHOLD = NUM_FB - 2;
+ // Derived parameters
+ localparam int unsigned LINE_SIZE_ECC = ICacheECC ? (LineSize + 8) : LineSize;
+ localparam int unsigned LINE_SIZE_BYTES = LineSize/8;
+ localparam int unsigned LINE_W = $clog2(LINE_SIZE_BYTES);
+ localparam int unsigned BUS_BYTES = BusWidth/8;
+ localparam int unsigned BUS_W = $clog2(BUS_BYTES);
+ localparam int unsigned LINE_BEATS = LINE_SIZE_BYTES / BUS_BYTES;
+ localparam int unsigned LINE_BEATS_W = $clog2(LINE_BEATS);
+ localparam int unsigned NUM_LINES = CacheSizeBytes / NumWays / LINE_SIZE_BYTES;
+ localparam int unsigned INDEX_W = $clog2(NUM_LINES);
+ localparam int unsigned INDEX_HI = INDEX_W + LINE_W - 1;
+ localparam int unsigned TAG_SIZE = ADDR_W - INDEX_W - LINE_W + 1; // 1 valid bit
+ localparam int unsigned TAG_SIZE_ECC = ICacheECC ? (TAG_SIZE + 6) : TAG_SIZE;
+ localparam int unsigned OUTPUT_BEATS = (BUS_BYTES / 2); // number of halfwords
+
+ // Prefetch signals
+ logic [ADDR_W-1:0] lookup_addr_aligned;
+ logic [ADDR_W-1:0] prefetch_addr_d, prefetch_addr_q;
+ logic prefetch_addr_en;
+ // Cache pipelipe IC0 signals
+ logic lookup_throttle;
+ logic lookup_req_ic0;
+ logic [ADDR_W-1:0] lookup_addr_ic0;
+ logic [INDEX_W-1:0] lookup_index_ic0;
+ logic fill_req_ic0;
+ logic [INDEX_W-1:0] fill_index_ic0;
+ logic [TAG_SIZE-1:0] fill_tag_ic0;
+ logic [LineSize-1:0] fill_wdata_ic0;
+ logic lookup_grant_ic0;
+ logic lookup_actual_ic0;
+ logic fill_grant_ic0;
+ logic tag_req_ic0;
+ logic [INDEX_W-1:0] tag_index_ic0;
+ logic [NumWays-1:0] tag_banks_ic0;
+ logic tag_write_ic0;
+ logic [TAG_SIZE_ECC-1:0] tag_wdata_ic0;
+ logic data_req_ic0;
+ logic [INDEX_W-1:0] data_index_ic0;
+ logic [NumWays-1:0] data_banks_ic0;
+ logic data_write_ic0;
+ logic [LINE_SIZE_ECC-1:0] data_wdata_ic0;
+ // Cache pipelipe IC1 signals
+ logic [TAG_SIZE_ECC-1:0] tag_rdata_ic1 [NumWays];
+ logic [LINE_SIZE_ECC-1:0] data_rdata_ic1 [NumWays];
+ logic [LINE_SIZE_ECC-1:0] hit_data_ic1;
+ logic lookup_valid_ic1;
+ logic [ADDR_W-1:INDEX_HI+1] lookup_addr_ic1;
+ logic [NumWays-1:0] tag_match_ic1;
+ logic tag_hit_ic1;
+ logic [NumWays-1:0] tag_invalid_ic1;
+ logic [NumWays-1:0] lowest_invalid_way_ic1;
+ logic [NumWays-1:0] round_robin_way_ic1, round_robin_way_q;
+ logic [NumWays-1:0] sel_way_ic1;
+ logic ecc_err_ic1;
+ logic ecc_write_req;
+ logic [NumWays-1:0] ecc_write_ways;
+ logic [INDEX_W-1:0] ecc_write_index;
+ // Fill buffer signals
+ logic gnt_or_pmp_err, gnt_not_pmp_err;
+ logic [$clog2(NUM_FB)-1:0] fb_fill_level;
+ logic fill_cache_new;
+ logic fill_new_alloc, fill_spec_done, fill_spec_hold;
+ logic [NUM_FB-1:0][NUM_FB-1:0] fill_older_d, fill_older_q;
+ logic [NUM_FB-1:0] fill_alloc_sel, fill_alloc;
+ logic [NUM_FB-1:0] fill_busy_d, fill_busy_q;
+ logic [NUM_FB-1:0] fill_done;
+ logic [NUM_FB-1:0] fill_in_ic1;
+ logic [NUM_FB-1:0] fill_stale_d, fill_stale_q;
+ logic [NUM_FB-1:0] fill_cache_d, fill_cache_q;
+ logic [NUM_FB-1:0] fill_hit_ic1, fill_hit_d, fill_hit_q;
+ logic [NUM_FB-1:0][LINE_BEATS_W:0] fill_ext_cnt_d, fill_ext_cnt_q;
+ logic [NUM_FB-1:0] fill_ext_hold_d, fill_ext_hold_q;
+ logic [NUM_FB-1:0] fill_ext_done;
+ logic [NUM_FB-1:0][LINE_BEATS_W:0] fill_rvd_cnt_d, fill_rvd_cnt_q;
+ logic [NUM_FB-1:0] fill_rvd_done;
+ logic [NUM_FB-1:0] fill_ram_done_d, fill_ram_done_q;
+ logic [NUM_FB-1:0] fill_out_grant;
+ logic [NUM_FB-1:0][LINE_BEATS_W:0] fill_out_cnt_d, fill_out_cnt_q;
+ logic [NUM_FB-1:0] fill_out_done;
+ logic [NUM_FB-1:0] fill_ext_req, fill_rvd_exp, fill_ram_req, fill_out_req;
+ logic [NUM_FB-1:0] fill_data_sel, fill_data_reg, fill_data_hit, fill_data_rvd;
+ logic [NUM_FB-1:0][LINE_BEATS_W-1:0] fill_ext_off, fill_rvd_off;
+ logic [NUM_FB-1:0][LINE_BEATS_W:0] fill_rvd_beat;
+ logic [NUM_FB-1:0] fill_ext_arb, fill_ram_arb, fill_out_arb;
+ logic [NUM_FB-1:0] fill_rvd_arb;
+ logic [NUM_FB-1:0] fill_entry_en;
+ logic [NUM_FB-1:0] fill_addr_en;
+ logic [NUM_FB-1:0] fill_way_en;
+ logic [NUM_FB-1:0][LINE_BEATS-1:0] fill_data_en;
+ logic [NUM_FB-1:0][LINE_BEATS-1:0] fill_err_d, fill_err_q;
+ logic [ADDR_W-1:0] fill_addr_q [NUM_FB];
+ logic [NumWays-1:0] fill_way_q [NUM_FB];
+ logic [LineSize-1:0] fill_data_d [NUM_FB];
+ logic [LineSize-1:0] fill_data_q [NUM_FB];
+ logic [ADDR_W-1:BUS_W] fill_ext_req_addr;
+ logic [ADDR_W-1:0] fill_ram_req_addr;
+ logic [NumWays-1:0] fill_ram_req_way;
+ logic [LineSize-1:0] fill_ram_req_data;
+ logic [LineSize-1:0] fill_out_data;
+ logic [LINE_BEATS-1:0] fill_out_err;
+ // External req signals
+ logic instr_req;
+ logic [ADDR_W-1:BUS_W] instr_addr;
+ // Data output signals
+ logic skid_complete_instr;
+ logic output_compressed;
+ logic skid_valid_d, skid_valid_q, skid_en;
+ logic [15:0] skid_data_d, skid_data_q;
+ logic skid_err_q;
+ logic output_valid;
+ logic addr_incr_two;
+ logic output_addr_en;
+ logic [ADDR_W-1:1] output_addr_d, output_addr_q;
+ logic [15:0] output_data_lo, output_data_hi;
+ logic data_valid, output_ready;
+ logic [LineSize-1:0] line_data;
+ logic [LINE_BEATS-1:0] line_err;
+ logic [31:0] line_data_muxed;
+ logic line_err_muxed;
+ logic [31:0] output_data;
+ logic output_err;
+ // Invalidations
+ logic start_inval, inval_done;
+ logic reset_inval_q;
+ logic inval_prog_d, inval_prog_q;
+ logic [INDEX_W-1:0] inval_index_d, inval_index_q;
+
+ //////////////////////////
+ // Instruction prefetch //
+ //////////////////////////
+
+ assign lookup_addr_aligned = {lookup_addr_ic0[ADDR_W-1:LINE_W],{LINE_W{1'b0}}};
+
+ // The prefetch address increments by one cache line for each granted request.
+ // This address is also updated if there is a branch that is not granted, since the target
+ // address (addr_i) is only valid for one cycle while branch_i is high.
+
+ // The captured branch target address is not forced to be aligned since the offset in the cache
+ // line must also be recorded for later use by the fill buffers.
+ assign prefetch_addr_d =
+ lookup_grant_ic0 ? (lookup_addr_aligned + {{ADDR_W-LINE_W-1{1'b0}},1'b1,{LINE_W{1'b0}}}) :
+ addr_i;
+
+ assign prefetch_addr_en = branch_i | lookup_grant_ic0;
+
+ always_ff @(posedge clk_i) begin
+ if (prefetch_addr_en) begin
+ prefetch_addr_q <= prefetch_addr_d;
+ end
+ end
+
+ ////////////////////////
+ // Pipeline stage IC0 //
+ ////////////////////////
+
+ // Cache lookup
+ assign lookup_throttle = (fb_fill_level > FB_THRESHOLD[$clog2(NUM_FB)-1:0]);
+
+ assign lookup_req_ic0 = req_i & ~&fill_busy_q & (branch_i | ~lookup_throttle) & ~ecc_write_req;
+ assign lookup_addr_ic0 = branch_i ? addr_i :
+ prefetch_addr_q;
+ assign lookup_index_ic0 = lookup_addr_ic0[INDEX_HI:LINE_W];
+
+ // Cache write
+ assign fill_req_ic0 = (|fill_ram_req);
+ assign fill_index_ic0 = fill_ram_req_addr[INDEX_HI:LINE_W];
+ assign fill_tag_ic0 = {(~inval_prog_q & ~ecc_write_req),fill_ram_req_addr[ADDR_W-1:INDEX_HI+1]};
+ assign fill_wdata_ic0 = fill_ram_req_data;
+
+ // Arbitrated signals - lookups have highest priority
+ assign lookup_grant_ic0 = lookup_req_ic0;
+ assign fill_grant_ic0 = fill_req_ic0 & ~lookup_req_ic0 & ~inval_prog_q & ~ecc_write_req;
+ // Qualified lookup grant to mask ram signals in IC1 if access was not made
+ assign lookup_actual_ic0 = lookup_grant_ic0 & icache_enable_i & ~inval_prog_q;
+
+ // Tagram
+ assign tag_req_ic0 = lookup_req_ic0 | fill_req_ic0 | inval_prog_q | ecc_write_req;
+ assign tag_index_ic0 = inval_prog_q ? inval_index_q :
+ ecc_write_req ? ecc_write_index :
+ fill_grant_ic0 ? fill_index_ic0 :
+ lookup_index_ic0;
+ assign tag_banks_ic0 = ecc_write_req ? ecc_write_ways :
+ fill_grant_ic0 ? fill_ram_req_way :
+ {NumWays{1'b1}};
+ assign tag_write_ic0 = fill_grant_ic0 | inval_prog_q | ecc_write_req;
+
+ // Dataram
+ assign data_req_ic0 = lookup_req_ic0 | fill_req_ic0;
+ assign data_index_ic0 = tag_index_ic0;
+ assign data_banks_ic0 = tag_banks_ic0;
+ assign data_write_ic0 = tag_write_ic0;
+
+ // Append ECC checkbits to write data if required
+ if (ICacheECC) begin : gen_ecc_wdata
+
+ // Tagram ECC
+ // Reuse the same ecc encoding module for larger cache sizes by padding with zeros
+ logic [21:0] tag_ecc_input_padded;
+ logic [27:0] tag_ecc_output_padded;
+ logic [22-TAG_SIZE:0] tag_ecc_output_unused;
+
+ assign tag_ecc_input_padded = {{22-TAG_SIZE{1'b0}},fill_tag_ic0};
+ assign tag_ecc_output_unused = tag_ecc_output_padded[21:TAG_SIZE-1];
+
+ prim_secded_28_22_enc tag_ecc_enc (
+ .in (tag_ecc_input_padded),
+ .out (tag_ecc_output_padded)
+ );
+
+ assign tag_wdata_ic0 = {tag_ecc_output_padded[27:22],tag_ecc_output_padded[TAG_SIZE-1:0]};
+
+ // Dataram ECC
+ prim_secded_72_64_enc data_ecc_enc (
+ .in (fill_wdata_ic0),
+ .out (data_wdata_ic0)
+ );
+
+ end else begin : gen_noecc_wdata
+ assign tag_wdata_ic0 = fill_tag_ic0;
+ assign data_wdata_ic0 = fill_wdata_ic0;
+ end
+
+ ////////////////
+ // IC0 -> IC1 //
+ ////////////////
+
+ for (genvar way = 0; way < NumWays; way++) begin : gen_rams
+ // Tag RAM instantiation
+ prim_generic_ram_1p #(
+ .Width (TAG_SIZE_ECC),
+ .Depth (NUM_LINES)
+ ) tag_bank (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .req_i (tag_req_ic0 & tag_banks_ic0[way]),
+ .write_i (tag_write_ic0),
+ .wmask_i ({TAG_SIZE_ECC{1'b1}}),
+ .addr_i (tag_index_ic0),
+ .wdata_i (tag_wdata_ic0),
+ .rvalid_o (),
+ .rdata_o (tag_rdata_ic1[way])
+ );
+ // Data RAM instantiation
+ prim_generic_ram_1p #(
+ .Width (LINE_SIZE_ECC),
+ .Depth (NUM_LINES)
+ ) data_bank (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .req_i (data_req_ic0 & data_banks_ic0[way]),
+ .write_i (data_write_ic0),
+ .wmask_i ({LINE_SIZE_ECC{1'b1}}),
+ .addr_i (data_index_ic0),
+ .wdata_i (data_wdata_ic0),
+ .rvalid_o (),
+ .rdata_o (data_rdata_ic1[way])
+ );
+ end
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ lookup_valid_ic1 <= 1'b0;
+ end else begin
+ lookup_valid_ic1 <= lookup_actual_ic0;
+ end
+ end
+
+ always_ff @(posedge clk_i) begin
+ if (lookup_grant_ic0) begin
+ lookup_addr_ic1 <= lookup_addr_ic0[ADDR_W-1:INDEX_HI+1];
+ fill_in_ic1 <= fill_alloc_sel;
+ end
+ end
+
+ ////////////////////////
+ // Pipeline stage IC1 //
+ ////////////////////////
+
+ // Tag matching
+ for (genvar way = 0; way < NumWays; way++) begin : gen_tag_match
+ assign tag_match_ic1[way] = (tag_rdata_ic1[way][TAG_SIZE-1:0] ==
+ {1'b1,lookup_addr_ic1[ADDR_W-1:INDEX_HI+1]});
+ assign tag_invalid_ic1[way] = ~tag_rdata_ic1[way][TAG_SIZE-1];
+ end
+
+ assign tag_hit_ic1 = |tag_match_ic1;
+
+ // Hit data mux
+ always_comb begin
+ hit_data_ic1 = 'b0;
+ for (int way = 0; way < NumWays; way++) begin
+ if (tag_match_ic1[way]) begin
+ hit_data_ic1 |= data_rdata_ic1[way];
+ end
+ end
+ end
+
+ // Way selection for allocations to the cache (onehot signals)
+ // 1 first invalid way
+ // 2 global round-robin (pseudorandom) way
+ assign lowest_invalid_way_ic1[0] = tag_invalid_ic1[0];
+ assign round_robin_way_ic1[0] = round_robin_way_q[NumWays-1];
+ for (genvar way = 1; way < NumWays; way++) begin : gen_lowest_way
+ assign lowest_invalid_way_ic1[way] = tag_invalid_ic1[way] & ~|tag_invalid_ic1[way-1:0];
+ assign round_robin_way_ic1[way] = round_robin_way_q[way-1];
+ end
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ round_robin_way_q <= {{NumWays-1{1'b0}},1'b1};
+ end else if (lookup_valid_ic1) begin
+ round_robin_way_q <= round_robin_way_ic1;
+ end
+ end
+
+ assign sel_way_ic1 = |tag_invalid_ic1 ? lowest_invalid_way_ic1 :
+ round_robin_way_q;
+
+ // ECC checking logic
+ if (ICacheECC) begin : gen_data_ecc_checking
+ logic [NumWays-1:0] tag_err_ic1;
+ logic [1:0] data_err_ic1;
+ logic ecc_correction_write_d, ecc_correction_write_q;
+ logic [NumWays-1:0] ecc_correction_ways_d, ecc_correction_ways_q;
+ logic [INDEX_W-1:0] lookup_index_ic1, ecc_correction_index_q;
+
+ // Tag ECC checking
+ for (genvar way = 0; way < NumWays; way++) begin : gen_tag_ecc
+ logic [1:0] tag_err_bank_ic1;
+ logic [27:0] tag_rdata_padded_ic1;
+
+ // Expand the tag rdata with extra padding if the tag size is less than the maximum
+ assign tag_rdata_padded_ic1 = {tag_rdata_ic1[way][TAG_SIZE_ECC-1-:6],
+ {22-TAG_SIZE{1'b0}},
+ tag_rdata_ic1[way][TAG_SIZE-1:0]};
+
+ prim_secded_28_22_dec data_ecc_dec (
+ .in (tag_rdata_padded_ic1),
+ .d_o (),
+ .syndrome_o (),
+ .err_o (tag_err_bank_ic1)
+ );
+ assign tag_err_ic1[way] = |tag_err_bank_ic1;
+ end
+
+ // Data ECC checking
+ // Note - could generate for all ways and mux after
+ prim_secded_72_64_dec data_ecc_dec (
+ .in (hit_data_ic1),
+ .d_o (),
+ .syndrome_o (),
+ .err_o (data_err_ic1)
+ );
+
+ assign ecc_err_ic1 = lookup_valid_ic1 & ((|data_err_ic1) | (|tag_err_ic1));
+
+ // Error correction
+ // The way(s) producing the error will be invalidated in the next cycle.
+ assign ecc_correction_ways_d = tag_err_ic1 | (tag_match_ic1 & {NumWays{|data_err_ic1}});
+ assign ecc_correction_write_d = ecc_err_ic1;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ ecc_correction_write_q <= 1'b0;
+ end else begin
+ ecc_correction_write_q <= ecc_correction_write_d;
+ end
+ end
+
+ // The index is required in IC1 only when ECC is configured so is registered here
+ always_ff @(posedge clk_i) begin
+ if (lookup_grant_ic0) begin
+ lookup_index_ic1 <= lookup_addr_ic0[INDEX_HI-:INDEX_W];
+ end
+ end
+
+ // Store the ways with errors to be invalidated
+ always_ff @(posedge clk_i) begin
+ if (ecc_err_ic1) begin
+ ecc_correction_ways_q <= ecc_correction_ways_d;
+ ecc_correction_index_q <= lookup_index_ic1;
+ end
+ end
+
+ assign ecc_write_req = ecc_correction_write_q;
+ assign ecc_write_ways = ecc_correction_ways_q;
+ assign ecc_write_index = ecc_correction_index_q;
+
+ end else begin : gen_no_data_ecc
+ assign ecc_err_ic1 = 1'b0;
+ assign ecc_write_req = 1'b0;
+ assign ecc_write_ways = '0;
+ assign ecc_write_index = '0;
+ end
+
+ ///////////////////////////////
+ // Cache allocation decision //
+ ///////////////////////////////
+
+ if (BranchCache) begin : gen_caching_logic
+
+ // Cache branch target + a number of subsequent lines
+ localparam int unsigned CACHE_AHEAD = 2;
+ localparam int unsigned CACHE_CNT_W = (CACHE_AHEAD == 1) ? 1 : $clog2(CACHE_AHEAD) + 1;
+ logic cache_cnt_dec;
+ logic [CACHE_CNT_W-1:0] cache_cnt_d, cache_cnt_q;
+
+ assign cache_cnt_dec = lookup_grant_ic0 & (|cache_cnt_q);
+ assign cache_cnt_d = branch_i ? CACHE_AHEAD[CACHE_CNT_W-1:0] :
+ (cache_cnt_q - {{CACHE_CNT_W-1{1'b0}},cache_cnt_dec});
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ cache_cnt_q <= '0;
+ end else begin
+ cache_cnt_q <= cache_cnt_d;
+ end
+ end
+
+ assign fill_cache_new = (branch_i | (|cache_cnt_q)) & icache_enable_i &
+ ~icache_inval_i & ~inval_prog_q;
+
+ end else begin : gen_cache_all
+
+ // Cache all missing fetches
+ assign fill_cache_new = icache_enable_i & ~icache_inval_i & ~inval_prog_q;
+ end
+
+ //////////////////////////
+ // Fill buffer tracking //
+ //////////////////////////
+
+ always_comb begin
+ fb_fill_level = '0;
+ for (int i = 0; i < NUM_FB; i++) begin
+ if (fill_busy_q[i] & ~fill_stale_q[i]) begin
+ fb_fill_level += {{$clog2(NUM_FB)-1{1'b0}},1'b1};
+ end
+ end
+ end
+
+ // PMP errors might not / don't need to be granted (since the external request is masked)
+ assign gnt_or_pmp_err = instr_gnt_i | instr_pmp_err_i;
+ assign gnt_not_pmp_err = instr_gnt_i & ~instr_pmp_err_i;
+ // Allocate a new buffer for every granted lookup
+ assign fill_new_alloc = lookup_grant_ic0;
+ // Track whether a speculative external request was made from IC0, and whether it was granted
+ assign fill_spec_done = (SpecRequest | branch_i) & ~|fill_ext_req & gnt_not_pmp_err;
+ assign fill_spec_hold = (SpecRequest | branch_i) & ~|fill_ext_req & ~gnt_or_pmp_err;
+
+ for (genvar fb = 0; fb < NUM_FB; fb++) begin : gen_fbs
+
+ /////////////////////////////
+ // Fill buffer allocations //
+ /////////////////////////////
+
+ // Allocate the lowest available buffer
+ if (fb == 0) begin : gen_fb_zero
+ assign fill_alloc_sel[fb] = ~fill_busy_q[fb];
+ end else begin : gen_fb_rest
+ assign fill_alloc_sel[fb] = ~fill_busy_q[fb] & (&fill_busy_q[fb-1:0]);
+ end
+
+ assign fill_alloc[fb] = fill_alloc_sel[fb] & fill_new_alloc;
+ assign fill_busy_d[fb] = fill_alloc[fb] | (fill_busy_q[fb] & ~fill_done[fb]);
+
+ // Track which other fill buffers are older than this one (for age-based arbitration)
+ // TODO sparsify
+ assign fill_older_d[fb] = (fill_alloc[fb] ? fill_busy_q : fill_older_q[fb]) & ~fill_done;
+
+ // A fill buffer can release once all its actions are completed
+ // all data written to the cache (unless hit or error)
+ assign fill_done[fb] = (fill_ram_done_q[fb] | fill_hit_q[fb] | ~fill_cache_q[fb] |
+ (|fill_err_q[fb])) &
+ // all data output unless stale due to intervening branch
+ (fill_out_done[fb] | fill_stale_q[fb] | branch_i) &
+ // all external requests completed
+ fill_rvd_done[fb];
+
+ /////////////////////////////////
+ // Fill buffer status tracking //
+ /////////////////////////////////
+
+ // Track staleness (requests become stale when a branch intervenes)
+ assign fill_stale_d[fb] = fill_busy_q[fb] & (branch_i | fill_stale_q[fb]);
+ // Track whether or not this request should allocate to the cache
+ assign fill_cache_d[fb] = (fill_alloc[fb] & fill_cache_new) |
+ (fill_cache_q[fb] & fill_busy_q[fb]);
+ // Record whether the request hit in the cache
+ assign fill_hit_ic1[fb] = lookup_valid_ic1 & fill_in_ic1[fb] & tag_hit_ic1;
+ assign fill_hit_d[fb] = (fill_hit_ic1[fb] & ~ecc_err_ic1) |
+ (fill_hit_q[fb] & fill_busy_q[fb]);
+
+ ///////////////////////////////////////////
+ // Fill buffer external request tracking //
+ ///////////////////////////////////////////
+
+ // Make an external request
+ assign fill_ext_req[fb] = fill_busy_q[fb] & ~fill_ext_done[fb];
+
+ // Count the number of completed external requests (each line requires LINE_BEATS requests)
+ // Don't count fake PMP error grants here since they will never receive an rvalid response
+ assign fill_ext_cnt_d[fb] = fill_alloc[fb] ?
+ {{LINE_BEATS_W{1'b0}},fill_spec_done} :
+ (fill_ext_cnt_q[fb] + {{LINE_BEATS_W{1'b0}},
+ fill_ext_arb[fb] & gnt_not_pmp_err});
+ // External request must be held until granted
+ assign fill_ext_hold_d[fb] = (fill_alloc[fb] & fill_spec_hold) |
+ (fill_ext_arb[fb] & ~gnt_or_pmp_err);
+ // External requests are completed when the counter is filled or when the request is cancelled
+ assign fill_ext_done[fb] = (fill_ext_cnt_q[fb][LINE_BEATS_W] |
+ // external requests are considered complete if the request hit
+ (fill_hit_ic1[fb] & ~ecc_err_ic1) | fill_hit_q[fb] |
+ // external requests will stop once any PMP error is received
+ fill_err_q[fb][fill_ext_off[fb]] |
+ // cancel if the line is stale and won't be cached
+ (~fill_cache_q[fb] & (branch_i | fill_stale_q[fb]))) &
+ // can't cancel while we are waiting for a grant on the bus
+ ~fill_ext_hold_q[fb];
+ // Track whether this fill buffer expects to receive beats of data
+ assign fill_rvd_exp[fb] = fill_busy_q[fb] & ~fill_rvd_done[fb];
+ // Count the number of rvalid beats received
+ assign fill_rvd_cnt_d[fb] = fill_alloc[fb] ? '0 :
+ (fill_rvd_cnt_q[fb] +
+ {{LINE_BEATS_W{1'b0}},fill_rvd_arb[fb]});
+ // External data is complete when all issued external requests have received their data
+ assign fill_rvd_done[fb] = fill_ext_done[fb] & (fill_rvd_cnt_q[fb] == fill_ext_cnt_q[fb]);
+
+ //////////////////////////////////////
+ // Fill buffer data output tracking //
+ //////////////////////////////////////
+
+ // Send data to the IF stage for requests that are not stale, have not completed their
+ // data output, and have data available to send.
+ // Data is available if:
+ // - The request hit in the cache
+ // - Buffered data is available (fill_rvd_cnt_q is ahead of fill_out_cnt_q)
+ // - Data is available from the bus this cycle (fill_rvd_arb)
+ assign fill_out_req[fb] = fill_busy_q[fb] & ~fill_stale_q[fb] & ~fill_out_done[fb] &
+ (fill_hit_ic1[fb] | fill_hit_q[fb] |
+ (fill_rvd_beat[fb] > fill_out_cnt_q[fb]) | fill_rvd_arb[fb]);
+
+ // Calculate when a beat of data is output. Any ECC error squashes the output that cycle.
+ assign fill_out_grant[fb] = fill_out_arb[fb] & output_ready & ~ecc_err_ic1;
+
+ // Count the beats of data output to the IF stage
+ assign fill_out_cnt_d[fb] = fill_alloc[fb] ? {1'b0,lookup_addr_ic0[LINE_W-1:BUS_W]} :
+ (fill_out_cnt_q[fb] +
+ {{LINE_BEATS_W{1'b0}},fill_out_grant[fb]});
+ // Data output complete when the counter fills
+ assign fill_out_done[fb] = fill_out_cnt_q[fb][LINE_BEATS_W];
+
+ //////////////////////////////////////
+ // Fill buffer ram request tracking //
+ //////////////////////////////////////
+
+ // make a fill request once all data beats received
+ assign fill_ram_req[fb] = fill_busy_q[fb] & fill_rvd_cnt_q[fb][LINE_BEATS_W] &
+ // unless the request hit, was non-allocating or got an error
+ ~fill_hit_q[fb] & fill_cache_q[fb] & ~|fill_err_q &
+ // or the request was already completed
+ ~fill_ram_done_q[fb];
+
+ // Record when a cache allocation request has been completed
+ assign fill_ram_done_d[fb] = fill_ram_arb[fb] | (fill_ram_done_q[fb] & fill_busy_q[fb]);
+
+ //////////////////////////////
+ // Fill buffer line offsets //
+ //////////////////////////////
+
+ // When we branch into the middle of a line, the output count will not start from zero. This
+ // beat count is used to know which incoming rdata beats are relevant.
+ assign fill_rvd_beat[fb] = {1'b0,fill_addr_q[fb][LINE_W-1:BUS_W]} +
+ fill_rvd_cnt_q[fb][LINE_BEATS_W:0];
+ assign fill_ext_off[fb] = fill_addr_q[fb][LINE_W-1:BUS_W] +
+ fill_ext_cnt_q[fb][LINE_BEATS_W-1:0];
+ assign fill_rvd_off[fb] = fill_rvd_beat[fb][LINE_BEATS_W-1:0];
+
+ /////////////////////////////
+ // Fill buffer arbitration //
+ /////////////////////////////
+
+ // Age based arbitration - all these signals are one-hot
+ assign fill_ext_arb[fb] = fill_ext_req[fb] & ~|(fill_ext_req & fill_older_q[fb]);
+ assign fill_ram_arb[fb] = fill_ram_req[fb] & fill_grant_ic0 & ~|(fill_ram_req & fill_older_q[fb]);
+ // Calculate which fill buffer is the oldest one which still needs to output data to IF
+ assign fill_data_sel[fb] = ~|(fill_busy_q & ~fill_out_done & ~fill_stale_q &
+ fill_older_q[fb]);
+ // Arbitrate the request which has data available to send, and is the oldest outstanding
+ assign fill_out_arb[fb] = fill_out_req[fb] & fill_data_sel[fb];
+ // Assign incoming rvalid data to the oldest fill buffer expecting it
+ assign fill_rvd_arb[fb] = instr_rvalid_i & fill_rvd_exp[fb] & ~|(fill_rvd_exp & fill_older_q[fb]);
+
+ /////////////////////////////
+ // Fill buffer data muxing //
+ /////////////////////////////
+
+ // Output data muxing controls
+ // 1. Select data from the fill buffer data register
+ assign fill_data_reg[fb] = fill_busy_q[fb] & ~fill_stale_q[fb] &
+ ~fill_out_done[fb] & fill_data_sel[fb] &
+ // The incoming data is already ahead of the output count
+ ((fill_rvd_beat[fb] > fill_out_cnt_q[fb]) | fill_hit_q[fb]);
+ // 2. Select IC1 hit data
+ assign fill_data_hit[fb] = fill_busy_q[fb] & fill_hit_ic1[fb] & fill_data_sel[fb];
+ // 3. Select incoming instr_rdata_i
+ assign fill_data_rvd[fb] = fill_busy_q[fb] & fill_rvd_arb[fb] & ~fill_hit_q[fb] &
+ ~fill_stale_q[fb] & ~fill_out_done[fb] &
+ // The incoming data lines up with the output count
+ (fill_rvd_beat[fb] == fill_out_cnt_q[fb]) & fill_data_sel[fb];
+
+
+ ///////////////////////////
+ // Fill buffer registers //
+ ///////////////////////////
+
+ // Fill buffer general enable
+ assign fill_entry_en[fb] = fill_alloc[fb] | fill_busy_q[fb];
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ fill_busy_q[fb] <= 1'b0;
+ fill_older_q[fb] <= '0;
+ fill_stale_q[fb] <= 1'b0;
+ fill_cache_q[fb] <= 1'b0;
+ fill_hit_q[fb] <= 1'b0;
+ fill_ext_cnt_q[fb] <= '0;
+ fill_ext_hold_q[fb] <= 1'b0;
+ fill_rvd_cnt_q[fb] <= '0;
+ fill_ram_done_q[fb] <= 1'b0;
+ fill_out_cnt_q[fb] <= '0;
+ end else if (fill_entry_en[fb]) begin
+ fill_busy_q[fb] <= fill_busy_d[fb];
+ fill_older_q[fb] <= fill_older_d[fb];
+ fill_stale_q[fb] <= fill_stale_d[fb];
+ fill_cache_q[fb] <= fill_cache_d[fb];
+ fill_hit_q[fb] <= fill_hit_d[fb];
+ fill_ext_cnt_q[fb] <= fill_ext_cnt_d[fb];
+ fill_ext_hold_q[fb] <= fill_ext_hold_d[fb];
+ fill_rvd_cnt_q[fb] <= fill_rvd_cnt_d[fb];
+ fill_ram_done_q[fb] <= fill_ram_done_d[fb];
+ fill_out_cnt_q[fb] <= fill_out_cnt_d[fb];
+ end
+ end
+
+ ////////////////////////////////////////
+ // Fill buffer address / data storage //
+ ////////////////////////////////////////
+
+ assign fill_addr_en[fb] = fill_alloc[fb];
+ assign fill_way_en[fb] = (lookup_valid_ic1 & fill_in_ic1[fb]);
+
+ always_ff @(posedge clk_i) begin
+ if (fill_addr_en[fb]) begin
+ fill_addr_q[fb] <= lookup_addr_ic0;
+ end
+ end
+
+ always_ff @(posedge clk_i) begin
+ if (fill_way_en[fb]) begin
+ fill_way_q[fb] <= sel_way_ic1;
+ end
+ end
+
+ // Data either comes from the cache or the bus. If there was an ECC error, we must take
+ // the incoming bus data since the cache hit data is corrupted.
+ assign fill_data_d[fb] = (fill_hit_ic1[fb] & ~ecc_err_ic1) ? hit_data_ic1[LineSize-1:0] :
+ {LINE_BEATS{instr_rdata_i}};
+
+ for (genvar b = 0; b < LINE_BEATS; b++) begin : gen_data_buf
+ // Error tracking (per beat)
+ // Either a PMP error at grant,
+ assign fill_err_d[fb][b] = (fill_ext_arb[fb] & instr_pmp_err_i &
+ (fill_ext_off[fb] == b[LINE_BEATS_W-1:0])) |
+ // Or a data error with instr_rvalid_i
+ (fill_rvd_arb[fb] & instr_err_i &
+ (fill_rvd_off[fb] == b[LINE_BEATS_W-1:0])) |
+ // Hold the error once recorded
+ (fill_busy_q[fb] & fill_err_q[fb][b]);
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ fill_err_q[fb][b] <= '0;
+ end else if (fill_entry_en[fb]) begin
+ fill_err_q[fb][b] <= fill_err_d[fb][b];
+ end
+ end
+
+ // Enable the relevant part of the data register (or all for cache hits)
+ assign fill_data_en[fb][b] = fill_hit_ic1[fb] |
+ (fill_rvd_arb[fb] & (fill_rvd_off[fb] == b[LINE_BEATS_W-1:0]));
+
+ always_ff @(posedge clk_i) begin
+ if (fill_data_en[fb][b]) begin
+ fill_data_q[fb][b*BusWidth+:BusWidth] <= fill_data_d[fb][b*BusWidth+:BusWidth];
+ end
+ end
+
+ end
+ end
+
+ ////////////////////////////////
+ // Fill buffer one-hot muxing //
+ ////////////////////////////////
+
+ // External req info
+ always_comb begin
+ fill_ext_req_addr = '0;
+ for (int i = 0; i < NUM_FB; i++) begin
+ if (fill_ext_arb[i]) begin
+ fill_ext_req_addr |= {fill_addr_q[i][ADDR_W-1:LINE_W], fill_ext_off[i]};
+ end
+ end
+ end
+
+ // Cache req info
+ always_comb begin
+ fill_ram_req_addr = '0;
+ fill_ram_req_way = '0;
+ fill_ram_req_data = '0;
+ for (int i = 0; i < NUM_FB; i++) begin
+ if (fill_ram_arb[i]) begin
+ fill_ram_req_addr |= fill_addr_q[i];
+ fill_ram_req_way |= fill_way_q[i];
+ fill_ram_req_data |= fill_data_q[i];
+ end
+ end
+ end
+
+ // IF stage output data
+ always_comb begin
+ fill_out_data = '0;
+ fill_out_err = '0;
+ for (int i = 0; i < NUM_FB; i++) begin
+ if (fill_data_reg[i]) begin
+ fill_out_data |= fill_data_q[i];
+ fill_out_err |= fill_err_q[i];
+ end
+ end
+ end
+
+ ///////////////////////
+ // External requests //
+ ///////////////////////
+
+ assign instr_req = ((SpecRequest | branch_i) & lookup_grant_ic0) |
+ |fill_ext_req;
+
+ assign instr_addr = |fill_ext_req ? fill_ext_req_addr :
+ lookup_addr_ic0[ADDR_W-1:BUS_W];
+
+ assign instr_req_o = instr_req;
+ assign instr_addr_o = {instr_addr[ADDR_W-1:BUS_W],{BUS_W{1'b0}}};
+
+ ////////////////////////
+ // Output data muxing //
+ ////////////////////////
+
+ // Mux between line-width data sources
+ assign line_data = |fill_data_hit ? hit_data_ic1[LineSize-1:0] : fill_out_data;
+ assign line_err = |fill_data_hit ? {LINE_BEATS{1'b0}} : fill_out_err;
+
+ // Mux the relevant beat of line data, based on the output address
+ always_comb begin
+ line_data_muxed = '0;
+ line_err_muxed = 1'b0;
+ for (int i = 0; i < LINE_BEATS; i++) begin
+ // When data has been skidded, the output address is behind by one
+ if ((output_addr_q[LINE_W-1:BUS_W] + {{LINE_BEATS_W-1{1'b0}},skid_valid_q}) ==
+ i[LINE_BEATS_W-1:0]) begin
+ line_data_muxed |= line_data[i*32+:32];
+ line_err_muxed |= line_err[i];
+ end
+ end
+ end
+
+ // Mux between incoming rdata and the muxed line data
+ assign output_data = |fill_data_rvd ? instr_rdata_i : line_data_muxed;
+ assign output_err = |fill_data_rvd ? instr_err_i : line_err_muxed;
+
+ // Output data is valid (from any of the three possible sources). Note that fill_out_arb
+ // must be used here rather than fill_out_req because data can become valid out of order
+ // (e.g. cache hit data can become available ahead of an older outstanding miss).
+ // Any ECC error suppresses the output that cycle.
+ assign data_valid = |fill_out_arb & ~ecc_err_ic1;
+
+ // Skid buffer data
+ assign skid_data_d = output_data[31:16];
+
+ assign skid_en = data_valid & ready_i;
+
+ always_ff @(posedge clk_i) begin
+ if (skid_en) begin
+ skid_data_q <= skid_data_d;
+ skid_err_q <= output_err;
+ end
+ end
+
+ // The data in the skid buffer is a complete compressed instruction
+ assign skid_complete_instr = skid_valid_q & (skid_data_q[1:0] != 2'b11);
+
+ assign output_ready = ready_i & ~skid_complete_instr;
+
+ assign output_compressed = (rdata_o[1:0] != 2'b11);
+
+ assign skid_valid_d =
+ // Branches invalidate the skid buffer
+ branch_i ? 1'b0 :
+ // Once valid, the skid buffer stays valid until a compressed instruction realigns the stream
+ (skid_valid_q ? ~(ready_i & (skid_data_q[1:0] != 2'b11)) :
+ // The skid buffer becomes valid when a compressed instruction misaligns the stream
+ ((output_addr_q[1] ^ output_compressed) & data_valid & ready_i));
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ skid_valid_q <= 1'b0;
+ end else begin
+ skid_valid_q <= skid_valid_d;
+ end
+ end
+
+ // Signal that valid data is available to the IF stage
+ // Note that if the first half of an unaligned instruction reports an error, we do not need
+ // to wait for the second half (and for PMP errors we might not have fetched the second half)
+ // Compressed instruction completely satisfied by skid buffer
+ assign output_valid = skid_complete_instr |
+ // Output data available and, output stream aligned, or skid data available,
+ (data_valid & (~output_addr_q[1] | skid_valid_q |
+ // or this half is an error, or this is an unaligned compressed instruction
+ output_err | (output_data[17:16] != 2'b11)));
+
+ // Update the address on branches and every time an instruction is driven
+ assign output_addr_en = branch_i | (ready_i & valid_o);
+
+ // Increment the address by two every time a compressed instruction is popped
+ assign addr_incr_two = output_compressed;
+
+ assign output_addr_d = branch_i ? addr_i[31:1] :
+ (output_addr_q[31:1] +
+ // Increment address by 4 or 2
+ {29'd0, ~addr_incr_two, addr_incr_two});
+
+ always_ff @(posedge clk_i) begin
+ if (output_addr_en) begin
+ output_addr_q <= output_addr_d;
+ end
+ end
+
+ // Mux the data from BusWidth to halfword
+ // This muxing realigns data when instruction words are split across BUS_W e.g.
+ // word 1 |----|*h1*|
+ // word 0 |*h0*|----| --> |*h1*|*h0*|
+ // 31 15 0 31 15 0
+ always_comb begin
+ output_data_lo = '0;
+ for (int i = 0; i < OUTPUT_BEATS; i++) begin
+ if (output_addr_q[BUS_W-1:1] == i[BUS_W-2:0]) begin
+ output_data_lo |= output_data[i*16+:16];
+ end
+ end
+ end
+
+ always_comb begin
+ output_data_hi = '0;
+ for (int i = 0; i < OUTPUT_BEATS-1; i++) begin
+ if (output_addr_q[BUS_W-1:1] == i[BUS_W-2:0]) begin
+ output_data_hi |= output_data[(i+1)*16+:16];
+ end
+ end
+ if (&output_addr_q[BUS_W-1:1]) begin
+ output_data_hi |= output_data[15:0];
+ end
+ end
+
+ assign valid_o = output_valid;
+ assign rdata_o = {output_data_hi, (skid_valid_q ? skid_data_q : output_data_lo)};
+ assign addr_o = {output_addr_q, 1'b0};
+ assign err_o = (skid_valid_q & skid_err_q) | (~skid_complete_instr & output_err);
+ // Error caused by the second half of a misaligned uncompressed instruction
+ assign err_plus2_o = output_addr_q[1] & output_err & ~skid_err_q &
+ ~(output_data[17:16] != 2'b11);
+
+ ///////////////////
+ // Invalidations //
+ ///////////////////
+
+ // Invalidate on reset, or when instructed. If an invalidation request is received while a
+ // previous invalidation is ongoing, it does not need to be restarted.
+ assign start_inval = (~reset_inval_q | icache_inval_i) & ~inval_prog_q;
+ assign inval_prog_d = start_inval | (inval_prog_q & ~inval_done);
+ assign inval_done = &inval_index_q;
+ assign inval_index_d = start_inval ? '0 :
+ (inval_index_q + {{INDEX_W-1{1'b0}},1'b1});
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ inval_prog_q <= 1'b0;
+ reset_inval_q <= 1'b0;
+ end else begin
+ inval_prog_q <= inval_prog_d;
+ reset_inval_q <= 1'b1;
+ end
+ end
+
+ always_ff @(posedge clk_i) begin
+ if (inval_prog_d) begin
+ inval_index_q <= inval_index_d;
+ end
+ end
+
+ /////////////////
+ // Busy status //
+ /////////////////
+
+ // Only busy (for WFI purposes) while an invalidation is in-progress, or external requests are
+ // outstanding.
+ assign busy_o = inval_prog_q | (|(fill_busy_q & ~fill_rvd_done));
+
+ ////////////////
+ // Assertions //
+ ////////////////
+
+ `ASSERT_INIT(size_param_legal, (LineSize > 32))
+
+ // ECC primitives will need to be changed for different sizes
+ `ASSERT_INIT(ecc_tag_param_legal, (TAG_SIZE <= 27))
+ `ASSERT_INIT(ecc_data_param_legal, (LineSize <= 121))
+
+endmodule
diff --git a/hw/vendor/lowrisc_ibex/rtl/ibex_id_stage.sv b/hw/vendor/lowrisc_ibex/rtl/ibex_id_stage.sv
index 572ecaa..62756cb 100644
--- a/hw/vendor/lowrisc_ibex/rtl/ibex_id_stage.sv
+++ b/hw/vendor/lowrisc_ibex/rtl/ibex_id_stage.sv
@@ -19,127 +19,154 @@
module ibex_id_stage #(
parameter bit RV32E = 0,
parameter bit RV32M = 1,
- parameter bit BranchTargetALU = 0
+ parameter bit RV32B = 0,
+ parameter bit BranchTargetALU = 0,
+ parameter bit WritebackStage = 0
) (
- input logic clk_i,
- input logic rst_ni,
+ input logic clk_i,
+ input logic rst_ni,
- input logic test_en_i,
-
- input logic fetch_enable_i,
- output logic ctrl_busy_o,
- output logic illegal_insn_o,
+ input logic fetch_enable_i,
+ output logic ctrl_busy_o,
+ output logic illegal_insn_o,
// Interface to IF stage
- input logic instr_valid_i,
- input logic instr_new_i,
- input logic [31:0] instr_rdata_i, // from IF-ID pipeline registers
- input logic [31:0] instr_rdata_alu_i, // from IF-ID pipeline registers
- input logic [15:0] instr_rdata_c_i, // from IF-ID pipeline registers
- input logic instr_is_compressed_i,
- output logic instr_req_o,
- output logic instr_valid_clear_o, // kill instr in IF-ID reg
- output logic id_in_ready_o, // ID stage is ready for next instr
+ input logic instr_valid_i,
+ input logic [31:0] instr_rdata_i, // from IF-ID pipeline registers
+ input logic [31:0] instr_rdata_alu_i, // from IF-ID pipeline registers
+ input logic [15:0] instr_rdata_c_i, // from IF-ID pipeline registers
+ input logic instr_is_compressed_i,
+ output logic instr_req_o,
+ output logic instr_first_cycle_id_o,
+ output logic instr_valid_clear_o, // kill instr in IF-ID reg
+ output logic id_in_ready_o, // ID stage is ready for next instr
+ output logic icache_inval_o,
// Jumps and branches
- input logic branch_decision_i,
+ input logic branch_decision_i,
// IF and ID stage signals
- output logic pc_set_o,
- output ibex_pkg::pc_sel_e pc_mux_o,
- output ibex_pkg::exc_pc_sel_e exc_pc_mux_o,
- output ibex_pkg::exc_cause_e exc_cause_o,
+ output logic pc_set_o,
+ output ibex_pkg::pc_sel_e pc_mux_o,
+ output ibex_pkg::exc_pc_sel_e exc_pc_mux_o,
+ output ibex_pkg::exc_cause_e exc_cause_o,
- input logic illegal_c_insn_i,
- input logic instr_fetch_err_i,
+ input logic illegal_c_insn_i,
+ input logic instr_fetch_err_i,
+ input logic instr_fetch_err_plus2_i,
- input logic [31:0] pc_id_i,
+ input logic [31:0] pc_id_i,
// Stalls
- input logic ex_valid_i, // EX stage has valid output
- input logic lsu_valid_i, // LSU has valid output, or is done
+ input logic ex_valid_i, // EX stage has valid output
+ input logic lsu_valid_i, // LSU has valid output, or is done
+ input logic lsu_load_i, // LSU is performing a load
+ input logic lsu_busy_i, // LSU is busy
// ALU
- output ibex_pkg::alu_op_e alu_operator_ex_o,
- output logic [31:0] alu_operand_a_ex_o,
- output logic [31:0] alu_operand_b_ex_o,
+ output ibex_pkg::alu_op_e alu_operator_ex_o,
+ output logic [31:0] alu_operand_a_ex_o,
+ output logic [31:0] alu_operand_b_ex_o,
// Branch target ALU
- output ibex_pkg::jt_mux_sel_e jt_mux_sel_ex_o,
- output logic [11:0] bt_operand_imm_o,
+ output logic [31:0] bt_a_operand_o,
+ output logic [31:0] bt_b_operand_o,
// MUL, DIV
- output logic mult_en_ex_o,
- output logic div_en_ex_o,
- output logic multdiv_sel_ex_o,
- output ibex_pkg::md_op_e multdiv_operator_ex_o,
- output logic [1:0] multdiv_signed_mode_ex_o,
- output logic [31:0] multdiv_operand_a_ex_o,
- output logic [31:0] multdiv_operand_b_ex_o,
+ output logic mult_en_ex_o,
+ output logic div_en_ex_o,
+ output logic multdiv_sel_ex_o,
+ output ibex_pkg::md_op_e multdiv_operator_ex_o,
+ output logic [1:0] multdiv_signed_mode_ex_o,
+ output logic [31:0] multdiv_operand_a_ex_o,
+ output logic [31:0] multdiv_operand_b_ex_o,
+ output logic multdiv_ready_id_o,
// CSR
- output logic csr_access_o,
- output ibex_pkg::csr_op_e csr_op_o,
- output logic csr_save_if_o,
- output logic csr_save_id_o,
- output logic csr_restore_mret_id_o,
- output logic csr_restore_dret_id_o,
- output logic csr_save_cause_o,
- output logic [31:0] csr_mtval_o,
- input ibex_pkg::priv_lvl_e priv_mode_i,
- input logic csr_mstatus_tw_i,
- input logic illegal_csr_insn_i,
+ output logic csr_access_o,
+ output ibex_pkg::csr_op_e csr_op_o,
+ output logic csr_op_en_o,
+ output logic csr_save_if_o,
+ output logic csr_save_id_o,
+ output logic csr_save_wb_o,
+ output logic csr_restore_mret_id_o,
+ output logic csr_restore_dret_id_o,
+ output logic csr_save_cause_o,
+ output logic [31:0] csr_mtval_o,
+ input ibex_pkg::priv_lvl_e priv_mode_i,
+ input logic csr_mstatus_tw_i,
+ input logic illegal_csr_insn_i,
// Interface to load store unit
- output logic data_req_ex_o,
- output logic data_we_ex_o,
- output logic [1:0] data_type_ex_o,
- output logic data_sign_ext_ex_o,
- output logic [31:0] data_wdata_ex_o,
+ output logic lsu_req_o,
+ output logic lsu_we_o,
+ output logic [1:0] lsu_type_o,
+ output logic lsu_sign_ext_o,
+ output logic [31:0] lsu_wdata_o,
- input logic lsu_addr_incr_req_i,
- input logic [31:0] lsu_addr_last_i,
+ input logic lsu_req_done_i, // Data req to LSU is complete and
+ // instruction can move to writeback
+ // (only relevant where writeback stage is
+ // present)
+
+ input logic lsu_addr_incr_req_i,
+ input logic [31:0] lsu_addr_last_i,
// Interrupt signals
- input logic csr_mstatus_mie_i,
- input logic irq_pending_i,
- input ibex_pkg::irqs_t irqs_i,
- input logic irq_nm_i,
- output logic nmi_mode_o,
+ input logic csr_mstatus_mie_i,
+ input logic irq_pending_i,
+ input ibex_pkg::irqs_t irqs_i,
+ input logic irq_nm_i,
+ output logic nmi_mode_o,
- input logic lsu_load_err_i,
- input logic lsu_store_err_i,
+ input logic lsu_load_err_i,
+ input logic lsu_store_err_i,
// Debug Signal
- output logic debug_mode_o,
- output ibex_pkg::dbg_cause_e debug_cause_o,
- output logic debug_csr_save_o,
- input logic debug_req_i,
- input logic debug_single_step_i,
- input logic debug_ebreakm_i,
- input logic debug_ebreaku_i,
- input logic trigger_match_i,
+ output logic debug_mode_o,
+ output ibex_pkg::dbg_cause_e debug_cause_o,
+ output logic debug_csr_save_o,
+ input logic debug_req_i,
+ input logic debug_single_step_i,
+ input logic debug_ebreakm_i,
+ input logic debug_ebreaku_i,
+ input logic trigger_match_i,
// Write back signal
- input logic [31:0] regfile_wdata_lsu_i,
- input logic [31:0] regfile_wdata_ex_i,
- input logic [31:0] csr_rdata_i,
+ input logic [31:0] result_ex_i,
+ input logic [31:0] csr_rdata_i,
-`ifdef RVFI
- output logic [4:0] rfvi_reg_raddr_ra_o,
- output logic [31:0] rfvi_reg_rdata_ra_o,
- output logic [4:0] rfvi_reg_raddr_rb_o,
- output logic [31:0] rfvi_reg_rdata_rb_o,
- output logic [4:0] rfvi_reg_waddr_rd_o,
- output logic [31:0] rfvi_reg_wdata_rd_o,
- output logic rfvi_reg_we_o,
-`endif
+ // Register file read
+ output logic [4:0] rf_raddr_a_o,
+ input logic [31:0] rf_rdata_a_i,
+ output logic [4:0] rf_raddr_b_o,
+ input logic [31:0] rf_rdata_b_i,
+
+ // Register file write (via writeback)
+ output logic [4:0] rf_waddr_id_o,
+ output logic [31:0] rf_wdata_id_o,
+ output logic rf_we_id_o,
+
+ // Register write information from writeback (for resolving data hazards)
+ input logic [4:0] rf_waddr_wb_i,
+ input logic [31:0] rf_wdata_fwd_wb_i,
+ input logic rf_write_wb_i,
+
+ output logic en_wb_o,
+ output ibex_pkg::wb_instr_type_e instr_type_wb_o,
+ input logic ready_wb_i,
+ input logic outstanding_load_wb_i,
+ input logic outstanding_store_wb_i,
// Performance Counters
- output logic perf_jump_o, // executing a jump instr
- output logic perf_branch_o, // executing a branch instr
- output logic perf_tbranch_o, // executing a taken branch instr
- output logic instr_ret_o,
- output logic instr_ret_compressed_o
+ output logic perf_jump_o, // executing a jump instr
+ output logic perf_branch_o, // executing a branch instr
+ output logic perf_tbranch_o, // executing a taken branch instr
+ output logic perf_dside_wait_o, // instruction in ID/EX is awaiting memory
+ // access to finish before proceeding
+ output logic perf_mul_wait_o,
+ output logic perf_div_wait_o,
+ output logic instr_id_done_o,
+ output logic instr_id_done_compressed_o
);
import ibex_pkg::*;
@@ -152,18 +179,26 @@
logic ecall_insn_dec;
logic wfi_insn_dec;
+ logic wb_exception;
+
logic branch_in_dec;
logic branch_set, branch_set_d;
logic jump_in_dec;
logic jump_set;
+ logic instr_first_cycle;
logic instr_executing;
- logic instr_multicycle;
- logic instr_multicycle_done_n, instr_multicycle_done_q;
- logic stall_lsu;
+ logic instr_done;
+ logic controller_run;
+ logic stall_ld_hz;
+ logic stall_mem;
logic stall_multdiv;
logic stall_branch;
logic stall_jump;
+ logic stall_id;
+ logic stall_wb;
+ logic flush_id;
+ logic multicycle_done;
// Immediate decoding and sign extension
logic [31:0] imm_i_type;
@@ -177,24 +212,22 @@
logic [31:0] imm_b; // contains the immediate for operand b
// Register file interface
- logic [4:0] regfile_raddr_a;
- logic [4:0] regfile_raddr_b;
- logic [4:0] regfile_waddr;
+ rf_wd_sel_e rf_wdata_sel;
+ logic rf_we_dec, rf_we_raw;
+ logic rf_ren_a, rf_ren_b;
- logic [31:0] regfile_rdata_a;
- logic [31:0] regfile_rdata_b;
- logic [31:0] regfile_wdata;
-
- rf_wd_sel_e regfile_wdata_sel;
- logic regfile_we;
- logic regfile_we_wb, regfile_we_dec;
+ logic [31:0] rf_rdata_a_fwd;
+ logic [31:0] rf_rdata_b_fwd;
// ALU Control
alu_op_e alu_operator;
op_a_sel_e alu_op_a_mux_sel, alu_op_a_mux_sel_dec;
op_b_sel_e alu_op_b_mux_sel, alu_op_b_mux_sel_dec;
+ op_a_sel_e bt_a_mux_sel;
+ imm_b_sel_e bt_b_mux_sel;
+
imm_a_sel_e imm_a_mux_sel;
imm_b_sel_e imm_b_mux_sel, imm_b_mux_sel_dec;
@@ -207,10 +240,11 @@
logic [1:0] multdiv_signed_mode;
// Data Memory Control
- logic data_we_id;
- logic [1:0] data_type_id;
- logic data_sign_ext_id;
- logic data_req_id, data_req_dec;
+ logic lsu_we;
+ logic [1:0] lsu_type;
+ logic lsu_sign_ext;
+ logic lsu_req, lsu_req_dec;
+ logic data_req_allowed;
// CSR control
logic csr_pipe_flush;
@@ -228,16 +262,16 @@
assign imm_b_mux_sel = lsu_addr_incr_req_i ? IMM_B_INCR_ADDR : imm_b_mux_sel_dec;
///////////////////
- // Operand A MUX //
+ // Operand MUXES //
///////////////////
- // Immediate MUX for Operand A
+ // Main ALU immediate MUX for Operand A
assign imm_a = (imm_a_mux_sel == IMM_A_Z) ? zimm_rs1_type : '0;
- // ALU MUX for Operand A
+ // Main ALU MUX for Operand A
always_comb begin : alu_operand_a_mux
unique case (alu_op_a_mux_sel)
- OP_A_REG_A: alu_operand_a = regfile_rdata_a;
+ OP_A_REG_A: alu_operand_a = rf_rdata_a_fwd;
OP_A_FWD: alu_operand_a = lsu_addr_last_i;
OP_A_CURRPC: alu_operand_a = pc_id_i;
OP_A_IMM: alu_operand_a = imm_a;
@@ -245,78 +279,81 @@
endcase
end
- ///////////////////
- // Operand B MUX //
- ///////////////////
+ if (BranchTargetALU) begin : g_btalu_muxes
+ // Branch target ALU operand A mux
+ always_comb begin : bt_operand_a_mux
+ unique case (bt_a_mux_sel)
+ OP_A_REG_A: bt_a_operand_o = rf_rdata_a_fwd;
+ OP_A_CURRPC: bt_a_operand_o = pc_id_i;
+ default: bt_a_operand_o = pc_id_i;
+ endcase
+ end
- // Immediate MUX for Operand B
- always_comb begin : immediate_b_mux
- unique case (imm_b_mux_sel)
- IMM_B_I: imm_b = imm_i_type;
- IMM_B_S: imm_b = imm_s_type;
- IMM_B_B: imm_b = imm_b_type;
- IMM_B_U: imm_b = imm_u_type;
- IMM_B_J: imm_b = imm_j_type;
- IMM_B_INCR_PC: imm_b = instr_is_compressed_i ? 32'h2 : 32'h4;
- IMM_B_INCR_ADDR: imm_b = 32'h4;
- default: imm_b = 32'h4;
- endcase
+ // Branch target ALU operand B mux
+ always_comb begin : bt_immediate_b_mux
+ unique case (bt_b_mux_sel)
+ IMM_B_I: bt_b_operand_o = imm_i_type;
+ IMM_B_B: bt_b_operand_o = imm_b_type;
+ IMM_B_J: bt_b_operand_o = imm_j_type;
+ IMM_B_INCR_PC: bt_b_operand_o = instr_is_compressed_i ? 32'h2 : 32'h4;
+ default: bt_b_operand_o = instr_is_compressed_i ? 32'h2 : 32'h4;
+ endcase
+ end
+
+ // Reduced main ALU immediate MUX for Operand B
+ always_comb begin : immediate_b_mux
+ unique case (imm_b_mux_sel)
+ IMM_B_I: imm_b = imm_i_type;
+ IMM_B_S: imm_b = imm_s_type;
+ IMM_B_U: imm_b = imm_u_type;
+ IMM_B_INCR_PC: imm_b = instr_is_compressed_i ? 32'h2 : 32'h4;
+ IMM_B_INCR_ADDR: imm_b = 32'h4;
+ default: imm_b = 32'h4;
+ endcase
+ end
+ end else begin : g_nobtalu
+ op_a_sel_e unused_a_mux_sel;
+ imm_b_sel_e unused_b_mux_sel;
+
+ assign unused_a_mux_sel = bt_a_mux_sel;
+ assign unused_b_mux_sel = bt_b_mux_sel;
+ assign bt_a_operand_o = '0;
+ assign bt_b_operand_o = '0;
+
+ // Full main ALU immediate MUX for Operand B
+ always_comb begin : immediate_b_mux
+ unique case (imm_b_mux_sel)
+ IMM_B_I: imm_b = imm_i_type;
+ IMM_B_S: imm_b = imm_s_type;
+ IMM_B_B: imm_b = imm_b_type;
+ IMM_B_U: imm_b = imm_u_type;
+ IMM_B_J: imm_b = imm_j_type;
+ IMM_B_INCR_PC: imm_b = instr_is_compressed_i ? 32'h2 : 32'h4;
+ IMM_B_INCR_ADDR: imm_b = 32'h4;
+ default: imm_b = 32'h4;
+ endcase
+ end
end
// ALU MUX for Operand B
- assign alu_operand_b = (alu_op_b_mux_sel == OP_B_IMM) ? imm_b : regfile_rdata_b;
+ assign alu_operand_b = (alu_op_b_mux_sel == OP_B_IMM) ? imm_b : rf_rdata_b_fwd;
///////////////////////
// Register File MUX //
///////////////////////
- // Register file write enable mux - do not propagate illegal CSR ops, do not write when idle,
- // for loads/stores and multdiv operations write when the data is ready only
- assign regfile_we = (illegal_csr_insn_i || !instr_executing) ? 1'b0 :
- (data_req_dec || multdiv_en_dec) ? regfile_we_wb : regfile_we_dec;
+ // Suppress register write if there is an illegal CSR access or instruction is not executing
+ assign rf_we_id_o = rf_we_raw & instr_executing & ~illegal_csr_insn_i;
// Register file write data mux
- always_comb begin : regfile_wdata_mux
- unique case (regfile_wdata_sel)
- RF_WD_EX: regfile_wdata = regfile_wdata_ex_i;
- RF_WD_LSU: regfile_wdata = regfile_wdata_lsu_i;
- RF_WD_CSR: regfile_wdata = csr_rdata_i;
- default: regfile_wdata = regfile_wdata_ex_i;
- endcase
+ always_comb begin : rf_wdata_id_mux
+ unique case (rf_wdata_sel)
+ RF_WD_EX: rf_wdata_id_o = result_ex_i;
+ RF_WD_CSR: rf_wdata_id_o = csr_rdata_i;
+ default: rf_wdata_id_o = result_ex_i;
+ endcase;
end
- ///////////////////
- // Register File //
- ///////////////////
-
- ibex_register_file #( .RV32E ( RV32E ) ) registers_i (
- .clk_i ( clk_i ),
- .rst_ni ( rst_ni ),
-
- .test_en_i ( test_en_i ),
-
- // Read port a
- .raddr_a_i ( regfile_raddr_a ),
- .rdata_a_o ( regfile_rdata_a ),
- // Read port b
- .raddr_b_i ( regfile_raddr_b ),
- .rdata_b_o ( regfile_rdata_b ),
- // write port
- .waddr_a_i ( regfile_waddr ),
- .wdata_a_i ( regfile_wdata ),
- .we_a_i ( regfile_we )
- );
-
-`ifdef RVFI
- assign rfvi_reg_raddr_ra_o = regfile_raddr_a;
- assign rfvi_reg_rdata_ra_o = regfile_rdata_a;
- assign rfvi_reg_raddr_rb_o = regfile_raddr_b;
- assign rfvi_reg_rdata_rb_o = regfile_rdata_b;
- assign rfvi_reg_waddr_rd_o = regfile_waddr;
- assign rfvi_reg_wdata_rd_o = regfile_wdata;
- assign rfvi_reg_we_o = regfile_we;
-`endif
-
/////////////
// Decoder //
/////////////
@@ -324,6 +361,7 @@
ibex_decoder #(
.RV32E ( RV32E ),
.RV32M ( RV32M ),
+ .RV32B ( RV32B ),
.BranchTargetALU ( BranchTargetALU )
) decoder_i (
.clk_i ( clk_i ),
@@ -337,9 +375,10 @@
.ecall_insn_o ( ecall_insn_dec ),
.wfi_insn_o ( wfi_insn_dec ),
.jump_set_o ( jump_set ),
+ .icache_inval_o ( icache_inval_o ),
// from IF-ID pipeline register
- .instr_new_i ( instr_new_i ),
+ .instr_first_cycle_i ( instr_first_cycle ),
.instr_rdata_i ( instr_rdata_i ),
.instr_rdata_alu_i ( instr_rdata_alu_i ),
.illegal_c_insn_i ( illegal_c_insn_i ),
@@ -347,7 +386,8 @@
// immediates
.imm_a_mux_sel_o ( imm_a_mux_sel ),
.imm_b_mux_sel_o ( imm_b_mux_sel_dec ),
- .jt_mux_sel_o ( jt_mux_sel_ex_o ),
+ .bt_a_mux_sel_o ( bt_a_mux_sel ),
+ .bt_b_mux_sel_o ( bt_b_mux_sel ),
.imm_i_type_o ( imm_i_type ),
.imm_s_type_o ( imm_s_type ),
@@ -357,12 +397,14 @@
.zimm_rs1_type_o ( zimm_rs1_type ),
// register file
- .regfile_wdata_sel_o ( regfile_wdata_sel ),
- .regfile_we_o ( regfile_we_dec ),
+ .rf_wdata_sel_o ( rf_wdata_sel ),
+ .rf_we_o ( rf_we_dec ),
- .regfile_raddr_a_o ( regfile_raddr_a ),
- .regfile_raddr_b_o ( regfile_raddr_b ),
- .regfile_waddr_o ( regfile_waddr ),
+ .rf_raddr_a_o ( rf_raddr_a_o ),
+ .rf_raddr_b_o ( rf_raddr_b_o ),
+ .rf_waddr_o ( rf_waddr_id_o ),
+ .rf_ren_a_o ( rf_ren_a ),
+ .rf_ren_b_o ( rf_ren_b ),
// ALU
.alu_operator_o ( alu_operator ),
@@ -379,162 +421,173 @@
// CSRs
.csr_access_o ( csr_access_o ),
.csr_op_o ( csr_op_o ),
- .csr_pipe_flush_o ( csr_pipe_flush ),
// LSU
- .data_req_o ( data_req_dec ),
- .data_we_o ( data_we_id ),
- .data_type_o ( data_type_id ),
- .data_sign_extension_o ( data_sign_ext_id ),
+ .data_req_o ( lsu_req_dec ),
+ .data_we_o ( lsu_we ),
+ .data_type_o ( lsu_type ),
+ .data_sign_extension_o ( lsu_sign_ext ),
// jump/branches
.jump_in_dec_o ( jump_in_dec ),
.branch_in_dec_o ( branch_in_dec )
);
+ /////////////////////////////////
+ // CSR-related pipline flushes //
+ /////////////////////////////////
+ always_comb begin : csr_pipeline_flushes
+ csr_pipe_flush = 1'b0;
+
+ // A pipeline flush is needed to let the controller react after modifying certain CSRs:
+ // - When enabling interrupts, pending IRQs become visible to the controller only during
+ // the next cycle. If during that cycle the core disables interrupts again, it does not
+ // see any pending IRQs and consequently does not start to handle interrupts.
+ // - When modifying debug CSRs - TODO: Check if this is really needed
+ if (csr_op_en_o == 1'b1 && (csr_op_o == CSR_OP_WRITE || csr_op_o == CSR_OP_SET)) begin
+ if (csr_num_e'(instr_rdata_i[31:20]) == CSR_MSTATUS ||
+ csr_num_e'(instr_rdata_i[31:20]) == CSR_MIE) begin
+ csr_pipe_flush = 1'b1;
+ end
+ end else if (csr_op_en_o == 1'b1 && csr_op_o != CSR_OP_READ) begin
+ if (csr_num_e'(instr_rdata_i[31:20]) == CSR_DCSR ||
+ csr_num_e'(instr_rdata_i[31:20]) == CSR_DPC ||
+ csr_num_e'(instr_rdata_i[31:20]) == CSR_DSCRATCH0 ||
+ csr_num_e'(instr_rdata_i[31:20]) == CSR_DSCRATCH1) begin
+ csr_pipe_flush = 1'b1;
+ end
+ end
+ end
+
////////////////
// Controller //
////////////////
assign illegal_insn_o = instr_valid_i & (illegal_insn_dec | illegal_csr_insn_i);
- ibex_controller controller_i (
- .clk_i ( clk_i ),
- .rst_ni ( rst_ni ),
+ ibex_controller #(
+ .WritebackStage ( WritebackStage )
+ ) controller_i (
+ .clk_i ( clk_i ),
+ .rst_ni ( rst_ni ),
- .fetch_enable_i ( fetch_enable_i ),
- .ctrl_busy_o ( ctrl_busy_o ),
+ .fetch_enable_i ( fetch_enable_i ),
+ .ctrl_busy_o ( ctrl_busy_o ),
// decoder related signals
- .illegal_insn_i ( illegal_insn_o ),
- .ecall_insn_i ( ecall_insn_dec ),
- .mret_insn_i ( mret_insn_dec ),
- .dret_insn_i ( dret_insn_dec ),
- .wfi_insn_i ( wfi_insn_dec ),
- .ebrk_insn_i ( ebrk_insn ),
- .csr_pipe_flush_i ( csr_pipe_flush ),
+ .illegal_insn_i ( illegal_insn_o ),
+ .ecall_insn_i ( ecall_insn_dec ),
+ .mret_insn_i ( mret_insn_dec ),
+ .dret_insn_i ( dret_insn_dec ),
+ .wfi_insn_i ( wfi_insn_dec ),
+ .ebrk_insn_i ( ebrk_insn ),
+ .csr_pipe_flush_i ( csr_pipe_flush ),
// from IF-ID pipeline
- .instr_valid_i ( instr_valid_i ),
- .instr_i ( instr_rdata_i ),
- .instr_compressed_i ( instr_rdata_c_i ),
- .instr_is_compressed_i ( instr_is_compressed_i ),
- .instr_fetch_err_i ( instr_fetch_err_i ),
- .pc_id_i ( pc_id_i ),
+ .instr_valid_i ( instr_valid_i ),
+ .instr_i ( instr_rdata_i ),
+ .instr_compressed_i ( instr_rdata_c_i ),
+ .instr_is_compressed_i ( instr_is_compressed_i ),
+ .instr_fetch_err_i ( instr_fetch_err_i ),
+ .instr_fetch_err_plus2_i ( instr_fetch_err_plus2_i ),
+ .pc_id_i ( pc_id_i ),
// to IF-ID pipeline
- .instr_valid_clear_o ( instr_valid_clear_o ),
- .id_in_ready_o ( id_in_ready_o ),
+ .instr_valid_clear_o ( instr_valid_clear_o ),
+ .id_in_ready_o ( id_in_ready_o ),
+ .controller_run_o ( controller_run ),
// to prefetcher
- .instr_req_o ( instr_req_o ),
- .pc_set_o ( pc_set_o ),
- .pc_mux_o ( pc_mux_o ),
- .exc_pc_mux_o ( exc_pc_mux_o ),
- .exc_cause_o ( exc_cause_o ),
+ .instr_req_o ( instr_req_o ),
+ .pc_set_o ( pc_set_o ),
+ .pc_mux_o ( pc_mux_o ),
+ .exc_pc_mux_o ( exc_pc_mux_o ),
+ .exc_cause_o ( exc_cause_o ),
// LSU
- .lsu_addr_last_i ( lsu_addr_last_i ),
- .load_err_i ( lsu_load_err_i ),
- .store_err_i ( lsu_store_err_i ),
+ .lsu_addr_last_i ( lsu_addr_last_i ),
+ .load_err_i ( lsu_load_err_i ),
+ .store_err_i ( lsu_store_err_i ),
+ .wb_exception_o ( wb_exception ),
// jump/branch control
- .branch_set_i ( branch_set ),
- .jump_set_i ( jump_set ),
+ .branch_set_i ( branch_set ),
+ .jump_set_i ( jump_set ),
// interrupt signals
- .csr_mstatus_mie_i ( csr_mstatus_mie_i ),
- .irq_pending_i ( irq_pending_i ),
- .irqs_i ( irqs_i ),
- .irq_nm_i ( irq_nm_i ),
- .nmi_mode_o ( nmi_mode_o ),
+ .csr_mstatus_mie_i ( csr_mstatus_mie_i ),
+ .irq_pending_i ( irq_pending_i ),
+ .irqs_i ( irqs_i ),
+ .irq_nm_i ( irq_nm_i ),
+ .nmi_mode_o ( nmi_mode_o ),
// CSR Controller Signals
- .csr_save_if_o ( csr_save_if_o ),
- .csr_save_id_o ( csr_save_id_o ),
- .csr_restore_mret_id_o ( csr_restore_mret_id_o ),
- .csr_restore_dret_id_o ( csr_restore_dret_id_o ),
- .csr_save_cause_o ( csr_save_cause_o ),
- .csr_mtval_o ( csr_mtval_o ),
- .priv_mode_i ( priv_mode_i ),
- .csr_mstatus_tw_i ( csr_mstatus_tw_i ),
+ .csr_save_if_o ( csr_save_if_o ),
+ .csr_save_id_o ( csr_save_id_o ),
+ .csr_save_wb_o ( csr_save_wb_o ),
+ .csr_restore_mret_id_o ( csr_restore_mret_id_o ),
+ .csr_restore_dret_id_o ( csr_restore_dret_id_o ),
+ .csr_save_cause_o ( csr_save_cause_o ),
+ .csr_mtval_o ( csr_mtval_o ),
+ .priv_mode_i ( priv_mode_i ),
+ .csr_mstatus_tw_i ( csr_mstatus_tw_i ),
// Debug Signal
- .debug_mode_o ( debug_mode_o ),
- .debug_cause_o ( debug_cause_o ),
- .debug_csr_save_o ( debug_csr_save_o ),
- .debug_req_i ( debug_req_i ),
- .debug_single_step_i ( debug_single_step_i ),
- .debug_ebreakm_i ( debug_ebreakm_i ),
- .debug_ebreaku_i ( debug_ebreaku_i ),
- .trigger_match_i ( trigger_match_i ),
+ .debug_mode_o ( debug_mode_o ),
+ .debug_cause_o ( debug_cause_o ),
+ .debug_csr_save_o ( debug_csr_save_o ),
+ .debug_req_i ( debug_req_i ),
+ .debug_single_step_i ( debug_single_step_i ),
+ .debug_ebreakm_i ( debug_ebreakm_i ),
+ .debug_ebreaku_i ( debug_ebreaku_i ),
+ .trigger_match_i ( trigger_match_i ),
// stall signals
- .stall_lsu_i ( stall_lsu ),
- .stall_multdiv_i ( stall_multdiv ),
- .stall_jump_i ( stall_jump ),
- .stall_branch_i ( stall_branch ),
+ .stall_id_i ( stall_id ),
+ .stall_wb_i ( stall_wb ),
+ .flush_id_o ( flush_id ),
// Performance Counters
- .perf_jump_o ( perf_jump_o ),
- .perf_tbranch_o ( perf_tbranch_o )
+ .perf_jump_o ( perf_jump_o ),
+ .perf_tbranch_o ( perf_tbranch_o )
);
- //////////////
- // ID-EX/WB //
- //////////////
-
assign multdiv_en_dec = mult_en_dec | div_en_dec;
- assign instr_multicycle = data_req_dec | multdiv_en_dec | branch_in_dec | jump_in_dec;
- // Forward decoder output to EX, WB and controller only if current instr is still
- // being executed. This is the case if the current instr is either:
- // - a new instr (not yet done)
- // - a multicycle instr that is not yet done
- // An instruction error will suppress any requests or register writes
- assign instr_executing = (instr_new_i | (instr_multicycle & ~instr_multicycle_done_q)) &
- ~instr_fetch_err_i;
- assign data_req_id = instr_executing ? data_req_dec : 1'b0;
- assign mult_en_id = instr_executing ? mult_en_dec : 1'b0;
- assign div_en_id = instr_executing ? div_en_dec : 1'b0;
+ assign lsu_req = instr_executing ? data_req_allowed & lsu_req_dec : 1'b0;
+ assign mult_en_id = instr_executing ? mult_en_dec : 1'b0;
+ assign div_en_id = instr_executing ? div_en_dec : 1'b0;
- ///////////
- // ID-EX //
- ///////////
-
- assign data_req_ex_o = data_req_id;
- assign data_we_ex_o = data_we_id;
- assign data_type_ex_o = data_type_id;
- assign data_sign_ext_ex_o = data_sign_ext_id;
- assign data_wdata_ex_o = regfile_rdata_b;
+ assign lsu_req_o = lsu_req;
+ assign lsu_we_o = lsu_we;
+ assign lsu_type_o = lsu_type;
+ assign lsu_sign_ext_o = lsu_sign_ext;
+ assign lsu_wdata_o = rf_rdata_b_fwd;
+ // csr_op_en_o is set when CSR access should actually happen.
+ // csv_access_o is set when CSR access instruction is present and is used to compute whether a CSR
+ // access is illegal. A combinational loop would be created if csr_op_en_o was used along (as
+ // asserting it for an illegal csr access would result in a flush that would need to deassert it).
+ assign csr_op_en_o = csr_access_o & instr_executing & instr_id_done_o;
assign alu_operator_ex_o = alu_operator;
assign alu_operand_a_ex_o = alu_operand_a;
assign alu_operand_b_ex_o = alu_operand_b;
- if (BranchTargetALU) begin : g_bt_operand_imm
- // Branch target ALU sign-extends and inserts bottom 0 bit so only want the
- // 'raw' B-type immediate bits.
- assign bt_operand_imm_o = imm_b_type[12:1];
- end else begin : g_no_bt_operand_imm
- assign bt_operand_imm_o = '0;
- end
-
assign mult_en_ex_o = mult_en_id;
assign div_en_ex_o = div_en_id;
assign multdiv_sel_ex_o = multdiv_sel_dec;
assign multdiv_operator_ex_o = multdiv_operator;
assign multdiv_signed_mode_ex_o = multdiv_signed_mode;
- assign multdiv_operand_a_ex_o = regfile_rdata_a;
- assign multdiv_operand_b_ex_o = regfile_rdata_b;
+ assign multdiv_operand_a_ex_o = rf_rdata_a_fwd;
+ assign multdiv_operand_b_ex_o = rf_rdata_b_fwd;
- typedef enum logic { IDLE, WAIT_MULTICYCLE } id_fsm_e;
- id_fsm_e id_wb_fsm_cs, id_wb_fsm_ns;
+ typedef enum logic { FIRST_CYCLE, MULTI_CYCLE } id_fsm_e;
+ id_fsm_e id_fsm_q, id_fsm_d;
- ////////////////////////////////
- // ID-EX/WB Pipeline Register //
- ////////////////////////////////
+ /////////////////////////////
+ // ID-EX Pipeline Register //
+ /////////////////////////////
if (BranchTargetALU) begin : g_branch_set_direct
// Branch set fed straight to controller with branch target ALU
@@ -556,130 +609,342 @@
assign branch_set = branch_set_q;
end
- always_ff @(posedge clk_i or negedge rst_ni) begin : id_wb_pipeline_reg
+ // Holding branch_set/jump_set high for more than one cycle may not cause a functional issue but
+ // could generate needless prefetch buffer flushes and instruction fetches. ID/EX is designed such
+ // that this shouldn't ever happen.
+ `ASSERT(NeverDoubleBranch, branch_set |=> ~branch_set)
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin : id_pipeline_reg
if (!rst_ni) begin
- id_wb_fsm_cs <= IDLE;
- instr_multicycle_done_q <= 1'b0;
+ id_fsm_q <= FIRST_CYCLE;
end else begin
- id_wb_fsm_cs <= id_wb_fsm_ns;
- instr_multicycle_done_q <= instr_multicycle_done_n;
+ id_fsm_q <= id_fsm_d;
end
end
- //////////////////
- // ID-EX/WB FSM //
- //////////////////
+ ///////////////
+ // ID-EX FSM //
+ ///////////////
- always_comb begin : id_wb_fsm
- id_wb_fsm_ns = id_wb_fsm_cs;
- instr_multicycle_done_n = instr_multicycle_done_q;
- regfile_we_wb = 1'b0;
- stall_lsu = 1'b0;
+ // ID/EX stage can be in two states, FIRST_CYCLE and MULTI_CYCLE. An instruction enters
+ // MULTI_CYCLE if it requires multiple cycles to complete regardless of stalls and other
+ // considerations. An instruction may be held in FIRST_CYCLE if it's unable to begin executing
+ // (this is controlled by instr_executing).
+
+ always_comb begin
+ id_fsm_d = id_fsm_q;
+ rf_we_raw = rf_we_dec;
stall_multdiv = 1'b0;
stall_jump = 1'b0;
stall_branch = 1'b0;
branch_set_d = 1'b0;
perf_branch_o = 1'b0;
- instr_ret_o = 1'b0;
- unique case (id_wb_fsm_cs)
-
- IDLE: begin
- // only detect multicycle when instruction is new, do not re-detect after
- // execution (when waiting for next instruction from IF stage)
- if (instr_new_i & ~instr_fetch_err_i) begin
+ if (instr_executing) begin
+ unique case (id_fsm_q)
+ FIRST_CYCLE: begin
unique case (1'b1)
- data_req_dec: begin
- // LSU operation
- id_wb_fsm_ns = WAIT_MULTICYCLE;
- stall_lsu = 1'b1;
- instr_multicycle_done_n = 1'b0;
+ lsu_req_dec: begin
+ if (!WritebackStage) begin
+ // LSU operation
+ id_fsm_d = MULTI_CYCLE;
+ end else begin
+ if(~lsu_req_done_i) begin
+ id_fsm_d = MULTI_CYCLE;
+ end
+ end
end
multdiv_en_dec: begin
// MUL or DIV operation
- id_wb_fsm_ns = WAIT_MULTICYCLE;
- stall_multdiv = 1'b1;
- instr_multicycle_done_n = 1'b0;
+ if (~ex_valid_i) begin
+ // When single-cycle multiply is configured mul can finish in the first cycle so
+ // only enter MULTI_CYCLE state if a result isn't immediately available
+ id_fsm_d = MULTI_CYCLE;
+ rf_we_raw = 1'b0;
+ stall_multdiv = 1'b1;
+ end
end
branch_in_dec: begin
// cond branch operation
- id_wb_fsm_ns = branch_decision_i ? WAIT_MULTICYCLE : IDLE;
- stall_branch = branch_decision_i;
- instr_multicycle_done_n = ~branch_decision_i;
- branch_set_d = branch_decision_i;
- perf_branch_o = 1'b1;
- instr_ret_o = ~branch_decision_i;
+ id_fsm_d = (!BranchTargetALU && branch_decision_i) ? MULTI_CYCLE : FIRST_CYCLE;
+ stall_branch = ~BranchTargetALU & branch_decision_i;
+ branch_set_d = branch_decision_i;
+ perf_branch_o = 1'b1;
end
jump_in_dec: begin
// uncond branch operation
- id_wb_fsm_ns = WAIT_MULTICYCLE;
- stall_jump = 1'b1;
- instr_multicycle_done_n = 1'b0;
+ // BTALU means jumps only need one cycle
+ id_fsm_d = BranchTargetALU ? FIRST_CYCLE : MULTI_CYCLE;
+ stall_jump = ~BranchTargetALU;
end
default: begin
- instr_multicycle_done_n = 1'b0;
- instr_ret_o = 1'b1;
+ id_fsm_d = FIRST_CYCLE;
end
endcase
end
- end
- WAIT_MULTICYCLE: begin
- if ((data_req_dec & lsu_valid_i) | (~data_req_dec & ex_valid_i)) begin
- id_wb_fsm_ns = IDLE;
- instr_multicycle_done_n = 1'b1;
- regfile_we_wb = regfile_we_dec & ~lsu_load_err_i;
- instr_ret_o = 1'b1;
- end else begin
- stall_lsu = data_req_dec;
- stall_multdiv = multdiv_en_dec;
- stall_branch = branch_in_dec;
- stall_jump = jump_in_dec;
+ MULTI_CYCLE: begin
+ if(multdiv_en_dec) begin
+ rf_we_raw = rf_we_dec & ex_valid_i;
+ end
+
+ if (multicycle_done & ready_wb_i) begin
+ id_fsm_d = FIRST_CYCLE;
+ end else begin
+ stall_multdiv = multdiv_en_dec;
+ stall_branch = branch_in_dec;
+ stall_jump = jump_in_dec;
+ end
end
- end
- default: begin
- id_wb_fsm_ns = IDLE;
- end
- endcase
+ default: begin
+ id_fsm_d = FIRST_CYCLE;
+ end
+ endcase
+ end
end
- assign instr_ret_compressed_o = instr_ret_o & instr_is_compressed_i;
+ // Note for the two-stage configuration ready_wb_i is always set
+ assign multdiv_ready_id_o = ready_wb_i;
+
+ `ASSERT(StallIDIfMulticycle, (id_fsm_q == FIRST_CYCLE) & (id_fsm_d == MULTI_CYCLE) |-> stall_id)
+
+ // Stall ID/EX stage for reason that relates to instruction in ID/EX
+ assign stall_id = stall_ld_hz | stall_mem | stall_multdiv | stall_jump | stall_branch;
+
+ assign instr_done = ~stall_id & ~flush_id & instr_executing;
+
+ if (WritebackStage) begin
+ assign multicycle_done = lsu_req_dec ? ~stall_mem : ex_valid_i;
+ end else begin
+ assign multicycle_done = lsu_req_dec ? lsu_valid_i : ex_valid_i;
+ end
+
+ // Signal instruction in ID is in it's first cycle. It can remain in its
+ // first cycle if it is stalled.
+ assign instr_first_cycle = instr_valid_i & (id_fsm_q == FIRST_CYCLE);
+ // Used by RVFI to know when to capture register read data
+ assign instr_first_cycle_id_o = instr_first_cycle;
+
+ if (WritebackStage) begin : gen_stall_mem
+ logic unused_lsu_busy;
+
+ // Register read address matches write address in WB
+ logic rf_rd_a_wb_match;
+ logic rf_rd_b_wb_match;
+ // Hazard between registers being read and written
+ logic rf_rd_a_hz;
+ logic rf_rd_b_hz;
+
+ logic data_req_complete_d;
+ logic data_req_complete_q;
+
+ logic outstanding_memory_access;
+
+ logic instr_kill;
+
+ assign unused_lsu_busy = lsu_busy_i;
+
+ assign data_req_complete_d =
+ (data_req_complete_q | (lsu_req & lsu_req_done_i)) & ~instr_id_done_o;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (~rst_ni) begin
+ data_req_complete_q <= 1'b0;
+ end else begin
+ data_req_complete_q <= data_req_complete_d;
+ end
+ end
+
+ // Is a memory access ongoing that isn't finishing this cycle
+ assign outstanding_memory_access = (outstanding_load_wb_i | outstanding_store_wb_i) &
+ ~lsu_valid_i;
+
+ // Can start a new memory access if any previous one has finished or is finishing
+ // Don't start a new memory access if this instruction has already done it's request
+ assign data_req_allowed = ~outstanding_memory_access & ~data_req_complete_q;
+
+ // Instruction won't execute because:
+ // - There is a pending exception in writeback
+ // The instruction in ID/EX will be flushed and the core will jump to an exception handler
+ // - The controller isn't running instructions
+ // This either happens in preparation for a flush and jump to an exception handler e.g. in
+ // response to an IRQ or debug request or whilst the core is sleeping or resetting/fetching
+ // first instruction in which case any valid instruction in ID/EX should be ignored.
+ // - There was an error on instruction fetch
+ assign instr_kill = instr_fetch_err_i |
+ wb_exception |
+ ~controller_run;
+
+ // With writeback stage instructions must be prevented from executing if there is:
+ // - A load hazard
+ // - A pending memory access
+ // If it receives an error response this results in a precise exception from WB so ID/EX
+ // instruction must not execute until error response is known).
+ // - A load/store error
+ // This will cause a precise exception for the instruction in WB so ID/EX instruction must not
+ // execute
+ assign instr_executing = instr_valid_i &
+ ~instr_kill &
+ ~stall_ld_hz &
+ ~outstanding_memory_access;
+
+ `ASSERT(IbexStallIfValidInstrNotExecuting,
+ instr_valid_i & ~instr_kill & ~instr_executing |-> stall_id)
+
+ // Stall for reasons related to memory:
+ // * Requested by LSU (load/store in ID/EX needs to be held in ID/EX whilst a data request or
+ // granted or the second half of a misaligned access is sent out)
+ // * LSU access required but data requests aren't currently allowed
+ // * There is an outstanding memory access that won't resolve this cycle (need to wait to allow
+ // precise exceptions)
+ assign stall_mem = instr_valid_i & ((lsu_req_dec & (~data_req_allowed | (~data_req_complete_q & ~lsu_req_done_i))) | outstanding_memory_access);
+
+ assign rf_rd_a_wb_match = (rf_waddr_wb_i == rf_raddr_a_o) & |rf_raddr_a_o;
+ assign rf_rd_b_wb_match = (rf_waddr_wb_i == rf_raddr_b_o) & |rf_raddr_b_o;
+
+ // If instruction is reading register that load will be writing stall in
+ // ID until load is complete. No need to stall when reading zero register.
+ assign rf_rd_a_hz = rf_rd_a_wb_match & rf_ren_a;
+ assign rf_rd_b_hz = rf_rd_b_wb_match & rf_ren_b;
+
+ // If instruction is read register that writeback is writing forward writeback data to read
+ // data. Note this doesn't factor in load data as it arrives too late, such hazards are
+ // resolved via a stall (see above).
+ assign rf_rdata_a_fwd = rf_rd_a_wb_match & rf_write_wb_i ? rf_wdata_fwd_wb_i : rf_rdata_a_i;
+ assign rf_rdata_b_fwd = rf_rd_b_wb_match & rf_write_wb_i ? rf_wdata_fwd_wb_i : rf_rdata_b_i;
+
+ assign stall_ld_hz = outstanding_load_wb_i & lsu_load_i & (rf_rd_a_hz | rf_rd_b_hz) & rf_write_wb_i;
+
+ assign instr_type_wb_o = ~lsu_req_dec ? WB_INSTR_OTHER :
+ lsu_we ? WB_INSTR_STORE :
+ WB_INSTR_LOAD;
+
+ assign en_wb_o = instr_done;
+
+ assign instr_id_done_o = en_wb_o & ready_wb_i;
+
+ // Stall ID/EX as instruction in ID/EX cannot proceed to writeback yet
+ assign stall_wb = en_wb_o & ~ready_wb_i;
+
+ assign perf_dside_wait_o = instr_valid_i & ~instr_kill & (outstanding_memory_access | stall_ld_hz);
+ end else begin
+
+ assign data_req_allowed = instr_first_cycle;
+
+ // Without Writeback Stage always stall the first cycle of a load/store.
+ // Then stall until it is complete
+ assign stall_mem = instr_valid_i & (lsu_busy_i | (lsu_req_dec & (~lsu_valid_i | instr_first_cycle)));
+
+ // No load hazards without Writeback Stage
+ assign stall_ld_hz = 1'b0;
+
+ // Without writeback stage any valid instruction that hasn't seen an error will execute
+ assign instr_executing = instr_valid_i & ~instr_fetch_err_i & controller_run;
+
+ `ASSERT(IbexStallIfValidInstrNotExecuting,
+ instr_valid_i & ~instr_fetch_err_i & ~instr_executing & controller_run |-> stall_id)
+
+ // No data forwarding without writeback stage so always take source register data direct from
+ // register file
+ assign rf_rdata_a_fwd = rf_rdata_a_i;
+ assign rf_rdata_b_fwd = rf_rdata_b_i;
+
+ // Unused Writeback stage only IO & wiring
+ // Assign inputs and internal wiring to unused signals to satisfy lint checks
+ // Tie-off outputs to constant values
+ logic unused_data_req_done_ex;
+ logic unused_lsu_load;
+ logic [4:0] unused_rf_waddr_wb;
+ logic unused_rf_write_wb;
+ logic unused_outstanding_load_wb;
+ logic unused_outstanding_store_wb;
+ logic unused_wb_exception;
+ logic unused_rf_ren_a, unused_rf_ren_b;
+ logic [31:0] unused_rf_wdata_fwd_wb;
+
+ assign unused_data_req_done_ex = lsu_req_done_i;
+ assign unused_lsu_load = lsu_load_i;
+ assign unused_rf_waddr_wb = rf_waddr_wb_i;
+ assign unused_rf_write_wb = rf_write_wb_i;
+ assign unused_outstanding_load_wb = outstanding_load_wb_i;
+ assign unused_outstanding_store_wb = outstanding_store_wb_i;
+ assign unused_wb_exception = wb_exception;
+ assign unused_rf_ren_a = rf_ren_a;
+ assign unused_rf_ren_b = rf_ren_b;
+ assign unused_rf_wdata_fwd_wb = rf_wdata_fwd_wb_i;
+
+ assign instr_type_wb_o = WB_INSTR_OTHER;
+ assign stall_wb = 1'b0;
+
+ assign perf_dside_wait_o = instr_executing & lsu_req_dec & ~lsu_valid_i;
+
+ assign en_wb_o = 1'b0;
+ assign instr_id_done_o = instr_done;
+ end
+
+ assign perf_mul_wait_o = stall_multdiv & mult_en_dec;
+ assign perf_div_wait_o = stall_multdiv & div_en_dec;
+
+ assign instr_id_done_compressed_o = instr_id_done_o & instr_is_compressed_i;
////////////////
// Assertions //
////////////////
// Selectors must be known/valid.
- `ASSERT_KNOWN(IbexAluOpMuxSelKnown, alu_op_a_mux_sel, clk_i, !rst_ni)
- `ASSERT(IbexImmBMuxSelValid, imm_b_mux_sel inside {
+ `ASSERT_KNOWN_IF(IbexAluOpMuxSelKnown, alu_op_a_mux_sel, instr_valid_i)
+ `ASSERT(IbexAluAOpMuxSelValid, instr_valid_i |-> alu_op_a_mux_sel inside {
+ OP_A_REG_A,
+ OP_A_FWD,
+ OP_A_CURRPC,
+ OP_A_IMM})
+ if (BranchTargetALU) begin : g_btalu_assertions
+ `ASSERT(IbexImmBMuxSelValid, instr_valid_i |-> imm_b_mux_sel inside {
+ IMM_B_I,
+ IMM_B_S,
+ IMM_B_U,
+ IMM_B_INCR_PC,
+ IMM_B_INCR_ADDR})
+ end else begin : g_nobtalu_assertions
+ `ASSERT(IbexImmBMuxSelValid, instr_valid_i |-> imm_b_mux_sel inside {
+ IMM_B_I,
+ IMM_B_S,
+ IMM_B_B,
+ IMM_B_U,
+ IMM_B_J,
+ IMM_B_INCR_PC,
+ IMM_B_INCR_ADDR})
+ end
+ `ASSERT_KNOWN_IF(IbexBTAluAOpMuxSelKnown, bt_a_mux_sel, instr_valid_i)
+ `ASSERT(IbexBTAluAOpMuxSelValid, instr_valid_i |-> bt_a_mux_sel inside {
+ OP_A_REG_A,
+ OP_A_CURRPC})
+ `ASSERT_KNOWN_IF(IbexBTAluBOpMuxSelKnown, bt_b_mux_sel, instr_valid_i)
+ `ASSERT(IbexBTAluBOpMuxSelValid, instr_valid_i |-> bt_b_mux_sel inside {
IMM_B_I,
- IMM_B_S,
IMM_B_B,
- IMM_B_U,
IMM_B_J,
- IMM_B_INCR_PC,
- IMM_B_INCR_ADDR})
- `ASSERT(IbexRegfileWdataSelValid, regfile_wdata_sel inside {
- RF_WD_LSU,
+ IMM_B_INCR_PC})
+ `ASSERT(IbexRegfileWdataSelValid, instr_valid_i |-> rf_wdata_sel inside {
RF_WD_EX,
RF_WD_CSR})
- `ASSERT_KNOWN(IbexWbStateKnown, id_wb_fsm_cs)
+ `ASSERT_KNOWN(IbexWbStateKnown, id_fsm_q)
// Branch decision must be valid when jumping.
- `ASSERT(IbexBranchDecisionValid, branch_in_dec |-> !$isunknown(branch_decision_i))
+ `ASSERT_KNOWN_IF(IbexBranchDecisionValid, branch_decision_i, instr_valid_i)
// Instruction delivered to ID stage can not contain X.
- `ASSERT(IbexIdInstrKnown,
- (instr_valid_i && !(illegal_c_insn_i || instr_fetch_err_i)) |-> !$isunknown(instr_rdata_i))
+ `ASSERT_KNOWN_IF(IbexIdInstrKnown, instr_rdata_i,
+ instr_valid_i && !(illegal_c_insn_i || instr_fetch_err_i))
// Instruction delivered to ID stage can not contain X.
- `ASSERT(IbexIdInstrALUKnown,
- (instr_valid_i && !(illegal_c_insn_i || instr_fetch_err_i)) |-> !$isunknown(instr_rdata_alu_i))
+ `ASSERT_KNOWN_IF(IbexIdInstrALUKnown, instr_rdata_alu_i,
+ instr_valid_i && !(illegal_c_insn_i || instr_fetch_err_i))
// Multicycle enable signals must be unique.
`ASSERT(IbexMulticycleEnableUnique,
- $onehot0({data_req_dec, multdiv_en_dec, branch_in_dec, jump_in_dec}))
+ $onehot0({lsu_req_dec, multdiv_en_dec, branch_in_dec, jump_in_dec}))
// Duplicated instruction flops must match
// === as DV environment can produce instructions with Xs in, so must use precise match that
diff --git a/hw/vendor/lowrisc_ibex/rtl/ibex_if_stage.sv b/hw/vendor/lowrisc_ibex/rtl/ibex_if_stage.sv
index 7510f9f..fa7a76a 100644
--- a/hw/vendor/lowrisc_ibex/rtl/ibex_if_stage.sv
+++ b/hw/vendor/lowrisc_ibex/rtl/ibex_if_stage.sv
@@ -13,8 +13,10 @@
`include "prim_assert.sv"
module ibex_if_stage #(
- parameter int unsigned DmHaltAddr = 32'h1A110800,
- parameter int unsigned DmExceptionAddr = 32'h1A110808
+ parameter int unsigned DmHaltAddr = 32'h1A110800,
+ parameter int unsigned DmExceptionAddr = 32'h1A110808,
+ parameter bit ICache = 1'b0,
+ parameter bit ICacheECC = 1'b0
) (
input logic clk_i,
input logic rst_ni,
@@ -43,6 +45,7 @@
output logic instr_is_compressed_id_o, // compressed decoder thinks this
// is a compressed instr
output logic instr_fetch_err_o, // bus error on fetch
+ output logic instr_fetch_err_plus2_o, // bus error misaligned
output logic illegal_c_insn_id_o, // compressed decoder thinks this
// is an invalid instr
output logic [31:0] pc_if_o,
@@ -55,8 +58,11 @@
input ibex_pkg::exc_pc_sel_e exc_pc_mux_i, // selects ISR address
input ibex_pkg::exc_cause_e exc_cause, // selects ISR address for
// vectorized interrupt lines
+ input logic icache_enable_i,
+ input logic icache_inval_i,
+
// jump and branch target
- input logic [31:0] jump_target_ex_i, // jump target address
+ input logic [31:0] branch_target_ex_i, // branch/jump target address
// CSRs
input logic [31:0] csr_mepc_i, // PC to restore after handling
@@ -70,14 +76,13 @@
input logic id_in_ready_i, // ID stage is ready for new instr
// misc signals
- output logic if_busy_o, // IF stage is busy fetching instr
- output logic perf_imiss_o // instr fetch miss
+ output logic if_busy_o // IF stage is busy fetching instr
);
import ibex_pkg::*;
- logic offset_in_init_d, offset_in_init_q;
- logic have_instr;
+ logic instr_valid_id_d, instr_valid_id_q;
+ logic instr_new_id_d, instr_new_id_q;
// prefetch buffer related signals
logic prefetch_busy;
@@ -89,6 +94,7 @@
logic [31:0] fetch_rdata;
logic [31:0] fetch_addr;
logic fetch_err;
+ logic fetch_err_plus2;
logic [31:0] exc_pc;
@@ -122,7 +128,7 @@
always_comb begin : fetch_addr_mux
unique case (pc_mux_i)
PC_BOOT: fetch_addr_n = { boot_addr_i[31:8], 8'h80 };
- PC_JUMP: fetch_addr_n = jump_target_ex_i;
+ PC_JUMP: fetch_addr_n = branch_target_ex_i;
PC_EXC: fetch_addr_n = exc_pc; // set PC to exception handler
PC_ERET: fetch_addr_n = csr_mepc_i; // restore PC when returning from EXC
PC_DRET: fetch_addr_n = csr_depc_i;
@@ -133,81 +139,77 @@
// tell CS register file to initialize mtvec on boot
assign csr_mtvec_init_o = (pc_mux_i == PC_BOOT) & pc_set_i;
- // prefetch buffer, caches a fixed number of instructions
- ibex_prefetch_buffer prefetch_buffer_i (
- .clk_i ( clk_i ),
- .rst_ni ( rst_ni ),
+ if (ICache) begin : gen_icache
+ // Full I-Cache option
+ ibex_icache #(
+ .ICacheECC (ICacheECC)
+ ) icache_i (
+ .clk_i ( clk_i ),
+ .rst_ni ( rst_ni ),
- .req_i ( req_i ),
+ .req_i ( req_i ),
- .branch_i ( branch_req ),
- .addr_i ( {fetch_addr_n[31:1], 1'b0} ),
+ .branch_i ( branch_req ),
+ .addr_i ( {fetch_addr_n[31:1], 1'b0} ),
- .ready_i ( fetch_ready ),
- .valid_o ( fetch_valid ),
- .rdata_o ( fetch_rdata ),
- .addr_o ( fetch_addr ),
- .err_o ( fetch_err ),
+ .ready_i ( fetch_ready ),
+ .valid_o ( fetch_valid ),
+ .rdata_o ( fetch_rdata ),
+ .addr_o ( fetch_addr ),
+ .err_o ( fetch_err ),
+ .err_plus2_o ( fetch_err_plus2 ),
- // goes to instruction memory / instruction cache
- .instr_req_o ( instr_req_o ),
- .instr_addr_o ( instr_addr_o ),
- .instr_gnt_i ( instr_gnt_i ),
- .instr_rvalid_i ( instr_rvalid_i ),
- .instr_rdata_i ( instr_rdata_i ),
- .instr_err_i ( instr_err_i ),
- .instr_pmp_err_i ( instr_pmp_err_i ),
+ .instr_req_o ( instr_req_o ),
+ .instr_addr_o ( instr_addr_o ),
+ .instr_gnt_i ( instr_gnt_i ),
+ .instr_rvalid_i ( instr_rvalid_i ),
+ .instr_rdata_i ( instr_rdata_i ),
+ .instr_err_i ( instr_err_i ),
+ .instr_pmp_err_i ( instr_pmp_err_i ),
- // Prefetch Buffer Status
- .busy_o ( prefetch_busy )
- );
+ .icache_enable_i ( icache_enable_i ),
+ .icache_inval_i ( icache_inval_i ),
+ .busy_o ( prefetch_busy )
+ );
+ end else begin : gen_prefetch_buffer
+ // prefetch buffer, caches a fixed number of instructions
+ ibex_prefetch_buffer prefetch_buffer_i (
+ .clk_i ( clk_i ),
+ .rst_ni ( rst_ni ),
+ .req_i ( req_i ),
- // offset initialization state
- always_ff @(posedge clk_i or negedge rst_ni) begin
- if (!rst_ni) begin
- offset_in_init_q <= 1'b1;
- end else begin
- offset_in_init_q <= offset_in_init_d;
- end
+ .branch_i ( branch_req ),
+ .addr_i ( {fetch_addr_n[31:1], 1'b0} ),
+
+ .ready_i ( fetch_ready ),
+ .valid_o ( fetch_valid ),
+ .rdata_o ( fetch_rdata ),
+ .addr_o ( fetch_addr ),
+ .err_o ( fetch_err ),
+ .err_plus2_o ( fetch_err_plus2 ),
+
+ .instr_req_o ( instr_req_o ),
+ .instr_addr_o ( instr_addr_o ),
+ .instr_gnt_i ( instr_gnt_i ),
+ .instr_rvalid_i ( instr_rvalid_i ),
+ .instr_rdata_i ( instr_rdata_i ),
+ .instr_err_i ( instr_err_i ),
+ .instr_pmp_err_i ( instr_pmp_err_i ),
+
+ .busy_o ( prefetch_busy )
+ );
+ // ICache tieoffs
+ logic unused_icen, unused_icinv;
+ assign unused_icen = icache_enable_i;
+ assign unused_icinv = icache_inval_i;
end
- // offset initialization related transition logic
- always_comb begin
- offset_in_init_d = offset_in_init_q;
+ assign branch_req = pc_set_i;
+ assign fetch_ready = id_in_ready_i;
- fetch_ready = 1'b0;
- branch_req = 1'b0;
-
- if (offset_in_init_q) begin
- // no valid instruction data for ID stage, assume aligned
- if (req_i) begin
- branch_req = 1'b1;
- offset_in_init_d = 1'b0;
- end
- end else begin
- // an instruction is ready for ID stage
- if (fetch_valid) begin
- if (req_i && if_id_pipe_reg_we) begin
- fetch_ready = 1'b1;
- offset_in_init_d = 1'b0;
- end
- end
- end
-
- // take care of jumps and branches
- if (pc_set_i) begin
- // switch to new PC from ID stage
- branch_req = 1'b1;
- offset_in_init_d = 1'b0;
- end
- end
-
- assign have_instr = fetch_valid & ~ (offset_in_init_q | pc_set_i);
-
- assign pc_if_o = fetch_addr;
- assign if_busy_o = prefetch_busy;
- assign perf_imiss_o = ~fetch_valid | branch_req;
+ assign pc_if_o = fetch_addr;
+ assign if_busy_o = prefetch_busy;
// compressed instruction decoding, or more precisely compressed instruction
// expander
@@ -228,35 +230,41 @@
.illegal_instr_o ( illegal_c_insn )
);
- // IF-ID pipeline registers, frozen when the ID stage is stalled
- assign if_id_pipe_reg_we = have_instr & id_in_ready_i;
+ // The ID stage becomes valid as soon as any instruction is registered in the ID stage flops.
+ // Note that the current instruction is squashed by the incoming pc_set_i signal.
+ // Valid is held until it is explicitly cleared (due to an instruction completing or an exception)
+ assign instr_valid_id_d = (fetch_valid & id_in_ready_i & ~pc_set_i) |
+ (instr_valid_id_q & ~instr_valid_clear_i);
+ assign instr_new_id_d = fetch_valid & id_in_ready_i;
- always_ff @(posedge clk_i or negedge rst_ni) begin : if_id_pipeline_regs
+ always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
- instr_new_id_o <= 1'b0;
- instr_valid_id_o <= 1'b0;
- instr_rdata_id_o <= '0;
- instr_rdata_alu_id_o <= '0;
- instr_fetch_err_o <= '0;
- instr_rdata_c_id_o <= '0;
- instr_is_compressed_id_o <= 1'b0;
- illegal_c_insn_id_o <= 1'b0;
- pc_id_o <= '0;
+ instr_valid_id_q <= 1'b0;
+ instr_new_id_q <= 1'b0;
end else begin
- instr_new_id_o <= if_id_pipe_reg_we;
- if (if_id_pipe_reg_we) begin
- instr_valid_id_o <= 1'b1;
- instr_rdata_id_o <= instr_decompressed;
- // To reduce fan-out and help timing from the instr_rdata_id flops they are replicated.
- instr_rdata_alu_id_o <= instr_decompressed;
- instr_fetch_err_o <= fetch_err;
- instr_rdata_c_id_o <= fetch_rdata[15:0];
- instr_is_compressed_id_o <= instr_is_compressed_int;
- illegal_c_insn_id_o <= illegal_c_insn;
- pc_id_o <= pc_if_o;
- end else if (instr_valid_clear_i) begin
- instr_valid_id_o <= 1'b0;
- end
+ instr_valid_id_q <= instr_valid_id_d;
+ instr_new_id_q <= instr_new_id_d;
+ end
+ end
+
+ assign instr_valid_id_o = instr_valid_id_q;
+ // Signal when a new instruction enters the ID stage (only used for RVFI signalling).
+ assign instr_new_id_o = instr_new_id_q;
+
+ // IF-ID pipeline registers, frozen when the ID stage is stalled
+ assign if_id_pipe_reg_we = instr_new_id_d;
+
+ always_ff @(posedge clk_i) begin
+ if (if_id_pipe_reg_we) begin
+ instr_rdata_id_o <= instr_decompressed;
+ // To reduce fan-out and help timing from the instr_rdata_id flops they are replicated.
+ instr_rdata_alu_id_o <= instr_decompressed;
+ instr_fetch_err_o <= fetch_err;
+ instr_fetch_err_plus2_o <= fetch_err_plus2;
+ instr_rdata_c_id_o <= fetch_rdata[15:0];
+ instr_is_compressed_id_o <= instr_is_compressed_int;
+ illegal_c_insn_id_o <= illegal_c_insn;
+ pc_id_o <= pc_if_o;
end
end
diff --git a/hw/vendor/lowrisc_ibex/rtl/ibex_load_store_unit.sv b/hw/vendor/lowrisc_ibex/rtl/ibex_load_store_unit.sv
index 33d9ede..689297b 100644
--- a/hw/vendor/lowrisc_ibex/rtl/ibex_load_store_unit.sv
+++ b/hw/vendor/lowrisc_ibex/rtl/ibex_load_store_unit.sv
@@ -3,6 +3,7 @@
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
+
/**
* Load Store Unit
*
@@ -12,7 +13,8 @@
`include "prim_assert.sv"
-module ibex_load_store_unit (
+module ibex_load_store_unit
+(
input logic clk_i,
input logic rst_ni,
@@ -30,13 +32,14 @@
input logic [31:0] data_rdata_i,
// signals to/from ID/EX stage
- input logic data_we_ex_i, // write enable -> from ID/EX
- input logic [1:0] data_type_ex_i, // data type: word, half word, byte -> from ID/EX
- input logic [31:0] data_wdata_ex_i, // data to write to memory -> from ID/EX
- input logic data_sign_ext_ex_i, // sign extension -> from ID/EX
+ input logic lsu_we_i, // write enable -> from ID/EX
+ input logic [1:0] lsu_type_i, // data type: word, half word, byte -> from ID/EX
+ input logic [31:0] lsu_wdata_i, // data to write to memory -> from ID/EX
+ input logic lsu_sign_ext_i, // sign extension -> from ID/EX
- output logic [31:0] data_rdata_ex_o, // requested data -> to ID/EX
- input logic data_req_ex_i, // data request -> from ID/EX
+ output logic [31:0] lsu_rdata_o, // requested data -> to ID/EX
+ output logic lsu_rdata_valid_o,
+ input logic lsu_req_i, // data request -> from ID/EX
input logic [31:0] adder_result_ex_i, // address computed in ALU -> from ID/EX
@@ -45,14 +48,23 @@
output logic [31:0] addr_last_o, // address of last transaction -> to controller
// -> mtval
// -> AGU for misaligned accesses
- output logic data_valid_o, // LSU has completed transaction -> to ID/EX
+
+ output logic lsu_req_done_o, // Signals that data request is complete
+ // (only need to await final data
+ // response) -> to ID/EX
+
+ output logic lsu_resp_valid_o, // LSU has response from transaction -> to ID/EX
// exception signals
output logic load_err_o,
output logic store_err_o,
+ output logic load_o,
output logic busy_o,
+ output logic perf_load_o,
+ output logic perf_store_o,
+
// used for assertions only
input logic illegal_insn_id_i, // illegal instruciton -> from ID/EX
input logic instr_valid_id_i // valid instruction -> from ID/EX
@@ -90,8 +102,8 @@
logic data_or_pmp_err;
typedef enum logic [2:0] {
- IDLE, WAIT_GNT_MIS, WAIT_RVALID_MIS, WAIT_GNT, WAIT_RVALID,
- WAIT_RVALID_DONE
+ IDLE, WAIT_GNT_MIS, WAIT_RVALID_MIS, WAIT_GNT,
+ WAIT_RVALID_MIS_GNTS_DONE
} ls_fsm_e;
ls_fsm_e ls_fsm_cs, ls_fsm_ns;
@@ -104,7 +116,7 @@
///////////////////
always_comb begin
- unique case (data_type_ex_i) // Data type 00 Word, 01 Half word, 11,10 byte
+ unique case (lsu_type_i) // Data type 00 Word, 01 Half word, 11,10 byte
2'b00: begin // Writing a word
if (!handle_misaligned_q) begin // first part of potentially misaligned transaction
unique case (data_offset)
@@ -151,7 +163,7 @@
end
default: data_be = 4'b1111;
- endcase // case (data_type_ex_i)
+ endcase // case (lsu_type_i)
end
/////////////////////
@@ -162,11 +174,11 @@
// we handle misaligned accesses, half word and byte accesses here
always_comb begin
unique case (data_offset)
- 2'b00: data_wdata = data_wdata_ex_i[31:0];
- 2'b01: data_wdata = {data_wdata_ex_i[23:0], data_wdata_ex_i[31:24]};
- 2'b10: data_wdata = {data_wdata_ex_i[15:0], data_wdata_ex_i[31:16]};
- 2'b11: data_wdata = {data_wdata_ex_i[ 7:0], data_wdata_ex_i[31: 8]};
- default: data_wdata = data_wdata_ex_i[31:0];
+ 2'b00: data_wdata = lsu_wdata_i[31:0];
+ 2'b01: data_wdata = {lsu_wdata_i[23:0], lsu_wdata_i[31:24]};
+ 2'b10: data_wdata = {lsu_wdata_i[15:0], lsu_wdata_i[31:16]};
+ 2'b11: data_wdata = {lsu_wdata_i[ 7:0], lsu_wdata_i[31: 8]};
+ default: data_wdata = lsu_wdata_i[31:0];
endcase // case (data_offset)
end
@@ -192,9 +204,9 @@
data_we_q <= 1'b0;
end else if (ctrl_update) begin
rdata_offset_q <= data_offset;
- data_type_q <= data_type_ex_i;
- data_sign_ext_q <= data_sign_ext_ex_i;
- data_we_q <= data_we_ex_i;
+ data_type_q <= lsu_type_i;
+ data_sign_ext_q <= lsu_sign_ext_i;
+ data_we_q <= lsu_we_i;
end
end
@@ -317,18 +329,16 @@
// check for misaligned accesses that need to be split into two word-aligned accesses
assign split_misaligned_access =
- ((data_type_ex_i == 2'b00) && (data_offset != 2'b00)) || // misaligned word access
- ((data_type_ex_i == 2'b01) && (data_offset == 2'b11)); // misaligned half-word access
+ ((lsu_type_i == 2'b00) && (data_offset != 2'b00)) || // misaligned word access
+ ((lsu_type_i == 2'b01) && (data_offset == 2'b11)); // misaligned half-word access
// FSM
always_comb begin
ls_fsm_ns = ls_fsm_cs;
data_req_o = 1'b0;
- data_valid_o = 1'b0;
addr_incr_req_o = 1'b0;
handle_misaligned_d = handle_misaligned_q;
- data_or_pmp_err = 1'b0;
pmp_err_d = pmp_err_q;
lsu_err_d = lsu_err_q;
@@ -336,18 +346,24 @@
ctrl_update = 1'b0;
rdata_update = 1'b0;
+ perf_load_o = 1'b0;
+ perf_store_o = 1'b0;
+
unique case (ls_fsm_cs)
IDLE: begin
- if (data_req_ex_i) begin
- data_req_o = 1'b1;
- pmp_err_d = data_pmp_err_i;
- lsu_err_d = 1'b0;
+ if (lsu_req_i) begin
+ data_req_o = 1'b1;
+ pmp_err_d = data_pmp_err_i;
+ lsu_err_d = 1'b0;
+ perf_load_o = ~lsu_we_i;
+ perf_store_o = lsu_we_i;
+
if (data_gnt_i) begin
ctrl_update = 1'b1;
addr_update = 1'b1;
handle_misaligned_d = split_misaligned_access;
- ls_fsm_ns = split_misaligned_access ? WAIT_RVALID_MIS : WAIT_RVALID;
+ ls_fsm_ns = split_misaligned_access ? WAIT_RVALID_MIS : IDLE;
end else begin
ls_fsm_ns = split_misaligned_access ? WAIT_GNT_MIS : WAIT_GNT;
end
@@ -383,15 +399,17 @@
// Capture the first rdata for loads
rdata_update = ~data_we_q;
// If already granted, wait for second rvalid
- ls_fsm_ns = data_gnt_i ? WAIT_RVALID : WAIT_GNT;
+ ls_fsm_ns = data_gnt_i ? IDLE : WAIT_GNT;
// Update the address for the second part, if no error
addr_update = data_gnt_i & ~(data_err_i | pmp_err_q);
-
+ // clear handle_misaligned if second request is granted
+ handle_misaligned_d = ~data_gnt_i;
end else begin
// first part rvalid is NOT received
if (data_gnt_i) begin
// second grant is received
- ls_fsm_ns = WAIT_RVALID_DONE;
+ ls_fsm_ns = WAIT_RVALID_MIS_GNTS_DONE;
+ handle_misaligned_d = 1'b0;
end
end
end
@@ -401,26 +419,15 @@
addr_incr_req_o = handle_misaligned_q;
data_req_o = 1'b1;
if (data_gnt_i || pmp_err_q) begin
- ctrl_update = 1'b1;
+ ctrl_update = 1'b1;
// Update the address, unless there was an error
- addr_update = ~lsu_err_q;
- ls_fsm_ns = WAIT_RVALID;
- end
- end
-
- WAIT_RVALID: begin
- if (data_rvalid_i || pmp_err_q) begin
- data_valid_o = 1'b1;
- // Data error from either part
- data_or_pmp_err = lsu_err_q | data_err_i | pmp_err_q;
- handle_misaligned_d = 1'b0;
+ addr_update = ~lsu_err_q;
ls_fsm_ns = IDLE;
- end else begin
- ls_fsm_ns = WAIT_RVALID;
+ handle_misaligned_d = 1'b0;
end
end
- WAIT_RVALID_DONE: begin
+ WAIT_RVALID_MIS_GNTS_DONE: begin
// tell ID/EX stage to update the address (to make sure the
// second address can be captured correctly for mtval and PMP checking)
addr_incr_req_o = 1'b1;
@@ -435,7 +442,7 @@
// Capture the first rdata for loads
rdata_update = ~data_we_q;
// Wait for second rvalid
- ls_fsm_ns = WAIT_RVALID;
+ ls_fsm_ns = IDLE;
end
end
@@ -445,6 +452,8 @@
endcase
end
+ assign lsu_req_done_o = (lsu_req_i | (ls_fsm_cs != IDLE)) & (ls_fsm_ns == IDLE);
+
// registers for FSM
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
@@ -464,8 +473,12 @@
// Outputs //
/////////////
+ assign data_or_pmp_err = lsu_err_q | data_err_i | pmp_err_q;
+ assign lsu_resp_valid_o = (data_rvalid_i | pmp_err_q) & (ls_fsm_cs == IDLE);
+ assign lsu_rdata_valid_o = lsu_resp_valid_o & ~data_we_q;
+
// output to register file
- assign data_rdata_ex_o = data_rdata_ext;
+ assign lsu_rdata_o = data_rdata_ext;
// output data address must be word aligned
assign data_addr_w_aligned = {data_addr[31:2], 2'b00};
@@ -473,17 +486,18 @@
// output to data interface
assign data_addr_o = data_addr_w_aligned;
assign data_wdata_o = data_wdata;
- assign data_we_o = data_we_ex_i;
+ assign data_we_o = lsu_we_i;
assign data_be_o = data_be;
// output to ID stage: mtval + AGU for misaligned transactions
assign addr_last_o = addr_last_q;
// Signal a load or store error depending on the transaction type outstanding
- assign load_err_o = data_or_pmp_err & ~data_we_q;
- assign store_err_o = data_or_pmp_err & data_we_q;
+ assign load_err_o = data_or_pmp_err & ~data_we_q & lsu_resp_valid_o;
+ assign store_err_o = data_or_pmp_err & data_we_q & lsu_resp_valid_o;
assign busy_o = (ls_fsm_cs != IDLE);
+ assign load_o = ~data_we_q;
////////////////
// Assertions //
@@ -497,19 +511,13 @@
assign unused_illegal_insn_id = illegal_insn_id_i;
// Selectors must be known/valid.
- `ASSERT(IbexDataTypeKnown, (instr_valid_id_i & ~illegal_insn_id_i) |-> !$isunknown(data_type_ex_i))
+ `ASSERT(IbexDataTypeKnown, (instr_valid_id_i & ~illegal_insn_id_i) |-> !$isunknown(lsu_type_i))
`ASSERT(IbexDataOffsetKnown, (instr_valid_id_i & ~illegal_insn_id_i) |-> !$isunknown(data_offset))
`ASSERT_KNOWN(IbexRDataOffsetQKnown, rdata_offset_q)
`ASSERT_KNOWN(IbexDataTypeQKnown, data_type_q)
`ASSERT(IbexLsuStateValid, ls_fsm_cs inside {
- IDLE, WAIT_GNT_MIS, WAIT_RVALID_MIS, WAIT_GNT, WAIT_RVALID,
- WAIT_RVALID_DONE})
-
- // There must not be an rvalid unless the FSM is handlling it.
- `ASSERT(IbexRvalidNotHandled, data_rvalid_i |-> (
- (ls_fsm_cs == WAIT_RVALID) ||
- (ls_fsm_cs == WAIT_RVALID_MIS) ||
- (ls_fsm_cs == WAIT_RVALID_DONE)))
+ IDLE, WAIT_GNT_MIS, WAIT_RVALID_MIS, WAIT_GNT,
+ WAIT_RVALID_MIS_GNTS_DONE})
// Errors must only be sent together with rvalid.
`ASSERT(IbexDataErrWithoutRvalid, data_err_i |-> data_rvalid_i)
diff --git a/hw/vendor/lowrisc_ibex/rtl/ibex_multdiv_fast.sv b/hw/vendor/lowrisc_ibex/rtl/ibex_multdiv_fast.sv
index 326926d..6fc2fd4 100644
--- a/hw/vendor/lowrisc_ibex/rtl/ibex_multdiv_fast.sv
+++ b/hw/vendor/lowrisc_ibex/rtl/ibex_multdiv_fast.sv
@@ -32,6 +32,8 @@
output logic [32:0] alu_operand_a_o,
output logic [32:0] alu_operand_b_o,
+ input logic multdiv_ready_id_i,
+
output logic [31:0] multdiv_result_o,
output logic valid_o
);
@@ -70,12 +72,21 @@
logic div_valid;
logic [ 4:0] div_counter_q, div_counter_d;
logic multdiv_en;
+ logic mult_hold;
+ logic div_hold;
+
+ logic mult_en_internal;
+ logic div_en_internal;
typedef enum logic [2:0] {
MD_IDLE, MD_ABS_A, MD_ABS_B, MD_COMP, MD_LAST, MD_CHANGE_SIGN, MD_FINISH
} md_fsm_e;
md_fsm_e md_state_q, md_state_d;
+
+ assign mult_en_internal = mult_en_i & ~mult_hold;
+ assign div_en_internal = div_en_i & ~div_hold;
+
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
div_counter_q <= '0;
@@ -83,7 +94,7 @@
op_denominator_q <= '0;
op_numerator_q <= '0;
op_quotient_q <= '0;
- end else if (div_en_i) begin
+ end else if (div_en_internal) begin
div_counter_q <= div_counter_d;
op_denominator_q <= op_denominator_d;
op_numerator_q <= op_numerator_d;
@@ -100,7 +111,11 @@
end
end
- assign multdiv_en = mult_en_i | div_en_i;
+ `ASSERT_KNOWN(DivEnKnown, div_en_internal);
+ `ASSERT_KNOWN(MultEnKnown, mult_en_internal);
+ `ASSERT_KNOWN(MultDivEnKnown, multdiv_en);
+
+ assign multdiv_en = mult_en_internal | div_en_internal;
assign intermediate_val_d = div_en_i ? op_remainder_d : mac_res_d;
@@ -172,6 +187,8 @@
mult_valid = mult_en_i;
mult_state_d = MULL;
+ mult_hold = 1'b0;
+
unique case (mult_state_q)
MULL: begin
@@ -179,6 +196,8 @@
mac_res_d = mac_res;
mult_valid = 1'b0;
mult_state_d = MULH;
+ end else begin
+ mult_hold = ~multdiv_ready_id_i;
end
end
@@ -196,6 +215,8 @@
mult_state_d = MULL;
mult_valid = 1'b1;
+
+ mult_hold = ~multdiv_ready_id_i;
end
default: begin
@@ -247,6 +268,7 @@
mac_res_d = mac_res;
mult_state_d = mult_state_q;
mult_valid = 1'b0;
+ mult_hold = 1'b0;
unique case (mult_state_q)
@@ -288,7 +310,10 @@
accum = {18'b0, intermediate_val_q[31:16]};
mac_res_d = {2'b0, mac_res[15:0], intermediate_val_q[15:0]};
mult_valid = 1'b1;
+
+ // Note no state transition will occur if mult_hold is set
mult_state_d = ALBL;
+ mult_hold = ~multdiv_ready_id_i;
end else begin
accum = intermediate_val_q;
mac_res_d = mac_res;
@@ -307,8 +332,11 @@
accum[33:18] = {16{signed_mult & intermediate_val_q[33]}};
// result of AH*BL is not signed only if signed_mode_i == 2'b00
mac_res_d = mac_res;
- mult_state_d = ALBL;
mult_valid = 1'b1;
+
+ // Note no state transition will occur if mult_hold is set
+ mult_state_d = ALBL;
+ mult_hold = ~multdiv_ready_id_i;
end
default: begin
mult_state_d = ALBL;
@@ -320,7 +348,7 @@
if (!rst_ni) begin
mult_state_q <= ALBL;
end else begin
- if (mult_en_i) begin
+ if (mult_en_internal) begin
mult_state_q <= mult_state_d;
end
end
@@ -367,6 +395,7 @@
alu_operand_a_o = {32'h0 , 1'b1};
alu_operand_b_o = {~op_b_i, 1'b1};
div_valid = 1'b0;
+ div_hold = 1'b0;
unique case(md_state_q)
MD_IDLE: begin
@@ -449,7 +478,10 @@
end
MD_FINISH: begin
+ // Hold result until ID stage is ready to accept it
+ // Note no state transition will occur if div_hold is set
md_state_d = MD_IDLE;
+ div_hold = ~multdiv_ready_id_i;
div_valid = 1'b1;
end
diff --git a/hw/vendor/lowrisc_ibex/rtl/ibex_multdiv_slow.sv b/hw/vendor/lowrisc_ibex/rtl/ibex_multdiv_slow.sv
index 0d80d90..96fffa2 100644
--- a/hw/vendor/lowrisc_ibex/rtl/ibex_multdiv_slow.sv
+++ b/hw/vendor/lowrisc_ibex/rtl/ibex_multdiv_slow.sv
@@ -11,7 +11,8 @@
`include "prim_assert.sv"
-module ibex_multdiv_slow (
+module ibex_multdiv_slow
+(
input logic clk_i,
input logic rst_ni,
input logic mult_en_i,
@@ -26,6 +27,9 @@
output logic [32:0] alu_operand_a_o,
output logic [32:0] alu_operand_b_o,
+
+ input logic multdiv_ready_id_i,
+
output logic [31:0] multdiv_result_o,
output logic valid_o
@@ -56,6 +60,7 @@
logic [31:0] op_numerator_q, op_numerator_d;
logic is_greater_equal;
logic div_change_sign, rem_change_sign;
+ logic multdiv_hold;
// (accum_window_q + op_a_shift_q)
assign res_adder_l = alu_adder_ext_i[32:0];
@@ -148,12 +153,14 @@
op_numerator_q <= 32'h0;
md_state_q <= MD_IDLE;
end else begin
- multdiv_state_q <= multdiv_state_d;
- accum_window_q <= accum_window_d;
- op_b_shift_q <= op_b_shift_d;
- op_a_shift_q <= op_a_shift_d;
- op_numerator_q <= op_numerator_d;
- md_state_q <= md_state_d;
+ if (~multdiv_hold) begin
+ multdiv_state_q <= multdiv_state_d;
+ accum_window_q <= accum_window_d;
+ op_b_shift_q <= op_b_shift_d;
+ op_a_shift_q <= op_a_shift_d;
+ op_numerator_q <= op_numerator_d;
+ md_state_q <= md_state_d;
+ end
end
end
@@ -164,6 +171,7 @@
op_a_shift_d = op_a_shift_q;
op_numerator_d = op_numerator_q;
md_state_d = md_state_q;
+ multdiv_hold = 1'b0;
if (mult_en_i || div_en_i) begin
unique case(md_state_q)
MD_IDLE: begin
@@ -241,11 +249,18 @@
unique case(operator_i)
MD_OP_MULL: begin
accum_window_d = res_adder_l;
- md_state_d = MD_IDLE;
+
+ // Note no state transition will occur if multdiv_hold is set
+ md_state_d = MD_IDLE;
+ multdiv_hold = ~multdiv_ready_id_i;
end
MD_OP_MULH: begin
accum_window_d = res_adder_l;
md_state_d = MD_IDLE;
+
+ // Note no state transition will occur if multdiv_hold is set
+ md_state_d = MD_IDLE;
+ multdiv_hold = ~multdiv_ready_id_i;
end
MD_OP_DIV: begin
// this time we save the quotient in accum_window_q since we do not need anymore the
@@ -272,7 +287,9 @@
end
MD_FINISH: begin
- md_state_d = MD_IDLE;
+ // Note no state transition will occur if multdiv_hold is set
+ md_state_d = MD_IDLE;
+ multdiv_hold = ~multdiv_ready_id_i;
end
default: begin
diff --git a/hw/vendor/lowrisc_ibex/rtl/ibex_pkg.sv b/hw/vendor/lowrisc_ibex/rtl/ibex_pkg.sv
index 15faa54..9dc01d1 100644
--- a/hw/vendor/lowrisc_ibex/rtl/ibex_pkg.sv
+++ b/hw/vendor/lowrisc_ibex/rtl/ibex_pkg.sv
@@ -32,7 +32,7 @@
// ALU operations //
////////////////////
-typedef enum logic [4:0] {
+typedef enum logic [5:0] {
// Arithmetics
ALU_ADD,
ALU_SUB,
@@ -41,11 +41,23 @@
ALU_XOR,
ALU_OR,
ALU_AND,
+ // RV32B
+ ALU_XNOR,
+ ALU_ORN,
+ ALU_ANDN,
// Shifts
ALU_SRA,
ALU_SRL,
ALU_SLL,
+ // RV32B
+ ALU_SRO,
+ ALU_SLO,
+ ALU_ROR,
+ ALU_ROL,
+ ALU_REV,
+ ALU_REV8,
+ ALU_ORCB,
// Comparisons
ALU_LT,
@@ -54,6 +66,23 @@
ALU_GEU,
ALU_EQ,
ALU_NE,
+ // RV32B
+ ALU_MIN,
+ ALU_MINU,
+ ALU_MAX,
+ ALU_MAXU,
+
+ // Pack
+ // RV32B
+ ALU_PACK,
+ ALU_PACKU,
+ ALU_PACKH,
+
+ // Bitcounting
+ // RV32B
+ ALU_CLZ,
+ ALU_CTZ,
+ ALU_PCNT,
// Set lower than
ALU_SLT,
@@ -96,6 +125,16 @@
XDEBUGVER_NONSTD = 4'd15 // debug not conforming to RISC-V debug spec
} x_debug_ver_e;
+//////////////
+// WB stage //
+//////////////
+
+// Type of instruction present in writeback stage
+typedef enum logic[1:0] {
+ WB_INSTR_LOAD, // Instruction is awaiting load data
+ WB_INSTR_STORE, // Instruction is awaiting store response
+ WB_INSTR_OTHER // Instruction doesn't fit into above categories
+} wb_instr_type_e;
//////////////
// ID stage //
@@ -132,15 +171,8 @@
IMM_B_INCR_ADDR
} imm_b_sel_e;
-// Only used when BranchTargetALU == 1
-typedef enum logic {
- JT_ALU, // Jump target from main ALU
- JT_BT_ALU // Jump target from specialised branch ALU
-} jt_mux_sel_e;
-
// Regfile write data selection
-typedef enum logic [1:0] {
- RF_WD_LSU,
+typedef enum logic {
RF_WD_EX,
RF_WD_CSR
} rf_wd_sel_e;
@@ -380,7 +412,8 @@
CSR_MHPMCOUNTER28H = 12'hB9C,
CSR_MHPMCOUNTER29H = 12'hB9D,
CSR_MHPMCOUNTER30H = 12'hB9E,
- CSR_MHPMCOUNTER31H = 12'hB9F
+ CSR_MHPMCOUNTER31H = 12'hB9F,
+ CSR_CPUCTRL = 12'h7C0
} csr_num_e;
// CSR pmp-related offsets
diff --git a/hw/vendor/lowrisc_ibex/rtl/ibex_pmp.sv b/hw/vendor/lowrisc_ibex/rtl/ibex_pmp.sv
index 0fee9b5..a93fda0 100644
--- a/hw/vendor/lowrisc_ibex/rtl/ibex_pmp.sv
+++ b/hw/vendor/lowrisc_ibex/rtl/ibex_pmp.sv
@@ -36,8 +36,6 @@
logic [PMPNumChan-1:0][PMPNumRegions-1:0] region_match_low;
logic [PMPNumChan-1:0][PMPNumRegions-1:0] region_match_both;
logic [PMPNumChan-1:0][PMPNumRegions-1:0] region_perm_check;
- logic [PMPNumChan-1:0][PMPNumRegions-1:0] machine_access_fault;
- logic [PMPNumChan-1:0][PMPNumRegions-1:0] user_access_allowed;
logic [PMPNumChan-1:0] access_fault;
@@ -87,14 +85,26 @@
((pmp_req_type_i[c] == PMP_ACC_EXEC) & csr_pmp_cfg_i[r].exec) |
((pmp_req_type_i[c] == PMP_ACC_WRITE) & csr_pmp_cfg_i[r].write) |
((pmp_req_type_i[c] == PMP_ACC_READ) & csr_pmp_cfg_i[r].read);
- // In machine mode, any match to a locked region without sufficient permissions is a fault
- assign machine_access_fault[c][r] = region_match_both[c][r] & csr_pmp_cfg_i[r].lock &
- ~region_perm_check[c][r];
- // In any other mode, any access should fault unless is matches a region
- assign user_access_allowed[c][r] = region_match_both[c][r] & region_perm_check[c][r];
end
- assign access_fault[c] = (priv_mode_i[c] == PRIV_LVL_M) ? |machine_access_fault[c] :
- ~|user_access_allowed[c];
+
+ // Access fault determination / prioritization
+ always_comb begin
+ // Default is allow for M-mode, deny for other modes
+ access_fault[c] = (priv_mode_i[c] != PRIV_LVL_M);
+
+ // PMP entries are statically prioritized, from 0 to N-1
+ // The lowest-numbered PMP entry which matches an address determines accessability
+ for (int r = PMPNumRegions-1; r >= 0; r--) begin
+ if (region_match_both[c][r]) begin
+ access_fault[c] = (priv_mode_i[c] == PRIV_LVL_M) ?
+ // For M-mode, any region which matches with the L-bit clear, or with sufficient
+ // access permissions will be allowed
+ (csr_pmp_cfg_i[r].lock & ~region_perm_check[c][r]) :
+ // For other modes, the lock bit doesn't matter
+ ~region_perm_check[c][r];
+ end
+ end
+ end
assign pmp_req_err_o[c] = access_fault[c];
end
diff --git a/hw/vendor/lowrisc_ibex/rtl/ibex_prefetch_buffer.sv b/hw/vendor/lowrisc_ibex/rtl/ibex_prefetch_buffer.sv
index ebd6024..30a223c 100644
--- a/hw/vendor/lowrisc_ibex/rtl/ibex_prefetch_buffer.sv
+++ b/hw/vendor/lowrisc_ibex/rtl/ibex_prefetch_buffer.sv
@@ -24,6 +24,7 @@
output logic [31:0] rdata_o,
output logic [31:0] addr_o,
output logic err_o,
+ output logic err_plus2_o,
// goes to instruction memory / instruction cache
@@ -98,7 +99,8 @@
.out_ready_i ( ready_i ),
.out_rdata_o ( rdata_o ),
.out_addr_o ( addr_o ),
- .out_err_o ( err_o )
+ .out_err_o ( err_o ),
+ .out_err_plus2_o ( err_plus2_o )
);
//////////////
diff --git a/hw/vendor/lowrisc_ibex/rtl/ibex_tracer.sv b/hw/vendor/lowrisc_ibex/rtl/ibex_tracer.sv
index 625c5ad..6d19f17 100644
--- a/hw/vendor/lowrisc_ibex/rtl/ibex_tracer.sv
+++ b/hw/vendor/lowrisc_ibex/rtl/ibex_tracer.sv
@@ -71,7 +71,6 @@
logic unused_rvfi_intr = rvfi_intr;
logic [ 1:0] unused_rvfi_mode = rvfi_mode;
- import ibex_pkg::*;
import ibex_tracer_pkg::*;
int file_handle;
@@ -400,6 +399,11 @@
decoded_str = $sformatf("%s\tx%0d,x%0d,x%0d", mnemonic, rvfi_rd_addr, rvfi_rs1_addr, rvfi_rs2_addr);
endfunction
+ function automatic void decode_r1_insn(input string mnemonic);
+ data_accessed = RS1 | RD;
+ decoded_str = $sformatf("%s\tx%0d,x%0d", mnemonic, rvfi_rd_addr, rvfi_rs1_addr);
+ endfunction
+
function automatic void decode_i_insn(input string mnemonic);
data_accessed = RS1 | RD;
decoded_str = $sformatf("%s\tx%0d,x%0d,%0d", mnemonic, rvfi_rd_addr, rvfi_rs1_addr,
@@ -407,7 +411,7 @@
endfunction
function automatic void decode_i_shift_insn(input string mnemonic);
- // SLLI, SRLI, SRAI
+ // SLLI, SRLI, SRAI, SROI, SLOI, RORI
logic [4:0] shamt;
shamt = {rvfi_insn[24:20]};
data_accessed = RS1 | RD;
@@ -843,6 +847,31 @@
// MISC-MEM
INSN_FENCE: decode_fence();
INSN_FENCEI: decode_mnemonic("fence.i");
+ // RV32B
+ INSN_SLOI: decode_i_shift_insn("sloi");
+ INSN_SROI: decode_i_shift_insn("sroi");
+ INSN_RORI: decode_i_shift_insn("rori");
+ INSN_SLO: decode_r_insn("slo");
+ INSN_SRO: decode_r_insn("sro");
+ INSN_ROL: decode_r_insn("rol");
+ INSN_ROR: decode_r_insn("ror");
+ INSN_MIN: decode_r_insn("min");
+ INSN_MAX: decode_r_insn("max");
+ INSN_MINU: decode_r_insn("minu");
+ INSN_MAXU: decode_r_insn("maxu");
+ INSN_XNOR: decode_r_insn("xnor");
+ INSN_ORN: decode_r_insn("orn");
+ INSN_ANDN: decode_r_insn("andn");
+ INSN_PACK: decode_r_insn("pack");
+ INSN_PACKH: decode_r_insn("packh");
+ INSN_PACKU: decode_r_insn("packu");
+ INSN_ORCB: decode_r_insn("orcb");
+ INSN_CLZ: decode_r1_insn("clz");
+ INSN_CTZ: decode_r1_insn("ctz");
+ INSN_PCNT: decode_r1_insn("pcnt");
+ INSN_REV: decode_r1_insn("rev");
+ INSN_REV8: decode_r1_insn("rev8");
+
default: decode_mnemonic("INVALID");
endcase
end
diff --git a/hw/vendor/lowrisc_ibex/rtl/ibex_tracer_pkg.sv b/hw/vendor/lowrisc_ibex/rtl/ibex_tracer_pkg.sv
index 9527091..2ff4164 100644
--- a/hw/vendor/lowrisc_ibex/rtl/ibex_tracer_pkg.sv
+++ b/hw/vendor/lowrisc_ibex/rtl/ibex_tracer_pkg.sv
@@ -71,6 +71,35 @@
parameter logic [31:0] INSN_PMULHSU = { 7'b0000001, 10'b?, 3'b010, 5'b?, {OPCODE_OP} };
parameter logic [31:0] INSN_PMULHU = { 7'b0000001, 10'b?, 3'b011, 5'b?, {OPCODE_OP} };
+// RV32B
+// ZBB
+// OPIMM
+parameter logic [31:0] INSN_SLOI = { 7'b00100 , 10'b?, 3'b001, 5'b?, {OPCODE_OP_IMM} };
+parameter logic [31:0] INSN_SROI = { 7'b0010000 , 10'b?, 3'b101, 5'b?, {OPCODE_OP_IMM} };
+parameter logic [31:0] INSN_RORI = { 7'b0110000 , 10'b?, 3'b101, 5'b?, {OPCODE_OP_IMM} };
+parameter logic [31:0] INSN_CLZ = { 12'b011000000000, 5'b? , 3'b001, 5'b?, {OPCODE_OP_IMM} };
+parameter logic [31:0] INSN_CTZ = { 12'b011000000001, 5'b? , 3'b001, 5'b?, {OPCODE_OP_IMM} };
+parameter logic [31:0] INSN_PCNT = { 12'b011000000010, 5'b? , 3'b001, 5'b?, {OPCODE_OP_IMM} };
+parameter logic [31:0] INSN_REV = { 12'b011010011111, 5'b? , 3'b101, 5'b?, {OPCODE_OP_IMM} };
+parameter logic [31:0] INSN_REV8 = { 12'b011010011000, 5'b? , 3'b101, 5'b?, {OPCODE_OP_IMM} };
+parameter logic [31:0] INSN_ORCB = { 12'b001010000111, 5'b? , 3'b101, 5'b?, {OPCODE_OP_IMM} };
+
+// OP
+parameter logic [31:0] INSN_SLO = { 7'b0010000, 10'b?, 3'b001, 5'b?, {OPCODE_OP} };
+parameter logic [31:0] INSN_SRO = { 7'b0010000, 10'b?, 3'b101, 5'b?, {OPCODE_OP} };
+parameter logic [31:0] INSN_ROL = { 7'b0110000, 10'b?, 3'b001, 5'b?, {OPCODE_OP} };
+parameter logic [31:0] INSN_ROR = { 7'b0110000, 10'b?, 3'b101, 5'b?, {OPCODE_OP} };
+parameter logic [31:0] INSN_MIN = { 7'b0000101, 10'b?, 3'b100, 5'b?, {OPCODE_OP} };
+parameter logic [31:0] INSN_MAX = { 7'b0000101, 10'b?, 3'b101, 5'b?, {OPCODE_OP} };
+parameter logic [31:0] INSN_MINU = { 7'b0000101, 10'b?, 3'b110, 5'b?, {OPCODE_OP} };
+parameter logic [31:0] INSN_MAXU = { 7'b0000101, 10'b?, 3'b111, 5'b?, {OPCODE_OP} };
+parameter logic [31:0] INSN_XNOR = { 7'b0100000, 10'b?, 3'b100, 5'b?, {OPCODE_OP} };
+parameter logic [31:0] INSN_ORN = { 7'b0100000, 10'b?, 3'b110, 5'b?, {OPCODE_OP} };
+parameter logic [31:0] INSN_ANDN = { 7'b0100000, 10'b?, 3'b111, 5'b?, {OPCODE_OP} };
+parameter logic [31:0] INSN_PACK = { 7'b0000100, 10'b?, 3'b100, 5'b?, {OPCODE_OP} };
+parameter logic [31:0] INSN_PACKU = { 7'b0100100, 10'b?, 3'b100, 5'b?, {OPCODE_OP} };
+parameter logic [31:0] INSN_PACKH = { 7'b0000100, 10'b?, 3'b111, 5'b?, {OPCODE_OP} };
+
// LOAD & STORE
parameter logic [31:0] INSN_LOAD = {25'b?, {OPCODE_LOAD } };
parameter logic [31:0] INSN_STORE = {25'b?, {OPCODE_STORE} };
diff --git a/hw/vendor/lowrisc_ibex/rtl/ibex_wb_stage.sv b/hw/vendor/lowrisc_ibex/rtl/ibex_wb_stage.sv
new file mode 100644
index 0000000..c6df081
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/rtl/ibex_wb_stage.sv
@@ -0,0 +1,161 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+/**
+ * Writeback Stage
+ *
+ * Writeback is an optional third pipeline stage. It writes data back to the register file that was
+ * produced in the ID/EX stage or awaits a response to a load/store (LSU writes direct to register
+ * file for load data). If the writeback stage is not present (WritebackStage == 0) this acts as
+ * a simple passthrough to write data direct to the register file.
+ */
+
+`include "prim_assert.sv"
+
+module ibex_wb_stage #(
+ parameter bit WritebackStage = 1'b0
+) (
+ input logic clk_i,
+ input logic rst_ni,
+
+ input logic en_wb_i,
+ input ibex_pkg::wb_instr_type_e instr_type_wb_i,
+ input logic [31:0] pc_id_i,
+
+ output logic ready_wb_o,
+ output logic rf_write_wb_o,
+ output logic outstanding_load_wb_o,
+ output logic outstanding_store_wb_o,
+ output logic [31:0] pc_wb_o,
+
+ input logic [4:0] rf_waddr_id_i,
+ input logic [31:0] rf_wdata_id_i,
+ input logic rf_we_id_i,
+
+ input logic [31:0] rf_wdata_lsu_i,
+ input logic rf_we_lsu_i,
+
+ output logic [31:0] rf_wdata_fwd_wb_o,
+
+ output logic [4:0] rf_waddr_wb_o,
+ output logic [31:0] rf_wdata_wb_o,
+ output logic rf_we_wb_o,
+
+ input logic lsu_data_valid_i,
+
+ output logic instr_done_wb_o
+);
+
+ import ibex_pkg::*;
+
+ // 0 == RF write from ID
+ // 1 == RF write from LSU
+ logic [31:0] rf_wdata_wb_mux [1:0];
+ logic [1:0] rf_wdata_wb_mux_we;
+
+ if(WritebackStage) begin : g_writeback_stage
+ logic [31:0] rf_wdata_wb_q;
+ logic rf_we_wb_q;
+ logic [4:0] rf_waddr_wb_q;
+
+ logic wb_done;
+
+ logic wb_valid_q;
+ logic [31:0] wb_pc_q;
+ wb_instr_type_e wb_instr_type_q;
+
+ logic wb_valid_d;
+
+ // Stage becomes valid if an instruction enters for ID/EX and valid is cleared when instruction
+ // is done
+ assign wb_valid_d = (en_wb_i & ready_wb_o) | (wb_valid_q & ~wb_done);
+
+ // Writeback for non load/store instructions always completes in a cycle (so instantly done)
+ // Writeback for load/store must wait for response to be received by the LSU
+ // Signal only relevant if wb_valid_q set
+ assign wb_done = (wb_instr_type_q == WB_INSTR_OTHER) | lsu_data_valid_i;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if(~rst_ni) begin
+ wb_valid_q <= 1'b0;
+ end else begin
+ wb_valid_q <= wb_valid_d;
+ end
+ end
+
+ always_ff @(posedge clk_i) begin
+ if(en_wb_i) begin
+ rf_we_wb_q <= rf_we_id_i;
+ rf_waddr_wb_q <= rf_waddr_id_i;
+ rf_wdata_wb_q <= rf_wdata_id_i;
+ wb_instr_type_q <= instr_type_wb_i;
+ wb_pc_q <= pc_id_i;
+ end
+ end
+
+ assign rf_waddr_wb_o = rf_waddr_wb_q;
+ assign rf_wdata_wb_mux[0] = rf_wdata_wb_q;
+ assign rf_wdata_wb_mux_we[0] = rf_we_wb_q & wb_valid_q;
+
+ assign ready_wb_o = ~wb_valid_q | wb_done;
+
+ // Instruction in writeback will be writing to register file if either rf_we is set or writeback
+ // is awaiting load data. This is used for determining RF read hazards in ID/EX
+ assign rf_write_wb_o = wb_valid_q & (rf_we_wb_q | (wb_instr_type_q == WB_INSTR_LOAD));
+
+ assign outstanding_load_wb_o = wb_valid_q & (wb_instr_type_q == WB_INSTR_LOAD);
+ assign outstanding_store_wb_o = wb_valid_q & (wb_instr_type_q == WB_INSTR_STORE);
+
+ assign pc_wb_o = wb_pc_q;
+
+ assign instr_done_wb_o = wb_valid_q & wb_done;
+
+ // Forward data that will be written to the RF back to ID to resolve data hazards. The flopped
+ // rf_wdata_wb_q is used rather than rf_wdata_wb_o as the latter includes read data from memory
+ // that returns too late to be used on the forwarding path.
+ assign rf_wdata_fwd_wb_o = rf_wdata_wb_q;
+ end else begin
+ // without writeback stage just pass through register write signals
+ assign rf_waddr_wb_o = rf_waddr_id_i;
+ assign rf_wdata_wb_mux[0] = rf_wdata_id_i;
+ assign rf_wdata_wb_mux_we[0] = rf_we_id_i;
+
+ // ready needs to be constant 1 without writeback stage (otherwise ID/EX stage will stall)
+ assign ready_wb_o = 1'b1;
+
+ // Unused Writeback stage only IO & wiring
+ // Assign inputs and internal wiring to unused signals to satisfy lint checks
+ // Tie-off outputs to constant values
+ logic unused_clk;
+ logic unused_rst;
+ logic unused_en_wb;
+ wb_instr_type_e unused_instr_type_wb;
+ logic [31:0] unused_pc_id;
+ logic unused_lsu_data_valid;
+
+ assign unused_clk = clk_i;
+ assign unused_rst = rst_ni;
+ assign unused_en_wb = en_wb_i;
+ assign unused_instr_type_wb = instr_type_wb_i;
+ assign unused_pc_id = pc_id_i;
+ assign unused_lsu_data_valid = lsu_data_valid_i;
+
+ assign outstanding_load_wb_o = 1'b0;
+ assign outstanding_store_wb_o = 1'b0;
+ assign pc_wb_o = '0;
+ assign rf_write_wb_o = 1'b0;
+ assign rf_wdata_fwd_wb_o = 32'b0;
+ assign instr_done_wb_o = 1'b0;
+ end
+
+ assign rf_wdata_wb_mux[1] = rf_wdata_lsu_i;
+ assign rf_wdata_wb_mux_we[1] = rf_we_lsu_i;
+
+ // RF write data can come from ID results (all RF writes that aren't because of loads will come
+ // from here) or the LSU (RF writes for load data)
+ assign rf_wdata_wb_o = rf_wdata_wb_mux_we[0] ? rf_wdata_wb_mux[0] : rf_wdata_wb_mux[1];
+ assign rf_we_wb_o = |rf_wdata_wb_mux_we;
+
+ `ASSERT(RFWriteFromOneSourceOnly, $onehot0(rf_wdata_wb_mux_we))
+endmodule
diff --git a/hw/vendor/lowrisc_ibex/shared/rtl/prim_generic_ram_1p.sv b/hw/vendor/lowrisc_ibex/shared/rtl/prim_generic_ram_1p.sv
new file mode 100644
index 0000000..2a33a51
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/shared/rtl/prim_generic_ram_1p.sv
@@ -0,0 +1,109 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Synchronous single-port SRAM model
+
+`include "prim_assert.sv"
+
+module prim_generic_ram_1p #(
+ parameter int Width = 32, // bit
+ parameter int Depth = 128,
+ parameter int DataBitsPerMask = 1, // Number of data bits per bit of write mask
+ localparam int Aw = $clog2(Depth) // derived parameter
+) (
+ input logic clk_i,
+ input logic rst_ni,
+
+ input logic req_i,
+ input logic write_i,
+ input logic [Aw-1:0] addr_i,
+ input logic [Width-1:0] wdata_i,
+ input logic [Width-1:0] wmask_i,
+ output logic rvalid_o,
+ output logic [Width-1:0] rdata_o
+);
+
+ // Width of internal write mask. Note wmask_i input into the module is always assumed
+ // to be the full bit mask
+ localparam int MaskWidth = Width / DataBitsPerMask;
+
+ logic [Width-1:0] mem [Depth];
+ logic [MaskWidth-1:0] wmask;
+
+ always_comb begin
+ for (int i=0; i < MaskWidth; i = i + 1) begin : create_wmask
+ wmask[i] = &wmask_i[i*DataBitsPerMask +: DataBitsPerMask];
+ end
+ end
+
+ // using always instead of always_ff to avoid 'ICPD - illegal combination of drivers' error
+ // thrown when using $readmemh system task to backdoor load an image
+ always @(posedge clk_i) begin
+ if (req_i) begin
+ if (write_i) begin
+ for (int i=0; i < MaskWidth; i = i + 1) begin
+ if (wmask[i]) begin
+ mem[addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
+ wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
+ end
+ end
+ end else begin
+ rdata_o <= mem[addr_i];
+ end
+ end
+ end
+
+ always_ff @(posedge clk_i, negedge rst_ni) begin
+ if (!rst_ni) begin
+ rvalid_o <= '0;
+ end else begin
+ rvalid_o <= req_i & ~write_i;
+ end
+ end
+
+ `ifdef VERILATOR
+ // Task for loading 'mem' with SystemVerilog system task $readmemh()
+ export "DPI-C" task simutil_verilator_memload;
+
+ task simutil_verilator_memload;
+ input string file;
+ $readmemh(file, mem);
+ endtask
+
+ // TODO: Allow 'val' to have other widths than 32 bit
+ // Note that the DPI export and function definition must both be in the same generate
+ // context to get the correct name.
+ if (Width == 32) begin : gen_32bit
+ // Function for setting a specific 32 bit element in |mem|
+ // Returns 1 (true) for success, 0 (false) for errors.
+ export "DPI-C" function simutil_verilator_set_mem;
+
+ function int simutil_verilator_set_mem(input int index,
+ input logic[31:0] val);
+ if (index >= Depth) begin
+ return 0;
+ end
+
+ mem[index] = val;
+ return 1;
+ endfunction
+ end else begin : gen_other
+ // Function doesn't work for Width != 32 so just return 0
+ export "DPI-C" function simutil_verilator_set_mem;
+
+ function int simutil_verilator_set_mem(input int index,
+ input logic[31:0] val);
+ return 0;
+ endfunction
+ end
+ `endif
+
+ `ifdef SRAM_INIT_FILE
+ localparam MEM_FILE = `PRIM_STRINGIFY(`SRAM_INIT_FILE);
+ initial begin
+ $display("Initializing SRAM from %s", MEM_FILE);
+ $readmemh(MEM_FILE, mem);
+ end
+ `endif
+endmodule
diff --git a/hw/vendor/lowrisc_ibex/shared/rtl/prim_secded_28_22_dec.sv b/hw/vendor/lowrisc_ibex/shared/rtl/prim_secded_28_22_dec.sv
new file mode 100644
index 0000000..6452c51
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/shared/rtl/prim_secded_28_22_dec.sv
@@ -0,0 +1,59 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// SECDED Decoder generated by secded_gen.py
+
+module prim_secded_28_22_dec (
+ input [27:0] in,
+ output logic [21:0] d_o,
+ output logic [5:0] syndrome_o,
+ output logic [1:0] err_o
+);
+
+ logic single_error;
+
+ // Syndrome calculation
+ assign syndrome_o[0] = in[22] ^ in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4] ^ in[5] ^ in[6] ^ in[7]
+ ^ in[8] ^ in[9] ^ in[20] ^ in[21];
+ assign syndrome_o[1] = in[23] ^ in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[10] ^ in[11] ^ in[12] ^ in[13]
+ ^ in[14] ^ in[15] ^ in[20] ^ in[21];
+ assign syndrome_o[2] = in[24] ^ in[0] ^ in[4] ^ in[5] ^ in[6] ^ in[10] ^ in[11] ^ in[12] ^ in[16]
+ ^ in[17] ^ in[18] ^ in[20];
+ assign syndrome_o[3] = in[25] ^ in[1] ^ in[4] ^ in[7] ^ in[8] ^ in[10] ^ in[13] ^ in[14] ^ in[16]
+ ^ in[17] ^ in[19] ^ in[21];
+ assign syndrome_o[4] = in[26] ^ in[2] ^ in[5] ^ in[7] ^ in[9] ^ in[11] ^ in[13] ^ in[15] ^ in[16]
+ ^ in[18] ^ in[19] ^ in[20] ^ in[21];
+ assign syndrome_o[5] = in[27] ^ in[3] ^ in[6] ^ in[8] ^ in[9] ^ in[12] ^ in[14] ^ in[15] ^ in[17]
+ ^ in[18] ^ in[19] ^ in[20] ^ in[21];
+
+ // Corrected output calculation
+ assign d_o[0] = (syndrome_o == 6'h7) ^ in[0];
+ assign d_o[1] = (syndrome_o == 6'hb) ^ in[1];
+ assign d_o[2] = (syndrome_o == 6'h13) ^ in[2];
+ assign d_o[3] = (syndrome_o == 6'h23) ^ in[3];
+ assign d_o[4] = (syndrome_o == 6'hd) ^ in[4];
+ assign d_o[5] = (syndrome_o == 6'h15) ^ in[5];
+ assign d_o[6] = (syndrome_o == 6'h25) ^ in[6];
+ assign d_o[7] = (syndrome_o == 6'h19) ^ in[7];
+ assign d_o[8] = (syndrome_o == 6'h29) ^ in[8];
+ assign d_o[9] = (syndrome_o == 6'h31) ^ in[9];
+ assign d_o[10] = (syndrome_o == 6'he) ^ in[10];
+ assign d_o[11] = (syndrome_o == 6'h16) ^ in[11];
+ assign d_o[12] = (syndrome_o == 6'h26) ^ in[12];
+ assign d_o[13] = (syndrome_o == 6'h1a) ^ in[13];
+ assign d_o[14] = (syndrome_o == 6'h2a) ^ in[14];
+ assign d_o[15] = (syndrome_o == 6'h32) ^ in[15];
+ assign d_o[16] = (syndrome_o == 6'h1c) ^ in[16];
+ assign d_o[17] = (syndrome_o == 6'h2c) ^ in[17];
+ assign d_o[18] = (syndrome_o == 6'h34) ^ in[18];
+ assign d_o[19] = (syndrome_o == 6'h38) ^ in[19];
+ assign d_o[20] = (syndrome_o == 6'h37) ^ in[20];
+ assign d_o[21] = (syndrome_o == 6'h3b) ^ in[21];
+
+ // err_o calc. bit0: single error, bit1: double error
+ assign single_error = ^syndrome_o;
+ assign err_o[0] = single_error;
+ assign err_o[1] = ~single_error & (|syndrome_o);
+endmodule
+
diff --git a/hw/vendor/lowrisc_ibex/shared/rtl/prim_secded_28_22_enc.sv b/hw/vendor/lowrisc_ibex/shared/rtl/prim_secded_28_22_enc.sv
new file mode 100644
index 0000000..0c1f023
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/shared/rtl/prim_secded_28_22_enc.sv
@@ -0,0 +1,47 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// SECDED Encoder generated by secded_gen.py
+
+module prim_secded_28_22_enc (
+ input [21:0] in,
+ output logic [27:0] out
+);
+
+ assign out[0] = in[0] ;
+ assign out[1] = in[1] ;
+ assign out[2] = in[2] ;
+ assign out[3] = in[3] ;
+ assign out[4] = in[4] ;
+ assign out[5] = in[5] ;
+ assign out[6] = in[6] ;
+ assign out[7] = in[7] ;
+ assign out[8] = in[8] ;
+ assign out[9] = in[9] ;
+ assign out[10] = in[10] ;
+ assign out[11] = in[11] ;
+ assign out[12] = in[12] ;
+ assign out[13] = in[13] ;
+ assign out[14] = in[14] ;
+ assign out[15] = in[15] ;
+ assign out[16] = in[16] ;
+ assign out[17] = in[17] ;
+ assign out[18] = in[18] ;
+ assign out[19] = in[19] ;
+ assign out[20] = in[20] ;
+ assign out[21] = in[21] ;
+ assign out[22] = in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4] ^ in[5] ^ in[6] ^ in[7] ^ in[8] ^ in[9]
+ ^ in[20] ^ in[21];
+ assign out[23] = in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[10] ^ in[11] ^ in[12] ^ in[13] ^ in[14]
+ ^ in[15] ^ in[20] ^ in[21];
+ assign out[24] = in[0] ^ in[4] ^ in[5] ^ in[6] ^ in[10] ^ in[11] ^ in[12] ^ in[16] ^ in[17]
+ ^ in[18] ^ in[20];
+ assign out[25] = in[1] ^ in[4] ^ in[7] ^ in[8] ^ in[10] ^ in[13] ^ in[14] ^ in[16] ^ in[17]
+ ^ in[19] ^ in[21];
+ assign out[26] = in[2] ^ in[5] ^ in[7] ^ in[9] ^ in[11] ^ in[13] ^ in[15] ^ in[16] ^ in[18]
+ ^ in[19] ^ in[20] ^ in[21];
+ assign out[27] = in[3] ^ in[6] ^ in[8] ^ in[9] ^ in[12] ^ in[14] ^ in[15] ^ in[17] ^ in[18]
+ ^ in[19] ^ in[20] ^ in[21];
+endmodule
+
diff --git a/hw/vendor/lowrisc_ibex/shared/rtl/prim_secded_72_64_dec.sv b/hw/vendor/lowrisc_ibex/shared/rtl/prim_secded_72_64_dec.sv
new file mode 100644
index 0000000..02b1822
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/shared/rtl/prim_secded_72_64_dec.sv
@@ -0,0 +1,121 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// SECDED Decoder generated by secded_gen.py
+
+module prim_secded_72_64_dec (
+ input [71:0] in,
+ output logic [63:0] d_o,
+ output logic [7:0] syndrome_o,
+ output logic [1:0] err_o
+);
+
+ logic single_error;
+
+ // Syndrome calculation
+ assign syndrome_o[0] = in[64] ^ in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4] ^ in[5] ^ in[6] ^ in[7]
+ ^ in[8] ^ in[9] ^ in[10] ^ in[11] ^ in[12] ^ in[13] ^ in[14] ^ in[15]
+ ^ in[16] ^ in[17] ^ in[18] ^ in[19] ^ in[20] ^ in[57] ^ in[58] ^ in[61]
+ ^ in[62] ^ in[63];
+ assign syndrome_o[1] = in[65] ^ in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4] ^ in[5] ^ in[21] ^ in[22]
+ ^ in[23] ^ in[24] ^ in[25] ^ in[26] ^ in[27] ^ in[28] ^ in[29] ^ in[30]
+ ^ in[31] ^ in[32] ^ in[33] ^ in[34] ^ in[35] ^ in[58] ^ in[59] ^ in[60]
+ ^ in[62] ^ in[63];
+ assign syndrome_o[2] = in[66] ^ in[0] ^ in[6] ^ in[7] ^ in[8] ^ in[9] ^ in[10] ^ in[21] ^ in[22]
+ ^ in[23] ^ in[24] ^ in[25] ^ in[36] ^ in[37] ^ in[38] ^ in[39] ^ in[40]
+ ^ in[41] ^ in[42] ^ in[43] ^ in[44] ^ in[45] ^ in[56] ^ in[57] ^ in[59]
+ ^ in[60] ^ in[63];
+ assign syndrome_o[3] = in[67] ^ in[1] ^ in[6] ^ in[11] ^ in[12] ^ in[13] ^ in[14] ^ in[21]
+ ^ in[26] ^ in[27] ^ in[28] ^ in[29] ^ in[36] ^ in[37] ^ in[38] ^ in[39]
+ ^ in[46] ^ in[47] ^ in[48] ^ in[49] ^ in[50] ^ in[51] ^ in[56] ^ in[57]
+ ^ in[58] ^ in[61] ^ in[63];
+ assign syndrome_o[4] = in[68] ^ in[2] ^ in[7] ^ in[11] ^ in[15] ^ in[16] ^ in[17] ^ in[22]
+ ^ in[26] ^ in[30] ^ in[31] ^ in[32] ^ in[36] ^ in[40] ^ in[41] ^ in[42]
+ ^ in[46] ^ in[47] ^ in[48] ^ in[52] ^ in[53] ^ in[54] ^ in[56] ^ in[58]
+ ^ in[59] ^ in[61] ^ in[62];
+ assign syndrome_o[5] = in[69] ^ in[3] ^ in[8] ^ in[12] ^ in[15] ^ in[18] ^ in[19] ^ in[23]
+ ^ in[27] ^ in[30] ^ in[33] ^ in[34] ^ in[37] ^ in[40] ^ in[43] ^ in[44]
+ ^ in[46] ^ in[49] ^ in[50] ^ in[52] ^ in[53] ^ in[55] ^ in[56] ^ in[57]
+ ^ in[59] ^ in[60] ^ in[61];
+ assign syndrome_o[6] = in[70] ^ in[4] ^ in[9] ^ in[13] ^ in[16] ^ in[18] ^ in[20] ^ in[24]
+ ^ in[28] ^ in[31] ^ in[33] ^ in[35] ^ in[38] ^ in[41] ^ in[43] ^ in[45]
+ ^ in[47] ^ in[49] ^ in[51] ^ in[52] ^ in[54] ^ in[55] ^ in[56] ^ in[59]
+ ^ in[60] ^ in[61] ^ in[62];
+ assign syndrome_o[7] = in[71] ^ in[5] ^ in[10] ^ in[14] ^ in[17] ^ in[19] ^ in[20] ^ in[25]
+ ^ in[29] ^ in[32] ^ in[34] ^ in[35] ^ in[39] ^ in[42] ^ in[44] ^ in[45]
+ ^ in[48] ^ in[50] ^ in[51] ^ in[53] ^ in[54] ^ in[55] ^ in[57] ^ in[58]
+ ^ in[60] ^ in[62] ^ in[63];
+
+ // Corrected output calculation
+ assign d_o[0] = (syndrome_o == 8'h7) ^ in[0];
+ assign d_o[1] = (syndrome_o == 8'hb) ^ in[1];
+ assign d_o[2] = (syndrome_o == 8'h13) ^ in[2];
+ assign d_o[3] = (syndrome_o == 8'h23) ^ in[3];
+ assign d_o[4] = (syndrome_o == 8'h43) ^ in[4];
+ assign d_o[5] = (syndrome_o == 8'h83) ^ in[5];
+ assign d_o[6] = (syndrome_o == 8'hd) ^ in[6];
+ assign d_o[7] = (syndrome_o == 8'h15) ^ in[7];
+ assign d_o[8] = (syndrome_o == 8'h25) ^ in[8];
+ assign d_o[9] = (syndrome_o == 8'h45) ^ in[9];
+ assign d_o[10] = (syndrome_o == 8'h85) ^ in[10];
+ assign d_o[11] = (syndrome_o == 8'h19) ^ in[11];
+ assign d_o[12] = (syndrome_o == 8'h29) ^ in[12];
+ assign d_o[13] = (syndrome_o == 8'h49) ^ in[13];
+ assign d_o[14] = (syndrome_o == 8'h89) ^ in[14];
+ assign d_o[15] = (syndrome_o == 8'h31) ^ in[15];
+ assign d_o[16] = (syndrome_o == 8'h51) ^ in[16];
+ assign d_o[17] = (syndrome_o == 8'h91) ^ in[17];
+ assign d_o[18] = (syndrome_o == 8'h61) ^ in[18];
+ assign d_o[19] = (syndrome_o == 8'ha1) ^ in[19];
+ assign d_o[20] = (syndrome_o == 8'hc1) ^ in[20];
+ assign d_o[21] = (syndrome_o == 8'he) ^ in[21];
+ assign d_o[22] = (syndrome_o == 8'h16) ^ in[22];
+ assign d_o[23] = (syndrome_o == 8'h26) ^ in[23];
+ assign d_o[24] = (syndrome_o == 8'h46) ^ in[24];
+ assign d_o[25] = (syndrome_o == 8'h86) ^ in[25];
+ assign d_o[26] = (syndrome_o == 8'h1a) ^ in[26];
+ assign d_o[27] = (syndrome_o == 8'h2a) ^ in[27];
+ assign d_o[28] = (syndrome_o == 8'h4a) ^ in[28];
+ assign d_o[29] = (syndrome_o == 8'h8a) ^ in[29];
+ assign d_o[30] = (syndrome_o == 8'h32) ^ in[30];
+ assign d_o[31] = (syndrome_o == 8'h52) ^ in[31];
+ assign d_o[32] = (syndrome_o == 8'h92) ^ in[32];
+ assign d_o[33] = (syndrome_o == 8'h62) ^ in[33];
+ assign d_o[34] = (syndrome_o == 8'ha2) ^ in[34];
+ assign d_o[35] = (syndrome_o == 8'hc2) ^ in[35];
+ assign d_o[36] = (syndrome_o == 8'h1c) ^ in[36];
+ assign d_o[37] = (syndrome_o == 8'h2c) ^ in[37];
+ assign d_o[38] = (syndrome_o == 8'h4c) ^ in[38];
+ assign d_o[39] = (syndrome_o == 8'h8c) ^ in[39];
+ assign d_o[40] = (syndrome_o == 8'h34) ^ in[40];
+ assign d_o[41] = (syndrome_o == 8'h54) ^ in[41];
+ assign d_o[42] = (syndrome_o == 8'h94) ^ in[42];
+ assign d_o[43] = (syndrome_o == 8'h64) ^ in[43];
+ assign d_o[44] = (syndrome_o == 8'ha4) ^ in[44];
+ assign d_o[45] = (syndrome_o == 8'hc4) ^ in[45];
+ assign d_o[46] = (syndrome_o == 8'h38) ^ in[46];
+ assign d_o[47] = (syndrome_o == 8'h58) ^ in[47];
+ assign d_o[48] = (syndrome_o == 8'h98) ^ in[48];
+ assign d_o[49] = (syndrome_o == 8'h68) ^ in[49];
+ assign d_o[50] = (syndrome_o == 8'ha8) ^ in[50];
+ assign d_o[51] = (syndrome_o == 8'hc8) ^ in[51];
+ assign d_o[52] = (syndrome_o == 8'h70) ^ in[52];
+ assign d_o[53] = (syndrome_o == 8'hb0) ^ in[53];
+ assign d_o[54] = (syndrome_o == 8'hd0) ^ in[54];
+ assign d_o[55] = (syndrome_o == 8'he0) ^ in[55];
+ assign d_o[56] = (syndrome_o == 8'h7c) ^ in[56];
+ assign d_o[57] = (syndrome_o == 8'had) ^ in[57];
+ assign d_o[58] = (syndrome_o == 8'h9b) ^ in[58];
+ assign d_o[59] = (syndrome_o == 8'h76) ^ in[59];
+ assign d_o[60] = (syndrome_o == 8'he6) ^ in[60];
+ assign d_o[61] = (syndrome_o == 8'h79) ^ in[61];
+ assign d_o[62] = (syndrome_o == 8'hd3) ^ in[62];
+ assign d_o[63] = (syndrome_o == 8'h8f) ^ in[63];
+
+ // err_o calc. bit0: single error, bit1: double error
+ assign single_error = ^syndrome_o;
+ assign err_o[0] = single_error;
+ assign err_o[1] = ~single_error & (|syndrome_o);
+endmodule
+
diff --git a/hw/vendor/lowrisc_ibex/shared/rtl/prim_secded_72_64_enc.sv b/hw/vendor/lowrisc_ibex/shared/rtl/prim_secded_72_64_enc.sv
new file mode 100644
index 0000000..207c45c
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/shared/rtl/prim_secded_72_64_enc.sv
@@ -0,0 +1,101 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// SECDED Encoder generated by secded_gen.py
+
+module prim_secded_72_64_enc (
+ input [63:0] in,
+ output logic [71:0] out
+);
+
+ assign out[0] = in[0] ;
+ assign out[1] = in[1] ;
+ assign out[2] = in[2] ;
+ assign out[3] = in[3] ;
+ assign out[4] = in[4] ;
+ assign out[5] = in[5] ;
+ assign out[6] = in[6] ;
+ assign out[7] = in[7] ;
+ assign out[8] = in[8] ;
+ assign out[9] = in[9] ;
+ assign out[10] = in[10] ;
+ assign out[11] = in[11] ;
+ assign out[12] = in[12] ;
+ assign out[13] = in[13] ;
+ assign out[14] = in[14] ;
+ assign out[15] = in[15] ;
+ assign out[16] = in[16] ;
+ assign out[17] = in[17] ;
+ assign out[18] = in[18] ;
+ assign out[19] = in[19] ;
+ assign out[20] = in[20] ;
+ assign out[21] = in[21] ;
+ assign out[22] = in[22] ;
+ assign out[23] = in[23] ;
+ assign out[24] = in[24] ;
+ assign out[25] = in[25] ;
+ assign out[26] = in[26] ;
+ assign out[27] = in[27] ;
+ assign out[28] = in[28] ;
+ assign out[29] = in[29] ;
+ assign out[30] = in[30] ;
+ assign out[31] = in[31] ;
+ assign out[32] = in[32] ;
+ assign out[33] = in[33] ;
+ assign out[34] = in[34] ;
+ assign out[35] = in[35] ;
+ assign out[36] = in[36] ;
+ assign out[37] = in[37] ;
+ assign out[38] = in[38] ;
+ assign out[39] = in[39] ;
+ assign out[40] = in[40] ;
+ assign out[41] = in[41] ;
+ assign out[42] = in[42] ;
+ assign out[43] = in[43] ;
+ assign out[44] = in[44] ;
+ assign out[45] = in[45] ;
+ assign out[46] = in[46] ;
+ assign out[47] = in[47] ;
+ assign out[48] = in[48] ;
+ assign out[49] = in[49] ;
+ assign out[50] = in[50] ;
+ assign out[51] = in[51] ;
+ assign out[52] = in[52] ;
+ assign out[53] = in[53] ;
+ assign out[54] = in[54] ;
+ assign out[55] = in[55] ;
+ assign out[56] = in[56] ;
+ assign out[57] = in[57] ;
+ assign out[58] = in[58] ;
+ assign out[59] = in[59] ;
+ assign out[60] = in[60] ;
+ assign out[61] = in[61] ;
+ assign out[62] = in[62] ;
+ assign out[63] = in[63] ;
+ assign out[64] = in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4] ^ in[5] ^ in[6] ^ in[7] ^ in[8] ^ in[9]
+ ^ in[10] ^ in[11] ^ in[12] ^ in[13] ^ in[14] ^ in[15] ^ in[16] ^ in[17] ^ in[18]
+ ^ in[19] ^ in[20] ^ in[57] ^ in[58] ^ in[61] ^ in[62] ^ in[63];
+ assign out[65] = in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4] ^ in[5] ^ in[21] ^ in[22] ^ in[23] ^ in[24]
+ ^ in[25] ^ in[26] ^ in[27] ^ in[28] ^ in[29] ^ in[30] ^ in[31] ^ in[32] ^ in[33]
+ ^ in[34] ^ in[35] ^ in[58] ^ in[59] ^ in[60] ^ in[62] ^ in[63];
+ assign out[66] = in[0] ^ in[6] ^ in[7] ^ in[8] ^ in[9] ^ in[10] ^ in[21] ^ in[22] ^ in[23]
+ ^ in[24] ^ in[25] ^ in[36] ^ in[37] ^ in[38] ^ in[39] ^ in[40] ^ in[41] ^ in[42]
+ ^ in[43] ^ in[44] ^ in[45] ^ in[56] ^ in[57] ^ in[59] ^ in[60] ^ in[63];
+ assign out[67] = in[1] ^ in[6] ^ in[11] ^ in[12] ^ in[13] ^ in[14] ^ in[21] ^ in[26] ^ in[27]
+ ^ in[28] ^ in[29] ^ in[36] ^ in[37] ^ in[38] ^ in[39] ^ in[46] ^ in[47] ^ in[48]
+ ^ in[49] ^ in[50] ^ in[51] ^ in[56] ^ in[57] ^ in[58] ^ in[61] ^ in[63];
+ assign out[68] = in[2] ^ in[7] ^ in[11] ^ in[15] ^ in[16] ^ in[17] ^ in[22] ^ in[26] ^ in[30]
+ ^ in[31] ^ in[32] ^ in[36] ^ in[40] ^ in[41] ^ in[42] ^ in[46] ^ in[47] ^ in[48]
+ ^ in[52] ^ in[53] ^ in[54] ^ in[56] ^ in[58] ^ in[59] ^ in[61] ^ in[62];
+ assign out[69] = in[3] ^ in[8] ^ in[12] ^ in[15] ^ in[18] ^ in[19] ^ in[23] ^ in[27] ^ in[30]
+ ^ in[33] ^ in[34] ^ in[37] ^ in[40] ^ in[43] ^ in[44] ^ in[46] ^ in[49] ^ in[50]
+ ^ in[52] ^ in[53] ^ in[55] ^ in[56] ^ in[57] ^ in[59] ^ in[60] ^ in[61];
+ assign out[70] = in[4] ^ in[9] ^ in[13] ^ in[16] ^ in[18] ^ in[20] ^ in[24] ^ in[28] ^ in[31]
+ ^ in[33] ^ in[35] ^ in[38] ^ in[41] ^ in[43] ^ in[45] ^ in[47] ^ in[49] ^ in[51]
+ ^ in[52] ^ in[54] ^ in[55] ^ in[56] ^ in[59] ^ in[60] ^ in[61] ^ in[62];
+ assign out[71] = in[5] ^ in[10] ^ in[14] ^ in[17] ^ in[19] ^ in[20] ^ in[25] ^ in[29] ^ in[32]
+ ^ in[34] ^ in[35] ^ in[39] ^ in[42] ^ in[44] ^ in[45] ^ in[48] ^ in[50] ^ in[51]
+ ^ in[53] ^ in[54] ^ in[55] ^ in[57] ^ in[58] ^ in[60] ^ in[62] ^ in[63];
+endmodule
+
diff --git a/hw/vendor/lowrisc_ibex/shared/sim_shared.core b/hw/vendor/lowrisc_ibex/shared/sim_shared.core
index 02ff4d4..286c610 100644
--- a/hw/vendor/lowrisc_ibex/shared/sim_shared.core
+++ b/hw/vendor/lowrisc_ibex/shared/sim_shared.core
@@ -10,6 +10,11 @@
- lowrisc:prim:assert
files:
- ./rtl/prim_clock_gating.sv
+ - ./rtl/prim_generic_ram_1p.sv
+ - ./rtl/prim_secded_28_22_enc.sv
+ - ./rtl/prim_secded_28_22_dec.sv
+ - ./rtl/prim_secded_72_64_enc.sv
+ - ./rtl/prim_secded_72_64_dec.sv
- ./rtl/ram_1p.sv
- ./rtl/ram_2p.sv
- ./rtl/bus.sv
diff --git a/hw/vendor/lowrisc_ibex/syn/README.md b/hw/vendor/lowrisc_ibex/syn/README.md
index 889b851..d7150d8 100644
--- a/hw/vendor/lowrisc_ibex/syn/README.md
+++ b/hw/vendor/lowrisc_ibex/syn/README.md
@@ -56,11 +56,11 @@
# Running the synthesis flow
Once `syn_setup.sh` has been created the `syn_yosys.sh` will run the entire
-flow. All outputs are placed in a directory with the prefix `syn_out_` with the
-current date/time forming the rest of the name, e.g.
-`syn_out_06_01_2020_11_19_15`
+flow. All outputs are placed under the `syn/syn_out` directory with the prefix
+`ibex_` with the current date/time forming the rest of the name, e.g.
+`syn/syn_out/ibex_06_01_2020_11_19_15`
-- `syn_out_dir`
+- `syn/syn_out/ibex_date`
- `reports` - All of the generated reports
- area.rpt - Total area used and per cell instance counts
- `timing`
@@ -77,6 +77,9 @@
- ibex_core.[library-name].out.sdc - Generated .sdc timing constraints
file
+If you wish to change the results directory naming or location edit
+`syn_setup.sh` appropriately.
+
# Timing constraints
Two files specify the timing constraints and timing related settings for the
diff --git a/hw/vendor/lowrisc_ibex/syn/ibex_core.nangate.sdc b/hw/vendor/lowrisc_ibex/syn/ibex_core.nangate.sdc
index f887018..f5fae74 100644
--- a/hw/vendor/lowrisc_ibex/syn/ibex_core.nangate.sdc
+++ b/hw/vendor/lowrisc_ibex/syn/ibex_core.nangate.sdc
@@ -2,5 +2,5 @@
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
-set_driving_cell BUF_X2
+set_driving_cell [all_inputs] -lib_cell BUF_X2
set_load 10.0 [all_outputs]
diff --git a/hw/vendor/lowrisc_ibex/syn/ibex_core_abc.nangate.sdc b/hw/vendor/lowrisc_ibex/syn/ibex_core_abc.nangate.sdc
new file mode 100644
index 0000000..f887018
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/syn/ibex_core_abc.nangate.sdc
@@ -0,0 +1,6 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+set_driving_cell BUF_X2
+set_load 10.0 [all_outputs]
diff --git a/hw/vendor/lowrisc_ibex/syn/syn_setup.example.sh b/hw/vendor/lowrisc_ibex/syn/syn_setup.example.sh
index e75f6af..f3b6f4e 100644
--- a/hw/vendor/lowrisc_ibex/syn/syn_setup.example.sh
+++ b/hw/vendor/lowrisc_ibex/syn/syn_setup.example.sh
@@ -7,7 +7,7 @@
if [ $# -eq 1 ]; then
export LR_SYNTH_OUT_DIR=$1
elif [ $# -eq 0 ]; then
- export LR_SYNTH_OUT_DIR_PREFIX=syn_out
+ export LR_SYNTH_OUT_DIR_PREFIX="syn_out/ibex"
export LR_SYNTH_OUT_DIR=$(date +"${LR_SYNTH_OUT_DIR_PREFIX}_%d_%m_%Y_%H_%M_%S")
else
echo "Usage $0 [synth_out_dir]"
diff --git a/hw/vendor/lowrisc_ibex/syn/tcl/lr_synth_flow_var_setup.tcl b/hw/vendor/lowrisc_ibex/syn/tcl/lr_synth_flow_var_setup.tcl
index 0ae986a..b665e2b 100644
--- a/hw/vendor/lowrisc_ibex/syn/tcl/lr_synth_flow_var_setup.tcl
+++ b/hw/vendor/lowrisc_ibex/syn/tcl/lr_synth_flow_var_setup.tcl
@@ -21,6 +21,7 @@
set_flow_var cell_library_name "nangate" "Name of cell library"
#set_flow_var sdc_file "${top_module}.sdc" "SDC file"
set_flow_var sdc_file_in "${lr_synth_top_module}.${lr_synth_cell_library_name}.sdc" "Input SDC file"
+ set_flow_var abc_sdc_file_in "${lr_synth_top_module}_abc.${lr_synth_cell_library_name}.sdc" "Input SDC file for ABC"
set flop_in_pin_default "*/D"
set flop_out_pin_default "*/Q"
diff --git a/hw/vendor/lowrisc_ibex/syn/tcl/yosys_run_synth.tcl b/hw/vendor/lowrisc_ibex/syn/tcl/yosys_run_synth.tcl
index fcece96..7f2de7d 100644
--- a/hw/vendor/lowrisc_ibex/syn/tcl/yosys_run_synth.tcl
+++ b/hw/vendor/lowrisc_ibex/syn/tcl/yosys_run_synth.tcl
@@ -31,7 +31,7 @@
set yosys_abc_clk_period [expr $lr_synth_clk_period - $lr_synth_abc_clk_uprate]
if { $lr_synth_timing_run } {
- yosys "abc -liberty $lr_synth_cell_library_path -constr $lr_synth_sdc_file_out -D $yosys_abc_clk_period"
+ yosys "abc -liberty $lr_synth_cell_library_path -constr $lr_synth_abc_sdc_file_in -D $yosys_abc_clk_period"
} else {
yosys "abc -liberty $lr_synth_cell_library_path"
}
@@ -43,7 +43,7 @@
# Produce netlist that OpenSTA can use
yosys "setundef -zero"
yosys "splitnets"
-
+ yosys "clean"
yosys "write_verilog -noattr -noexpr -nohex -nodec $lr_synth_sta_netlist_out"
}
diff --git a/hw/vendor/lowrisc_ibex/util/ibex_config.py b/hw/vendor/lowrisc_ibex/util/ibex_config.py
new file mode 100755
index 0000000..70ecc3e
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/util/ibex_config.py
@@ -0,0 +1,207 @@
+#!/usr/bin/env python3
+
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+import argparse
+import collections
+import os
+import shlex
+import sys
+
+import yaml
+
+_DEFAULT_CONFIG_FILE = 'ibex_configs.yaml'
+
+
+class ConfigException(Exception):
+ pass
+
+
+def _verify_config(name, config_dict):
+ """Checks a config_dict matches expectations.
+
+ A config_dict is the dictionary mapping parameters to values for a
+ particular config, it must obey the following rules:
+ - It's a mapping object e.g. OrderedDict
+ - Its values can only be strings, integers or booleans
+
+ Args:
+ name: The name of the config being checked (used to form useful error
+ messages)
+ config_dict: The config_dict to check, must be a mapping object
+
+ Returns:
+ Nothing, an exception is thrown if an issue is found
+
+ Raises:
+ ConfigException: An issue was found with config_dict
+ """
+
+ if not isinstance(config_dict, collections.Mapping):
+ raise ConfigException('Config ' + name +
+ ' must have dictionary giving parameters')
+
+ for k, v in config_dict.items():
+ if isinstance(v, int):
+ continue
+ if isinstance(v, str):
+ continue
+ if isinstance(v, bool):
+ continue
+
+ raise ConfigException('Parameter ' + k + ' for config ' + name +
+ ' must be string, int or bool got ' +
+ str(type(v)))
+
+
+def _verify_config_parameters(config_dicts):
+ """Verifies all parameters across config_dicts match expectations.
+
+ Each configuration must obey the following fules:
+ - Each config has the same set of parameters specified
+
+ Args:
+ config_dicts: A dictionary of configurations, maps from configuration
+ name to a configuration (itself a dictionary)
+
+ Returns:
+ Nothing, an exception is thrown if an issue is found
+
+ Raises:
+ ConfigException: An issue was found with config_dicts
+ """
+
+ parameters = set()
+
+ first = True
+
+ for name, config_dict in config_dicts.items():
+ parameters_this_config = set()
+
+ for parameter, value in config_dict.items():
+ if first:
+ parameters.add(parameter)
+
+ parameters_this_config.add(parameter)
+
+ if first:
+ first = False
+ else:
+ parameter_difference = parameters ^ parameters_this_config
+ if parameter_difference:
+ raise ConfigException('Config ' + name +
+ ' has differing parameters ' +
+ ','.join(parameter_difference))
+
+
+def get_config_dicts(config_file):
+ """Extracts a dictionary of configuration dictionaries from a file object
+
+ Given a file object parses YAML from it to obtain a dictionary of
+ configurations
+
+ Args:
+ config_file: A file object for a file containing the YAML configuration
+ file
+
+ Returns:
+ A dictionary of configurations, maps from a configuration name to a
+ configuration (itself a dictionary mapping parameters to values)
+
+ Raises:
+ ConfigException: An issue was found with the configuration file
+ """
+
+ try:
+ config_yaml = yaml.load(config_file, Loader=yaml.SafeLoader)
+ except yaml.YAMLError as e:
+ raise ConfigException('Could not decode yaml:\n' + str(e))
+
+ for k, v in config_yaml.items():
+ _verify_config(k, v)
+
+ _verify_config_parameters(config_yaml)
+
+ return config_yaml
+
+
+def _config_dict_to_fusesoc_opts(config_dict):
+ fusesoc_cmd = []
+ for parameter, value in config_dict.items():
+ if isinstance(value, bool):
+ # For fusesoc boolean parameter are set to true if given on the
+ # command line otherwise false, it doesn't support an explicit
+ # --param=True style
+ if value:
+ fusesoc_cmd.append(shlex.quote('--' + parameter))
+ else:
+ fusesoc_cmd.append(shlex.quote('--' + parameter + '=' + str(value)))
+
+ return ' '.join(fusesoc_cmd)
+
+
+def get_config_file_location():
+ """Returns the location of the config file
+
+ Default is _DEFAULT_CONFIG_FILE and the IBEX_CONFIG_FILE environment
+ variable overrides the default"""
+
+ return os.environ.get('IBEX_CONFIG_FILE', _DEFAULT_CONFIG_FILE)
+
+
+def main():
+ config_outputs = {'fusesoc_opts': _config_dict_to_fusesoc_opts}
+
+ argparser = argparse.ArgumentParser(description=(
+ 'Outputs Ibex configuration '
+ 'parameters for a named config in a number of formats. If not '
+ 'specified on the command line the config will be read from {0}. This '
+ 'default can be overridden by setting the IBEX_CONFIG_FILE environment '
+ 'variable').format(get_config_file_location()))
+
+ argparser.add_argument('config_name',
+ help=('The name of the Ibex '
+ 'configuration to output'))
+
+ argparser.add_argument('output_type',
+ help=('Format to output the '
+ 'configuration parameters in'),
+ choices=config_outputs.keys())
+
+ argparser.add_argument('--config_filename',
+ help='Config file to read',
+ default=get_config_file_location())
+
+ args = argparser.parse_args()
+
+ try:
+ config_file = open(args.config_filename)
+ config_dicts = get_config_dicts(config_file)
+
+ if args.config_name not in config_dicts:
+ print('ERROR: configuration',
+ args.config_name,
+ 'not found in',
+ args.config_filename,
+ file=sys.stderr)
+
+ sys.exit(1)
+
+ print(config_outputs[args.output_type](config_dicts[args.config_name]))
+ except ConfigException as ce:
+ print('ERROR: failure to read configuration from',
+ args.config_filename,
+ ce,
+ file=sys.stderr)
+ sys.exit(1)
+ except FileNotFoundError:
+ print('ERROR: could not find configuration file',
+ args.config_filename,
+ file=sys.stderr)
+ sys.exit(1)
+
+
+if __name__ == "__main__":
+ main()
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark.lock.hjson b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark.lock.hjson
new file mode 100644
index 0000000..1fcba7d
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark.lock.hjson
@@ -0,0 +1,14 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// This file is generated by the util/vendor script. Please do not modify it
+// manually.
+
+{
+ upstream:
+ {
+ url: https://github.com/eembc/coremark
+ rev: 0c91314d1a4fdfc157d623ad5cb6ac5aef746db1
+ }
+}
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/LICENSE.md b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/LICENSE.md
new file mode 100644
index 0000000..14e53e9
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/LICENSE.md
@@ -0,0 +1,100 @@
+# COREMARK® ACCEPTABLE USE AGREEMENT
+
+This ACCEPTABLE USE AGREEMENT (this “Agreement”) is offered by Embedded Microprocessor Benchmark Consortium, a California nonprofit corporation (“Licensor”), to users of its CoreMark® software (“Licensee”) exclusively on the following terms.
+
+Licensor offers benchmarking software (“Software”) pursuant to an open source license, but carefully controls use of its benchmarks and their associated goodwill. Licensor has registered its trademark in one of the benchmarks available through the Software, COREMARK, Ser. No. 85/487,290; Reg. No. 4,179,307 (the “Trademark”), and promotes the use of a standard metric as a benchmark for assessing the performance of embedded systems. Solely on the terms described herein, Licensee may use and display the Trademark in connection with the generation of data regarding measurement and analysis of computer and embedded system benchmarking via the Software (the “Licensed Use”).
+
+## Article 1 – License Grant.
+1.1. License. Subject to the terms and conditions of this Agreement, Licensor hereby grants to Licensee, and Licensee hereby accepts from Licensor, a personal, non-exclusive, royalty-free, revocable right and license to use and display the Trademark during the term of this Agreement (the “Term”), solely and exclusively in connection with the Licensed Use. During the Term, Licensee (i) shall not modify or otherwise create derivative works of the Trademark, and (ii) may use the Trademark only to the extent permitted under this License. Neither Licensee nor any affiliate or agent thereof shall otherwise use the Trademark without the prior express written consent of Licensor, which may be withheld in its sole and absolute discretion. All rights not expressly granted to Licensee hereunder shall remain the exclusive property of Licensor.
+
+1.2. Modifications to the Software. Licensee shall not use the Trademark in connection with any use of a modified, derivative, or otherwise altered copy of the Software.
+
+1.3. Licensor’s Use. Nothing in this Agreement shall preclude Licensor or any of its successors or assigns from using or permitting other entities to use the Trademark, whether or not such entity directly or indirectly competes or conflicts with Licensee’s Licensed Use in any manner.
+
+1.4. Term and Termination. This Agreement is perpetual unless terminated by either of the parties. Licensee may terminate this Agreement for convenience, without cause or liability, for any reason or for no reason whatsoever, upon ten (10) business days written notice. Licensor may terminate this Agreement effective immediately upon notice of breach. Upon termination, Licensee shall immediately remove all implementations of the Trademark from the Licensed Use, and delete all digitals files and records of all materials related to the Trademark.
+
+## Article 2 – Ownership.
+2.1. Ownership. Licensee acknowledges and agrees that Licensor is the owner of all right, title, and interest in and to the Trademark, and all such right, title, and interest shall remain with Licensor. Licensee shall not contest, dispute, challenge, oppose, or seek to cancel Licensor’s right, title, and interest in and to the Trademark. Licensee shall not prosecute any application for registration of the Trademark. Licensee shall display appropriate notices regarding ownership of the Trademark in connection with the Licensed Use.
+
+2.2. Goodwill. Licensee acknowledges that Licensee shall not acquire any right, title, or interest in the Trademark by virtue of this Agreement other than the license granted hereunder, and disclaims any such right, title, interest, or ownership. All goodwill and reputation generated by Licensee’s use of the Trademark shall inure to the exclusive benefit of Licensor. Licensee shall not by any act or omission use the Trademark in any manner that disparages or reflects adversely on Licensor or its Licensed Use or reputation. Licensee shall not take any action that would interfere with or prejudice Licensor’s ownership or registration of the Trademark, the validity of the Trademark or the validity of the license granted by this Agreement. If Licensor determines and notifies Licensee that any act taken in connection with the Licensed Use (i) is inaccurate, unlawful or offensive to good taste; (ii) fails to provide for proper trademark notices, or (iii) otherwise violates Licensee’s obligations under this Agreement, the license granted under this Agreement shall terminate.
+
+## Article 3 – Indemnification.
+3.1. Indemnification Generally. Licensee agrees to indemnify, defend, and hold harmless (collectively “indemnify” or “indemnification”) Licensor, including Licensor’s members, managers, officers, and employees (collectively “Related Persons”), from and against, and pay or reimburse Licensor and such Related Persons for, any and all third-party actions, claims, demands, proceedings, investigations, inquiries (collectively, “Claims”), and any and all liabilities, obligations, fines, deficiencies, costs, expenses, royalties, losses, and damages (including reasonable outside counsel fees and expenses) associated with such Claims, to the extent that such Claim arises out of (i) Licensee’s material breach of this Agreement, or (ii) any allegation(s) that Licensee’s actions infringe or violate any third-party intellectual property right, including without limitation, any U.S. copyright, patent, or trademark, or are otherwise found to be tortious or criminal (whether or not such indemnified person is a named party in a legal proceeding).
+
+3.2. Notice and Defense of Claims. Licensor shall promptly notify Licensee of any Claim for which indemnification is sought, following actual knowledge of such Claim, provided however that the failure to give such notice shall not relieve Licensee of its obligations hereunder except to the extent that Licensee is materially prejudiced by such failure. In the event that any third-party Claim is brought, Licensee shall have the right and option to undertake and control the defense of such action with counsel of its choice, provided however that (i) Licensor at its own expense may participate and appear on an equal footing with Licensee in the defense of any such Claim, (ii) Licensor may undertake and control such defense in the event of the material failure of Licensee to undertake and control the same; and (iii) the defense of any Claim relating to the intellectual property rights of Licensor or its licensors and any related counterclaims shall be solely controlled by Licensor with counsel of its choice. Licensee shall not consent to judgment or concede or settle or compromise any Claim without the prior written approval of Licensor (whose approval shall not be unreasonably withheld), unless such concession or settlement or compromise includes a full and unconditional release of Licensor and any applicable Related Persons from all liabilities in respect of such Claim.
+
+## Article 4 – Miscellaneous.
+4.1. Relationship of the Parties. This Agreement does not create a partnership, franchise, joint venture, agency, fiduciary, or employment relationship between the parties.
+
+4.2. No Third-Party Beneficiaries. Except for the rights of Related Persons under Article 3 (Indemnification), there are no third-party beneficiaries to this Agreement.
+
+4.3. Assignment. Licensee’s rights hereunder are non-assignable, and may not be sublicensed.
+
+4.4. Equitable Relief. Licensee acknowledges that the remedies available at law for any breach of this Agreement will, by their nature, be inadequate. Accordingly, Licensor may obtain injunctive relief or other equitable relief to restrain a breach or threatened breach of this Agreement or to specifically enforce this Agreement, without proving that any monetary damages have been sustained, and without the requirement of posting of a bond prior to obtaining such equitable relief.
+
+4.5. Governing Law. This Agreement will be interpreted, construed, and enforced in all respects in accordance with the laws of the State of California, without reference to its conflict of law principles.
+
+4.6. Attorneys’ Fees. If any legal action, arbitration or other proceeding is brought for the enforcement of this Agreement, or because of an alleged dispute, breach, default, or misrepresentation in connection with any of the provisions of this Agreement, the successful or prevailing party shall be entitled to recover its reasonable attorneys’ fees and other reasonable costs incurred in that action or proceeding, in addition to any other relief to which it may be entitled.
+
+4.7. Amendment; Waiver. This Agreement may not be amended, nor may any rights under it be waived, except in writing by Licensor.
+
+4.8. Severability. If any provision of this Agreement is held by a court of competent jurisdiction to be contrary to law, the provision shall be modified by the court and interpreted so as best to accomplish the objectives of the original provision to the fullest extent
+permitted by law, and the remaining provisions of this Agreement shall remain in effect.
+
+4.9. Entire Agreement. This Agreement constitutes the entire agreement between the parties and supersedes all prior and contemporaneous agreements, proposals or representations, written or oral, concerning its subject matter.
+
+
+# Apache License
+
+Version 2.0, January 2004
+
+http://www.apache.org/licenses/
+
+## TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
+1. Definitions.
+
+"License" shall mean the terms and conditions for use, reproduction, and distribution as defined by Sections 1 through 9 of this document.
+
+"Licensor" shall mean the copyright owner or entity authorized by the copyright owner that is granting the License.
+
+"Legal Entity" shall mean the union of the acting entity and all other entities that control, are controlled by, or are under common control with that entity. For the purposes of this definition, "control" means (i) the power, direct or indirect, to cause the direction or management of such entity, whether by contract or otherwise, or (ii) ownership of fifty percent (50%) or more of the outstanding shares, or (iii) beneficial ownership of such entity.
+
+"You" (or "Your") shall mean an individual or Legal Entity exercising permissions granted by this License.
+
+"Source" form shall mean the preferred form for making modifications, including but not limited to software source code, documentation source, and configuration files.
+
+"Object" form shall mean any form resulting from mechanical transformation or translation of a Source form, including but not limited to compiled object code, generated documentation, and conversions to other media types.
+
+"Work" shall mean the work of authorship, whether in Source or Object form, made available under the License, as indicated by a copyright notice that is included in or attached to the work (an example is provided in the Appendix below).
+
+"Derivative Works" shall mean any work, whether in Source or Object form, that is based on (or derived from) the Work and for which the editorial revisions, annotations, elaborations, or other modifications represent, as a whole, an original work of authorship. For the purposes of this License, Derivative Works shall not include works that remain separable from, or merely link (or bind by name) to the interfaces of, the Work and Derivative Works thereof.
+
+"Contribution" shall mean any work of authorship, including the original version of the Work and any modifications or additions to that Work or Derivative Works thereof, that is intentionally submitted to Licensor for inclusion in the Work by the copyright owner or by an individual or Legal Entity authorized to submit on behalf of the copyright owner. For the purposes of this definition, "submitted" means any form of electronic, verbal, or written communication sent to the Licensor or its representatives, including but not limited to communication on electronic mailing lists, source code control systems, and issue tracking systems that are managed by, or on behalf of, the Licensor for the purpose of discussing and improving the Work, but excluding communication that is conspicuously marked or otherwise designated in writing by the copyright owner as "Not a Contribution."
+
+"Contributor" shall mean Licensor and any individual or Legal Entity on behalf of whom a Contribution has been received by Licensor and subsequently incorporated within the Work.
+
+2. Grant of Copyright License. Subject to the terms and conditions of this License, each Contributor hereby grants to You a perpetual, worldwide, non-exclusive, no-charge, royalty-free, irrevocable copyright license to reproduce, prepare Derivative Works of, publicly display, publicly perform, sublicense, and distribute the Work and such Derivative Works in Source or Object form.
+
+3. Grant of Patent License. Subject to the terms and conditions of this License, each Contributor hereby grants to You a perpetual, worldwide, non-exclusive, no-charge, royalty-free, irrevocable (except as stated in this section) patent license to make, have made, use, offer to sell, sell, import, and otherwise transfer the Work, where such license applies only to those patent claims licensable by such Contributor that are necessarily infringed by their Contribution(s) alone or by combination of their Contribution(s) with the Work to which such Contribution(s) was submitted. If You institute patent litigation against any entity (including a cross-claim or counterclaim in a lawsuit) alleging that the Work or a Contribution incorporated within the Work constitutes direct or contributory patent infringement, then any patent licenses granted to You under this License for that Work shall terminate as of the date such litigation is filed.
+
+4. Redistribution. You may reproduce and distribute copies of the Work or Derivative Works thereof in any medium, with or without modifications, and in Source or Object form, provided that You meet the following conditions:
+
+ You must give any other recipients of the Work or Derivative Works a copy of this License; and
+ You must cause any modified files to carry prominent notices stating that You changed the files; and
+ You must retain, in the Source form of any Derivative Works that You distribute, all copyright, patent, trademark, and attribution notices from the Source form of the Work, excluding those notices that do not pertain to any part of the Derivative Works; and
+ If the Work includes a "NOTICE" text file as part of its distribution, then any Derivative Works that You distribute must include a readable copy of the attribution notices contained within such NOTICE file, excluding those notices that do not pertain to any part of the Derivative Works, in at least one of the following places: within a NOTICE text file distributed as part of the Derivative Works; within the Source form or documentation, if provided along with the Derivative Works; or, within a display generated by the Derivative Works, if and wherever such third-party notices normally appear. The contents of the NOTICE file are for informational purposes only and do not modify the License. You may add Your own attribution notices within Derivative Works that You distribute, alongside or as an addendum to the NOTICE text from the Work, provided that such additional attribution notices cannot be construed as modifying the License.
+
+ You may add Your own copyright statement to Your modifications and may provide additional or different license terms and conditions for use, reproduction, or distribution of Your modifications, or for any such Derivative Works as a whole, provided Your use, reproduction, and distribution of the Work otherwise complies with the conditions stated in this License.
+
+5. Submission of Contributions. Unless You explicitly state otherwise, any Contribution intentionally submitted for inclusion in the Work by You to the Licensor shall be under the terms and conditions of this License, without any additional terms or conditions. Notwithstanding the above, nothing herein shall supersede or modify the terms of any separate license agreement you may have executed with Licensor regarding such Contributions.
+
+6. Trademarks. This License does not grant permission to use the trade names, trademarks, service marks, or product names of the Licensor, except as required for reasonable and customary use in describing the origin of the Work and reproducing the content of the NOTICE file.
+
+7. Disclaimer of Warranty. Unless required by applicable law or agreed to in writing, Licensor provides the Work (and each Contributor provides its Contributions) on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, including, without limitation, any warranties or conditions of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A PARTICULAR PURPOSE. You are solely responsible for determining the appropriateness of using or redistributing the Work and assume any risks associated with Your exercise of permissions under this License.
+
+8. Limitation of Liability. In no event and under no legal theory, whether in tort (including negligence), contract, or otherwise, unless required by applicable law (such as deliberate and grossly negligent acts) or agreed to in writing, shall any Contributor be liable to You for damages, including any direct, indirect, special, incidental, or consequential damages of any character arising as a result of this License or out of the use or inability to use the Work (including but not limited to damages for loss of goodwill, work stoppage, computer failure or malfunction, or any and all other commercial damages or losses), even if such Contributor has been advised of the possibility of such damages.
+
+9. Accepting Warranty or Additional Liability. While redistributing the Work or Derivative Works thereof, You may choose to offer, and charge a fee for, acceptance of support, warranty, indemnity, or other liability obligations and/or rights consistent with this License. However, in accepting such obligations, You may act only on Your own behalf and on Your sole responsibility, not on behalf of any other Contributor, and only if You agree to indemnify, defend, and hold each Contributor harmless for any liability incurred by, or claims asserted against, such Contributor by reason of your accepting any such warranty or additional liability.
+
+END OF TERMS AND CONDITIONS
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/Makefile b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/Makefile
new file mode 100644
index 0000000..5f90912
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/Makefile
@@ -0,0 +1,139 @@
+# Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# Original Author: Shay Gal-on
+
+# Make sure the default target is to simply build and run the benchmark.
+RSTAMP = v1.0
+
+.PHONY: run score
+run: $(OUTFILE) rerun score
+
+score:
+ @echo "Check run1.log and run2.log for results."
+ @echo "See README.md for run and reporting rules."
+
+ifndef PORT_DIR
+# Ports for a couple of common self hosted platforms
+UNAME=$(shell if command -v uname 2> /dev/null; then uname ; fi)
+ifneq (,$(findstring CYGWIN,$(UNAME)))
+PORT_DIR=cygwin
+endif
+ifneq (,$(findstring Linux,$(UNAME)))
+MACHINE=$(shell uname -m)
+ifneq (,$(findstring 64,$(MACHINE)))
+PORT_DIR=linux64
+else
+PORT_DIR=linux
+endif
+endif
+endif
+ifndef PORT_DIR
+$(error PLEASE define PORT_DIR! (e.g. make PORT_DIR=simple))
+endif
+vpath %.c $(PORT_DIR)
+vpath %.h $(PORT_DIR)
+vpath %.mak $(PORT_DIR)
+include $(PORT_DIR)/core_portme.mak
+
+ifndef ITERATIONS
+ITERATIONS=0
+endif
+ifdef REBUILD
+FORCE_REBUILD=force_rebuild
+endif
+
+CFLAGS += -DITERATIONS=$(ITERATIONS)
+
+CORE_FILES = core_list_join core_main core_matrix core_state core_util
+ORIG_SRCS = $(addsuffix .c,$(CORE_FILES))
+SRCS = $(ORIG_SRCS) $(PORT_SRCS)
+OBJS = $(addprefix $(OPATH),$(addsuffix $(OEXT),$(CORE_FILES)) $(PORT_OBJS))
+OUTNAME = coremark$(EXE)
+OUTFILE = $(OPATH)$(OUTNAME)
+LOUTCMD = $(OFLAG) $(OUTFILE) $(LFLAGS_END)
+OUTCMD = $(OUTFLAG) $(OUTFILE) $(LFLAGS_END)
+
+HEADERS = coremark.h
+CHECK_FILES = $(ORIG_SRCS) $(HEADERS)
+
+$(OPATH):
+ $(MKDIR) $(OPATH)
+
+.PHONY: compile link
+ifdef SEPARATE_COMPILE
+$(OPATH)$(PORT_DIR):
+ $(MKDIR) $(OPATH)$(PORT_DIR)
+
+compile: $(OPATH) $(OPATH)$(PORT_DIR) $(OBJS) $(HEADERS)
+link: compile
+ $(LD) $(LFLAGS) $(XLFLAGS) $(OBJS) $(LOUTCMD)
+
+else
+
+compile: $(OPATH) $(SRCS) $(HEADERS)
+ $(CC) $(CFLAGS) $(XCFLAGS) $(SRCS) $(OUTCMD)
+link: compile
+ @echo "Link performed along with compile"
+
+endif
+
+$(OUTFILE): $(SRCS) $(HEADERS) Makefile core_portme.mak $(FORCE_REBUILD)
+ $(MAKE) port_prebuild
+ $(MAKE) link
+ $(MAKE) port_postbuild
+
+.PHONY: rerun
+rerun:
+ $(MAKE) XCFLAGS="$(XCFLAGS) -DPERFORMANCE_RUN=1" load run1.log
+ $(MAKE) XCFLAGS="$(XCFLAGS) -DVALIDATION_RUN=1" load run2.log
+
+PARAM1=$(PORT_PARAMS) 0x0 0x0 0x66 $(ITERATIONS)
+PARAM2=$(PORT_PARAMS) 0x3415 0x3415 0x66 $(ITERATIONS)
+PARAM3=$(PORT_PARAMS) 8 8 8 $(ITERATIONS)
+
+run1.log-PARAM=$(PARAM1) 7 1 2000
+run2.log-PARAM=$(PARAM2) 7 1 2000
+run3.log-PARAM=$(PARAM3) 7 1 1200
+
+run1.log run2.log run3.log: load
+ $(MAKE) port_prerun
+ $(RUN) $(OUTFILE) $($(@)-PARAM) > $(OPATH)$@
+ $(MAKE) port_postrun
+
+.PHONY: gen_pgo_data
+gen_pgo_data: run3.log
+
+.PHONY: load
+load: $(OUTFILE)
+ $(MAKE) port_preload
+ $(LOAD) $(OUTFILE)
+ $(MAKE) port_postload
+
+.PHONY: clean
+clean:
+ rm -f $(OUTFILE) $(OPATH)*.log *.info $(OPATH)index.html $(PORT_CLEAN)
+
+.PHONY: force_rebuild
+force_rebuild:
+ echo "Forcing Rebuild"
+
+.PHONY: check
+check:
+ md5sum -c coremark.md5
+
+ifdef ETC
+# Targets related to testing and releasing CoreMark. Not part of the general release!
+include Makefile.internal
+endif
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/README.md b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/README.md
new file mode 100644
index 0000000..6e00041
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/README.md
@@ -0,0 +1,396 @@
+
+# Introduction
+
+CoreMark's primary goals are simplicity and providing a method for testing only a processor's core features. For more information about EEMBC's comprehensive embedded benchmark suites, please see www.eembc.org.
+
+For a more compute-intensive version of CoreMark that uses larger datasets and execution loops taken from common applications, please check out EEMBC's [CoreMark-PRO](https://www.github.com/eembc/coremark-pro) benchmark, also on GitHub.
+
+# Building and Running
+
+To build and run the benchmark, type
+
+`> make`
+
+Full results are available in the files `run1.log` and `run2.log`. CoreMark result can be found in `run1.log`.
+
+## Cross Compiling
+
+For cross compile platforms please adjust `core_portme.mak`, `core_portme.h` (and possibly `core_portme.c`) according to the specific platform used. When porting to a new platform, it is recommended to copy one of the default port folders (e.g. `mkdir <platform> && cp linux/* <platform>`), adjust the porting files, and run:
+~~~
+% make PORT_DIR=<platform>
+~~~
+
+## Make Targets
+`run` - Default target, creates `run1.log` and `run2.log`.
+`run1.log` - Run the benchmark with performance parameters, and output to `run1.log`
+`run2.log` - Run the benchmark with validation parameters, and output to `run2.log`
+`run3.log` - Run the benchmark with profile generation parameters, and output to `run3.log`
+`compile` - compile the benchmark executable
+`link` - link the benchmark executable
+`check` - test MD5 of sources that may not be modified
+`clean` - clean temporary files
+
+### Make flag: `ITERATIONS`
+By default, the benchmark will run between 10-100 seconds. To override, use `ITERATIONS=N`
+~~~
+% make ITERATIONS=10
+~~~
+Will run the benchmark for 10 iterations. It is recommended to set a specific number of iterations in certain situations e.g.:
+
+* Running with a simulator
+* Measuring power/energy
+* Timing cannot be restarted
+
+Minimum required run time: **Results are only valid for reporting if the benchmark ran for at least 10 secs!**
+
+### Make flag: `XCFLAGS`
+To add compiler flags from the command line, use `XCFLAGS` e.g.:
+
+~~~
+% make XCFLAGS="-g -DMULTITHREAD=4 -DUSE_FORK=1"
+~~~
+
+### Make flag: `CORE_DEBUG`
+
+Define to compile for a debug run if you get incorrect CRC.
+
+~~~
+% make XCFLAGS="-DCORE_DEBUG=1"
+~~~
+
+### Make flag: `REBUILD`
+
+Force a rebuild of the executable.
+
+## Systems Without `make`
+The following files need to be compiled:
+* `core_list_join.c`
+* `core_main.c`
+* `core_matrix.c`
+* `core_state.c`
+* `core_util.c`
+* `PORT_DIR/core_portme.c`
+
+For example:
+~~~
+% gcc -O2 -o coremark.exe core_list_join.c core_main.c core_matrix.c core_state.c core_util.c simple/core_portme.c -DPERFORMANCE_RUN=1 -DITERATIONS=1000
+% ./coremark.exe > run1.log
+~~~
+The above will compile the benchmark for a performance run and 1000 iterations. Output is redirected to `run1.log`.
+
+# Parallel Execution
+Use `XCFLAGS=-DMULTITHREAD=N` where N is number of threads to run in parallel. Several implementations are available to execute in multiple contexts, or you can implement your own in `core_portme.c`.
+
+~~~
+% make XCFLAGS="-DMULTITHREAD=4 -DUSE_PTHREAD"
+~~~
+
+Above will compile the benchmark for execution on 4 cores, using POSIX Threads API.
+
+# Run Parameters for the Benchmark Executable
+CoreMark's executable takes several parameters as follows (but only if `main()` accepts arguments):
+1st - A seed value used for initialization of data.
+2nd - A seed value used for initialization of data.
+3rd - A seed value used for initialization of data.
+4th - Number of iterations (0 for auto : default value)
+5th - Reserved for internal use.
+6th - Reserved for internal use.
+7th - For malloc users only, ovreride the size of the input data buffer.
+
+The run target from make will run coremark with 2 different data initialization seeds.
+
+## Alternative parameters:
+If not using `malloc` or command line arguments are not supported, the buffer size
+for the algorithms must be defined via the compiler define `TOTAL_DATA_SIZE`.
+`TOTAL_DATA_SIZE` must be set to 2000 bytes (default) for standard runs.
+The default for such a target when testing different configurations could be:
+
+~~~
+% make XCFLAGS="-DTOTAL_DATA_SIZE=6000 -DMAIN_HAS_NOARGC=1"
+~~~
+
+# Submitting Results
+
+CoreMark results can be submitted on the web. Open a web browser and go to the [submission page](https://www.eembc.org/coremark/submit.php). After registering an account you may enter a score.
+
+# Run Rules
+What is and is not allowed.
+
+## Required
+1. The benchmark needs to run for at least 10 seconds.
+2. All validation must succeed for seeds `0,0,0x66` and `0x3415,0x3415,0x66`, buffer size of 2000 bytes total.
+ * If not using command line arguments to main:
+~~~
+ % make XCFLAGS="-DPERFORMANCE_RUN=1" REBUILD=1 run1.log
+ % make XCFLAGS="-DVALIDATION_RUN=1" REBUILD=1 run2.log
+~~~
+3. If using profile guided optimization, profile must be generated using seeds of `8,8,8`, and buffer size of 1200 bytes total.
+~~~
+ % make XCFLAGS="-DTOTAL_DATA_SIZE=1200 -DPROFILE_RUN=1" REBUILD=1 run3.log
+~~~
+4. All source files must be compiled with the same flags.
+5. All data type sizes must match size in bits such that:
+ * `ee_u8` is an unsigned 8-bit datatype.
+ * `ee_s16` is a signed 16-bit datatype.
+ * `ee_u16` is an unsigned 16-bit datatype.
+ * `ee_s32` is a signed 32-bit datatype.
+ * `ee_u32` is an unsigned 32-bit datatype.
+
+## Allowed
+
+1. Changing number of iterations
+2. Changing toolchain and build/load/run options
+3. Changing method of acquiring a data memory block
+5. Changing the method of acquiring seed values
+6. Changing implementation `in core_portme.c`
+7. Changing configuration values in `core_portme.h`
+8. Changing `core_portme.mak`
+
+## NOT ALLOWED
+1. Changing of source file other then `core_portme*` (use `make check` to validate)
+
+# Reporting rules
+Use the following syntax to report results on a data sheet:
+
+CoreMark 1.0 : N / C [/ P] [/ M]
+
+N - Number of iterations per second with seeds 0,0,0x66,size=2000)
+
+C - Compiler version and flags
+
+P - Parameters such as data and code allocation specifics
+
+* This parameter *may* be omitted if all data was allocated on the heap in RAM.
+* This parameter *may not* be omitted when reporting CoreMark/MHz
+
+M - Type of parallel execution (if used) and number of contexts
+* This parameter may be omitted if parallel execution was not used.
+
+e.g.:
+
+~~~
+CoreMark 1.0 : 128 / GCC 4.1.2 -O2 -fprofile-use / Heap in TCRAM / FORK:2
+~~~
+or
+~~~
+CoreMark 1.0 : 1400 / GCC 3.4 -O4
+~~~
+
+If reporting scaling results, the results must be reported as follows:
+
+CoreMark/MHz 1.0 : N / C / P [/ M]
+
+P - When reporting scaling results, memory parameter must also indicate memory frequency:core frequency ratio.
+1. If the core has cache and cache frequency to core frequency ratio is configurable, that must also be included.
+
+e.g.:
+
+~~~
+CoreMark/MHz 1.0 : 1.47 / GCC 4.1.2 -O2 / DDR3(Heap) 30:1 Memory 1:1 Cache
+~~~
+
+# Log File Format
+The log files have the following format
+
+~~~
+2K performance run parameters for coremark. (Run type)
+CoreMark Size : 666 (Buffer size)
+Total ticks : 25875 (platform dependent value)
+Total time (secs) : 25.875000 (actual time in seconds)
+Iterations/Sec : 3864.734300 (Performance value to report)
+Iterations : 100000 (number of iterations used)
+Compiler version : GCC3.4.4 (Compiler and version)
+Compiler flags : -O2 (Compiler and linker flags)
+Memory location : Code in flash, data in on chip RAM
+seedcrc : 0xe9f5 (identifier for the input seeds)
+[0]crclist : 0xe714 (validation for list part)
+[0]crcmatrix : 0x1fd7 (validation for matrix part)
+[0]crcstate : 0x8e3a (validation for state part)
+[0]crcfinal : 0x33ff (iteration dependent output)
+Correct operation validated. See README.md for run and reporting rules. (*Only when run is successful*)
+CoreMark 1.0 : 6508.490622 / GCC3.4.4 -O2 / Heap (*Only on a successful performance run*)
+~~~
+
+# Theory of Operation
+
+This section describes the initial goals of CoreMark and their implementation.
+
+## Small and easy to understand
+
+* X number of source code lines for timed portion of the benchmark.
+* Meaningful names for variables and functions.
+* Comments for each block of code more than 10 lines long.
+
+## Portability
+
+A thin abstraction layer will be provided for I/O and timing in a separate file. All I/O and timing of the benchmark will be done through this layer.
+
+### Code / data size
+
+* Compile with gcc on x86 and make sure all sizes are according to requirements.
+* If dynamic memory allocation is used, take total memory allocated into account as well.
+* Avoid recursive functions and keep track of stack usage.
+* Use the same memory block as data site for all algorithms, and initialize the data before each algorithm – while this means that initialization with data happens during the timed portion, it will only happen once during the timed portion and so have negligible effect on the results.
+
+## Controlled output
+
+This may be the most difficult goal. Compilers are constantly improving and getting better at analyzing code. To create work that cannot be computed at compile time and must be computed at run time, we will rely on two assumptions:
+
+* Some system functions (e.g. time, scanf) and parameters cannot be computed at compile time. In most cases, marking a variable volatile means the compiler is force to read this variable every time it is read. This will be used to introduce a factor into the input that cannot be precomputed at compile time. Since the results are input dependent, that will make sure that computation has to happen at run time.
+
+* Either a system function or I/O (e.g. scanf) or command line parameters or volatile variables will be used before the timed portion to generate data which is not available at compile time. Specific method used is not relevant as long as it can be controlled, and that it cannot be computed or eliminated by the compiler at compile time. E.g. if the clock() functions is a compiler stub, it may not be used. The derived values will be reported on the output so that verification can be done on a different machine.
+
+* We cannot rely on command line parameters since some embedded systems do not have the capability to provide command line parameters. All 3 methods above will be implemented (time based, scanf and command line parameters) and all 3 are valid if the compiler cannot determine the value at compile time.
+
+* It is important to note that The actual values that are to be supplied at run time will be standardized. The methodology is not intended to provide random data, but simply to provide controlled data that cannot be precomputed at compile time.
+
+* Printed results must be valid at run time. This will be used to make sure the computation has been executed.
+
+* Some embedded systems do not provide “printf” or other I/O functionality. All I/O will be done through a thin abstraction interface to allow execution on such systems (e.g. allow output via JTAG).
+
+## Key Algorithms
+
+### Linked List
+
+The following linked list structure will be used:
+
+~~~
+typedef struct list_data_s {
+ ee_s16 data16;
+ ee_s16 idx;
+} list_data;
+
+typedef struct list_head_s {
+ struct list_head_s *next;
+ struct list_data_s *info;
+} list_head;
+~~~
+
+While adding a level of indirection accessing the data, this structure is realistic and used in many embedded applications for small to medium lists.
+
+The list itself will be initialized on a block of memory that will be passed in to the initialization function. While in general linked lists use malloc for new nodes, embedded applications sometime control the memory for small data structures such as arrays and lists directly to avoid the overhead of system calls, so this approach is realistic.
+
+The linked list will be initialized such that 1/4 of the list pointers point to sequential areas in memory, and 3/4 of the list pointers are distributed in a non sequential manner. This is done to emulate a linked list that had add/remove happen for a while disrupting the neat order, and then a series of adds that are likely to come from sequential memory locations.
+
+For the benchmark itself:
+- Multiple find operations are going to be performed. These find operations may result in the whole list being traversed. The result of each find will become part of the output chain.
+- The list will be sorted using merge sort based on the data16 value, and then derive CRC of the data16 item in order for part of the list. The CRC will become part of the output chain.
+- The list will be sorted again using merge sort based on the idx value. This sort will guarantee that the list is returned to the primary state before leaving the function, so that multiple iterations of the function will have the same result. CRC of the data16 for part of the list will again be calculated and become part of the output chain.
+
+The actual `data16` in each cell will be pseudo random based on a single 16b input that cannot be determined at compile time. In addition, the part of the list which is used for CRC will also be passed to the function, and determined based on an input that cannot be determined at run time.
+
+### Matrix Multiply
+
+This very simple algorithm forms the basis of many more complex algorithms. The tight inner loop is the focus of many optimizations (compiler as well as hardware based) and is thus relevant for embedded processing.
+
+The total available data space will be divided to 3 parts:
+1. NxN matrix A.
+2. NxN matrix B.
+3. NxN matrix C.
+
+E.g. for 2K we will have 3 12x12 matrices (assuming data type of 32b 12(len)*12(wid)*4(size)*3(num) =1728 bytes).
+
+Matrix A will be initialized with small values (upper 3/4 of the bits all zero).
+Matrix B will be initialized with medium values (upper half of the bits all zero).
+Matrix C will be used for the result.
+
+For the benchmark itself:
+- Multiple A by a constant into C, add the upper bits of each of the values in the result matrix. The result will become part of the output chain.
+- Multiple A by column X of B into C, add the upper bits of each of the values in the result matrix. The result will become part of the output chain.
+- Multiple A by B into C, add the upper bits of each of the values in the result matrix. The result will become part of the output chain.
+
+The actual values for A and B must be derived based on input that is not available at compile time.
+
+### State Machine
+
+This part of the code needs to exercise switch and if statements. As such, we will use a small Moore state machine. In particular, this will be a state machine that identifies string input as numbers and divides them according to format.
+
+The state machine will parse the input string until either a “,” separator or end of input is encountered. An invalid number will cause the state machine to return invalid state and a valid number will cause the state machine to return with type of number format (int/float/scientific).
+
+This code will perform a realistic task, be small enough to easily understand, and exercise the required functionality. The other option used in embedded systems is a mealy based state machine, which is driven by a table. The table then determines the number of states and complexity of transitions. This approach, however, tests mainly the load/store and function call mechanisms and less the handling of branches. If analysis of the final results shows that the load/store functionality of the processor is not exercised thoroughly, it may be a good addition to the benchmark (codesize allowing).
+
+For input, the memory block will be initialized with comma separated values of mixed formats, as well as invalid inputs.
+
+For the benchmark itself:
+- Invoke the state machine on all of the input and count final states and state transitions. CRC of all final states and transitions will become part of the output chain.
+- Modify the input at intervals (inject errors) and repeat the state machine operation.
+- Modify the input back to original form.
+
+The actual input must be initialized based on data that cannot be determined at compile time. In addition the intervals for modification of the input and the actual modification must be based on input that cannot be determined at compile time.
+
+# Validation
+
+This release was tested on the following platforms:
+* x86 cygwin and gcc 3.4 (Quad, dual and single core systems)
+* x86 linux (Ubuntu/Fedora) and gcc (4.2/4.1) (Quad and single core systems)
+* MIPS64 BE linux and gcc 3.4 16 cores system
+* MIPS32 BE linux with CodeSourcery compiler 4.2-177 on Malta/Linux with a 1004K 3-core system
+* PPC simulator with gcc 4.2.2 (No OS)
+* PPC 64b BE linux (yellowdog) with gcc 3.4 and 4.1 (Dual core system)
+* BF533 with VDSP50
+* Renesas R8C/H8 MCU with HEW 4.05
+* NXP LPC1700 armcc v4.0.0.524
+* NEC 78K with IAR v4.61
+* ARM simulator with armcc v4
+
+# Memory Analysis
+
+Valgrind 3.4.0 used and no errors reported.
+
+# Balance Analysis
+
+Number of instructions executed for each function tested with cachegrind and found balanced with gcc and -O0.
+
+# Statistics
+
+Lines:
+~~~
+Lines Blank Cmnts Source AESL
+===== ===== ===== ===== ========== =======================================
+ 469 66 170 251 627.5 core_list_join.c (C)
+ 330 18 54 268 670.0 core_main.c (C)
+ 256 32 80 146 365.0 core_matrix.c (C)
+ 240 16 51 186 465.0 core_state.c (C)
+ 165 11 20 134 335.0 core_util.c (C)
+ 150 23 36 98 245.0 coremark.h (C)
+ 1610 166 411 1083 2707.5 ----- Benchmark ----- (6 files)
+ 293 15 74 212 530.0 linux/core_portme.c (C)
+ 235 30 104 104 260.0 linux/core_portme.h (C)
+ 528 45 178 316 790.0 ----- Porting ----- (2 files)
+
+* For comparison, here are the stats for Dhrystone
+Lines Blank Cmnts Source AESL
+===== ===== ===== ===== ========== =======================================
+ 311 15 242 54 135.0 dhry.h (C)
+ 789 132 119 553 1382.5 dhry_1.c (C)
+ 186 26 68 107 267.5 dhry_2.c (C)
+ 1286 173 429 714 1785.0 ----- C ----- (3 files)
+~~~
+
+# Credits
+Many thanks to all of the individuals who helped with the development or testing of CoreMark including (Sorted by company name; note that company names may no longer be accurate as this was written in 2009).
+* Alan Anderson, ADI
+* Adhikary Rajiv, ADI
+* Elena Stohr, ARM
+* Ian Rickards, ARM
+* Andrew Pickard, ARM
+* Trent Parker, CAVIUM
+* Shay Gal-On, EEMBC
+* Markus Levy, EEMBC
+* Peter Torelli, EEMBC
+* Ron Olson, IBM
+* Eyal Barzilay, MIPS
+* Jens Eltze, NEC
+* Hirohiko Ono, NEC
+* Ulrich Drees, NEC
+* Frank Roscheda, NEC
+* Rob Cosaro, NXP
+* Shumpei Kawasaki, RENESAS
+
+# Legal
+Please refer to LICENSE.md in this reposity for a description of your rights to use this code.
+
+# Copyright
+Copyright © 2009 EEMBC All rights reserved.
+CoreMark is a trademark of EEMBC and EEMBC is a registered trademark of the Embedded Microprocessor Benchmark Consortium.
+
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/barebones/core_portme.c b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/barebones/core_portme.c
new file mode 100755
index 0000000..3364681
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/barebones/core_portme.c
@@ -0,0 +1,128 @@
+/*
+Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Original Author: Shay Gal-on
+*/
+#include "coremark.h"
+#include "core_portme.h"
+
+#if VALIDATION_RUN
+ volatile ee_s32 seed1_volatile=0x3415;
+ volatile ee_s32 seed2_volatile=0x3415;
+ volatile ee_s32 seed3_volatile=0x66;
+#endif
+#if PERFORMANCE_RUN
+ volatile ee_s32 seed1_volatile=0x0;
+ volatile ee_s32 seed2_volatile=0x0;
+ volatile ee_s32 seed3_volatile=0x66;
+#endif
+#if PROFILE_RUN
+ volatile ee_s32 seed1_volatile=0x8;
+ volatile ee_s32 seed2_volatile=0x8;
+ volatile ee_s32 seed3_volatile=0x8;
+#endif
+ volatile ee_s32 seed4_volatile=ITERATIONS;
+ volatile ee_s32 seed5_volatile=0;
+/* Porting : Timing functions
+ How to capture time and convert to seconds must be ported to whatever is supported by the platform.
+ e.g. Read value from on board RTC, read value from cpu clock cycles performance counter etc.
+ Sample implementation for standard time.h and windows.h definitions included.
+*/
+CORETIMETYPE barebones_clock() {
+ #error "You must implement a method to measure time in barebones_clock()! This function should return current time.\n"
+}
+/* Define : TIMER_RES_DIVIDER
+ Divider to trade off timer resolution and total time that can be measured.
+
+ Use lower values to increase resolution, but make sure that overflow does not occur.
+ If there are issues with the return value overflowing, increase this value.
+ */
+#define GETMYTIME(_t) (*_t=barebones_clock())
+#define MYTIMEDIFF(fin,ini) ((fin)-(ini))
+#define TIMER_RES_DIVIDER 1
+#define SAMPLE_TIME_IMPLEMENTATION 1
+#define EE_TICKS_PER_SEC (CLOCKS_PER_SEC / TIMER_RES_DIVIDER)
+
+/** Define Host specific (POSIX), or target specific global time variables. */
+static CORETIMETYPE start_time_val, stop_time_val;
+
+/* Function : start_time
+ This function will be called right before starting the timed portion of the benchmark.
+
+ Implementation may be capturing a system timer (as implemented in the example code)
+ or zeroing some system parameters - e.g. setting the cpu clocks cycles to 0.
+*/
+void start_time(void) {
+ GETMYTIME(&start_time_val );
+}
+/* Function : stop_time
+ This function will be called right after ending the timed portion of the benchmark.
+
+ Implementation may be capturing a system timer (as implemented in the example code)
+ or other system parameters - e.g. reading the current value of cpu cycles counter.
+*/
+void stop_time(void) {
+ GETMYTIME(&stop_time_val );
+}
+/* Function : get_time
+ Return an abstract "ticks" number that signifies time on the system.
+
+ Actual value returned may be cpu cycles, milliseconds or any other value,
+ as long as it can be converted to seconds by <time_in_secs>.
+ This methodology is taken to accomodate any hardware or simulated platform.
+ The sample implementation returns millisecs by default,
+ and the resolution is controlled by <TIMER_RES_DIVIDER>
+*/
+CORE_TICKS get_time(void) {
+ CORE_TICKS elapsed=(CORE_TICKS)(MYTIMEDIFF(stop_time_val, start_time_val));
+ return elapsed;
+}
+/* Function : time_in_secs
+ Convert the value returned by get_time to seconds.
+
+ The <secs_ret> type is used to accomodate systems with no support for floating point.
+ Default implementation implemented by the EE_TICKS_PER_SEC macro above.
+*/
+secs_ret time_in_secs(CORE_TICKS ticks) {
+ secs_ret retval=((secs_ret)ticks) / (secs_ret)EE_TICKS_PER_SEC;
+ return retval;
+}
+
+ee_u32 default_num_contexts=1;
+
+/* Function : portable_init
+ Target specific initialization code
+ Test for some common mistakes.
+*/
+void portable_init(core_portable *p, int *argc, char *argv[])
+{
+ #error "Call board initialization routines in portable init (if needed), in particular initialize UART!\n"
+ if (sizeof(ee_ptr_int) != sizeof(ee_u8 *)) {
+ ee_printf("ERROR! Please define ee_ptr_int to a type that holds a pointer!\n");
+ }
+ if (sizeof(ee_u32) != 4) {
+ ee_printf("ERROR! Please define ee_u32 to a 32b unsigned type!\n");
+ }
+ p->portable_id=1;
+}
+/* Function : portable_fini
+ Target specific final code
+*/
+void portable_fini(core_portable *p)
+{
+ p->portable_id=0;
+}
+
+
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/barebones/core_portme.h b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/barebones/core_portme.h
new file mode 100755
index 0000000..23a1558
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/barebones/core_portme.h
@@ -0,0 +1,199 @@
+/*
+Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Original Author: Shay Gal-on
+*/
+/* Topic : Description
+ This file contains configuration constants required to execute on different platforms
+*/
+#ifndef CORE_PORTME_H
+#define CORE_PORTME_H
+/************************/
+/* Data types and settings */
+/************************/
+/* Configuration : HAS_FLOAT
+ Define to 1 if the platform supports floating point.
+*/
+#ifndef HAS_FLOAT
+#define HAS_FLOAT 1
+#endif
+/* Configuration : HAS_TIME_H
+ Define to 1 if platform has the time.h header file,
+ and implementation of functions thereof.
+*/
+#ifndef HAS_TIME_H
+#define HAS_TIME_H 1
+#endif
+/* Configuration : USE_CLOCK
+ Define to 1 if platform has the time.h header file,
+ and implementation of functions thereof.
+*/
+#ifndef USE_CLOCK
+#define USE_CLOCK 1
+#endif
+/* Configuration : HAS_STDIO
+ Define to 1 if the platform has stdio.h.
+*/
+#ifndef HAS_STDIO
+#define HAS_STDIO 0
+#endif
+/* Configuration : HAS_PRINTF
+ Define to 1 if the platform has stdio.h and implements the printf function.
+*/
+#ifndef HAS_PRINTF
+#define HAS_PRINTF 0
+#endif
+
+
+/* Definitions : COMPILER_VERSION, COMPILER_FLAGS, MEM_LOCATION
+ Initialize these strings per platform
+*/
+#ifndef COMPILER_VERSION
+ #ifdef __GNUC__
+ #define COMPILER_VERSION "GCC"__VERSION__
+ #else
+ #define COMPILER_VERSION "Please put compiler version here (e.g. gcc 4.1)"
+ #endif
+#endif
+#ifndef COMPILER_FLAGS
+ #define COMPILER_FLAGS FLAGS_STR /* "Please put compiler flags here (e.g. -o3)" */
+#endif
+#ifndef MEM_LOCATION
+ #define MEM_LOCATION "STACK"
+#endif
+
+/* Data Types :
+ To avoid compiler issues, define the data types that need ot be used for 8b, 16b and 32b in <core_portme.h>.
+
+ *Imprtant* :
+ ee_ptr_int needs to be the data type used to hold pointers, otherwise coremark may fail!!!
+*/
+typedef signed short ee_s16;
+typedef unsigned short ee_u16;
+typedef signed int ee_s32;
+typedef double ee_f32;
+typedef unsigned char ee_u8;
+typedef unsigned int ee_u32;
+typedef ee_u32 ee_ptr_int;
+typedef size_t ee_size_t;
+#define NULL ((void *)0)
+/* align_mem :
+ This macro is used to align an offset to point to a 32b value. It is used in the Matrix algorithm to initialize the input memory blocks.
+*/
+#define align_mem(x) (void *)(4 + (((ee_ptr_int)(x) - 1) & ~3))
+
+/* Configuration : CORE_TICKS
+ Define type of return from the timing functions.
+ */
+#define CORETIMETYPE ee_u32
+typedef ee_u32 CORE_TICKS;
+
+/* Configuration : SEED_METHOD
+ Defines method to get seed values that cannot be computed at compile time.
+
+ Valid values :
+ SEED_ARG - from command line.
+ SEED_FUNC - from a system function.
+ SEED_VOLATILE - from volatile variables.
+*/
+#ifndef SEED_METHOD
+#define SEED_METHOD SEED_VOLATILE
+#endif
+
+/* Configuration : MEM_METHOD
+ Defines method to get a block of memry.
+
+ Valid values :
+ MEM_MALLOC - for platforms that implement malloc and have malloc.h.
+ MEM_STATIC - to use a static memory array.
+ MEM_STACK - to allocate the data block on the stack (NYI).
+*/
+#ifndef MEM_METHOD
+#define MEM_METHOD MEM_STACK
+#endif
+
+/* Configuration : MULTITHREAD
+ Define for parallel execution
+
+ Valid values :
+ 1 - only one context (default).
+ N>1 - will execute N copies in parallel.
+
+ Note :
+ If this flag is defined to more then 1, an implementation for launching parallel contexts must be defined.
+
+ Two sample implementations are provided. Use <USE_PTHREAD> or <USE_FORK> to enable them.
+
+ It is valid to have a different implementation of <core_start_parallel> and <core_end_parallel> in <core_portme.c>,
+ to fit a particular architecture.
+*/
+#ifndef MULTITHREAD
+#define MULTITHREAD 1
+#define USE_PTHREAD 0
+#define USE_FORK 0
+#define USE_SOCKET 0
+#endif
+
+/* Configuration : MAIN_HAS_NOARGC
+ Needed if platform does not support getting arguments to main.
+
+ Valid values :
+ 0 - argc/argv to main is supported
+ 1 - argc/argv to main is not supported
+
+ Note :
+ This flag only matters if MULTITHREAD has been defined to a value greater then 1.
+*/
+#ifndef MAIN_HAS_NOARGC
+#define MAIN_HAS_NOARGC 0
+#endif
+
+/* Configuration : MAIN_HAS_NORETURN
+ Needed if platform does not support returning a value from main.
+
+ Valid values :
+ 0 - main returns an int, and return value will be 0.
+ 1 - platform does not support returning a value from main
+*/
+#ifndef MAIN_HAS_NORETURN
+#define MAIN_HAS_NORETURN 0
+#endif
+
+/* Variable : default_num_contexts
+ Not used for this simple port, must cintain the value 1.
+*/
+extern ee_u32 default_num_contexts;
+
+typedef struct CORE_PORTABLE_S {
+ ee_u8 portable_id;
+} core_portable;
+
+/* target specific init/fini */
+void portable_init(core_portable *p, int *argc, char *argv[]);
+void portable_fini(core_portable *p);
+
+#if !defined(PROFILE_RUN) && !defined(PERFORMANCE_RUN) && !defined(VALIDATION_RUN)
+#if (TOTAL_DATA_SIZE==1200)
+#define PROFILE_RUN 1
+#elif (TOTAL_DATA_SIZE==2000)
+#define PERFORMANCE_RUN 1
+#else
+#define VALIDATION_RUN 1
+#endif
+#endif
+
+int ee_printf(const char *fmt, ...);
+
+#endif /* CORE_PORTME_H */
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/barebones/core_portme.mak b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/barebones/core_portme.mak
new file mode 100755
index 0000000..8159469
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/barebones/core_portme.mak
@@ -0,0 +1,87 @@
+# Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# Original Author: Shay Gal-on
+
+#File : core_portme.mak
+
+# Flag : OUTFLAG
+# Use this flag to define how to to get an executable (e.g -o)
+OUTFLAG= -o
+# Flag : CC
+# Use this flag to define compiler to use
+CC = gcc
+# Flag : LD
+# Use this flag to define compiler to use
+LD = gld
+# Flag : AS
+# Use this flag to define compiler to use
+AS = gas
+# Flag : CFLAGS
+# Use this flag to define compiler options. Note, you can add compiler options from the command line using XCFLAGS="other flags"
+PORT_CFLAGS = -O0 -g
+FLAGS_STR = "$(PORT_CFLAGS) $(XCFLAGS) $(XLFLAGS) $(LFLAGS_END)"
+CFLAGS = $(PORT_CFLAGS) -I$(PORT_DIR) -I. -DFLAGS_STR=\"$(FLAGS_STR)\"
+#Flag : LFLAGS_END
+# Define any libraries needed for linking or other flags that should come at the end of the link line (e.g. linker scripts).
+# Note : On certain platforms, the default clock_gettime implementation is supported but requires linking of librt.
+SEPARATE_COMPILE=1
+# Flag : SEPARATE_COMPILE
+# You must also define below how to create an object file, and how to link.
+OBJOUT = -o
+LFLAGS =
+ASFLAGS =
+OFLAG = -o
+COUT = -c
+
+LFLAGS_END =
+# Flag : PORT_SRCS
+# Port specific source files can be added here
+# You may also need cvt.c if the fcvt functions are not provided as intrinsics by your compiler!
+PORT_SRCS = $(PORT_DIR)/core_portme.c $(PORT_DIR)/ee_printf.c
+vpath %.c $(PORT_DIR)
+vpath %.s $(PORT_DIR)
+
+# Flag : LOAD
+# For a simple port, we assume self hosted compile and run, no load needed.
+
+# Flag : RUN
+# For a simple port, we assume self hosted compile and run, simple invocation of the executable
+
+LOAD = echo "Please set LOAD to the process of loading the executable to the flash"
+RUN = echo "Please set LOAD to the process of running the executable (e.g. via jtag, or board reset)"
+
+OEXT = .o
+EXE = .bin
+
+$(OPATH)$(PORT_DIR)/%$(OEXT) : %.c
+ $(CC) $(CFLAGS) $(XCFLAGS) $(COUT) $< $(OBJOUT) $@
+
+$(OPATH)%$(OEXT) : %.c
+ $(CC) $(CFLAGS) $(XCFLAGS) $(COUT) $< $(OBJOUT) $@
+
+$(OPATH)$(PORT_DIR)/%$(OEXT) : %.s
+ $(AS) $(ASFLAGS) $< $(OBJOUT) $@
+
+# Target : port_pre% and port_post%
+# For the purpose of this simple port, no pre or post steps needed.
+
+.PHONY : port_prebuild port_postbuild port_prerun port_postrun port_preload port_postload
+port_pre% port_post% :
+
+# FLAG : OPATH
+# Path to the output folder. Default - current folder.
+OPATH = ./
+MKDIR = mkdir -p
+
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/barebones/cvt.c b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/barebones/cvt.c
new file mode 100755
index 0000000..ee0506d
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/barebones/cvt.c
@@ -0,0 +1,117 @@
+/*
+Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+*/
+#include <math.h>
+#define CVTBUFSIZE 80
+static char CVTBUF[CVTBUFSIZE];
+
+static char *cvt(double arg, int ndigits, int *decpt, int *sign, char *buf, int eflag)
+{
+ int r2;
+ double fi, fj;
+ char *p, *p1;
+
+ if (ndigits < 0) ndigits = 0;
+ if (ndigits >= CVTBUFSIZE - 1) ndigits = CVTBUFSIZE - 2;
+ r2 = 0;
+ *sign = 0;
+ p = &buf[0];
+ if (arg < 0)
+ {
+ *sign = 1;
+ arg = -arg;
+ }
+ arg = modf(arg, &fi);
+ p1 = &buf[CVTBUFSIZE];
+
+ if (fi != 0)
+ {
+ p1 = &buf[CVTBUFSIZE];
+ while (fi != 0)
+ {
+ fj = modf(fi / 10, &fi);
+ *--p1 = (int)((fj + .03) * 10) + '0';
+ r2++;
+ }
+ while (p1 < &buf[CVTBUFSIZE]) *p++ = *p1++;
+ }
+ else if (arg > 0)
+ {
+ while ((fj = arg * 10) < 1)
+ {
+ arg = fj;
+ r2--;
+ }
+ }
+ p1 = &buf[ndigits];
+ if (eflag == 0) p1 += r2;
+ *decpt = r2;
+ if (p1 < &buf[0])
+ {
+ buf[0] = '\0';
+ return buf;
+ }
+ while (p <= p1 && p < &buf[CVTBUFSIZE])
+ {
+ arg *= 10;
+ arg = modf(arg, &fj);
+ *p++ = (int) fj + '0';
+ }
+ if (p1 >= &buf[CVTBUFSIZE])
+ {
+ buf[CVTBUFSIZE - 1] = '\0';
+ return buf;
+ }
+ p = p1;
+ *p1 += 5;
+ while (*p1 > '9')
+ {
+ *p1 = '0';
+ if (p1 > buf)
+ ++*--p1;
+ else
+ {
+ *p1 = '1';
+ (*decpt)++;
+ if (eflag == 0)
+ {
+ if (p > buf) *p = '0';
+ p++;
+ }
+ }
+ }
+ *p = '\0';
+ return buf;
+}
+
+char *ecvt(double arg, int ndigits, int *decpt, int *sign)
+{
+ return cvt(arg, ndigits, decpt, sign, CVTBUF, 1);
+}
+
+char *ecvtbuf(double arg, int ndigits, int *decpt, int *sign, char *buf)
+{
+ return cvt(arg, ndigits, decpt, sign, buf, 1);
+}
+
+char *fcvt(double arg, int ndigits, int *decpt, int *sign)
+{
+ return cvt(arg, ndigits, decpt, sign, CVTBUF, 0);
+}
+
+char *fcvtbuf(double arg, int ndigits, int *decpt, int *sign, char *buf)
+{
+ return cvt(arg, ndigits, decpt, sign, buf, 0);
+}
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/barebones/ee_printf.c b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/barebones/ee_printf.c
new file mode 100755
index 0000000..b08f59d
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/barebones/ee_printf.c
@@ -0,0 +1,597 @@
+/*
+Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+*/
+
+#include <coremark.h>
+#include <stdarg.h>
+
+#define ZEROPAD (1<<0) /* Pad with zero */
+#define SIGN (1<<1) /* Unsigned/signed long */
+#define PLUS (1<<2) /* Show plus */
+#define SPACE (1<<3) /* Spacer */
+#define LEFT (1<<4) /* Left justified */
+#define HEX_PREP (1<<5) /* 0x */
+#define UPPERCASE (1<<6) /* 'ABCDEF' */
+
+#define is_digit(c) ((c) >= '0' && (c) <= '9')
+
+static char *digits = "0123456789abcdefghijklmnopqrstuvwxyz";
+static char *upper_digits = "0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ";
+static ee_size_t strnlen(const char *s, ee_size_t count);
+
+static ee_size_t strnlen(const char *s, ee_size_t count)
+{
+ const char *sc;
+ for (sc = s; *sc != '\0' && count--; ++sc);
+ return sc - s;
+}
+
+static int skip_atoi(const char **s)
+{
+ int i = 0;
+ while (is_digit(**s)) i = i*10 + *((*s)++) - '0';
+ return i;
+}
+
+static char *number(char *str, long num, int base, int size, int precision, int type)
+{
+ char c, sign, tmp[66];
+ char *dig = digits;
+ int i;
+
+ if (type & UPPERCASE) dig = upper_digits;
+ if (type & LEFT) type &= ~ZEROPAD;
+ if (base < 2 || base > 36) return 0;
+
+ c = (type & ZEROPAD) ? '0' : ' ';
+ sign = 0;
+ if (type & SIGN)
+ {
+ if (num < 0)
+ {
+ sign = '-';
+ num = -num;
+ size--;
+ }
+ else if (type & PLUS)
+ {
+ sign = '+';
+ size--;
+ }
+ else if (type & SPACE)
+ {
+ sign = ' ';
+ size--;
+ }
+ }
+
+ if (type & HEX_PREP)
+ {
+ if (base == 16)
+ size -= 2;
+ else if (base == 8)
+ size--;
+ }
+
+ i = 0;
+
+ if (num == 0)
+ tmp[i++] = '0';
+ else
+ {
+ while (num != 0)
+ {
+ tmp[i++] = dig[((unsigned long) num) % (unsigned) base];
+ num = ((unsigned long) num) / (unsigned) base;
+ }
+ }
+
+ if (i > precision) precision = i;
+ size -= precision;
+ if (!(type & (ZEROPAD | LEFT))) while (size-- > 0) *str++ = ' ';
+ if (sign) *str++ = sign;
+
+ if (type & HEX_PREP)
+ {
+ if (base == 8)
+ *str++ = '0';
+ else if (base == 16)
+ {
+ *str++ = '0';
+ *str++ = digits[33];
+ }
+ }
+
+ if (!(type & LEFT)) while (size-- > 0) *str++ = c;
+ while (i < precision--) *str++ = '0';
+ while (i-- > 0) *str++ = tmp[i];
+ while (size-- > 0) *str++ = ' ';
+
+ return str;
+}
+
+static char *eaddr(char *str, unsigned char *addr, int size, int precision, int type)
+{
+ char tmp[24];
+ char *dig = digits;
+ int i, len;
+
+ if (type & UPPERCASE) dig = upper_digits;
+ len = 0;
+ for (i = 0; i < 6; i++)
+ {
+ if (i != 0) tmp[len++] = ':';
+ tmp[len++] = dig[addr[i] >> 4];
+ tmp[len++] = dig[addr[i] & 0x0F];
+ }
+
+ if (!(type & LEFT)) while (len < size--) *str++ = ' ';
+ for (i = 0; i < len; ++i) *str++ = tmp[i];
+ while (len < size--) *str++ = ' ';
+
+ return str;
+}
+
+static char *iaddr(char *str, unsigned char *addr, int size, int precision, int type)
+{
+ char tmp[24];
+ int i, n, len;
+
+ len = 0;
+ for (i = 0; i < 4; i++)
+ {
+ if (i != 0) tmp[len++] = '.';
+ n = addr[i];
+
+ if (n == 0)
+ tmp[len++] = digits[0];
+ else
+ {
+ if (n >= 100)
+ {
+ tmp[len++] = digits[n / 100];
+ n = n % 100;
+ tmp[len++] = digits[n / 10];
+ n = n % 10;
+ }
+ else if (n >= 10)
+ {
+ tmp[len++] = digits[n / 10];
+ n = n % 10;
+ }
+
+ tmp[len++] = digits[n];
+ }
+ }
+
+ if (!(type & LEFT)) while (len < size--) *str++ = ' ';
+ for (i = 0; i < len; ++i) *str++ = tmp[i];
+ while (len < size--) *str++ = ' ';
+
+ return str;
+}
+
+#if HAS_FLOAT
+
+char *ecvtbuf(double arg, int ndigits, int *decpt, int *sign, char *buf);
+char *fcvtbuf(double arg, int ndigits, int *decpt, int *sign, char *buf);
+static void ee_bufcpy(char *d, char *s, int count);
+
+void ee_bufcpy(char *pd, char *ps, int count) {
+ char *pe=ps+count;
+ while (ps!=pe)
+ *pd++=*ps++;
+}
+
+static void parse_float(double value, char *buffer, char fmt, int precision)
+{
+ int decpt, sign, exp, pos;
+ char *digits = NULL;
+ char cvtbuf[80];
+ int capexp = 0;
+ int magnitude;
+
+ if (fmt == 'G' || fmt == 'E')
+ {
+ capexp = 1;
+ fmt += 'a' - 'A';
+ }
+
+ if (fmt == 'g')
+ {
+ digits = ecvtbuf(value, precision, &decpt, &sign, cvtbuf);
+ magnitude = decpt - 1;
+ if (magnitude < -4 || magnitude > precision - 1)
+ {
+ fmt = 'e';
+ precision -= 1;
+ }
+ else
+ {
+ fmt = 'f';
+ precision -= decpt;
+ }
+ }
+
+ if (fmt == 'e')
+ {
+ digits = ecvtbuf(value, precision + 1, &decpt, &sign, cvtbuf);
+
+ if (sign) *buffer++ = '-';
+ *buffer++ = *digits;
+ if (precision > 0) *buffer++ = '.';
+ ee_bufcpy(buffer, digits + 1, precision);
+ buffer += precision;
+ *buffer++ = capexp ? 'E' : 'e';
+
+ if (decpt == 0)
+ {
+ if (value == 0.0)
+ exp = 0;
+ else
+ exp = -1;
+ }
+ else
+ exp = decpt - 1;
+
+ if (exp < 0)
+ {
+ *buffer++ = '-';
+ exp = -exp;
+ }
+ else
+ *buffer++ = '+';
+
+ buffer[2] = (exp % 10) + '0';
+ exp = exp / 10;
+ buffer[1] = (exp % 10) + '0';
+ exp = exp / 10;
+ buffer[0] = (exp % 10) + '0';
+ buffer += 3;
+ }
+ else if (fmt == 'f')
+ {
+ digits = fcvtbuf(value, precision, &decpt, &sign, cvtbuf);
+ if (sign) *buffer++ = '-';
+ if (*digits)
+ {
+ if (decpt <= 0)
+ {
+ *buffer++ = '0';
+ *buffer++ = '.';
+ for (pos = 0; pos < -decpt; pos++) *buffer++ = '0';
+ while (*digits) *buffer++ = *digits++;
+ }
+ else
+ {
+ pos = 0;
+ while (*digits)
+ {
+ if (pos++ == decpt) *buffer++ = '.';
+ *buffer++ = *digits++;
+ }
+ }
+ }
+ else
+ {
+ *buffer++ = '0';
+ if (precision > 0)
+ {
+ *buffer++ = '.';
+ for (pos = 0; pos < precision; pos++) *buffer++ = '0';
+ }
+ }
+ }
+
+ *buffer = '\0';
+}
+
+static void decimal_point(char *buffer)
+{
+ while (*buffer)
+ {
+ if (*buffer == '.') return;
+ if (*buffer == 'e' || *buffer == 'E') break;
+ buffer++;
+ }
+
+ if (*buffer)
+ {
+ int n = strnlen(buffer,256);
+ while (n > 0)
+ {
+ buffer[n + 1] = buffer[n];
+ n--;
+ }
+
+ *buffer = '.';
+ }
+ else
+ {
+ *buffer++ = '.';
+ *buffer = '\0';
+ }
+}
+
+static void cropzeros(char *buffer)
+{
+ char *stop;
+
+ while (*buffer && *buffer != '.') buffer++;
+ if (*buffer++)
+ {
+ while (*buffer && *buffer != 'e' && *buffer != 'E') buffer++;
+ stop = buffer--;
+ while (*buffer == '0') buffer--;
+ if (*buffer == '.') buffer--;
+ while (buffer!=stop)
+ *++buffer=0;
+ }
+}
+
+static char *flt(char *str, double num, int size, int precision, char fmt, int flags)
+{
+ char tmp[80];
+ char c, sign;
+ int n, i;
+
+ // Left align means no zero padding
+ if (flags & LEFT) flags &= ~ZEROPAD;
+
+ // Determine padding and sign char
+ c = (flags & ZEROPAD) ? '0' : ' ';
+ sign = 0;
+ if (flags & SIGN)
+ {
+ if (num < 0.0)
+ {
+ sign = '-';
+ num = -num;
+ size--;
+ }
+ else if (flags & PLUS)
+ {
+ sign = '+';
+ size--;
+ }
+ else if (flags & SPACE)
+ {
+ sign = ' ';
+ size--;
+ }
+ }
+
+ // Compute the precision value
+ if (precision < 0)
+ precision = 6; // Default precision: 6
+
+ // Convert floating point number to text
+ parse_float(num, tmp, fmt, precision);
+
+ if ((flags & HEX_PREP) && precision == 0) decimal_point(tmp);
+ if (fmt == 'g' && !(flags & HEX_PREP)) cropzeros(tmp);
+
+ n = strnlen(tmp,256);
+
+ // Output number with alignment and padding
+ size -= n;
+ if (!(flags & (ZEROPAD | LEFT))) while (size-- > 0) *str++ = ' ';
+ if (sign) *str++ = sign;
+ if (!(flags & LEFT)) while (size-- > 0) *str++ = c;
+ for (i = 0; i < n; i++) *str++ = tmp[i];
+ while (size-- > 0) *str++ = ' ';
+
+ return str;
+}
+
+#endif
+
+static int ee_vsprintf(char *buf, const char *fmt, va_list args)
+{
+ int len;
+ unsigned long num;
+ int i, base;
+ char *str;
+ char *s;
+
+ int flags; // Flags to number()
+
+ int field_width; // Width of output field
+ int precision; // Min. # of digits for integers; max number of chars for from string
+ int qualifier; // 'h', 'l', or 'L' for integer fields
+
+ for (str = buf; *fmt; fmt++)
+ {
+ if (*fmt != '%')
+ {
+ *str++ = *fmt;
+ continue;
+ }
+
+ // Process flags
+ flags = 0;
+repeat:
+ fmt++; // This also skips first '%'
+ switch (*fmt)
+ {
+ case '-': flags |= LEFT; goto repeat;
+ case '+': flags |= PLUS; goto repeat;
+ case ' ': flags |= SPACE; goto repeat;
+ case '#': flags |= HEX_PREP; goto repeat;
+ case '0': flags |= ZEROPAD; goto repeat;
+ }
+
+ // Get field width
+ field_width = -1;
+ if (is_digit(*fmt))
+ field_width = skip_atoi(&fmt);
+ else if (*fmt == '*')
+ {
+ fmt++;
+ field_width = va_arg(args, int);
+ if (field_width < 0)
+ {
+ field_width = -field_width;
+ flags |= LEFT;
+ }
+ }
+
+ // Get the precision
+ precision = -1;
+ if (*fmt == '.')
+ {
+ ++fmt;
+ if (is_digit(*fmt))
+ precision = skip_atoi(&fmt);
+ else if (*fmt == '*')
+ {
+ ++fmt;
+ precision = va_arg(args, int);
+ }
+ if (precision < 0) precision = 0;
+ }
+
+ // Get the conversion qualifier
+ qualifier = -1;
+ if (*fmt == 'l' || *fmt == 'L')
+ {
+ qualifier = *fmt;
+ fmt++;
+ }
+
+ // Default base
+ base = 10;
+
+ switch (*fmt)
+ {
+ case 'c':
+ if (!(flags & LEFT)) while (--field_width > 0) *str++ = ' ';
+ *str++ = (unsigned char) va_arg(args, int);
+ while (--field_width > 0) *str++ = ' ';
+ continue;
+
+ case 's':
+ s = va_arg(args, char *);
+ if (!s) s = "<NULL>";
+ len = strnlen(s, precision);
+ if (!(flags & LEFT)) while (len < field_width--) *str++ = ' ';
+ for (i = 0; i < len; ++i) *str++ = *s++;
+ while (len < field_width--) *str++ = ' ';
+ continue;
+
+ case 'p':
+ if (field_width == -1)
+ {
+ field_width = 2 * sizeof(void *);
+ flags |= ZEROPAD;
+ }
+ str = number(str, (unsigned long) va_arg(args, void *), 16, field_width, precision, flags);
+ continue;
+
+ case 'A':
+ flags |= UPPERCASE;
+
+ case 'a':
+ if (qualifier == 'l')
+ str = eaddr(str, va_arg(args, unsigned char *), field_width, precision, flags);
+ else
+ str = iaddr(str, va_arg(args, unsigned char *), field_width, precision, flags);
+ continue;
+
+ // Integer number formats - set up the flags and "break"
+ case 'o':
+ base = 8;
+ break;
+
+ case 'X':
+ flags |= UPPERCASE;
+
+ case 'x':
+ base = 16;
+ break;
+
+ case 'd':
+ case 'i':
+ flags |= SIGN;
+
+ case 'u':
+ break;
+
+#if HAS_FLOAT
+
+ case 'f':
+ str = flt(str, va_arg(args, double), field_width, precision, *fmt, flags | SIGN);
+ continue;
+
+#endif
+
+ default:
+ if (*fmt != '%') *str++ = '%';
+ if (*fmt)
+ *str++ = *fmt;
+ else
+ --fmt;
+ continue;
+ }
+
+ if (qualifier == 'l')
+ num = va_arg(args, unsigned long);
+ else if (flags & SIGN)
+ num = va_arg(args, int);
+ else
+ num = va_arg(args, unsigned int);
+
+ str = number(str, num, base, field_width, precision, flags);
+ }
+
+ *str = '\0';
+ return str - buf;
+}
+
+void uart_send_char(char c) {
+#error "You must implement the method uart_send_char to use this file!\n";
+/* Output of a char to a UART usually follows the following model:
+ Wait until UART is ready
+ Write char to UART
+ Wait until UART is done
+
+ Or in code:
+ while (*UART_CONTROL_ADDRESS != UART_READY);
+ *UART_DATA_ADDRESS = c;
+ while (*UART_CONTROL_ADDRESS != UART_READY);
+
+ Check the UART sample code on your platform or the board documentation.
+*/
+}
+
+int ee_printf(const char *fmt, ...)
+{
+ char buf[256],*p;
+ va_list args;
+ int n=0;
+
+ va_start(args, fmt);
+ ee_vsprintf(buf, fmt, args);
+ va_end(args);
+ p=buf;
+ while (*p) {
+ uart_send_char(*p);
+ n++;
+ p++;
+ }
+
+ return n;
+}
+
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/core_list_join.c b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/core_list_join.c
new file mode 100644
index 0000000..a515428
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/core_list_join.c
@@ -0,0 +1,495 @@
+/*
+Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Original Author: Shay Gal-on
+*/
+
+#include "coremark.h"
+/*
+Topic: Description
+ Benchmark using a linked list.
+
+ Linked list is a common data structure used in many applications.
+
+ For our purposes, this will excercise the memory units of the processor.
+ In particular, usage of the list pointers to find and alter data.
+
+ We are not using Malloc since some platforms do not support this library.
+
+ Instead, the memory block being passed in is used to create a list,
+ and the benchmark takes care not to add more items then can be
+ accomodated by the memory block. The porting layer will make sure
+ that we have a valid memory block.
+
+ All operations are done in place, without using any extra memory.
+
+ The list itself contains list pointers and pointers to data items.
+ Data items contain the following:
+
+ idx - An index that captures the initial order of the list.
+ data - Variable data initialized based on the input parameters. The 16b are divided as follows:
+ o Upper 8b are backup of original data.
+ o Bit 7 indicates if the lower 7 bits are to be used as is or calculated.
+ o Bits 0-2 indicate type of operation to perform to get a 7b value.
+ o Bits 3-6 provide input for the operation.
+
+*/
+
+/* local functions */
+
+list_head *core_list_find(list_head *list,list_data *info);
+list_head *core_list_reverse(list_head *list);
+list_head *core_list_remove(list_head *item);
+list_head *core_list_undo_remove(list_head *item_removed, list_head *item_modified);
+list_head *core_list_insert_new(list_head *insert_point
+ , list_data *info, list_head **memblock, list_data **datablock
+ , list_head *memblock_end, list_data *datablock_end);
+typedef ee_s32(*list_cmp)(list_data *a, list_data *b, core_results *res);
+list_head *core_list_mergesort(list_head *list, list_cmp cmp, core_results *res);
+
+ee_s16 calc_func(ee_s16 *pdata, core_results *res) {
+ ee_s16 data=*pdata;
+ ee_s16 retval;
+ ee_u8 optype=(data>>7) & 1; /* bit 7 indicates if the function result has been cached */
+ if (optype) /* if cached, use cache */
+ return (data & 0x007f);
+ else { /* otherwise calculate and cache the result */
+ ee_s16 flag=data & 0x7; /* bits 0-2 is type of function to perform */
+ ee_s16 dtype=((data>>3) & 0xf); /* bits 3-6 is specific data for the operation */
+ dtype |= dtype << 4; /* replicate the lower 4 bits to get an 8b value */
+ switch (flag) {
+ case 0:
+ if (dtype<0x22) /* set min period for bit corruption */
+ dtype=0x22;
+ retval=core_bench_state(res->size,res->memblock[3],res->seed1,res->seed2,dtype,res->crc);
+ if (res->crcstate==0)
+ res->crcstate=retval;
+ break;
+ case 1:
+ retval=core_bench_matrix(&(res->mat),dtype,res->crc);
+ if (res->crcmatrix==0)
+ res->crcmatrix=retval;
+ break;
+ default:
+ retval=data;
+ break;
+ }
+ res->crc=crcu16(retval,res->crc);
+ retval &= 0x007f;
+ *pdata = (data & 0xff00) | 0x0080 | retval; /* cache the result */
+ return retval;
+ }
+}
+/* Function: cmp_complex
+ Compare the data item in a list cell.
+
+ Can be used by mergesort.
+*/
+ee_s32 cmp_complex(list_data *a, list_data *b, core_results *res) {
+ ee_s16 val1=calc_func(&(a->data16),res);
+ ee_s16 val2=calc_func(&(b->data16),res);
+ return val1 - val2;
+}
+
+/* Function: cmp_idx
+ Compare the idx item in a list cell, and regen the data.
+
+ Can be used by mergesort.
+*/
+ee_s32 cmp_idx(list_data *a, list_data *b, core_results *res) {
+ if (res==NULL) {
+ a->data16 = (a->data16 & 0xff00) | (0x00ff & (a->data16>>8));
+ b->data16 = (b->data16 & 0xff00) | (0x00ff & (b->data16>>8));
+ }
+ return a->idx - b->idx;
+}
+
+void copy_info(list_data *to,list_data *from) {
+ to->data16=from->data16;
+ to->idx=from->idx;
+}
+
+/* Benchmark for linked list:
+ - Try to find multiple data items.
+ - List sort
+ - Operate on data from list (crc)
+ - Single remove/reinsert
+ * At the end of this function, the list is back to original state
+*/
+ee_u16 core_bench_list(core_results *res, ee_s16 finder_idx) {
+ ee_u16 retval=0;
+ ee_u16 found=0,missed=0;
+ list_head *list=res->list;
+ ee_s16 find_num=res->seed3;
+ list_head *this_find;
+ list_head *finder, *remover;
+ list_data info;
+ ee_s16 i;
+
+ info.idx=finder_idx;
+ /* find <find_num> values in the list, and change the list each time (reverse and cache if value found) */
+ for (i=0; i<find_num; i++) {
+ info.data16= (i & 0xff) ;
+ this_find=core_list_find(list,&info);
+ list=core_list_reverse(list);
+ if (this_find==NULL) {
+ missed++;
+ retval+=(list->next->info->data16 >> 8) & 1;
+ }
+ else {
+ found++;
+ if (this_find->info->data16 & 0x1) /* use found value */
+ retval+=(this_find->info->data16 >> 9) & 1;
+ /* and cache next item at the head of the list (if any) */
+ if (this_find->next != NULL) {
+ finder = this_find->next;
+ this_find->next = finder->next;
+ finder->next=list->next;
+ list->next=finder;
+ }
+ }
+ if (info.idx>=0)
+ info.idx++;
+#if CORE_DEBUG
+ ee_printf("List find %d: [%d,%d,%d]\n",i,retval,missed,found);
+#endif
+ }
+ retval+=found*4-missed;
+ /* sort the list by data content and remove one item*/
+ if (finder_idx>0)
+ list=core_list_mergesort(list,cmp_complex,res);
+ remover=core_list_remove(list->next);
+ /* CRC data content of list from location of index N forward, and then undo remove */
+ finder=core_list_find(list,&info);
+ if (!finder)
+ finder=list->next;
+ while (finder) {
+ retval=crc16(list->info->data16,retval);
+ finder=finder->next;
+ }
+#if CORE_DEBUG
+ ee_printf("List sort 1: %04x\n",retval);
+#endif
+ remover=core_list_undo_remove(remover,list->next);
+ /* sort the list by index, in effect returning the list to original state */
+ list=core_list_mergesort(list,cmp_idx,NULL);
+ /* CRC data content of list */
+ finder=list->next;
+ while (finder) {
+ retval=crc16(list->info->data16,retval);
+ finder=finder->next;
+ }
+#if CORE_DEBUG
+ ee_printf("List sort 2: %04x\n",retval);
+#endif
+ return retval;
+}
+/* Function: core_list_init
+ Initialize list with data.
+
+ Parameters:
+ blksize - Size of memory to be initialized.
+ memblock - Pointer to memory block.
+ seed - Actual values chosen depend on the seed parameter.
+ The seed parameter MUST be supplied from a source that cannot be determined at compile time
+
+ Returns:
+ Pointer to the head of the list.
+
+*/
+list_head *core_list_init(ee_u32 blksize, list_head *memblock, ee_s16 seed) {
+ /* calculated pointers for the list */
+ ee_u32 per_item=16+sizeof(struct list_data_s);
+ ee_u32 size=(blksize/per_item)-2; /* to accomodate systems with 64b pointers, and make sure same code is executed, set max list elements */
+ list_head *memblock_end=memblock+size;
+ list_data *datablock=(list_data *)(memblock_end);
+ list_data *datablock_end=datablock+size;
+ /* some useful variables */
+ ee_u32 i;
+ list_head *finder,*list=memblock;
+ list_data info;
+
+ /* create a fake items for the list head and tail */
+ list->next=NULL;
+ list->info=datablock;
+ list->info->idx=0x0000;
+ list->info->data16=(ee_s16)0x8080;
+ memblock++;
+ datablock++;
+ info.idx=0x7fff;
+ info.data16=(ee_s16)0xffff;
+ core_list_insert_new(list,&info,&memblock,&datablock,memblock_end,datablock_end);
+
+ /* then insert size items */
+ for (i=0; i<size; i++) {
+ ee_u16 datpat=((ee_u16)(seed^i) & 0xf);
+ ee_u16 dat=(datpat<<3) | (i&0x7); /* alternate between algorithms */
+ info.data16=(dat<<8) | dat; /* fill the data with actual data and upper bits with rebuild value */
+ core_list_insert_new(list,&info,&memblock,&datablock,memblock_end,datablock_end);
+ }
+ /* and now index the list so we know initial seed order of the list */
+ finder=list->next;
+ i=1;
+ while (finder->next!=NULL) {
+ if (i<size/5) /* first 20% of the list in order */
+ finder->info->idx=i++;
+ else {
+ ee_u16 pat=(ee_u16)(i++ ^ seed); /* get a pseudo random number */
+ finder->info->idx=0x3fff & (((i & 0x07) << 8) | pat); /* make sure the mixed items end up after the ones in sequence */
+ }
+ finder=finder->next;
+ }
+ list = core_list_mergesort(list,cmp_idx,NULL);
+#if CORE_DEBUG
+ ee_printf("Initialized list:\n");
+ finder=list;
+ while (finder) {
+ ee_printf("[%04x,%04x]",finder->info->idx,(ee_u16)finder->info->data16);
+ finder=finder->next;
+ }
+ ee_printf("\n");
+#endif
+ return list;
+}
+
+/* Function: core_list_insert
+ Insert an item to the list
+
+ Parameters:
+ insert_point - where to insert the item.
+ info - data for the cell.
+ memblock - pointer for the list header
+ datablock - pointer for the list data
+ memblock_end - end of region for list headers
+ datablock_end - end of region for list data
+
+ Returns:
+ Pointer to new item.
+*/
+list_head *core_list_insert_new(list_head *insert_point, list_data *info, list_head **memblock, list_data **datablock
+ , list_head *memblock_end, list_data *datablock_end) {
+ list_head *newitem;
+
+ if ((*memblock+1) >= memblock_end)
+ return NULL;
+ if ((*datablock+1) >= datablock_end)
+ return NULL;
+
+ newitem=*memblock;
+ (*memblock)++;
+ newitem->next=insert_point->next;
+ insert_point->next=newitem;
+
+ newitem->info=*datablock;
+ (*datablock)++;
+ copy_info(newitem->info,info);
+
+ return newitem;
+}
+
+/* Function: core_list_remove
+ Remove an item from the list.
+
+ Operation:
+ For a singly linked list, remove by copying the data from the next item
+ over to the current cell, and unlinking the next item.
+
+ Note:
+ since there is always a fake item at the end of the list, no need to check for NULL.
+
+ Returns:
+ Removed item.
+*/
+list_head *core_list_remove(list_head *item) {
+ list_data *tmp;
+ list_head *ret=item->next;
+ /* swap data pointers */
+ tmp=item->info;
+ item->info=ret->info;
+ ret->info=tmp;
+ /* and eliminate item */
+ item->next=item->next->next;
+ ret->next=NULL;
+ return ret;
+}
+
+/* Function: core_list_undo_remove
+ Undo a remove operation.
+
+ Operation:
+ Since we want each iteration of the benchmark to be exactly the same,
+ we need to be able to undo a remove.
+ Link the removed item back into the list, and switch the info items.
+
+ Parameters:
+ item_removed - Return value from the <core_list_remove>
+ item_modified - List item that was modified during <core_list_remove>
+
+ Returns:
+ The item that was linked back to the list.
+
+*/
+list_head *core_list_undo_remove(list_head *item_removed, list_head *item_modified) {
+ list_data *tmp;
+ /* swap data pointers */
+ tmp=item_removed->info;
+ item_removed->info=item_modified->info;
+ item_modified->info=tmp;
+ /* and insert item */
+ item_removed->next=item_modified->next;
+ item_modified->next=item_removed;
+ return item_removed;
+}
+
+/* Function: core_list_find
+ Find an item in the list
+
+ Operation:
+ Find an item by idx (if not 0) or specific data value
+
+ Parameters:
+ list - list head
+ info - idx or data to find
+
+ Returns:
+ Found item, or NULL if not found.
+*/
+list_head *core_list_find(list_head *list,list_data *info) {
+ if (info->idx>=0) {
+ while (list && (list->info->idx != info->idx))
+ list=list->next;
+ return list;
+ } else {
+ while (list && ((list->info->data16 & 0xff) != info->data16))
+ list=list->next;
+ return list;
+ }
+}
+/* Function: core_list_reverse
+ Reverse a list
+
+ Operation:
+ Rearrange the pointers so the list is reversed.
+
+ Parameters:
+ list - list head
+ info - idx or data to find
+
+ Returns:
+ Found item, or NULL if not found.
+*/
+
+list_head *core_list_reverse(list_head *list) {
+ list_head *next=NULL, *tmp;
+ while (list) {
+ tmp=list->next;
+ list->next=next;
+ next=list;
+ list=tmp;
+ }
+ return next;
+}
+/* Function: core_list_mergesort
+ Sort the list in place without recursion.
+
+ Description:
+ Use mergesort, as for linked list this is a realistic solution.
+ Also, since this is aimed at embedded, care was taken to use iterative rather then recursive algorithm.
+ The sort can either return the list to original order (by idx) ,
+ or use the data item to invoke other other algorithms and change the order of the list.
+
+ Parameters:
+ list - list to be sorted.
+ cmp - cmp function to use
+
+ Returns:
+ New head of the list.
+
+ Note:
+ We have a special header for the list that will always be first,
+ but the algorithm could theoretically modify where the list starts.
+
+ */
+list_head *core_list_mergesort(list_head *list, list_cmp cmp, core_results *res) {
+ list_head *p, *q, *e, *tail;
+ ee_s32 insize, nmerges, psize, qsize, i;
+
+ insize = 1;
+
+ while (1) {
+ p = list;
+ list = NULL;
+ tail = NULL;
+
+ nmerges = 0; /* count number of merges we do in this pass */
+
+ while (p) {
+ nmerges++; /* there exists a merge to be done */
+ /* step `insize' places along from p */
+ q = p;
+ psize = 0;
+ for (i = 0; i < insize; i++) {
+ psize++;
+ q = q->next;
+ if (!q) break;
+ }
+
+ /* if q hasn't fallen off end, we have two lists to merge */
+ qsize = insize;
+
+ /* now we have two lists; merge them */
+ while (psize > 0 || (qsize > 0 && q)) {
+
+ /* decide whether next element of merge comes from p or q */
+ if (psize == 0) {
+ /* p is empty; e must come from q. */
+ e = q; q = q->next; qsize--;
+ } else if (qsize == 0 || !q) {
+ /* q is empty; e must come from p. */
+ e = p; p = p->next; psize--;
+ } else if (cmp(p->info,q->info,res) <= 0) {
+ /* First element of p is lower (or same); e must come from p. */
+ e = p; p = p->next; psize--;
+ } else {
+ /* First element of q is lower; e must come from q. */
+ e = q; q = q->next; qsize--;
+ }
+
+ /* add the next element to the merged list */
+ if (tail) {
+ tail->next = e;
+ } else {
+ list = e;
+ }
+ tail = e;
+ }
+
+ /* now p has stepped `insize' places along, and q has too */
+ p = q;
+ }
+
+ tail->next = NULL;
+
+ /* If we have done only one merge, we're finished. */
+ if (nmerges <= 1) /* allow for nmerges==0, the empty list case */
+ return list;
+
+ /* Otherwise repeat, merging lists twice the size */
+ insize *= 2;
+ }
+#if COMPILER_REQUIRES_SORT_RETURN
+ return list;
+#endif
+}
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/core_main.c b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/core_main.c
new file mode 100644
index 0000000..cca596c
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/core_main.c
@@ -0,0 +1,362 @@
+/*
+Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Original Author: Shay Gal-on
+*/
+
+/* File: core_main.c
+ This file contains the framework to acquire a block of memory, seed initial parameters, tun t he benchmark and report the results.
+*/
+#include "coremark.h"
+
+/* Function: iterate
+ Run the benchmark for a specified number of iterations.
+
+ Operation:
+ For each type of benchmarked algorithm:
+ a - Initialize the data block for the algorithm.
+ b - Execute the algorithm N times.
+
+ Returns:
+ NULL.
+*/
+static ee_u16 list_known_crc[] = {(ee_u16)0xd4b0,(ee_u16)0x3340,(ee_u16)0x6a79,(ee_u16)0xe714,(ee_u16)0xe3c1};
+static ee_u16 matrix_known_crc[] = {(ee_u16)0xbe52,(ee_u16)0x1199,(ee_u16)0x5608,(ee_u16)0x1fd7,(ee_u16)0x0747};
+static ee_u16 state_known_crc[] = {(ee_u16)0x5e47,(ee_u16)0x39bf,(ee_u16)0xe5a4,(ee_u16)0x8e3a,(ee_u16)0x8d84};
+void *iterate(void *pres) {
+ ee_u32 i;
+ ee_u16 crc;
+ core_results *res=(core_results *)pres;
+ ee_u32 iterations=res->iterations;
+ res->crc=0;
+ res->crclist=0;
+ res->crcmatrix=0;
+ res->crcstate=0;
+
+ for (i=0; i<iterations; i++) {
+ crc=core_bench_list(res,1);
+ res->crc=crcu16(crc,res->crc);
+ crc=core_bench_list(res,-1);
+ res->crc=crcu16(crc,res->crc);
+ if (i==0) res->crclist=res->crc;
+ }
+ return NULL;
+}
+
+#if (SEED_METHOD==SEED_ARG)
+ee_s32 get_seed_args(int i, int argc, char *argv[]);
+#define get_seed(x) (ee_s16)get_seed_args(x,argc,argv)
+#define get_seed_32(x) get_seed_args(x,argc,argv)
+#else /* via function or volatile */
+ee_s32 get_seed_32(int i);
+#define get_seed(x) (ee_s16)get_seed_32(x)
+#endif
+
+#if (MEM_METHOD==MEM_STATIC)
+ee_u8 static_memblk[TOTAL_DATA_SIZE];
+#endif
+char *mem_name[3] = {"Static","Heap","Stack"};
+/* Function: main
+ Main entry routine for the benchmark.
+ This function is responsible for the following steps:
+
+ 1 - Initialize input seeds from a source that cannot be determined at compile time.
+ 2 - Initialize memory block for use.
+ 3 - Run and time the benchmark.
+ 4 - Report results, testing the validity of the output if the seeds are known.
+
+ Arguments:
+ 1 - first seed : Any value
+ 2 - second seed : Must be identical to first for iterations to be identical
+ 3 - third seed : Any value, should be at least an order of magnitude less then the input size, but bigger then 32.
+ 4 - Iterations : Special, if set to 0, iterations will be automatically determined such that the benchmark will run between 10 to 100 secs
+
+*/
+
+#if MAIN_HAS_NOARGC
+MAIN_RETURN_TYPE main(void) {
+ int argc=0;
+ char *argv[1];
+#else
+MAIN_RETURN_TYPE main(int argc, char *argv[]) {
+#endif
+ ee_u16 i,j=0,num_algorithms=0;
+ ee_s16 known_id=-1,total_errors=0;
+ ee_u16 seedcrc=0;
+ CORE_TICKS total_time;
+ core_results results[MULTITHREAD];
+#if (MEM_METHOD==MEM_STACK)
+ ee_u8 stack_memblock[TOTAL_DATA_SIZE*MULTITHREAD];
+#endif
+ /* first call any initializations needed */
+ portable_init(&(results[0].port), &argc, argv);
+ /* First some checks to make sure benchmark will run ok */
+ if (sizeof(struct list_head_s)>128) {
+ ee_printf("list_head structure too big for comparable data!\n");
+ return MAIN_RETURN_VAL;
+ }
+ results[0].seed1=get_seed(1);
+ results[0].seed2=get_seed(2);
+ results[0].seed3=get_seed(3);
+ results[0].iterations=get_seed_32(4);
+#if CORE_DEBUG
+ results[0].iterations=1;
+#endif
+ results[0].execs=get_seed_32(5);
+ if (results[0].execs==0) { /* if not supplied, execute all algorithms */
+ results[0].execs=ALL_ALGORITHMS_MASK;
+ }
+ /* put in some default values based on one seed only for easy testing */
+ if ((results[0].seed1==0) && (results[0].seed2==0) && (results[0].seed3==0)) { /* validation run */
+ results[0].seed1=0;
+ results[0].seed2=0;
+ results[0].seed3=0x66;
+ }
+ if ((results[0].seed1==1) && (results[0].seed2==0) && (results[0].seed3==0)) { /* perfromance run */
+ results[0].seed1=0x3415;
+ results[0].seed2=0x3415;
+ results[0].seed3=0x66;
+ }
+#if (MEM_METHOD==MEM_STATIC)
+ results[0].memblock[0]=(void *)static_memblk;
+ results[0].size=TOTAL_DATA_SIZE;
+ results[0].err=0;
+ #if (MULTITHREAD>1)
+ #error "Cannot use a static data area with multiple contexts!"
+ #endif
+#elif (MEM_METHOD==MEM_MALLOC)
+ for (i=0 ; i<MULTITHREAD; i++) {
+ ee_s32 malloc_override=get_seed(7);
+ if (malloc_override != 0)
+ results[i].size=malloc_override;
+ else
+ results[i].size=TOTAL_DATA_SIZE;
+ results[i].memblock[0]=portable_malloc(results[i].size);
+ results[i].seed1=results[0].seed1;
+ results[i].seed2=results[0].seed2;
+ results[i].seed3=results[0].seed3;
+ results[i].err=0;
+ results[i].execs=results[0].execs;
+ }
+#elif (MEM_METHOD==MEM_STACK)
+ for (i=0 ; i<MULTITHREAD; i++) {
+ results[i].memblock[0]=stack_memblock+i*TOTAL_DATA_SIZE;
+ results[i].size=TOTAL_DATA_SIZE;
+ results[i].seed1=results[0].seed1;
+ results[i].seed2=results[0].seed2;
+ results[i].seed3=results[0].seed3;
+ results[i].err=0;
+ results[i].execs=results[0].execs;
+ }
+#else
+#error "Please define a way to initialize a memory block."
+#endif
+ /* Data init */
+ /* Find out how space much we have based on number of algorithms */
+ for (i=0; i<NUM_ALGORITHMS; i++) {
+ if ((1<<(ee_u32)i) & results[0].execs)
+ num_algorithms++;
+ }
+ for (i=0 ; i<MULTITHREAD; i++)
+ results[i].size=results[i].size/num_algorithms;
+ /* Assign pointers */
+ for (i=0; i<NUM_ALGORITHMS; i++) {
+ ee_u32 ctx;
+ if ((1<<(ee_u32)i) & results[0].execs) {
+ for (ctx=0 ; ctx<MULTITHREAD; ctx++)
+ results[ctx].memblock[i+1]=(char *)(results[ctx].memblock[0])+results[0].size*j;
+ j++;
+ }
+ }
+ /* call inits */
+ for (i=0 ; i<MULTITHREAD; i++) {
+ if (results[i].execs & ID_LIST) {
+ results[i].list=core_list_init(results[0].size,results[i].memblock[1],results[i].seed1);
+ }
+ if (results[i].execs & ID_MATRIX) {
+ core_init_matrix(results[0].size, results[i].memblock[2], (ee_s32)results[i].seed1 | (((ee_s32)results[i].seed2) << 16), &(results[i].mat) );
+ }
+ if (results[i].execs & ID_STATE) {
+ core_init_state(results[0].size,results[i].seed1,results[i].memblock[3]);
+ }
+ }
+
+ /* automatically determine number of iterations if not set */
+ if (results[0].iterations==0) {
+ secs_ret secs_passed=0;
+ ee_u32 divisor;
+ results[0].iterations=1;
+ while (secs_passed < (secs_ret)1) {
+ results[0].iterations*=10;
+ start_time();
+ iterate(&results[0]);
+ stop_time();
+ secs_passed=time_in_secs(get_time());
+ }
+ /* now we know it executes for at least 1 sec, set actual run time at about 10 secs */
+ divisor=(ee_u32)secs_passed;
+ if (divisor==0) /* some machines cast float to int as 0 since this conversion is not defined by ANSI, but we know at least one second passed */
+ divisor=1;
+ results[0].iterations*=1+10/divisor;
+ }
+ /* perform actual benchmark */
+ start_time();
+#if (MULTITHREAD>1)
+ if (default_num_contexts>MULTITHREAD) {
+ default_num_contexts=MULTITHREAD;
+ }
+ for (i=0 ; i<default_num_contexts; i++) {
+ results[i].iterations=results[0].iterations;
+ results[i].execs=results[0].execs;
+ core_start_parallel(&results[i]);
+ }
+ for (i=0 ; i<default_num_contexts; i++) {
+ core_stop_parallel(&results[i]);
+ }
+#else
+ iterate(&results[0]);
+#endif
+ stop_time();
+ total_time=get_time();
+ /* get a function of the input to report */
+ seedcrc=crc16(results[0].seed1,seedcrc);
+ seedcrc=crc16(results[0].seed2,seedcrc);
+ seedcrc=crc16(results[0].seed3,seedcrc);
+ seedcrc=crc16(results[0].size,seedcrc);
+
+ switch (seedcrc) { /* test known output for common seeds */
+ case 0x8a02: /* seed1=0, seed2=0, seed3=0x66, size 2000 per algorithm */
+ known_id=0;
+ ee_printf("6k performance run parameters for coremark.\n");
+ break;
+ case 0x7b05: /* seed1=0x3415, seed2=0x3415, seed3=0x66, size 2000 per algorithm */
+ known_id=1;
+ ee_printf("6k validation run parameters for coremark.\n");
+ break;
+ case 0x4eaf: /* seed1=0x8, seed2=0x8, seed3=0x8, size 400 per algorithm */
+ known_id=2;
+ ee_printf("Profile generation run parameters for coremark.\n");
+ break;
+ case 0xe9f5: /* seed1=0, seed2=0, seed3=0x66, size 666 per algorithm */
+ known_id=3;
+ ee_printf("2K performance run parameters for coremark.\n");
+ break;
+ case 0x18f2: /* seed1=0x3415, seed2=0x3415, seed3=0x66, size 666 per algorithm */
+ known_id=4;
+ ee_printf("2K validation run parameters for coremark.\n");
+ break;
+ default:
+ total_errors=-1;
+ break;
+ }
+ if (known_id>=0) {
+ for (i=0 ; i<default_num_contexts; i++) {
+ results[i].err=0;
+ if ((results[i].execs & ID_LIST) &&
+ (results[i].crclist!=list_known_crc[known_id])) {
+ ee_printf("[%u]ERROR! list crc 0x%04x - should be 0x%04x\n",i,results[i].crclist,list_known_crc[known_id]);
+ results[i].err++;
+ }
+ if ((results[i].execs & ID_MATRIX) &&
+ (results[i].crcmatrix!=matrix_known_crc[known_id])) {
+ ee_printf("[%u]ERROR! matrix crc 0x%04x - should be 0x%04x\n",i,results[i].crcmatrix,matrix_known_crc[known_id]);
+ results[i].err++;
+ }
+ if ((results[i].execs & ID_STATE) &&
+ (results[i].crcstate!=state_known_crc[known_id])) {
+ ee_printf("[%u]ERROR! state crc 0x%04x - should be 0x%04x\n",i,results[i].crcstate,state_known_crc[known_id]);
+ results[i].err++;
+ }
+ total_errors+=results[i].err;
+ }
+ }
+ total_errors+=check_data_types();
+ /* and report results */
+ ee_printf("CoreMark Size : %lu\n", (long unsigned) results[0].size);
+ ee_printf("Total ticks : %lu\n", (long unsigned) total_time);
+#if HAS_FLOAT
+ ee_printf("Total time (secs): %f\n",time_in_secs(total_time));
+ if (time_in_secs(total_time) > 0)
+ ee_printf("Iterations/Sec : %f\n",default_num_contexts*results[0].iterations/time_in_secs(total_time));
+#else
+ ee_printf("Total time (secs): %d\n",time_in_secs(total_time));
+ if (time_in_secs(total_time) > 0)
+ ee_printf("Iterations/Sec : %d\n",default_num_contexts*results[0].iterations/time_in_secs(total_time));
+#endif
+ // Remove error report if execution time low.
+ // On Ibex a few loops suffices to get an accurate result. With this check in
+ // the verilator simulation of coremark will report failure (unless left running
+ // for a significant number of iterations greatly increasing simulation time).
+ // The other error checking is useful to determine if the benchmark has been
+ // broken in some way which is masked if this check is left in.
+ //if (time_in_secs(total_time) < 10) {
+ // ee_printf("ERROR! Must execute for at least 10 secs for a valid result!\n");
+ // total_errors++;
+ //}
+
+ ee_printf("Iterations : %lu\n", (long unsigned) default_num_contexts*results[0].iterations);
+ ee_printf("Compiler version : %s\n",COMPILER_VERSION);
+ ee_printf("Compiler flags : %s\n",COMPILER_FLAGS);
+#if (MULTITHREAD>1)
+ ee_printf("Parallel %s : %d\n",PARALLEL_METHOD,default_num_contexts);
+#endif
+ ee_printf("Memory location : %s\n",MEM_LOCATION);
+ /* output for verification */
+ ee_printf("seedcrc : 0x%04x\n",seedcrc);
+ if (results[0].execs & ID_LIST)
+ for (i=0 ; i<default_num_contexts; i++)
+ ee_printf("[%d]crclist : 0x%04x\n",i,results[i].crclist);
+ if (results[0].execs & ID_MATRIX)
+ for (i=0 ; i<default_num_contexts; i++)
+ ee_printf("[%d]crcmatrix : 0x%04x\n",i,results[i].crcmatrix);
+ if (results[0].execs & ID_STATE)
+ for (i=0 ; i<default_num_contexts; i++)
+ ee_printf("[%d]crcstate : 0x%04x\n",i,results[i].crcstate);
+ for (i=0 ; i<default_num_contexts; i++)
+ ee_printf("[%d]crcfinal : 0x%04x\n",i,results[i].crc);
+ if (total_errors==0) {
+ ee_printf("Correct operation validated. See README.md for run and reporting rules.\n");
+#if HAS_FLOAT
+ if (known_id==3) {
+ ee_printf("CoreMark 1.0 : %f / %s %s",default_num_contexts*results[0].iterations/time_in_secs(total_time),COMPILER_VERSION,COMPILER_FLAGS);
+#if defined(MEM_LOCATION) && !defined(MEM_LOCATION_UNSPEC)
+ ee_printf(" / %s",MEM_LOCATION);
+#else
+ ee_printf(" / %s",mem_name[MEM_METHOD]);
+#endif
+
+#if (MULTITHREAD>1)
+ ee_printf(" / %d:%s",default_num_contexts,PARALLEL_METHOD);
+#endif
+ ee_printf("\n");
+ }
+#endif
+ }
+ if (total_errors>0)
+ ee_printf("Errors detected\n");
+ if (total_errors<0)
+ ee_printf("Cannot validate operation for these seed values, please compare with results on a known platform.\n");
+
+#if (MEM_METHOD==MEM_MALLOC)
+ for (i=0 ; i<MULTITHREAD; i++)
+ portable_free(results[i].memblock[0]);
+#endif
+ /* And last call any target specific code for finalizing */
+ portable_fini(&(results[0].port));
+
+ return MAIN_RETURN_VAL;
+}
+
+
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/core_matrix.c b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/core_matrix.c
new file mode 100644
index 0000000..ebfa1d7
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/core_matrix.c
@@ -0,0 +1,308 @@
+/*
+Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Original Author: Shay Gal-on
+*/
+
+#include "coremark.h"
+/*
+Topic: Description
+ Matrix manipulation benchmark
+
+ This very simple algorithm forms the basis of many more complex algorithms.
+
+ The tight inner loop is the focus of many optimizations (compiler as well as hardware based)
+ and is thus relevant for embedded processing.
+
+ The total available data space will be divided to 3 parts:
+ NxN Matrix A - initialized with small values (upper 3/4 of the bits all zero).
+ NxN Matrix B - initialized with medium values (upper half of the bits all zero).
+ NxN Matrix C - used for the result.
+
+ The actual values for A and B must be derived based on input that is not available at compile time.
+*/
+ee_s16 matrix_test(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B, MATDAT val);
+ee_s16 matrix_sum(ee_u32 N, MATRES *C, MATDAT clipval);
+void matrix_mul_const(ee_u32 N, MATRES *C, MATDAT *A, MATDAT val);
+void matrix_mul_vect(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B);
+void matrix_mul_matrix(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B);
+void matrix_mul_matrix_bitextract(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B);
+void matrix_add_const(ee_u32 N, MATDAT *A, MATDAT val);
+
+#define matrix_test_next(x) (x+1)
+#define matrix_clip(x,y) ((y) ? (x) & 0x0ff : (x) & 0x0ffff)
+#define matrix_big(x) (0xf000 | (x))
+#define bit_extract(x,from,to) (((x)>>(from)) & (~(0xffffffff << (to))))
+
+#if CORE_DEBUG
+void printmat(MATDAT *A, ee_u32 N, char *name) {
+ ee_u32 i,j;
+ ee_printf("Matrix %s [%dx%d]:\n",name,N,N);
+ for (i=0; i<N; i++) {
+ for (j=0; j<N; j++) {
+ if (j!=0)
+ ee_printf(",");
+ ee_printf("%d",A[i*N+j]);
+ }
+ ee_printf("\n");
+ }
+}
+void printmatC(MATRES *C, ee_u32 N, char *name) {
+ ee_u32 i,j;
+ ee_printf("Matrix %s [%dx%d]:\n",name,N,N);
+ for (i=0; i<N; i++) {
+ for (j=0; j<N; j++) {
+ if (j!=0)
+ ee_printf(",");
+ ee_printf("%d",C[i*N+j]);
+ }
+ ee_printf("\n");
+ }
+}
+#endif
+/* Function: core_bench_matrix
+ Benchmark function
+
+ Iterate <matrix_test> N times,
+ changing the matrix values slightly by a constant amount each time.
+*/
+ee_u16 core_bench_matrix(mat_params *p, ee_s16 seed, ee_u16 crc) {
+ ee_u32 N=p->N;
+ MATRES *C=p->C;
+ MATDAT *A=p->A;
+ MATDAT *B=p->B;
+ MATDAT val=(MATDAT)seed;
+
+ crc=crc16(matrix_test(N,C,A,B,val),crc);
+
+ return crc;
+}
+
+/* Function: matrix_test
+ Perform matrix manipulation.
+
+ Parameters:
+ N - Dimensions of the matrix.
+ C - memory for result matrix.
+ A - input matrix
+ B - operator matrix (not changed during operations)
+
+ Returns:
+ A CRC value that captures all results calculated in the function.
+ In particular, crc of the value calculated on the result matrix
+ after each step by <matrix_sum>.
+
+ Operation:
+
+ 1 - Add a constant value to all elements of a matrix.
+ 2 - Multiply a matrix by a constant.
+ 3 - Multiply a matrix by a vector.
+ 4 - Multiply a matrix by a matrix.
+ 5 - Add a constant value to all elements of a matrix.
+
+ After the last step, matrix A is back to original contents.
+*/
+ee_s16 matrix_test(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B, MATDAT val) {
+ ee_u16 crc=0;
+ MATDAT clipval=matrix_big(val);
+
+ matrix_add_const(N,A,val); /* make sure data changes */
+#if CORE_DEBUG
+ printmat(A,N,"matrix_add_const");
+#endif
+ matrix_mul_const(N,C,A,val);
+ crc=crc16(matrix_sum(N,C,clipval),crc);
+#if CORE_DEBUG
+ printmatC(C,N,"matrix_mul_const");
+#endif
+ matrix_mul_vect(N,C,A,B);
+ crc=crc16(matrix_sum(N,C,clipval),crc);
+#if CORE_DEBUG
+ printmatC(C,N,"matrix_mul_vect");
+#endif
+ matrix_mul_matrix(N,C,A,B);
+ crc=crc16(matrix_sum(N,C,clipval),crc);
+#if CORE_DEBUG
+ printmatC(C,N,"matrix_mul_matrix");
+#endif
+ matrix_mul_matrix_bitextract(N,C,A,B);
+ crc=crc16(matrix_sum(N,C,clipval),crc);
+#if CORE_DEBUG
+ printmatC(C,N,"matrix_mul_matrix_bitextract");
+#endif
+
+ matrix_add_const(N,A,-val); /* return matrix to initial value */
+ return crc;
+}
+
+/* Function : matrix_init
+ Initialize the memory block for matrix benchmarking.
+
+ Parameters:
+ blksize - Size of memory to be initialized.
+ memblk - Pointer to memory block.
+ seed - Actual values chosen depend on the seed parameter.
+ p - pointers to <mat_params> containing initialized matrixes.
+
+ Returns:
+ Matrix dimensions.
+
+ Note:
+ The seed parameter MUST be supplied from a source that cannot be determined at compile time
+*/
+ee_u32 core_init_matrix(ee_u32 blksize, void *memblk, ee_s32 seed, mat_params *p) {
+ ee_u32 N=0;
+ MATDAT *A;
+ MATDAT *B;
+ ee_s32 order=1;
+ MATDAT val;
+ ee_u32 i=0,j=0;
+ if (seed==0)
+ seed=1;
+ while (j<blksize) {
+ i++;
+ j=i*i*2*4;
+ }
+ N=i-1;
+ A=(MATDAT *)align_mem(memblk);
+ B=A+N*N;
+
+ for (i=0; i<N; i++) {
+ for (j=0; j<N; j++) {
+ seed = ( ( order * seed ) % 65536 );
+ val = (seed + order);
+ val=matrix_clip(val,0);
+ B[i*N+j] = val;
+ val = (val + order);
+ val=matrix_clip(val,1);
+ A[i*N+j] = val;
+ order++;
+ }
+ }
+
+ p->A=A;
+ p->B=B;
+ p->C=(MATRES *)align_mem(B+N*N);
+ p->N=N;
+#if CORE_DEBUG
+ printmat(A,N,"A");
+ printmat(B,N,"B");
+#endif
+ return N;
+}
+
+/* Function: matrix_sum
+ Calculate a function that depends on the values of elements in the matrix.
+
+ For each element, accumulate into a temporary variable.
+
+ As long as this value is under the parameter clipval,
+ add 1 to the result if the element is bigger then the previous.
+
+ Otherwise, reset the accumulator and add 10 to the result.
+*/
+ee_s16 matrix_sum(ee_u32 N, MATRES *C, MATDAT clipval) {
+ MATRES tmp=0,prev=0,cur=0;
+ ee_s16 ret=0;
+ ee_u32 i,j;
+ for (i=0; i<N; i++) {
+ for (j=0; j<N; j++) {
+ cur=C[i*N+j];
+ tmp+=cur;
+ if (tmp>clipval) {
+ ret+=10;
+ tmp=0;
+ } else {
+ ret += (cur>prev) ? 1 : 0;
+ }
+ prev=cur;
+ }
+ }
+ return ret;
+}
+
+/* Function: matrix_mul_const
+ Multiply a matrix by a constant.
+ This could be used as a scaler for instance.
+*/
+void matrix_mul_const(ee_u32 N, MATRES *C, MATDAT *A, MATDAT val) {
+ ee_u32 i,j;
+ for (i=0; i<N; i++) {
+ for (j=0; j<N; j++) {
+ C[i*N+j]=(MATRES)A[i*N+j] * (MATRES)val;
+ }
+ }
+}
+
+/* Function: matrix_add_const
+ Add a constant value to all elements of a matrix.
+*/
+void matrix_add_const(ee_u32 N, MATDAT *A, MATDAT val) {
+ ee_u32 i,j;
+ for (i=0; i<N; i++) {
+ for (j=0; j<N; j++) {
+ A[i*N+j] += val;
+ }
+ }
+}
+
+/* Function: matrix_mul_vect
+ Multiply a matrix by a vector.
+ This is common in many simple filters (e.g. fir where a vector of coefficients is applied to the matrix.)
+*/
+void matrix_mul_vect(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B) {
+ ee_u32 i,j;
+ for (i=0; i<N; i++) {
+ C[i]=0;
+ for (j=0; j<N; j++) {
+ C[i]+=(MATRES)A[i*N+j] * (MATRES)B[j];
+ }
+ }
+}
+
+/* Function: matrix_mul_matrix
+ Multiply a matrix by a matrix.
+ Basic code is used in many algorithms, mostly with minor changes such as scaling.
+*/
+void matrix_mul_matrix(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B) {
+ ee_u32 i,j,k;
+ for (i=0; i<N; i++) {
+ for (j=0; j<N; j++) {
+ C[i*N+j]=0;
+ for(k=0;k<N;k++)
+ {
+ C[i*N+j]+=(MATRES)A[i*N+k] * (MATRES)B[k*N+j];
+ }
+ }
+ }
+}
+
+/* Function: matrix_mul_matrix_bitextract
+ Multiply a matrix by a matrix, and extract some bits from the result.
+ Basic code is used in many algorithms, mostly with minor changes such as scaling.
+*/
+void matrix_mul_matrix_bitextract(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B) {
+ ee_u32 i,j,k;
+ for (i=0; i<N; i++) {
+ for (j=0; j<N; j++) {
+ C[i*N+j]=0;
+ for(k=0;k<N;k++)
+ {
+ MATRES tmp=(MATRES)A[i*N+k] * (MATRES)B[k*N+j];
+ C[i*N+j]+=bit_extract(tmp,2,4)*bit_extract(tmp,5,7);
+ }
+ }
+ }
+}
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/core_state.c b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/core_state.c
new file mode 100644
index 0000000..bb31933
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/core_state.c
@@ -0,0 +1,277 @@
+/*
+Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Original Author: Shay Gal-on
+*/
+
+#include "coremark.h"
+/* local functions */
+enum CORE_STATE core_state_transition( ee_u8 **instr , ee_u32 *transition_count);
+
+/*
+Topic: Description
+ Simple state machines like this one are used in many embedded products.
+
+ For more complex state machines, sometimes a state transition table implementation is used instead,
+ trading speed of direct coding for ease of maintenance.
+
+ Since the main goal of using a state machine in CoreMark is to excercise the switch/if behaviour,
+ we are using a small moore machine.
+
+ In particular, this machine tests type of string input,
+ trying to determine whether the input is a number or something else.
+ (see core_state.png).
+*/
+
+/* Function: core_bench_state
+ Benchmark function
+
+ Go over the input twice, once direct, and once after introducing some corruption.
+*/
+ee_u16 core_bench_state(ee_u32 blksize, ee_u8 *memblock,
+ ee_s16 seed1, ee_s16 seed2, ee_s16 step, ee_u16 crc)
+{
+ ee_u32 final_counts[NUM_CORE_STATES];
+ ee_u32 track_counts[NUM_CORE_STATES];
+ ee_u8 *p=memblock;
+ ee_u32 i;
+
+
+#if CORE_DEBUG
+ ee_printf("State Bench: %d,%d,%d,%04x\n",seed1,seed2,step,crc);
+#endif
+ for (i=0; i<NUM_CORE_STATES; i++) {
+ final_counts[i]=track_counts[i]=0;
+ }
+ /* run the state machine over the input */
+ while (*p!=0) {
+ enum CORE_STATE fstate=core_state_transition(&p,track_counts);
+ final_counts[fstate]++;
+#if CORE_DEBUG
+ ee_printf("%d,",fstate);
+ }
+ ee_printf("\n");
+#else
+ }
+#endif
+ p=memblock;
+ while (p < (memblock+blksize)) { /* insert some corruption */
+ if (*p!=',')
+ *p^=(ee_u8)seed1;
+ p+=step;
+ }
+ p=memblock;
+ /* run the state machine over the input again */
+ while (*p!=0) {
+ enum CORE_STATE fstate=core_state_transition(&p,track_counts);
+ final_counts[fstate]++;
+#if CORE_DEBUG
+ ee_printf("%d,",fstate);
+ }
+ ee_printf("\n");
+#else
+ }
+#endif
+ p=memblock;
+ while (p < (memblock+blksize)) { /* undo corruption is seed1 and seed2 are equal */
+ if (*p!=',')
+ *p^=(ee_u8)seed2;
+ p+=step;
+ }
+ /* end timing */
+ for (i=0; i<NUM_CORE_STATES; i++) {
+ crc=crcu32(final_counts[i],crc);
+ crc=crcu32(track_counts[i],crc);
+ }
+ return crc;
+}
+
+/* Default initialization patterns */
+static ee_u8 *intpat[4] ={(ee_u8 *)"5012",(ee_u8 *)"1234",(ee_u8 *)"-874",(ee_u8 *)"+122"};
+static ee_u8 *floatpat[4]={(ee_u8 *)"35.54400",(ee_u8 *)".1234500",(ee_u8 *)"-110.700",(ee_u8 *)"+0.64400"};
+static ee_u8 *scipat[4] ={(ee_u8 *)"5.500e+3",(ee_u8 *)"-.123e-2",(ee_u8 *)"-87e+832",(ee_u8 *)"+0.6e-12"};
+static ee_u8 *errpat[4] ={(ee_u8 *)"T0.3e-1F",(ee_u8 *)"-T.T++Tq",(ee_u8 *)"1T3.4e4z",(ee_u8 *)"34.0e-T^"};
+
+/* Function: core_init_state
+ Initialize the input data for the state machine.
+
+ Populate the input with several predetermined strings, interspersed.
+ Actual patterns chosen depend on the seed parameter.
+
+ Note:
+ The seed parameter MUST be supplied from a source that cannot be determined at compile time
+*/
+void core_init_state(ee_u32 size, ee_s16 seed, ee_u8 *p) {
+ ee_u32 total=0,next=0,i;
+ ee_u8 *buf=0;
+#if CORE_DEBUG
+ ee_u8 *start=p;
+ ee_printf("State: %d,%d\n",size,seed);
+#endif
+ size--;
+ next=0;
+ while ((total+next+1)<size) {
+ if (next>0) {
+ for(i=0;i<next;i++)
+ *(p+total+i)=buf[i];
+ *(p+total+i)=',';
+ total+=next+1;
+ }
+ seed++;
+ switch (seed & 0x7) {
+ case 0: /* int */
+ case 1: /* int */
+ case 2: /* int */
+ buf=intpat[(seed>>3) & 0x3];
+ next=4;
+ break;
+ case 3: /* float */
+ case 4: /* float */
+ buf=floatpat[(seed>>3) & 0x3];
+ next=8;
+ break;
+ case 5: /* scientific */
+ case 6: /* scientific */
+ buf=scipat[(seed>>3) & 0x3];
+ next=8;
+ break;
+ case 7: /* invalid */
+ buf=errpat[(seed>>3) & 0x3];
+ next=8;
+ break;
+ default: /* Never happen, just to make some compilers happy */
+ break;
+ }
+ }
+ size++;
+ while (total<size) { /* fill the rest with 0 */
+ *(p+total)=0;
+ total++;
+ }
+#if CORE_DEBUG
+ ee_printf("State Input: %s\n",start);
+#endif
+}
+
+static ee_u8 ee_isdigit(ee_u8 c) {
+ ee_u8 retval;
+ retval = ((c>='0') & (c<='9')) ? 1 : 0;
+ return retval;
+}
+
+/* Function: core_state_transition
+ Actual state machine.
+
+ The state machine will continue scanning until either:
+ 1 - an invalid input is detcted.
+ 2 - a valid number has been detected.
+
+ The input pointer is updated to point to the end of the token, and the end state is returned (either specific format determined or invalid).
+*/
+
+enum CORE_STATE core_state_transition( ee_u8 **instr , ee_u32 *transition_count) {
+ ee_u8 *str=*instr;
+ ee_u8 NEXT_SYMBOL;
+ enum CORE_STATE state=CORE_START;
+ for( ; *str && state != CORE_INVALID; str++ ) {
+ NEXT_SYMBOL = *str;
+ if (NEXT_SYMBOL==',') /* end of this input */ {
+ str++;
+ break;
+ }
+ switch(state) {
+ case CORE_START:
+ if(ee_isdigit(NEXT_SYMBOL)) {
+ state = CORE_INT;
+ }
+ else if( NEXT_SYMBOL == '+' || NEXT_SYMBOL == '-' ) {
+ state = CORE_S1;
+ }
+ else if( NEXT_SYMBOL == '.' ) {
+ state = CORE_FLOAT;
+ }
+ else {
+ state = CORE_INVALID;
+ transition_count[CORE_INVALID]++;
+ }
+ transition_count[CORE_START]++;
+ break;
+ case CORE_S1:
+ if(ee_isdigit(NEXT_SYMBOL)) {
+ state = CORE_INT;
+ transition_count[CORE_S1]++;
+ }
+ else if( NEXT_SYMBOL == '.' ) {
+ state = CORE_FLOAT;
+ transition_count[CORE_S1]++;
+ }
+ else {
+ state = CORE_INVALID;
+ transition_count[CORE_S1]++;
+ }
+ break;
+ case CORE_INT:
+ if( NEXT_SYMBOL == '.' ) {
+ state = CORE_FLOAT;
+ transition_count[CORE_INT]++;
+ }
+ else if(!ee_isdigit(NEXT_SYMBOL)) {
+ state = CORE_INVALID;
+ transition_count[CORE_INT]++;
+ }
+ break;
+ case CORE_FLOAT:
+ if( NEXT_SYMBOL == 'E' || NEXT_SYMBOL == 'e' ) {
+ state = CORE_S2;
+ transition_count[CORE_FLOAT]++;
+ }
+ else if(!ee_isdigit(NEXT_SYMBOL)) {
+ state = CORE_INVALID;
+ transition_count[CORE_FLOAT]++;
+ }
+ break;
+ case CORE_S2:
+ if( NEXT_SYMBOL == '+' || NEXT_SYMBOL == '-' ) {
+ state = CORE_EXPONENT;
+ transition_count[CORE_S2]++;
+ }
+ else {
+ state = CORE_INVALID;
+ transition_count[CORE_S2]++;
+ }
+ break;
+ case CORE_EXPONENT:
+ if(ee_isdigit(NEXT_SYMBOL)) {
+ state = CORE_SCIENTIFIC;
+ transition_count[CORE_EXPONENT]++;
+ }
+ else {
+ state = CORE_INVALID;
+ transition_count[CORE_EXPONENT]++;
+ }
+ break;
+ case CORE_SCIENTIFIC:
+ if(!ee_isdigit(NEXT_SYMBOL)) {
+ state = CORE_INVALID;
+ transition_count[CORE_INVALID]++;
+ }
+ break;
+ default:
+ break;
+ }
+ }
+ *instr=str;
+ return state;
+}
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/core_util.c b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/core_util.c
new file mode 100644
index 0000000..581adcc
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/core_util.c
@@ -0,0 +1,210 @@
+/*
+Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Original Author: Shay Gal-on
+*/
+
+#include "coremark.h"
+/* Function: get_seed
+ Get a values that cannot be determined at compile time.
+
+ Since different embedded systems and compilers are used, 3 different methods are provided:
+ 1 - Using a volatile variable. This method is only valid if the compiler is forced to generate code that
+ reads the value of a volatile variable from memory at run time.
+ Please note, if using this method, you would need to modify core_portme.c to generate training profile.
+ 2 - Command line arguments. This is the preferred method if command line arguments are supported.
+ 3 - System function. If none of the first 2 methods is available on the platform,
+ a system function which is not a stub can be used.
+
+ e.g. read the value on GPIO pins connected to switches, or invoke special simulator functions.
+*/
+#if (SEED_METHOD==SEED_VOLATILE)
+ extern volatile ee_s32 seed1_volatile;
+ extern volatile ee_s32 seed2_volatile;
+ extern volatile ee_s32 seed3_volatile;
+ extern volatile ee_s32 seed4_volatile;
+ extern volatile ee_s32 seed5_volatile;
+ ee_s32 get_seed_32(int i) {
+ ee_s32 retval;
+ switch (i) {
+ case 1:
+ retval=seed1_volatile;
+ break;
+ case 2:
+ retval=seed2_volatile;
+ break;
+ case 3:
+ retval=seed3_volatile;
+ break;
+ case 4:
+ retval=seed4_volatile;
+ break;
+ case 5:
+ retval=seed5_volatile;
+ break;
+ default:
+ retval=0;
+ break;
+ }
+ return retval;
+ }
+#elif (SEED_METHOD==SEED_ARG)
+ee_s32 parseval(char *valstring) {
+ ee_s32 retval=0;
+ ee_s32 neg=1;
+ int hexmode=0;
+ if (*valstring == '-') {
+ neg=-1;
+ valstring++;
+ }
+ if ((valstring[0] == '0') && (valstring[1] == 'x')) {
+ hexmode=1;
+ valstring+=2;
+ }
+ /* first look for digits */
+ if (hexmode) {
+ while (((*valstring >= '0') && (*valstring <= '9')) || ((*valstring >= 'a') && (*valstring <= 'f'))) {
+ ee_s32 digit=*valstring-'0';
+ if (digit>9)
+ digit=10+*valstring-'a';
+ retval*=16;
+ retval+=digit;
+ valstring++;
+ }
+ } else {
+ while ((*valstring >= '0') && (*valstring <= '9')) {
+ ee_s32 digit=*valstring-'0';
+ retval*=10;
+ retval+=digit;
+ valstring++;
+ }
+ }
+ /* now add qualifiers */
+ if (*valstring=='K')
+ retval*=1024;
+ if (*valstring=='M')
+ retval*=1024*1024;
+
+ retval*=neg;
+ return retval;
+}
+
+ee_s32 get_seed_args(int i, int argc, char *argv[]) {
+ if (argc>i)
+ return parseval(argv[i]);
+ return 0;
+}
+
+#elif (SEED_METHOD==SEED_FUNC)
+/* If using OS based function, you must define and implement the functions below in core_portme.h and core_portme.c ! */
+ee_s32 get_seed_32(int i) {
+ ee_s32 retval;
+ switch (i) {
+ case 1:
+ retval=portme_sys1();
+ break;
+ case 2:
+ retval=portme_sys2();
+ break;
+ case 3:
+ retval=portme_sys3();
+ break;
+ case 4:
+ retval=portme_sys4();
+ break;
+ case 5:
+ retval=portme_sys5();
+ break;
+ default:
+ retval=0;
+ break;
+ }
+ return retval;
+}
+#endif
+
+/* Function: crc*
+ Service functions to calculate 16b CRC code.
+
+*/
+ee_u16 crcu8(ee_u8 data, ee_u16 crc )
+{
+ ee_u8 i=0,x16=0,carry=0;
+
+ for (i = 0; i < 8; i++)
+ {
+ x16 = (ee_u8)((data & 1) ^ ((ee_u8)crc & 1));
+ data >>= 1;
+
+ if (x16 == 1)
+ {
+ crc ^= 0x4002;
+ carry = 1;
+ }
+ else
+ carry = 0;
+ crc >>= 1;
+ if (carry)
+ crc |= 0x8000;
+ else
+ crc &= 0x7fff;
+ }
+ return crc;
+}
+ee_u16 crcu16(ee_u16 newval, ee_u16 crc) {
+ crc=crcu8( (ee_u8) (newval) ,crc);
+ crc=crcu8( (ee_u8) ((newval)>>8) ,crc);
+ return crc;
+}
+ee_u16 crcu32(ee_u32 newval, ee_u16 crc) {
+ crc=crc16((ee_s16) newval ,crc);
+ crc=crc16((ee_s16) (newval>>16) ,crc);
+ return crc;
+}
+ee_u16 crc16(ee_s16 newval, ee_u16 crc) {
+ return crcu16((ee_u16)newval, crc);
+}
+
+ee_u8 check_data_types() {
+ ee_u8 retval=0;
+ if (sizeof(ee_u8) != 1) {
+ ee_printf("ERROR: ee_u8 is not an 8b datatype!\n");
+ retval++;
+ }
+ if (sizeof(ee_u16) != 2) {
+ ee_printf("ERROR: ee_u16 is not a 16b datatype!\n");
+ retval++;
+ }
+ if (sizeof(ee_s16) != 2) {
+ ee_printf("ERROR: ee_s16 is not a 16b datatype!\n");
+ retval++;
+ }
+ if (sizeof(ee_s32) != 4) {
+ ee_printf("ERROR: ee_s32 is not a 32b datatype!\n");
+ retval++;
+ }
+ if (sizeof(ee_u32) != 4) {
+ ee_printf("ERROR: ee_u32 is not a 32b datatype!\n");
+ retval++;
+ }
+ if (sizeof(ee_ptr_int) != sizeof(int *)) {
+ ee_printf("ERROR: ee_ptr_int is not a datatype that holds an int pointer!\n");
+ retval++;
+ }
+ if (retval>0) {
+ ee_printf("ERROR: Please modify the datatypes in core_portme.h!\n");
+ }
+ return retval;
+}
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/coremark.h b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/coremark.h
new file mode 100644
index 0000000..29b775a
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/coremark.h
@@ -0,0 +1,174 @@
+/*
+Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Original Author: Shay Gal-on
+*/
+
+/* Topic: Description
+ This file contains declarations of the various benchmark functions.
+*/
+
+/* Configuration: TOTAL_DATA_SIZE
+ Define total size for data algorithms will operate on
+*/
+#ifndef TOTAL_DATA_SIZE
+#define TOTAL_DATA_SIZE 2*1000
+#endif
+
+#define SEED_ARG 0
+#define SEED_FUNC 1
+#define SEED_VOLATILE 2
+
+#define MEM_STATIC 0
+#define MEM_MALLOC 1
+#define MEM_STACK 2
+
+#include "core_portme.h"
+
+#if HAS_STDIO
+#include <stdio.h>
+#endif
+#if HAS_PRINTF
+#define ee_printf printf
+#endif
+
+/* Actual benchmark execution in iterate */
+void *iterate(void *pres);
+
+/* Typedef: secs_ret
+ For machines that have floating point support, get number of seconds as a double.
+ Otherwise an unsigned int.
+*/
+#if HAS_FLOAT
+typedef double secs_ret;
+#else
+typedef ee_u32 secs_ret;
+#endif
+
+#if MAIN_HAS_NORETURN
+#define MAIN_RETURN_VAL
+#define MAIN_RETURN_TYPE void
+#else
+#define MAIN_RETURN_VAL 0
+#define MAIN_RETURN_TYPE int
+#endif
+
+void start_time(void);
+void stop_time(void);
+CORE_TICKS get_time(void);
+secs_ret time_in_secs(CORE_TICKS ticks);
+
+/* Misc useful functions */
+ee_u16 crcu8(ee_u8 data, ee_u16 crc);
+ee_u16 crc16(ee_s16 newval, ee_u16 crc);
+ee_u16 crcu16(ee_u16 newval, ee_u16 crc);
+ee_u16 crcu32(ee_u32 newval, ee_u16 crc);
+ee_u8 check_data_types(void);
+void *portable_malloc(ee_size_t size);
+void portable_free(void *p);
+ee_s32 parseval(char *valstring);
+
+/* Algorithm IDS */
+#define ID_LIST (1<<0)
+#define ID_MATRIX (1<<1)
+#define ID_STATE (1<<2)
+#define ALL_ALGORITHMS_MASK (ID_LIST|ID_MATRIX|ID_STATE)
+#define NUM_ALGORITHMS 3
+
+/* list data structures */
+typedef struct list_data_s {
+ ee_s16 data16;
+ ee_s16 idx;
+} list_data;
+
+typedef struct list_head_s {
+ struct list_head_s *next;
+ struct list_data_s *info;
+} list_head;
+
+
+/*matrix benchmark related stuff */
+#define MATDAT_INT 1
+#if MATDAT_INT
+typedef ee_s16 MATDAT;
+typedef ee_s32 MATRES;
+#else
+typedef ee_f16 MATDAT;
+typedef ee_f32 MATRES;
+#endif
+
+typedef struct MAT_PARAMS_S {
+ int N;
+ MATDAT *A;
+ MATDAT *B;
+ MATRES *C;
+} mat_params;
+
+/* state machine related stuff */
+/* List of all the possible states for the FSM */
+typedef enum CORE_STATE {
+ CORE_START=0,
+ CORE_INVALID,
+ CORE_S1,
+ CORE_S2,
+ CORE_INT,
+ CORE_FLOAT,
+ CORE_EXPONENT,
+ CORE_SCIENTIFIC,
+ NUM_CORE_STATES
+} core_state_e ;
+
+
+/* Helper structure to hold results */
+typedef struct RESULTS_S {
+ /* inputs */
+ ee_s16 seed1; /* Initializing seed */
+ ee_s16 seed2; /* Initializing seed */
+ ee_s16 seed3; /* Initializing seed */
+ void *memblock[4]; /* Pointer to safe memory location */
+ ee_u32 size; /* Size of the data */
+ ee_u32 iterations; /* Number of iterations to execute */
+ ee_u32 execs; /* Bitmask of operations to execute */
+ struct list_head_s *list;
+ mat_params mat;
+ /* outputs */
+ ee_u16 crc;
+ ee_u16 crclist;
+ ee_u16 crcmatrix;
+ ee_u16 crcstate;
+ ee_s16 err;
+ /* ultithread specific */
+ core_portable port;
+} core_results;
+
+/* Multicore execution handling */
+#if (MULTITHREAD>1)
+ee_u8 core_start_parallel(core_results *res);
+ee_u8 core_stop_parallel(core_results *res);
+#endif
+
+/* list benchmark functions */
+list_head *core_list_init(ee_u32 blksize, list_head *memblock, ee_s16 seed);
+ee_u16 core_bench_list(core_results *res, ee_s16 finder_idx);
+
+/* state benchmark functions */
+void core_init_state(ee_u32 size, ee_s16 seed, ee_u8 *p);
+ee_u16 core_bench_state(ee_u32 blksize, ee_u8 *memblock,
+ ee_s16 seed1, ee_s16 seed2, ee_s16 step, ee_u16 crc);
+
+/* matrix benchmark functions */
+ee_u32 core_init_matrix(ee_u32 blksize, void *memblk, ee_s32 seed, mat_params *p);
+ee_u16 core_bench_matrix(mat_params *p, ee_s16 seed, ee_u16 crc);
+
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/coremark.md5 b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/coremark.md5
new file mode 100644
index 0000000..0c92b14
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/coremark.md5
@@ -0,0 +1,6 @@
+f837f8c5c5c6c0f5ef33bb1badc5ebef core_list_join.c
+3c7e2aeca881577ae02d628ad56a584a core_main.c
+6fef286af62d28486aa6e6c61fb11841 core_matrix.c
+640f7d70fab3ce61da49d0f9eef04f7f core_state.c
+85a5a29a1c55be49787bc1e1e7082f80 core_util.c
+9233fff3d437a831187153be4da64d23 coremark.h
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/cygwin/core_portme.c b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/cygwin/core_portme.c
new file mode 100755
index 0000000..fe8d299
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/cygwin/core_portme.c
@@ -0,0 +1,336 @@
+/*
+Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Original Author: Shay Gal-on
+*/
+
+#include <stdio.h>
+#include <stdlib.h>
+#include "coremark.h"
+#if CALLGRIND_RUN
+#include <valgrind/callgrind.h>
+#endif
+
+#if (MEM_METHOD==MEM_MALLOC)
+#include <malloc.h>
+/* Function: portable_malloc
+ Provide malloc() functionality in a platform specific way.
+*/
+void *portable_malloc(size_t size) {
+ return malloc(size);
+}
+/* Function: portable_free
+ Provide free() functionality in a platform specific way.
+*/
+void portable_free(void *p) {
+ free(p);
+}
+#else
+void *portable_malloc(size_t size) {
+ return NULL;
+}
+void portable_free(void *p) {
+ p=NULL;
+}
+#endif
+
+#if (SEED_METHOD==SEED_VOLATILE)
+#if VALIDATION_RUN
+ volatile ee_s32 seed1_volatile=0x3415;
+ volatile ee_s32 seed2_volatile=0x3415;
+ volatile ee_s32 seed3_volatile=0x66;
+#endif
+#if PERFORMANCE_RUN
+ volatile ee_s32 seed1_volatile=0x0;
+ volatile ee_s32 seed2_volatile=0x0;
+ volatile ee_s32 seed3_volatile=0x66;
+#endif
+#if PROFILE_RUN
+ volatile ee_s32 seed1_volatile=0x8;
+ volatile ee_s32 seed2_volatile=0x8;
+ volatile ee_s32 seed3_volatile=0x8;
+#endif
+ volatile ee_s32 seed4_volatile=ITERATIONS;
+ volatile ee_s32 seed5_volatile=0;
+#endif
+/* Porting: Timing functions
+ How to capture time and convert to seconds must be ported to whatever is supported by the platform.
+ e.g. Read value from on board RTC, read value from cpu clock cycles performance counter etc.
+ Sample implementation for standard time.h and windows.h definitions included.
+*/
+/* Define: TIMER_RES_DIVIDER
+ Divider to trade off timer resolution and total time that can be measured.
+
+ Use lower values to increase resolution, but make sure that overflow does not occur.
+ If there are issues with the return value overflowing, increase this value.
+ */
+#if USE_CLOCK
+ #define NSECS_PER_SEC CLOCKS_PER_SEC
+ #define EE_TIMER_TICKER_RATE 1000
+ #define CORETIMETYPE clock_t
+ #define GETMYTIME(_t) (*_t=clock())
+ #define MYTIMEDIFF(fin,ini) ((fin)-(ini))
+ #define TIMER_RES_DIVIDER 1
+ #define SAMPLE_TIME_IMPLEMENTATION 1
+#elif defined(_MSC_VER)
+ #define NSECS_PER_SEC 10000000
+ #define EE_TIMER_TICKER_RATE 1000
+ #define CORETIMETYPE FILETIME
+ #define GETMYTIME(_t) GetSystemTimeAsFileTime(_t)
+ #define MYTIMEDIFF(fin,ini) (((*(__int64*)&fin)-(*(__int64*)&ini))/TIMER_RES_DIVIDER)
+ /* setting to millisces resolution by default with MSDEV */
+ #ifndef TIMER_RES_DIVIDER
+ #define TIMER_RES_DIVIDER 1000
+ #endif
+ #define SAMPLE_TIME_IMPLEMENTATION 1
+#elif HAS_TIME_H
+ #define NSECS_PER_SEC 1000000000
+ #define EE_TIMER_TICKER_RATE 1000
+ #define CORETIMETYPE struct timespec
+ #define GETMYTIME(_t) clock_gettime(CLOCK_REALTIME,_t)
+ #define MYTIMEDIFF(fin,ini) ((fin.tv_sec-ini.tv_sec)*(NSECS_PER_SEC/TIMER_RES_DIVIDER)+(fin.tv_nsec-ini.tv_nsec)/TIMER_RES_DIVIDER)
+ /* setting to 1/1000 of a second resolution by default with linux */
+ #ifndef TIMER_RES_DIVIDER
+ #define TIMER_RES_DIVIDER 1000000
+ #endif
+ #define SAMPLE_TIME_IMPLEMENTATION 1
+#else
+ #define SAMPLE_TIME_IMPLEMENTATION 0
+#endif
+#define EE_TICKS_PER_SEC (NSECS_PER_SEC / TIMER_RES_DIVIDER)
+
+#if SAMPLE_TIME_IMPLEMENTATION
+/** Define Host specific (POSIX), or target specific global time variables. */
+static CORETIMETYPE start_time_val, stop_time_val;
+
+/* Function: start_time
+ This function will be called right before starting the timed portion of the benchmark.
+
+ Implementation may be capturing a system timer (as implemented in the example code)
+ or zeroing some system parameters - e.g. setting the cpu clocks cycles to 0.
+*/
+void start_time(void) {
+ GETMYTIME(&start_time_val );
+#if CALLGRIND_RUN
+ CALLGRIND_START_INSTRUMENTATION
+#endif
+#if MICA
+ asm volatile("int3");/*1 */
+#endif
+}
+/* Function: stop_time
+ This function will be called right after ending the timed portion of the benchmark.
+
+ Implementation may be capturing a system timer (as implemented in the example code)
+ or other system parameters - e.g. reading the current value of cpu cycles counter.
+*/
+void stop_time(void) {
+#if CALLGRIND_RUN
+ CALLGRIND_STOP_INSTRUMENTATION
+#endif
+#if MICA
+ asm volatile("int3");/*1 */
+#endif
+ GETMYTIME(&stop_time_val );
+}
+/* Function: get_time
+ Return an abstract "ticks" number that signifies time on the system.
+
+ Actual value returned may be cpu cycles, milliseconds or any other value,
+ as long as it can be converted to seconds by <time_in_secs>.
+ This methodology is taken to accomodate any hardware or simulated platform.
+ The sample implementation returns millisecs by default,
+ and the resolution is controlled by <TIMER_RES_DIVIDER>
+*/
+CORE_TICKS get_time(void) {
+ CORE_TICKS elapsed=(CORE_TICKS)(MYTIMEDIFF(stop_time_val, start_time_val));
+ return elapsed;
+}
+/* Function: time_in_secs
+ Convert the value returned by get_time to seconds.
+
+ The <secs_ret> type is used to accomodate systems with no support for floating point.
+ Default implementation implemented by the EE_TICKS_PER_SEC macro above.
+*/
+secs_ret time_in_secs(CORE_TICKS ticks) {
+ secs_ret retval=((secs_ret)ticks) / (secs_ret)EE_TICKS_PER_SEC;
+ return retval;
+}
+#else
+#error "Please implement timing functionality in core_portme.c"
+#endif /* SAMPLE_TIME_IMPLEMENTATION */
+
+ee_u32 default_num_contexts=MULTITHREAD;
+
+/* Function: portable_init
+ Target specific initialization code
+ Test for some common mistakes.
+*/
+void portable_init(core_portable *p, int *argc, char *argv[])
+{
+#if PRINT_ARGS
+ int i;
+ for (i=0; i<*argc; i++) {
+ ee_printf("Arg[%d]=%s\n",i,argv[i]);
+ }
+#endif
+ if (sizeof(ee_ptr_int) != sizeof(ee_u8 *)) {
+ ee_printf("ERROR! Please define ee_ptr_int to a type that holds a pointer!\n");
+ }
+ if (sizeof(ee_u32) != 4) {
+ ee_printf("ERROR! Please define ee_u32 to a 32b unsigned type!\n");
+ }
+#if (MAIN_HAS_NOARGC && (SEED_METHOD==SEED_ARG))
+ ee_printf("ERROR! Main has no argc, but SEED_METHOD defined to SEED_ARG!\n");
+#endif
+
+#if (MULTITHREAD>1) && (SEED_METHOD==SEED_ARG)
+ int nargs=*argc,i;
+ if ((nargs>1) && (*argv[1]=='M')) {
+ default_num_contexts=parseval(argv[1]+1);
+ if (default_num_contexts>MULTITHREAD)
+ default_num_contexts=MULTITHREAD;
+ /* Shift args since first arg is directed to the portable part and not to coremark main */
+ --nargs;
+ for (i=1; i<nargs; i++)
+ argv[i]=argv[i+1];
+ *argc=nargs;
+ }
+#endif /* sample of potential platform specific init via command line, reset the number of contexts being used if first argument is M<n>*/
+ p->portable_id=1;
+}
+/* Function: portable_fini
+ Target specific final code
+*/
+void portable_fini(core_portable *p)
+{
+ p->portable_id=0;
+}
+
+#if (MULTITHREAD>1)
+
+/* Function: core_start_parallel
+ Start benchmarking in a parallel context.
+
+ Three implementations are provided, one using pthreads, one using fork and shared mem, and one using fork and sockets.
+ Other implementations using MCAPI or other standards can easily be devised.
+*/
+/* Function: core_stop_parallel
+ Stop a parallel context execution of coremark, and gather the results.
+
+ Three implementations are provided, one using pthreads, one using fork and shared mem, and one using fork and sockets.
+ Other implementations using MCAPI or other standards can easily be devised.
+*/
+#if USE_PTHREAD
+ee_u8 core_start_parallel(core_results *res) {
+ return (ee_u8)pthread_create(&(res->port.thread),NULL,iterate,(void *)res);
+}
+ee_u8 core_stop_parallel(core_results *res) {
+ void *retval;
+ return (ee_u8)pthread_join(res->port.thread,&retval);
+}
+#elif USE_FORK
+static int key_id=0;
+ee_u8 core_start_parallel(core_results *res) {
+ key_t key=4321+key_id;
+ key_id++;
+ res->port.pid=fork();
+ res->port.shmid=shmget(key, 8, IPC_CREAT | 0666);
+ if (res->port.shmid<0) {
+ ee_printf("ERROR in shmget!\n");
+ }
+ if (res->port.pid==0) {
+ iterate(res);
+ res->port.shm=shmat(res->port.shmid, NULL, 0);
+ /* copy the validation values to the shared memory area and quit*/
+ if (res->port.shm == (char *) -1) {
+ ee_printf("ERROR in child shmat!\n");
+ } else {
+ memcpy(res->port.shm,&(res->crc),8);
+ shmdt(res->port.shm);
+ }
+ exit(0);
+ }
+ return 1;
+}
+ee_u8 core_stop_parallel(core_results *res) {
+ int status;
+ pid_t wpid = waitpid(res->port.pid,&status,WUNTRACED);
+ if (wpid != res->port.pid) {
+ ee_printf("ERROR waiting for child.\n");
+ if (errno == ECHILD) ee_printf("errno=No such child %d\n",res->port.pid);
+ if (errno == EINTR) ee_printf("errno=Interrupted\n");
+ return 0;
+ }
+ /* after process is done, get the values from the shared memory area */
+ res->port.shm=shmat(res->port.shmid, NULL, 0);
+ if (res->port.shm == (char *) -1) {
+ ee_printf("ERROR in parent shmat!\n");
+ return 0;
+ }
+ memcpy(&(res->crc),res->port.shm,8);
+ shmdt(res->port.shm);
+ return 1;
+}
+#elif USE_SOCKET
+static int key_id=0;
+ee_u8 core_start_parallel(core_results *res) {
+ int bound, buffer_length=8;
+ res->port.sa.sin_family = AF_INET;
+ res->port.sa.sin_addr.s_addr = htonl(0x7F000001);
+ res->port.sa.sin_port = htons(7654+key_id);
+ key_id++;
+ res->port.pid=fork();
+ if (res->port.pid==0) { /* benchmark child */
+ iterate(res);
+ res->port.sock = socket(PF_INET, SOCK_DGRAM, IPPROTO_UDP);
+ if (-1 == res->port.sock) /* if socket failed to initialize, exit */ {
+ ee_printf("Error Creating Socket");
+ } else {
+ int bytes_sent = sendto(res->port.sock, &(res->crc), buffer_length, 0,(struct sockaddr*)&(res->port.sa), sizeof (struct sockaddr_in));
+ if (bytes_sent < 0)
+ ee_printf("Error sending packet: %s\n", strerror(errno));
+ close(res->port.sock); /* close the socket */
+ }
+ exit(0);
+ }
+ /* parent process, open the socket */
+ res->port.sock = socket(PF_INET, SOCK_DGRAM, IPPROTO_UDP);
+ bound = bind(res->port.sock,(struct sockaddr*)&(res->port.sa), sizeof(struct sockaddr));
+ if (bound < 0)
+ ee_printf("bind(): %s\n",strerror(errno));
+ return 1;
+}
+ee_u8 core_stop_parallel(core_results *res) {
+ int status;
+ int fromlen=sizeof(struct sockaddr);
+ int recsize = recvfrom(res->port.sock, &(res->crc), 8, 0, (struct sockaddr*)&(res->port.sa), &fromlen);
+ if (recsize < 0) {
+ ee_printf("Error in receive: %s\n", strerror(errno));
+ return 0;
+ }
+ pid_t wpid = waitpid(res->port.pid,&status,WUNTRACED);
+ if (wpid != res->port.pid) {
+ ee_printf("ERROR waiting for child.\n");
+ if (errno == ECHILD) ee_printf("errno=No such child %d\n",res->port.pid);
+ if (errno == EINTR) ee_printf("errno=Interrupted\n");
+ return 0;
+ }
+ return 1;
+}
+#else /* no standard multicore implementation */
+#error "Please implement multicore functionality in core_portme.c to use multiple contexts."
+#endif /* multithread implementations */
+#endif
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/cygwin/core_portme.h b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/cygwin/core_portme.h
new file mode 100755
index 0000000..9471b12
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/cygwin/core_portme.h
@@ -0,0 +1,293 @@
+/*
+Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Original Author: Shay Gal-on
+*/
+
+/* Topic: Description
+ This file contains configuration constants required to execute on different platforms
+*/
+#ifndef CORE_PORTME_H
+#define CORE_PORTME_H
+/************************/
+/* Data types and settings */
+/************************/
+/* Configuration: HAS_FLOAT
+ Define to 1 if the platform supports floating point.
+*/
+#ifndef HAS_FLOAT
+#define HAS_FLOAT 1
+#endif
+/* Configuration: HAS_TIME_H
+ Define to 1 if platform has the time.h header file,
+ and implementation of functions thereof.
+*/
+#ifndef HAS_TIME_H
+#define HAS_TIME_H 1
+#endif
+/* Configuration: USE_CLOCK
+ Define to 1 if platform has the time.h header file,
+ and implementation of functions thereof.
+*/
+#ifndef USE_CLOCK
+#define USE_CLOCK 0
+#endif
+/* Configuration: HAS_STDIO
+ Define to 1 if the platform has stdio.h.
+*/
+#ifndef HAS_STDIO
+#define HAS_STDIO 1
+#endif
+/* Configuration: HAS_PRINTF
+ Define to 1 if the platform has stdio.h and implements the printf function.
+*/
+#ifndef HAS_PRINTF
+#define HAS_PRINTF 1
+#endif
+
+/* Configuration: CORE_TICKS
+ Define type of return from the timing functions.
+ */
+#if defined(_MSC_VER)
+#include <windows.h>
+typedef size_t CORE_TICKS;
+#elif HAS_TIME_H
+#include <time.h>
+typedef clock_t CORE_TICKS;
+#else
+#error "Please define type of CORE_TICKS and implement start_time, end_time get_time and time_in_secs functions!"
+#endif
+
+/* Definitions: COMPILER_VERSION, COMPILER_FLAGS, MEM_LOCATION
+ Initialize these strings per platform
+*/
+#ifndef COMPILER_VERSION
+ #ifdef __GNUC__
+ #define COMPILER_VERSION "GCC"__VERSION__
+ #else
+ #define COMPILER_VERSION "Please put compiler version here (e.g. gcc 4.1)"
+ #endif
+#endif
+#ifndef COMPILER_FLAGS
+ #define COMPILER_FLAGS FLAGS_STR /* "Please put compiler flags here (e.g. -o3)" */
+#endif
+#ifndef MEM_LOCATION
+ #define MEM_LOCATION "Please put data memory location here\n\t\t\t(e.g. code in flash, data on heap etc)"
+ #define MEM_LOCATION_UNSPEC 1
+#endif
+
+/* Data Types:
+ To avoid compiler issues, define the data types that need ot be used for 8b, 16b and 32b in <core_portme.h>.
+
+ *Imprtant*:
+ ee_ptr_int needs to be the data type used to hold pointers, otherwise coremark may fail!!!
+*/
+typedef signed short ee_s16;
+typedef unsigned short ee_u16;
+typedef signed int ee_s32;
+typedef double ee_f32;
+typedef unsigned char ee_u8;
+typedef unsigned int ee_u32;
+typedef ee_u32 ee_ptr_int;
+typedef size_t ee_size_t;
+/* align_mem:
+ This macro is used to align an offset to point to a 32b value. It is used in the Matrix algorithm to initialize the input memory blocks.
+*/
+#define align_mem(x) (void *)(4 + (((ee_ptr_int)(x) - 1) & ~3))
+
+/* Configuration: SEED_METHOD
+ Defines method to get seed values that cannot be computed at compile time.
+
+ Valid values:
+ SEED_ARG - from command line.
+ SEED_FUNC - from a system function.
+ SEED_VOLATILE - from volatile variables.
+*/
+#ifndef SEED_METHOD
+#define SEED_METHOD SEED_ARG
+#endif
+
+/* Configuration: MEM_METHOD
+ Defines method to get a block of memry.
+
+ Valid values:
+ MEM_MALLOC - for platforms that implement malloc and have malloc.h.
+ MEM_STATIC - to use a static memory array.
+ MEM_STACK - to allocate the data block on the stack (NYI).
+*/
+#ifndef MEM_METHOD
+#define MEM_METHOD MEM_MALLOC
+#endif
+
+/* Configuration: MULTITHREAD
+ Define for parallel execution
+
+ Valid values:
+ 1 - only one context (default).
+ N>1 - will execute N copies in parallel.
+
+ Note:
+ If this flag is defined to more then 1, an implementation for launching parallel contexts must be defined.
+
+ Two sample implementations are provided. Use <USE_PTHREAD> or <USE_FORK> to enable them.
+
+ It is valid to have a different implementation of <core_start_parallel> and <core_end_parallel> in <core_portme.c>,
+ to fit a particular architecture.
+*/
+#ifndef MULTITHREAD
+#define MULTITHREAD 1
+#endif
+
+/* Configuration: USE_PTHREAD
+ Sample implementation for launching parallel contexts
+ This implementation uses pthread_thread_create and pthread_join.
+
+ Valid values:
+ 0 - Do not use pthreads API.
+ 1 - Use pthreads API
+
+ Note:
+ This flag only matters if MULTITHREAD has been defined to a value greater then 1.
+*/
+#ifndef USE_PTHREAD
+#define USE_PTHREAD 0
+#endif
+
+/* Configuration: USE_FORK
+ Sample implementation for launching parallel contexts
+ This implementation uses fork, waitpid, shmget,shmat and shmdt.
+
+ Valid values:
+ 0 - Do not use fork API.
+ 1 - Use fork API
+
+ Note:
+ This flag only matters if MULTITHREAD has been defined to a value greater then 1.
+*/
+#ifndef USE_FORK
+#define USE_FORK 0
+#endif
+
+/* Configuration: USE_SOCKET
+ Sample implementation for launching parallel contexts
+ This implementation uses fork, socket, sendto and recvfrom
+
+ Valid values:
+ 0 - Do not use fork and sockets API.
+ 1 - Use fork and sockets API
+
+ Note:
+ This flag only matters if MULTITHREAD has been defined to a value greater then 1.
+*/
+#ifndef USE_SOCKET
+#define USE_SOCKET 0
+#endif
+
+/* Configuration: MAIN_HAS_NOARGC
+ Needed if platform does not support getting arguments to main.
+
+ Valid values:
+ 0 - argc/argv to main is supported
+ 1 - argc/argv to main is not supported
+*/
+#ifndef MAIN_HAS_NOARGC
+#define MAIN_HAS_NOARGC 0
+#endif
+
+/* Configuration: MAIN_HAS_NORETURN
+ Needed if platform does not support returning a value from main.
+
+ Valid values:
+ 0 - main returns an int, and return value will be 0.
+ 1 - platform does not support returning a value from main
+*/
+#ifndef MAIN_HAS_NORETURN
+#define MAIN_HAS_NORETURN 0
+#endif
+
+/* Variable: default_num_contexts
+ Number of contexts to spawn in multicore context.
+ Override this global value to change number of contexts used.
+
+ Note:
+ This value may not be set higher then the <MULTITHREAD> define.
+
+ To experiment, you can set the <MULTITHREAD> define to the highest value expected, and use argc/argv in the <portable_init> to set this value from the command line.
+*/
+extern ee_u32 default_num_contexts;
+
+#if (MULTITHREAD>1)
+#if USE_PTHREAD
+ #include <pthread.h>
+ #define PARALLEL_METHOD "PThreads"
+#elif USE_FORK
+ #include <unistd.h>
+ #include <errno.h>
+ #include <sys/wait.h>
+ #include <sys/shm.h>
+ #include <string.h> /* for memcpy */
+ #define PARALLEL_METHOD "Fork"
+#elif USE_SOCKET
+ #include <sys/types.h>
+ #include <sys/socket.h>
+ #include <netinet/in.h>
+ #include <arpa/inet.h>
+ #include <sys/wait.h>
+ #include <stdio.h>
+ #include <stdlib.h>
+ #include <string.h>
+ #include <unistd.h>
+ #include <errno.h>
+ #define PARALLEL_METHOD "Sockets"
+#else
+ #define PARALLEL_METHOD "Proprietary"
+ #error "Please implement multicore functionality in core_portme.c to use multiple contexts."
+#endif /* Method for multithreading */
+#endif /* MULTITHREAD > 1 */
+
+typedef struct CORE_PORTABLE_S {
+#if (MULTITHREAD>1)
+ #if USE_PTHREAD
+ pthread_t thread;
+ #elif USE_FORK
+ pid_t pid;
+ int shmid;
+ void *shm;
+ #elif USE_SOCKET
+ pid_t pid;
+ int sock;
+ struct sockaddr_in sa;
+ #endif /* Method for multithreading */
+#endif /* MULTITHREAD>1 */
+ ee_u8 portable_id;
+} core_portable;
+
+/* target specific init/fini */
+void portable_init(core_portable *p, int *argc, char *argv[]);
+void portable_fini(core_portable *p);
+
+#if (SEED_METHOD==SEED_VOLATILE)
+ #if (VALIDATION_RUN || PERFORMANCE_RUN || PROFILE_RUN)
+ #define RUN_TYPE_FLAG 1
+ #else
+ #if (TOTAL_DATA_SIZE==1200)
+ #define PROFILE_RUN 1
+ #else
+ #define PERFORMANCE_RUN 1
+ #endif
+ #endif
+#endif /* SEED_METHOD==SEED_VOLATILE */
+
+#endif /* CORE_PORTME_H */
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/cygwin/core_portme.mak b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/cygwin/core_portme.mak
new file mode 100755
index 0000000..721ba2e
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/cygwin/core_portme.mak
@@ -0,0 +1,141 @@
+# Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# Original Author: Shay Gal-on
+
+#File: core_portme.mak
+
+# Flag: OUTFLAG
+# Use this flag to define how to to get an executable (e.g -o)
+OUTFLAG= -o
+# Flag: CC
+# Use this flag to define compiler to use
+CC = gcc
+# Flag: CFLAGS
+# Use this flag to define compiler options. Note, you can add compiler options from the command line using XCFLAGS="other flags"
+PORT_CFLAGS = -O2
+FLAGS_STR = "$(PORT_CFLAGS) $(XCFLAGS) $(XLFLAGS) $(LFLAGS_END)"
+CFLAGS = $(PORT_CFLAGS) -I$(PORT_DIR) -I. -DFLAGS_STR=\"$(FLAGS_STR)\"
+#Flag: LFLAGS_END
+# Define any libraries needed for linking or other flags that should come at the end of the link line (e.g. linker scripts).
+# Note: On certain platforms, the default clock_gettime implementation is supported but requires linking of librt.
+LFLAGS_END =
+# Flag: PORT_SRCS
+# Port specific source files can be added here
+PORT_SRCS = $(PORT_DIR)/core_portme.c
+# Flag: LOAD
+# Define this flag if you need to load to a target, as in a cross compile environment.
+
+# Flag: RUN
+# Define this flag if running does not consist of simple invocation of the binary.
+# In a cross compile environment, you need to define this.
+
+#For flashing and using a tera term macro, you could use
+#LOAD = flash ADDR
+#RUN = ttpmacro coremark.ttl
+
+#For copying to target and executing via SSH connection, you could use
+#LOAD = scp $(OUTFILE) user@target:~
+#RUN = ssh user@target -c
+
+#For native compilation and execution
+LOAD = echo Loading done
+RUN =
+
+OEXT = .o
+EXE = .exe
+
+# Flag: SEPARATE_COMPILE
+# Define if you need to separate compilation from link stage.
+# In this case, you also need to define below how to create an object file, and how to link.
+ifdef SEPARATE_COMPILE
+
+LD = gcc
+OBJOUT = -o
+LFLAGS =
+OFLAG = -o
+COUT = -c
+# Flag: PORT_OBJS
+# Port specific object files can be added here
+PORT_OBJS = $(PORT_DIR)/core_portme$(OEXT)
+PORT_CLEAN = *$(OEXT)
+
+$(OPATH)%$(OEXT) : %.c
+ $(CC) $(CFLAGS) $(XCFLAGS) $(COUT) $< $(OBJOUT) $@
+
+endif
+
+# Target: port_prebuild
+# Generate any files that are needed before actual build starts.
+# E.g. generate profile guidance files. Sample PGO generation for gcc enabled with PGO=1
+# - First, check if PGO was defined on the command line, if so, need to add -fprofile-use to compile line.
+# - Second, if PGO reference has not yet been generated, add a step to the prebuild that will build a profile-generate version and run it.
+# Note - Using REBUILD=1
+#
+# Use make PGO=1 to invoke this sample processing.
+
+ifdef PGO
+ ifeq (,$(findstring $(PGO),gen))
+ PGO_STAGE=build_pgo_gcc
+ CFLAGS+=-fprofile-use
+ endif
+ PORT_CLEAN+=*.gcda *.gcno gmon.out
+endif
+
+.PHONY: port_prebuild
+port_prebuild: $(PGO_STAGE)
+
+.PHONY: build_pgo_gcc
+build_pgo_gcc:
+ $(MAKE) PGO=gen XCFLAGS="$(XCFLAGS) -fprofile-generate -DTOTAL_DATA_SIZE=1200" ITERATIONS=10 gen_pgo_data REBUILD=1
+
+# Target: port_postbuild
+# Generate any files that are needed after actual build end.
+# E.g. change format to srec, bin, zip in order to be able to load into flash
+.PHONY: port_postbuild
+port_postbuild:
+
+# Target: port_postrun
+# Do platform specific after run stuff.
+# E.g. reset the board, backup the logfiles etc.
+.PHONY: port_postrun
+port_postrun:
+
+# Target: port_prerun
+# Do platform specific after run stuff.
+# E.g. reset the board, backup the logfiles etc.
+.PHONY: port_prerun
+port_prerun:
+
+# Target: port_postload
+# Do platform specific after load stuff.
+# E.g. reset the reset power to the flash eraser
+.PHONY: port_postload
+port_postload:
+
+# Target: port_preload
+# Do platform specific before load stuff.
+# E.g. reset the reset power to the flash eraser
+.PHONY: port_preload
+port_preload:
+
+
+# FLAG: OPATH
+# Path to the output folder. Default - current folder.
+OPATH = ./
+MKDIR = mkdir -p
+
+# FLAG: PERL
+# Define perl executable to calculate the geomean if running separate.
+PERL=perl
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/READM.md b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/READM.md
new file mode 100644
index 0000000..6f71f42
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/READM.md
@@ -0,0 +1 @@
+This folder contains the original, unaltered documents from the CoreMark V1.0 release.
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/balance_O0_joined.png b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/balance_O0_joined.png
new file mode 100644
index 0000000..46b4158
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/balance_O0_joined.png
Binary files differ
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/coremark_profile_o0_joined.png b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/coremark_profile_o0_joined.png
new file mode 100644
index 0000000..5504dd0
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/coremark_profile_o0_joined.png
Binary files differ
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/files/PIC32/core_portme-mak.html b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/files/PIC32/core_portme-mak.html
new file mode 100644
index 0000000..c222bac
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/files/PIC32/core_portme-mak.html
@@ -0,0 +1,68 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd">
+
+<html><head><title>core_portme.mak - CoreMark</title><link rel="stylesheet" type="text/css" href="../../styles/main.css"><script language=JavaScript src="../../javascript/main.js"></script><script language=JavaScript src="../../javascript/searchdata.js"></script></head><body class="ContentPage" onLoad="NDOnLoad()"><script language=JavaScript><!--
+if (browserType) {document.write("<div class=" + browserType + ">");if (browserVer) {document.write("<div class=" + browserVer + ">"); }}// --></script>
+
+<!-- Copyright 2009 EEMBC -->
+<!-- saved from url=(0026)http://www.naturaldocs.org -->
+
+
+
+
+<div id=Content><div class="CFile"><div class=CTopic id=MainTopic><h1 class=CTitle><a name="core_portme.mak"></a>core_portme.mak</h1><div class=CBody><!--START_ND_SUMMARY--><div class=Summary><div class=STitle>Summary</div><div class=SBorder><table border=0 cellspacing=0 cellpadding=0 class=STable><tr class="SMain"><td class=SEntry><a href="#core_portme.mak" >core_portme.mak</a></td><td class=SDescription></td></tr><tr class="SGroup"><td class=SEntry><a href="#Variables" >Variables</a></td><td class=SDescription></td></tr><tr class="SVariable SIndent1 SMarked"><td class=SEntry><a href="#OUTFLAG" >OUTFLAG</a></td><td class=SDescription>Use this flag to define how to to get an executable (e.g -o)</td></tr><tr class="SVariable SIndent1"><td class=SEntry><a href="#CFLAGS" >CFLAGS</a></td><td class=SDescription>Use this flag to define compiler options. </td></tr><tr class="SVariable SIndent1 SMarked"><td class=SEntry><a href="#LFLAGS_END" >LFLAGS_END</a></td><td class=SDescription>Define any libraries needed for linking or other flags that should come at the end of the link line (e.g. </td></tr><tr class="SVariable SIndent1"><td class=SEntry><a href="#SEPARATE_COMPILE" >SEPARATE_COMPILE</a></td><td class=SDescription>Define if you need to separate compilation from link stage. </td></tr><tr class="SVariable SIndent1 SMarked"><td class=SEntry><a href="#PORT_OBJS" >PORT_OBJS</a></td><td class=SDescription>Port specific object files can be added here</td></tr><tr class="SGroup"><td class=SEntry><a href="#Build_Targets" >Build Targets</a></td><td class=SDescription></td></tr><tr class="SBuildTarget SIndent1 SMarked"><td class=SEntry><a href="#port_prebuild" >port_prebuild</a></td><td class=SDescription>Generate any files that are needed before actual build starts. </td></tr><tr class="SBuildTarget SIndent1"><td class=SEntry><a href="#port_postbuild" >port_postbuild</a></td><td class=SDescription>Generate any files that are needed after actual build end. </td></tr><tr class="SBuildTarget SIndent1 SMarked"><td class=SEntry><a href="#port_postrun" >port_postrun</a></td><td class=SDescription>Do platform specific after run stuff. </td></tr><tr class="SBuildTarget SIndent1"><td class=SEntry><a href="#port_prerun" >port_prerun</a></td><td class=SDescription>Do platform specific after run stuff. </td></tr><tr class="SBuildTarget SIndent1 SMarked"><td class=SEntry><a href="#port_postload" >port_postload</a></td><td class=SDescription>Do platform specific after load stuff. </td></tr><tr class="SBuildTarget SIndent1"><td class=SEntry><a href="#port_preload" >port_preload</a></td><td class=SDescription>Do platform specific before load stuff. </td></tr><tr class="SGroup"><td class=SEntry><a href="#Variables" >Variables</a></td><td class=SDescription></td></tr><tr class="SVariable SIndent1 SMarked"><td class=SEntry><a href="#OPATH" >OPATH</a></td><td class=SDescription></td></tr><tr class="SVariable SIndent1"><td class=SEntry><a href="#PERL" >PERL</a></td><td class=SDescription>Define perl executable to calculate the geomean if running separate.</td></tr></table></div></div><!--END_ND_SUMMARY--></div></div></div>
+
+<div class="CGroup"><div class=CTopic><h3 class=CTitle><a name="Variables"></a>Variables</h3></div></div>
+
+<div class="CVariable"><div class=CTopic><h3 class=CTitle><a name="OUTFLAG"></a>OUTFLAG</h3><div class=CBody><p>Use this flag to define how to to get an executable (e.g -o)</p></div></div></div>
+
+<div class="CVariable"><div class=CTopic><h3 class=CTitle><a name="CFLAGS"></a>CFLAGS</h3><div class=CBody><p>Use this flag to define compiler options. Note, you can add compiler options from the command line using XCFLAGS=”other flags”</p></div></div></div>
+
+<div class="CVariable"><div class=CTopic><h3 class=CTitle><a name="LFLAGS_END"></a>LFLAGS_END</h3><div class=CBody><p>Define any libraries needed for linking or other flags that should come at the end of the link line (e.g. linker scripts). Note: On certain platforms, the default clock_gettime implementation is supported but requires linking of librt.</p></div></div></div>
+
+<div class="CVariable"><div class=CTopic><h3 class=CTitle><a name="SEPARATE_COMPILE"></a>SEPARATE_COMPILE</h3><div class=CBody><p>Define if you need to separate compilation from link stage. In this case, you also need to define below how to create an object file, and how to link.</p></div></div></div>
+
+<div class="CVariable"><div class=CTopic><h3 class=CTitle><a name="PORT_OBJS"></a>PORT_OBJS</h3><div class=CBody><p>Port specific object files can be added here</p></div></div></div>
+
+<div class="CGroup"><div class=CTopic><h3 class=CTitle><a name="Build_Targets"></a>Build Targets</h3></div></div>
+
+<div class="CBuildTarget"><div class=CTopic><h3 class=CTitle><a name="port_prebuild"></a>port_prebuild</h3><div class=CBody><p>Generate any files that are needed before actual build starts. E.g. generate profile guidance files. Sample PGO generation for gcc enabled with PGO=1</p><ul><li>First, check if PGO was defined on the command line, if so, need to add -fprofile-use to compile line.</li><li>Second, if PGO reference has not yet been generated, add a step to the prebuild that will build a profile-generate version and run it.</li></ul><table border=0 cellspacing=0 cellpadding=0 class=CDescriptionList><tr><td class=CDLEntry>Note</td><td class=CDLDescription>Using REBUILD=1</td></tr></table><p>Use make PGO=1 to invoke this sample processing.</p></div></div></div>
+
+<div class="CBuildTarget"><div class=CTopic><h3 class=CTitle><a name="port_postbuild"></a>port_postbuild</h3><div class=CBody><p>Generate any files that are needed after actual build end. E.g. change format to srec, bin, zip in order to be able to load into flash</p></div></div></div>
+
+<div class="CBuildTarget"><div class=CTopic><h3 class=CTitle><a name="port_postrun"></a>port_postrun</h3><div class=CBody><p>Do platform specific after run stuff. E.g. reset the board, backup the logfiles etc.</p></div></div></div>
+
+<div class="CBuildTarget"><div class=CTopic><h3 class=CTitle><a name="port_prerun"></a>port_prerun</h3><div class=CBody><p>Do platform specific after run stuff. E.g. reset the board, backup the logfiles etc.</p></div></div></div>
+
+<div class="CBuildTarget"><div class=CTopic><h3 class=CTitle><a name="port_postload"></a>port_postload</h3><div class=CBody><p>Do platform specific after load stuff. E.g. reset the reset power to the flash eraser</p></div></div></div>
+
+<div class="CBuildTarget"><div class=CTopic><h3 class=CTitle><a name="port_preload"></a>port_preload</h3><div class=CBody><p>Do platform specific before load stuff. E.g. reset the reset power to the flash eraser</p></div></div></div>
+
+<div class="CGroup"><div class=CTopic><h3 class=CTitle><a name="Variables"></a>Variables</h3></div></div>
+
+<div class="CVariable"><div class=CTopic><h3 class=CTitle><a name="OPATH"></a>OPATH</h3><div class=CBody><table border=0 cellspacing=0 cellpadding=0 class=CDescriptionList><tr><td class=CDLEntry>Path to the output folder. Default</td><td class=CDLDescription>current folder.</td></tr></table></div></div></div>
+
+<div class="CVariable"><div class=CTopic><h3 class=CTitle><a name="PERL"></a>PERL</h3><div class=CBody><p>Define perl executable to calculate the geomean if running separate.</p></div></div></div>
+
+</div><!--Content-->
+
+
+<div id=Footer><a href="http://www.naturaldocs.org">Copyright 2009 EEMBC</a></div><!--Footer-->
+
+
+<div id=Menu><div class=MTitle>CoreMark<div class=MSubTitle>(c) EEMBC</div></div><div class=MEntry><div class=MFile><a href="../readme-txt.html">CoreMark</a></div></div><div class=MEntry><div class=MFile><a href="../release_notes-txt.html">Release Notes</a></div></div><div class=MEntry><div class=MGroup><a href="javascript:ToggleMenu('MGroupContent2')">Source</a><div class=MGroupContent id=MGroupContent2><div class=MEntry><div class=MFile><a href="../core_list_join-c.html">core_list_join.c</a></div></div><div class=MEntry><div class=MFile><a href="../core_main-c.html">core_main.c</a></div></div><div class=MEntry><div class=MFile><a href="../core_matrix-c.html">core_matrix.c</a></div></div><div class=MEntry><div class=MFile id=MSelected>core_portme.mak</div></div><div class=MEntry><div class=MFile><a href="../core_state-c.html">core_state.c</a></div></div><div class=MEntry><div class=MFile><a href="../core_util-c.html">core_util.c</a></div></div><div class=MEntry><div class=MFile><a href="../coremark-h.html">coremark.h</a></div></div><div class=MEntry><div class=MGroup><a href="javascript:ToggleMenu('MGroupContent1')">Porting</a><div class=MGroupContent id=MGroupContent1><div class=MEntry><div class=MFile><a href="../linux/core_portme-c.html">PORT_DIR/<span class=HB> </span>core_portme.c</a></div></div><div class=MEntry><div class=MFile><a href="../linux/core_portme-h.html">PORT_DIR/<span class=HB> </span>core_portme.h</a></div></div><div class=MEntry><div class=MFile><a href="../linux/core_portme-mak.html">PORT_DIR/<span class=HB> </span>core_portme.mak</a></div></div></div></div></div></div></div></div><div class=MEntry><div class=MGroup><a href="javascript:ToggleMenu('MGroupContent3')">Index</a><div class=MGroupContent id=MGroupContent3><div class=MEntry><div class=MIndex><a href="../../index/General.html">Everything</a></div></div><div class=MEntry><div class=MIndex><a href="../../index/Files.html">Files</a></div></div><div class=MEntry><div class=MIndex><a href="../../index/Functions.html">Functions</a></div></div><div class=MEntry><div class=MIndex><a href="../../index/Types.html">Types</a></div></div><div class=MEntry><div class=MIndex><a href="../../index/Configuration.html">Configurations</a></div></div><div class=MEntry><div class=MIndex><a href="../../index/Variables.html">Variables</a></div></div><div class=MEntry><div class=MIndex><a href="../../index/BuildTargets.html">Build Targets</a></div></div></div></div></div><script type="text/javascript"><!--
+var searchPanel = new SearchPanel("searchPanel", "HTML", "../../search");
+--></script><div id=MSearchPanel class=MSearchPanelInactive><input type=text id=MSearchField value=Search onFocus="searchPanel.OnSearchFieldFocus(true)" onBlur="searchPanel.OnSearchFieldFocus(false)" onKeyUp="searchPanel.OnSearchFieldChange()"><select id=MSearchType onFocus="searchPanel.OnSearchTypeFocus(true)" onBlur="searchPanel.OnSearchTypeFocus(false)" onChange="searchPanel.OnSearchTypeChange()"><option id=MSearchEverything selected value="General">Everything</option><option value="BuildTargets">Build Targets</option><option value="Configuration">Configuration</option><option value="Files">Files</option><option value="Functions">Functions</option><option value="Types">Types</option><option value="Variables">Variables</option></select></div></div><!--Menu-->
+
+
+
+<!--START_ND_TOOLTIPS-->
+<!--END_ND_TOOLTIPS-->
+
+
+
+
+<div id=MSearchResultsWindow><iframe src="" frameborder=0 name=MSearchResults id=MSearchResults></iframe><a href="javascript:searchPanel.CloseResultsWindow()" id=MSearchResultsWindowClose>Close</a></div>
+
+
+<script language=JavaScript><!--
+if (browserType) {if (browserVer) {document.write("</div>"); }document.write("</div>");}// --></script></body></html>
\ No newline at end of file
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/files/core_list_join-c.html b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/files/core_list_join-c.html
new file mode 100644
index 0000000..6ee2aee
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/files/core_list_join-c.html
@@ -0,0 +1,58 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd">
+
+<html><head><title>/cygdrive/d/dev/code/coremark/core_list_join.c - CoreMark</title><link rel="stylesheet" type="text/css" href="../styles/main.css"><script language=JavaScript src="../javascript/main.js"></script><script language=JavaScript src="../javascript/searchdata.js"></script></head><body class="ContentPage" onLoad="NDOnLoad()"><script language=JavaScript><!--
+if (browserType) {document.write("<div class=" + browserType + ">");if (browserVer) {document.write("<div class=" + browserVer + ">"); }}// --></script>
+
+<!-- Copyright 2009 EEMBC -->
+<!-- saved from url=(0026)http://www.naturaldocs.org -->
+
+
+
+
+<div id=Content><div class="CFile"><div class=CTopic id=MainTopic><h1 class=CTitle><a name="core_list_join.c"></a>core_list_join.c</h1><div class=CBody><!--START_ND_SUMMARY--><div class=Summary><div class=STitle>Summary</div><div class=SBorder><table border=0 cellspacing=0 cellpadding=0 class=STable><tr class="SMain"><td class=SEntry><a href="#core_list_join.c" >core_list_join.c</a></td><td class=SDescription></td></tr><tr class="SGeneric SMarked"><td class=SEntry><a href="#Description" >Description</a></td><td class=SDescription>Benchmark using a linked list.</td></tr><tr class="SGroup"><td class=SEntry><a href="#Functions" >Functions</a></td><td class=SDescription></td></tr><tr class="SFunction SIndent1 SMarked"><td class=SEntry><a href="#cmp_complex" id=link1 onMouseOver="ShowTip(event, 'tt1', 'link1')" onMouseOut="HideTip('tt1')">cmp_complex</a></td><td class=SDescription>Compare the data item in a list cell.</td></tr><tr class="SFunction SIndent1"><td class=SEntry><a href="#cmp_idx" id=link2 onMouseOver="ShowTip(event, 'tt2', 'link2')" onMouseOut="HideTip('tt2')">cmp_idx</a></td><td class=SDescription>Compare the idx item in a list cell, and regen the data.</td></tr><tr class="SFunction SIndent1 SMarked"><td class=SEntry><a href="#core_list_init" id=link3 onMouseOver="ShowTip(event, 'tt3', 'link3')" onMouseOut="HideTip('tt3')">core_list_init</a></td><td class=SDescription>Initialize list with data.</td></tr><tr class="SFunction SIndent1"><td class=SEntry><a href="#core_list_insert" id=link4 onMouseOver="ShowTip(event, 'tt4', 'link4')" onMouseOut="HideTip('tt4')">core_list_insert</a></td><td class=SDescription>Insert an item to the list</td></tr><tr class="SFunction SIndent1 SMarked"><td class=SEntry><a href="#core_list_remove" id=link5 onMouseOver="ShowTip(event, 'tt5', 'link5')" onMouseOut="HideTip('tt5')">core_list_remove</a></td><td class=SDescription>Remove an item from the list.</td></tr><tr class="SFunction SIndent1"><td class=SEntry><a href="#core_list_undo_remove" id=link6 onMouseOver="ShowTip(event, 'tt6', 'link6')" onMouseOut="HideTip('tt6')">core_list_undo_remove</a></td><td class=SDescription>Undo a remove operation.</td></tr><tr class="SFunction SIndent1 SMarked"><td class=SEntry><a href="#core_list_find" id=link7 onMouseOver="ShowTip(event, 'tt7', 'link7')" onMouseOut="HideTip('tt7')">core_list_find</a></td><td class=SDescription>Find an item in the list</td></tr><tr class="SFunction SIndent1"><td class=SEntry><a href="#core_list_reverse" id=link8 onMouseOver="ShowTip(event, 'tt8', 'link8')" onMouseOut="HideTip('tt8')">core_list_reverse</a></td><td class=SDescription>Reverse a list</td></tr><tr class="SFunction SIndent1 SMarked"><td class=SEntry><a href="#core_list_mergesort" id=link9 onMouseOver="ShowTip(event, 'tt9', 'link9')" onMouseOut="HideTip('tt9')">core_list_mergesort</a></td><td class=SDescription>Sort the list in place without recursion.</td></tr></table></div></div><!--END_ND_SUMMARY--></div></div></div>
+
+<div class="CGeneric"><div class=CTopic><h3 class=CTitle><a name="Description"></a>Description</h3><div class=CBody><p>Benchmark using a linked list.</p><p>Linked list is a common data structure used in many applications.</p><p>For our purposes, this will excercise the memory units of the processor. In particular, usage of the list pointers to find and alter data.</p><p>We are not using Malloc since some platforms do not support this library.</p><p>Instead, the memory block being passed in is used to create a list, and the benchmark takes care not to add more items then can be accomodated by the memory block. The porting layer will make sure that we have a valid memory block.</p><p>All operations are done in place, without using any extra memory.</p><p>The list itself contains list pointers and pointers to data items. Data items contain the following:</p><table border=0 cellspacing=0 cellpadding=0 class=CDescriptionList><tr><td class=CDLEntry>idx</td><td class=CDLDescription>An index that captures the initial order of the list.</td></tr><tr><td class=CDLEntry>data</td><td class=CDLDescription>Variable data initialized based on the input parameters. The 16b are divided as follows:</td></tr></table><ul><li>Upper 8b are backup of original data.</li><li>Bit 7 indicates if the lower 7 bits are to be used as is or calculated.</li><li>Bits 0-2 indicate type of operation to perform to get a 7b value.</li><li>Bits 3-6 provide input for the operation.</li></ul></div></div></div>
+
+<div class="CGroup"><div class=CTopic><h3 class=CTitle><a name="Functions"></a>Functions</h3></div></div>
+
+<div class="CFunction"><div class=CTopic><h3 class=CTitle><a name="cmp_complex"></a>cmp_complex</h3><div class=CBody><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>ee_s32 cmp_complex(</td><td class=PType nowrap>list_data </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>a,</td></tr><tr><td></td><td class=PType nowrap>list_data </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>b,</td></tr><tr><td></td><td class=PType nowrap>core_results </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>res</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote><p>Compare the data item in a list cell.</p><p>Can be used by mergesort.</p></div></div></div>
+
+<div class="CFunction"><div class=CTopic><h3 class=CTitle><a name="cmp_idx"></a>cmp_idx</h3><div class=CBody><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>ee_s32 cmp_idx(</td><td class=PType nowrap>list_data </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>a,</td></tr><tr><td></td><td class=PType nowrap>list_data </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>b,</td></tr><tr><td></td><td class=PType nowrap>core_results </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>res</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote><p>Compare the idx item in a list cell, and regen the data.</p><p>Can be used by mergesort.</p></div></div></div>
+
+<div class="CFunction"><div class=CTopic><h3 class=CTitle><a name="core_list_init"></a>core_list_init</h3><div class=CBody><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>list_head *core_list_init(</td><td class=PType nowrap>ee_u32 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>blksize,</td></tr><tr><td></td><td class=PType nowrap>list_head </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>memblock,</td></tr><tr><td></td><td class=PType nowrap>ee_s16 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>seed</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote><p>Initialize list with data.</p><h4 class=CHeading>Parameters</h4><table border=0 cellspacing=0 cellpadding=0 class=CDescriptionList><tr><td class=CDLEntry>blksize</td><td class=CDLDescription>Size of memory to be initialized.</td></tr><tr><td class=CDLEntry>memblock</td><td class=CDLDescription>Pointer to memory block.</td></tr><tr><td class=CDLEntry>seed</td><td class=CDLDescription>Actual values chosen depend on the seed parameter. The seed parameter MUST be supplied from a source that cannot be determined at compile time</td></tr></table><h4 class=CHeading>Returns</h4><p>Pointer to the head of the list.</p></div></div></div>
+
+<div class="CFunction"><div class=CTopic><h3 class=CTitle><a name="core_list_insert"></a>core_list_insert</h3><div class=CBody><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>list_head *core_list_insert_new(</td><td class=PTypePrefix nowrap></td><td class=PType nowrap>list_head </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>insert_point,</td></tr><tr><td></td><td class=PTypePrefix nowrap></td><td class=PType nowrap>list_data </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>info,</td></tr><tr><td></td><td class=PTypePrefix nowrap></td><td class=PType nowrap>list_head </td><td class=PParameterPrefix nowrap>**</td><td class=PParameter nowrap>memblock,</td></tr><tr><td></td><td class=PTypePrefix nowrap>list_data </td><td class=PType nowrap>**datablock </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>,</td></tr><tr><td></td><td class=PTypePrefix nowrap></td><td class=PType nowrap>list_head </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>memblock_end,</td></tr><tr><td></td><td class=PTypePrefix nowrap></td><td class=PType nowrap>list_data </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>datablock_end</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote><p>Insert an item to the list</p><h4 class=CHeading>Parameters</h4><table border=0 cellspacing=0 cellpadding=0 class=CDescriptionList><tr><td class=CDLEntry>insert_point</td><td class=CDLDescription>where to insert the item.</td></tr><tr><td class=CDLEntry>info</td><td class=CDLDescription>data for the cell.</td></tr><tr><td class=CDLEntry>memblock</td><td class=CDLDescription>pointer for the list header</td></tr><tr><td class=CDLEntry>datablock</td><td class=CDLDescription>pointer for the list data</td></tr><tr><td class=CDLEntry>memblock_end</td><td class=CDLDescription>end of region for list headers</td></tr><tr><td class=CDLEntry>datablock_end</td><td class=CDLDescription>end of region for list data</td></tr></table><h4 class=CHeading>Returns</h4><p>Pointer to new item.</p></div></div></div>
+
+<div class="CFunction"><div class=CTopic><h3 class=CTitle><a name="core_list_remove"></a>core_list_remove</h3><div class=CBody><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>list_head *core_list_remove(</td><td class=PType nowrap>list_head </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>item</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote><p>Remove an item from the list.</p><h4 class=CHeading>Operation</h4><p>For a singly linked list, remove by copying the data from the next item over to the current cell, and unlinking the next item.</p><h4 class=CHeading>Note</h4><p>since there is always a fake item at the end of the list, no need to check for NULL.</p><h4 class=CHeading>Returns</h4><p>Removed item.</p></div></div></div>
+
+<div class="CFunction"><div class=CTopic><h3 class=CTitle><a name="core_list_undo_remove"></a>core_list_undo_remove</h3><div class=CBody><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>list_head *core_list_undo_remove(</td><td class=PType nowrap>list_head </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>item_removed,</td></tr><tr><td></td><td class=PType nowrap>list_head </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>item_modified</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote><p>Undo a remove operation.</p><h4 class=CHeading>Operation</h4><p>Since we want each iteration of the benchmark to be exactly the same, we need to be able to undo a remove. Link the removed item back into the list, and switch the info items.</p><h4 class=CHeading>Parameters</h4><table border=0 cellspacing=0 cellpadding=0 class=CDescriptionList><tr><td class=CDLEntry>item_removed</td><td class=CDLDescription>Return value from the <a href="#core_list_remove" class=LFunction id=link10 onMouseOver="ShowTip(event, 'tt5', 'link10')" onMouseOut="HideTip('tt5')">core_list_remove</a></td></tr><tr><td class=CDLEntry>item_modified</td><td class=CDLDescription>List item that was modified during <a href="#core_list_remove" class=LFunction id=link11 onMouseOver="ShowTip(event, 'tt5', 'link11')" onMouseOut="HideTip('tt5')">core_list_remove</a></td></tr></table><h4 class=CHeading>Returns</h4><p>The item that was linked back to the list.</p></div></div></div>
+
+<div class="CFunction"><div class=CTopic><h3 class=CTitle><a name="core_list_find"></a>core_list_find</h3><div class=CBody><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>list_head *core_list_find(</td><td class=PType nowrap>list_head </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>list,</td></tr><tr><td></td><td class=PType nowrap>list_data </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>info</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote><p>Find an item in the list</p><h4 class=CHeading>Operation</h4><p>Find an item by idx (if not 0) or specific data value</p><h4 class=CHeading>Parameters</h4><table border=0 cellspacing=0 cellpadding=0 class=CDescriptionList><tr><td class=CDLEntry>list</td><td class=CDLDescription>list head</td></tr><tr><td class=CDLEntry>info</td><td class=CDLDescription>idx or data to find</td></tr></table><h4 class=CHeading>Returns</h4><p>Found item, or NULL if not found.</p></div></div></div>
+
+<div class="CFunction"><div class=CTopic><h3 class=CTitle><a name="core_list_reverse"></a>core_list_reverse</h3><div class=CBody><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>list_head *core_list_reverse(</td><td class=PType nowrap>list_head </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>list</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote><p>Reverse a list</p><h4 class=CHeading>Operation</h4><p>Rearrange the pointers so the list is reversed.</p><h4 class=CHeading>Parameters</h4><table border=0 cellspacing=0 cellpadding=0 class=CDescriptionList><tr><td class=CDLEntry>list</td><td class=CDLDescription>list head</td></tr><tr><td class=CDLEntry>info</td><td class=CDLDescription>idx or data to find</td></tr></table><h4 class=CHeading>Returns</h4><p>Found item, or NULL if not found.</p></div></div></div>
+
+<div class="CFunction"><div class=CTopic><h3 class=CTitle><a name="core_list_mergesort"></a>core_list_mergesort</h3><div class=CBody><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>list_head *core_list_mergesort(</td><td class=PType nowrap>list_head </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>list,</td></tr><tr><td></td><td class=PType nowrap>list_cmp </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>cmp,</td></tr><tr><td></td><td class=PType nowrap>core_results </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>res</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote><p>Sort the list in place without recursion.</p><h4 class=CHeading>Description</h4><p>Use mergesort, as for linked list this is a realistic solution. Also, since this is aimed at embedded, care was taken to use iterative rather then recursive algorithm. The sort can either return the list to original order (by idx) , or use the data item to invoke other other algorithms and change the order of the list.</p><h4 class=CHeading>Parameters</h4><table border=0 cellspacing=0 cellpadding=0 class=CDescriptionList><tr><td class=CDLEntry>list</td><td class=CDLDescription>list to be sorted.</td></tr><tr><td class=CDLEntry>cmp</td><td class=CDLDescription>cmp function to use</td></tr></table><h4 class=CHeading>Returns</h4><p>New head of the list.</p><h4 class=CHeading>Note</h4><p>We have a special header for the list that will always be first, but the algorithm could theoretically modify where the list starts.</p></div></div></div>
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+<div id=Menu><div class=MTitle>CoreMark<div class=MSubTitle>(c) EEMBC</div></div><div class=MEntry><div class=MFile><a href="readme-txt.html">CoreMark</a></div></div><div class=MEntry><div class=MFile><a href="release_notes-txt.html">Release Notes</a></div></div><div class=MEntry><div class=MGroup><a href="javascript:ToggleMenu('MGroupContent2')">Source</a><div class=MGroupContent id=MGroupContent2><div class=MEntry><div class=MFile id=MSelected>core_list_join.c</div></div><div class=MEntry><div class=MFile><a href="core_main-c.html">core_main.c</a></div></div><div class=MEntry><div class=MFile><a href="core_matrix-c.html">core_matrix.c</a></div></div><div class=MEntry><div class=MFile><a href="PIC32/core_portme-mak.html">core_portme.mak</a></div></div><div class=MEntry><div class=MFile><a href="core_state-c.html">core_state.c</a></div></div><div class=MEntry><div class=MFile><a href="core_util-c.html">core_util.c</a></div></div><div class=MEntry><div class=MFile><a href="coremark-h.html">coremark.h</a></div></div><div class=MEntry><div class=MGroup><a href="javascript:ToggleMenu('MGroupContent1')">Porting</a><div class=MGroupContent id=MGroupContent1><div class=MEntry><div class=MFile><a href="linux/core_portme-c.html">PORT_DIR/<span class=HB> </span>core_portme.c</a></div></div><div class=MEntry><div class=MFile><a href="linux/core_portme-h.html">PORT_DIR/<span class=HB> </span>core_portme.h</a></div></div><div class=MEntry><div class=MFile><a href="linux/core_portme-mak.html">PORT_DIR/<span class=HB> </span>core_portme.mak</a></div></div></div></div></div></div></div></div><div class=MEntry><div class=MGroup><a href="javascript:ToggleMenu('MGroupContent3')">Index</a><div class=MGroupContent id=MGroupContent3><div class=MEntry><div class=MIndex><a href="../index/General.html">Everything</a></div></div><div class=MEntry><div class=MIndex><a href="../index/Files.html">Files</a></div></div><div class=MEntry><div class=MIndex><a href="../index/Functions.html">Functions</a></div></div><div class=MEntry><div class=MIndex><a href="../index/Types.html">Types</a></div></div><div class=MEntry><div class=MIndex><a href="../index/Configuration.html">Configurations</a></div></div><div class=MEntry><div class=MIndex><a href="../index/Variables.html">Variables</a></div></div><div class=MEntry><div class=MIndex><a href="../index/BuildTargets.html">Build Targets</a></div></div></div></div></div><script type="text/javascript"><!--
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+<!--START_ND_TOOLTIPS-->
+<div class=CToolTip id="tt1"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>ee_s32 cmp_complex(</td><td class=PType nowrap>list_data </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>a,</td></tr><tr><td></td><td class=PType nowrap>list_data </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>b,</td></tr><tr><td></td><td class=PType nowrap>core_results </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>res</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Compare the data item in a list cell.</div></div><div class=CToolTip id="tt2"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>ee_s32 cmp_idx(</td><td class=PType nowrap>list_data </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>a,</td></tr><tr><td></td><td class=PType nowrap>list_data </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>b,</td></tr><tr><td></td><td class=PType nowrap>core_results </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>res</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Compare the idx item in a list cell, and regen the data.</div></div><div class=CToolTip id="tt3"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>list_head *core_list_init(</td><td class=PType nowrap>ee_u32 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>blksize,</td></tr><tr><td></td><td class=PType nowrap>list_head </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>memblock,</td></tr><tr><td></td><td class=PType nowrap>ee_s16 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>seed</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Initialize list with data.</div></div><div class=CToolTip id="tt4"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>list_head *core_list_insert_new(</td><td class=PTypePrefix nowrap></td><td class=PType nowrap>list_head </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>insert_point,</td></tr><tr><td></td><td class=PTypePrefix nowrap></td><td class=PType nowrap>list_data </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>info,</td></tr><tr><td></td><td class=PTypePrefix nowrap></td><td class=PType nowrap>list_head </td><td class=PParameterPrefix nowrap>**</td><td class=PParameter nowrap>memblock,</td></tr><tr><td></td><td class=PTypePrefix nowrap>list_data </td><td class=PType nowrap>**datablock </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>,</td></tr><tr><td></td><td class=PTypePrefix nowrap></td><td class=PType nowrap>list_head </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>memblock_end,</td></tr><tr><td></td><td class=PTypePrefix nowrap></td><td class=PType nowrap>list_data </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>datablock_end</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Insert an item to the list</div></div><div class=CToolTip id="tt5"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>list_head *core_list_remove(</td><td class=PType nowrap>list_head </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>item</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Remove an item from the list.</div></div><div class=CToolTip id="tt6"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>list_head *core_list_undo_remove(</td><td class=PType nowrap>list_head </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>item_removed,</td></tr><tr><td></td><td class=PType nowrap>list_head </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>item_modified</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Undo a remove operation.</div></div><div class=CToolTip id="tt7"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>list_head *core_list_find(</td><td class=PType nowrap>list_head </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>list,</td></tr><tr><td></td><td class=PType nowrap>list_data </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>info</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Find an item in the list</div></div><div class=CToolTip id="tt8"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>list_head *core_list_reverse(</td><td class=PType nowrap>list_head </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>list</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Reverse a list</div></div><div class=CToolTip id="tt9"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>list_head *core_list_mergesort(</td><td class=PType nowrap>list_head </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>list,</td></tr><tr><td></td><td class=PType nowrap>list_cmp </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>cmp,</td></tr><tr><td></td><td class=PType nowrap>core_results </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>res</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Sort the list in place without recursion.</div></div><!--END_ND_TOOLTIPS-->
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+<html><head><title>core_main.c - CoreMark</title><link rel="stylesheet" type="text/css" href="../styles/main.css"><script language=JavaScript src="../javascript/main.js"></script><script language=JavaScript src="../javascript/searchdata.js"></script></head><body class="ContentPage" onLoad="NDOnLoad()"><script language=JavaScript><!--
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+
+<div id=Content><div class="CFile"><div class=CTopic id=MainTopic><h1 class=CTitle><a name="core_main.c"></a>core_main.c</h1><div class=CBody><p>This file contains the framework to acquire a block of memory, seed initial parameters, tun t he benchmark and report the results.</p><!--START_ND_SUMMARY--><div class=Summary><div class=STitle>Summary</div><div class=SBorder><table border=0 cellspacing=0 cellpadding=0 class=STable><tr class="SMain"><td class=SEntry><a href="#core_main.c" >core_main.c</a></td><td class=SDescription>This file contains the framework to acquire a block of memory, seed initial parameters, tun t he benchmark and report the results.</td></tr><tr class="SGroup"><td class=SEntry><a href="#Functions" >Functions</a></td><td class=SDescription></td></tr><tr class="SFunction SIndent1 SMarked"><td class=SEntry><a href="#iterate" >iterate</a></td><td class=SDescription>Run the benchmark for a specified number of iterations.</td></tr><tr class="SFunction SIndent1"><td class=SEntry><a href="#main" id=link1 onMouseOver="ShowTip(event, 'tt1', 'link1')" onMouseOut="HideTip('tt1')">main</a></td><td class=SDescription>Main entry routine for the benchmark. </td></tr></table></div></div><!--END_ND_SUMMARY--></div></div></div>
+
+<div class="CGroup"><div class=CTopic><h3 class=CTitle><a name="Functions"></a>Functions</h3></div></div>
+
+<div class="CFunction"><div class=CTopic><h3 class=CTitle><a name="iterate"></a>iterate</h3><div class=CBody><p>Run the benchmark for a specified number of iterations.</p><h4 class=CHeading>Operation</h4><p>For each type of benchmarked algorithm: a - Initialize the data block for the algorithm. b - Execute the algorithm N times.</p><h4 class=CHeading>Returns</h4><p>NULL.</p></div></div></div>
+
+<div class="CFunction"><div class=CTopic><h3 class=CTitle><a name="main"></a>main</h3><div class=CBody><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>#if MAIN_HAS_NOARGC MAIN_RETURN_TYPE main(</td><td class=PParameter nowrap>void</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote><p>Main entry routine for the benchmark. This function is responsible for the following steps:</p><table border=0 cellspacing=0 cellpadding=0 class=CDescriptionList><tr><td class=CDLEntry>1</td><td class=CDLDescription>Initialize input seeds from a source that cannot be determined at compile time.</td></tr><tr><td class=CDLEntry>2</td><td class=CDLDescription>Initialize memory block for use.</td></tr><tr><td class=CDLEntry>3</td><td class=CDLDescription>Run and time the benchmark.</td></tr><tr><td class=CDLEntry>4</td><td class=CDLDescription>Report results, testing the validity of the output if the seeds are known.</td></tr></table><h4 class=CHeading>Arguments</h4><table border=0 cellspacing=0 cellpadding=0 class=CDescriptionList><tr><td class=CDLEntry>1</td><td class=CDLDescription>first seed : Any value</td></tr><tr><td class=CDLEntry>2</td><td class=CDLDescription>second seed : Must be identical to first for iterations to be identical</td></tr><tr><td class=CDLEntry>3</td><td class=CDLDescription>third seed : Any value, should be at least an order of magnitude less then the input size, but bigger then 32.</td></tr><tr><td class=CDLEntry>4</td><td class=CDLDescription>Iterations : Special, if set to 0, iterations will be automatically determined such that the benchmark will run between 10 to 100 secs</td></tr></table></div></div></div>
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+<div id=Content><div class="CFile"><div class=CTopic id=MainTopic><h1 class=CTitle><a name="core_matrix.c"></a>core_matrix.c</h1><div class=CBody><!--START_ND_SUMMARY--><div class=Summary><div class=STitle>Summary</div><div class=SBorder><table border=0 cellspacing=0 cellpadding=0 class=STable><tr class="SMain"><td class=SEntry><a href="#core_matrix.c" >core_matrix.c</a></td><td class=SDescription></td></tr><tr class="SGeneric SMarked"><td class=SEntry><a href="#Description" >Description</a></td><td class=SDescription>Matrix manipulation benchmark</td></tr><tr class="SGroup"><td class=SEntry><a href="#Functions" >Functions</a></td><td class=SDescription></td></tr><tr class="SFunction SIndent1 SMarked"><td class=SEntry><a href="#core_bench_matrix" id=link1 onMouseOver="ShowTip(event, 'tt1', 'link1')" onMouseOut="HideTip('tt1')">core_bench_matrix</a></td><td class=SDescription>Benchmark function</td></tr><tr class="SFunction SIndent1"><td class=SEntry><a href="#matrix_test" id=link2 onMouseOver="ShowTip(event, 'tt2', 'link2')" onMouseOut="HideTip('tt2')">matrix_test</a></td><td class=SDescription>Perform matrix manipulation.</td></tr><tr class="SFunction SIndent1 SMarked"><td class=SEntry><a href="#matrix_sum" id=link3 onMouseOver="ShowTip(event, 'tt3', 'link3')" onMouseOut="HideTip('tt3')">matrix_sum</a></td><td class=SDescription>Calculate a function that depends on the values of elements in the matrix.</td></tr><tr class="SFunction SIndent1"><td class=SEntry><a href="#matrix_mul_const" id=link4 onMouseOver="ShowTip(event, 'tt4', 'link4')" onMouseOut="HideTip('tt4')">matrix_mul_const</a></td><td class=SDescription>Multiply a matrix by a constant. </td></tr><tr class="SFunction SIndent1 SMarked"><td class=SEntry><a href="#matrix_add_const" id=link5 onMouseOver="ShowTip(event, 'tt5', 'link5')" onMouseOut="HideTip('tt5')">matrix_add_const</a></td><td class=SDescription>Add a constant value to all elements of a matrix.</td></tr><tr class="SFunction SIndent1"><td class=SEntry><a href="#matrix_mul_vect" id=link6 onMouseOver="ShowTip(event, 'tt6', 'link6')" onMouseOut="HideTip('tt6')">matrix_mul_vect</a></td><td class=SDescription>Multiply a matrix by a vector. </td></tr><tr class="SFunction SIndent1 SMarked"><td class=SEntry><a href="#matrix_mul_matrix" id=link7 onMouseOver="ShowTip(event, 'tt7', 'link7')" onMouseOut="HideTip('tt7')">matrix_mul_matrix</a></td><td class=SDescription>Multiply a matrix by a matrix. </td></tr><tr class="SFunction SIndent1"><td class=SEntry><a href="#matrix_mul_matrix_bitextract" id=link8 onMouseOver="ShowTip(event, 'tt8', 'link8')" onMouseOut="HideTip('tt8')">matrix_mul_matrix_bitextract</a></td><td class=SDescription>Multiply a matrix by a matrix, and extract some bits from the result. </td></tr></table></div></div><!--END_ND_SUMMARY--></div></div></div>
+
+<div class="CGeneric"><div class=CTopic><h3 class=CTitle><a name="Description"></a>Description</h3><div class=CBody><p>Matrix manipulation benchmark</p><p>This very simple algorithm forms the basis of many more complex algorithms.</p><p>The tight inner loop is the focus of many optimizations (compiler as well as hardware based) and is thus relevant for embedded processing.</p><h4 class=CHeading>The total available data space will be divided to 3 parts</h4><table border=0 cellspacing=0 cellpadding=0 class=CDescriptionList><tr><td class=CDLEntry>NxN Matrix A</td><td class=CDLDescription>initialized with small values (upper 3/4 of the bits all zero).</td></tr><tr><td class=CDLEntry>NxN Matrix B</td><td class=CDLDescription>initialized with medium values (upper half of the bits all zero).</td></tr><tr><td class=CDLEntry>NxN Matrix C</td><td class=CDLDescription>used for the result.</td></tr></table><p>The actual values for A and B must be derived based on input that is not available at compile time.</p></div></div></div>
+
+<div class="CGroup"><div class=CTopic><h3 class=CTitle><a name="Functions"></a>Functions</h3></div></div>
+
+<div class="CFunction"><div class=CTopic><h3 class=CTitle><a name="core_bench_matrix"></a>core_bench_matrix</h3><div class=CBody><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>ee_u16 core_bench_matrix(</td><td class=PType nowrap>mat_params </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>p,</td></tr><tr><td></td><td class=PType nowrap>ee_s16 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>seed,</td></tr><tr><td></td><td class=PType nowrap>ee_u16 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>crc</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote><p>Benchmark function</p><p>Iterate <a href="#matrix_test" class=LFunction id=link9 onMouseOver="ShowTip(event, 'tt2', 'link9')" onMouseOut="HideTip('tt2')">matrix_test</a> N times, changing the matrix values slightly by a constant amount each time.</p></div></div></div>
+
+<div class="CFunction"><div class=CTopic><h3 class=CTitle><a name="matrix_test"></a>matrix_test</h3><div class=CBody><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>ee_s16 matrix_test(</td><td class=PType nowrap>ee_u32 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>N,</td></tr><tr><td></td><td class=PType nowrap>MATRES </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>C,</td></tr><tr><td></td><td class=PType nowrap>MATDAT </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>A,</td></tr><tr><td></td><td class=PType nowrap>MATDAT </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>B,</td></tr><tr><td></td><td class=PType nowrap>MATDAT </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>val</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote><p>Perform matrix manipulation.</p><h4 class=CHeading>Parameters</h4><table border=0 cellspacing=0 cellpadding=0 class=CDescriptionList><tr><td class=CDLEntry>N</td><td class=CDLDescription>Dimensions of the matrix.</td></tr><tr><td class=CDLEntry>C</td><td class=CDLDescription>memory for result matrix.</td></tr><tr><td class=CDLEntry>A</td><td class=CDLDescription>input matrix</td></tr><tr><td class=CDLEntry>B</td><td class=CDLDescription>operator matrix (not changed during operations)</td></tr></table><h4 class=CHeading>Returns</h4><p>A CRC value that captures all results calculated in the function. In particular, crc of the value calculated on the result matrix after each step by <a href="#matrix_sum" class=LFunction id=link10 onMouseOver="ShowTip(event, 'tt3', 'link10')" onMouseOut="HideTip('tt3')">matrix_sum</a>.</p><h4 class=CHeading>Operation</h4><table border=0 cellspacing=0 cellpadding=0 class=CDescriptionList><tr><td class=CDLEntry>1</td><td class=CDLDescription>Add a constant value to all elements of a matrix.</td></tr><tr><td class=CDLEntry>2</td><td class=CDLDescription>Multiply a matrix by a constant.</td></tr><tr><td class=CDLEntry>3</td><td class=CDLDescription>Multiply a matrix by a vector.</td></tr><tr><td class=CDLEntry>4</td><td class=CDLDescription>Multiply a matrix by a matrix.</td></tr><tr><td class=CDLEntry>5</td><td class=CDLDescription>Add a constant value to all elements of a matrix.</td></tr></table><p>After the last step, matrix A is back to original contents.</p></div></div></div>
+
+<div class="CFunction"><div class=CTopic><h3 class=CTitle><a name="matrix_sum"></a>matrix_sum</h3><div class=CBody><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>ee_s16 matrix_sum(</td><td class=PType nowrap>ee_u32 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>N,</td></tr><tr><td></td><td class=PType nowrap>MATRES </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>C,</td></tr><tr><td></td><td class=PType nowrap>MATDAT </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>clipval</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote><p>Calculate a function that depends on the values of elements in the matrix.</p><p>For each element, accumulate into a temporary variable.</p><p>As long as this value is under the parameter clipval, add 1 to the result if the element is bigger then the previous.</p><p>Otherwise, reset the accumulator and add 10 to the result.</p></div></div></div>
+
+<div class="CFunction"><div class=CTopic><h3 class=CTitle><a name="matrix_mul_const"></a>matrix_mul_const</h3><div class=CBody><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>void matrix_mul_const(</td><td class=PType nowrap>ee_u32 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>N,</td></tr><tr><td></td><td class=PType nowrap>MATRES </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>C,</td></tr><tr><td></td><td class=PType nowrap>MATDAT </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>A,</td></tr><tr><td></td><td class=PType nowrap>MATDAT </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>val</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote><p>Multiply a matrix by a constant. This could be used as a scaler for instance.</p></div></div></div>
+
+<div class="CFunction"><div class=CTopic><h3 class=CTitle><a name="matrix_add_const"></a>matrix_add_const</h3><div class=CBody><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>void matrix_add_const(</td><td class=PType nowrap>ee_u32 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>N,</td></tr><tr><td></td><td class=PType nowrap>MATDAT </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>A,</td></tr><tr><td></td><td class=PType nowrap>MATDAT </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>val</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote><p>Add a constant value to all elements of a matrix.</p></div></div></div>
+
+<div class="CFunction"><div class=CTopic><h3 class=CTitle><a name="matrix_mul_vect"></a>matrix_mul_vect</h3><div class=CBody><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>void matrix_mul_vect(</td><td class=PType nowrap>ee_u32 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>N,</td></tr><tr><td></td><td class=PType nowrap>MATRES </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>C,</td></tr><tr><td></td><td class=PType nowrap>MATDAT </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>A,</td></tr><tr><td></td><td class=PType nowrap>MATDAT </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>B</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote><p>Multiply a matrix by a vector. This is common in many simple filters (e.g. fir where a vector of coefficients is applied to the matrix.)</p></div></div></div>
+
+<div class="CFunction"><div class=CTopic><h3 class=CTitle><a name="matrix_mul_matrix"></a>matrix_mul_matrix</h3><div class=CBody><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>void matrix_mul_matrix(</td><td class=PType nowrap>ee_u32 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>N,</td></tr><tr><td></td><td class=PType nowrap>MATRES </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>C,</td></tr><tr><td></td><td class=PType nowrap>MATDAT </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>A,</td></tr><tr><td></td><td class=PType nowrap>MATDAT </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>B</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote><p>Multiply a matrix by a matrix. Basic code is used in many algorithms, mostly with minor changes such as scaling.</p></div></div></div>
+
+<div class="CFunction"><div class=CTopic><h3 class=CTitle><a name="matrix_mul_matrix_bitextract"></a>matrix_mul_matrix_bitextract</h3><div class=CBody><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>void matrix_mul_matrix_bitextract(</td><td class=PType nowrap>ee_u32 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>N,</td></tr><tr><td></td><td class=PType nowrap>MATRES </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>C,</td></tr><tr><td></td><td class=PType nowrap>MATDAT </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>A,</td></tr><tr><td></td><td class=PType nowrap>MATDAT </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>B</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote><p>Multiply a matrix by a matrix, and extract some bits from the result. Basic code is used in many algorithms, mostly with minor changes such as scaling.</p></div></div></div>
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+<!--START_ND_TOOLTIPS-->
+<div class=CToolTip id="tt1"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>ee_u16 core_bench_matrix(</td><td class=PType nowrap>mat_params </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>p,</td></tr><tr><td></td><td class=PType nowrap>ee_s16 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>seed,</td></tr><tr><td></td><td class=PType nowrap>ee_u16 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>crc</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Benchmark function</div></div><div class=CToolTip id="tt2"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>ee_s16 matrix_test(</td><td class=PType nowrap>ee_u32 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>N,</td></tr><tr><td></td><td class=PType nowrap>MATRES </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>C,</td></tr><tr><td></td><td class=PType nowrap>MATDAT </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>A,</td></tr><tr><td></td><td class=PType nowrap>MATDAT </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>B,</td></tr><tr><td></td><td class=PType nowrap>MATDAT </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>val</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Perform matrix manipulation.</div></div><div class=CToolTip id="tt3"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>ee_s16 matrix_sum(</td><td class=PType nowrap>ee_u32 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>N,</td></tr><tr><td></td><td class=PType nowrap>MATRES </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>C,</td></tr><tr><td></td><td class=PType nowrap>MATDAT </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>clipval</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Calculate a function that depends on the values of elements in the matrix.</div></div><div class=CToolTip id="tt4"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>void matrix_mul_const(</td><td class=PType nowrap>ee_u32 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>N,</td></tr><tr><td></td><td class=PType nowrap>MATRES </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>C,</td></tr><tr><td></td><td class=PType nowrap>MATDAT </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>A,</td></tr><tr><td></td><td class=PType nowrap>MATDAT </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>val</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Multiply a matrix by a constant. </div></div><div class=CToolTip id="tt5"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>void matrix_add_const(</td><td class=PType nowrap>ee_u32 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>N,</td></tr><tr><td></td><td class=PType nowrap>MATDAT </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>A,</td></tr><tr><td></td><td class=PType nowrap>MATDAT </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>val</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Add a constant value to all elements of a matrix.</div></div><div class=CToolTip id="tt6"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>void matrix_mul_vect(</td><td class=PType nowrap>ee_u32 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>N,</td></tr><tr><td></td><td class=PType nowrap>MATRES </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>C,</td></tr><tr><td></td><td class=PType nowrap>MATDAT </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>A,</td></tr><tr><td></td><td class=PType nowrap>MATDAT </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>B</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Multiply a matrix by a vector. </div></div><div class=CToolTip id="tt7"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>void matrix_mul_matrix(</td><td class=PType nowrap>ee_u32 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>N,</td></tr><tr><td></td><td class=PType nowrap>MATRES </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>C,</td></tr><tr><td></td><td class=PType nowrap>MATDAT </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>A,</td></tr><tr><td></td><td class=PType nowrap>MATDAT </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>B</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Multiply a matrix by a matrix. </div></div><div class=CToolTip id="tt8"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>void matrix_mul_matrix_bitextract(</td><td class=PType nowrap>ee_u32 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>N,</td></tr><tr><td></td><td class=PType nowrap>MATRES </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>C,</td></tr><tr><td></td><td class=PType nowrap>MATDAT </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>A,</td></tr><tr><td></td><td class=PType nowrap>MATDAT </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>B</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Multiply a matrix by a matrix, and extract some bits from the result. </div></div><!--END_ND_TOOLTIPS-->
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diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/files/core_state-c.html b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/files/core_state-c.html
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+<div id=Content><div class="CFile"><div class=CTopic id=MainTopic><h1 class=CTitle><a name="core_state.c"></a>core_state.c</h1><div class=CBody><!--START_ND_SUMMARY--><div class=Summary><div class=STitle>Summary</div><div class=SBorder><table border=0 cellspacing=0 cellpadding=0 class=STable><tr class="SMain"><td class=SEntry><a href="#core_state.c" >core_state.c</a></td><td class=SDescription></td></tr><tr class="SGeneric SMarked"><td class=SEntry><a href="#Description" >Description</a></td><td class=SDescription>Simple state machines like this one are used in many embedded products.</td></tr><tr class="SGroup"><td class=SEntry><a href="#Functions" >Functions</a></td><td class=SDescription></td></tr><tr class="SFunction SIndent1 SMarked"><td class=SEntry><a href="#core_bench_state" id=link1 onMouseOver="ShowTip(event, 'tt1', 'link1')" onMouseOut="HideTip('tt1')">core_bench_state</a></td><td class=SDescription>Benchmark function</td></tr><tr class="SFunction SIndent1"><td class=SEntry><a href="#core_init_state" id=link2 onMouseOver="ShowTip(event, 'tt2', 'link2')" onMouseOut="HideTip('tt2')">core_init_state</a></td><td class=SDescription>Initialize the input data for the state machine.</td></tr><tr class="SFunction SIndent1 SMarked"><td class=SEntry><a href="#core_state_transition" id=link3 onMouseOver="ShowTip(event, 'tt3', 'link3')" onMouseOut="HideTip('tt3')">core_state_transition</a></td><td class=SDescription>Actual state machine.</td></tr></table></div></div><!--END_ND_SUMMARY--></div></div></div>
+
+<div class="CGeneric"><div class=CTopic><h3 class=CTitle><a name="Description"></a>Description</h3><div class=CBody><p>Simple state machines like this one are used in many embedded products.</p><p>For more complex state machines, sometimes a state transition table implementation is used instead, trading speed of direct coding for ease of maintenance.</p><p>Since the main goal of using a state machine in CoreMark is to excercise the switch/if behaviour, we are using a small moore machine.</p><p>In particular, this machine tests type of string input, trying to determine whether the input is a number or something else. <a href="#Image1" class=CImageLink>(see core_state)</a>.</p><blockquote><div class=CImage><a name="Image1"></a><div class=CImageCaption>core_state</div><img src="docs/core_state.png" width="768" height="570"></div></blockquote></div></div></div>
+
+<div class="CGroup"><div class=CTopic><h3 class=CTitle><a name="Functions"></a>Functions</h3></div></div>
+
+<div class="CFunction"><div class=CTopic><h3 class=CTitle><a name="core_bench_state"></a>core_bench_state</h3><div class=CBody><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>ee_u16 core_bench_state(</td><td class=PType nowrap>ee_u32 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>blksize,</td></tr><tr><td></td><td class=PType nowrap>ee_u8 </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>memblock,</td></tr><tr><td></td><td class=PType nowrap>ee_s16 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>seed1,</td></tr><tr><td></td><td class=PType nowrap>ee_s16 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>seed2,</td></tr><tr><td></td><td class=PType nowrap>ee_s16 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>step,</td></tr><tr><td></td><td class=PType nowrap>ee_u16 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>crc</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote><p>Benchmark function</p><p>Go over the input twice, once direct, and once after introducing some corruption.</p></div></div></div>
+
+<div class="CFunction"><div class=CTopic><h3 class=CTitle><a name="core_init_state"></a>core_init_state</h3><div class=CBody><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>void core_init_state(</td><td class=PType nowrap>ee_u32 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>size,</td></tr><tr><td></td><td class=PType nowrap>ee_s16 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>seed,</td></tr><tr><td></td><td class=PType nowrap>ee_u8 </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>p</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote><p>Initialize the input data for the state machine.</p><p>Populate the input with several predetermined strings, interspersed. Actual patterns chosen depend on the seed parameter.</p><h4 class=CHeading>Note</h4><p>The seed parameter MUST be supplied from a source that cannot be determined at compile time</p></div></div></div>
+
+<div class="CFunction"><div class=CTopic><h3 class=CTitle><a name="core_state_transition"></a>core_state_transition</h3><div class=CBody><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>enum CORE_STATE core_state_transition(</td><td class=PTypePrefix nowrap>ee_u8 </td><td class=PType nowrap>**instr </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>,</td></tr><tr><td></td><td class=PTypePrefix nowrap></td><td class=PType nowrap>ee_u32 </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>transition_count</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote><p>Actual state machine.</p><h4 class=CHeading>The state machine will continue scanning until either</h4><table border=0 cellspacing=0 cellpadding=0 class=CDescriptionList><tr><td class=CDLEntry>1</td><td class=CDLDescription>an invalid input is detcted.</td></tr><tr><td class=CDLEntry>2</td><td class=CDLDescription>a valid number has been detected.</td></tr></table><p>The input pointer is updated to point to the end of the token, and the end state is returned (either specific format determined or invalid).</p></div></div></div>
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+<div class=CToolTip id="tt1"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>ee_u16 core_bench_state(</td><td class=PType nowrap>ee_u32 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>blksize,</td></tr><tr><td></td><td class=PType nowrap>ee_u8 </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>memblock,</td></tr><tr><td></td><td class=PType nowrap>ee_s16 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>seed1,</td></tr><tr><td></td><td class=PType nowrap>ee_s16 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>seed2,</td></tr><tr><td></td><td class=PType nowrap>ee_s16 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>step,</td></tr><tr><td></td><td class=PType nowrap>ee_u16 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>crc</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Benchmark function</div></div><div class=CToolTip id="tt2"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>void core_init_state(</td><td class=PType nowrap>ee_u32 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>size,</td></tr><tr><td></td><td class=PType nowrap>ee_s16 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>seed,</td></tr><tr><td></td><td class=PType nowrap>ee_u8 </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>p</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Initialize the input data for the state machine.</div></div><div class=CToolTip id="tt3"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>enum CORE_STATE core_state_transition(</td><td class=PTypePrefix nowrap>ee_u8 </td><td class=PType nowrap>**instr </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>,</td></tr><tr><td></td><td class=PTypePrefix nowrap></td><td class=PType nowrap>ee_u32 </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>transition_count</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Actual state machine.</div></div><!--END_ND_TOOLTIPS-->
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diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/files/core_util-c.html b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/files/core_util-c.html
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+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/files/core_util-c.html
@@ -0,0 +1,42 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd">
+
+<html><head><title>/cygdrive/d/dev/code/coremark/core_util.c - CoreMark</title><link rel="stylesheet" type="text/css" href="../styles/main.css"><script language=JavaScript src="../javascript/main.js"></script><script language=JavaScript src="../javascript/searchdata.js"></script></head><body class="ContentPage" onLoad="NDOnLoad()"><script language=JavaScript><!--
+if (browserType) {document.write("<div class=" + browserType + ">");if (browserVer) {document.write("<div class=" + browserVer + ">"); }}// --></script>
+
+<!-- Copyright 2009 EEMBC -->
+<!-- saved from url=(0026)http://www.naturaldocs.org -->
+
+
+
+
+<div id=Content><div class="CFile"><div class=CTopic id=MainTopic><h1 class=CTitle><a name="core_util.c"></a>core_util.c</h1><div class=CBody><!--START_ND_SUMMARY--><div class=Summary><div class=STitle>Summary</div><div class=SBorder><table border=0 cellspacing=0 cellpadding=0 class=STable><tr class="SMain"><td class=SEntry><a href="#core_util.c" >core_util.c</a></td><td class=SDescription></td></tr><tr class="SGroup"><td class=SEntry><a href="#Functions" >Functions</a></td><td class=SDescription></td></tr><tr class="SFunction SIndent1 SMarked"><td class=SEntry><a href="#get_seed" >get_seed</a></td><td class=SDescription>Get a values that cannot be determined at compile time.</td></tr><tr class="SFunction SIndent1"><td class=SEntry><a href="#crc*" >crc*</a></td><td class=SDescription>Service functions to calculate 16b CRC code.</td></tr></table></div></div><!--END_ND_SUMMARY--></div></div></div>
+
+<div class="CGroup"><div class=CTopic><h3 class=CTitle><a name="Functions"></a>Functions</h3></div></div>
+
+<div class="CFunction"><div class=CTopic><h3 class=CTitle><a name="get_seed"></a>get_seed</h3><div class=CBody><p>Get a values that cannot be determined at compile time.</p><h4 class=CHeading>Since different embedded systems and compilers are used, 3 different methods are provided</h4><table border=0 cellspacing=0 cellpadding=0 class=CDescriptionList><tr><td class=CDLEntry>1</td><td class=CDLDescription>Using a volatile variable. This method is only valid if the compiler is forced to generate code that reads the value of a volatile variable from memory at run time. Please note, if using this method, you would need to modify core_portme.c to generate training profile.</td></tr><tr><td class=CDLEntry>2</td><td class=CDLDescription>Command line arguments. This is the preferred method if command line arguments are supported.</td></tr><tr><td class=CDLEntry>3</td><td class=CDLDescription>System function. If none of the first 2 methods is available on the platform, a system function which is not a stub can be used.</td></tr></table><p>e.g. read the value on GPIO pins connected to switches, or invoke special simulator functions.</p></div></div></div>
+
+<div class="CFunction"><div class=CTopic><h3 class=CTitle><a name="crc*"></a>crc*</h3><div class=CBody><p>Service functions to calculate 16b CRC code.</p></div></div></div>
+
+</div><!--Content-->
+
+
+<div id=Footer><a href="http://www.naturaldocs.org">Copyright 2009 EEMBC</a></div><!--Footer-->
+
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+<div id=Menu><div class=MTitle>CoreMark<div class=MSubTitle>(c) EEMBC</div></div><div class=MEntry><div class=MFile><a href="readme-txt.html">CoreMark</a></div></div><div class=MEntry><div class=MFile><a href="release_notes-txt.html">Release Notes</a></div></div><div class=MEntry><div class=MGroup><a href="javascript:ToggleMenu('MGroupContent2')">Source</a><div class=MGroupContent id=MGroupContent2><div class=MEntry><div class=MFile><a href="core_list_join-c.html">core_list_join.c</a></div></div><div class=MEntry><div class=MFile><a href="core_main-c.html">core_main.c</a></div></div><div class=MEntry><div class=MFile><a href="core_matrix-c.html">core_matrix.c</a></div></div><div class=MEntry><div class=MFile><a href="PIC32/core_portme-mak.html">core_portme.mak</a></div></div><div class=MEntry><div class=MFile><a href="core_state-c.html">core_state.c</a></div></div><div class=MEntry><div class=MFile id=MSelected>core_util.c</div></div><div class=MEntry><div class=MFile><a href="coremark-h.html">coremark.h</a></div></div><div class=MEntry><div class=MGroup><a href="javascript:ToggleMenu('MGroupContent1')">Porting</a><div class=MGroupContent id=MGroupContent1><div class=MEntry><div class=MFile><a href="linux/core_portme-c.html">PORT_DIR/<span class=HB> </span>core_portme.c</a></div></div><div class=MEntry><div class=MFile><a href="linux/core_portme-h.html">PORT_DIR/<span class=HB> </span>core_portme.h</a></div></div><div class=MEntry><div class=MFile><a href="linux/core_portme-mak.html">PORT_DIR/<span class=HB> </span>core_portme.mak</a></div></div></div></div></div></div></div></div><div class=MEntry><div class=MGroup><a href="javascript:ToggleMenu('MGroupContent3')">Index</a><div class=MGroupContent id=MGroupContent3><div class=MEntry><div class=MIndex><a href="../index/General.html">Everything</a></div></div><div class=MEntry><div class=MIndex><a href="../index/Files.html">Files</a></div></div><div class=MEntry><div class=MIndex><a href="../index/Functions.html">Functions</a></div></div><div class=MEntry><div class=MIndex><a href="../index/Types.html">Types</a></div></div><div class=MEntry><div class=MIndex><a href="../index/Configuration.html">Configurations</a></div></div><div class=MEntry><div class=MIndex><a href="../index/Variables.html">Variables</a></div></div><div class=MEntry><div class=MIndex><a href="../index/BuildTargets.html">Build Targets</a></div></div></div></div></div><script type="text/javascript"><!--
+var searchPanel = new SearchPanel("searchPanel", "HTML", "../search");
+--></script><div id=MSearchPanel class=MSearchPanelInactive><input type=text id=MSearchField value=Search onFocus="searchPanel.OnSearchFieldFocus(true)" onBlur="searchPanel.OnSearchFieldFocus(false)" onKeyUp="searchPanel.OnSearchFieldChange()"><select id=MSearchType onFocus="searchPanel.OnSearchTypeFocus(true)" onBlur="searchPanel.OnSearchTypeFocus(false)" onChange="searchPanel.OnSearchTypeChange()"><option id=MSearchEverything selected value="General">Everything</option><option value="BuildTargets">Build Targets</option><option value="Configuration">Configuration</option><option value="Files">Files</option><option value="Functions">Functions</option><option value="Types">Types</option><option value="Variables">Variables</option></select></div></div><!--Menu-->
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+if (browserType) {if (browserVer) {document.write("</div>"); }document.write("</div>");}// --></script></body></html>
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diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/files/coremark-h.html b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/files/coremark-h.html
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--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/files/coremark-h.html
@@ -0,0 +1,46 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd">
+
+<html><head><title>/cygdrive/d/dev/code/coremark/coremark.h - CoreMark</title><link rel="stylesheet" type="text/css" href="../styles/main.css"><script language=JavaScript src="../javascript/main.js"></script><script language=JavaScript src="../javascript/searchdata.js"></script></head><body class="ContentPage" onLoad="NDOnLoad()"><script language=JavaScript><!--
+if (browserType) {document.write("<div class=" + browserType + ">");if (browserVer) {document.write("<div class=" + browserVer + ">"); }}// --></script>
+
+<!-- Copyright 2009 EEMBC -->
+<!-- saved from url=(0026)http://www.naturaldocs.org -->
+
+
+
+
+<div id=Content><div class="CFile"><div class=CTopic id=MainTopic><h1 class=CTitle><a name="coremark.h"></a>coremark.h</h1><div class=CBody><!--START_ND_SUMMARY--><div class=Summary><div class=STitle>Summary</div><div class=SBorder><table border=0 cellspacing=0 cellpadding=0 class=STable><tr class="SMain"><td class=SEntry><a href="#coremark.h" >coremark.h</a></td><td class=SDescription></td></tr><tr class="SGeneric SMarked"><td class=SEntry><a href="#Description" >Description</a></td><td class=SDescription>This file contains declarations of the various benchmark functions.</td></tr><tr class="SGroup"><td class=SEntry><a href="#Configuration" >Configuration</a></td><td class=SDescription></td></tr><tr class="SConfiguration SIndent1 SMarked"><td class=SEntry><a href="#TOTAL_DATA_SIZE" >TOTAL_DATA_SIZE</a></td><td class=SDescription>Define total size for data algorithms will operate on</td></tr><tr class="SGroup"><td class=SEntry><a href="#Types" >Types</a></td><td class=SDescription></td></tr><tr class="SType SIndent1 SMarked"><td class=SEntry><a href="#secs_ret" >secs_ret</a></td><td class=SDescription>For machines that have floating point support, get number of seconds as a double. </td></tr></table></div></div><!--END_ND_SUMMARY--></div></div></div>
+
+<div class="CGeneric"><div class=CTopic><h3 class=CTitle><a name="Description"></a>Description</h3><div class=CBody><p>This file contains declarations of the various benchmark functions.</p></div></div></div>
+
+<div class="CGroup"><div class=CTopic><h3 class=CTitle><a name="Configuration"></a>Configuration</h3></div></div>
+
+<div class="CConfiguration"><div class=CTopic><h3 class=CTitle><a name="TOTAL_DATA_SIZE"></a>TOTAL_DATA_SIZE</h3><div class=CBody><p>Define total size for data algorithms will operate on</p></div></div></div>
+
+<div class="CGroup"><div class=CTopic><h3 class=CTitle><a name="Types"></a>Types</h3></div></div>
+
+<div class="CType"><div class=CTopic><h3 class=CTitle><a name="secs_ret"></a>secs_ret</h3><div class=CBody><p>For machines that have floating point support, get number of seconds as a double. Otherwise an unsigned int.</p></div></div></div>
+
+</div><!--Content-->
+
+
+<div id=Footer><a href="http://www.naturaldocs.org">Copyright 2009 EEMBC</a></div><!--Footer-->
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+<div id=Menu><div class=MTitle>CoreMark<div class=MSubTitle>(c) EEMBC</div></div><div class=MEntry><div class=MFile><a href="readme-txt.html">CoreMark</a></div></div><div class=MEntry><div class=MFile><a href="release_notes-txt.html">Release Notes</a></div></div><div class=MEntry><div class=MGroup><a href="javascript:ToggleMenu('MGroupContent2')">Source</a><div class=MGroupContent id=MGroupContent2><div class=MEntry><div class=MFile><a href="core_list_join-c.html">core_list_join.c</a></div></div><div class=MEntry><div class=MFile><a href="core_main-c.html">core_main.c</a></div></div><div class=MEntry><div class=MFile><a href="core_matrix-c.html">core_matrix.c</a></div></div><div class=MEntry><div class=MFile><a href="PIC32/core_portme-mak.html">core_portme.mak</a></div></div><div class=MEntry><div class=MFile><a href="core_state-c.html">core_state.c</a></div></div><div class=MEntry><div class=MFile><a href="core_util-c.html">core_util.c</a></div></div><div class=MEntry><div class=MFile id=MSelected>coremark.h</div></div><div class=MEntry><div class=MGroup><a href="javascript:ToggleMenu('MGroupContent1')">Porting</a><div class=MGroupContent id=MGroupContent1><div class=MEntry><div class=MFile><a href="linux/core_portme-c.html">PORT_DIR/<span class=HB> </span>core_portme.c</a></div></div><div class=MEntry><div class=MFile><a href="linux/core_portme-h.html">PORT_DIR/<span class=HB> </span>core_portme.h</a></div></div><div class=MEntry><div class=MFile><a href="linux/core_portme-mak.html">PORT_DIR/<span class=HB> </span>core_portme.mak</a></div></div></div></div></div></div></div></div><div class=MEntry><div class=MGroup><a href="javascript:ToggleMenu('MGroupContent3')">Index</a><div class=MGroupContent id=MGroupContent3><div class=MEntry><div class=MIndex><a href="../index/General.html">Everything</a></div></div><div class=MEntry><div class=MIndex><a href="../index/Files.html">Files</a></div></div><div class=MEntry><div class=MIndex><a href="../index/Functions.html">Functions</a></div></div><div class=MEntry><div class=MIndex><a href="../index/Types.html">Types</a></div></div><div class=MEntry><div class=MIndex><a href="../index/Configuration.html">Configurations</a></div></div><div class=MEntry><div class=MIndex><a href="../index/Variables.html">Variables</a></div></div><div class=MEntry><div class=MIndex><a href="../index/BuildTargets.html">Build Targets</a></div></div></div></div></div><script type="text/javascript"><!--
+var searchPanel = new SearchPanel("searchPanel", "HTML", "../search");
+--></script><div id=MSearchPanel class=MSearchPanelInactive><input type=text id=MSearchField value=Search onFocus="searchPanel.OnSearchFieldFocus(true)" onBlur="searchPanel.OnSearchFieldFocus(false)" onKeyUp="searchPanel.OnSearchFieldChange()"><select id=MSearchType onFocus="searchPanel.OnSearchTypeFocus(true)" onBlur="searchPanel.OnSearchTypeFocus(false)" onChange="searchPanel.OnSearchTypeChange()"><option id=MSearchEverything selected value="General">Everything</option><option value="BuildTargets">Build Targets</option><option value="Configuration">Configuration</option><option value="Files">Files</option><option value="Functions">Functions</option><option value="Types">Types</option><option value="Variables">Variables</option></select></div></div><!--Menu-->
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diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/files/docs/core_state.png b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/files/docs/core_state.png
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@@ -0,0 +1,58 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd">
+
+<html><head><title>core_portme.c - CoreMark</title><link rel="stylesheet" type="text/css" href="../../styles/main.css"><script language=JavaScript src="../../javascript/main.js"></script><script language=JavaScript src="../../javascript/searchdata.js"></script></head><body class="ContentPage" onLoad="NDOnLoad()"><script language=JavaScript><!--
+if (browserType) {document.write("<div class=" + browserType + ">");if (browserVer) {document.write("<div class=" + browserVer + ">"); }}// --></script>
+
+<!-- Copyright 2009 EEMBC -->
+<!-- saved from url=(0026)http://www.naturaldocs.org -->
+
+
+
+
+<div id=Content><div class="CFile"><div class=CTopic id=MainTopic><h1 class=CTitle><a name="core_portme.c"></a>core_portme.c</h1><div class=CBody><!--START_ND_SUMMARY--><div class=Summary><div class=STitle>Summary</div><div class=SBorder><table border=0 cellspacing=0 cellpadding=0 class=STable><tr class="SMain"><td class=SEntry><a href="#core_portme.c" >core_portme.c</a></td><td class=SDescription></td></tr><tr class="SFunction SMarked"><td class=SEntry><a href="#portable_malloc" id=link1 onMouseOver="ShowTip(event, 'tt1', 'link1')" onMouseOut="HideTip('tt1')">portable_malloc</a></td><td class=SDescription>Provide malloc() functionality in a platform specific way.</td></tr><tr class="SFunction"><td class=SEntry><a href="#portable_free" id=link2 onMouseOver="ShowTip(event, 'tt2', 'link2')" onMouseOut="HideTip('tt2')">portable_free</a></td><td class=SDescription>Provide free() functionality in a platform specific way.</td></tr><tr class="SGroup"><td class=SEntry><a href="#TIMER_RES_DIVIDER" >TIMER_RES_DIVIDER</a></td><td class=SDescription>Divider to trade off timer resolution and total time that can be measured.</td></tr><tr class="SFunction SIndent1 SMarked"><td class=SEntry><a href="#start_time" id=link3 onMouseOver="ShowTip(event, 'tt3', 'link3')" onMouseOut="HideTip('tt3')">start_time</a></td><td class=SDescription>This function will be called right before starting the timed portion of the benchmark.</td></tr><tr class="SFunction SIndent1"><td class=SEntry><a href="#stop_time" id=link4 onMouseOver="ShowTip(event, 'tt4', 'link4')" onMouseOut="HideTip('tt4')">stop_time</a></td><td class=SDescription>This function will be called right after ending the timed portion of the benchmark.</td></tr><tr class="SFunction SIndent1 SMarked"><td class=SEntry><a href="#get_time" id=link5 onMouseOver="ShowTip(event, 'tt5', 'link5')" onMouseOut="HideTip('tt5')">get_time</a></td><td class=SDescription>Return an abstract “ticks” number that signifies time on the system.</td></tr><tr class="SFunction SIndent1"><td class=SEntry><a href="#time_in_secs" id=link6 onMouseOver="ShowTip(event, 'tt6', 'link6')" onMouseOut="HideTip('tt6')">time_in_secs</a></td><td class=SDescription>Convert the value returned by get_time to seconds.</td></tr><tr class="SFunction SIndent1 SMarked"><td class=SEntry><a href="#portable_init" id=link7 onMouseOver="ShowTip(event, 'tt7', 'link7')" onMouseOut="HideTip('tt7')">portable_init</a></td><td class=SDescription>Target specific initialization code Test for some common mistakes.</td></tr><tr class="SFunction SIndent1"><td class=SEntry><a href="#portable_fini" id=link8 onMouseOver="ShowTip(event, 'tt8', 'link8')" onMouseOut="HideTip('tt8')">portable_fini</a></td><td class=SDescription>Target specific final code</td></tr><tr class="SFunction SIndent1 SMarked"><td class=SEntry><a href="#core_start_parallel" >core_start_parallel</a></td><td class=SDescription>Start benchmarking in a parallel context.</td></tr><tr class="SFunction SIndent1"><td class=SEntry><a href="#core_stop_parallel" >core_stop_parallel</a></td><td class=SDescription>Stop a parallel context execution of coremark, and gather the results.</td></tr></table></div></div><!--END_ND_SUMMARY--></div></div></div>
+
+<div class="CFunction"><div class=CTopic><h3 class=CTitle><a name="portable_malloc"></a>portable_malloc</h3><div class=CBody><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>void *portable_malloc(</td><td class=PType nowrap>size_t </td><td class=PParameter nowrap>size</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote><p>Provide malloc() functionality in a platform specific way.</p></div></div></div>
+
+<div class="CFunction"><div class=CTopic><h3 class=CTitle><a name="portable_free"></a>portable_free</h3><div class=CBody><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>void portable_free(</td><td class=PType nowrap>void </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>p</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote><p>Provide free() functionality in a platform specific way.</p></div></div></div>
+
+<div class="CGroup"><div class=CTopic><h3 class=CTitle><a name="TIMER_RES_DIVIDER"></a>TIMER_RES_DIVIDER</h3><div class=CBody><p>Divider to trade off timer resolution and total time that can be measured.</p><p>Use lower values to increase resolution, but make sure that overflow does not occur. If there are issues with the return value overflowing, increase this value.</p></div></div></div>
+
+<div class="CFunction"><div class=CTopic><h3 class=CTitle><a name="start_time"></a>start_time</h3><div class=CBody><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>void start_time(</td><td class=PParameter nowrap>void</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote><p>This function will be called right before starting the timed portion of the benchmark.</p><p>Implementation may be capturing a system timer (as implemented in the example code) or zeroing some system parameters - e.g. setting the cpu clocks cycles to 0.</p></div></div></div>
+
+<div class="CFunction"><div class=CTopic><h3 class=CTitle><a name="stop_time"></a>stop_time</h3><div class=CBody><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>void stop_time(</td><td class=PParameter nowrap>void</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote><p>This function will be called right after ending the timed portion of the benchmark.</p><p>Implementation may be capturing a system timer (as implemented in the example code) or other system parameters - e.g. reading the current value of cpu cycles counter.</p></div></div></div>
+
+<div class="CFunction"><div class=CTopic><h3 class=CTitle><a name="get_time"></a>get_time</h3><div class=CBody><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>CORE_TICKS get_time(</td><td class=PParameter nowrap>void</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote><p>Return an abstract “ticks” number that signifies time on the system.</p><p>Actual value returned may be cpu cycles, milliseconds or any other value, as long as it can be converted to seconds by <a href="#time_in_secs" class=LFunction id=link9 onMouseOver="ShowTip(event, 'tt6', 'link9')" onMouseOut="HideTip('tt6')">time_in_secs</a>. This methodology is taken to accomodate any hardware or simulated platform. The sample implementation returns millisecs by default, and the resolution is controlled by <a href="#TIMER_RES_DIVIDER" class=LGroup id=link10 onMouseOver="ShowTip(event, 'tt9', 'link10')" onMouseOut="HideTip('tt9')">TIMER_RES_DIVIDER</a></p></div></div></div>
+
+<div class="CFunction"><div class=CTopic><h3 class=CTitle><a name="time_in_secs"></a>time_in_secs</h3><div class=CBody><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>secs_ret time_in_secs(</td><td class=PType nowrap>CORE_TICKS </td><td class=PParameter nowrap>ticks</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote><p>Convert the value returned by get_time to seconds.</p><p>The <a href="../coremark-h.html#secs_ret" class=LType id=link11 onMouseOver="ShowTip(event, 'tt10', 'link11')" onMouseOut="HideTip('tt10')">secs_ret</a> type is used to accomodate systems with no support for floating point. Default implementation implemented by the EE_TICKS_PER_SEC macro above.</p></div></div></div>
+
+<div class="CFunction"><div class=CTopic><h3 class=CTitle><a name="portable_init"></a>portable_init</h3><div class=CBody><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>void portable_init(</td><td class=PType nowrap>core_portable </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>p,</td></tr><tr><td></td><td class=PType nowrap>int </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>argc,</td></tr><tr><td></td><td class=PType nowrap>char </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>argv[]</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote><p>Target specific initialization code Test for some common mistakes.</p></div></div></div>
+
+<div class="CFunction"><div class=CTopic><h3 class=CTitle><a name="portable_fini"></a>portable_fini</h3><div class=CBody><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>void portable_fini(</td><td class=PType nowrap>core_portable </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>p</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote><p>Target specific final code</p></div></div></div>
+
+<div class="CFunction"><div class=CTopic><h3 class=CTitle><a name="core_start_parallel"></a>core_start_parallel</h3><div class=CBody><p>Start benchmarking in a parallel context.</p><p>Three implementations are provided, one using pthreads, one using fork and shared mem, and one using fork and sockets. Other implementations using MCAPI or other standards can easily be devised.</p></div></div></div>
+
+<div class="CFunction"><div class=CTopic><h3 class=CTitle><a name="core_stop_parallel"></a>core_stop_parallel</h3><div class=CBody><p>Stop a parallel context execution of coremark, and gather the results.</p><p>Three implementations are provided, one using pthreads, one using fork and shared mem, and one using fork and sockets. Other implementations using MCAPI or other standards can easily be devised.</p></div></div></div>
+
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+<div id=Menu><div class=MTitle>CoreMark<div class=MSubTitle>(c) EEMBC</div></div><div class=MEntry><div class=MFile><a href="../readme-txt.html">CoreMark</a></div></div><div class=MEntry><div class=MFile><a href="../release_notes-txt.html">Release Notes</a></div></div><div class=MEntry><div class=MGroup><a href="javascript:ToggleMenu('MGroupContent2')">Source</a><div class=MGroupContent id=MGroupContent2><div class=MEntry><div class=MFile><a href="../core_list_join-c.html">core_list_join.c</a></div></div><div class=MEntry><div class=MFile><a href="../core_main-c.html">core_main.c</a></div></div><div class=MEntry><div class=MFile><a href="../core_matrix-c.html">core_matrix.c</a></div></div><div class=MEntry><div class=MFile><a href="../PIC32/core_portme-mak.html">core_portme.mak</a></div></div><div class=MEntry><div class=MFile><a href="../core_state-c.html">core_state.c</a></div></div><div class=MEntry><div class=MFile><a href="../core_util-c.html">core_util.c</a></div></div><div class=MEntry><div class=MFile><a href="../coremark-h.html">coremark.h</a></div></div><div class=MEntry><div class=MGroup><a href="javascript:ToggleMenu('MGroupContent1')">Porting</a><div class=MGroupContent id=MGroupContent1><div class=MEntry><div class=MFile id=MSelected>PORT_DIR/<span class=HB> </span>core_portme.c</div></div><div class=MEntry><div class=MFile><a href="core_portme-h.html">PORT_DIR/<span class=HB> </span>core_portme.h</a></div></div><div class=MEntry><div class=MFile><a href="core_portme-mak.html">PORT_DIR/<span class=HB> </span>core_portme.mak</a></div></div></div></div></div></div></div></div><div class=MEntry><div class=MGroup><a href="javascript:ToggleMenu('MGroupContent3')">Index</a><div class=MGroupContent id=MGroupContent3><div class=MEntry><div class=MIndex><a href="../../index/General.html">Everything</a></div></div><div class=MEntry><div class=MIndex><a href="../../index/Files.html">Files</a></div></div><div class=MEntry><div class=MIndex><a href="../../index/Functions.html">Functions</a></div></div><div class=MEntry><div class=MIndex><a href="../../index/Types.html">Types</a></div></div><div class=MEntry><div class=MIndex><a href="../../index/Configuration.html">Configurations</a></div></div><div class=MEntry><div class=MIndex><a href="../../index/Variables.html">Variables</a></div></div><div class=MEntry><div class=MIndex><a href="../../index/BuildTargets.html">Build Targets</a></div></div></div></div></div><script type="text/javascript"><!--
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+
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+<!--START_ND_TOOLTIPS-->
+<div class=CToolTip id="tt1"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>void *portable_malloc(</td><td class=PType nowrap>size_t </td><td class=PParameter nowrap>size</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Provide malloc() functionality in a platform specific way.</div></div><div class=CToolTip id="tt2"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>void portable_free(</td><td class=PType nowrap>void </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>p</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Provide free() functionality in a platform specific way.</div></div><div class=CToolTip id="tt3"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>void start_time(</td><td class=PParameter nowrap>void</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>This function will be called right before starting the timed portion of the benchmark.</div></div><div class=CToolTip id="tt4"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>void stop_time(</td><td class=PParameter nowrap>void</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>This function will be called right after ending the timed portion of the benchmark.</div></div><div class=CToolTip id="tt5"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>CORE_TICKS get_time(</td><td class=PParameter nowrap>void</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Return an abstract “ticks” number that signifies time on the system.</div></div><div class=CToolTip id="tt6"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>secs_ret time_in_secs(</td><td class=PType nowrap>CORE_TICKS </td><td class=PParameter nowrap>ticks</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Convert the value returned by get_time to seconds.</div></div><div class=CToolTip id="tt7"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>void portable_init(</td><td class=PType nowrap>core_portable </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>p,</td></tr><tr><td></td><td class=PType nowrap>int </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>argc,</td></tr><tr><td></td><td class=PType nowrap>char </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>argv[]</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Target specific initialization code Test for some common mistakes.</div></div><div class=CToolTip id="tt8"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>void portable_fini(</td><td class=PType nowrap>core_portable </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>p</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Target specific final code</div></div><div class=CToolTip id="tt9"><div class=CGroup>Divider to trade off timer resolution and total time that can be measured.</div></div><div class=CToolTip id="tt10"><div class=CType>For machines that have floating point support, get number of seconds as a double. </div></div><!--END_ND_TOOLTIPS-->
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diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/files/linux/core_portme-h.html b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/files/linux/core_portme-h.html
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@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd">
+
+<html><head><title>core_portme.h - CoreMark</title><link rel="stylesheet" type="text/css" href="../../styles/main.css"><script language=JavaScript src="../../javascript/main.js"></script><script language=JavaScript src="../../javascript/searchdata.js"></script></head><body class="ContentPage" onLoad="NDOnLoad()"><script language=JavaScript><!--
+if (browserType) {document.write("<div class=" + browserType + ">");if (browserVer) {document.write("<div class=" + browserVer + ">"); }}// --></script>
+
+<!-- Copyright 2009 EEMBC -->
+<!-- saved from url=(0026)http://www.naturaldocs.org -->
+
+
+
+
+<div id=Content><div class="CFile"><div class=CTopic id=MainTopic><h1 class=CTitle><a name="core_portme.h"></a>core_portme.h</h1><div class=CBody><!--START_ND_SUMMARY--><div class=Summary><div class=STitle>Summary</div><div class=SBorder><table border=0 cellspacing=0 cellpadding=0 class=STable><tr class="SMain"><td class=SEntry><a href="#core_portme.h" >core_portme.h</a></td><td class=SDescription></td></tr><tr class="SGeneric SMarked"><td class=SEntry><a href="#Description" >Description</a></td><td class=SDescription>This file contains configuration constants required to execute on different platforms</td></tr><tr class="SGroup"><td class=SEntry><a href="#Configuration" >Configuration</a></td><td class=SDescription></td></tr><tr class="SConfiguration SIndent1 SMarked"><td class=SEntry><a href="#HAS_FLOAT" >HAS_FLOAT</a></td><td class=SDescription>Define to 1 if the platform supports floating point.</td></tr><tr class="SConfiguration SIndent1"><td class=SEntry><a href="#HAS_TIME_H" >HAS_TIME_H</a></td><td class=SDescription>Define to 1 if platform has the time.h header file, and implementation of functions thereof.</td></tr><tr class="SConfiguration SIndent1 SMarked"><td class=SEntry><a href="#USE_CLOCK" >USE_CLOCK</a></td><td class=SDescription>Define to 1 if platform has the time.h header file, and implementation of functions thereof.</td></tr><tr class="SConfiguration SIndent1"><td class=SEntry><a href="#HAS_STDIO" >HAS_STDIO</a></td><td class=SDescription>Define to 1 if the platform has stdio.h.</td></tr><tr class="SConfiguration SIndent1 SMarked"><td class=SEntry><a href="#HAS_PRINTF" >HAS_PRINTF</a></td><td class=SDescription>Define to 1 if the platform has stdio.h and implements the printf function.</td></tr><tr class="SConfiguration SIndent1"><td class=SEntry><a href="#CORE_TICKS" >CORE_TICKS</a></td><td class=SDescription>Define type of return from the timing functions.</td></tr><tr class="SConfiguration SIndent1 SMarked"><td class=SEntry><a href="#SEED_METHOD" >SEED_METHOD</a></td><td class=SDescription>Defines method to get seed values that cannot be computed at compile time.</td></tr><tr class="SConfiguration SIndent1"><td class=SEntry><a href="#MEM_METHOD" >MEM_METHOD</a></td><td class=SDescription>Defines method to get a block of memry.</td></tr><tr class="SConfiguration SIndent1 SMarked"><td class=SEntry><a href="#MULTITHREAD" >MULTITHREAD</a></td><td class=SDescription>Define for parallel execution</td></tr><tr class="SConfiguration SIndent1"><td class=SEntry><a href="#USE_PTHREAD" >USE_PTHREAD</a></td><td class=SDescription>Sample implementation for launching parallel contexts This implementation uses pthread_thread_create and pthread_join.</td></tr><tr class="SConfiguration SIndent1 SMarked"><td class=SEntry><a href="#USE_FORK" >USE_FORK</a></td><td class=SDescription>Sample implementation for launching parallel contexts This implementation uses fork, waitpid, shmget,shmat and shmdt.</td></tr><tr class="SConfiguration SIndent1"><td class=SEntry><a href="#USE_SOCKET" >USE_SOCKET</a></td><td class=SDescription>Sample implementation for launching parallel contexts This implementation uses fork, socket, sendto and recvfrom</td></tr><tr class="SConfiguration SIndent1 SMarked"><td class=SEntry><a href="#MAIN_HAS_NOARGC" >MAIN_HAS_NOARGC</a></td><td class=SDescription>Needed if platform does not support getting arguments to main.</td></tr><tr class="SConfiguration SIndent1"><td class=SEntry><a href="#MAIN_HAS_NORETURN" >MAIN_HAS_NORETURN</a></td><td class=SDescription>Needed if platform does not support returning a value from main.</td></tr><tr class="SGroup"><td class=SEntry><a href="#Variables" >Variables</a></td><td class=SDescription></td></tr><tr class="SVariable SIndent1 SMarked"><td class=SEntry><a href="#default_num_contexts" id=link1 onMouseOver="ShowTip(event, 'tt1', 'link1')" onMouseOut="HideTip('tt1')">default_num_contexts</a></td><td class=SDescription>Number of contexts to spawn in multicore context. </td></tr></table></div></div><!--END_ND_SUMMARY--></div></div></div>
+
+<div class="CGeneric"><div class=CTopic><h3 class=CTitle><a name="Description"></a>Description</h3><div class=CBody><p>This file contains configuration constants required to execute on different platforms</p></div></div></div>
+
+<div class="CGroup"><div class=CTopic><h3 class=CTitle><a name="Configuration"></a>Configuration</h3></div></div>
+
+<div class="CConfiguration"><div class=CTopic><h3 class=CTitle><a name="HAS_FLOAT"></a>HAS_FLOAT</h3><div class=CBody><p>Define to 1 if the platform supports floating point.</p></div></div></div>
+
+<div class="CConfiguration"><div class=CTopic><h3 class=CTitle><a name="HAS_TIME_H"></a>HAS_TIME_H</h3><div class=CBody><p>Define to 1 if platform has the time.h header file, and implementation of functions thereof.</p></div></div></div>
+
+<div class="CConfiguration"><div class=CTopic><h3 class=CTitle><a name="USE_CLOCK"></a>USE_CLOCK</h3><div class=CBody><p>Define to 1 if platform has the time.h header file, and implementation of functions thereof.</p></div></div></div>
+
+<div class="CConfiguration"><div class=CTopic><h3 class=CTitle><a name="HAS_STDIO"></a>HAS_STDIO</h3><div class=CBody><p>Define to 1 if the platform has stdio.h.</p></div></div></div>
+
+<div class="CConfiguration"><div class=CTopic><h3 class=CTitle><a name="HAS_PRINTF"></a>HAS_PRINTF</h3><div class=CBody><p>Define to 1 if the platform has stdio.h and implements the printf function.</p></div></div></div>
+
+<div class="CConfiguration"><div class=CTopic><h3 class=CTitle><a name="CORE_TICKS"></a>CORE_TICKS</h3><div class=CBody><p>Define type of return from the timing functions.</p></div></div></div>
+
+<div class="CConfiguration"><div class=CTopic><h3 class=CTitle><a name="SEED_METHOD"></a>SEED_METHOD</h3><div class=CBody><p>Defines method to get seed values that cannot be computed at compile time.</p><h4 class=CHeading>Valid values</h4><table border=0 cellspacing=0 cellpadding=0 class=CDescriptionList><tr><td class=CDLEntry>SEED_ARG</td><td class=CDLDescription>from command line.</td></tr><tr><td class=CDLEntry>SEED_FUNC</td><td class=CDLDescription>from a system function.</td></tr><tr><td class=CDLEntry>SEED_VOLATILE</td><td class=CDLDescription>from volatile variables.</td></tr></table></div></div></div>
+
+<div class="CConfiguration"><div class=CTopic><h3 class=CTitle><a name="MEM_METHOD"></a>MEM_METHOD</h3><div class=CBody><p>Defines method to get a block of memry.</p><h4 class=CHeading>Valid values</h4><table border=0 cellspacing=0 cellpadding=0 class=CDescriptionList><tr><td class=CDLEntry>MEM_MALLOC</td><td class=CDLDescription>for platforms that implement malloc and have malloc.h.</td></tr><tr><td class=CDLEntry>MEM_STATIC</td><td class=CDLDescription>to use a static memory array.</td></tr><tr><td class=CDLEntry>MEM_STACK</td><td class=CDLDescription>to allocate the data block on the stack (NYI).</td></tr></table></div></div></div>
+
+<div class="CConfiguration"><div class=CTopic><h3 class=CTitle><a name="MULTITHREAD"></a>MULTITHREAD</h3><div class=CBody><p>Define for parallel execution</p><h4 class=CHeading>Valid values</h4><table border=0 cellspacing=0 cellpadding=0 class=CDescriptionList><tr><td class=CDLEntry>1</td><td class=CDLDescription>only one context (default).</td></tr><tr><td class=CDLEntry>N>1</td><td class=CDLDescription>will execute N copies in parallel.</td></tr></table><h4 class=CHeading>Note</h4><p>If this flag is defined to more then 1, an implementation for launching parallel contexts must be defined.</p><p>Two sample implementations are provided. Use <a href="#USE_PTHREAD" class=LConfiguration id=link2 onMouseOver="ShowTip(event, 'tt2', 'link2')" onMouseOut="HideTip('tt2')">USE_PTHREAD</a> or <a href="#USE_FORK" class=LConfiguration id=link3 onMouseOver="ShowTip(event, 'tt3', 'link3')" onMouseOut="HideTip('tt3')">USE_FORK</a> to enable them.</p><p>It is valid to have a different implementation of <a href="core_portme-c.html#core_start_parallel" class=LFunction id=link4 onMouseOver="ShowTip(event, 'tt4', 'link4')" onMouseOut="HideTip('tt4')">core_start_parallel</a> and <core_end_parallel> in <a href="core_portme-c.html#core_portme.c" class=LFile >core_portme.c</a>, to fit a particular architecture.</p></div></div></div>
+
+<div class="CConfiguration"><div class=CTopic><h3 class=CTitle><a name="USE_PTHREAD"></a>USE_PTHREAD</h3><div class=CBody><p>Sample implementation for launching parallel contexts This implementation uses pthread_thread_create and pthread_join.</p><h4 class=CHeading>Valid values</h4><table border=0 cellspacing=0 cellpadding=0 class=CDescriptionList><tr><td class=CDLEntry>0</td><td class=CDLDescription>Do not use pthreads API.</td></tr><tr><td class=CDLEntry>1</td><td class=CDLDescription>Use pthreads API</td></tr></table><h4 class=CHeading>Note</h4><p>This flag only matters if MULTITHREAD has been defined to a value greater then 1.</p></div></div></div>
+
+<div class="CConfiguration"><div class=CTopic><h3 class=CTitle><a name="USE_FORK"></a>USE_FORK</h3><div class=CBody><p>Sample implementation for launching parallel contexts This implementation uses fork, waitpid, shmget,shmat and shmdt.</p><h4 class=CHeading>Valid values</h4><table border=0 cellspacing=0 cellpadding=0 class=CDescriptionList><tr><td class=CDLEntry>0</td><td class=CDLDescription>Do not use fork API.</td></tr><tr><td class=CDLEntry>1</td><td class=CDLDescription>Use fork API</td></tr></table><h4 class=CHeading>Note</h4><p>This flag only matters if MULTITHREAD has been defined to a value greater then 1.</p></div></div></div>
+
+<div class="CConfiguration"><div class=CTopic><h3 class=CTitle><a name="USE_SOCKET"></a>USE_SOCKET</h3><div class=CBody><p>Sample implementation for launching parallel contexts This implementation uses fork, socket, sendto and recvfrom</p><h4 class=CHeading>Valid values</h4><table border=0 cellspacing=0 cellpadding=0 class=CDescriptionList><tr><td class=CDLEntry>0</td><td class=CDLDescription>Do not use fork and sockets API.</td></tr><tr><td class=CDLEntry>1</td><td class=CDLDescription>Use fork and sockets API</td></tr></table><h4 class=CHeading>Note</h4><p>This flag only matters if MULTITHREAD has been defined to a value greater then 1.</p></div></div></div>
+
+<div class="CConfiguration"><div class=CTopic><h3 class=CTitle><a name="MAIN_HAS_NOARGC"></a>MAIN_HAS_NOARGC</h3><div class=CBody><p>Needed if platform does not support getting arguments to main.</p><h4 class=CHeading>Valid values</h4><table border=0 cellspacing=0 cellpadding=0 class=CDescriptionList><tr><td class=CDLEntry>0</td><td class=CDLDescription>argc/argv to main is supported</td></tr><tr><td class=CDLEntry>1</td><td class=CDLDescription>argc/argv to main is not supported</td></tr></table></div></div></div>
+
+<div class="CConfiguration"><div class=CTopic><h3 class=CTitle><a name="MAIN_HAS_NORETURN"></a>MAIN_HAS_NORETURN</h3><div class=CBody><p>Needed if platform does not support returning a value from main.</p><h4 class=CHeading>Valid values</h4><table border=0 cellspacing=0 cellpadding=0 class=CDescriptionList><tr><td class=CDLEntry>0</td><td class=CDLDescription>main returns an int, and return value will be 0.</td></tr><tr><td class=CDLEntry>1</td><td class=CDLDescription>platform does not support returning a value from main</td></tr></table></div></div></div>
+
+<div class="CGroup"><div class=CTopic><h3 class=CTitle><a name="Variables"></a>Variables</h3></div></div>
+
+<div class="CVariable"><div class=CTopic><h3 class=CTitle><a name="default_num_contexts"></a>default_num_contexts</h3><div class=CBody><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td>extern ee_u32 default_num_contexts</td></tr></table></blockquote><p>Number of contexts to spawn in multicore context. Override this global value to change number of contexts used.</p><h4 class=CHeading>Note</h4><p>This value may not be set higher then the <a href="#MULTITHREAD" class=LConfiguration id=link5 onMouseOver="ShowTip(event, 'tt5', 'link5')" onMouseOut="HideTip('tt5')">MULTITHREAD</a> define.</p><p>To experiment, you can set the <a href="#MULTITHREAD" class=LConfiguration id=link6 onMouseOver="ShowTip(event, 'tt5', 'link6')" onMouseOut="HideTip('tt5')">MULTITHREAD</a> define to the highest value expected, and use argc/argv in the <a href="core_portme-c.html#portable_init" class=LFunction id=link7 onMouseOver="ShowTip(event, 'tt6', 'link7')" onMouseOut="HideTip('tt6')">portable_init</a> to set this value from the command line.</p></div></div></div>
+
+</div><!--Content-->
+
+
+<div id=Footer><a href="http://www.naturaldocs.org">Copyright 2009 EEMBC</a></div><!--Footer-->
+
+
+<div id=Menu><div class=MTitle>CoreMark<div class=MSubTitle>(c) EEMBC</div></div><div class=MEntry><div class=MFile><a href="../readme-txt.html">CoreMark</a></div></div><div class=MEntry><div class=MFile><a href="../release_notes-txt.html">Release Notes</a></div></div><div class=MEntry><div class=MGroup><a href="javascript:ToggleMenu('MGroupContent2')">Source</a><div class=MGroupContent id=MGroupContent2><div class=MEntry><div class=MFile><a href="../core_list_join-c.html">core_list_join.c</a></div></div><div class=MEntry><div class=MFile><a href="../core_main-c.html">core_main.c</a></div></div><div class=MEntry><div class=MFile><a href="../core_matrix-c.html">core_matrix.c</a></div></div><div class=MEntry><div class=MFile><a href="../PIC32/core_portme-mak.html">core_portme.mak</a></div></div><div class=MEntry><div class=MFile><a href="../core_state-c.html">core_state.c</a></div></div><div class=MEntry><div class=MFile><a href="../core_util-c.html">core_util.c</a></div></div><div class=MEntry><div class=MFile><a href="../coremark-h.html">coremark.h</a></div></div><div class=MEntry><div class=MGroup><a href="javascript:ToggleMenu('MGroupContent1')">Porting</a><div class=MGroupContent id=MGroupContent1><div class=MEntry><div class=MFile><a href="core_portme-c.html">PORT_DIR/<span class=HB> </span>core_portme.c</a></div></div><div class=MEntry><div class=MFile id=MSelected>PORT_DIR/<span class=HB> </span>core_portme.h</div></div><div class=MEntry><div class=MFile><a href="core_portme-mak.html">PORT_DIR/<span class=HB> </span>core_portme.mak</a></div></div></div></div></div></div></div></div><div class=MEntry><div class=MGroup><a href="javascript:ToggleMenu('MGroupContent3')">Index</a><div class=MGroupContent id=MGroupContent3><div class=MEntry><div class=MIndex><a href="../../index/General.html">Everything</a></div></div><div class=MEntry><div class=MIndex><a href="../../index/Files.html">Files</a></div></div><div class=MEntry><div class=MIndex><a href="../../index/Functions.html">Functions</a></div></div><div class=MEntry><div class=MIndex><a href="../../index/Types.html">Types</a></div></div><div class=MEntry><div class=MIndex><a href="../../index/Configuration.html">Configurations</a></div></div><div class=MEntry><div class=MIndex><a href="../../index/Variables.html">Variables</a></div></div><div class=MEntry><div class=MIndex><a href="../../index/BuildTargets.html">Build Targets</a></div></div></div></div></div><script type="text/javascript"><!--
+var searchPanel = new SearchPanel("searchPanel", "HTML", "../../search");
+--></script><div id=MSearchPanel class=MSearchPanelInactive><input type=text id=MSearchField value=Search onFocus="searchPanel.OnSearchFieldFocus(true)" onBlur="searchPanel.OnSearchFieldFocus(false)" onKeyUp="searchPanel.OnSearchFieldChange()"><select id=MSearchType onFocus="searchPanel.OnSearchTypeFocus(true)" onBlur="searchPanel.OnSearchTypeFocus(false)" onChange="searchPanel.OnSearchTypeChange()"><option id=MSearchEverything selected value="General">Everything</option><option value="BuildTargets">Build Targets</option><option value="Configuration">Configuration</option><option value="Files">Files</option><option value="Functions">Functions</option><option value="Types">Types</option><option value="Variables">Variables</option></select></div></div><!--Menu-->
+
+
+
+<!--START_ND_TOOLTIPS-->
+<div class=CToolTip id="tt1"><div class=CVariable><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td>extern ee_u32 default_num_contexts</td></tr></table></blockquote>Number of contexts to spawn in multicore context. </div></div><div class=CToolTip id="tt2"><div class=CConfiguration>Sample implementation for launching parallel contexts This implementation uses pthread_thread_create and pthread_join.</div></div><div class=CToolTip id="tt3"><div class=CConfiguration>Sample implementation for launching parallel contexts This implementation uses fork, waitpid, shmget,shmat and shmdt.</div></div><div class=CToolTip id="tt4"><div class=CFunction>Start benchmarking in a parallel context.</div></div><div class=CToolTip id="tt5"><div class=CConfiguration>Define for parallel execution</div></div><div class=CToolTip id="tt6"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>void portable_init(</td><td class=PType nowrap>core_portable </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>p,</td></tr><tr><td></td><td class=PType nowrap>int </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>argc,</td></tr><tr><td></td><td class=PType nowrap>char </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>argv[]</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Target specific initialization code Test for some common mistakes.</div></div><!--END_ND_TOOLTIPS-->
+
+
+
+
+<div id=MSearchResultsWindow><iframe src="" frameborder=0 name=MSearchResults id=MSearchResults></iframe><a href="javascript:searchPanel.CloseResultsWindow()" id=MSearchResultsWindowClose>Close</a></div>
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\ No newline at end of file
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/files/linux/core_portme-mak.html b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/files/linux/core_portme-mak.html
new file mode 100644
index 0000000..ffd6cbe
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/files/linux/core_portme-mak.html
@@ -0,0 +1,76 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd">
+
+<html><head><title>core_portme.mak - CoreMark</title><link rel="stylesheet" type="text/css" href="../../styles/main.css"><script language=JavaScript src="../../javascript/main.js"></script><script language=JavaScript src="../../javascript/searchdata.js"></script></head><body class="ContentPage" onLoad="NDOnLoad()"><script language=JavaScript><!--
+if (browserType) {document.write("<div class=" + browserType + ">");if (browserVer) {document.write("<div class=" + browserVer + ">"); }}// --></script>
+
+<!-- Copyright 2009 EEMBC -->
+<!-- saved from url=(0026)http://www.naturaldocs.org -->
+
+
+
+
+<div id=Content><div class="CFile"><div class=CTopic id=MainTopic><h1 class=CTitle><a name="core_portme.mak"></a>core_portme.mak</h1><div class=CBody><!--START_ND_SUMMARY--><div class=Summary><div class=STitle>Summary</div><div class=SBorder><table border=0 cellspacing=0 cellpadding=0 class=STable><tr class="SMain"><td class=SEntry><a href="#core_portme.mak" >core_portme.mak</a></td><td class=SDescription></td></tr><tr class="SGroup"><td class=SEntry><a href="#Variables" >Variables</a></td><td class=SDescription></td></tr><tr class="SVariable SIndent1 SMarked"><td class=SEntry><a href="#OUTFLAG" >OUTFLAG</a></td><td class=SDescription>Use this flag to define how to to get an executable (e.g -o)</td></tr><tr class="SVariable SIndent1"><td class=SEntry><a href="#CC" >CC</a></td><td class=SDescription>Use this flag to define compiler to use</td></tr><tr class="SVariable SIndent1 SMarked"><td class=SEntry><a href="#CFLAGS" >CFLAGS</a></td><td class=SDescription>Use this flag to define compiler options. </td></tr><tr class="SVariable SIndent1"><td class=SEntry><a href="#LFLAGS_END" >LFLAGS_END</a></td><td class=SDescription>Define any libraries needed for linking or other flags that should come at the end of the link line (e.g. </td></tr><tr class="SVariable SIndent1 SMarked"><td class=SEntry><a href="#PORT_SRCS" >PORT_SRCS</a></td><td class=SDescription>Port specific source files can be added here</td></tr><tr class="SVariable SIndent1"><td class=SEntry><a href="#LOAD" >LOAD</a></td><td class=SDescription>Define this flag if you need to load to a target, as in a cross compile environment.</td></tr><tr class="SVariable SIndent1 SMarked"><td class=SEntry><a href="#RUN" >RUN</a></td><td class=SDescription>Define this flag if running does not consist of simple invocation of the binary. </td></tr><tr class="SVariable SIndent1"><td class=SEntry><a href="#SEPARATE_COMPILE" >SEPARATE_COMPILE</a></td><td class=SDescription>Define if you need to separate compilation from link stage. </td></tr><tr class="SVariable SIndent1 SMarked"><td class=SEntry><a href="#PORT_OBJS" >PORT_OBJS</a></td><td class=SDescription>Port specific object files can be added here</td></tr><tr class="SGroup"><td class=SEntry><a href="#Build_Targets" >Build Targets</a></td><td class=SDescription></td></tr><tr class="SBuildTarget SIndent1 SMarked"><td class=SEntry><a href="#port_prebuild" >port_prebuild</a></td><td class=SDescription>Generate any files that are needed before actual build starts. </td></tr><tr class="SBuildTarget SIndent1"><td class=SEntry><a href="#port_postbuild" >port_postbuild</a></td><td class=SDescription>Generate any files that are needed after actual build end. </td></tr><tr class="SBuildTarget SIndent1 SMarked"><td class=SEntry><a href="#port_postrun" >port_postrun</a></td><td class=SDescription>Do platform specific after run stuff. </td></tr><tr class="SBuildTarget SIndent1"><td class=SEntry><a href="#port_prerun" >port_prerun</a></td><td class=SDescription>Do platform specific after run stuff. </td></tr><tr class="SBuildTarget SIndent1 SMarked"><td class=SEntry><a href="#port_postload" >port_postload</a></td><td class=SDescription>Do platform specific after load stuff. </td></tr><tr class="SBuildTarget SIndent1"><td class=SEntry><a href="#port_preload" >port_preload</a></td><td class=SDescription>Do platform specific before load stuff. </td></tr><tr class="SGroup"><td class=SEntry><a href="#Variables" >Variables</a></td><td class=SDescription></td></tr><tr class="SVariable SIndent1 SMarked"><td class=SEntry><a href="#OPATH" >OPATH</a></td><td class=SDescription></td></tr><tr class="SVariable SIndent1"><td class=SEntry><a href="#PERL" >PERL</a></td><td class=SDescription>Define perl executable to calculate the geomean if running separate.</td></tr></table></div></div><!--END_ND_SUMMARY--></div></div></div>
+
+<div class="CGroup"><div class=CTopic><h3 class=CTitle><a name="Variables"></a>Variables</h3></div></div>
+
+<div class="CVariable"><div class=CTopic><h3 class=CTitle><a name="OUTFLAG"></a>OUTFLAG</h3><div class=CBody><p>Use this flag to define how to to get an executable (e.g -o)</p></div></div></div>
+
+<div class="CVariable"><div class=CTopic><h3 class=CTitle><a name="CC"></a>CC</h3><div class=CBody><p>Use this flag to define compiler to use</p></div></div></div>
+
+<div class="CVariable"><div class=CTopic><h3 class=CTitle><a name="CFLAGS"></a>CFLAGS</h3><div class=CBody><p>Use this flag to define compiler options. Note, you can add compiler options from the command line using XCFLAGS=”other flags”</p></div></div></div>
+
+<div class="CVariable"><div class=CTopic><h3 class=CTitle><a name="LFLAGS_END"></a>LFLAGS_END</h3><div class=CBody><p>Define any libraries needed for linking or other flags that should come at the end of the link line (e.g. linker scripts). Note: On certain platforms, the default clock_gettime implementation is supported but requires linking of librt.</p></div></div></div>
+
+<div class="CVariable"><div class=CTopic><h3 class=CTitle><a name="PORT_SRCS"></a>PORT_SRCS</h3><div class=CBody><p>Port specific source files can be added here</p></div></div></div>
+
+<div class="CVariable"><div class=CTopic><h3 class=CTitle><a name="LOAD"></a>LOAD</h3><div class=CBody><p>Define this flag if you need to load to a target, as in a cross compile environment.</p></div></div></div>
+
+<div class="CVariable"><div class=CTopic><h3 class=CTitle><a name="RUN"></a>RUN</h3><div class=CBody><p>Define this flag if running does not consist of simple invocation of the binary. In a cross compile environment, you need to define this.</p></div></div></div>
+
+<div class="CVariable"><div class=CTopic><h3 class=CTitle><a name="SEPARATE_COMPILE"></a>SEPARATE_COMPILE</h3><div class=CBody><p>Define if you need to separate compilation from link stage. In this case, you also need to define below how to create an object file, and how to link.</p></div></div></div>
+
+<div class="CVariable"><div class=CTopic><h3 class=CTitle><a name="PORT_OBJS"></a>PORT_OBJS</h3><div class=CBody><p>Port specific object files can be added here</p></div></div></div>
+
+<div class="CGroup"><div class=CTopic><h3 class=CTitle><a name="Build_Targets"></a>Build Targets</h3></div></div>
+
+<div class="CBuildTarget"><div class=CTopic><h3 class=CTitle><a name="port_prebuild"></a>port_prebuild</h3><div class=CBody><p>Generate any files that are needed before actual build starts. E.g. generate profile guidance files. Sample PGO generation for gcc enabled with PGO=1</p><ul><li>First, check if PGO was defined on the command line, if so, need to add -fprofile-use to compile line.</li><li>Second, if PGO reference has not yet been generated, add a step to the prebuild that will build a profile-generate version and run it.</li></ul><table border=0 cellspacing=0 cellpadding=0 class=CDescriptionList><tr><td class=CDLEntry>Note</td><td class=CDLDescription>Using REBUILD=1</td></tr></table><p>Use make PGO=1 to invoke this sample processing.</p></div></div></div>
+
+<div class="CBuildTarget"><div class=CTopic><h3 class=CTitle><a name="port_postbuild"></a>port_postbuild</h3><div class=CBody><p>Generate any files that are needed after actual build end. E.g. change format to srec, bin, zip in order to be able to load into flash</p></div></div></div>
+
+<div class="CBuildTarget"><div class=CTopic><h3 class=CTitle><a name="port_postrun"></a>port_postrun</h3><div class=CBody><p>Do platform specific after run stuff. E.g. reset the board, backup the logfiles etc.</p></div></div></div>
+
+<div class="CBuildTarget"><div class=CTopic><h3 class=CTitle><a name="port_prerun"></a>port_prerun</h3><div class=CBody><p>Do platform specific after run stuff. E.g. reset the board, backup the logfiles etc.</p></div></div></div>
+
+<div class="CBuildTarget"><div class=CTopic><h3 class=CTitle><a name="port_postload"></a>port_postload</h3><div class=CBody><p>Do platform specific after load stuff. E.g. reset the reset power to the flash eraser</p></div></div></div>
+
+<div class="CBuildTarget"><div class=CTopic><h3 class=CTitle><a name="port_preload"></a>port_preload</h3><div class=CBody><p>Do platform specific before load stuff. E.g. reset the reset power to the flash eraser</p></div></div></div>
+
+<div class="CGroup"><div class=CTopic><h3 class=CTitle><a name="Variables"></a>Variables</h3></div></div>
+
+<div class="CVariable"><div class=CTopic><h3 class=CTitle><a name="OPATH"></a>OPATH</h3><div class=CBody><table border=0 cellspacing=0 cellpadding=0 class=CDescriptionList><tr><td class=CDLEntry>Path to the output folder. Default</td><td class=CDLDescription>current folder.</td></tr></table></div></div></div>
+
+<div class="CVariable"><div class=CTopic><h3 class=CTitle><a name="PERL"></a>PERL</h3><div class=CBody><p>Define perl executable to calculate the geomean if running separate.</p></div></div></div>
+
+</div><!--Content-->
+
+
+<div id=Footer><a href="http://www.naturaldocs.org">Copyright 2009 EEMBC</a></div><!--Footer-->
+
+
+<div id=Menu><div class=MTitle>CoreMark<div class=MSubTitle>(c) EEMBC</div></div><div class=MEntry><div class=MFile><a href="../readme-txt.html">CoreMark</a></div></div><div class=MEntry><div class=MFile><a href="../release_notes-txt.html">Release Notes</a></div></div><div class=MEntry><div class=MGroup><a href="javascript:ToggleMenu('MGroupContent2')">Source</a><div class=MGroupContent id=MGroupContent2><div class=MEntry><div class=MFile><a href="../core_list_join-c.html">core_list_join.c</a></div></div><div class=MEntry><div class=MFile><a href="../core_main-c.html">core_main.c</a></div></div><div class=MEntry><div class=MFile><a href="../core_matrix-c.html">core_matrix.c</a></div></div><div class=MEntry><div class=MFile><a href="../PIC32/core_portme-mak.html">core_portme.mak</a></div></div><div class=MEntry><div class=MFile><a href="../core_state-c.html">core_state.c</a></div></div><div class=MEntry><div class=MFile><a href="../core_util-c.html">core_util.c</a></div></div><div class=MEntry><div class=MFile><a href="../coremark-h.html">coremark.h</a></div></div><div class=MEntry><div class=MGroup><a href="javascript:ToggleMenu('MGroupContent1')">Porting</a><div class=MGroupContent id=MGroupContent1><div class=MEntry><div class=MFile><a href="core_portme-c.html">PORT_DIR/<span class=HB> </span>core_portme.c</a></div></div><div class=MEntry><div class=MFile><a href="core_portme-h.html">PORT_DIR/<span class=HB> </span>core_portme.h</a></div></div><div class=MEntry><div class=MFile id=MSelected>PORT_DIR/<span class=HB> </span>core_portme.mak</div></div></div></div></div></div></div></div><div class=MEntry><div class=MGroup><a href="javascript:ToggleMenu('MGroupContent3')">Index</a><div class=MGroupContent id=MGroupContent3><div class=MEntry><div class=MIndex><a href="../../index/General.html">Everything</a></div></div><div class=MEntry><div class=MIndex><a href="../../index/Files.html">Files</a></div></div><div class=MEntry><div class=MIndex><a href="../../index/Functions.html">Functions</a></div></div><div class=MEntry><div class=MIndex><a href="../../index/Types.html">Types</a></div></div><div class=MEntry><div class=MIndex><a href="../../index/Configuration.html">Configurations</a></div></div><div class=MEntry><div class=MIndex><a href="../../index/Variables.html">Variables</a></div></div><div class=MEntry><div class=MIndex><a href="../../index/BuildTargets.html">Build Targets</a></div></div></div></div></div><script type="text/javascript"><!--
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+<!--START_ND_TOOLTIPS-->
+<!--END_ND_TOOLTIPS-->
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+if (browserType) {if (browserVer) {document.write("</div>"); }document.write("</div>");}// --></script></body></html>
\ No newline at end of file
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/files/readme-txt.html b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/files/readme-txt.html
new file mode 100644
index 0000000..2b57f37
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/files/readme-txt.html
@@ -0,0 +1,71 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd">
+
+<html><head><title>CoreMark</title><link rel="stylesheet" type="text/css" href="../styles/main.css"><script language=JavaScript src="../javascript/main.js"></script><script language=JavaScript src="../javascript/searchdata.js"></script></head><body class="ContentPage" onLoad="NDOnLoad()"><script language=JavaScript><!--
+if (browserType) {document.write("<div class=" + browserType + ">");if (browserVer) {document.write("<div class=" + browserVer + ">"); }}// --></script>
+
+<!-- Copyright 2009 EEMBC -->
+<!-- saved from url=(0026)http://www.naturaldocs.org -->
+
+
+
+
+<div id=Content><div class="CFile"><div class=CTopic id=MainTopic><h1 class=CTitle><a name="CoreMark"></a>CoreMark</h1><div class=CBody><!--START_ND_SUMMARY--><div class=Summary><div class=STitle>Summary</div><div class=SBorder><table border=0 cellspacing=0 cellpadding=0 class=STable><tr class="SMain"><td class=SEntry><a href="#CoreMark" >CoreMark</a></td><td class=SDescription></td></tr><tr class="SGeneric SMarked"><td class=SEntry><a href="#Welcome" >Welcome</a></td><td class=SDescription>Copyright © 2009 EEMBC All rights reserved. </td></tr><tr class="SGeneric"><td class=SEntry><a href="#Building_and_running" >Building and running</a></td><td class=SDescription>Download the release files from the www.coremark.org. </td></tr><tr class="SGeneric SMarked"><td class=SEntry><a href="#Documentation" >Documentation</a></td><td class=SDescription>When you unpack the documentation (tar -vzxf coremark_<version>_docs.tgz) a docs folder will be created. </td></tr><tr class="SGeneric"><td class=SEntry><a href="#Submitting_results" >Submitting results</a></td><td class=SDescription>CoreMark results can be submitted on the web.</td></tr><tr class="SGeneric SMarked"><td class=SEntry><a href="#Run_rules" >Run rules</a></td><td class=SDescription>What is and is not allowed.</td></tr><tr class="SGeneric"><td class=SEntry><a href="#Reporting_rules" >Reporting rules</a></td><td class=SDescription>How to report results on a data sheet?</td></tr><tr class="SGeneric SMarked"><td class=SEntry><a href="#Log_File_Format" >Log File Format</a></td><td class=SDescription>The log files have the following format</td></tr><tr class="SGeneric"><td class=SEntry><a href="#Legal" >Legal</a></td><td class=SDescription>See LICENSE.txt or the word document file under docs/LICENSE.doc. </td></tr><tr class="SGeneric SMarked"><td class=SEntry><a href="#Credits" >Credits</a></td><td class=SDescription>Many thanks to all of the individuals who helped with the development or testing of CoreMark including (Sorted by company name)</td></tr></table></div></div><!--END_ND_SUMMARY--></div></div></div>
+
+<div class="CGeneric"><div class=CTopic><h3 class=CTitle><a name="Welcome"></a>Welcome</h3><div class=CBody><p>Copyright © 2009 EEMBC All rights reserved. CoreMark is a trademark of EEMBC and EEMBC is a registered trademark of the Embedded Microprocessor Benchmark Consortium.</p><p>CoreMark’s primary goals are simplicity and providing a method for testing only a processor’s core features.</p><p>For more information about EEMBC’s comprehensive embedded benchmark suites, please see www.eembc.org.</p></div></div></div>
+
+<div class="CGeneric"><div class=CTopic><h3 class=CTitle><a name="Building_and_running"></a>Building and running</h3><div class=CBody><p>Download the release files from the www.coremark.org. You can verify the download using the coremark_<version>.md5 file</p><blockquote><pre>md5sum -c coremark_<version>.md5</pre></blockquote><p>Unpack the distribution (tar -vzxf coremark_<version>.tgz && tar -vzxf coremark_<version>_docs.tgz) then change to the coremark_<version> folder.</p><p>To build and run the benchmark, type</p><blockquote><pre>make</pre></blockquote><p>Full results are available in the files run1.log and run2.log. CoreMark result can be found in run1.log.</p><p>For self hosted Linux or Cygwin platforms, a simple make should work.</p><h4 class=CHeading>Cross Compile</h4><p>For cross compile platforms please adjust <a href="linux/core_portme-mak.html#core_portme.mak" class=LFile >core_portme.mak</a>, <a href="linux/core_portme-h.html#core_portme.h" class=LFile >core_portme.h</a> (and possibly <a href="linux/core_portme-c.html#core_portme.c" class=LFile >core_portme.c</a>) according to the specific platform used. When porting to a new platform, it is recommended to copy one of the default port folders (e.g. mkdir <platform> && cp linux/* <platform>), adjust the porting files, and run</p><blockquote><pre>make PORT_DIR=<platform></pre></blockquote><h4 class=CHeading>Systems without make</h4><p>The following files need to be compiled:</p><ul><li><a href="core_list_join-c.html#core_list_join.c" class=LFile >core_list_join.c</a></li><li><a href="core_main-c.html#core_main.c" class=LFile id=link1 onMouseOver="ShowTip(event, 'tt1', 'link1')" onMouseOut="HideTip('tt1')">core_main.c</a></li><li><a href="core_matrix-c.html#core_matrix.c" class=LFile >core_matrix.c</a></li><li><a href="core_state-c.html#core_state.c" class=LFile >core_state.c</a></li><li><a href="core_util-c.html#core_util.c" class=LFile >core_util.c</a></li><li><PORT_DIR>/<a href="linux/core_portme-c.html#core_portme.c" class=LFile >core_portme.c</a></li></ul><p>For example</p><blockquote><pre>gcc -O2 -o coremark.exe core_list_join.c core_main.c core_matrix.c core_state.c core_util.c simple/core_portme.c -DPERFORMANCE_RUN=1 -DITERATIONS=1000
+./coremark.exe > run1.log</pre></blockquote><p>The above will compile the benchmark for a performance run and 1000 iterations. Output is redirected to run1.log.</p><h4 class=CHeading>Make targets</h4><table border=0 cellspacing=0 cellpadding=0 class=CDescriptionList><tr><td class=CDLEntry>run</td><td class=CDLDescription>Default target, creates run1.log and run2.log.</td></tr><tr><td class=CDLEntry>run1.log</td><td class=CDLDescription>Run the benchmark with performance parameters, and output to run1.log</td></tr><tr><td class=CDLEntry>run2.log</td><td class=CDLDescription>Run the benchmark with validation parameters, and output to run2.log</td></tr><tr><td class=CDLEntry>run3.log</td><td class=CDLDescription>Run the benchmark with profile generation parameters, and output to run3.log</td></tr><tr><td class=CDLEntry>compile</td><td class=CDLDescription>compile the benchmark executable</td></tr><tr><td class=CDLEntry>link</td><td class=CDLDescription>link the benchmark executable</td></tr><tr><td class=CDLEntry>check</td><td class=CDLDescription>test MD5 of sources that may not be modified</td></tr><tr><td class=CDLEntry>clean</td><td class=CDLDescription>clean temporary files</td></tr></table><h4 class=CHeading>ITERATIONS</h4><p>By default, the benchmark will run between 10-100 seconds. To override, use ITERATIONS=N</p><blockquote><pre>make ITERATIONS=10</pre></blockquote><p>Will run the benchmark for 10 iterations. It is recommended to set a specific number of iterations in certain situations e.g.:</p><ul><li>Running with a simulator</li><li>Measuring power/energy</li><li>Timing cannot be restarted</li></ul><h4 class=CHeading>Minimum required run time</h4><p>Results are only valid for reporting if the benchmark ran for at least 10 secs!</p><h4 class=CHeading>XCFLAGS</h4><p>To add compiler flags from the command line, use XCFLAGS e.g.</p><blockquote><pre>make XCFLAGS="-g -DMULTITHREAD=4 -DUSE_FORK=1"</pre></blockquote><ul><li>CORE_DEBUG</li></ul><p>Define to compile for a debug run if you get incorrect CRC.</p><blockquote><pre>make XCFLAGS="-DCORE_DEBUG=1"</pre></blockquote><ul><li>Parallel Execution</li></ul><p>Use XCFLAGS=-DMULTITHREAD=N where N is number of threads to run in parallel. Several implementations are available to execute in multiple contexts, or you can implement your own in <a href="linux/core_portme-c.html#core_portme.c" class=LFile >core_portme.c</a>.</p><blockquote><pre>make XCFLAGS="-DMULTITHREAD=4 -DUSE_PTHREAD"</pre></blockquote><p>Above will compile the benchmark for execution on 4 cores, using POSIX Threads API.</p><h4 class=CHeading>REBUILD</h4><p>To force rebuild, add the flag REBUILD to the command line</p><blockquote><pre>make REBUILD=1</pre></blockquote><p>Check core_portme.mak for more important options.</p><h4 class=CHeading>Run parameters for the benchmark executable</h4><p>Coremark executable takes several parameters as follows (if main accepts arguments). 1st - A seed value used for initialization of data. 2nd - A seed value used for initialization of data. 3rd - A seed value used for initialization of data. 4th - Number of iterations (0 for auto : default value) 5th - Reserved for internal use. 6th - Reserved for internal use. 7th - For malloc users only, ovreride the size of the input data buffer.</p><p>The run target from make will run coremark with 2 different data initialization seeds.</p><h4 class=CHeading>Alternative parameters</h4><p>If not using malloc or command line arguments are not supported, the buffer size for the algorithms must be defined via the compiler define TOTAL_DATA_SIZE. TOTAL_DATA_SIZE must be set to 2000 bytes (default) for standard runs. The default for such a target when testing different configurations could be ...</p><blockquote><pre>make XCFLAGS="-DTOTAL_DATA_SIZE=6000 -DMAIN_HAS_NOARGC=1"</pre></blockquote></div></div></div>
+
+<div class="CGeneric"><div class=CTopic><h3 class=CTitle><a name="Documentation"></a>Documentation</h3><div class=CBody><p>When you unpack the documentation (tar -vzxf coremark_<version>_docs.tgz) a docs folder will be created. Check the file docs/html/index.html and the website <a href="http://www.coremark.org" class=LURL target=_top>http://www.coremark.org</a> for more info.</p></div></div></div>
+
+<div class="CGeneric"><div class=CTopic><h3 class=CTitle><a name="Submitting_results"></a>Submitting results</h3><div class=CBody><p>CoreMark results can be submitted on the web.</p><p>Open a web browser and go to <a href="http://www.coremark.org/benchmark/index.php?pg=benchmark" class=LURL target=_top>http://www.coremark.org<span class=HB>- </span>/benchmark<span class=HB>- </span>/index.php?pg=benchmark</a> Select the link to add a new score and follow the instructions.</p></div></div></div>
+
+<div class="CGeneric"><div class=CTopic><h3 class=CTitle><a name="Run_rules"></a>Run rules</h3><div class=CBody><p>What is and is not allowed.</p><h4 class=CHeading>Required</h4><table border=0 cellspacing=0 cellpadding=0 class=CDescriptionList><tr><td class=CDLEntry>1</td><td class=CDLDescription>The benchmark needs to run for at least 10 seconds.</td></tr><tr><td class=CDLEntry>2</td><td class=CDLDescription>All validation must succeed for seeds 0,0,0x66 and 0x3415,0x3415,0x66, buffer size of 2000 bytes total.</td></tr></table><ul><li>If not using command line arguments to main:</li></ul><blockquote><pre>make XCFLAGS="-DPERFORMANCE_RUN=1" REBUILD=1 run1.log
+make XCFLAGS="-DVALIDATION_RUN=1" REBUILD=1 run2.log</pre></blockquote><table border=0 cellspacing=0 cellpadding=0 class=CDescriptionList><tr><td class=CDLEntry>3</td><td class=CDLDescription>If using profile guided optimization, profile must be generated using seeds of 8,8,8, and buffer size of 1200 bytes total.</td></tr></table><blockquote><pre>make XCFLAGS="-DTOTAL_DATA_SIZE=1200 -DPROFILE_RUN=1" REBUILD=1 run3.log</pre></blockquote><table border=0 cellspacing=0 cellpadding=0 class=CDescriptionList><tr><td class=CDLEntry>4</td><td class=CDLDescription>All source files must be compiled with the same flags.</td></tr><tr><td class=CDLEntry>5</td><td class=CDLDescription>All data type sizes must match size in bits such that:</td></tr></table><ul><li>ee_u8 is an 8 bits datatype.</li><li>ee_s16 is an 16 bits datatype.</li><li>ee_u16 is an 16 bits datatype.</li><li>ee_s32 is an 32 bits datatype.</li><li>ee_u32 is an 32 bits datatype.</li></ul><h4 class=CHeading>Allowed</h4><ul><li>Changing number of iterations</li><li>Changing toolchain and build/load/run options</li><li>Changing method of acquiring a data memory block</li><li>Changing the method of acquiring seed values</li><li>Changing implementation in core_portme.c</li><li>Changing configuration values in core_portme.h</li><li>Changing core_portme.mak</li></ul><h4 class=CHeading>Not allowed</h4><ul><li>Changing of source file other then core_portme* (use make check to validate)</li></ul></div></div></div>
+
+<div class="CGeneric"><div class=CTopic><h3 class=CTitle><a name="Reporting_rules"></a>Reporting rules</h3><div class=CBody><p>How to report results on a data sheet?</p><p>CoreMark 1.0 : N / C [/ P] [/ M]</p><table border=0 cellspacing=0 cellpadding=0 class=CDescriptionList><tr><td class=CDLEntry>N</td><td class=CDLDescription>Number of iterations per second with seeds 0,0,0x66,size=2000)</td></tr><tr><td class=CDLEntry>C</td><td class=CDLDescription>Compiler version and flags</td></tr><tr><td class=CDLEntry>P</td><td class=CDLDescription>Parameters such as data and code allocation specifics</td></tr></table><ul><li>This parameter <b>may</b> be omitted if all data was allocated on the heap in RAM.</li><li>This parameter <b>may not</b> be omitted when reporting CoreMark/MHz</li></ul><table border=0 cellspacing=0 cellpadding=0 class=CDescriptionList><tr><td class=CDLEntry>M</td><td class=CDLDescription>Type of parallel execution (if used) and number of contexts This parameter may be omitted if parallel execution was not used.</td></tr></table><p>e.g.</p><blockquote><pre>CoreMark 1.0 : 128 / GCC 4.1.2 -O2 -fprofile-use / Heap in TCRAM / FORK:2</pre></blockquote><p>or</p><blockquote><pre>CoreMark 1.0 : 1400 / GCC 3.4 -O4</pre></blockquote><h4 class=CHeading>If reporting scaling results, the results must be reported as follows</h4><p>CoreMark/MHz 1.0 : N / C / P [/ M]</p><table border=0 cellspacing=0 cellpadding=0 class=CDescriptionList><tr><td class=CDLEntry>P</td><td class=CDLDescription>When reporting scaling results, memory parameter must also indicate memory frequency:core frequency ratio.</td></tr></table><ul><li>If the core has cache and cache frequency to core frequency ratio is configurable, that must also be included.</li></ul><p>e.g.</p><blockquote><pre>CoreMark/MHz 1.0 : 1.47 / GCC 4.1.2 -O2 / DDR3(Heap) 30:1 Memory 1:1 Cache</pre></blockquote></div></div></div>
+
+<div class="CGeneric"><div class=CTopic><h3 class=CTitle><a name="Log_File_Format"></a>Log File Format</h3><div class=CBody><p>The log files have the following format</p><blockquote><pre>2K performance run parameters for coremark. (Run type)
+CoreMark Size : 666 (Buffer size)
+Total ticks : 25875 (platform dependent value)
+Total time (secs) : 25.875000 (actual time in seconds)
+Iterations/Sec : 3864.734300 (Performance value to report)
+Iterations : 100000 (number of iterations used)
+Compiler version : GCC3.4.4 (Compiler and version)
+Compiler flags : -O2 (Compiler and linker flags)
+Memory location : Code in flash, data in on chip RAM
+seedcrc : 0xe9f5 (identifier for the input seeds)
+[0]crclist : 0xe714 (validation for list part)
+[0]crcmatrix : 0x1fd7 (validation for matrix part)
+[0]crcstate : 0x8e3a (validation for state part)
+[0]crcfinal : 0x33ff (iteration dependent output)
+Correct operation validated. See README.md for run and reporting rules. (*Only when run is successful*)
+CoreMark 1.0 : 6508.490622 / GCC3.4.4 -O2 / Heap (*Only on a successful performance run*)</pre></blockquote></div></div></div>
+
+<div class="CGeneric"><div class=CTopic><h3 class=CTitle><a name="Legal"></a>Legal</h3><div class=CBody><p>See LICENSE.txt or the word document file under docs/LICENSE.doc. For more information on your legal rights to use this benchmark, please see <a href="http://www.coremark.org/download/register.php?pg=register" class=LURL target=_top>http://www.coremark.org<span class=HB>- </span>/download<span class=HB>- </span>/register.php?pg=register</a></p></div></div></div>
+
+<div class="CGeneric"><div class=CTopic><h3 class=CTitle><a name="Credits"></a>Credits</h3><div class=CBody><p>Many thanks to all of the individuals who helped with the development or testing of CoreMark including (Sorted by company name)</p><ul><li>Alan Anderson, ADI</li><li>Adhikary Rajiv, ADI</li><li>Elena Stohr, ARM</li><li>Ian Rickards, ARM</li><li>Andrew Pickard, ARM</li><li>Trent Parker, CAVIUM</li><li>Shay Gal-On, EEMBC</li><li>Markus Levy, EEMBC</li><li>Ron Olson, IBM</li><li>Eyal Barzilay, MIPS</li><li>Jens Eltze, NEC</li><li>Hirohiko Ono, NEC</li><li>Ulrich Drees, NEC</li><li>Frank Roscheda, NEC</li><li>Rob Cosaro, NXP</li><li>Shumpei Kawasaki, RENESAS</li></ul></div></div></div>
+
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+<div id=Menu><div class=MTitle>CoreMark<div class=MSubTitle>(c) EEMBC</div></div><div class=MEntry><div class=MFile id=MSelected>CoreMark</div></div><div class=MEntry><div class=MFile><a href="release_notes-txt.html">Release Notes</a></div></div><div class=MEntry><div class=MGroup><a href="javascript:ToggleMenu('MGroupContent2')">Source</a><div class=MGroupContent id=MGroupContent2><div class=MEntry><div class=MFile><a href="core_list_join-c.html">core_list_join.c</a></div></div><div class=MEntry><div class=MFile><a href="core_main-c.html">core_main.c</a></div></div><div class=MEntry><div class=MFile><a href="core_matrix-c.html">core_matrix.c</a></div></div><div class=MEntry><div class=MFile><a href="PIC32/core_portme-mak.html">core_portme.mak</a></div></div><div class=MEntry><div class=MFile><a href="core_state-c.html">core_state.c</a></div></div><div class=MEntry><div class=MFile><a href="core_util-c.html">core_util.c</a></div></div><div class=MEntry><div class=MFile><a href="coremark-h.html">coremark.h</a></div></div><div class=MEntry><div class=MGroup><a href="javascript:ToggleMenu('MGroupContent1')">Porting</a><div class=MGroupContent id=MGroupContent1><div class=MEntry><div class=MFile><a href="linux/core_portme-c.html">PORT_DIR/<span class=HB> </span>core_portme.c</a></div></div><div class=MEntry><div class=MFile><a href="linux/core_portme-h.html">PORT_DIR/<span class=HB> </span>core_portme.h</a></div></div><div class=MEntry><div class=MFile><a href="linux/core_portme-mak.html">PORT_DIR/<span class=HB> </span>core_portme.mak</a></div></div></div></div></div></div></div></div><div class=MEntry><div class=MGroup><a href="javascript:ToggleMenu('MGroupContent3')">Index</a><div class=MGroupContent id=MGroupContent3><div class=MEntry><div class=MIndex><a href="../index/General.html">Everything</a></div></div><div class=MEntry><div class=MIndex><a href="../index/Files.html">Files</a></div></div><div class=MEntry><div class=MIndex><a href="../index/Functions.html">Functions</a></div></div><div class=MEntry><div class=MIndex><a href="../index/Types.html">Types</a></div></div><div class=MEntry><div class=MIndex><a href="../index/Configuration.html">Configurations</a></div></div><div class=MEntry><div class=MIndex><a href="../index/Variables.html">Variables</a></div></div><div class=MEntry><div class=MIndex><a href="../index/BuildTargets.html">Build Targets</a></div></div></div></div></div><script type="text/javascript"><!--
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+<div id=Content><div class="CFile"><div class=CTopic id=MainTopic><h1 class=CTitle><a name="Release_Notes"></a>Release Notes</h1><div class=CBody><p>Version: 1.01</p><h4 class=CHeading>History</h4><p>Version 1.01</p><ul><li>Added validation testing the sizes of datatypes.</li></ul><p>Version 1.00</p><ul><li>First public version.</li></ul><h4 class=CHeading>Validation</h4><p>This release was tested on the following platforms</p><ul><li>x86 cygwin and gcc 3.4 (Quad, dual and single core systems)</li><li>x86 linux (Ubuntu/Fedora) and gcc (4.2/4.1) (Quad and single core systems)</li><li>MIPS64 BE linux and gcc 3.4 16 cores system</li><li>MIPS32 BE linux with CodeSourcery compiler 4.2-177 on Malta/Linux with a 1004K 3-core system</li><li>PPC simulator with gcc 4.2.2 (No OS)</li><li>PPC 64b BE linux (yellowdog) with gcc 3.4 and 4.1 (Dual core system)</li><li>BF533 with VDSP50</li><li>Renesas R8C/H8 MCU with HEW 4.05</li><li>NXP LPC1700 armcc v4.0.0.524</li><li>NEC 78K with IAR v4.61</li><li>ARM simulator with armcc v4</li></ul><h4 class=CHeading>Coverage</h4><p>GCOV results can be found on SVN under cover.</p><h4 class=CHeading>Memory analysis</h4><p>Valgrind 3.4.0 used and no errors reported.</p><h4 class=CHeading>Balance analysis</h4><p>Number of instructions executed for each function tested with cachegrind and found balanced with gcc and -O0.</p><h4 class=CHeading>Statistics</h4><h4 class=CHeading>Lines</h4><blockquote><pre>Lines Blank Cmnts Source AESL
+===== ===== ===== ===== ========== =======================================
+ 469 66 170 251 627.5 core_list_join.c (C)
+ 330 18 54 268 670.0 core_main.c (C)
+ 256 32 80 146 365.0 core_matrix.c (C)
+ 240 16 51 186 465.0 core_state.c (C)
+ 165 11 20 134 335.0 core_util.c (C)
+ 150 23 36 98 245.0 coremark.h (C)
+ 1610 166 411 1083 2707.5 ----- Benchmark ----- (6 files)
+ 293 15 74 212 530.0 linux/core_portme.c (C)
+ 235 30 104 104 260.0 linux/core_portme.h (C)
+ 528 45 178 316 790.0 ----- Porting ----- (2 files)
+
+
+* For comparison, here are the stats for Dhrystone
+Lines Blank Cmnts Source AESL
+===== ===== ===== ===== ========== =======================================
+ 311 15 242 54 135.0 dhry.h (C)
+ 789 132 119 553 1382.5 dhry_1.c (C)
+ 186 26 68 107 267.5 dhry_2.c (C)
+ 1286 173 429 714 1785.0 ----- C ----- (3 files)</pre></blockquote></div></div></div>
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diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/index.html b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/index.html
new file mode 100644
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diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/index/BuildTargets.html b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/index/BuildTargets.html
new file mode 100644
index 0000000..635c0ff
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@@ -0,0 +1,31 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd">
+
+<html><head><title>Build Target Index - CoreMark</title><link rel="stylesheet" type="text/css" href="../styles/main.css"><script language=JavaScript src="../javascript/main.js"></script><script language=JavaScript src="../javascript/searchdata.js"></script></head><body class="IndexPage" onLoad="NDOnLoad()"><script language=JavaScript><!--
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+<!-- saved from url=(0026)http://www.naturaldocs.org -->
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+<div id=Index><div class=IPageTitle>Build Target Index</div><div class=INavigationBar>$#! · 0-9 · A · B · C · D · E · F · G · H · I · J · K · L · M · N · O · <a href="#P">P</a> · Q · R · S · T · U · V · W · X · Y · Z</div><table border=0 cellspacing=0 cellpadding=0><tr><td class=IHeading id=IFirstHeading><a name="P"></a>P</td><td></td></tr><tr><td class=ISymbolPrefix id=IFirstSymbolPrefix> </td><td class=IEntry><span class=ISymbol>port_postbuild</span><div class=ISubIndex><a href="../files/linux/core_portme-mak.html#port_postbuild" id=link1 onMouseOver="ShowTip(event, 'tt1', 'link1')" onMouseOut="HideTip('tt1')" class=IFile>linux/<span class=HB> </span>core_portme.mak</a><a href="../files/PIC32/core_portme-mak.html#port_postbuild" id=link2 onMouseOver="ShowTip(event, 'tt1', 'link2')" onMouseOut="HideTip('tt1')" class=IFile>PIC32/<span class=HB> </span>core_portme.mak</a></div></td></tr><tr><td class=ISymbolPrefix> </td><td class=IEntry><span class=ISymbol>port_postload</span><div class=ISubIndex><a href="../files/linux/core_portme-mak.html#port_postload" id=link3 onMouseOver="ShowTip(event, 'tt2', 'link3')" onMouseOut="HideTip('tt2')" class=IFile>linux/<span class=HB> </span>core_portme.mak</a><a href="../files/PIC32/core_portme-mak.html#port_postload" id=link4 onMouseOver="ShowTip(event, 'tt2', 'link4')" onMouseOut="HideTip('tt2')" class=IFile>PIC32/<span class=HB> </span>core_portme.mak</a></div></td></tr><tr><td class=ISymbolPrefix> </td><td class=IEntry><span class=ISymbol>port_postrun</span><div class=ISubIndex><a href="../files/linux/core_portme-mak.html#port_postrun" id=link5 onMouseOver="ShowTip(event, 'tt3', 'link5')" onMouseOut="HideTip('tt3')" class=IFile>linux/<span class=HB> </span>core_portme.mak</a><a href="../files/PIC32/core_portme-mak.html#port_postrun" id=link6 onMouseOver="ShowTip(event, 'tt3', 'link6')" onMouseOut="HideTip('tt3')" class=IFile>PIC32/<span class=HB> </span>core_portme.mak</a></div></td></tr><tr><td class=ISymbolPrefix> </td><td class=IEntry><span class=ISymbol>port_prebuild</span><div class=ISubIndex><a href="../files/linux/core_portme-mak.html#port_prebuild" id=link7 onMouseOver="ShowTip(event, 'tt4', 'link7')" onMouseOut="HideTip('tt4')" class=IFile>linux/<span class=HB> </span>core_portme.mak</a><a href="../files/PIC32/core_portme-mak.html#port_prebuild" id=link8 onMouseOver="ShowTip(event, 'tt4', 'link8')" onMouseOut="HideTip('tt4')" class=IFile>PIC32/<span class=HB> </span>core_portme.mak</a></div></td></tr><tr><td class=ISymbolPrefix> </td><td class=IEntry><span class=ISymbol>port_preload</span><div class=ISubIndex><a href="../files/linux/core_portme-mak.html#port_preload" id=link9 onMouseOver="ShowTip(event, 'tt5', 'link9')" onMouseOut="HideTip('tt5')" class=IFile>linux/<span class=HB> </span>core_portme.mak</a><a href="../files/PIC32/core_portme-mak.html#port_preload" id=link10 onMouseOver="ShowTip(event, 'tt5', 'link10')" onMouseOut="HideTip('tt5')" class=IFile>PIC32/<span class=HB> </span>core_portme.mak</a></div></td></tr><tr><td class=ISymbolPrefix id=ILastSymbolPrefix> </td><td class=IEntry><span class=ISymbol>port_prerun</span><div class=ISubIndex><a href="../files/linux/core_portme-mak.html#port_prerun" id=link11 onMouseOver="ShowTip(event, 'tt6', 'link11')" onMouseOut="HideTip('tt6')" class=IFile>linux/<span class=HB> </span>core_portme.mak</a><a href="../files/PIC32/core_portme-mak.html#port_prerun" id=link12 onMouseOver="ShowTip(event, 'tt6', 'link12')" onMouseOut="HideTip('tt6')" class=IFile>PIC32/<span class=HB> </span>core_portme.mak</a></div></td></tr></table>
+<!--START_ND_TOOLTIPS-->
+<div class=CToolTip id="tt1"><div class=CBuildTarget>Generate any files that are needed after actual build end. </div></div><div class=CToolTip id="tt2"><div class=CBuildTarget>Do platform specific after load stuff. </div></div><div class=CToolTip id="tt3"><div class=CBuildTarget>Do platform specific after run stuff. </div></div><div class=CToolTip id="tt4"><div class=CBuildTarget>Generate any files that are needed before actual build starts. </div></div><div class=CToolTip id="tt5"><div class=CBuildTarget>Do platform specific before load stuff. </div></div><div class=CToolTip id="tt6"><div class=CBuildTarget>Do platform specific after run stuff. </div></div><!--END_ND_TOOLTIPS-->
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+<div id=Menu><div class=MTitle>CoreMark<div class=MSubTitle>(c) EEMBC</div></div><div class=MEntry><div class=MFile><a href="../files/readme-txt.html">CoreMark</a></div></div><div class=MEntry><div class=MFile><a href="../files/release_notes-txt.html">Release Notes</a></div></div><div class=MEntry><div class=MGroup><a href="javascript:ToggleMenu('MGroupContent2')">Source</a><div class=MGroupContent id=MGroupContent2><div class=MEntry><div class=MFile><a href="../files/core_list_join-c.html">core_list_join.c</a></div></div><div class=MEntry><div class=MFile><a href="../files/core_main-c.html">core_main.c</a></div></div><div class=MEntry><div class=MFile><a href="../files/core_matrix-c.html">core_matrix.c</a></div></div><div class=MEntry><div class=MFile><a href="../files/PIC32/core_portme-mak.html">core_portme.mak</a></div></div><div class=MEntry><div class=MFile><a href="../files/core_state-c.html">core_state.c</a></div></div><div class=MEntry><div class=MFile><a href="../files/core_util-c.html">core_util.c</a></div></div><div class=MEntry><div class=MFile><a href="../files/coremark-h.html">coremark.h</a></div></div><div class=MEntry><div class=MGroup><a href="javascript:ToggleMenu('MGroupContent1')">Porting</a><div class=MGroupContent id=MGroupContent1><div class=MEntry><div class=MFile><a href="../files/linux/core_portme-c.html">PORT_DIR/<span class=HB> </span>core_portme.c</a></div></div><div class=MEntry><div class=MFile><a href="../files/linux/core_portme-h.html">PORT_DIR/<span class=HB> </span>core_portme.h</a></div></div><div class=MEntry><div class=MFile><a href="../files/linux/core_portme-mak.html">PORT_DIR/<span class=HB> </span>core_portme.mak</a></div></div></div></div></div></div></div></div><div class=MEntry><div class=MGroup><a href="javascript:ToggleMenu('MGroupContent3')">Index</a><div class=MGroupContent id=MGroupContent3><div class=MEntry><div class=MIndex><a href="General.html">Everything</a></div></div><div class=MEntry><div class=MIndex><a href="Files.html">Files</a></div></div><div class=MEntry><div class=MIndex><a href="Functions.html">Functions</a></div></div><div class=MEntry><div class=MIndex><a href="Types.html">Types</a></div></div><div class=MEntry><div class=MIndex><a href="Configuration.html">Configurations</a></div></div><div class=MEntry><div class=MIndex><a href="Variables.html">Variables</a></div></div><div class=MEntry><div class=MIndex id=MSelected>Build Targets</div></div></div></div></div><script type="text/javascript"><!--
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diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/index/Configuration.html b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/index/Configuration.html
new file mode 100644
index 0000000..8e5ef3a
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/index/Configuration.html
@@ -0,0 +1,51 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd">
+
+<html><head><title>Configuration Index - CoreMark</title><link rel="stylesheet" type="text/css" href="../styles/main.css"><script language=JavaScript src="../javascript/main.js"></script><script language=JavaScript src="../javascript/searchdata.js"></script></head><body class="IndexPage" onLoad="NDOnLoad()"><script language=JavaScript><!--
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+
+<!-- Copyright 2009 EEMBC -->
+<!-- saved from url=(0026)http://www.naturaldocs.org -->
+
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+
+
+<div id=Index><div class=IPageTitle>Configuration Index</div><div class=INavigationBar>$#! · 0-9 · A · B · <a href="#C">C</a> · D · E · F · G · <a href="#H">H</a> · I · J · K · L · <a href="#M">M</a> · N · O · P · Q · R · <a href="#S">S</a> · <a href="#T">T</a> · <a href="#U">U</a> · V · W · X · Y · Z</div><table border=0 cellspacing=0 cellpadding=0><tr><td class=IHeading id=IFirstHeading><a name="C"></a>C</td><td></td></tr><tr><td class=ISymbolPrefix id=IOnlySymbolPrefix> </td><td class=IEntry><a href="../files/linux/core_portme-h.html#CORE_TICKS" id=link1 onMouseOver="ShowTip(event, 'tt1', 'link1')" onMouseOut="HideTip('tt1')" class=ISymbol>CORE_TICKS</a></td></tr><tr><td class=IHeading><a name="H"></a>H</td><td></td></tr><tr><td class=ISymbolPrefix id=IFirstSymbolPrefix> </td><td class=IEntry><a href="../files/linux/core_portme-h.html#HAS_FLOAT" id=link2 onMouseOver="ShowTip(event, 'tt2', 'link2')" onMouseOut="HideTip('tt2')" class=ISymbol>HAS_FLOAT</a></td></tr><tr><td class=ISymbolPrefix> </td><td class=IEntry><a href="../files/linux/core_portme-h.html#HAS_PRINTF" id=link3 onMouseOver="ShowTip(event, 'tt3', 'link3')" onMouseOut="HideTip('tt3')" class=ISymbol>HAS_PRINTF</a></td></tr><tr><td class=ISymbolPrefix> </td><td class=IEntry><a href="../files/linux/core_portme-h.html#HAS_STDIO" id=link4 onMouseOver="ShowTip(event, 'tt4', 'link4')" onMouseOut="HideTip('tt4')" class=ISymbol>HAS_STDIO</a></td></tr><tr><td class=ISymbolPrefix id=ILastSymbolPrefix> </td><td class=IEntry><a href="../files/linux/core_portme-h.html#HAS_TIME_H" id=link5 onMouseOver="ShowTip(event, 'tt5', 'link5')" onMouseOut="HideTip('tt5')" class=ISymbol>HAS_TIME_H</a></td></tr><tr><td class=IHeading><a name="M"></a>M</td><td></td></tr><tr><td class=ISymbolPrefix id=IFirstSymbolPrefix> </td><td class=IEntry><a href="../files/linux/core_portme-h.html#MAIN_HAS_NOARGC" id=link6 onMouseOver="ShowTip(event, 'tt6', 'link6')" onMouseOut="HideTip('tt6')" class=ISymbol>MAIN_HAS_NOARGC</a></td></tr><tr><td class=ISymbolPrefix> </td><td class=IEntry><a href="../files/linux/core_portme-h.html#MAIN_HAS_NORETURN" id=link7 onMouseOver="ShowTip(event, 'tt7', 'link7')" onMouseOut="HideTip('tt7')" class=ISymbol>MAIN_HAS_NORETURN</a></td></tr><tr><td class=ISymbolPrefix> </td><td class=IEntry><a href="../files/linux/core_portme-h.html#MEM_METHOD" id=link8 onMouseOver="ShowTip(event, 'tt8', 'link8')" onMouseOut="HideTip('tt8')" class=ISymbol>MEM_METHOD</a></td></tr><tr><td class=ISymbolPrefix id=ILastSymbolPrefix> </td><td class=IEntry><a href="../files/linux/core_portme-h.html#MULTITHREAD" id=link9 onMouseOver="ShowTip(event, 'tt9', 'link9')" onMouseOut="HideTip('tt9')" class=ISymbol>MULTITHREAD</a></td></tr><tr><td class=IHeading><a name="S"></a>S</td><td></td></tr><tr><td class=ISymbolPrefix id=IOnlySymbolPrefix> </td><td class=IEntry><a href="../files/linux/core_portme-h.html#SEED_METHOD" id=link10 onMouseOver="ShowTip(event, 'tt10', 'link10')" onMouseOut="HideTip('tt10')" class=ISymbol>SEED_METHOD</a></td></tr><tr><td class=IHeading><a name="T"></a>T</td><td></td></tr><tr><td class=ISymbolPrefix id=IOnlySymbolPrefix> </td><td class=IEntry><a href="../files/coremark-h.html#TOTAL_DATA_SIZE" id=link11 onMouseOver="ShowTip(event, 'tt11', 'link11')" onMouseOut="HideTip('tt11')" class=ISymbol>TOTAL_DATA_SIZE</a></td></tr><tr><td class=IHeading><a name="U"></a>U</td><td></td></tr><tr><td class=ISymbolPrefix id=IFirstSymbolPrefix> </td><td class=IEntry><a href="../files/linux/core_portme-h.html#USE_CLOCK" id=link12 onMouseOver="ShowTip(event, 'tt12', 'link12')" onMouseOut="HideTip('tt12')" class=ISymbol>USE_CLOCK</a></td></tr><tr><td class=ISymbolPrefix> </td><td class=IEntry><a href="../files/linux/core_portme-h.html#USE_FORK" id=link13 onMouseOver="ShowTip(event, 'tt13', 'link13')" onMouseOut="HideTip('tt13')" class=ISymbol>USE_FORK</a></td></tr><tr><td class=ISymbolPrefix> </td><td class=IEntry><a href="../files/linux/core_portme-h.html#USE_PTHREAD" id=link14 onMouseOver="ShowTip(event, 'tt14', 'link14')" onMouseOut="HideTip('tt14')" class=ISymbol>USE_PTHREAD</a></td></tr><tr><td class=ISymbolPrefix id=ILastSymbolPrefix> </td><td class=IEntry><a href="../files/linux/core_portme-h.html#USE_SOCKET" id=link15 onMouseOver="ShowTip(event, 'tt15', 'link15')" onMouseOut="HideTip('tt15')" class=ISymbol>USE_SOCKET</a></td></tr></table>
+<!--START_ND_TOOLTIPS-->
+<div class=CToolTip id="tt1"><div class=CConfiguration>Define type of return from the timing functions.</div></div><!--END_ND_TOOLTIPS-->
+
+
+<!--START_ND_TOOLTIPS-->
+<div class=CToolTip id="tt2"><div class=CConfiguration>Define to 1 if the platform supports floating point.</div></div><div class=CToolTip id="tt3"><div class=CConfiguration>Define to 1 if the platform has stdio.h and implements the printf function.</div></div><div class=CToolTip id="tt4"><div class=CConfiguration>Define to 1 if the platform has stdio.h.</div></div><div class=CToolTip id="tt5"><div class=CConfiguration>Define to 1 if platform has the time.h header file, and implementation of functions thereof.</div></div><!--END_ND_TOOLTIPS-->
+
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+<!--START_ND_TOOLTIPS-->
+<div class=CToolTip id="tt6"><div class=CConfiguration>Needed if platform does not support getting arguments to main.</div></div><div class=CToolTip id="tt7"><div class=CConfiguration>Needed if platform does not support returning a value from main.</div></div><div class=CToolTip id="tt8"><div class=CConfiguration>Defines method to get a block of memry.</div></div><div class=CToolTip id="tt9"><div class=CConfiguration>Define for parallel execution</div></div><!--END_ND_TOOLTIPS-->
+
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+<!--START_ND_TOOLTIPS-->
+<div class=CToolTip id="tt10"><div class=CConfiguration>Defines method to get seed values that cannot be computed at compile time.</div></div><!--END_ND_TOOLTIPS-->
+
+
+<!--START_ND_TOOLTIPS-->
+<div class=CToolTip id="tt11"><div class=CConfiguration>Define total size for data algorithms will operate on</div></div><!--END_ND_TOOLTIPS-->
+
+
+<!--START_ND_TOOLTIPS-->
+<div class=CToolTip id="tt12"><div class=CConfiguration>Define to 1 if platform has the time.h header file, and implementation of functions thereof.</div></div><div class=CToolTip id="tt13"><div class=CConfiguration>Sample implementation for launching parallel contexts This implementation uses fork, waitpid, shmget,shmat and shmdt.</div></div><div class=CToolTip id="tt14"><div class=CConfiguration>Sample implementation for launching parallel contexts This implementation uses pthread_thread_create and pthread_join.</div></div><div class=CToolTip id="tt15"><div class=CConfiguration>Sample implementation for launching parallel contexts This implementation uses fork, socket, sendto and recvfrom</div></div><!--END_ND_TOOLTIPS-->
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diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/index/Configurations.html b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/index/Configurations.html
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+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd">
+
+<html><head><title>Configuration Index</title><link rel="stylesheet" type="text/css" href="../styles/main.css"><script language=JavaScript src="../javascript/main.js"></script><script language=JavaScript src="../javascript/searchdata.js"></script></head><body class="IndexPage" onLoad="NDOnLoad()"><script language=JavaScript><!--
+if (browserType) {document.write("<div class=" + browserType + ">");if (browserVer) {document.write("<div class=" + browserVer + ">"); }}// --></script>
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+<!-- Generated by Natural Docs, version Development Release 01-12-2008 (1.35 base) -->
+<!-- http://www.naturaldocs.org -->
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+<!-- saved from url=(0026)http://www.naturaldocs.org -->
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+<div id=Index><div class=IPageTitle>Configuration Index</div><div class=INavigationBar>$#! · 0-9 · A · B · C · D · E · F · G · <a href="#H">H</a> · I · J · K · L · <a href="#M">M</a> · N · O · P · Q · R · <a href="#S">S</a> · <a href="#T">T</a> · U · V · W · X · Y · Z</div><table border=0 cellspacing=0 cellpadding=0><tr><td class=IHeading id=IFirstHeading><a name="H"></a>H</td><td></td></tr><tr><td class=ISymbolPrefix id=IFirstSymbolPrefix> </td><td class=IEntry><a href="../files/coremark-h.html#HAS_FLOAT" id=link1 onMouseOver="ShowTip(event, 'tt1', 'link1')" onMouseOut="HideTip('tt1')" class=ISymbol>HAS_FLOAT</a></td></tr><tr><td class=ISymbolPrefix> </td><td class=IEntry><a href="../files/coremark-h.html#HAS_STDIO" id=link2 onMouseOver="ShowTip(event, 'tt2', 'link2')" onMouseOut="HideTip('tt2')" class=ISymbol>HAS_STDIO</a></td></tr><tr><td class=ISymbolPrefix id=ILastSymbolPrefix> </td><td class=IEntry><a href="../files/coremark-h.html#HAS_TIME_H" id=link3 onMouseOver="ShowTip(event, 'tt3', 'link3')" onMouseOut="HideTip('tt3')" class=ISymbol>HAS_TIME_H</a></td></tr><tr><td class=IHeading><a name="M"></a>M</td><td></td></tr><tr><td class=ISymbolPrefix id=IOnlySymbolPrefix> </td><td class=IEntry><a href="../files/coremark-h.html#MEM_METHOD" id=link4 onMouseOver="ShowTip(event, 'tt4', 'link4')" onMouseOut="HideTip('tt4')" class=ISymbol>MEM_METHOD</a></td></tr><tr><td class=IHeading><a name="S"></a>S</td><td></td></tr><tr><td class=ISymbolPrefix id=IOnlySymbolPrefix> </td><td class=IEntry><a href="../files/coremark-h.html#SEED_METHOD" id=link5 onMouseOver="ShowTip(event, 'tt5', 'link5')" onMouseOut="HideTip('tt5')" class=ISymbol>SEED_METHOD</a></td></tr><tr><td class=IHeading><a name="T"></a>T</td><td></td></tr><tr><td class=ISymbolPrefix id=IOnlySymbolPrefix> </td><td class=IEntry><a href="../files/coremark-h.html#TOTAL_DATA_SIZE" id=link6 onMouseOver="ShowTip(event, 'tt6', 'link6')" onMouseOut="HideTip('tt6')" class=ISymbol>TOTAL_DATA_SIZE</a></td></tr></table>
+<!--START_ND_TOOLTIPS-->
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+<!--START_ND_TOOLTIPS-->
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+<!--START_ND_TOOLTIPS-->
+<div class=CToolTip id="tt6"><div class=CConfiguration>Define total size for data algorithms will operate on</div></div><!--END_ND_TOOLTIPS-->
+
+</div><!--Index-->
+
+
+<div id=Footer><a href="http://www.naturaldocs.org">Generated by Natural Docs</a></div><!--Footer-->
+
+
+<div id=Menu><div class=MEntry><div class=MFile><a href="../files/readme-txt.html">CoreMark Version 0.1a</a></div></div><div class=MEntry><div class=MFile><a href="../files/core_list-c.html">core_list.c</a></div></div><div class=MEntry><div class=MFile><a href="../files/core_matrix-c.html">core_matrix.c</a></div></div><div class=MEntry><div class=MFile><a href="../files/core_portme-c.html">core_portme.c</a></div></div><div class=MEntry><div class=MFile><a href="../files/core_main-c.html">core_results</a></div></div><div class=MEntry><div class=MFile><a href="../files/core_state-c.html">core_state.c</a></div></div><div class=MEntry><div class=MFile><a href="../files/coremark-h.html">coremark.h</a></div></div><div class=MEntry><div class=MGroup><a href="javascript:ToggleMenu('MGroupContent1')">Index</a><div class=MGroupContent id=MGroupContent1><div class=MEntry><div class=MIndex><a href="General.html">Everything</a></div></div><div class=MEntry><div class=MIndex><a href="Classes.html">Classes</a></div></div><div class=MEntry><div class=MIndex><a href="Files.html">Files</a></div></div><div class=MEntry><div class=MIndex><a href="Functions.html">Functions</a></div></div><div class=MEntry><div class=MIndex><a href="Types.html">Types</a></div></div><div class=MEntry><div class=MIndex id=MSelected>Configurations</div></div></div></div></div><script type="text/javascript"><!--
+var searchPanel = new SearchPanel("searchPanel", "HTML", "../search");
+--></script><div id=MSearchPanel class=MSearchPanelInactive><input type=text id=MSearchField value=Search onFocus="searchPanel.OnSearchFieldFocus(true)" onBlur="searchPanel.OnSearchFieldFocus(false)" onKeyUp="searchPanel.OnSearchFieldChange()"><select id=MSearchType onFocus="searchPanel.OnSearchTypeFocus(true)" onBlur="searchPanel.OnSearchTypeFocus(false)" onChange="searchPanel.OnSearchTypeChange()"><option id=MSearchEverything selected value="General">Everything</option><option value="Classes">Classes</option><option value="Configurations">Configurations</option><option value="Files">Files</option><option value="Functions">Functions</option><option value="Types">Types</option></select></div></div><!--Menu-->
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+
+<div id=MSearchResultsWindow><iframe src="" frameborder=0 name=MSearchResults id=MSearchResults></iframe><a href="javascript:searchPanel.CloseResultsWindow()" id=MSearchResultsWindowClose>Close</a></div>
+
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+<script language=JavaScript><!--
+if (browserType) {if (browserVer) {document.write("</div>"); }document.write("</div>");}// --></script></body></html>
\ No newline at end of file
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/index/Files.html b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/index/Files.html
new file mode 100644
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--- /dev/null
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+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd">
+
+<html><head><title>File Index - CoreMark</title><link rel="stylesheet" type="text/css" href="../styles/main.css"><script language=JavaScript src="../javascript/main.js"></script><script language=JavaScript src="../javascript/searchdata.js"></script></head><body class="IndexPage" onLoad="NDOnLoad()"><script language=JavaScript><!--
+if (browserType) {document.write("<div class=" + browserType + ">");if (browserVer) {document.write("<div class=" + browserVer + ">"); }}// --></script>
+
+<!-- Copyright 2009 EEMBC -->
+<!-- saved from url=(0026)http://www.naturaldocs.org -->
+
+
+
+
+<div id=Index><div class=IPageTitle>File Index</div><div class=INavigationBar>$#! · 0-9 · A · B · <a href="#C">C</a> · D · E · F · G · H · I · J · K · L · M · N · O · P · Q · <a href="#R">R</a> · S · T · U · V · W · X · Y · Z</div><table border=0 cellspacing=0 cellpadding=0><tr><td class=IHeading id=IFirstHeading><a name="C"></a>C</td><td></td></tr><tr><td class=ISymbolPrefix id=IFirstSymbolPrefix> </td><td class=IEntry><a href="../files/core_list_join-c.html#core_list_join.c" class=ISymbol>core_list_join.c</a></td></tr><tr><td class=ISymbolPrefix> </td><td class=IEntry><a href="../files/core_main-c.html#core_main.c" id=link1 onMouseOver="ShowTip(event, 'tt1', 'link1')" onMouseOut="HideTip('tt1')" class=ISymbol>core_main.c</a></td></tr><tr><td class=ISymbolPrefix> </td><td class=IEntry><a href="../files/core_matrix-c.html#core_matrix.c" class=ISymbol>core_matrix.c</a></td></tr><tr><td class=ISymbolPrefix> </td><td class=IEntry><a href="../files/linux/core_portme-c.html#core_portme.c" class=ISymbol>core_portme.c</a></td></tr><tr><td class=ISymbolPrefix> </td><td class=IEntry><a href="../files/linux/core_portme-h.html#core_portme.h" class=ISymbol>core_portme.h</a></td></tr><tr><td class=ISymbolPrefix> </td><td class=IEntry><span class=ISymbol>core_portme.mak</span><div class=ISubIndex><a href="../files/linux/core_portme-mak.html#core_portme.mak" class=IFile>linux/<span class=HB> </span>core_portme.mak</a><a href="../files/PIC32/core_portme-mak.html#core_portme.mak" class=IFile>PIC32/<span class=HB> </span>core_portme.mak</a></div></td></tr><tr><td class=ISymbolPrefix> </td><td class=IEntry><a href="../files/core_state-c.html#core_state.c" class=ISymbol>core_state.c</a></td></tr><tr><td class=ISymbolPrefix> </td><td class=IEntry><a href="../files/core_util-c.html#core_util.c" class=ISymbol>core_util.c</a></td></tr><tr><td class=ISymbolPrefix> </td><td class=IEntry><a href="../files/readme-txt.html#CoreMark" class=ISymbol>CoreMark</a></td></tr><tr><td class=ISymbolPrefix id=ILastSymbolPrefix> </td><td class=IEntry><a href="../files/coremark-h.html#coremark.h" class=ISymbol>coremark.h</a></td></tr><tr><td class=IHeading><a name="R"></a>R</td><td></td></tr><tr><td class=ISymbolPrefix id=IOnlySymbolPrefix> </td><td class=IEntry><a href="../files/release_notes-txt.html#Release_Notes" id=link2 onMouseOver="ShowTip(event, 'tt2', 'link2')" onMouseOut="HideTip('tt2')" class=ISymbol>Release Notes</a></td></tr></table>
+<!--START_ND_TOOLTIPS-->
+<div class=CToolTip id="tt1"><div class=CFile>This file contains the framework to acquire a block of memory, seed initial parameters, tun t he benchmark and report the results.</div></div><!--END_ND_TOOLTIPS-->
+
+
+<!--START_ND_TOOLTIPS-->
+<div class=CToolTip id="tt2"><div class=CFile>Version: 1.01</div></div><!--END_ND_TOOLTIPS-->
+
+</div><!--Index-->
+
+
+<div id=Footer><a href="http://www.naturaldocs.org">Copyright 2009 EEMBC</a></div><!--Footer-->
+
+
+<div id=Menu><div class=MTitle>CoreMark<div class=MSubTitle>(c) EEMBC</div></div><div class=MEntry><div class=MFile><a href="../files/readme-txt.html">CoreMark</a></div></div><div class=MEntry><div class=MFile><a href="../files/release_notes-txt.html">Release Notes</a></div></div><div class=MEntry><div class=MGroup><a href="javascript:ToggleMenu('MGroupContent2')">Source</a><div class=MGroupContent id=MGroupContent2><div class=MEntry><div class=MFile><a href="../files/core_list_join-c.html">core_list_join.c</a></div></div><div class=MEntry><div class=MFile><a href="../files/core_main-c.html">core_main.c</a></div></div><div class=MEntry><div class=MFile><a href="../files/core_matrix-c.html">core_matrix.c</a></div></div><div class=MEntry><div class=MFile><a href="../files/PIC32/core_portme-mak.html">core_portme.mak</a></div></div><div class=MEntry><div class=MFile><a href="../files/core_state-c.html">core_state.c</a></div></div><div class=MEntry><div class=MFile><a href="../files/core_util-c.html">core_util.c</a></div></div><div class=MEntry><div class=MFile><a href="../files/coremark-h.html">coremark.h</a></div></div><div class=MEntry><div class=MGroup><a href="javascript:ToggleMenu('MGroupContent1')">Porting</a><div class=MGroupContent id=MGroupContent1><div class=MEntry><div class=MFile><a href="../files/linux/core_portme-c.html">PORT_DIR/<span class=HB> </span>core_portme.c</a></div></div><div class=MEntry><div class=MFile><a href="../files/linux/core_portme-h.html">PORT_DIR/<span class=HB> </span>core_portme.h</a></div></div><div class=MEntry><div class=MFile><a href="../files/linux/core_portme-mak.html">PORT_DIR/<span class=HB> </span>core_portme.mak</a></div></div></div></div></div></div></div></div><div class=MEntry><div class=MGroup><a href="javascript:ToggleMenu('MGroupContent3')">Index</a><div class=MGroupContent id=MGroupContent3><div class=MEntry><div class=MIndex><a href="General.html">Everything</a></div></div><div class=MEntry><div class=MIndex id=MSelected>Files</div></div><div class=MEntry><div class=MIndex><a href="Functions.html">Functions</a></div></div><div class=MEntry><div class=MIndex><a href="Types.html">Types</a></div></div><div class=MEntry><div class=MIndex><a href="Configuration.html">Configurations</a></div></div><div class=MEntry><div class=MIndex><a href="Variables.html">Variables</a></div></div><div class=MEntry><div class=MIndex><a href="BuildTargets.html">Build Targets</a></div></div></div></div></div><script type="text/javascript"><!--
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+
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+<div id=MSearchResultsWindow><iframe src="" frameborder=0 name=MSearchResults id=MSearchResults></iframe><a href="javascript:searchPanel.CloseResultsWindow()" id=MSearchResultsWindowClose>Close</a></div>
+
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+<script language=JavaScript><!--
+if (browserType) {if (browserVer) {document.write("</div>"); }document.write("</div>");}// --></script></body></html>
\ No newline at end of file
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/index/Functions.html b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/index/Functions.html
new file mode 100644
index 0000000..a249d51
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/index/Functions.html
@@ -0,0 +1,55 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd">
+
+<html><head><title>Function Index - CoreMark</title><link rel="stylesheet" type="text/css" href="../styles/main.css"><script language=JavaScript src="../javascript/main.js"></script><script language=JavaScript src="../javascript/searchdata.js"></script></head><body class="IndexPage" onLoad="NDOnLoad()"><script language=JavaScript><!--
+if (browserType) {document.write("<div class=" + browserType + ">");if (browserVer) {document.write("<div class=" + browserVer + ">"); }}// --></script>
+
+<!-- Copyright 2009 EEMBC -->
+<!-- saved from url=(0026)http://www.naturaldocs.org -->
+
+
+
+
+<div id=Index><div class=IPageTitle>Function Index</div><div class=INavigationBar>$#! · 0-9 · A · B · <a href="#C">C</a> · D · E · F · <a href="#G">G</a> · H · <a href="#I">I</a> · J · K · L · <a href="#M">M</a> · N · O · <a href="#P">P</a> · Q · R · <a href="#S">S</a> · <a href="#T">T</a> · U · V · W · X · Y · Z</div><table border=0 cellspacing=0 cellpadding=0><tr><td class=IHeading id=IFirstHeading><a name="C"></a>C</td><td></td></tr><tr><td class=ISymbolPrefix id=IFirstSymbolPrefix> </td><td class=IEntry><a href="../files/core_list_join-c.html#cmp_complex" id=link1 onMouseOver="ShowTip(event, 'tt1', 'link1')" onMouseOut="HideTip('tt1')" class=ISymbol>cmp_complex</a></td></tr><tr><td class=ISymbolPrefix> </td><td class=IEntry><a href="../files/core_list_join-c.html#cmp_idx" id=link2 onMouseOver="ShowTip(event, 'tt2', 'link2')" onMouseOut="HideTip('tt2')" class=ISymbol>cmp_idx</a></td></tr><tr><td class=ISymbolPrefix> </td><td class=IEntry><a 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onMouseOut="HideTip('tt11')" class=ISymbol>core_list_reverse</a></td></tr><tr><td class=ISymbolPrefix> </td><td class=IEntry><a href="../files/core_list_join-c.html#core_list_undo_remove" id=link12 onMouseOver="ShowTip(event, 'tt12', 'link12')" onMouseOut="HideTip('tt12')" class=ISymbol>core_list_undo_remove</a></td></tr><tr><td class=ISymbolPrefix> </td><td class=IEntry><a href="../files/linux/core_portme-c.html#core_start_parallel" id=link13 onMouseOver="ShowTip(event, 'tt13', 'link13')" onMouseOut="HideTip('tt13')" class=ISymbol>core_start_parallel</a></td></tr><tr><td class=ISymbolPrefix> </td><td class=IEntry><a href="../files/core_state-c.html#core_state_transition" id=link14 onMouseOver="ShowTip(event, 'tt14', 'link14')" onMouseOut="HideTip('tt14')" class=ISymbol>core_state_transition</a></td></tr><tr><td class=ISymbolPrefix> </td><td class=IEntry><a href="../files/linux/core_portme-c.html#core_stop_parallel" id=link15 onMouseOver="ShowTip(event, 'tt15', 'link15')" onMouseOut="HideTip('tt15')" class=ISymbol>core_stop_parallel</a></td></tr><tr><td class=ISymbolPrefix id=ILastSymbolPrefix> </td><td class=IEntry><a href="../files/core_util-c.html#crc*" id=link16 onMouseOver="ShowTip(event, 'tt16', 'link16')" onMouseOut="HideTip('tt16')" class=ISymbol>crc*</a></td></tr><tr><td class=IHeading><a name="G"></a>G</td><td></td></tr><tr><td class=ISymbolPrefix id=IFirstSymbolPrefix> </td><td class=IEntry><a href="../files/core_util-c.html#get_seed" id=link17 onMouseOver="ShowTip(event, 'tt17', 'link17')" onMouseOut="HideTip('tt17')" class=ISymbol>get_seed</a></td></tr><tr><td class=ISymbolPrefix id=ILastSymbolPrefix> </td><td class=IEntry><a href="../files/linux/core_portme-c.html#get_time" id=link18 onMouseOver="ShowTip(event, 'tt18', 'link18')" onMouseOut="HideTip('tt18')" class=ISymbol>get_time</a></td></tr><tr><td class=IHeading><a name="I"></a>I</td><td></td></tr><tr><td class=ISymbolPrefix id=IOnlySymbolPrefix> </td><td class=IEntry><a href="../files/core_main-c.html#iterate" id=link19 onMouseOver="ShowTip(event, 'tt19', 'link19')" onMouseOut="HideTip('tt19')" class=ISymbol>iterate</a></td></tr><tr><td class=IHeading><a name="M"></a>M</td><td></td></tr><tr><td class=ISymbolPrefix id=IFirstSymbolPrefix> </td><td class=IEntry><a href="../files/core_main-c.html#main" id=link20 onMouseOver="ShowTip(event, 'tt20', 'link20')" onMouseOut="HideTip('tt20')" class=ISymbol>main</a></td></tr><tr><td class=ISymbolPrefix> </td><td class=IEntry><a href="../files/core_matrix-c.html#matrix_add_const" id=link21 onMouseOver="ShowTip(event, 'tt21', 'link21')" onMouseOut="HideTip('tt21')" class=ISymbol>matrix_add_const</a></td></tr><tr><td class=ISymbolPrefix> </td><td class=IEntry><a href="../files/core_matrix-c.html#matrix_mul_const" id=link22 onMouseOver="ShowTip(event, 'tt22', 'link22')" onMouseOut="HideTip('tt22')" class=ISymbol>matrix_mul_const</a></td></tr><tr><td class=ISymbolPrefix> </td><td class=IEntry><a href="../files/core_matrix-c.html#matrix_mul_matrix" id=link23 onMouseOver="ShowTip(event, 'tt23', 'link23')" onMouseOut="HideTip('tt23')" class=ISymbol>matrix_mul_matrix</a></td></tr><tr><td class=ISymbolPrefix> </td><td class=IEntry><a href="../files/core_matrix-c.html#matrix_mul_matrix_bitextract" id=link24 onMouseOver="ShowTip(event, 'tt24', 'link24')" onMouseOut="HideTip('tt24')" class=ISymbol>matrix_mul_matrix_bitextract</a></td></tr><tr><td class=ISymbolPrefix> </td><td class=IEntry><a href="../files/core_matrix-c.html#matrix_mul_vect" id=link25 onMouseOver="ShowTip(event, 'tt25', 'link25')" onMouseOut="HideTip('tt25')" class=ISymbol>matrix_mul_vect</a></td></tr><tr><td class=ISymbolPrefix> </td><td class=IEntry><a href="../files/core_matrix-c.html#matrix_sum" id=link26 onMouseOver="ShowTip(event, 'tt26', 'link26')" onMouseOut="HideTip('tt26')" class=ISymbol>matrix_sum</a></td></tr><tr><td class=ISymbolPrefix id=ILastSymbolPrefix> </td><td class=IEntry><a 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id=ILastSymbolPrefix> </td><td class=IEntry><a href="../files/linux/core_portme-c.html#portable_malloc" id=link31 onMouseOver="ShowTip(event, 'tt31', 'link31')" onMouseOut="HideTip('tt31')" class=ISymbol>portable_malloc</a></td></tr><tr><td class=IHeading><a name="S"></a>S</td><td></td></tr><tr><td class=ISymbolPrefix id=IFirstSymbolPrefix> </td><td class=IEntry><a href="../files/linux/core_portme-c.html#start_time" id=link32 onMouseOver="ShowTip(event, 'tt32', 'link32')" onMouseOut="HideTip('tt32')" class=ISymbol>start_time</a></td></tr><tr><td class=ISymbolPrefix id=ILastSymbolPrefix> </td><td class=IEntry><a href="../files/linux/core_portme-c.html#stop_time" id=link33 onMouseOver="ShowTip(event, 'tt33', 'link33')" onMouseOut="HideTip('tt33')" class=ISymbol>stop_time</a></td></tr><tr><td class=IHeading><a name="T"></a>T</td><td></td></tr><tr><td class=ISymbolPrefix id=IOnlySymbolPrefix> </td><td class=IEntry><a href="../files/linux/core_portme-c.html#time_in_secs" id=link34 onMouseOver="ShowTip(event, 'tt34', 'link34')" onMouseOut="HideTip('tt34')" class=ISymbol>time_in_secs</a></td></tr></table>
+<!--START_ND_TOOLTIPS-->
+<div class=CToolTip id="tt1"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>ee_s32 cmp_complex(</td><td class=PType nowrap>list_data </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>a,</td></tr><tr><td></td><td class=PType nowrap>list_data </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>b,</td></tr><tr><td></td><td class=PType nowrap>core_results </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>res</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Compare the data item in a list cell.</div></div><div class=CToolTip id="tt2"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>ee_s32 cmp_idx(</td><td class=PType nowrap>list_data </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>a,</td></tr><tr><td></td><td class=PType nowrap>list_data </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>b,</td></tr><tr><td></td><td class=PType nowrap>core_results </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>res</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Compare the idx item in a list cell, and regen the data.</div></div><div class=CToolTip id="tt3"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>ee_u16 core_bench_matrix(</td><td class=PType nowrap>mat_params </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>p,</td></tr><tr><td></td><td class=PType nowrap>ee_s16 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>seed,</td></tr><tr><td></td><td class=PType nowrap>ee_u16 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>crc</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Benchmark function</div></div><div class=CToolTip id="tt4"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>ee_u16 core_bench_state(</td><td class=PType nowrap>ee_u32 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>blksize,</td></tr><tr><td></td><td class=PType nowrap>ee_u8 </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>memblock,</td></tr><tr><td></td><td class=PType nowrap>ee_s16 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>seed1,</td></tr><tr><td></td><td class=PType nowrap>ee_s16 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>seed2,</td></tr><tr><td></td><td class=PType nowrap>ee_s16 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>step,</td></tr><tr><td></td><td class=PType nowrap>ee_u16 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>crc</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Benchmark function</div></div><div class=CToolTip id="tt5"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>void core_init_state(</td><td class=PType nowrap>ee_u32 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>size,</td></tr><tr><td></td><td class=PType nowrap>ee_s16 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>seed,</td></tr><tr><td></td><td class=PType nowrap>ee_u8 </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>p</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Initialize the input data for the state machine.</div></div><div class=CToolTip id="tt6"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>list_head *core_list_find(</td><td class=PType nowrap>list_head </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>list,</td></tr><tr><td></td><td class=PType nowrap>list_data </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>info</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Find an item in the list</div></div><div class=CToolTip id="tt7"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>list_head *core_list_init(</td><td class=PType nowrap>ee_u32 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>blksize,</td></tr><tr><td></td><td class=PType nowrap>list_head </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>memblock,</td></tr><tr><td></td><td class=PType nowrap>ee_s16 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>seed</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Initialize list with data.</div></div><div class=CToolTip id="tt8"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>list_head *core_list_insert_new(</td><td class=PTypePrefix nowrap></td><td class=PType nowrap>list_head </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>insert_point,</td></tr><tr><td></td><td class=PTypePrefix nowrap></td><td class=PType nowrap>list_data </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>info,</td></tr><tr><td></td><td class=PTypePrefix nowrap></td><td class=PType nowrap>list_head </td><td class=PParameterPrefix nowrap>**</td><td class=PParameter nowrap>memblock,</td></tr><tr><td></td><td class=PTypePrefix nowrap>list_data </td><td class=PType nowrap>**datablock </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>,</td></tr><tr><td></td><td class=PTypePrefix nowrap></td><td class=PType nowrap>list_head </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>memblock_end,</td></tr><tr><td></td><td class=PTypePrefix nowrap></td><td class=PType nowrap>list_data </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>datablock_end</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Insert an item to the list</div></div><div class=CToolTip id="tt9"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>list_head *core_list_mergesort(</td><td class=PType nowrap>list_head </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>list,</td></tr><tr><td></td><td class=PType nowrap>list_cmp </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>cmp,</td></tr><tr><td></td><td class=PType nowrap>core_results </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>res</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Sort the list in place without recursion.</div></div><div class=CToolTip id="tt10"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>list_head *core_list_remove(</td><td class=PType nowrap>list_head </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>item</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Remove an item from the list.</div></div><div class=CToolTip id="tt11"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>list_head *core_list_reverse(</td><td class=PType nowrap>list_head </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>list</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Reverse a list</div></div><div class=CToolTip id="tt12"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>list_head *core_list_undo_remove(</td><td class=PType nowrap>list_head </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>item_removed,</td></tr><tr><td></td><td class=PType nowrap>list_head </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>item_modified</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Undo a remove operation.</div></div><div class=CToolTip id="tt13"><div class=CFunction>Start benchmarking in a parallel context.</div></div><div class=CToolTip id="tt14"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>enum CORE_STATE core_state_transition(</td><td class=PTypePrefix nowrap>ee_u8 </td><td class=PType nowrap>**instr </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>,</td></tr><tr><td></td><td class=PTypePrefix nowrap></td><td class=PType nowrap>ee_u32 </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>transition_count</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Actual state machine.</div></div><div class=CToolTip id="tt15"><div class=CFunction>Stop a parallel context execution of coremark, and gather the results.</div></div><div class=CToolTip id="tt16"><div class=CFunction>Service functions to calculate 16b CRC code.</div></div><!--END_ND_TOOLTIPS-->
+
+
+<!--START_ND_TOOLTIPS-->
+<div class=CToolTip id="tt17"><div class=CFunction>Get a values that cannot be determined at compile time.</div></div><div class=CToolTip id="tt18"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>CORE_TICKS get_time(</td><td class=PParameter nowrap>void</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Return an abstract “ticks” number that signifies time on the system.</div></div><!--END_ND_TOOLTIPS-->
+
+
+<!--START_ND_TOOLTIPS-->
+<div class=CToolTip id="tt19"><div class=CFunction>Run the benchmark for a specified number of iterations.</div></div><!--END_ND_TOOLTIPS-->
+
+
+<!--START_ND_TOOLTIPS-->
+<div class=CToolTip id="tt20"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>#if MAIN_HAS_NOARGC MAIN_RETURN_TYPE main(</td><td class=PParameter nowrap>void</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Main entry routine for the benchmark. </div></div><div class=CToolTip id="tt21"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>void matrix_add_const(</td><td class=PType nowrap>ee_u32 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>N,</td></tr><tr><td></td><td class=PType nowrap>MATDAT </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>A,</td></tr><tr><td></td><td class=PType nowrap>MATDAT </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>val</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Add a constant value to all elements of a matrix.</div></div><div class=CToolTip id="tt22"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>void matrix_mul_const(</td><td class=PType nowrap>ee_u32 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>N,</td></tr><tr><td></td><td class=PType nowrap>MATRES </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>C,</td></tr><tr><td></td><td class=PType nowrap>MATDAT </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>A,</td></tr><tr><td></td><td class=PType nowrap>MATDAT </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>val</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Multiply a matrix by a constant. </div></div><div class=CToolTip id="tt23"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>void matrix_mul_matrix(</td><td class=PType nowrap>ee_u32 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>N,</td></tr><tr><td></td><td class=PType nowrap>MATRES </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>C,</td></tr><tr><td></td><td class=PType nowrap>MATDAT </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>A,</td></tr><tr><td></td><td class=PType nowrap>MATDAT </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>B</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Multiply a matrix by a matrix. </div></div><div class=CToolTip id="tt24"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>void matrix_mul_matrix_bitextract(</td><td class=PType nowrap>ee_u32 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>N,</td></tr><tr><td></td><td class=PType nowrap>MATRES </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>C,</td></tr><tr><td></td><td class=PType nowrap>MATDAT </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>A,</td></tr><tr><td></td><td class=PType nowrap>MATDAT </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>B</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Multiply a matrix by a matrix, and extract some bits from the result. </div></div><div class=CToolTip id="tt25"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>void matrix_mul_vect(</td><td class=PType nowrap>ee_u32 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>N,</td></tr><tr><td></td><td class=PType nowrap>MATRES </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>C,</td></tr><tr><td></td><td class=PType nowrap>MATDAT </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>A,</td></tr><tr><td></td><td class=PType nowrap>MATDAT </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>B</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Multiply a matrix by a vector. </div></div><div class=CToolTip id="tt26"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>ee_s16 matrix_sum(</td><td class=PType nowrap>ee_u32 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>N,</td></tr><tr><td></td><td class=PType nowrap>MATRES </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>C,</td></tr><tr><td></td><td class=PType nowrap>MATDAT </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>clipval</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Calculate a function that depends on the values of elements in the matrix.</div></div><div class=CToolTip id="tt27"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>ee_s16 matrix_test(</td><td class=PType nowrap>ee_u32 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>N,</td></tr><tr><td></td><td class=PType nowrap>MATRES </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>C,</td></tr><tr><td></td><td class=PType nowrap>MATDAT </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>A,</td></tr><tr><td></td><td class=PType nowrap>MATDAT </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>B,</td></tr><tr><td></td><td class=PType nowrap>MATDAT </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>val</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Perform matrix manipulation.</div></div><!--END_ND_TOOLTIPS-->
+
+
+<!--START_ND_TOOLTIPS-->
+<div class=CToolTip id="tt28"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>void portable_fini(</td><td class=PType nowrap>core_portable </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>p</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Target specific final code</div></div><div class=CToolTip id="tt29"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>void portable_free(</td><td class=PType nowrap>void </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>p</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Provide free() functionality in a platform specific way.</div></div><div class=CToolTip id="tt30"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>void portable_init(</td><td class=PType nowrap>core_portable </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>p,</td></tr><tr><td></td><td class=PType nowrap>int </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>argc,</td></tr><tr><td></td><td class=PType nowrap>char </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>argv[]</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Target specific initialization code Test for some common mistakes.</div></div><div class=CToolTip id="tt31"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>void *portable_malloc(</td><td class=PType nowrap>size_t </td><td class=PParameter nowrap>size</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Provide malloc() functionality in a platform specific way.</div></div><!--END_ND_TOOLTIPS-->
+
+
+<!--START_ND_TOOLTIPS-->
+<div class=CToolTip id="tt32"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>void start_time(</td><td class=PParameter nowrap>void</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>This function will be called right before starting the timed portion of the benchmark.</div></div><div class=CToolTip id="tt33"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>void stop_time(</td><td class=PParameter nowrap>void</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>This function will be called right after ending the timed portion of the benchmark.</div></div><!--END_ND_TOOLTIPS-->
+
+
+<!--START_ND_TOOLTIPS-->
+<div class=CToolTip id="tt34"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>secs_ret time_in_secs(</td><td class=PType nowrap>CORE_TICKS </td><td class=PParameter nowrap>ticks</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Convert the value returned by get_time to seconds.</div></div><!--END_ND_TOOLTIPS-->
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diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/index/General.html b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/index/General.html
new file mode 100644
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+<!--START_ND_TOOLTIPS-->
+<div class=CToolTip id="tt1"><div class=CGeneric>Download the release files from the www.coremark.org. </div></div><!--END_ND_TOOLTIPS-->
+
+
+<!--START_ND_TOOLTIPS-->
+<div class=CToolTip id="tt2"><div class=CVariable>Use this flag to define compiler to use</div></div><div class=CToolTip id="tt3"><div class=CVariable>Use this flag to define compiler options. </div></div><div class=CToolTip id="tt4"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>ee_s32 cmp_complex(</td><td class=PType nowrap>list_data </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>a,</td></tr><tr><td></td><td class=PType nowrap>list_data </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>b,</td></tr><tr><td></td><td class=PType nowrap>core_results </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>res</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Compare the data item in a list cell.</div></div><div class=CToolTip id="tt5"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>ee_s32 cmp_idx(</td><td class=PType nowrap>list_data </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>a,</td></tr><tr><td></td><td class=PType nowrap>list_data </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>b,</td></tr><tr><td></td><td class=PType nowrap>core_results </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>res</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Compare the idx item in a list cell, and regen the data.</div></div><div class=CToolTip id="tt6"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>ee_u16 core_bench_matrix(</td><td class=PType nowrap>mat_params </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>p,</td></tr><tr><td></td><td class=PType nowrap>ee_s16 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>seed,</td></tr><tr><td></td><td class=PType nowrap>ee_u16 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>crc</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Benchmark function</div></div><div class=CToolTip id="tt7"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>ee_u16 core_bench_state(</td><td class=PType nowrap>ee_u32 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>blksize,</td></tr><tr><td></td><td class=PType nowrap>ee_u8 </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>memblock,</td></tr><tr><td></td><td class=PType nowrap>ee_s16 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>seed1,</td></tr><tr><td></td><td class=PType nowrap>ee_s16 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>seed2,</td></tr><tr><td></td><td class=PType nowrap>ee_s16 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>step,</td></tr><tr><td></td><td class=PType nowrap>ee_u16 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>crc</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Benchmark function</div></div><div class=CToolTip id="tt8"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>void core_init_state(</td><td class=PType nowrap>ee_u32 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>size,</td></tr><tr><td></td><td class=PType nowrap>ee_s16 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>seed,</td></tr><tr><td></td><td class=PType nowrap>ee_u8 </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>p</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Initialize the input data for the state machine.</div></div><div class=CToolTip id="tt9"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>list_head *core_list_find(</td><td class=PType nowrap>list_head </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>list,</td></tr><tr><td></td><td class=PType nowrap>list_data </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>info</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Find an item in the list</div></div><div class=CToolTip id="tt10"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>list_head *core_list_init(</td><td class=PType nowrap>ee_u32 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>blksize,</td></tr><tr><td></td><td class=PType nowrap>list_head </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>memblock,</td></tr><tr><td></td><td class=PType nowrap>ee_s16 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>seed</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Initialize list with data.</div></div><div class=CToolTip id="tt11"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>list_head *core_list_insert_new(</td><td class=PTypePrefix nowrap></td><td class=PType nowrap>list_head </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>insert_point,</td></tr><tr><td></td><td class=PTypePrefix nowrap></td><td class=PType nowrap>list_data </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>info,</td></tr><tr><td></td><td class=PTypePrefix nowrap></td><td class=PType nowrap>list_head </td><td class=PParameterPrefix nowrap>**</td><td class=PParameter nowrap>memblock,</td></tr><tr><td></td><td class=PTypePrefix nowrap>list_data </td><td class=PType nowrap>**datablock </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>,</td></tr><tr><td></td><td class=PTypePrefix nowrap></td><td class=PType nowrap>list_head </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>memblock_end,</td></tr><tr><td></td><td class=PTypePrefix nowrap></td><td class=PType nowrap>list_data </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>datablock_end</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Insert an item to the list</div></div><div class=CToolTip id="tt12"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>list_head *core_list_mergesort(</td><td class=PType nowrap>list_head </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>list,</td></tr><tr><td></td><td class=PType nowrap>list_cmp </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>cmp,</td></tr><tr><td></td><td class=PType nowrap>core_results </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>res</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Sort the list in place without recursion.</div></div><div class=CToolTip id="tt13"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>list_head *core_list_remove(</td><td class=PType nowrap>list_head </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>item</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Remove an item from the list.</div></div><div class=CToolTip id="tt14"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>list_head *core_list_reverse(</td><td class=PType nowrap>list_head </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>list</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Reverse a list</div></div><div class=CToolTip id="tt15"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>list_head *core_list_undo_remove(</td><td class=PType nowrap>list_head </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>item_removed,</td></tr><tr><td></td><td class=PType nowrap>list_head </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>item_modified</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Undo a remove operation.</div></div><div class=CToolTip id="tt16"><div class=CFile>This file contains the framework to acquire a block of memory, seed initial parameters, tun t he benchmark and report the results.</div></div><div class=CToolTip id="tt17"><div class=CFunction>Start benchmarking in a parallel context.</div></div><div class=CToolTip id="tt18"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>enum CORE_STATE core_state_transition(</td><td class=PTypePrefix nowrap>ee_u8 </td><td class=PType nowrap>**instr </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>,</td></tr><tr><td></td><td class=PTypePrefix nowrap></td><td class=PType nowrap>ee_u32 </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>transition_count</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Actual state machine.</div></div><div class=CToolTip id="tt19"><div class=CFunction>Stop a parallel context execution of coremark, and gather the results.</div></div><div class=CToolTip id="tt20"><div class=CConfiguration>Define type of return from the timing functions.</div></div><div class=CToolTip id="tt21"><div class=CFunction>Service functions to calculate 16b CRC code.</div></div><div class=CToolTip id="tt22"><div class=CGeneric>Many thanks to all of the individuals who helped with the development or testing of CoreMark including (Sorted by company name)</div></div><!--END_ND_TOOLTIPS-->
+
+
+<!--START_ND_TOOLTIPS-->
+<div class=CToolTip id="tt23"><div class=CVariable><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td>extern ee_u32 default_num_contexts</td></tr></table></blockquote>Number of contexts to spawn in multicore context. </div></div><div class=CToolTip id="tt24"><div class=CGeneric>Benchmark using a linked list.</div></div><div class=CToolTip id="tt25"><div class=CGeneric>When you unpack the documentation (tar -vzxf coremark_version_docs.tgz) a docs folder will be created. </div></div><!--END_ND_TOOLTIPS-->
+
+
+<!--START_ND_TOOLTIPS-->
+<!--END_ND_TOOLTIPS-->
+
+
+<!--START_ND_TOOLTIPS-->
+<div class=CToolTip id="tt26"><div class=CFunction>Get a values that cannot be determined at compile time.</div></div><div class=CToolTip id="tt27"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>CORE_TICKS get_time(</td><td class=PParameter nowrap>void</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Return an abstract “ticks” number that signifies time on the system.</div></div><!--END_ND_TOOLTIPS-->
+
+
+<!--START_ND_TOOLTIPS-->
+<div class=CToolTip id="tt28"><div class=CConfiguration>Define to 1 if the platform supports floating point.</div></div><div class=CToolTip id="tt29"><div class=CConfiguration>Define to 1 if the platform has stdio.h and implements the printf function.</div></div><div class=CToolTip id="tt30"><div class=CConfiguration>Define to 1 if the platform has stdio.h.</div></div><div class=CToolTip id="tt31"><div class=CConfiguration>Define to 1 if platform has the time.h header file, and implementation of functions thereof.</div></div><!--END_ND_TOOLTIPS-->
+
+
+<!--START_ND_TOOLTIPS-->
+<div class=CToolTip id="tt32"><div class=CFunction>Run the benchmark for a specified number of iterations.</div></div><!--END_ND_TOOLTIPS-->
+
+
+<!--START_ND_TOOLTIPS-->
+<div class=CToolTip id="tt33"><div class=CGeneric>See LICENSE.txt or the word document file under docs/LICENSE.doc. </div></div><div class=CToolTip id="tt34"><div class=CVariable>Define any libraries needed for linking or other flags that should come at the end of the link line (e.g. </div></div><div class=CToolTip id="tt35"><div class=CVariable>Define this flag if you need to load to a target, as in a cross compile environment.</div></div><div class=CToolTip id="tt36"><div class=CGeneric>The log files have the following format</div></div><!--END_ND_TOOLTIPS-->
+
+
+<!--START_ND_TOOLTIPS-->
+<div class=CToolTip id="tt37"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>#if MAIN_HAS_NOARGC MAIN_RETURN_TYPE main(</td><td class=PParameter nowrap>void</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Main entry routine for the benchmark. </div></div><div class=CToolTip id="tt38"><div class=CConfiguration>Needed if platform does not support getting arguments to main.</div></div><div class=CToolTip id="tt39"><div class=CConfiguration>Needed if platform does not support returning a value from main.</div></div><div class=CToolTip id="tt40"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>void matrix_add_const(</td><td class=PType nowrap>ee_u32 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>N,</td></tr><tr><td></td><td class=PType nowrap>MATDAT </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>A,</td></tr><tr><td></td><td class=PType nowrap>MATDAT </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>val</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Add a constant value to all elements of a matrix.</div></div><div class=CToolTip id="tt41"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>void matrix_mul_const(</td><td class=PType nowrap>ee_u32 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>N,</td></tr><tr><td></td><td class=PType nowrap>MATRES </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>C,</td></tr><tr><td></td><td class=PType nowrap>MATDAT </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>A,</td></tr><tr><td></td><td class=PType nowrap>MATDAT </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>val</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Multiply a matrix by a constant. </div></div><div class=CToolTip id="tt42"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>void matrix_mul_matrix(</td><td class=PType nowrap>ee_u32 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>N,</td></tr><tr><td></td><td class=PType nowrap>MATRES </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>C,</td></tr><tr><td></td><td class=PType nowrap>MATDAT </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>A,</td></tr><tr><td></td><td class=PType nowrap>MATDAT </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>B</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Multiply a matrix by a matrix. </div></div><div class=CToolTip id="tt43"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>void matrix_mul_matrix_bitextract(</td><td class=PType nowrap>ee_u32 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>N,</td></tr><tr><td></td><td class=PType nowrap>MATRES </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>C,</td></tr><tr><td></td><td class=PType nowrap>MATDAT </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>A,</td></tr><tr><td></td><td class=PType nowrap>MATDAT </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>B</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Multiply a matrix by a matrix, and extract some bits from the result. </div></div><div class=CToolTip id="tt44"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>void matrix_mul_vect(</td><td class=PType nowrap>ee_u32 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>N,</td></tr><tr><td></td><td class=PType nowrap>MATRES </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>C,</td></tr><tr><td></td><td class=PType nowrap>MATDAT </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>A,</td></tr><tr><td></td><td class=PType nowrap>MATDAT </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>B</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Multiply a matrix by a vector. </div></div><div class=CToolTip id="tt45"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>ee_s16 matrix_sum(</td><td class=PType nowrap>ee_u32 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>N,</td></tr><tr><td></td><td class=PType nowrap>MATRES </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>C,</td></tr><tr><td></td><td class=PType nowrap>MATDAT </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>clipval</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Calculate a function that depends on the values of elements in the matrix.</div></div><div class=CToolTip id="tt46"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>ee_s16 matrix_test(</td><td class=PType nowrap>ee_u32 </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>N,</td></tr><tr><td></td><td class=PType nowrap>MATRES </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>C,</td></tr><tr><td></td><td class=PType nowrap>MATDAT </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>A,</td></tr><tr><td></td><td class=PType nowrap>MATDAT </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>B,</td></tr><tr><td></td><td class=PType nowrap>MATDAT </td><td class=PParameterPrefix nowrap></td><td class=PParameter nowrap>val</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Perform matrix manipulation.</div></div><div class=CToolTip id="tt47"><div class=CConfiguration>Defines method to get a block of memry.</div></div><div class=CToolTip id="tt48"><div class=CConfiguration>Define for parallel execution</div></div><!--END_ND_TOOLTIPS-->
+
+
+<!--START_ND_TOOLTIPS-->
+<div class=CToolTip id="tt49"><div class=CVariable>Use this flag to define how to to get an executable (e.g -o)</div></div><!--END_ND_TOOLTIPS-->
+
+
+<!--START_ND_TOOLTIPS-->
+<div class=CToolTip id="tt50"><div class=CVariable>Define perl executable to calculate the geomean if running separate.</div></div><div class=CToolTip id="tt51"><div class=CVariable>Port specific object files can be added here</div></div><div class=CToolTip id="tt52"><div class=CBuildTarget>Generate any files that are needed after actual build end. </div></div><div class=CToolTip id="tt53"><div class=CBuildTarget>Do platform specific after load stuff. </div></div><div class=CToolTip id="tt54"><div class=CBuildTarget>Do platform specific after run stuff. </div></div><div class=CToolTip id="tt55"><div class=CBuildTarget>Generate any files that are needed before actual build starts. </div></div><div class=CToolTip id="tt56"><div class=CBuildTarget>Do platform specific before load stuff. </div></div><div class=CToolTip id="tt57"><div class=CBuildTarget>Do platform specific after run stuff. </div></div><div class=CToolTip id="tt58"><div class=CVariable>Port specific source files can be added here</div></div><div class=CToolTip id="tt59"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>void portable_fini(</td><td class=PType nowrap>core_portable </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>p</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Target specific final code</div></div><div class=CToolTip id="tt60"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>void portable_free(</td><td class=PType nowrap>void </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>p</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Provide free() functionality in a platform specific way.</div></div><div class=CToolTip id="tt61"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>void portable_init(</td><td class=PType nowrap>core_portable </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>p,</td></tr><tr><td></td><td class=PType nowrap>int </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>argc,</td></tr><tr><td></td><td class=PType nowrap>char </td><td class=PParameterPrefix nowrap>*</td><td class=PParameter nowrap>argv[]</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Target specific initialization code Test for some common mistakes.</div></div><div class=CToolTip id="tt62"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>void *portable_malloc(</td><td class=PType nowrap>size_t </td><td class=PParameter nowrap>size</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Provide malloc() functionality in a platform specific way.</div></div><!--END_ND_TOOLTIPS-->
+
+
+<!--START_ND_TOOLTIPS-->
+<div class=CToolTip id="tt63"><div class=CFile>Version: 1.01</div></div><div class=CToolTip id="tt64"><div class=CGeneric>How to report results on a data sheet?</div></div><div class=CToolTip id="tt65"><div class=CVariable>Define this flag if running does not consist of simple invocation of the binary. </div></div><div class=CToolTip id="tt66"><div class=CGeneric>What is and is not allowed.</div></div><!--END_ND_TOOLTIPS-->
+
+</div><!--Index-->
+
+
+<div id=Footer><a href="http://www.naturaldocs.org">Copyright 2009 EEMBC</a></div><!--Footer-->
+
+
+<div id=Menu><div class=MTitle>CoreMark<div class=MSubTitle>(c) EEMBC</div></div><div class=MEntry><div class=MFile><a href="../files/readme-txt.html">CoreMark</a></div></div><div class=MEntry><div class=MFile><a href="../files/release_notes-txt.html">Release Notes</a></div></div><div class=MEntry><div class=MGroup><a href="javascript:ToggleMenu('MGroupContent2')">Source</a><div class=MGroupContent id=MGroupContent2><div class=MEntry><div class=MFile><a href="../files/core_list_join-c.html">core_list_join.c</a></div></div><div class=MEntry><div class=MFile><a href="../files/core_main-c.html">core_main.c</a></div></div><div class=MEntry><div class=MFile><a href="../files/core_matrix-c.html">core_matrix.c</a></div></div><div class=MEntry><div class=MFile><a href="../files/PIC32/core_portme-mak.html">core_portme.mak</a></div></div><div class=MEntry><div class=MFile><a href="../files/core_state-c.html">core_state.c</a></div></div><div class=MEntry><div class=MFile><a href="../files/core_util-c.html">core_util.c</a></div></div><div class=MEntry><div class=MFile><a href="../files/coremark-h.html">coremark.h</a></div></div><div class=MEntry><div class=MGroup><a href="javascript:ToggleMenu('MGroupContent1')">Porting</a><div class=MGroupContent id=MGroupContent1><div class=MEntry><div class=MFile><a href="../files/linux/core_portme-c.html">PORT_DIR/<span class=HB> </span>core_portme.c</a></div></div><div class=MEntry><div class=MFile><a href="../files/linux/core_portme-h.html">PORT_DIR/<span class=HB> </span>core_portme.h</a></div></div><div class=MEntry><div class=MFile><a href="../files/linux/core_portme-mak.html">PORT_DIR/<span class=HB> </span>core_portme.mak</a></div></div></div></div></div></div></div></div><div class=MEntry><div class=MGroup><a href="javascript:ToggleMenu('MGroupContent3')">Index</a><div class=MGroupContent id=MGroupContent3><div class=MEntry><div class=MIndex id=MSelected>Everything</div></div><div class=MEntry><div class=MIndex><a href="Files.html">Files</a></div></div><div class=MEntry><div class=MIndex><a href="Functions.html">Functions</a></div></div><div class=MEntry><div class=MIndex><a href="Types.html">Types</a></div></div><div class=MEntry><div class=MIndex><a href="Configuration.html">Configurations</a></div></div><div class=MEntry><div class=MIndex><a href="Variables.html">Variables</a></div></div><div class=MEntry><div class=MIndex><a href="BuildTargets.html">Build Targets</a></div></div></div></div></div><script type="text/javascript"><!--
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+<div id=MSearchResultsWindow><iframe src="" frameborder=0 name=MSearchResults id=MSearchResults></iframe><a href="javascript:searchPanel.CloseResultsWindow()" id=MSearchResultsWindowClose>Close</a></div>
+
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+<script language=JavaScript><!--
+if (browserType) {if (browserVer) {document.write("</div>"); }document.write("</div>");}// --></script></body></html>
\ No newline at end of file
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/index/General2.html b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/index/General2.html
new file mode 100644
index 0000000..3852ab5
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/index/General2.html
@@ -0,0 +1,47 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd">
+
+<html><head><title>Index - CoreMark</title><link rel="stylesheet" type="text/css" href="../styles/main.css"><script language=JavaScript src="../javascript/main.js"></script><script language=JavaScript src="../javascript/searchdata.js"></script></head><body class="IndexPage" onLoad="NDOnLoad()"><script language=JavaScript><!--
+if (browserType) {document.write("<div class=" + browserType + ">");if (browserVer) {document.write("<div class=" + browserVer + ">"); }}// --></script>
+
+<!-- Copyright 2009 EEMBC -->
+<!-- saved from url=(0026)http://www.naturaldocs.org -->
+
+
+
+
+<div id=Index><div class=IPageTitle>Index</div><div class=INavigationBar>$#! · 0-9 · A · <a href="General.html#B">B</a> · <a href="General.html#C">C</a> · <a href="General.html#D">D</a> · E · <a href="General.html#F">F</a> · <a href="General.html#G">G</a> · <a href="General.html#H">H</a> · <a href="General.html#I">I</a> · J · K · <a href="General.html#L">L</a> · <a href="General.html#M">M</a> · N · <a href="General.html#O">O</a> · <a href="General.html#P">P</a> · Q · <a href="General.html#R">R</a> · <a href="#S">S</a> · <a href="#T">T</a> · <a href="#U">U</a> · <a href="#V">V</a> · <a href="#W">W</a> · X · Y · Z</div><table border=0 cellspacing=0 cellpadding=0><tr><td class=IHeading id=IFirstHeading><a name="S"></a>S</td><td></td></tr><tr><td class=ISymbolPrefix id=IFirstSymbolPrefix> </td><td class=IEntry><a href="../files/coremark-h.html#secs_ret" id=link82 onMouseOver="ShowTip(event, 'tt67', 'link82')" onMouseOut="HideTip('tt67')" class=ISymbol>secs_ret</a></td></tr><tr><td class=ISymbolPrefix> </td><td class=IEntry><a href="../files/linux/core_portme-h.html#SEED_METHOD" id=link83 onMouseOver="ShowTip(event, 'tt68', 'link83')" onMouseOut="HideTip('tt68')" class=ISymbol>SEED_METHOD</a></td></tr><tr><td class=ISymbolPrefix> </td><td class=IEntry><span class=ISymbol>SEPARATE_COMPILE</span><div class=ISubIndex><a href="../files/linux/core_portme-mak.html#SEPARATE_COMPILE" id=link84 onMouseOver="ShowTip(event, 'tt69', 'link84')" onMouseOut="HideTip('tt69')" class=IFile>linux/<span class=HB> </span>core_portme.mak</a><a href="../files/PIC32/core_portme-mak.html#SEPARATE_COMPILE" id=link85 onMouseOver="ShowTip(event, 'tt69', 'link85')" onMouseOut="HideTip('tt69')" class=IFile>PIC32/<span class=HB> </span>core_portme.mak</a></div></td></tr><tr><td class=ISymbolPrefix> </td><td class=IEntry><a href="../files/linux/core_portme-c.html#start_time" id=link86 onMouseOver="ShowTip(event, 'tt70', 'link86')" onMouseOut="HideTip('tt70')" class=ISymbol>start_time</a></td></tr><tr><td class=ISymbolPrefix> </td><td class=IEntry><a href="../files/linux/core_portme-c.html#stop_time" id=link87 onMouseOver="ShowTip(event, 'tt71', 'link87')" onMouseOut="HideTip('tt71')" class=ISymbol>stop_time</a></td></tr><tr><td class=ISymbolPrefix id=ILastSymbolPrefix> </td><td class=IEntry><a href="../files/readme-txt.html#Submitting_results" id=link88 onMouseOver="ShowTip(event, 'tt72', 'link88')" onMouseOut="HideTip('tt72')" class=ISymbol>Submitting results</a></td></tr><tr><td class=IHeading><a name="T"></a>T</td><td></td></tr><tr><td class=ISymbolPrefix id=IFirstSymbolPrefix> </td><td class=IEntry><a href="../files/linux/core_portme-c.html#time_in_secs" id=link89 onMouseOver="ShowTip(event, 'tt73', 'link89')" onMouseOut="HideTip('tt73')" class=ISymbol>time_in_secs</a></td></tr><tr><td class=ISymbolPrefix> </td><td class=IEntry><a href="../files/linux/core_portme-c.html#TIMER_RES_DIVIDER" id=link90 onMouseOver="ShowTip(event, 'tt74', 'link90')" onMouseOut="HideTip('tt74')" class=ISymbol>TIMER_RES_DIVIDER</a></td></tr><tr><td class=ISymbolPrefix> </td><td class=IEntry><a href="../files/coremark-h.html#TOTAL_DATA_SIZE" id=link91 onMouseOver="ShowTip(event, 'tt75', 'link91')" onMouseOut="HideTip('tt75')" class=ISymbol>TOTAL_DATA_SIZE</a></td></tr><tr><td class=ISymbolPrefix id=ILastSymbolPrefix> </td><td class=IEntry><a href="../files/coremark-h.html#Types" class=ISymbol>Types</a></td></tr><tr><td class=IHeading><a name="U"></a>U</td><td></td></tr><tr><td class=ISymbolPrefix id=IFirstSymbolPrefix> </td><td class=IEntry><a href="../files/linux/core_portme-h.html#USE_CLOCK" id=link92 onMouseOver="ShowTip(event, 'tt76', 'link92')" onMouseOut="HideTip('tt76')" class=ISymbol>USE_CLOCK</a></td></tr><tr><td class=ISymbolPrefix> </td><td class=IEntry><a href="../files/linux/core_portme-h.html#USE_FORK" id=link93 onMouseOver="ShowTip(event, 'tt77', 'link93')" onMouseOut="HideTip('tt77')" class=ISymbol>USE_FORK</a></td></tr><tr><td class=ISymbolPrefix> </td><td class=IEntry><a href="../files/linux/core_portme-h.html#USE_PTHREAD" id=link94 onMouseOver="ShowTip(event, 'tt78', 'link94')" onMouseOut="HideTip('tt78')" class=ISymbol>USE_PTHREAD</a></td></tr><tr><td class=ISymbolPrefix id=ILastSymbolPrefix> </td><td class=IEntry><a href="../files/linux/core_portme-h.html#USE_SOCKET" id=link95 onMouseOver="ShowTip(event, 'tt79', 'link95')" onMouseOut="HideTip('tt79')" class=ISymbol>USE_SOCKET</a></td></tr><tr><td class=IHeading><a name="V"></a>V</td><td></td></tr><tr><td class=ISymbolPrefix id=IOnlySymbolPrefix> </td><td class=IEntry><span class=ISymbol>Variables</span><div class=ISubIndex><a href="../files/linux/core_portme-h.html#Variables" class=IFile>linux/<span class=HB> </span>core_portme.h</a><a href="../files/linux/core_portme-mak.html#Variables" class=IFile>linux/<span class=HB> </span>core_portme.mak</a><a href="../files/PIC32/core_portme-mak.html#Variables" class=IFile>PIC32/<span class=HB> </span>core_portme.mak</a></div></td></tr><tr><td class=IHeading><a name="W"></a>W</td><td></td></tr><tr><td class=ISymbolPrefix id=IOnlySymbolPrefix> </td><td class=IEntry><a href="../files/readme-txt.html#Welcome" id=link96 onMouseOver="ShowTip(event, 'tt80', 'link96')" onMouseOut="HideTip('tt80')" class=ISymbol>Welcome</a></td></tr></table>
+<!--START_ND_TOOLTIPS-->
+<div class=CToolTip id="tt67"><div class=CType>For machines that have floating point support, get number of seconds as a double. </div></div><div class=CToolTip id="tt68"><div class=CConfiguration>Defines method to get seed values that cannot be computed at compile time.</div></div><div class=CToolTip id="tt69"><div class=CVariable>Define if you need to separate compilation from link stage. </div></div><div class=CToolTip id="tt70"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>void start_time(</td><td class=PParameter nowrap>void</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>This function will be called right before starting the timed portion of the benchmark.</div></div><div class=CToolTip id="tt71"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>void stop_time(</td><td class=PParameter nowrap>void</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>This function will be called right after ending the timed portion of the benchmark.</div></div><div class=CToolTip id="tt72"><div class=CGeneric>CoreMark results can be submitted on the web.</div></div><!--END_ND_TOOLTIPS-->
+
+
+<!--START_ND_TOOLTIPS-->
+<div class=CToolTip id="tt73"><div class=CFunction><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td><table border=0 cellspacing=0 cellpadding=0><tr><td class=PBeforeParameters nowrap>secs_ret time_in_secs(</td><td class=PType nowrap>CORE_TICKS </td><td class=PParameter nowrap>ticks</td><td class=PAfterParameters nowrap>)</td></tr></table></td></tr></table></blockquote>Convert the value returned by get_time to seconds.</div></div><div class=CToolTip id="tt74"><div class=CGroup>Divider to trade off timer resolution and total time that can be measured.</div></div><div class=CToolTip id="tt75"><div class=CConfiguration>Define total size for data algorithms will operate on</div></div><!--END_ND_TOOLTIPS-->
+
+
+<!--START_ND_TOOLTIPS-->
+<div class=CToolTip id="tt76"><div class=CConfiguration>Define to 1 if platform has the time.h header file, and implementation of functions thereof.</div></div><div class=CToolTip id="tt77"><div class=CConfiguration>Sample implementation for launching parallel contexts This implementation uses fork, waitpid, shmget,shmat and shmdt.</div></div><div class=CToolTip id="tt78"><div class=CConfiguration>Sample implementation for launching parallel contexts This implementation uses pthread_thread_create and pthread_join.</div></div><div class=CToolTip id="tt79"><div class=CConfiguration>Sample implementation for launching parallel contexts This implementation uses fork, socket, sendto and recvfrom</div></div><!--END_ND_TOOLTIPS-->
+
+
+<!--START_ND_TOOLTIPS-->
+<!--END_ND_TOOLTIPS-->
+
+
+<!--START_ND_TOOLTIPS-->
+<div class=CToolTip id="tt80"><div class=CGeneric>Copyright © 2009 EEMBC All rights reserved. </div></div><!--END_ND_TOOLTIPS-->
+
+</div><!--Index-->
+
+
+<div id=Footer><a href="http://www.naturaldocs.org">Copyright 2009 EEMBC</a></div><!--Footer-->
+
+
+<div id=Menu><div class=MTitle>CoreMark<div class=MSubTitle>(c) EEMBC</div></div><div class=MEntry><div class=MFile><a href="../files/readme-txt.html">CoreMark</a></div></div><div class=MEntry><div class=MFile><a href="../files/release_notes-txt.html">Release Notes</a></div></div><div class=MEntry><div class=MGroup><a href="javascript:ToggleMenu('MGroupContent2')">Source</a><div class=MGroupContent id=MGroupContent2><div class=MEntry><div class=MFile><a href="../files/core_list_join-c.html">core_list_join.c</a></div></div><div class=MEntry><div class=MFile><a href="../files/core_main-c.html">core_main.c</a></div></div><div class=MEntry><div class=MFile><a href="../files/core_matrix-c.html">core_matrix.c</a></div></div><div class=MEntry><div class=MFile><a href="../files/PIC32/core_portme-mak.html">core_portme.mak</a></div></div><div class=MEntry><div class=MFile><a href="../files/core_state-c.html">core_state.c</a></div></div><div class=MEntry><div class=MFile><a href="../files/core_util-c.html">core_util.c</a></div></div><div class=MEntry><div class=MFile><a href="../files/coremark-h.html">coremark.h</a></div></div><div class=MEntry><div class=MGroup><a href="javascript:ToggleMenu('MGroupContent1')">Porting</a><div class=MGroupContent id=MGroupContent1><div class=MEntry><div class=MFile><a href="../files/linux/core_portme-c.html">PORT_DIR/<span class=HB> </span>core_portme.c</a></div></div><div class=MEntry><div class=MFile><a href="../files/linux/core_portme-h.html">PORT_DIR/<span class=HB> </span>core_portme.h</a></div></div><div class=MEntry><div class=MFile><a href="../files/linux/core_portme-mak.html">PORT_DIR/<span class=HB> </span>core_portme.mak</a></div></div></div></div></div></div></div></div><div class=MEntry><div class=MGroup><a href="javascript:ToggleMenu('MGroupContent3')">Index</a><div class=MGroupContent id=MGroupContent3><div class=MEntry><div class=MIndex id=MSelected>Everything</div></div><div class=MEntry><div class=MIndex><a href="Files.html">Files</a></div></div><div class=MEntry><div class=MIndex><a href="Functions.html">Functions</a></div></div><div class=MEntry><div class=MIndex><a href="Types.html">Types</a></div></div><div class=MEntry><div class=MIndex><a href="Configuration.html">Configurations</a></div></div><div class=MEntry><div class=MIndex><a href="Variables.html">Variables</a></div></div><div class=MEntry><div class=MIndex><a href="BuildTargets.html">Build Targets</a></div></div></div></div></div><script type="text/javascript"><!--
+var searchPanel = new SearchPanel("searchPanel", "HTML", "../search");
+--></script><div id=MSearchPanel class=MSearchPanelInactive><input type=text id=MSearchField value=Search onFocus="searchPanel.OnSearchFieldFocus(true)" onBlur="searchPanel.OnSearchFieldFocus(false)" onKeyUp="searchPanel.OnSearchFieldChange()"><select id=MSearchType onFocus="searchPanel.OnSearchTypeFocus(true)" onBlur="searchPanel.OnSearchTypeFocus(false)" onChange="searchPanel.OnSearchTypeChange()"><option id=MSearchEverything selected value="General">Everything</option><option value="BuildTargets">Build Targets</option><option value="Configuration">Configuration</option><option value="Files">Files</option><option value="Functions">Functions</option><option value="Types">Types</option><option value="Variables">Variables</option></select></div></div><!--Menu-->
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+<div id=MSearchResultsWindow><iframe src="" frameborder=0 name=MSearchResults id=MSearchResults></iframe><a href="javascript:searchPanel.CloseResultsWindow()" id=MSearchResultsWindowClose>Close</a></div>
+
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+<script language=JavaScript><!--
+if (browserType) {if (browserVer) {document.write("</div>"); }document.write("</div>");}// --></script></body></html>
\ No newline at end of file
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/index/Types.html b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/index/Types.html
new file mode 100644
index 0000000..1f44136
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/index/Types.html
@@ -0,0 +1,31 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd">
+
+<html><head><title>Type Index - CoreMark</title><link rel="stylesheet" type="text/css" href="../styles/main.css"><script language=JavaScript src="../javascript/main.js"></script><script language=JavaScript src="../javascript/searchdata.js"></script></head><body class="IndexPage" onLoad="NDOnLoad()"><script language=JavaScript><!--
+if (browserType) {document.write("<div class=" + browserType + ">");if (browserVer) {document.write("<div class=" + browserVer + ">"); }}// --></script>
+
+<!-- Copyright 2009 EEMBC -->
+<!-- saved from url=(0026)http://www.naturaldocs.org -->
+
+
+
+
+<div id=Index><div class=IPageTitle>Type Index</div><div class=INavigationBar>$#! · 0-9 · A · B · C · D · E · F · G · H · I · J · K · L · M · N · O · P · Q · R · <a href="#S">S</a> · T · U · V · W · X · Y · Z</div><table border=0 cellspacing=0 cellpadding=0><tr><td class=IHeading id=IFirstHeading><a name="S"></a>S</td><td></td></tr><tr><td class=ISymbolPrefix id=IOnlySymbolPrefix> </td><td class=IEntry><a href="../files/coremark-h.html#secs_ret" id=link1 onMouseOver="ShowTip(event, 'tt1', 'link1')" onMouseOut="HideTip('tt1')" class=ISymbol>secs_ret</a></td></tr></table>
+<!--START_ND_TOOLTIPS-->
+<div class=CToolTip id="tt1"><div class=CType>For machines that have floating point support, get number of seconds as a double. </div></div><!--END_ND_TOOLTIPS-->
+
+</div><!--Index-->
+
+
+<div id=Footer><a href="http://www.naturaldocs.org">Copyright 2009 EEMBC</a></div><!--Footer-->
+
+
+<div id=Menu><div class=MTitle>CoreMark<div class=MSubTitle>(c) EEMBC</div></div><div class=MEntry><div class=MFile><a href="../files/readme-txt.html">CoreMark</a></div></div><div class=MEntry><div class=MFile><a href="../files/release_notes-txt.html">Release Notes</a></div></div><div class=MEntry><div class=MGroup><a href="javascript:ToggleMenu('MGroupContent2')">Source</a><div class=MGroupContent id=MGroupContent2><div class=MEntry><div class=MFile><a href="../files/core_list_join-c.html">core_list_join.c</a></div></div><div class=MEntry><div class=MFile><a href="../files/core_main-c.html">core_main.c</a></div></div><div class=MEntry><div class=MFile><a href="../files/core_matrix-c.html">core_matrix.c</a></div></div><div class=MEntry><div class=MFile><a href="../files/PIC32/core_portme-mak.html">core_portme.mak</a></div></div><div class=MEntry><div class=MFile><a href="../files/core_state-c.html">core_state.c</a></div></div><div class=MEntry><div class=MFile><a href="../files/core_util-c.html">core_util.c</a></div></div><div class=MEntry><div class=MFile><a href="../files/coremark-h.html">coremark.h</a></div></div><div class=MEntry><div class=MGroup><a href="javascript:ToggleMenu('MGroupContent1')">Porting</a><div class=MGroupContent id=MGroupContent1><div class=MEntry><div class=MFile><a href="../files/linux/core_portme-c.html">PORT_DIR/<span class=HB> </span>core_portme.c</a></div></div><div class=MEntry><div class=MFile><a href="../files/linux/core_portme-h.html">PORT_DIR/<span class=HB> </span>core_portme.h</a></div></div><div class=MEntry><div class=MFile><a href="../files/linux/core_portme-mak.html">PORT_DIR/<span class=HB> </span>core_portme.mak</a></div></div></div></div></div></div></div></div><div class=MEntry><div class=MGroup><a href="javascript:ToggleMenu('MGroupContent3')">Index</a><div class=MGroupContent id=MGroupContent3><div class=MEntry><div class=MIndex><a href="General.html">Everything</a></div></div><div class=MEntry><div class=MIndex><a href="Files.html">Files</a></div></div><div class=MEntry><div class=MIndex><a href="Functions.html">Functions</a></div></div><div class=MEntry><div class=MIndex id=MSelected>Types</div></div><div class=MEntry><div class=MIndex><a href="Configuration.html">Configurations</a></div></div><div class=MEntry><div class=MIndex><a href="Variables.html">Variables</a></div></div><div class=MEntry><div class=MIndex><a href="BuildTargets.html">Build Targets</a></div></div></div></div></div><script type="text/javascript"><!--
+var searchPanel = new SearchPanel("searchPanel", "HTML", "../search");
+--></script><div id=MSearchPanel class=MSearchPanelInactive><input type=text id=MSearchField value=Search onFocus="searchPanel.OnSearchFieldFocus(true)" onBlur="searchPanel.OnSearchFieldFocus(false)" onKeyUp="searchPanel.OnSearchFieldChange()"><select id=MSearchType onFocus="searchPanel.OnSearchTypeFocus(true)" onBlur="searchPanel.OnSearchTypeFocus(false)" onChange="searchPanel.OnSearchTypeChange()"><option id=MSearchEverything selected value="General">Everything</option><option value="BuildTargets">Build Targets</option><option value="Configuration">Configuration</option><option value="Files">Files</option><option value="Functions">Functions</option><option value="Types">Types</option><option value="Variables">Variables</option></select></div></div><!--Menu-->
+
+
+<div id=MSearchResultsWindow><iframe src="" frameborder=0 name=MSearchResults id=MSearchResults></iframe><a href="javascript:searchPanel.CloseResultsWindow()" id=MSearchResultsWindowClose>Close</a></div>
+
+
+<script language=JavaScript><!--
+if (browserType) {if (browserVer) {document.write("</div>"); }document.write("</div>");}// --></script></body></html>
\ No newline at end of file
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/index/Variables.html b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/index/Variables.html
new file mode 100644
index 0000000..8c050da
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/index/Variables.html
@@ -0,0 +1,55 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd">
+
+<html><head><title>Variable Index - CoreMark</title><link rel="stylesheet" type="text/css" href="../styles/main.css"><script language=JavaScript src="../javascript/main.js"></script><script language=JavaScript src="../javascript/searchdata.js"></script></head><body class="IndexPage" onLoad="NDOnLoad()"><script language=JavaScript><!--
+if (browserType) {document.write("<div class=" + browserType + ">");if (browserVer) {document.write("<div class=" + browserVer + ">"); }}// --></script>
+
+<!-- Copyright 2009 EEMBC -->
+<!-- saved from url=(0026)http://www.naturaldocs.org -->
+
+
+
+
+<div id=Index><div class=IPageTitle>Variable Index</div><div class=INavigationBar>$#! · 0-9 · A · B · <a href="#C">C</a> · <a href="#D">D</a> · E · F · G · H · I · J · K · <a href="#L">L</a> · M · N · <a href="#O">O</a> · <a href="#P">P</a> · Q · <a href="#R">R</a> · <a href="#S">S</a> · T · U · V · W · X · Y · Z</div><table border=0 cellspacing=0 cellpadding=0><tr><td class=IHeading id=IFirstHeading><a name="C"></a>C</td><td></td></tr><tr><td class=ISymbolPrefix id=IFirstSymbolPrefix> </td><td class=IEntry><a href="../files/linux/core_portme-mak.html#CC" id=link1 onMouseOver="ShowTip(event, 'tt1', 'link1')" onMouseOut="HideTip('tt1')" class=ISymbol>CC</a></td></tr><tr><td class=ISymbolPrefix id=ILastSymbolPrefix> </td><td class=IEntry><span class=ISymbol>CFLAGS</span><div class=ISubIndex><a href="../files/linux/core_portme-mak.html#CFLAGS" id=link2 onMouseOver="ShowTip(event, 'tt2', 'link2')" onMouseOut="HideTip('tt2')" class=IFile>linux/<span class=HB> </span>core_portme.mak</a><a href="../files/PIC32/core_portme-mak.html#CFLAGS" id=link3 onMouseOver="ShowTip(event, 'tt2', 'link3')" onMouseOut="HideTip('tt2')" class=IFile>PIC32/<span class=HB> </span>core_portme.mak</a></div></td></tr><tr><td class=IHeading><a name="D"></a>D</td><td></td></tr><tr><td class=ISymbolPrefix id=IOnlySymbolPrefix> </td><td class=IEntry><a href="../files/linux/core_portme-h.html#default_num_contexts" id=link4 onMouseOver="ShowTip(event, 'tt3', 'link4')" onMouseOut="HideTip('tt3')" class=ISymbol>default_num_contexts</a></td></tr><tr><td class=IHeading><a name="L"></a>L</td><td></td></tr><tr><td class=ISymbolPrefix id=IFirstSymbolPrefix> </td><td class=IEntry><span class=ISymbol>LFLAGS_END</span><div class=ISubIndex><a href="../files/linux/core_portme-mak.html#LFLAGS_END" id=link5 onMouseOver="ShowTip(event, 'tt4', 'link5')" onMouseOut="HideTip('tt4')" class=IFile>linux/<span class=HB> </span>core_portme.mak</a><a href="../files/PIC32/core_portme-mak.html#LFLAGS_END" id=link6 onMouseOver="ShowTip(event, 'tt4', 'link6')" onMouseOut="HideTip('tt4')" class=IFile>PIC32/<span class=HB> </span>core_portme.mak</a></div></td></tr><tr><td class=ISymbolPrefix id=ILastSymbolPrefix> </td><td class=IEntry><a href="../files/linux/core_portme-mak.html#LOAD" id=link7 onMouseOver="ShowTip(event, 'tt5', 'link7')" onMouseOut="HideTip('tt5')" class=ISymbol>LOAD</a></td></tr><tr><td class=IHeading><a name="O"></a>O</td><td></td></tr><tr><td class=ISymbolPrefix id=IFirstSymbolPrefix> </td><td class=IEntry><span class=ISymbol>OPATH</span><div class=ISubIndex><a href="../files/linux/core_portme-mak.html#OPATH" class=IFile>linux/<span class=HB> </span>core_portme.mak</a><a href="../files/PIC32/core_portme-mak.html#OPATH" class=IFile>PIC32/<span class=HB> </span>core_portme.mak</a></div></td></tr><tr><td class=ISymbolPrefix id=ILastSymbolPrefix> </td><td class=IEntry><span class=ISymbol>OUTFLAG</span><div class=ISubIndex><a href="../files/linux/core_portme-mak.html#OUTFLAG" id=link8 onMouseOver="ShowTip(event, 'tt6', 'link8')" onMouseOut="HideTip('tt6')" class=IFile>linux/<span class=HB> </span>core_portme.mak</a><a href="../files/PIC32/core_portme-mak.html#OUTFLAG" id=link9 onMouseOver="ShowTip(event, 'tt6', 'link9')" onMouseOut="HideTip('tt6')" class=IFile>PIC32/<span class=HB> </span>core_portme.mak</a></div></td></tr><tr><td class=IHeading><a name="P"></a>P</td><td></td></tr><tr><td class=ISymbolPrefix id=IFirstSymbolPrefix> </td><td class=IEntry><span class=ISymbol>PERL</span><div class=ISubIndex><a href="../files/linux/core_portme-mak.html#PERL" id=link10 onMouseOver="ShowTip(event, 'tt7', 'link10')" onMouseOut="HideTip('tt7')" class=IFile>linux/<span class=HB> </span>core_portme.mak</a><a href="../files/PIC32/core_portme-mak.html#PERL" id=link11 onMouseOver="ShowTip(event, 'tt7', 'link11')" onMouseOut="HideTip('tt7')" class=IFile>PIC32/<span class=HB> </span>core_portme.mak</a></div></td></tr><tr><td class=ISymbolPrefix> </td><td class=IEntry><span class=ISymbol>PORT_OBJS</span><div class=ISubIndex><a href="../files/linux/core_portme-mak.html#PORT_OBJS" id=link12 onMouseOver="ShowTip(event, 'tt8', 'link12')" onMouseOut="HideTip('tt8')" class=IFile>linux/<span class=HB> </span>core_portme.mak</a><a href="../files/PIC32/core_portme-mak.html#PORT_OBJS" id=link13 onMouseOver="ShowTip(event, 'tt8', 'link13')" onMouseOut="HideTip('tt8')" class=IFile>PIC32/<span class=HB> </span>core_portme.mak</a></div></td></tr><tr><td class=ISymbolPrefix id=ILastSymbolPrefix> </td><td class=IEntry><a href="../files/linux/core_portme-mak.html#PORT_SRCS" id=link14 onMouseOver="ShowTip(event, 'tt9', 'link14')" onMouseOut="HideTip('tt9')" class=ISymbol>PORT_SRCS</a></td></tr><tr><td class=IHeading><a name="R"></a>R</td><td></td></tr><tr><td class=ISymbolPrefix id=IOnlySymbolPrefix> </td><td class=IEntry><a href="../files/linux/core_portme-mak.html#RUN" id=link15 onMouseOver="ShowTip(event, 'tt10', 'link15')" onMouseOut="HideTip('tt10')" class=ISymbol>RUN</a></td></tr><tr><td class=IHeading><a name="S"></a>S</td><td></td></tr><tr><td class=ISymbolPrefix id=IOnlySymbolPrefix> </td><td class=IEntry><span class=ISymbol>SEPARATE_COMPILE</span><div class=ISubIndex><a href="../files/linux/core_portme-mak.html#SEPARATE_COMPILE" id=link16 onMouseOver="ShowTip(event, 'tt11', 'link16')" onMouseOut="HideTip('tt11')" class=IFile>linux/<span class=HB> </span>core_portme.mak</a><a href="../files/PIC32/core_portme-mak.html#SEPARATE_COMPILE" id=link17 onMouseOver="ShowTip(event, 'tt11', 'link17')" onMouseOut="HideTip('tt11')" class=IFile>PIC32/<span class=HB> </span>core_portme.mak</a></div></td></tr></table>
+<!--START_ND_TOOLTIPS-->
+<div class=CToolTip id="tt1"><div class=CVariable>Use this flag to define compiler to use</div></div><div class=CToolTip id="tt2"><div class=CVariable>Use this flag to define compiler options. </div></div><!--END_ND_TOOLTIPS-->
+
+
+<!--START_ND_TOOLTIPS-->
+<div class=CToolTip id="tt3"><div class=CVariable><blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td>extern ee_u32 default_num_contexts</td></tr></table></blockquote>Number of contexts to spawn in multicore context. </div></div><!--END_ND_TOOLTIPS-->
+
+
+<!--START_ND_TOOLTIPS-->
+<div class=CToolTip id="tt4"><div class=CVariable>Define any libraries needed for linking or other flags that should come at the end of the link line (e.g. </div></div><div class=CToolTip id="tt5"><div class=CVariable>Define this flag if you need to load to a target, as in a cross compile environment.</div></div><!--END_ND_TOOLTIPS-->
+
+
+<!--START_ND_TOOLTIPS-->
+<div class=CToolTip id="tt6"><div class=CVariable>Use this flag to define how to to get an executable (e.g -o)</div></div><!--END_ND_TOOLTIPS-->
+
+
+<!--START_ND_TOOLTIPS-->
+<div class=CToolTip id="tt7"><div class=CVariable>Define perl executable to calculate the geomean if running separate.</div></div><div class=CToolTip id="tt8"><div class=CVariable>Port specific object files can be added here</div></div><div class=CToolTip id="tt9"><div class=CVariable>Port specific source files can be added here</div></div><!--END_ND_TOOLTIPS-->
+
+
+<!--START_ND_TOOLTIPS-->
+<div class=CToolTip id="tt10"><div class=CVariable>Define this flag if running does not consist of simple invocation of the binary. </div></div><!--END_ND_TOOLTIPS-->
+
+
+<!--START_ND_TOOLTIPS-->
+<div class=CToolTip id="tt11"><div class=CVariable>Define if you need to separate compilation from link stage. </div></div><!--END_ND_TOOLTIPS-->
+
+</div><!--Index-->
+
+
+<div id=Footer><a href="http://www.naturaldocs.org">Copyright 2009 EEMBC</a></div><!--Footer-->
+
+
+<div id=Menu><div class=MTitle>CoreMark<div class=MSubTitle>(c) EEMBC</div></div><div class=MEntry><div class=MFile><a href="../files/readme-txt.html">CoreMark</a></div></div><div class=MEntry><div class=MFile><a href="../files/release_notes-txt.html">Release Notes</a></div></div><div class=MEntry><div class=MGroup><a href="javascript:ToggleMenu('MGroupContent2')">Source</a><div class=MGroupContent id=MGroupContent2><div class=MEntry><div class=MFile><a href="../files/core_list_join-c.html">core_list_join.c</a></div></div><div class=MEntry><div class=MFile><a href="../files/core_main-c.html">core_main.c</a></div></div><div class=MEntry><div class=MFile><a href="../files/core_matrix-c.html">core_matrix.c</a></div></div><div class=MEntry><div class=MFile><a href="../files/PIC32/core_portme-mak.html">core_portme.mak</a></div></div><div class=MEntry><div class=MFile><a href="../files/core_state-c.html">core_state.c</a></div></div><div class=MEntry><div class=MFile><a href="../files/core_util-c.html">core_util.c</a></div></div><div class=MEntry><div class=MFile><a href="../files/coremark-h.html">coremark.h</a></div></div><div class=MEntry><div class=MGroup><a href="javascript:ToggleMenu('MGroupContent1')">Porting</a><div class=MGroupContent id=MGroupContent1><div class=MEntry><div class=MFile><a href="../files/linux/core_portme-c.html">PORT_DIR/<span class=HB> </span>core_portme.c</a></div></div><div class=MEntry><div class=MFile><a href="../files/linux/core_portme-h.html">PORT_DIR/<span class=HB> </span>core_portme.h</a></div></div><div class=MEntry><div class=MFile><a href="../files/linux/core_portme-mak.html">PORT_DIR/<span class=HB> </span>core_portme.mak</a></div></div></div></div></div></div></div></div><div class=MEntry><div class=MGroup><a href="javascript:ToggleMenu('MGroupContent3')">Index</a><div class=MGroupContent id=MGroupContent3><div class=MEntry><div class=MIndex><a href="General.html">Everything</a></div></div><div class=MEntry><div class=MIndex><a href="Files.html">Files</a></div></div><div class=MEntry><div class=MIndex><a href="Functions.html">Functions</a></div></div><div class=MEntry><div class=MIndex><a href="Types.html">Types</a></div></div><div class=MEntry><div class=MIndex><a href="Configuration.html">Configurations</a></div></div><div class=MEntry><div class=MIndex id=MSelected>Variables</div></div><div class=MEntry><div class=MIndex><a href="BuildTargets.html">Build Targets</a></div></div></div></div></div><script type="text/javascript"><!--
+var searchPanel = new SearchPanel("searchPanel", "HTML", "../search");
+--></script><div id=MSearchPanel class=MSearchPanelInactive><input type=text id=MSearchField value=Search onFocus="searchPanel.OnSearchFieldFocus(true)" onBlur="searchPanel.OnSearchFieldFocus(false)" onKeyUp="searchPanel.OnSearchFieldChange()"><select id=MSearchType onFocus="searchPanel.OnSearchTypeFocus(true)" onBlur="searchPanel.OnSearchTypeFocus(false)" onChange="searchPanel.OnSearchTypeChange()"><option id=MSearchEverything selected value="General">Everything</option><option value="BuildTargets">Build Targets</option><option value="Configuration">Configuration</option><option value="Files">Files</option><option value="Functions">Functions</option><option value="Types">Types</option><option value="Variables">Variables</option></select></div></div><!--Menu-->
+
+
+<div id=MSearchResultsWindow><iframe src="" frameborder=0 name=MSearchResults id=MSearchResults></iframe><a href="javascript:searchPanel.CloseResultsWindow()" id=MSearchResultsWindowClose>Close</a></div>
+
+
+<script language=JavaScript><!--
+if (browserType) {if (browserVer) {document.write("</div>"); }document.write("</div>");}// --></script></body></html>
\ No newline at end of file
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/javascript/main.js b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/javascript/main.js
new file mode 100644
index 0000000..91991f5
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/javascript/main.js
@@ -0,0 +1,836 @@
+// This file is part of Natural Docs, which is Copyright (C) 2003-2008 Greg Valure
+// Natural Docs is licensed under the GPL
+
+
+//
+// Browser Styles
+// ____________________________________________________________________________
+
+var agt=navigator.userAgent.toLowerCase();
+var browserType;
+var browserVer;
+
+if (agt.indexOf("opera") != -1)
+ {
+ browserType = "Opera";
+
+ if (agt.indexOf("opera 7") != -1 || agt.indexOf("opera/7") != -1)
+ { browserVer = "Opera7"; }
+ else if (agt.indexOf("opera 8") != -1 || agt.indexOf("opera/8") != -1)
+ { browserVer = "Opera8"; }
+ else if (agt.indexOf("opera 9") != -1 || agt.indexOf("opera/9") != -1)
+ { browserVer = "Opera9"; }
+ }
+
+else if (agt.indexOf("applewebkit") != -1)
+ {
+ browserType = "Safari";
+
+ if (agt.indexOf("version/3") != -1)
+ { browserVer = "Safari3"; }
+ else if (agt.indexOf("safari/4") != -1)
+ { browserVer = "Safari2"; }
+ }
+
+else if (agt.indexOf("khtml") != -1)
+ {
+ browserType = "Konqueror";
+ }
+
+else if (agt.indexOf("msie") != -1)
+ {
+ browserType = "IE";
+
+ if (agt.indexOf("msie 6") != -1)
+ { browserVer = "IE6"; }
+ else if (agt.indexOf("msie 7") != -1)
+ { browserVer = "IE7"; }
+ }
+
+else if (agt.indexOf("gecko") != -1)
+ {
+ browserType = "Firefox";
+
+ if (agt.indexOf("rv:1.7") != -1)
+ { browserVer = "Firefox1"; }
+ else if (agt.indexOf("rv:1.8)") != -1 || agt.indexOf("rv:1.8.0") != -1)
+ { browserVer = "Firefox15"; }
+ else if (agt.indexOf("rv:1.8.1") != -1)
+ { browserVer = "Firefox2"; }
+ }
+
+
+//
+// Support Functions
+// ____________________________________________________________________________
+
+
+function GetXPosition(item)
+ {
+ var position = 0;
+
+ if (item.offsetWidth != null)
+ {
+ while (item != document.body && item != null)
+ {
+ position += item.offsetLeft;
+ item = item.offsetParent;
+ };
+ };
+
+ return position;
+ };
+
+
+function GetYPosition(item)
+ {
+ var position = 0;
+
+ if (item.offsetWidth != null)
+ {
+ while (item != document.body && item != null)
+ {
+ position += item.offsetTop;
+ item = item.offsetParent;
+ };
+ };
+
+ return position;
+ };
+
+
+function MoveToPosition(item, x, y)
+ {
+ // Opera 5 chokes on the px extension, so it can use the Microsoft one instead.
+
+ if (item.style.left != null)
+ {
+ item.style.left = x + "px";
+ item.style.top = y + "px";
+ }
+ else if (item.style.pixelLeft != null)
+ {
+ item.style.pixelLeft = x;
+ item.style.pixelTop = y;
+ };
+ };
+
+
+//
+// Menu
+// ____________________________________________________________________________
+
+
+function ToggleMenu(id)
+ {
+ if (!window.document.getElementById)
+ { return; };
+
+ var display = window.document.getElementById(id).style.display;
+
+ if (display == "none")
+ { display = "block"; }
+ else
+ { display = "none"; }
+
+ window.document.getElementById(id).style.display = display;
+ }
+
+function HideAllBut(ids, max)
+ {
+ if (document.getElementById)
+ {
+ ids.sort( function(a,b) { return a - b; } );
+ var number = 1;
+
+ while (number < max)
+ {
+ if (ids.length > 0 && number == ids[0])
+ { ids.shift(); }
+ else
+ {
+ document.getElementById("MGroupContent" + number).style.display = "none";
+ };
+
+ number++;
+ };
+ };
+ }
+
+
+//
+// Tooltips
+// ____________________________________________________________________________
+
+
+var tooltipTimer = 0;
+
+function ShowTip(event, tooltipID, linkID)
+ {
+ if (tooltipTimer)
+ { clearTimeout(tooltipTimer); };
+
+ var docX = event.clientX + window.pageXOffset;
+ var docY = event.clientY + window.pageYOffset;
+
+ var showCommand = "ReallyShowTip('" + tooltipID + "', '" + linkID + "', " + docX + ", " + docY + ")";
+
+ tooltipTimer = setTimeout(showCommand, 1000);
+ }
+
+function ReallyShowTip(tooltipID, linkID, docX, docY)
+ {
+ tooltipTimer = 0;
+
+ var tooltip;
+ var link;
+
+ if (document.getElementById)
+ {
+ tooltip = document.getElementById(tooltipID);
+ link = document.getElementById(linkID);
+ }
+/* else if (document.all)
+ {
+ tooltip = eval("document.all['" + tooltipID + "']");
+ link = eval("document.all['" + linkID + "']");
+ }
+*/
+ if (tooltip)
+ {
+ var left = GetXPosition(link);
+ var top = GetYPosition(link);
+ top += link.offsetHeight;
+
+
+ // The fallback method is to use the mouse X and Y relative to the document. We use a separate if and test if its a number
+ // in case some browser snuck through the above if statement but didn't support everything.
+
+ if (!isFinite(top) || top == 0)
+ {
+ left = docX;
+ top = docY;
+ }
+
+ // Some spacing to get it out from under the cursor.
+
+ top += 10;
+
+ // Make sure the tooltip doesnt get smushed by being too close to the edge, or in some browsers, go off the edge of the
+ // page. We do it here because Konqueror does get offsetWidth right even if it doesnt get the positioning right.
+
+ if (tooltip.offsetWidth != null)
+ {
+ var width = tooltip.offsetWidth;
+ var docWidth = document.body.clientWidth;
+
+ if (left + width > docWidth)
+ { left = docWidth - width - 1; }
+
+ // If there's a horizontal scroll bar we could go past zero because it's using the page width, not the window width.
+ if (left < 0)
+ { left = 0; };
+ }
+
+ MoveToPosition(tooltip, left, top);
+ tooltip.style.visibility = "visible";
+ }
+ }
+
+function HideTip(tooltipID)
+ {
+ if (tooltipTimer)
+ {
+ clearTimeout(tooltipTimer);
+ tooltipTimer = 0;
+ }
+
+ var tooltip;
+
+ if (document.getElementById)
+ { tooltip = document.getElementById(tooltipID); }
+ else if (document.all)
+ { tooltip = eval("document.all['" + tooltipID + "']"); }
+
+ if (tooltip)
+ { tooltip.style.visibility = "hidden"; }
+ }
+
+
+//
+// Blockquote fix for IE
+// ____________________________________________________________________________
+
+
+function NDOnLoad()
+ {
+ if (browserVer == "IE6")
+ {
+ var scrollboxes = document.getElementsByTagName('blockquote');
+
+ if (scrollboxes.item(0))
+ {
+ NDDoResize();
+ window.onresize=NDOnResize;
+ };
+ };
+ };
+
+
+var resizeTimer = 0;
+
+function NDOnResize()
+ {
+ if (resizeTimer != 0)
+ { clearTimeout(resizeTimer); };
+
+ resizeTimer = setTimeout(NDDoResize, 250);
+ };
+
+
+function NDDoResize()
+ {
+ var scrollboxes = document.getElementsByTagName('blockquote');
+
+ var i;
+ var item;
+
+ i = 0;
+ while (item = scrollboxes.item(i))
+ {
+ item.style.width = 100;
+ i++;
+ };
+
+ i = 0;
+ while (item = scrollboxes.item(i))
+ {
+ item.style.width = item.parentNode.offsetWidth;
+ i++;
+ };
+
+ clearTimeout(resizeTimer);
+ resizeTimer = 0;
+ }
+
+
+
+/* ________________________________________________________________________________________________________
+
+ Class: SearchPanel
+ ________________________________________________________________________________________________________
+
+ A class handling everything associated with the search panel.
+
+ Parameters:
+
+ name - The name of the global variable that will be storing this instance. Is needed to be able to set timeouts.
+ mode - The mode the search is going to work in. Pass <NaturalDocs::Builder::Base->CommandLineOption()>, so the
+ value will be something like "HTML" or "FramedHTML".
+
+ ________________________________________________________________________________________________________
+*/
+
+
+function SearchPanel(name, mode, resultsPath)
+ {
+ if (!name || !mode || !resultsPath)
+ { alert("Incorrect parameters to SearchPanel."); };
+
+
+ // Group: Variables
+ // ________________________________________________________________________
+
+ /*
+ var: name
+ The name of the global variable that will be storing this instance of the class.
+ */
+ this.name = name;
+
+ /*
+ var: mode
+ The mode the search is going to work in, such as "HTML" or "FramedHTML".
+ */
+ this.mode = mode;
+
+ /*
+ var: resultsPath
+ The relative path from the current HTML page to the results page directory.
+ */
+ this.resultsPath = resultsPath;
+
+ /*
+ var: keyTimeout
+ The timeout used between a keystroke and when a search is performed.
+ */
+ this.keyTimeout = 0;
+
+ /*
+ var: keyTimeoutLength
+ The length of <keyTimeout> in thousandths of a second.
+ */
+ this.keyTimeoutLength = 500;
+
+ /*
+ var: lastSearchValue
+ The last search string executed, or an empty string if none.
+ */
+ this.lastSearchValue = "";
+
+ /*
+ var: lastResultsPage
+ The last results page. The value is only relevant if <lastSearchValue> is set.
+ */
+ this.lastResultsPage = "";
+
+ /*
+ var: deactivateTimeout
+
+ The timeout used between when a control is deactivated and when the entire panel is deactivated. Is necessary
+ because a control may be deactivated in favor of another control in the same panel, in which case it should stay
+ active.
+ */
+ this.deactivateTimout = 0;
+
+ /*
+ var: deactivateTimeoutLength
+ The length of <deactivateTimeout> in thousandths of a second.
+ */
+ this.deactivateTimeoutLength = 200;
+
+
+
+
+ // Group: DOM Elements
+ // ________________________________________________________________________
+
+
+ // Function: DOMSearchField
+ this.DOMSearchField = function()
+ { return document.getElementById("MSearchField"); };
+
+ // Function: DOMSearchType
+ this.DOMSearchType = function()
+ { return document.getElementById("MSearchType"); };
+
+ // Function: DOMPopupSearchResults
+ this.DOMPopupSearchResults = function()
+ { return document.getElementById("MSearchResults"); };
+
+ // Function: DOMPopupSearchResultsWindow
+ this.DOMPopupSearchResultsWindow = function()
+ { return document.getElementById("MSearchResultsWindow"); };
+
+ // Function: DOMSearchPanel
+ this.DOMSearchPanel = function()
+ { return document.getElementById("MSearchPanel"); };
+
+
+
+
+ // Group: Event Handlers
+ // ________________________________________________________________________
+
+
+ /*
+ Function: OnSearchFieldFocus
+ Called when focus is added or removed from the search field.
+ */
+ this.OnSearchFieldFocus = function(isActive)
+ {
+ this.Activate(isActive);
+ };
+
+
+ /*
+ Function: OnSearchFieldChange
+ Called when the content of the search field is changed.
+ */
+ this.OnSearchFieldChange = function()
+ {
+ if (this.keyTimeout)
+ {
+ clearTimeout(this.keyTimeout);
+ this.keyTimeout = 0;
+ };
+
+ var searchValue = this.DOMSearchField().value.replace(/ +/g, "");
+
+ if (searchValue != this.lastSearchValue)
+ {
+ if (searchValue != "")
+ {
+ this.keyTimeout = setTimeout(this.name + ".Search()", this.keyTimeoutLength);
+ }
+ else
+ {
+ if (this.mode == "HTML")
+ { this.DOMPopupSearchResultsWindow().style.display = "none"; };
+ this.lastSearchValue = "";
+ };
+ };
+ };
+
+
+ /*
+ Function: OnSearchTypeFocus
+ Called when focus is added or removed from the search type.
+ */
+ this.OnSearchTypeFocus = function(isActive)
+ {
+ this.Activate(isActive);
+ };
+
+
+ /*
+ Function: OnSearchTypeChange
+ Called when the search type is changed.
+ */
+ this.OnSearchTypeChange = function()
+ {
+ var searchValue = this.DOMSearchField().value.replace(/ +/g, "");
+
+ if (searchValue != "")
+ {
+ this.Search();
+ };
+ };
+
+
+
+ // Group: Action Functions
+ // ________________________________________________________________________
+
+
+ /*
+ Function: CloseResultsWindow
+ Closes the results window.
+ */
+ this.CloseResultsWindow = function()
+ {
+ this.DOMPopupSearchResultsWindow().style.display = "none";
+ this.Activate(false, true);
+ };
+
+
+ /*
+ Function: Search
+ Performs a search.
+ */
+ this.Search = function()
+ {
+ this.keyTimeout = 0;
+
+ var searchValue = this.DOMSearchField().value.replace(/^ +/, "");
+ var searchTopic = this.DOMSearchType().value;
+
+ var pageExtension = searchValue.substr(0,1);
+
+ if (pageExtension.match(/^[a-z]/i))
+ { pageExtension = pageExtension.toUpperCase(); }
+ else if (pageExtension.match(/^[0-9]/))
+ { pageExtension = 'Numbers'; }
+ else
+ { pageExtension = "Symbols"; };
+
+ var resultsPage;
+ var resultsPageWithSearch;
+ var hasResultsPage;
+
+ // indexSectionsWithContent is defined in searchdata.js
+ if (indexSectionsWithContent[searchTopic][pageExtension] == true)
+ {
+ resultsPage = this.resultsPath + '/' + searchTopic + pageExtension + '.html';
+ resultsPageWithSearch = resultsPage+'?'+escape(searchValue);
+ hasResultsPage = true;
+ }
+ else
+ {
+ resultsPage = this.resultsPath + '/NoResults.html';
+ resultsPageWithSearch = resultsPage;
+ hasResultsPage = false;
+ };
+
+ var resultsFrame;
+ if (this.mode == "HTML")
+ { resultsFrame = window.frames.MSearchResults; }
+ else if (this.mode == "FramedHTML")
+ { resultsFrame = window.top.frames['Content']; };
+
+
+ if (resultsPage != this.lastResultsPage ||
+
+ // Bug in IE. If everything becomes hidden in a run, none of them will be able to be reshown in the next for some
+ // reason. It counts the right number of results, and you can even read the display as "block" after setting it, but it
+ // just doesn't work in IE 6 or IE 7. So if we're on the right page but the previous search had no results, reload the
+ // page anyway to get around the bug.
+ (browserType == "IE" && hasResultsPage &&
+ (!resultsFrame.searchResults || resultsFrame.searchResults.lastMatchCount == 0)) )
+
+ {
+ resultsFrame.location.href = resultsPageWithSearch;
+ }
+
+ // So if the results page is right and there's no IE bug, reperform the search on the existing page. We have to check if there
+ // are results because NoResults.html doesn't have any JavaScript, and it would be useless to do anything on that page even
+ // if it did.
+ else if (hasResultsPage)
+ {
+ // We need to check if this exists in case the frame is present but didn't finish loading.
+ if (resultsFrame.searchResults)
+ { resultsFrame.searchResults.Search(searchValue); }
+
+ // Otherwise just reload instead of waiting.
+ else
+ { resultsFrame.location.href = resultsPageWithSearch; };
+ };
+
+
+ var domPopupSearchResultsWindow = this.DOMPopupSearchResultsWindow();
+
+ if (this.mode == "HTML" && domPopupSearchResultsWindow.style.display != "block")
+ {
+ var domSearchType = this.DOMSearchType();
+
+ var left = GetXPosition(domSearchType);
+ var top = GetYPosition(domSearchType) + domSearchType.offsetHeight;
+
+ MoveToPosition(domPopupSearchResultsWindow, left, top);
+ domPopupSearchResultsWindow.style.display = 'block';
+ };
+
+
+ this.lastSearchValue = searchValue;
+ this.lastResultsPage = resultsPage;
+ };
+
+
+
+ // Group: Activation Functions
+ // Functions that handle whether the entire panel is active or not.
+ // ________________________________________________________________________
+
+
+ /*
+ Function: Activate
+
+ Activates or deactivates the search panel, resetting things to their default values if necessary. You can call this on every
+ control's OnBlur() and it will handle not deactivating the entire panel when focus is just switching between them transparently.
+
+ Parameters:
+
+ isActive - Whether you're activating or deactivating the panel.
+ ignoreDeactivateDelay - Set if you're positive the action will deactivate the panel and thus want to skip the delay.
+ */
+ this.Activate = function(isActive, ignoreDeactivateDelay)
+ {
+ // We want to ignore isActive being false while the results window is open.
+ if (isActive || (this.mode == "HTML" && this.DOMPopupSearchResultsWindow().style.display == "block"))
+ {
+ if (this.inactivateTimeout)
+ {
+ clearTimeout(this.inactivateTimeout);
+ this.inactivateTimeout = 0;
+ };
+
+ this.DOMSearchPanel().className = 'MSearchPanelActive';
+
+ var searchField = this.DOMSearchField();
+
+ if (searchField.value == 'Search')
+ { searchField.value = ""; }
+ }
+ else if (!ignoreDeactivateDelay)
+ {
+ this.inactivateTimeout = setTimeout(this.name + ".InactivateAfterTimeout()", this.inactivateTimeoutLength);
+ }
+ else
+ {
+ this.InactivateAfterTimeout();
+ };
+ };
+
+
+ /*
+ Function: InactivateAfterTimeout
+
+ Called by <inactivateTimeout>, which is set by <Activate()>. Inactivation occurs on a timeout because a control may
+ receive OnBlur() when focus is really transferring to another control in the search panel. In this case we don't want to
+ actually deactivate the panel because not only would that cause a visible flicker but it could also reset the search value.
+ So by doing it on a timeout instead, there's a short period where the second control's OnFocus() can cancel the deactivation.
+ */
+ this.InactivateAfterTimeout = function()
+ {
+ this.inactivateTimeout = 0;
+
+ this.DOMSearchPanel().className = 'MSearchPanelInactive';
+ this.DOMSearchField().value = "Search";
+
+ this.lastSearchValue = "";
+ this.lastResultsPage = "";
+ };
+ };
+
+
+
+
+/* ________________________________________________________________________________________________________
+
+ Class: SearchResults
+ _________________________________________________________________________________________________________
+
+ The class that handles everything on the search results page.
+ _________________________________________________________________________________________________________
+*/
+
+
+function SearchResults(name, mode)
+ {
+ /*
+ var: mode
+ The mode the search is going to work in, such as "HTML" or "FramedHTML".
+ */
+ this.mode = mode;
+
+ /*
+ var: lastMatchCount
+ The number of matches from the last run of <Search()>.
+ */
+ this.lastMatchCount = 0;
+
+
+ /*
+ Function: Toggle
+ Toggles the visibility of the passed element ID.
+ */
+ this.Toggle = function(id)
+ {
+ if (this.mode == "FramedHTML")
+ { return; };
+
+ var parentElement = document.getElementById(id);
+
+ var element = parentElement.firstChild;
+
+ while (element && element != parentElement)
+ {
+ if (element.nodeName == 'DIV' && element.className == 'ISubIndex')
+ {
+ if (element.style.display == 'block')
+ { element.style.display = "none"; }
+ else
+ { element.style.display = 'block'; }
+ };
+
+ if (element.nodeName == 'DIV' && element.hasChildNodes())
+ { element = element.firstChild; }
+ else if (element.nextSibling)
+ { element = element.nextSibling; }
+ else
+ {
+ do
+ {
+ element = element.parentNode;
+ }
+ while (element && element != parentElement && !element.nextSibling);
+
+ if (element && element != parentElement)
+ { element = element.nextSibling; };
+ };
+ };
+ };
+
+
+ /*
+ Function: Search
+
+ Searches for the passed string. If there is no parameter, it takes it from the URL query.
+
+ Always returns true, since other documents may try to call it and that may or may not be possible.
+ */
+ this.Search = function(search)
+ {
+ if (!search)
+ {
+ search = window.location.search;
+ search = search.substring(1); // Remove the leading ?
+ search = unescape(search);
+ };
+
+ search = search.replace(/^ +/, "");
+ search = search.replace(/ +$/, "");
+ search = search.toLowerCase();
+
+ if (search.match(/[^a-z0-9]/)) // Just a little speedup so it doesn't have to go through the below unnecessarily.
+ {
+ search = search.replace(/\_/g, "_und");
+ search = search.replace(/\ +/gi, "_spc");
+ search = search.replace(/\~/g, "_til");
+ search = search.replace(/\!/g, "_exc");
+ search = search.replace(/\@/g, "_att");
+ search = search.replace(/\#/g, "_num");
+ search = search.replace(/\$/g, "_dol");
+ search = search.replace(/\%/g, "_pct");
+ search = search.replace(/\^/g, "_car");
+ search = search.replace(/\&/g, "_amp");
+ search = search.replace(/\*/g, "_ast");
+ search = search.replace(/\(/g, "_lpa");
+ search = search.replace(/\)/g, "_rpa");
+ search = search.replace(/\-/g, "_min");
+ search = search.replace(/\+/g, "_plu");
+ search = search.replace(/\=/g, "_equ");
+ search = search.replace(/\{/g, "_lbc");
+ search = search.replace(/\}/g, "_rbc");
+ search = search.replace(/\[/g, "_lbk");
+ search = search.replace(/\]/g, "_rbk");
+ search = search.replace(/\:/g, "_col");
+ search = search.replace(/\;/g, "_sco");
+ search = search.replace(/\"/g, "_quo");
+ search = search.replace(/\'/g, "_apo");
+ search = search.replace(/\</g, "_lan");
+ search = search.replace(/\>/g, "_ran");
+ search = search.replace(/\,/g, "_com");
+ search = search.replace(/\./g, "_per");
+ search = search.replace(/\?/g, "_que");
+ search = search.replace(/\//g, "_sla");
+ search = search.replace(/[^a-z0-9\_]i/gi, "_zzz");
+ };
+
+ var resultRows = document.getElementsByTagName("div");
+ var matches = 0;
+
+ var i = 0;
+ while (i < resultRows.length)
+ {
+ var row = resultRows.item(i);
+
+ if (row.className == "SRResult")
+ {
+ var rowMatchName = row.id.toLowerCase();
+ rowMatchName = rowMatchName.replace(/^sr\d*_/, '');
+
+ if (search.length <= rowMatchName.length && rowMatchName.substr(0, search.length) == search)
+ {
+ row.style.display = "block";
+ matches++;
+ }
+ else
+ { row.style.display = "none"; };
+ };
+
+ i++;
+ };
+
+ document.getElementById("Searching").style.display="none";
+
+ if (matches == 0)
+ { document.getElementById("NoMatches").style.display="block"; }
+ else
+ { document.getElementById("NoMatches").style.display="none"; }
+
+ this.lastMatchCount = matches;
+
+ return true;
+ };
+ };
+
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/javascript/searchdata.js b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/javascript/searchdata.js
new file mode 100644
index 0000000..901318e
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/javascript/searchdata.js
@@ -0,0 +1,212 @@
+var indexSectionsWithContent = {
+ "General": {
+ "Symbols": false,
+ "Numbers": false,
+ "A": false,
+ "B": false,
+ "C": true,
+ "D": true,
+ "E": false,
+ "F": true,
+ "G": true,
+ "H": false,
+ "I": true,
+ "J": false,
+ "K": false,
+ "L": false,
+ "M": true,
+ "N": false,
+ "O": false,
+ "P": false,
+ "Q": false,
+ "R": false,
+ "S": true,
+ "T": true,
+ "U": false,
+ "V": false,
+ "W": false,
+ "X": false,
+ "Y": false,
+ "Z": false
+ },
+ "Variables": {
+ "Symbols": false,
+ "Numbers": false,
+ "A": false,
+ "B": false,
+ "C": true,
+ "D": true,
+ "E": false,
+ "F": false,
+ "G": false,
+ "H": false,
+ "I": false,
+ "J": false,
+ "K": false,
+ "L": true,
+ "M": false,
+ "N": false,
+ "O": true,
+ "P": true,
+ "Q": false,
+ "R": true,
+ "S": true,
+ "T": false,
+ "U": false,
+ "V": false,
+ "W": false,
+ "X": false,
+ "Y": false,
+ "Z": false
+ },
+ "Functions": {
+ "Symbols": false,
+ "Numbers": false,
+ "A": false,
+ "B": false,
+ "C": true,
+ "D": false,
+ "E": false,
+ "F": false,
+ "G": true,
+ "H": false,
+ "I": true,
+ "J": false,
+ "K": false,
+ "L": false,
+ "M": true,
+ "N": false,
+ "O": false,
+ "P": true,
+ "Q": false,
+ "R": false,
+ "S": true,
+ "T": true,
+ "U": false,
+ "V": false,
+ "W": false,
+ "X": false,
+ "Y": false,
+ "Z": false
+ },
+ "Files": {
+ "Symbols": false,
+ "Numbers": false,
+ "A": false,
+ "B": false,
+ "C": true,
+ "D": false,
+ "E": false,
+ "F": false,
+ "G": false,
+ "H": false,
+ "I": false,
+ "J": false,
+ "K": false,
+ "L": false,
+ "M": false,
+ "N": false,
+ "O": false,
+ "P": false,
+ "Q": false,
+ "R": true,
+ "S": false,
+ "T": false,
+ "U": false,
+ "V": false,
+ "W": false,
+ "X": false,
+ "Y": false,
+ "Z": false
+ },
+ "Configuration": {
+ "Symbols": false,
+ "Numbers": false,
+ "A": false,
+ "B": false,
+ "C": true,
+ "D": false,
+ "E": false,
+ "F": false,
+ "G": false,
+ "H": true,
+ "I": false,
+ "J": false,
+ "K": false,
+ "L": false,
+ "M": true,
+ "N": false,
+ "O": false,
+ "P": false,
+ "Q": false,
+ "R": false,
+ "S": true,
+ "T": true,
+ "U": true,
+ "V": false,
+ "W": false,
+ "X": false,
+ "Y": false,
+ "Z": false
+ },
+ "Types": {
+ "Symbols": false,
+ "Numbers": false,
+ "A": false,
+ "B": false,
+ "C": false,
+ "D": false,
+ "E": false,
+ "F": false,
+ "G": false,
+ "H": false,
+ "I": false,
+ "J": false,
+ "K": false,
+ "L": false,
+ "M": false,
+ "N": false,
+ "O": false,
+ "P": false,
+ "Q": false,
+ "R": false,
+ "S": true,
+ "T": false,
+ "U": false,
+ "V": false,
+ "W": false,
+ "X": false,
+ "Y": false,
+ "Z": false
+ },
+ "BuildTargets": {
+ "Symbols": false,
+ "Numbers": false,
+ "A": false,
+ "B": false,
+ "C": false,
+ "D": false,
+ "E": false,
+ "F": false,
+ "G": false,
+ "H": false,
+ "I": false,
+ "J": false,
+ "K": false,
+ "L": false,
+ "M": false,
+ "N": false,
+ "O": false,
+ "P": true,
+ "Q": false,
+ "R": false,
+ "S": false,
+ "T": false,
+ "U": false,
+ "V": false,
+ "W": false,
+ "X": false,
+ "Y": false,
+ "Z": false
+ }
+ }
\ No newline at end of file
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/BuildTargetsP.html b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/BuildTargetsP.html
new file mode 100644
index 0000000..65e741d
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/BuildTargetsP.html
@@ -0,0 +1,18 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd">
+
+<html><head><link rel="stylesheet" type="text/css" href="../styles/main.css"><script language=JavaScript src="../javascript/main.js"></script></head><body class="PopupSearchResultsPage" onLoad="NDOnLoad()"><script language=JavaScript><!--
+if (browserType) {document.write("<div class=" + browserType + ">");if (browserVer) {document.write("<div class=" + browserVer + ">"); }}// --></script>
+
+<!-- Copyright 2009 EEMBC -->
+<!-- saved from url=(0026)http://www.naturaldocs.org -->
+
+
+
+
+<div id=Index><div class=SRStatus id=Loading>Loading...</div><table border=0 cellspacing=0 cellpadding=0><div class=SRResult id=SR_port_undpostbuild><div class=IEntry><a href="javascript:searchResults.Toggle('SR_port_undpostbuild')" class=ISymbol>port_postbuild</a><div class=ISubIndex><a href="../files/linux/core_portme-mak.html#port_postbuild" target=_parent class=IFile>linux/<span class=HB> </span>core_portme.mak</a><a href="../files/PIC32/core_portme-mak.html#port_postbuild" target=_parent class=IFile>PIC32/<span class=HB> </span>core_portme.mak</a></div></div></div><div class=SRResult id=SR_port_undpostload><div class=IEntry><a href="javascript:searchResults.Toggle('SR_port_undpostload')" class=ISymbol>port_postload</a><div class=ISubIndex><a href="../files/linux/core_portme-mak.html#port_postload" target=_parent class=IFile>linux/<span class=HB> </span>core_portme.mak</a><a href="../files/PIC32/core_portme-mak.html#port_postload" target=_parent class=IFile>PIC32/<span class=HB> </span>core_portme.mak</a></div></div></div><div class=SRResult id=SR_port_undpostrun><div class=IEntry><a href="javascript:searchResults.Toggle('SR_port_undpostrun')" class=ISymbol>port_postrun</a><div class=ISubIndex><a href="../files/linux/core_portme-mak.html#port_postrun" target=_parent class=IFile>linux/<span class=HB> </span>core_portme.mak</a><a href="../files/PIC32/core_portme-mak.html#port_postrun" target=_parent class=IFile>PIC32/<span class=HB> </span>core_portme.mak</a></div></div></div><div class=SRResult id=SR_port_undprebuild><div class=IEntry><a href="javascript:searchResults.Toggle('SR_port_undprebuild')" class=ISymbol>port_prebuild</a><div class=ISubIndex><a href="../files/linux/core_portme-mak.html#port_prebuild" target=_parent class=IFile>linux/<span class=HB> </span>core_portme.mak</a><a href="../files/PIC32/core_portme-mak.html#port_prebuild" target=_parent class=IFile>PIC32/<span class=HB> </span>core_portme.mak</a></div></div></div><div class=SRResult id=SR_port_undpreload><div class=IEntry><a href="javascript:searchResults.Toggle('SR_port_undpreload')" class=ISymbol>port_preload</a><div class=ISubIndex><a href="../files/linux/core_portme-mak.html#port_preload" target=_parent class=IFile>linux/<span class=HB> </span>core_portme.mak</a><a href="../files/PIC32/core_portme-mak.html#port_preload" target=_parent class=IFile>PIC32/<span class=HB> </span>core_portme.mak</a></div></div></div><div class=SRResult id=SR_port_undprerun><div class=IEntry><a href="javascript:searchResults.Toggle('SR_port_undprerun')" class=ISymbol>port_prerun</a><div class=ISubIndex><a href="../files/linux/core_portme-mak.html#port_prerun" target=_parent class=IFile>linux/<span class=HB> </span>core_portme.mak</a><a href="../files/PIC32/core_portme-mak.html#port_prerun" target=_parent class=IFile>PIC32/<span class=HB> </span>core_portme.mak</a></div></div></div></table><div class=SRStatus id=Searching>Searching...</div><div class=SRStatus id=NoMatches>No Matches</div><script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults", "HTML");
+searchResults.Search();
+--></script></div><script language=JavaScript><!--
+if (browserType) {if (browserVer) {document.write("</div>"); }document.write("</div>");}// --></script></body></html>
\ No newline at end of file
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/ConfigurationC.html b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/ConfigurationC.html
new file mode 100644
index 0000000..84b49ca
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/ConfigurationC.html
@@ -0,0 +1,18 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd">
+
+<html><head><link rel="stylesheet" type="text/css" href="../styles/main.css"><script language=JavaScript src="../javascript/main.js"></script></head><body class="PopupSearchResultsPage" onLoad="NDOnLoad()"><script language=JavaScript><!--
+if (browserType) {document.write("<div class=" + browserType + ">");if (browserVer) {document.write("<div class=" + browserVer + ">"); }}// --></script>
+
+<!-- Copyright 2009 EEMBC -->
+<!-- saved from url=(0026)http://www.naturaldocs.org -->
+
+
+
+
+<div id=Index><div class=SRStatus id=Loading>Loading...</div><table border=0 cellspacing=0 cellpadding=0><div class=SRResult id=SR_CORE_undTICKS><div class=IEntry><a href="../files/linux/core_portme-h.html#CORE_TICKS" target=_parent class=ISymbol>CORE_TICKS</a></div></div></table><div class=SRStatus id=Searching>Searching...</div><div class=SRStatus id=NoMatches>No Matches</div><script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults", "HTML");
+searchResults.Search();
+--></script></div><script language=JavaScript><!--
+if (browserType) {if (browserVer) {document.write("</div>"); }document.write("</div>");}// --></script></body></html>
\ No newline at end of file
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/ConfigurationH.html b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/ConfigurationH.html
new file mode 100644
index 0000000..3b0c392
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/ConfigurationH.html
@@ -0,0 +1,18 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd">
+
+<html><head><link rel="stylesheet" type="text/css" href="../styles/main.css"><script language=JavaScript src="../javascript/main.js"></script></head><body class="PopupSearchResultsPage" onLoad="NDOnLoad()"><script language=JavaScript><!--
+if (browserType) {document.write("<div class=" + browserType + ">");if (browserVer) {document.write("<div class=" + browserVer + ">"); }}// --></script>
+
+<!-- Copyright 2009 EEMBC -->
+<!-- saved from url=(0026)http://www.naturaldocs.org -->
+
+
+
+
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+<!-- Copyright 2009 EEMBC -->
+<!-- saved from url=(0026)http://www.naturaldocs.org -->
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+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults", "HTML");
+searchResults.Search();
+--></script></div><script language=JavaScript><!--
+if (browserType) {if (browserVer) {document.write("</div>"); }document.write("</div>");}// --></script></body></html>
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diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/FunctionsG.html b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/FunctionsG.html
new file mode 100644
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--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/FunctionsG.html
@@ -0,0 +1,18 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd">
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+if (browserType) {document.write("<div class=" + browserType + ">");if (browserVer) {document.write("<div class=" + browserVer + ">"); }}// --></script>
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+<!-- Copyright 2009 EEMBC -->
+<!-- saved from url=(0026)http://www.naturaldocs.org -->
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+
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+
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+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults", "HTML");
+searchResults.Search();
+--></script></div><script language=JavaScript><!--
+if (browserType) {if (browserVer) {document.write("</div>"); }document.write("</div>");}// --></script></body></html>
\ No newline at end of file
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/FunctionsI.html b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/FunctionsI.html
new file mode 100644
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--- /dev/null
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@@ -0,0 +1,18 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd">
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+<html><head><link rel="stylesheet" type="text/css" href="../styles/main.css"><script language=JavaScript src="../javascript/main.js"></script></head><body class="PopupSearchResultsPage" onLoad="NDOnLoad()"><script language=JavaScript><!--
+if (browserType) {document.write("<div class=" + browserType + ">");if (browserVer) {document.write("<div class=" + browserVer + ">"); }}// --></script>
+
+<!-- Copyright 2009 EEMBC -->
+<!-- saved from url=(0026)http://www.naturaldocs.org -->
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+
+
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+<div id=Index><div class=SRStatus id=Loading>Loading...</div><table border=0 cellspacing=0 cellpadding=0><div class=SRResult id=SR_iterate><div class=IEntry><a href="../files/core_main-c.html#iterate" target=_parent class=ISymbol>iterate</a></div></div></table><div class=SRStatus id=Searching>Searching...</div><div class=SRStatus id=NoMatches>No Matches</div><script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults", "HTML");
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+--></script></div><script language=JavaScript><!--
+if (browserType) {if (browserVer) {document.write("</div>"); }document.write("</div>");}// --></script></body></html>
\ No newline at end of file
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/FunctionsM.html b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/FunctionsM.html
new file mode 100644
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--- /dev/null
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@@ -0,0 +1,18 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd">
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+if (browserType) {document.write("<div class=" + browserType + ">");if (browserVer) {document.write("<div class=" + browserVer + ">"); }}// --></script>
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+<!-- Copyright 2009 EEMBC -->
+<!-- saved from url=(0026)http://www.naturaldocs.org -->
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+
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+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults", "HTML");
+searchResults.Search();
+--></script></div><script language=JavaScript><!--
+if (browserType) {if (browserVer) {document.write("</div>"); }document.write("</div>");}// --></script></body></html>
\ No newline at end of file
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/FunctionsP.html b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/FunctionsP.html
new file mode 100644
index 0000000..c4b9d2d
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/FunctionsP.html
@@ -0,0 +1,18 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd">
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+if (browserType) {document.write("<div class=" + browserType + ">");if (browserVer) {document.write("<div class=" + browserVer + ">"); }}// --></script>
+
+<!-- Copyright 2009 EEMBC -->
+<!-- saved from url=(0026)http://www.naturaldocs.org -->
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+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults", "HTML");
+searchResults.Search();
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\ No newline at end of file
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/FunctionsS.html b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/FunctionsS.html
new file mode 100644
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--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/FunctionsS.html
@@ -0,0 +1,18 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd">
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+if (browserType) {document.write("<div class=" + browserType + ">");if (browserVer) {document.write("<div class=" + browserVer + ">"); }}// --></script>
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+<!-- Copyright 2009 EEMBC -->
+<!-- saved from url=(0026)http://www.naturaldocs.org -->
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+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults", "HTML");
+searchResults.Search();
+--></script></div><script language=JavaScript><!--
+if (browserType) {if (browserVer) {document.write("</div>"); }document.write("</div>");}// --></script></body></html>
\ No newline at end of file
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/FunctionsT.html b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/FunctionsT.html
new file mode 100644
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--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/FunctionsT.html
@@ -0,0 +1,18 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd">
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+if (browserType) {document.write("<div class=" + browserType + ">");if (browserVer) {document.write("<div class=" + browserVer + ">"); }}// --></script>
+
+<!-- Copyright 2009 EEMBC -->
+<!-- saved from url=(0026)http://www.naturaldocs.org -->
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+
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+
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+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults", "HTML");
+searchResults.Search();
+--></script></div><script language=JavaScript><!--
+if (browserType) {if (browserVer) {document.write("</div>"); }document.write("</div>");}// --></script></body></html>
\ No newline at end of file
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/GeneralB.html b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/GeneralB.html
new file mode 100644
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+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/GeneralB.html
@@ -0,0 +1,18 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd">
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+if (browserType) {document.write("<div class=" + browserType + ">");if (browserVer) {document.write("<div class=" + browserVer + ">"); }}// --></script>
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+<!-- Copyright 2009 EEMBC -->
+<!-- saved from url=(0026)http://www.naturaldocs.org -->
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+
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+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults", "HTML");
+searchResults.Search();
+--></script></div><script language=JavaScript><!--
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\ No newline at end of file
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/GeneralC.html b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/GeneralC.html
new file mode 100644
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--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/GeneralC.html
@@ -0,0 +1,18 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd">
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+if (browserType) {document.write("<div class=" + browserType + ">");if (browserVer) {document.write("<div class=" + browserVer + ">"); }}// --></script>
+
+<!-- Copyright 2009 EEMBC -->
+<!-- saved from url=(0026)http://www.naturaldocs.org -->
+
+
+
+
+<div id=Index><div class=SRStatus id=Loading>Loading...</div><table border=0 cellspacing=0 cellpadding=0><div class=SRResult id=SR_CC><div class=IEntry><a href="../files/linux/core_portme-mak.html#CC" target=_parent class=ISymbol>CC</a></div></div><div class=SRResult id=SR_CFLAGS><div class=IEntry><a href="javascript:searchResults.Toggle('SR_CFLAGS')" class=ISymbol>CFLAGS</a><div class=ISubIndex><a href="../files/linux/core_portme-mak.html#CFLAGS" target=_parent class=IFile>linux/<span class=HB> </span>core_portme.mak</a><a href="../files/PIC32/core_portme-mak.html#CFLAGS" target=_parent class=IFile>PIC32/<span class=HB> </span>core_portme.mak</a></div></div></div><div class=SRResult id=SR_cmp_undcomplex><div class=IEntry><a href="../files/core_list_join-c.html#cmp_complex" target=_parent class=ISymbol>cmp_complex</a></div></div><div class=SRResult id=SR_cmp_undidx><div class=IEntry><a href="../files/core_list_join-c.html#cmp_idx" target=_parent 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+document.getElementById("Loading").style.display="none";
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diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/GeneralD.html b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/GeneralD.html
new file mode 100644
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+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd">
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+<!-- saved from url=(0026)http://www.naturaldocs.org -->
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+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults", "HTML");
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diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/GeneralF.html b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/GeneralF.html
new file mode 100644
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--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/GeneralF.html
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+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd">
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+if (browserType) {document.write("<div class=" + browserType + ">");if (browserVer) {document.write("<div class=" + browserVer + ">"); }}// --></script>
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+<!-- Copyright 2009 EEMBC -->
+<!-- saved from url=(0026)http://www.naturaldocs.org -->
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+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults", "HTML");
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+if (browserType) {if (browserVer) {document.write("</div>"); }document.write("</div>");}// --></script></body></html>
\ No newline at end of file
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/GeneralG.html b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/GeneralG.html
new file mode 100644
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--- /dev/null
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+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd">
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+if (browserType) {document.write("<div class=" + browserType + ">");if (browserVer) {document.write("<div class=" + browserVer + ">"); }}// --></script>
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+<!-- Copyright 2009 EEMBC -->
+<!-- saved from url=(0026)http://www.naturaldocs.org -->
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+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults", "HTML");
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\ No newline at end of file
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/GeneralH.html b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/GeneralH.html
new file mode 100644
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@@ -0,0 +1,18 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd">
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+if (browserType) {document.write("<div class=" + browserType + ">");if (browserVer) {document.write("<div class=" + browserVer + ">"); }}// --></script>
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+<!-- Copyright 2009 EEMBC -->
+<!-- saved from url=(0026)http://www.naturaldocs.org -->
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+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults", "HTML");
+searchResults.Search();
+--></script></div><script language=JavaScript><!--
+if (browserType) {if (browserVer) {document.write("</div>"); }document.write("</div>");}// --></script></body></html>
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diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/GeneralI.html b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/GeneralI.html
new file mode 100644
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--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/GeneralI.html
@@ -0,0 +1,18 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd">
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+if (browserType) {document.write("<div class=" + browserType + ">");if (browserVer) {document.write("<div class=" + browserVer + ">"); }}// --></script>
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+<!-- Copyright 2009 EEMBC -->
+<!-- saved from url=(0026)http://www.naturaldocs.org -->
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+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults", "HTML");
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\ No newline at end of file
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/GeneralL.html b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/GeneralL.html
new file mode 100644
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--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/GeneralL.html
@@ -0,0 +1,18 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd">
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+if (browserType) {document.write("<div class=" + browserType + ">");if (browserVer) {document.write("<div class=" + browserVer + ">"); }}// --></script>
+
+<!-- Copyright 2009 EEMBC -->
+<!-- saved from url=(0026)http://www.naturaldocs.org -->
+
+
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+document.getElementById("Loading").style.display="none";
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\ No newline at end of file
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/GeneralM.html b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/GeneralM.html
new file mode 100644
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--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/GeneralM.html
@@ -0,0 +1,18 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd">
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+if (browserType) {document.write("<div class=" + browserType + ">");if (browserVer) {document.write("<div class=" + browserVer + ">"); }}// --></script>
+
+<!-- Copyright 2009 EEMBC -->
+<!-- saved from url=(0026)http://www.naturaldocs.org -->
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+
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+
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+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults", "HTML");
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diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/GeneralO.html b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/GeneralO.html
new file mode 100644
index 0000000..b14f180
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/GeneralO.html
@@ -0,0 +1,18 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd">
+
+<html><head><link rel="stylesheet" type="text/css" href="../styles/main.css"><script language=JavaScript src="../javascript/main.js"></script></head><body class="PopupSearchResultsPage" onLoad="NDOnLoad()"><script language=JavaScript><!--
+if (browserType) {document.write("<div class=" + browserType + ">");if (browserVer) {document.write("<div class=" + browserVer + ">"); }}// --></script>
+
+<!-- Copyright 2009 EEMBC -->
+<!-- saved from url=(0026)http://www.naturaldocs.org -->
+
+
+
+
+<div id=Index><div class=SRStatus id=Loading>Loading...</div><table border=0 cellspacing=0 cellpadding=0><div class=SRResult id=SR_OPATH><div class=IEntry><a href="javascript:searchResults.Toggle('SR_OPATH')" class=ISymbol>OPATH</a><div class=ISubIndex><a href="../files/linux/core_portme-mak.html#OPATH" target=_parent class=IFile>linux/<span class=HB> </span>core_portme.mak</a><a href="../files/PIC32/core_portme-mak.html#OPATH" target=_parent class=IFile>PIC32/<span class=HB> </span>core_portme.mak</a></div></div></div><div class=SRResult id=SR_OUTFLAG><div class=IEntry><a href="javascript:searchResults.Toggle('SR_OUTFLAG')" class=ISymbol>OUTFLAG</a><div class=ISubIndex><a href="../files/linux/core_portme-mak.html#OUTFLAG" target=_parent class=IFile>linux/<span class=HB> </span>core_portme.mak</a><a href="../files/PIC32/core_portme-mak.html#OUTFLAG" target=_parent class=IFile>PIC32/<span class=HB> </span>core_portme.mak</a></div></div></div></table><div class=SRStatus id=Searching>Searching...</div><div class=SRStatus id=NoMatches>No Matches</div><script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults", "HTML");
+searchResults.Search();
+--></script></div><script language=JavaScript><!--
+if (browserType) {if (browserVer) {document.write("</div>"); }document.write("</div>");}// --></script></body></html>
\ No newline at end of file
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/GeneralP.html b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/GeneralP.html
new file mode 100644
index 0000000..063a6c1
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/GeneralP.html
@@ -0,0 +1,18 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd">
+
+<html><head><link rel="stylesheet" type="text/css" href="../styles/main.css"><script language=JavaScript src="../javascript/main.js"></script></head><body class="PopupSearchResultsPage" onLoad="NDOnLoad()"><script language=JavaScript><!--
+if (browserType) {document.write("<div class=" + browserType + ">");if (browserVer) {document.write("<div class=" + browserVer + ">"); }}// --></script>
+
+<!-- Copyright 2009 EEMBC -->
+<!-- saved from url=(0026)http://www.naturaldocs.org -->
+
+
+
+
+<div id=Index><div class=SRStatus id=Loading>Loading...</div><table border=0 cellspacing=0 cellpadding=0><div class=SRResult id=SR_PERL><div class=IEntry><a href="javascript:searchResults.Toggle('SR_PERL')" class=ISymbol>PERL</a><div class=ISubIndex><a href="../files/linux/core_portme-mak.html#PERL" target=_parent class=IFile>linux/<span class=HB> </span>core_portme.mak</a><a href="../files/PIC32/core_portme-mak.html#PERL" target=_parent class=IFile>PIC32/<span class=HB> </span>core_portme.mak</a></div></div></div><div class=SRResult id=SR_PORT_undOBJS><div class=IEntry><a href="javascript:searchResults.Toggle('SR_PORT_undOBJS')" class=ISymbol>PORT_OBJS</a><div class=ISubIndex><a href="../files/linux/core_portme-mak.html#PORT_OBJS" target=_parent class=IFile>linux/<span class=HB> </span>core_portme.mak</a><a href="../files/PIC32/core_portme-mak.html#PORT_OBJS" target=_parent class=IFile>PIC32/<span class=HB> </span>core_portme.mak</a></div></div></div><div class=SRResult id=SR_port_undpostbuild><div class=IEntry><a href="javascript:searchResults.Toggle('SR_port_undpostbuild')" class=ISymbol>port_postbuild</a><div class=ISubIndex><a href="../files/linux/core_portme-mak.html#port_postbuild" target=_parent class=IFile>linux/<span class=HB> </span>core_portme.mak</a><a href="../files/PIC32/core_portme-mak.html#port_postbuild" target=_parent class=IFile>PIC32/<span class=HB> </span>core_portme.mak</a></div></div></div><div class=SRResult id=SR_port_undpostload><div class=IEntry><a href="javascript:searchResults.Toggle('SR_port_undpostload')" class=ISymbol>port_postload</a><div class=ISubIndex><a href="../files/linux/core_portme-mak.html#port_postload" target=_parent class=IFile>linux/<span class=HB> </span>core_portme.mak</a><a href="../files/PIC32/core_portme-mak.html#port_postload" target=_parent class=IFile>PIC32/<span class=HB> </span>core_portme.mak</a></div></div></div><div class=SRResult id=SR_port_undpostrun><div class=IEntry><a href="javascript:searchResults.Toggle('SR_port_undpostrun')" class=ISymbol>port_postrun</a><div class=ISubIndex><a href="../files/linux/core_portme-mak.html#port_postrun" target=_parent class=IFile>linux/<span class=HB> </span>core_portme.mak</a><a href="../files/PIC32/core_portme-mak.html#port_postrun" target=_parent class=IFile>PIC32/<span class=HB> </span>core_portme.mak</a></div></div></div><div class=SRResult id=SR_port_undprebuild><div class=IEntry><a href="javascript:searchResults.Toggle('SR_port_undprebuild')" class=ISymbol>port_prebuild</a><div class=ISubIndex><a href="../files/linux/core_portme-mak.html#port_prebuild" target=_parent class=IFile>linux/<span class=HB> </span>core_portme.mak</a><a href="../files/PIC32/core_portme-mak.html#port_prebuild" target=_parent class=IFile>PIC32/<span class=HB> </span>core_portme.mak</a></div></div></div><div class=SRResult id=SR_port_undpreload><div class=IEntry><a href="javascript:searchResults.Toggle('SR_port_undpreload')" class=ISymbol>port_preload</a><div class=ISubIndex><a href="../files/linux/core_portme-mak.html#port_preload" target=_parent class=IFile>linux/<span class=HB> </span>core_portme.mak</a><a href="../files/PIC32/core_portme-mak.html#port_preload" target=_parent class=IFile>PIC32/<span class=HB> </span>core_portme.mak</a></div></div></div><div class=SRResult id=SR_port_undprerun><div class=IEntry><a href="javascript:searchResults.Toggle('SR_port_undprerun')" class=ISymbol>port_prerun</a><div class=ISubIndex><a href="../files/linux/core_portme-mak.html#port_prerun" target=_parent class=IFile>linux/<span class=HB> </span>core_portme.mak</a><a href="../files/PIC32/core_portme-mak.html#port_prerun" target=_parent class=IFile>PIC32/<span class=HB> </span>core_portme.mak</a></div></div></div><div class=SRResult id=SR_PORT_undSRCS><div class=IEntry><a href="../files/linux/core_portme-mak.html#PORT_SRCS" target=_parent class=ISymbol>PORT_SRCS</a></div></div><div class=SRResult id=SR_portable_undfini><div class=IEntry><a href="../files/linux/core_portme-c.html#portable_fini" target=_parent class=ISymbol>portable_fini</a></div></div><div class=SRResult id=SR_portable_undfree><div class=IEntry><a href="../files/linux/core_portme-c.html#portable_free" target=_parent class=ISymbol>portable_free</a></div></div><div class=SRResult id=SR_portable_undinit><div class=IEntry><a href="../files/linux/core_portme-c.html#portable_init" target=_parent class=ISymbol>portable_init</a></div></div><div class=SRResult id=SR_portable_undmalloc><div class=IEntry><a href="../files/linux/core_portme-c.html#portable_malloc" target=_parent class=ISymbol>portable_malloc</a></div></div></table><div class=SRStatus id=Searching>Searching...</div><div class=SRStatus id=NoMatches>No Matches</div><script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults", "HTML");
+searchResults.Search();
+--></script></div><script language=JavaScript><!--
+if (browserType) {if (browserVer) {document.write("</div>"); }document.write("</div>");}// --></script></body></html>
\ No newline at end of file
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/GeneralR.html b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/GeneralR.html
new file mode 100644
index 0000000..24f3395
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/GeneralR.html
@@ -0,0 +1,18 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd">
+
+<html><head><link rel="stylesheet" type="text/css" href="../styles/main.css"><script language=JavaScript src="../javascript/main.js"></script></head><body class="PopupSearchResultsPage" onLoad="NDOnLoad()"><script language=JavaScript><!--
+if (browserType) {document.write("<div class=" + browserType + ">");if (browserVer) {document.write("<div class=" + browserVer + ">"); }}// --></script>
+
+<!-- Copyright 2009 EEMBC -->
+<!-- saved from url=(0026)http://www.naturaldocs.org -->
+
+
+
+
+<div id=Index><div class=SRStatus id=Loading>Loading...</div><table border=0 cellspacing=0 cellpadding=0><div class=SRResult id=SR_Release_spcNotes><div class=IEntry><a href="../files/release_notes-txt.html#Release_Notes" target=_parent class=ISymbol>Release Notes</a></div></div><div class=SRResult id=SR_Reporting_spcrules><div class=IEntry><a href="../files/readme-txt.html#Reporting_rules" target=_parent class=ISymbol>Reporting rules</a></div></div><div class=SRResult id=SR_RUN><div class=IEntry><a href="../files/linux/core_portme-mak.html#RUN" target=_parent class=ISymbol>RUN</a></div></div><div class=SRResult id=SR_Run_spcrules><div class=IEntry><a href="../files/readme-txt.html#Run_rules" target=_parent class=ISymbol>Run rules</a></div></div></table><div class=SRStatus id=Searching>Searching...</div><div class=SRStatus id=NoMatches>No Matches</div><script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults", "HTML");
+searchResults.Search();
+--></script></div><script language=JavaScript><!--
+if (browserType) {if (browserVer) {document.write("</div>"); }document.write("</div>");}// --></script></body></html>
\ No newline at end of file
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/GeneralS.html b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/GeneralS.html
new file mode 100644
index 0000000..a18c407
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/GeneralS.html
@@ -0,0 +1,18 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd">
+
+<html><head><link rel="stylesheet" type="text/css" href="../styles/main.css"><script language=JavaScript src="../javascript/main.js"></script></head><body class="PopupSearchResultsPage" onLoad="NDOnLoad()"><script language=JavaScript><!--
+if (browserType) {document.write("<div class=" + browserType + ">");if (browserVer) {document.write("<div class=" + browserVer + ">"); }}// --></script>
+
+<!-- Copyright 2009 EEMBC -->
+<!-- saved from url=(0026)http://www.naturaldocs.org -->
+
+
+
+
+<div id=Index><div class=SRStatus id=Loading>Loading...</div><table border=0 cellspacing=0 cellpadding=0><div class=SRResult id=SR_secs_undret><div class=IEntry><a href="../files/coremark-h.html#secs_ret" target=_parent class=ISymbol>secs_ret</a></div></div><div class=SRResult id=SR_SEED_undMETHOD><div class=IEntry><a href="../files/linux/core_portme-h.html#SEED_METHOD" target=_parent class=ISymbol>SEED_METHOD</a></div></div><div class=SRResult id=SR_SEPARATE_undCOMPILE><div class=IEntry><a href="javascript:searchResults.Toggle('SR_SEPARATE_undCOMPILE')" class=ISymbol>SEPARATE_COMPILE</a><div class=ISubIndex><a href="../files/linux/core_portme-mak.html#SEPARATE_COMPILE" target=_parent class=IFile>linux/<span class=HB> </span>core_portme.mak</a><a href="../files/PIC32/core_portme-mak.html#SEPARATE_COMPILE" target=_parent class=IFile>PIC32/<span class=HB> </span>core_portme.mak</a></div></div></div><div class=SRResult id=SR_start_undtime><div class=IEntry><a href="../files/linux/core_portme-c.html#start_time" target=_parent class=ISymbol>start_time</a></div></div><div class=SRResult id=SR_stop_undtime><div class=IEntry><a href="../files/linux/core_portme-c.html#stop_time" target=_parent class=ISymbol>stop_time</a></div></div><div class=SRResult id=SR_Submitting_spcresults><div class=IEntry><a href="../files/readme-txt.html#Submitting_results" target=_parent class=ISymbol>Submitting results</a></div></div></table><div class=SRStatus id=Searching>Searching...</div><div class=SRStatus id=NoMatches>No Matches</div><script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults", "HTML");
+searchResults.Search();
+--></script></div><script language=JavaScript><!--
+if (browserType) {if (browserVer) {document.write("</div>"); }document.write("</div>");}// --></script></body></html>
\ No newline at end of file
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/GeneralT.html b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/GeneralT.html
new file mode 100644
index 0000000..a2fde7e
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/GeneralT.html
@@ -0,0 +1,18 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd">
+
+<html><head><link rel="stylesheet" type="text/css" href="../styles/main.css"><script language=JavaScript src="../javascript/main.js"></script></head><body class="PopupSearchResultsPage" onLoad="NDOnLoad()"><script language=JavaScript><!--
+if (browserType) {document.write("<div class=" + browserType + ">");if (browserVer) {document.write("<div class=" + browserVer + ">"); }}// --></script>
+
+<!-- Copyright 2009 EEMBC -->
+<!-- saved from url=(0026)http://www.naturaldocs.org -->
+
+
+
+
+<div id=Index><div class=SRStatus id=Loading>Loading...</div><table border=0 cellspacing=0 cellpadding=0><div class=SRResult id=SR_time_undin_undsecs><div class=IEntry><a href="../files/linux/core_portme-c.html#time_in_secs" target=_parent class=ISymbol>time_in_secs</a></div></div><div class=SRResult id=SR_TIMER_undRES_undDIVIDER><div class=IEntry><a href="../files/linux/core_portme-c.html#TIMER_RES_DIVIDER" target=_parent class=ISymbol>TIMER_RES_DIVIDER</a></div></div><div class=SRResult id=SR_TOTAL_undDATA_undSIZE><div class=IEntry><a href="../files/coremark-h.html#TOTAL_DATA_SIZE" target=_parent class=ISymbol>TOTAL_DATA_SIZE</a></div></div><div class=SRResult id=SR_Types><div class=IEntry><a href="../files/coremark-h.html#Types" target=_parent class=ISymbol>Types</a></div></div></table><div class=SRStatus id=Searching>Searching...</div><div class=SRStatus id=NoMatches>No Matches</div><script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults", "HTML");
+searchResults.Search();
+--></script></div><script language=JavaScript><!--
+if (browserType) {if (browserVer) {document.write("</div>"); }document.write("</div>");}// --></script></body></html>
\ No newline at end of file
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/GeneralU.html b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/GeneralU.html
new file mode 100644
index 0000000..d9b46a5
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/GeneralU.html
@@ -0,0 +1,18 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd">
+
+<html><head><link rel="stylesheet" type="text/css" href="../styles/main.css"><script language=JavaScript src="../javascript/main.js"></script></head><body class="PopupSearchResultsPage" onLoad="NDOnLoad()"><script language=JavaScript><!--
+if (browserType) {document.write("<div class=" + browserType + ">");if (browserVer) {document.write("<div class=" + browserVer + ">"); }}// --></script>
+
+<!-- Copyright 2009 EEMBC -->
+<!-- saved from url=(0026)http://www.naturaldocs.org -->
+
+
+
+
+<div id=Index><div class=SRStatus id=Loading>Loading...</div><table border=0 cellspacing=0 cellpadding=0><div class=SRResult id=SR_USE_undCLOCK><div class=IEntry><a href="../files/linux/core_portme-h.html#USE_CLOCK" target=_parent class=ISymbol>USE_CLOCK</a></div></div><div class=SRResult id=SR_USE_undFORK><div class=IEntry><a href="../files/linux/core_portme-h.html#USE_FORK" target=_parent class=ISymbol>USE_FORK</a></div></div><div class=SRResult id=SR_USE_undPTHREAD><div class=IEntry><a href="../files/linux/core_portme-h.html#USE_PTHREAD" target=_parent class=ISymbol>USE_PTHREAD</a></div></div><div class=SRResult id=SR_USE_undSOCKET><div class=IEntry><a href="../files/linux/core_portme-h.html#USE_SOCKET" target=_parent class=ISymbol>USE_SOCKET</a></div></div></table><div class=SRStatus id=Searching>Searching...</div><div class=SRStatus id=NoMatches>No Matches</div><script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults", "HTML");
+searchResults.Search();
+--></script></div><script language=JavaScript><!--
+if (browserType) {if (browserVer) {document.write("</div>"); }document.write("</div>");}// --></script></body></html>
\ No newline at end of file
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/GeneralV.html b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/GeneralV.html
new file mode 100644
index 0000000..9c53066
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/GeneralV.html
@@ -0,0 +1,18 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd">
+
+<html><head><link rel="stylesheet" type="text/css" href="../styles/main.css"><script language=JavaScript src="../javascript/main.js"></script></head><body class="PopupSearchResultsPage" onLoad="NDOnLoad()"><script language=JavaScript><!--
+if (browserType) {document.write("<div class=" + browserType + ">");if (browserVer) {document.write("<div class=" + browserVer + ">"); }}// --></script>
+
+<!-- Copyright 2009 EEMBC -->
+<!-- saved from url=(0026)http://www.naturaldocs.org -->
+
+
+
+
+<div id=Index><div class=SRStatus id=Loading>Loading...</div><table border=0 cellspacing=0 cellpadding=0><div class=SRResult id=SR_Variables><div class=IEntry><a href="javascript:searchResults.Toggle('SR_Variables')" class=ISymbol>Variables</a><div class=ISubIndex><a href="../files/linux/core_portme-h.html#Variables" target=_parent class=IFile>linux/<span class=HB> </span>core_portme.h</a><a href="../files/linux/core_portme-mak.html#Variables" target=_parent class=IFile>linux/<span class=HB> </span>core_portme.mak</a><a href="../files/PIC32/core_portme-mak.html#Variables" target=_parent class=IFile>PIC32/<span class=HB> </span>core_portme.mak</a></div></div></div></table><div class=SRStatus id=Searching>Searching...</div><div class=SRStatus id=NoMatches>No Matches</div><script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults", "HTML");
+searchResults.Search();
+--></script></div><script language=JavaScript><!--
+if (browserType) {if (browserVer) {document.write("</div>"); }document.write("</div>");}// --></script></body></html>
\ No newline at end of file
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/GeneralW.html b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/GeneralW.html
new file mode 100644
index 0000000..e22dcb0
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/GeneralW.html
@@ -0,0 +1,18 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd">
+
+<html><head><link rel="stylesheet" type="text/css" href="../styles/main.css"><script language=JavaScript src="../javascript/main.js"></script></head><body class="PopupSearchResultsPage" onLoad="NDOnLoad()"><script language=JavaScript><!--
+if (browserType) {document.write("<div class=" + browserType + ">");if (browserVer) {document.write("<div class=" + browserVer + ">"); }}// --></script>
+
+<!-- Copyright 2009 EEMBC -->
+<!-- saved from url=(0026)http://www.naturaldocs.org -->
+
+
+
+
+<div id=Index><div class=SRStatus id=Loading>Loading...</div><table border=0 cellspacing=0 cellpadding=0><div class=SRResult id=SR_Welcome><div class=IEntry><a href="../files/readme-txt.html#Welcome" target=_parent class=ISymbol>Welcome</a></div></div></table><div class=SRStatus id=Searching>Searching...</div><div class=SRStatus id=NoMatches>No Matches</div><script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults", "HTML");
+searchResults.Search();
+--></script></div><script language=JavaScript><!--
+if (browserType) {if (browserVer) {document.write("</div>"); }document.write("</div>");}// --></script></body></html>
\ No newline at end of file
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/NoResults.html b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/NoResults.html
new file mode 100644
index 0000000..49e3859
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/NoResults.html
@@ -0,0 +1,13 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd">
+
+<html><head><link rel="stylesheet" type="text/css" href="../styles/main.css"><script language=JavaScript src="../javascript/main.js"></script></head><body class="PopupSearchResultsPage" onLoad="NDOnLoad()"><script language=JavaScript><!--
+if (browserType) {document.write("<div class=" + browserType + ">");if (browserVer) {document.write("<div class=" + browserVer + ">"); }}// --></script>
+
+<!-- Copyright 2009 EEMBC -->
+<!-- saved from url=(0026)http://www.naturaldocs.org -->
+
+
+
+
+<div id=Index><div class=SRStatus id=NoMatches>No Matches</div></div><script language=JavaScript><!--
+if (browserType) {if (browserVer) {document.write("</div>"); }document.write("</div>");}// --></script></body></html>
\ No newline at end of file
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/TypesS.html b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/TypesS.html
new file mode 100644
index 0000000..3d87649
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/TypesS.html
@@ -0,0 +1,18 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd">
+
+<html><head><link rel="stylesheet" type="text/css" href="../styles/main.css"><script language=JavaScript src="../javascript/main.js"></script></head><body class="PopupSearchResultsPage" onLoad="NDOnLoad()"><script language=JavaScript><!--
+if (browserType) {document.write("<div class=" + browserType + ">");if (browserVer) {document.write("<div class=" + browserVer + ">"); }}// --></script>
+
+<!-- Copyright 2009 EEMBC -->
+<!-- saved from url=(0026)http://www.naturaldocs.org -->
+
+
+
+
+<div id=Index><div class=SRStatus id=Loading>Loading...</div><table border=0 cellspacing=0 cellpadding=0><div class=SRResult id=SR_secs_undret><div class=IEntry><a href="../files/coremark-h.html#secs_ret" target=_parent class=ISymbol>secs_ret</a></div></div></table><div class=SRStatus id=Searching>Searching...</div><div class=SRStatus id=NoMatches>No Matches</div><script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults", "HTML");
+searchResults.Search();
+--></script></div><script language=JavaScript><!--
+if (browserType) {if (browserVer) {document.write("</div>"); }document.write("</div>");}// --></script></body></html>
\ No newline at end of file
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/VariablesC.html b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/VariablesC.html
new file mode 100644
index 0000000..d3bdfef
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/VariablesC.html
@@ -0,0 +1,18 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd">
+
+<html><head><link rel="stylesheet" type="text/css" href="../styles/main.css"><script language=JavaScript src="../javascript/main.js"></script></head><body class="PopupSearchResultsPage" onLoad="NDOnLoad()"><script language=JavaScript><!--
+if (browserType) {document.write("<div class=" + browserType + ">");if (browserVer) {document.write("<div class=" + browserVer + ">"); }}// --></script>
+
+<!-- Copyright 2009 EEMBC -->
+<!-- saved from url=(0026)http://www.naturaldocs.org -->
+
+
+
+
+<div id=Index><div class=SRStatus id=Loading>Loading...</div><table border=0 cellspacing=0 cellpadding=0><div class=SRResult id=SR_CC><div class=IEntry><a href="../files/linux/core_portme-mak.html#CC" target=_parent class=ISymbol>CC</a></div></div><div class=SRResult id=SR_CFLAGS><div class=IEntry><a href="javascript:searchResults.Toggle('SR_CFLAGS')" class=ISymbol>CFLAGS</a><div class=ISubIndex><a href="../files/linux/core_portme-mak.html#CFLAGS" target=_parent class=IFile>linux/<span class=HB> </span>core_portme.mak</a><a href="../files/PIC32/core_portme-mak.html#CFLAGS" target=_parent class=IFile>PIC32/<span class=HB> </span>core_portme.mak</a></div></div></div></table><div class=SRStatus id=Searching>Searching...</div><div class=SRStatus id=NoMatches>No Matches</div><script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults", "HTML");
+searchResults.Search();
+--></script></div><script language=JavaScript><!--
+if (browserType) {if (browserVer) {document.write("</div>"); }document.write("</div>");}// --></script></body></html>
\ No newline at end of file
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/VariablesD.html b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/VariablesD.html
new file mode 100644
index 0000000..d4b961d
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/VariablesD.html
@@ -0,0 +1,18 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd">
+
+<html><head><link rel="stylesheet" type="text/css" href="../styles/main.css"><script language=JavaScript src="../javascript/main.js"></script></head><body class="PopupSearchResultsPage" onLoad="NDOnLoad()"><script language=JavaScript><!--
+if (browserType) {document.write("<div class=" + browserType + ">");if (browserVer) {document.write("<div class=" + browserVer + ">"); }}// --></script>
+
+<!-- Copyright 2009 EEMBC -->
+<!-- saved from url=(0026)http://www.naturaldocs.org -->
+
+
+
+
+<div id=Index><div class=SRStatus id=Loading>Loading...</div><table border=0 cellspacing=0 cellpadding=0><div class=SRResult id=SR_default_undnum_undcontexts><div class=IEntry><a href="../files/linux/core_portme-h.html#default_num_contexts" target=_parent class=ISymbol>default_num_contexts</a></div></div></table><div class=SRStatus id=Searching>Searching...</div><div class=SRStatus id=NoMatches>No Matches</div><script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults", "HTML");
+searchResults.Search();
+--></script></div><script language=JavaScript><!--
+if (browserType) {if (browserVer) {document.write("</div>"); }document.write("</div>");}// --></script></body></html>
\ No newline at end of file
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/VariablesL.html b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/VariablesL.html
new file mode 100644
index 0000000..09e4b9a
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/VariablesL.html
@@ -0,0 +1,18 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd">
+
+<html><head><link rel="stylesheet" type="text/css" href="../styles/main.css"><script language=JavaScript src="../javascript/main.js"></script></head><body class="PopupSearchResultsPage" onLoad="NDOnLoad()"><script language=JavaScript><!--
+if (browserType) {document.write("<div class=" + browserType + ">");if (browserVer) {document.write("<div class=" + browserVer + ">"); }}// --></script>
+
+<!-- Copyright 2009 EEMBC -->
+<!-- saved from url=(0026)http://www.naturaldocs.org -->
+
+
+
+
+<div id=Index><div class=SRStatus id=Loading>Loading...</div><table border=0 cellspacing=0 cellpadding=0><div class=SRResult id=SR_LFLAGS_undEND><div class=IEntry><a href="javascript:searchResults.Toggle('SR_LFLAGS_undEND')" class=ISymbol>LFLAGS_END</a><div class=ISubIndex><a href="../files/linux/core_portme-mak.html#LFLAGS_END" target=_parent class=IFile>linux/<span class=HB> </span>core_portme.mak</a><a href="../files/PIC32/core_portme-mak.html#LFLAGS_END" target=_parent class=IFile>PIC32/<span class=HB> </span>core_portme.mak</a></div></div></div><div class=SRResult id=SR_LOAD><div class=IEntry><a href="../files/linux/core_portme-mak.html#LOAD" target=_parent class=ISymbol>LOAD</a></div></div></table><div class=SRStatus id=Searching>Searching...</div><div class=SRStatus id=NoMatches>No Matches</div><script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults", "HTML");
+searchResults.Search();
+--></script></div><script language=JavaScript><!--
+if (browserType) {if (browserVer) {document.write("</div>"); }document.write("</div>");}// --></script></body></html>
\ No newline at end of file
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/VariablesO.html b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/VariablesO.html
new file mode 100644
index 0000000..b14f180
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/VariablesO.html
@@ -0,0 +1,18 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd">
+
+<html><head><link rel="stylesheet" type="text/css" href="../styles/main.css"><script language=JavaScript src="../javascript/main.js"></script></head><body class="PopupSearchResultsPage" onLoad="NDOnLoad()"><script language=JavaScript><!--
+if (browserType) {document.write("<div class=" + browserType + ">");if (browserVer) {document.write("<div class=" + browserVer + ">"); }}// --></script>
+
+<!-- Copyright 2009 EEMBC -->
+<!-- saved from url=(0026)http://www.naturaldocs.org -->
+
+
+
+
+<div id=Index><div class=SRStatus id=Loading>Loading...</div><table border=0 cellspacing=0 cellpadding=0><div class=SRResult id=SR_OPATH><div class=IEntry><a href="javascript:searchResults.Toggle('SR_OPATH')" class=ISymbol>OPATH</a><div class=ISubIndex><a href="../files/linux/core_portme-mak.html#OPATH" target=_parent class=IFile>linux/<span class=HB> </span>core_portme.mak</a><a href="../files/PIC32/core_portme-mak.html#OPATH" target=_parent class=IFile>PIC32/<span class=HB> </span>core_portme.mak</a></div></div></div><div class=SRResult id=SR_OUTFLAG><div class=IEntry><a href="javascript:searchResults.Toggle('SR_OUTFLAG')" class=ISymbol>OUTFLAG</a><div class=ISubIndex><a href="../files/linux/core_portme-mak.html#OUTFLAG" target=_parent class=IFile>linux/<span class=HB> </span>core_portme.mak</a><a href="../files/PIC32/core_portme-mak.html#OUTFLAG" target=_parent class=IFile>PIC32/<span class=HB> </span>core_portme.mak</a></div></div></div></table><div class=SRStatus id=Searching>Searching...</div><div class=SRStatus id=NoMatches>No Matches</div><script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults", "HTML");
+searchResults.Search();
+--></script></div><script language=JavaScript><!--
+if (browserType) {if (browserVer) {document.write("</div>"); }document.write("</div>");}// --></script></body></html>
\ No newline at end of file
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/VariablesP.html b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/VariablesP.html
new file mode 100644
index 0000000..c687999
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/VariablesP.html
@@ -0,0 +1,18 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd">
+
+<html><head><link rel="stylesheet" type="text/css" href="../styles/main.css"><script language=JavaScript src="../javascript/main.js"></script></head><body class="PopupSearchResultsPage" onLoad="NDOnLoad()"><script language=JavaScript><!--
+if (browserType) {document.write("<div class=" + browserType + ">");if (browserVer) {document.write("<div class=" + browserVer + ">"); }}// --></script>
+
+<!-- Copyright 2009 EEMBC -->
+<!-- saved from url=(0026)http://www.naturaldocs.org -->
+
+
+
+
+<div id=Index><div class=SRStatus id=Loading>Loading...</div><table border=0 cellspacing=0 cellpadding=0><div class=SRResult id=SR_PERL><div class=IEntry><a href="javascript:searchResults.Toggle('SR_PERL')" class=ISymbol>PERL</a><div class=ISubIndex><a href="../files/linux/core_portme-mak.html#PERL" target=_parent class=IFile>linux/<span class=HB> </span>core_portme.mak</a><a href="../files/PIC32/core_portme-mak.html#PERL" target=_parent class=IFile>PIC32/<span class=HB> </span>core_portme.mak</a></div></div></div><div class=SRResult id=SR_PORT_undOBJS><div class=IEntry><a href="javascript:searchResults.Toggle('SR_PORT_undOBJS')" class=ISymbol>PORT_OBJS</a><div class=ISubIndex><a href="../files/linux/core_portme-mak.html#PORT_OBJS" target=_parent class=IFile>linux/<span class=HB> </span>core_portme.mak</a><a href="../files/PIC32/core_portme-mak.html#PORT_OBJS" target=_parent class=IFile>PIC32/<span class=HB> </span>core_portme.mak</a></div></div></div><div class=SRResult id=SR_PORT_undSRCS><div class=IEntry><a href="../files/linux/core_portme-mak.html#PORT_SRCS" target=_parent class=ISymbol>PORT_SRCS</a></div></div></table><div class=SRStatus id=Searching>Searching...</div><div class=SRStatus id=NoMatches>No Matches</div><script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults", "HTML");
+searchResults.Search();
+--></script></div><script language=JavaScript><!--
+if (browserType) {if (browserVer) {document.write("</div>"); }document.write("</div>");}// --></script></body></html>
\ No newline at end of file
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/VariablesR.html b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/VariablesR.html
new file mode 100644
index 0000000..9cd771d
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/VariablesR.html
@@ -0,0 +1,18 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd">
+
+<html><head><link rel="stylesheet" type="text/css" href="../styles/main.css"><script language=JavaScript src="../javascript/main.js"></script></head><body class="PopupSearchResultsPage" onLoad="NDOnLoad()"><script language=JavaScript><!--
+if (browserType) {document.write("<div class=" + browserType + ">");if (browserVer) {document.write("<div class=" + browserVer + ">"); }}// --></script>
+
+<!-- Copyright 2009 EEMBC -->
+<!-- saved from url=(0026)http://www.naturaldocs.org -->
+
+
+
+
+<div id=Index><div class=SRStatus id=Loading>Loading...</div><table border=0 cellspacing=0 cellpadding=0><div class=SRResult id=SR_RUN><div class=IEntry><a href="../files/linux/core_portme-mak.html#RUN" target=_parent class=ISymbol>RUN</a></div></div></table><div class=SRStatus id=Searching>Searching...</div><div class=SRStatus id=NoMatches>No Matches</div><script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults", "HTML");
+searchResults.Search();
+--></script></div><script language=JavaScript><!--
+if (browserType) {if (browserVer) {document.write("</div>"); }document.write("</div>");}// --></script></body></html>
\ No newline at end of file
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/VariablesS.html b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/VariablesS.html
new file mode 100644
index 0000000..a1280a7
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/search/VariablesS.html
@@ -0,0 +1,18 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd">
+
+<html><head><link rel="stylesheet" type="text/css" href="../styles/main.css"><script language=JavaScript src="../javascript/main.js"></script></head><body class="PopupSearchResultsPage" onLoad="NDOnLoad()"><script language=JavaScript><!--
+if (browserType) {document.write("<div class=" + browserType + ">");if (browserVer) {document.write("<div class=" + browserVer + ">"); }}// --></script>
+
+<!-- Copyright 2009 EEMBC -->
+<!-- saved from url=(0026)http://www.naturaldocs.org -->
+
+
+
+
+<div id=Index><div class=SRStatus id=Loading>Loading...</div><table border=0 cellspacing=0 cellpadding=0><div class=SRResult id=SR_SEPARATE_undCOMPILE><div class=IEntry><a href="javascript:searchResults.Toggle('SR_SEPARATE_undCOMPILE')" class=ISymbol>SEPARATE_COMPILE</a><div class=ISubIndex><a href="../files/linux/core_portme-mak.html#SEPARATE_COMPILE" target=_parent class=IFile>linux/<span class=HB> </span>core_portme.mak</a><a href="../files/PIC32/core_portme-mak.html#SEPARATE_COMPILE" target=_parent class=IFile>PIC32/<span class=HB> </span>core_portme.mak</a></div></div></div></table><div class=SRStatus id=Searching>Searching...</div><div class=SRStatus id=NoMatches>No Matches</div><script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults", "HTML");
+searchResults.Search();
+--></script></div><script language=JavaScript><!--
+if (browserType) {if (browserVer) {document.write("</div>"); }document.write("</div>");}// --></script></body></html>
\ No newline at end of file
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/styles/1.css b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/styles/1.css
new file mode 100644
index 0000000..d5a8bd6
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/styles/1.css
@@ -0,0 +1,767 @@
+/*
+ IMPORTANT: If you're editing this file in the output directory of one of
+ your projects, your changes will be overwritten the next time you run
+ Natural Docs. Instead, copy this file to your project directory, make your
+ changes, and you can use it with -s. Even better would be to make a CSS
+ file in your project directory with only your changes, which you can then
+ use with -s [original style] [your changes].
+
+ On the other hand, if you're editing this file in the Natural Docs styles
+ directory, the changes will automatically be applied to all your projects
+ that use this style the next time Natural Docs is run on them.
+
+ This file is part of Natural Docs, which is Copyright (C) 2003-2008 Greg Valure
+ Natural Docs is licensed under the GPL
+*/
+
+body {
+ font: 10pt Verdana, Arial, sans-serif;
+ color: #000000;
+ margin: 0; padding: 0;
+ }
+
+.ContentPage,
+.IndexPage,
+.FramedMenuPage {
+ background-color: #E8E8E8;
+ }
+.FramedContentPage,
+.FramedIndexPage,
+.FramedSearchResultsPage,
+.PopupSearchResultsPage {
+ background-color: #FFFFFF;
+ }
+
+
+a:link,
+a:visited { color: #900000; text-decoration: none }
+a:hover { color: #900000; text-decoration: underline }
+a:active { color: #FF0000; text-decoration: underline }
+
+td {
+ vertical-align: top }
+
+img { border: 0; }
+
+
+/*
+ Comment out this line to use web-style paragraphs (blank line between
+ paragraphs, no indent) instead of print-style paragraphs (no blank line,
+ indented.)
+*/
+p {
+ text-indent: 5ex; margin: 0 }
+
+
+/* Can't use something like display: none or it won't break. */
+.HB {
+ font-size: 1px;
+ visibility: hidden;
+ }
+
+/* Blockquotes are used as containers for things that may need to scroll. */
+blockquote {
+ padding: 0;
+ margin: 0;
+ overflow: auto;
+ }
+
+
+.Firefox1 blockquote {
+ padding-bottom: .5em;
+ }
+
+/* Turn off scrolling when printing. */
+@media print {
+ blockquote {
+ overflow: visible;
+ }
+ .IE blockquote {
+ width: auto;
+ }
+ }
+
+
+
+#Menu {
+ font-size: 9pt;
+ padding: 10px 0 0 0;
+ }
+.ContentPage #Menu,
+.IndexPage #Menu {
+ position: absolute;
+ top: 0;
+ left: 0;
+ width: 31ex;
+ overflow: hidden;
+ }
+.ContentPage .Firefox #Menu,
+.IndexPage .Firefox #Menu {
+ width: 27ex;
+ }
+
+
+ .MTitle {
+ font-size: 16pt; font-weight: bold; font-variant: small-caps;
+ text-align: center;
+ padding: 5px 10px 15px 10px;
+ border-bottom: 1px dotted #000000;
+ margin-bottom: 15px }
+
+ .MSubTitle {
+ font-size: 9pt; font-weight: normal; font-variant: normal;
+ margin-top: 1ex; margin-bottom: 5px }
+
+
+ .MEntry a:link,
+ .MEntry a:hover,
+ .MEntry a:visited { color: #606060; margin-right: 0 }
+ .MEntry a:active { color: #A00000; margin-right: 0 }
+
+
+ .MGroup {
+ font-variant: small-caps; font-weight: bold;
+ margin: 1em 0 1em 10px;
+ }
+
+ .MGroupContent {
+ font-variant: normal; font-weight: normal }
+
+ .MGroup a:link,
+ .MGroup a:hover,
+ .MGroup a:visited { color: #545454; margin-right: 10px }
+ .MGroup a:active { color: #A00000; margin-right: 10px }
+
+
+ .MFile,
+ .MText,
+ .MLink,
+ .MIndex {
+ padding: 1px 17px 2px 10px;
+ margin: .25em 0 .25em 0;
+ }
+
+ .MText {
+ font-size: 8pt; font-style: italic }
+
+ .MLink {
+ font-style: italic }
+
+ #MSelected {
+ color: #000000; background-color: #FFFFFF;
+ /* Replace padding with border. */
+ padding: 0 10px 0 10px;
+ border-width: 1px 2px 2px 0; border-style: solid; border-color: #000000;
+ margin-right: 5px;
+ }
+
+ /* Close off the left side when its in a group. */
+ .MGroup #MSelected {
+ padding-left: 9px; border-left-width: 1px }
+
+ /* A treat for Mozilla users. Blatantly non-standard. Will be replaced with CSS 3 attributes when finalized/supported. */
+ .Firefox #MSelected {
+ -moz-border-radius-topright: 10px;
+ -moz-border-radius-bottomright: 10px }
+ .Firefox .MGroup #MSelected {
+ -moz-border-radius-topleft: 10px;
+ -moz-border-radius-bottomleft: 10px }
+
+
+ #MSearchPanel {
+ padding: 0px 6px;
+ margin: .25em 0;
+ }
+
+
+ #MSearchField {
+ font: italic 9pt Verdana, sans-serif;
+ color: #606060;
+ background-color: #E8E8E8;
+ border: none;
+ padding: 2px 4px;
+ width: 100%;
+ }
+ /* Only Opera gets it right. */
+ .Firefox #MSearchField,
+ .IE #MSearchField,
+ .Safari #MSearchField {
+ width: 94%;
+ }
+ .Opera9 #MSearchField,
+ .Konqueror #MSearchField {
+ width: 97%;
+ }
+ .FramedMenuPage .Firefox #MSearchField,
+ .FramedMenuPage .Safari #MSearchField,
+ .FramedMenuPage .Konqueror #MSearchField {
+ width: 98%;
+ }
+
+ /* Firefox doesn't do this right in frames without #MSearchPanel added on.
+ It's presence doesn't hurt anything other browsers. */
+ #MSearchPanel.MSearchPanelInactive:hover #MSearchField {
+ background-color: #FFFFFF;
+ border: 1px solid #C0C0C0;
+ padding: 1px 3px;
+ }
+ .MSearchPanelActive #MSearchField {
+ background-color: #FFFFFF;
+ border: 1px solid #C0C0C0;
+ font-style: normal;
+ padding: 1px 3px;
+ }
+
+ #MSearchType {
+ visibility: hidden;
+ font: 8pt Verdana, sans-serif;
+ width: 98%;
+ padding: 0;
+ border: 1px solid #C0C0C0;
+ }
+ .MSearchPanelActive #MSearchType,
+ /* As mentioned above, Firefox doesn't do this right in frames without #MSearchPanel added on. */
+ #MSearchPanel.MSearchPanelInactive:hover #MSearchType,
+ #MSearchType:focus {
+ visibility: visible;
+ color: #606060;
+ }
+ #MSearchType option#MSearchEverything {
+ font-weight: bold;
+ }
+
+ .Opera8 .MSearchPanelInactive:hover,
+ .Opera8 .MSearchPanelActive {
+ margin-left: -1px;
+ }
+
+
+ iframe#MSearchResults {
+ width: 60ex;
+ height: 15em;
+ }
+ #MSearchResultsWindow {
+ display: none;
+ position: absolute;
+ left: 0; top: 0;
+ border: 1px solid #000000;
+ background-color: #E8E8E8;
+ }
+ #MSearchResultsWindowClose {
+ font-weight: bold;
+ font-size: 8pt;
+ display: block;
+ padding: 2px 5px;
+ }
+ #MSearchResultsWindowClose:link,
+ #MSearchResultsWindowClose:visited {
+ color: #000000;
+ text-decoration: none;
+ }
+ #MSearchResultsWindowClose:active,
+ #MSearchResultsWindowClose:hover {
+ color: #800000;
+ text-decoration: none;
+ background-color: #F4F4F4;
+ }
+
+
+
+
+#Content {
+ padding-bottom: 15px;
+ }
+
+.ContentPage #Content {
+ border-width: 0 0 1px 1px;
+ border-style: solid;
+ border-color: #000000;
+ background-color: #FFFFFF;
+ font-size: 9pt; /* To make 31ex match the menu's 31ex. */
+ margin-left: 31ex;
+ }
+.ContentPage .Firefox #Content {
+ margin-left: 27ex;
+ }
+
+
+
+ .CTopic {
+ font-size: 10pt;
+ margin-bottom: 3em;
+ }
+
+
+ .CTitle {
+ font-size: 12pt; font-weight: bold;
+ border-width: 0 0 1px 0; border-style: solid; border-color: #A0A0A0;
+ margin: 0 15px .5em 15px }
+
+ .CGroup .CTitle {
+ font-size: 16pt; font-variant: small-caps;
+ padding-left: 15px; padding-right: 15px;
+ border-width: 0 0 2px 0; border-color: #000000;
+ margin-left: 0; margin-right: 0 }
+
+ .CClass .CTitle,
+ .CInterface .CTitle,
+ .CDatabase .CTitle,
+ .CDatabaseTable .CTitle,
+ .CSection .CTitle {
+ font-size: 18pt;
+ color: #FFFFFF; background-color: #A0A0A0;
+ padding: 10px 15px 10px 15px;
+ border-width: 2px 0; border-color: #000000;
+ margin-left: 0; margin-right: 0 }
+
+ #MainTopic .CTitle {
+ font-size: 20pt;
+ color: #FFFFFF; background-color: #7070C0;
+ padding: 10px 15px 10px 15px;
+ border-width: 0 0 3px 0; border-color: #000000;
+ margin-left: 0; margin-right: 0 }
+
+ .CBody {
+ margin-left: 15px; margin-right: 15px }
+
+
+ .CToolTip {
+ position: absolute; visibility: hidden;
+ left: 0; top: 0;
+ background-color: #FFFFE0;
+ padding: 5px;
+ border-width: 1px 2px 2px 1px; border-style: solid; border-color: #000000;
+ font-size: 8pt;
+ }
+
+ .Opera .CToolTip {
+ max-width: 98%;
+ }
+
+ /* Scrollbars would be useless. */
+ .CToolTip blockquote {
+ overflow: hidden;
+ }
+ .IE6 .CToolTip blockquote {
+ overflow: visible;
+ }
+
+ .CHeading {
+ font-weight: bold; font-size: 10pt;
+ margin: 1.5em 0 .5em 0;
+ }
+
+ .CBody pre {
+ font: 10pt "Courier New", Courier, monospace;
+ margin: 1em 0;
+ }
+
+ .CBody ul {
+ /* I don't know why CBody's margin doesn't apply, but it's consistent across browsers so whatever.
+ Reapply it here as padding. */
+ padding-left: 15px; padding-right: 15px;
+ margin: .5em 5ex .5em 5ex;
+ }
+
+ .CDescriptionList {
+ margin: .5em 5ex 0 5ex }
+
+ .CDLEntry {
+ font: 10pt "Courier New", Courier, monospace; color: #808080;
+ padding-bottom: .25em;
+ white-space: nowrap }
+
+ .CDLDescription {
+ font-size: 10pt; /* For browsers that don't inherit correctly, like Opera 5. */
+ padding-bottom: .5em; padding-left: 5ex }
+
+
+ .CTopic img {
+ text-align: center;
+ display: block;
+ margin: 1em auto;
+ }
+ .CImageCaption {
+ font-variant: small-caps;
+ font-size: 8pt;
+ color: #808080;
+ text-align: center;
+ position: relative;
+ top: 1em;
+ }
+
+ .CImageLink {
+ color: #808080;
+ font-style: italic;
+ }
+ a.CImageLink:link,
+ a.CImageLink:visited,
+ a.CImageLink:hover { color: #808080 }
+
+
+
+
+
+.Prototype {
+ font: 10pt "Courier New", Courier, monospace;
+ padding: 5px 3ex;
+ border-width: 1px; border-style: solid;
+ margin: 0 5ex 1.5em 5ex;
+ }
+
+ .Prototype td {
+ font-size: 10pt;
+ }
+
+ .PDefaultValue,
+ .PDefaultValuePrefix,
+ .PTypePrefix {
+ color: #8F8F8F;
+ }
+ .PTypePrefix {
+ text-align: right;
+ }
+ .PAfterParameters {
+ vertical-align: bottom;
+ }
+
+ .IE .Prototype table {
+ padding: 0;
+ }
+
+ .CFunction .Prototype {
+ background-color: #F4F4F4; border-color: #D0D0D0 }
+ .CProperty .Prototype {
+ background-color: #F4F4FF; border-color: #C0C0E8 }
+ .CVariable .Prototype {
+ background-color: #FFFFF0; border-color: #E0E0A0 }
+
+ .CClass .Prototype {
+ border-width: 1px 2px 2px 1px; border-style: solid; border-color: #A0A0A0;
+ background-color: #F4F4F4;
+ }
+ .CInterface .Prototype {
+ border-width: 1px 2px 2px 1px; border-style: solid; border-color: #A0A0D0;
+ background-color: #F4F4FF;
+ }
+
+ .CDatabaseIndex .Prototype,
+ .CConstant .Prototype {
+ background-color: #D0D0D0; border-color: #000000 }
+ .CType .Prototype,
+ .CEnumeration .Prototype {
+ background-color: #FAF0F0; border-color: #E0B0B0;
+ }
+ .CDatabaseTrigger .Prototype,
+ .CEvent .Prototype,
+ .CDelegate .Prototype {
+ background-color: #F0FCF0; border-color: #B8E4B8 }
+
+ .CToolTip .Prototype {
+ margin: 0 0 .5em 0;
+ white-space: nowrap;
+ }
+
+
+
+
+
+.Summary {
+ margin: 1.5em 5ex 0 5ex }
+
+ .STitle {
+ font-size: 12pt; font-weight: bold;
+ margin-bottom: .5em }
+
+
+ .SBorder {
+ background-color: #FFFFF0;
+ padding: 15px;
+ border: 1px solid #C0C060 }
+
+ /* In a frame IE 6 will make them too long unless you set the width to 100%. Without frames it will be correct without a width
+ or slightly too long (but not enough to scroll) with a width. This arbitrary weirdness simply astounds me. IE 7 has the same
+ problem with frames, haven't tested it without. */
+ .FramedContentPage .IE .SBorder {
+ width: 100% }
+
+ /* A treat for Mozilla users. Blatantly non-standard. Will be replaced with CSS 3 attributes when finalized/supported. */
+ .Firefox .SBorder {
+ -moz-border-radius: 20px }
+
+
+ .STable {
+ font-size: 9pt; width: 100% }
+
+ .SEntry {
+ width: 30% }
+ .SDescription {
+ width: 70% }
+
+
+ .SMarked {
+ background-color: #F8F8D8 }
+
+ .SDescription { padding-left: 2ex }
+ .SIndent1 .SEntry { padding-left: 1.5ex } .SIndent1 .SDescription { padding-left: 3.5ex }
+ .SIndent2 .SEntry { padding-left: 3.0ex } .SIndent2 .SDescription { padding-left: 5.0ex }
+ .SIndent3 .SEntry { padding-left: 4.5ex } .SIndent3 .SDescription { padding-left: 6.5ex }
+ .SIndent4 .SEntry { padding-left: 6.0ex } .SIndent4 .SDescription { padding-left: 8.0ex }
+ .SIndent5 .SEntry { padding-left: 7.5ex } .SIndent5 .SDescription { padding-left: 9.5ex }
+
+ .SDescription a { color: #800000}
+ .SDescription a:active { color: #A00000 }
+
+ .SGroup td {
+ padding-top: .5em; padding-bottom: .25em }
+
+ .SGroup .SEntry {
+ font-weight: bold; font-variant: small-caps }
+
+ .SGroup .SEntry a { color: #800000 }
+ .SGroup .SEntry a:active { color: #F00000 }
+
+
+ .SMain td,
+ .SClass td,
+ .SDatabase td,
+ .SDatabaseTable td,
+ .SSection td {
+ font-size: 10pt;
+ padding-bottom: .25em }
+
+ .SClass td,
+ .SDatabase td,
+ .SDatabaseTable td,
+ .SSection td {
+ padding-top: 1em }
+
+ .SMain .SEntry,
+ .SClass .SEntry,
+ .SDatabase .SEntry,
+ .SDatabaseTable .SEntry,
+ .SSection .SEntry {
+ font-weight: bold;
+ }
+
+ .SMain .SEntry a,
+ .SClass .SEntry a,
+ .SDatabase .SEntry a,
+ .SDatabaseTable .SEntry a,
+ .SSection .SEntry a { color: #000000 }
+
+ .SMain .SEntry a:active,
+ .SClass .SEntry a:active,
+ .SDatabase .SEntry a:active,
+ .SDatabaseTable .SEntry a:active,
+ .SSection .SEntry a:active { color: #A00000 }
+
+
+
+
+
+.ClassHierarchy {
+ margin: 0 15px 1em 15px }
+
+ .CHEntry {
+ border-width: 1px 2px 2px 1px; border-style: solid; border-color: #A0A0A0;
+ margin-bottom: 3px;
+ padding: 2px 2ex;
+ font-size: 10pt;
+ background-color: #F4F4F4; color: #606060;
+ }
+
+ .Firefox .CHEntry {
+ -moz-border-radius: 4px;
+ }
+
+ .CHCurrent .CHEntry {
+ font-weight: bold;
+ border-color: #000000;
+ color: #000000;
+ }
+
+ .CHChildNote .CHEntry {
+ font-style: italic;
+ font-size: 8pt;
+ }
+
+ .CHIndent {
+ margin-left: 3ex;
+ }
+
+ .CHEntry a:link,
+ .CHEntry a:visited,
+ .CHEntry a:hover {
+ color: #606060;
+ }
+ .CHEntry a:active {
+ color: #800000;
+ }
+
+
+
+
+
+#Index {
+ background-color: #FFFFFF;
+ }
+
+/* As opposed to .PopupSearchResultsPage #Index */
+.IndexPage #Index,
+.FramedIndexPage #Index,
+.FramedSearchResultsPage #Index {
+ padding: 15px;
+ }
+
+.IndexPage #Index {
+ border-width: 0 0 1px 1px;
+ border-style: solid;
+ border-color: #000000;
+ font-size: 9pt; /* To make 27ex match the menu's 27ex. */
+ margin-left: 27ex;
+ }
+
+
+ .IPageTitle {
+ font-size: 20pt; font-weight: bold;
+ color: #FFFFFF; background-color: #7070C0;
+ padding: 10px 15px 10px 15px;
+ border-width: 0 0 3px 0; border-color: #000000; border-style: solid;
+ margin: -15px -15px 0 -15px }
+
+ .FramedSearchResultsPage .IPageTitle {
+ margin-bottom: 15px;
+ }
+
+ .INavigationBar {
+ font-size: 10pt;
+ text-align: center;
+ background-color: #FFFFF0;
+ padding: 5px;
+ border-bottom: solid 1px black;
+ margin: 0 -15px 15px -15px;
+ }
+
+ .INavigationBar a {
+ font-weight: bold }
+
+ .IHeading {
+ font-size: 16pt; font-weight: bold;
+ padding: 2.5em 0 .5em 0;
+ text-align: center;
+ width: 3.5ex;
+ }
+ #IFirstHeading {
+ padding-top: 0;
+ }
+
+ .IEntry {
+ font-size: 10pt;
+ padding-left: 1ex;
+ }
+ .PopupSearchResultsPage .IEntry {
+ font-size: 8pt;
+ padding: 1px 5px;
+ }
+ .PopupSearchResultsPage .Opera9 .IEntry,
+ .FramedSearchResultsPage .Opera9 .IEntry {
+ text-align: left;
+ }
+ .FramedSearchResultsPage .IEntry {
+ padding: 0;
+ }
+
+ .ISubIndex {
+ padding-left: 3ex; padding-bottom: .5em }
+ .PopupSearchResultsPage .ISubIndex {
+ display: none;
+ }
+
+ /* While it may cause some entries to look like links when they aren't, I found it's much easier to read the
+ index if everything's the same color. */
+ .ISymbol {
+ font-weight: bold; color: #900000 }
+
+ .IndexPage .ISymbolPrefix,
+ .FramedIndexPage .ISymbolPrefix {
+ font-size: 10pt;
+ text-align: right;
+ color: #C47C7C;
+ background-color: #F8F8F8;
+ border-right: 3px solid #E0E0E0;
+ border-left: 1px solid #E0E0E0;
+ padding: 0 1px 0 2px;
+ }
+ .PopupSearchResultsPage .ISymbolPrefix,
+ .FramedSearchResultsPage .ISymbolPrefix {
+ color: #900000;
+ }
+ .PopupSearchResultsPage .ISymbolPrefix {
+ font-size: 8pt;
+ }
+
+ .IndexPage #IFirstSymbolPrefix,
+ .FramedIndexPage #IFirstSymbolPrefix {
+ border-top: 1px solid #E0E0E0;
+ }
+ .IndexPage #ILastSymbolPrefix,
+ .FramedIndexPage #ILastSymbolPrefix {
+ border-bottom: 1px solid #E0E0E0;
+ }
+ .IndexPage #IOnlySymbolPrefix,
+ .FramedIndexPage #IOnlySymbolPrefix {
+ border-top: 1px solid #E0E0E0;
+ border-bottom: 1px solid #E0E0E0;
+ }
+
+ a.IParent,
+ a.IFile {
+ display: block;
+ }
+
+ .PopupSearchResultsPage .SRStatus {
+ padding: 2px 5px;
+ font-size: 8pt;
+ font-style: italic;
+ }
+ .FramedSearchResultsPage .SRStatus {
+ font-size: 10pt;
+ font-style: italic;
+ }
+
+ .SRResult {
+ display: none;
+ }
+
+
+
+#Footer {
+ font-size: 8pt;
+ color: #989898;
+ text-align: right;
+ }
+
+#Footer p {
+ text-indent: 0;
+ margin-bottom: .5em;
+ }
+
+.ContentPage #Footer,
+.IndexPage #Footer {
+ text-align: right;
+ margin: 2px;
+ }
+
+.FramedMenuPage #Footer {
+ text-align: center;
+ margin: 5em 10px 10px 10px;
+ padding-top: 1em;
+ border-top: 1px solid #C8C8C8;
+ }
+
+ #Footer a:link,
+ #Footer a:hover,
+ #Footer a:visited { color: #989898 }
+ #Footer a:active { color: #A00000 }
+
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/styles/2.css b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/styles/2.css
new file mode 100644
index 0000000..69a1d1a
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/styles/2.css
@@ -0,0 +1,6 @@
+#Menu {
+ padding: 48px 0 0 0;
+ background: url(file:../../coremark_logo.jpg) no-repeat;
+ background-position: 30px 10px;
+ }
+
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/styles/main.css b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/styles/main.css
new file mode 100644
index 0000000..a672a94
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/docs/html/styles/main.css
@@ -0,0 +1,2 @@
+@import URL("1.css");
+@import URL("2.css");
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/freebsd/core_portme.c b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/freebsd/core_portme.c
new file mode 100755
index 0000000..5c659c3
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/freebsd/core_portme.c
@@ -0,0 +1,335 @@
+/*
+Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Original Author: Shay Gal-on
+*/
+
+#include <stdio.h>
+#include <stdlib.h>
+#include "coremark.h"
+#if CALLGRIND_RUN
+#include <valgrind/callgrind.h>
+#endif
+
+#if (MEM_METHOD==MEM_MALLOC)
+/* Function: portable_malloc
+ Provide malloc() functionality in a platform specific way.
+*/
+void *portable_malloc(size_t size) {
+ return malloc(size);
+}
+/* Function: portable_free
+ Provide free() functionality in a platform specific way.
+*/
+void portable_free(void *p) {
+ free(p);
+}
+#else
+void *portable_malloc(size_t size) {
+ return NULL;
+}
+void portable_free(void *p) {
+ p=NULL;
+}
+#endif
+
+#if (SEED_METHOD==SEED_VOLATILE)
+#if VALIDATION_RUN
+ volatile ee_s32 seed1_volatile=0x3415;
+ volatile ee_s32 seed2_volatile=0x3415;
+ volatile ee_s32 seed3_volatile=0x66;
+#endif
+#if PERFORMANCE_RUN
+ volatile ee_s32 seed1_volatile=0x0;
+ volatile ee_s32 seed2_volatile=0x0;
+ volatile ee_s32 seed3_volatile=0x66;
+#endif
+#if PROFILE_RUN
+ volatile ee_s32 seed1_volatile=0x8;
+ volatile ee_s32 seed2_volatile=0x8;
+ volatile ee_s32 seed3_volatile=0x8;
+#endif
+ volatile ee_s32 seed4_volatile=ITERATIONS;
+ volatile ee_s32 seed5_volatile=0;
+#endif
+/* Porting: Timing functions
+ How to capture time and convert to seconds must be ported to whatever is supported by the platform.
+ e.g. Read value from on board RTC, read value from cpu clock cycles performance counter etc.
+ Sample implementation for standard time.h and windows.h definitions included.
+*/
+/* Define: TIMER_RES_DIVIDER
+ Divider to trade off timer resolution and total time that can be measured.
+
+ Use lower values to increase resolution, but make sure that overflow does not occur.
+ If there are issues with the return value overflowing, increase this value.
+ */
+#if USE_CLOCK
+ #define NSECS_PER_SEC CLOCKS_PER_SEC
+ #define EE_TIMER_TICKER_RATE 1000
+ #define CORETIMETYPE clock_t
+ #define GETMYTIME(_t) (*_t=clock())
+ #define MYTIMEDIFF(fin,ini) ((fin)-(ini))
+ #define TIMER_RES_DIVIDER 1
+ #define SAMPLE_TIME_IMPLEMENTATION 1
+#elif defined(_MSC_VER)
+ #define NSECS_PER_SEC 10000000
+ #define EE_TIMER_TICKER_RATE 1000
+ #define CORETIMETYPE FILETIME
+ #define GETMYTIME(_t) GetSystemTimeAsFileTime(_t)
+ #define MYTIMEDIFF(fin,ini) (((*(__int64*)&fin)-(*(__int64*)&ini))/TIMER_RES_DIVIDER)
+ /* setting to millisces resolution by default with MSDEV */
+ #ifndef TIMER_RES_DIVIDER
+ #define TIMER_RES_DIVIDER 1000
+ #endif
+ #define SAMPLE_TIME_IMPLEMENTATION 1
+#elif HAS_TIME_H
+ #define NSECS_PER_SEC 1000000000
+ #define EE_TIMER_TICKER_RATE 1000
+ #define CORETIMETYPE struct timespec
+ #define GETMYTIME(_t) clock_gettime(CLOCK_REALTIME,_t)
+ #define MYTIMEDIFF(fin,ini) ((fin.tv_sec-ini.tv_sec)*(NSECS_PER_SEC/TIMER_RES_DIVIDER)+(fin.tv_nsec-ini.tv_nsec)/TIMER_RES_DIVIDER)
+ /* setting to 1/1000 of a second resolution by default with linux */
+ #ifndef TIMER_RES_DIVIDER
+ #define TIMER_RES_DIVIDER 1000000
+ #endif
+ #define SAMPLE_TIME_IMPLEMENTATION 1
+#else
+ #define SAMPLE_TIME_IMPLEMENTATION 0
+#endif
+#define EE_TICKS_PER_SEC (NSECS_PER_SEC / TIMER_RES_DIVIDER)
+
+#if SAMPLE_TIME_IMPLEMENTATION
+/** Define Host specific (POSIX), or target specific global time variables. */
+static CORETIMETYPE start_time_val, stop_time_val;
+
+/* Function: start_time
+ This function will be called right before starting the timed portion of the benchmark.
+
+ Implementation may be capturing a system timer (as implemented in the example code)
+ or zeroing some system parameters - e.g. setting the cpu clocks cycles to 0.
+*/
+void start_time(void) {
+ GETMYTIME(&start_time_val );
+#if CALLGRIND_RUN
+ CALLGRIND_START_INSTRUMENTATION
+#endif
+#if MICA
+ asm volatile("int3");/*1 */
+#endif
+}
+/* Function: stop_time
+ This function will be called right after ending the timed portion of the benchmark.
+
+ Implementation may be capturing a system timer (as implemented in the example code)
+ or other system parameters - e.g. reading the current value of cpu cycles counter.
+*/
+void stop_time(void) {
+#if CALLGRIND_RUN
+ CALLGRIND_STOP_INSTRUMENTATION
+#endif
+#if MICA
+ asm volatile("int3");/*1 */
+#endif
+ GETMYTIME(&stop_time_val );
+}
+/* Function: get_time
+ Return an abstract "ticks" number that signifies time on the system.
+
+ Actual value returned may be cpu cycles, milliseconds or any other value,
+ as long as it can be converted to seconds by <time_in_secs>.
+ This methodology is taken to accomodate any hardware or simulated platform.
+ The sample implementation returns millisecs by default,
+ and the resolution is controlled by <TIMER_RES_DIVIDER>
+*/
+CORE_TICKS get_time(void) {
+ CORE_TICKS elapsed=(CORE_TICKS)(MYTIMEDIFF(stop_time_val, start_time_val));
+ return elapsed;
+}
+/* Function: time_in_secs
+ Convert the value returned by get_time to seconds.
+
+ The <secs_ret> type is used to accomodate systems with no support for floating point.
+ Default implementation implemented by the EE_TICKS_PER_SEC macro above.
+*/
+secs_ret time_in_secs(CORE_TICKS ticks) {
+ secs_ret retval=((secs_ret)ticks) / (secs_ret)EE_TICKS_PER_SEC;
+ return retval;
+}
+#else
+#error "Please implement timing functionality in core_portme.c"
+#endif /* SAMPLE_TIME_IMPLEMENTATION */
+
+ee_u32 default_num_contexts=MULTITHREAD;
+
+/* Function: portable_init
+ Target specific initialization code
+ Test for some common mistakes.
+*/
+void portable_init(core_portable *p, int *argc, char *argv[])
+{
+#if PRINT_ARGS
+ int i;
+ for (i=0; i<*argc; i++) {
+ ee_printf("Arg[%d]=%s\n",i,argv[i]);
+ }
+#endif
+ if (sizeof(ee_ptr_int) != sizeof(ee_u8 *)) {
+ ee_printf("ERROR! Please define ee_ptr_int to a type that holds a pointer!\n");
+ }
+ if (sizeof(ee_u32) != 4) {
+ ee_printf("ERROR! Please define ee_u32 to a 32b unsigned type!\n");
+ }
+#if (MAIN_HAS_NOARGC && (SEED_METHOD==SEED_ARG))
+ ee_printf("ERROR! Main has no argc, but SEED_METHOD defined to SEED_ARG!\n");
+#endif
+
+#if (MULTITHREAD>1) && (SEED_METHOD==SEED_ARG)
+ int nargs=*argc,i;
+ if ((nargs>1) && (*argv[1]=='M')) {
+ default_num_contexts=parseval(argv[1]+1);
+ if (default_num_contexts>MULTITHREAD)
+ default_num_contexts=MULTITHREAD;
+ /* Shift args since first arg is directed to the portable part and not to coremark main */
+ --nargs;
+ for (i=1; i<nargs; i++)
+ argv[i]=argv[i+1];
+ *argc=nargs;
+ }
+#endif /* sample of potential platform specific init via command line, reset the number of contexts being used if first argument is M<n>*/
+ p->portable_id=1;
+}
+/* Function: portable_fini
+ Target specific final code
+*/
+void portable_fini(core_portable *p)
+{
+ p->portable_id=0;
+}
+
+#if (MULTITHREAD>1)
+
+/* Function: core_start_parallel
+ Start benchmarking in a parallel context.
+
+ Three implementations are provided, one using pthreads, one using fork and shared mem, and one using fork and sockets.
+ Other implementations using MCAPI or other standards can easily be devised.
+*/
+/* Function: core_stop_parallel
+ Stop a parallel context execution of coremark, and gather the results.
+
+ Three implementations are provided, one using pthreads, one using fork and shared mem, and one using fork and sockets.
+ Other implementations using MCAPI or other standards can easily be devised.
+*/
+#if USE_PTHREAD
+ee_u8 core_start_parallel(core_results *res) {
+ return (ee_u8)pthread_create(&(res->port.thread),NULL,iterate,(void *)res);
+}
+ee_u8 core_stop_parallel(core_results *res) {
+ void *retval;
+ return (ee_u8)pthread_join(res->port.thread,&retval);
+}
+#elif USE_FORK
+static int key_id=0;
+ee_u8 core_start_parallel(core_results *res) {
+ key_t key=4321+key_id;
+ key_id++;
+ res->port.pid=fork();
+ res->port.shmid=shmget(key, 8, IPC_CREAT | 0666);
+ if (res->port.shmid<0) {
+ ee_printf("ERROR in shmget!\n");
+ }
+ if (res->port.pid==0) {
+ iterate(res);
+ res->port.shm=shmat(res->port.shmid, NULL, 0);
+ /* copy the validation values to the shared memory area and quit*/
+ if (res->port.shm == (char *) -1) {
+ ee_printf("ERROR in child shmat!\n");
+ } else {
+ memcpy(res->port.shm,&(res->crc),8);
+ shmdt(res->port.shm);
+ }
+ exit(0);
+ }
+ return 1;
+}
+ee_u8 core_stop_parallel(core_results *res) {
+ int status;
+ pid_t wpid = waitpid(res->port.pid,&status,WUNTRACED);
+ if (wpid != res->port.pid) {
+ ee_printf("ERROR waiting for child.\n");
+ if (errno == ECHILD) ee_printf("errno=No such child %d\n",res->port.pid);
+ if (errno == EINTR) ee_printf("errno=Interrupted\n");
+ return 0;
+ }
+ /* after process is done, get the values from the shared memory area */
+ res->port.shm=shmat(res->port.shmid, NULL, 0);
+ if (res->port.shm == (char *) -1) {
+ ee_printf("ERROR in parent shmat!\n");
+ return 0;
+ }
+ memcpy(&(res->crc),res->port.shm,8);
+ shmdt(res->port.shm);
+ return 1;
+}
+#elif USE_SOCKET
+static int key_id=0;
+ee_u8 core_start_parallel(core_results *res) {
+ int bound, buffer_length=8;
+ res->port.sa.sin_family = AF_INET;
+ res->port.sa.sin_addr.s_addr = htonl(0x7F000001);
+ res->port.sa.sin_port = htons(7654+key_id);
+ key_id++;
+ res->port.pid=fork();
+ if (res->port.pid==0) { /* benchmark child */
+ iterate(res);
+ res->port.sock = socket(PF_INET, SOCK_DGRAM, IPPROTO_UDP);
+ if (-1 == res->port.sock) /* if socket failed to initialize, exit */ {
+ ee_printf("Error Creating Socket");
+ } else {
+ int bytes_sent = sendto(res->port.sock, &(res->crc), buffer_length, 0,(struct sockaddr*)&(res->port.sa), sizeof (struct sockaddr_in));
+ if (bytes_sent < 0)
+ ee_printf("Error sending packet: %s\n", strerror(errno));
+ close(res->port.sock); /* close the socket */
+ }
+ exit(0);
+ }
+ /* parent process, open the socket */
+ res->port.sock = socket(PF_INET, SOCK_DGRAM, IPPROTO_UDP);
+ bound = bind(res->port.sock,(struct sockaddr*)&(res->port.sa), sizeof(struct sockaddr));
+ if (bound < 0)
+ ee_printf("bind(): %s\n",strerror(errno));
+ return 1;
+}
+ee_u8 core_stop_parallel(core_results *res) {
+ int status;
+ int fromlen=sizeof(struct sockaddr);
+ int recsize = recvfrom(res->port.sock, &(res->crc), 8, 0, (struct sockaddr*)&(res->port.sa), &fromlen);
+ if (recsize < 0) {
+ ee_printf("Error in receive: %s\n", strerror(errno));
+ return 0;
+ }
+ pid_t wpid = waitpid(res->port.pid,&status,WUNTRACED);
+ if (wpid != res->port.pid) {
+ ee_printf("ERROR waiting for child.\n");
+ if (errno == ECHILD) ee_printf("errno=No such child %d\n",res->port.pid);
+ if (errno == EINTR) ee_printf("errno=Interrupted\n");
+ return 0;
+ }
+ return 1;
+}
+#else /* no standard multicore implementation */
+#error "Please implement multicore functionality in core_portme.c to use multiple contexts."
+#endif /* multithread implementations */
+#endif
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/freebsd/core_portme.h b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/freebsd/core_portme.h
new file mode 100755
index 0000000..fccd6b5
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/freebsd/core_portme.h
@@ -0,0 +1,291 @@
+/*
+Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Original Author: Shay Gal-on
+*/
+
+/* Topic: Description
+ This file contains configuration constants required to execute on different platforms
+*/
+#ifndef CORE_PORTME_H
+#define CORE_PORTME_H
+/************************/
+/* Data types and settings */
+/************************/
+/* Configuration: HAS_FLOAT
+ Define to 1 if the platform supports floating point.
+*/
+#ifndef HAS_FLOAT
+#define HAS_FLOAT 1
+#endif
+/* Configuration: HAS_TIME_H
+ Define to 1 if platform has the time.h header file,
+ and implementation of functions thereof.
+*/
+#ifndef HAS_TIME_H
+#define HAS_TIME_H 1
+#endif
+/* Configuration: USE_CLOCK
+ Define to 1 if platform has the time.h header file,
+ and implementation of functions thereof.
+*/
+#ifndef USE_CLOCK
+#define USE_CLOCK 0
+#endif
+/* Configuration: HAS_STDIO
+ Define to 1 if the platform has stdio.h.
+*/
+#ifndef HAS_STDIO
+#define HAS_STDIO 1
+#endif
+/* Configuration: HAS_PRINTF
+ Define to 1 if the platform has stdio.h and implements the printf function.
+*/
+#ifndef HAS_PRINTF
+#define HAS_PRINTF 1
+#endif
+
+/* Configuration: CORE_TICKS
+ Define type of return from the timing functions.
+ */
+#if defined(_MSC_VER)
+#include <windows.h>
+typedef size_t CORE_TICKS;
+#elif HAS_TIME_H
+#include <time.h>
+typedef clock_t CORE_TICKS;
+#else
+#error "Please define type of CORE_TICKS and implement start_time, end_time get_time and time_in_secs functions!"
+#endif
+
+/* Definitions: COMPILER_VERSION, COMPILER_FLAGS, MEM_LOCATION
+ Initialize these strings per platform
+*/
+#ifndef COMPILER_VERSION
+ #ifdef __GNUC__
+ #define COMPILER_VERSION "GCC"__VERSION__
+ #else
+ #define COMPILER_VERSION "Please put compiler version here (e.g. gcc 4.1)"
+ #endif
+#endif
+#ifndef COMPILER_FLAGS
+ #define COMPILER_FLAGS FLAGS_STR /* "Please put compiler flags here (e.g. -o3)" */
+#endif
+#ifndef MEM_LOCATION
+ #define MEM_LOCATION "Please put data memory location here\n\t\t\t(e.g. code in flash, data on heap etc)"
+ #define MEM_LOCATION_UNSPEC 1
+#endif
+
+/* Data Types:
+ To avoid compiler issues, define the data types that need ot be used for 8b, 16b and 32b in <core_portme.h>.
+
+ *Imprtant*:
+ ee_ptr_int needs to be the data type used to hold pointers, otherwise coremark may fail!!!
+*/
+typedef signed short ee_s16;
+typedef unsigned short ee_u16;
+typedef signed int ee_s32;
+typedef double ee_f32;
+typedef unsigned char ee_u8;
+typedef unsigned int ee_u32;
+typedef unsigned long ee_ptr_int;
+typedef size_t ee_size_t;
+/* align an offset to point to a 32b value */
+#define align_mem(x) (void *)(4 + (((ee_ptr_int)(x) - 1) & ~3))
+
+/* Configuration: SEED_METHOD
+ Defines method to get seed values that cannot be computed at compile time.
+
+ Valid values:
+ SEED_ARG - from command line.
+ SEED_FUNC - from a system function.
+ SEED_VOLATILE - from volatile variables.
+*/
+#ifndef SEED_METHOD
+#define SEED_METHOD SEED_ARG
+#endif
+
+/* Configuration: MEM_METHOD
+ Defines method to get a block of memry.
+
+ Valid values:
+ MEM_MALLOC - for platforms that implement malloc and have malloc.h.
+ MEM_STATIC - to use a static memory array.
+ MEM_STACK - to allocate the data block on the stack (NYI).
+*/
+#ifndef MEM_METHOD
+#define MEM_METHOD MEM_MALLOC
+#endif
+
+/* Configuration: MULTITHREAD
+ Define for parallel execution
+
+ Valid values:
+ 1 - only one context (default).
+ N>1 - will execute N copies in parallel.
+
+ Note:
+ If this flag is defined to more then 1, an implementation for launching parallel contexts must be defined.
+
+ Two sample implementations are provided. Use <USE_PTHREAD> or <USE_FORK> to enable them.
+
+ It is valid to have a different implementation of <core_start_parallel> and <core_end_parallel> in <core_portme.c>,
+ to fit a particular architecture.
+*/
+#ifndef MULTITHREAD
+#define MULTITHREAD 1
+#endif
+
+/* Configuration: USE_PTHREAD
+ Sample implementation for launching parallel contexts
+ This implementation uses pthread_thread_create and pthread_join.
+
+ Valid values:
+ 0 - Do not use pthreads API.
+ 1 - Use pthreads API
+
+ Note:
+ This flag only matters if MULTITHREAD has been defined to a value greater then 1.
+*/
+#ifndef USE_PTHREAD
+#define USE_PTHREAD 0
+#endif
+
+/* Configuration: USE_FORK
+ Sample implementation for launching parallel contexts
+ This implementation uses fork, waitpid, shmget,shmat and shmdt.
+
+ Valid values:
+ 0 - Do not use fork API.
+ 1 - Use fork API
+
+ Note:
+ This flag only matters if MULTITHREAD has been defined to a value greater then 1.
+*/
+#ifndef USE_FORK
+#define USE_FORK 0
+#endif
+
+/* Configuration: USE_SOCKET
+ Sample implementation for launching parallel contexts
+ This implementation uses fork, socket, sendto and recvfrom
+
+ Valid values:
+ 0 - Do not use fork and sockets API.
+ 1 - Use fork and sockets API
+
+ Note:
+ This flag only matters if MULTITHREAD has been defined to a value greater then 1.
+*/
+#ifndef USE_SOCKET
+#define USE_SOCKET 0
+#endif
+
+/* Configuration: MAIN_HAS_NOARGC
+ Needed if platform does not support getting arguments to main.
+
+ Valid values:
+ 0 - argc/argv to main is supported
+ 1 - argc/argv to main is not supported
+*/
+#ifndef MAIN_HAS_NOARGC
+#define MAIN_HAS_NOARGC 0
+#endif
+
+/* Configuration: MAIN_HAS_NORETURN
+ Needed if platform does not support returning a value from main.
+
+ Valid values:
+ 0 - main returns an int, and return value will be 0.
+ 1 - platform does not support returning a value from main
+*/
+#ifndef MAIN_HAS_NORETURN
+#define MAIN_HAS_NORETURN 0
+#endif
+
+/* Variable: default_num_contexts
+ Number of contexts to spawn in multicore context.
+ Override this global value to change number of contexts used.
+
+ Note:
+ This value may not be set higher then the <MULTITHREAD> define.
+
+ To experiment, you can set the <MULTITHREAD> define to the highest value expected, and use argc/argv in the <portable_init> to set this value from the command line.
+*/
+extern ee_u32 default_num_contexts;
+
+#if (MULTITHREAD>1)
+#if USE_PTHREAD
+ #include <pthread.h>
+ #define PARALLEL_METHOD "PThreads"
+#elif USE_FORK
+ #include <unistd.h>
+ #include <errno.h>
+ #include <sys/wait.h>
+ #include <sys/shm.h>
+ #include <string.h> /* for memcpy */
+ #define PARALLEL_METHOD "Fork"
+#elif USE_SOCKET
+ #include <sys/types.h>
+ #include <sys/socket.h>
+ #include <netinet/in.h>
+ #include <arpa/inet.h>
+ #include <sys/wait.h>
+ #include <stdio.h>
+ #include <stdlib.h>
+ #include <string.h>
+ #include <unistd.h>
+ #include <errno.h>
+ #define PARALLEL_METHOD "Sockets"
+#else
+ #define PARALLEL_METHOD "Proprietary"
+ #error "Please implement multicore functionality in core_portme.c to use multiple contexts."
+#endif /* Method for multithreading */
+#endif /* MULTITHREAD > 1 */
+
+typedef struct CORE_PORTABLE_S {
+#if (MULTITHREAD>1)
+ #if USE_PTHREAD
+ pthread_t thread;
+ #elif USE_FORK
+ pid_t pid;
+ int shmid;
+ void *shm;
+ #elif USE_SOCKET
+ pid_t pid;
+ int sock;
+ struct sockaddr_in sa;
+ #endif /* Method for multithreading */
+#endif /* MULTITHREAD>1 */
+ ee_u8 portable_id;
+} core_portable;
+
+/* target specific init/fini */
+void portable_init(core_portable *p, int *argc, char *argv[]);
+void portable_fini(core_portable *p);
+
+#if (SEED_METHOD==SEED_VOLATILE)
+ #if (VALIDATION_RUN || PERFORMANCE_RUN || PROFILE_RUN)
+ #define RUN_TYPE_FLAG 1
+ #else
+ #if (TOTAL_DATA_SIZE==1200)
+ #define PROFILE_RUN 1
+ #else
+ #define PERFORMANCE_RUN 1
+ #endif
+ #endif
+#endif /* SEED_METHOD==SEED_VOLATILE */
+
+#endif /* CORE_PORTME_H */
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/freebsd/core_portme.mak b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/freebsd/core_portme.mak
new file mode 100755
index 0000000..fbb8f08
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/freebsd/core_portme.mak
@@ -0,0 +1,140 @@
+# Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# Original Author: Shay Gal-on
+
+#File: core_portme.mak
+
+# Flag: OUTFLAG
+# Use this flag to define how to to get an executable (e.g -o)
+OUTFLAG= -o
+# Flag: CC
+# Use this flag to define compiler to use
+CC?= cc
+# Flag: CFLAGS
+# Use this flag to define compiler options. Note, you can add compiler options from the command line using XCFLAGS="other flags"
+PORT_CFLAGS = -O2
+FLAGS_STR = "$(PORT_CFLAGS) $(XCFLAGS) $(XLFLAGS) $(LFLAGS_END)"
+CFLAGS = $(PORT_CFLAGS) -I$(PORT_DIR) -I. -DFLAGS_STR=\"$(FLAGS_STR)\"
+#Flag: LFLAGS_END
+# Define any libraries needed for linking or other flags that should come at the end of the link line (e.g. linker scripts).
+# Note: On certain platforms, the default clock_gettime implementation is supported but requires linking of librt.
+LFLAGS_END += -lrt
+# Flag: PORT_SRCS
+# Port specific source files can be added here
+PORT_SRCS = $(PORT_DIR)/core_portme.c
+# Flag: LOAD
+# Define this flag if you need to load to a target, as in a cross compile environment.
+
+# Flag: RUN
+# Define this flag if running does not consist of simple invocation of the binary.
+# In a cross compile environment, you need to define this.
+
+#For flashing and using a tera term macro, you could use
+#LOAD = flash ADDR
+#RUN = ttpmacro coremark.ttl
+
+#For copying to target and executing via SSH connection, you could use
+#LOAD = scp $(OUTFILE) user@target:~
+#RUN = ssh user@target -c
+
+#For native compilation and execution
+LOAD = echo Loading done
+RUN =
+
+OEXT = .o
+EXE = .exe
+
+# Flag: SEPARATE_COMPILE
+# Define if you need to separate compilation from link stage.
+# In this case, you also need to define below how to create an object file, and how to link.
+ifdef SEPARATE_COMPILE
+
+LD = gcc
+OBJOUT = -o
+LFLAGS =
+OFLAG = -o
+COUT = -c
+# Flag: PORT_OBJS
+# Port specific object files can be added here
+PORT_OBJS = $(PORT_DIR)/core_portme$(OEXT)
+PORT_CLEAN = *$(OEXT)
+
+$(OPATH)%$(OEXT) : %.c
+ $(CC) $(CFLAGS) $(XCFLAGS) $(COUT) $< $(OBJOUT) $@
+
+endif
+
+# Target: port_prebuild
+# Generate any files that are needed before actual build starts.
+# E.g. generate profile guidance files. Sample PGO generation for gcc enabled with PGO=1
+# - First, check if PGO was defined on the command line, if so, need to add -fprofile-use to compile line.
+# - Second, if PGO reference has not yet been generated, add a step to the prebuild that will build a profile-generate version and run it.
+# Note - Using REBUILD=1
+#
+# Use make PGO=1 to invoke this sample processing.
+
+ifdef PGO
+ ifeq (,$(findstring $(PGO),gen))
+ PGO_STAGE=build_pgo_gcc
+ CFLAGS+=-fprofile-use
+ endif
+ PORT_CLEAN+=*.gcda *.gcno gmon.out
+endif
+
+.PHONY: port_prebuild
+port_prebuild: $(PGO_STAGE)
+
+.PHONY: build_pgo_gcc
+build_pgo_gcc:
+ $(MAKE) PGO=gen XCFLAGS="$(XCFLAGS) -fprofile-generate -DTOTAL_DATA_SIZE=1200" ITERATIONS=10 gen_pgo_data REBUILD=1
+
+# Target: port_postbuild
+# Generate any files that are needed after actual build end.
+# E.g. change format to srec, bin, zip in order to be able to load into flash
+.PHONY: port_postbuild
+port_postbuild:
+
+# Target: port_postrun
+# Do platform specific after run stuff.
+# E.g. reset the board, backup the logfiles etc.
+.PHONY: port_postrun
+port_postrun:
+
+# Target: port_prerun
+# Do platform specific after run stuff.
+# E.g. reset the board, backup the logfiles etc.
+.PHONY: port_prerun
+port_prerun:
+
+# Target: port_postload
+# Do platform specific after load stuff.
+# E.g. reset the reset power to the flash eraser
+.PHONY: port_postload
+port_postload:
+
+# Target: port_preload
+# Do platform specific before load stuff.
+# E.g. reset the reset power to the flash eraser
+.PHONY: port_preload
+port_preload:
+
+# FLAG: OPATH
+# Path to the output folder. Default - current folder.
+OPATH = ./
+MKDIR = mkdir -p
+
+# FLAG: PERL
+# Define perl executable to calculate the geomean if running separate.
+PERL=/usr/bin/perl
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/linux/core_portme.c b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/linux/core_portme.c
new file mode 100755
index 0000000..6b63610
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/linux/core_portme.c
@@ -0,0 +1,338 @@
+/*
+Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Original Author: Shay Gal-on
+*/
+
+#include <stdio.h>
+#include <stdlib.h>
+#include "coremark.h"
+#if CALLGRIND_RUN
+#include <valgrind/callgrind.h>
+#endif
+
+#if (MEM_METHOD==MEM_MALLOC)
+#include <malloc.h>
+/* Function: portable_malloc
+ Provide malloc() functionality in a platform specific way.
+*/
+void *portable_malloc(size_t size) {
+ return malloc(size);
+}
+/* Function: portable_free
+ Provide free() functionality in a platform specific way.
+*/
+void portable_free(void *p) {
+ free(p);
+}
+#else
+void *portable_malloc(size_t size) {
+ return NULL;
+}
+void portable_free(void *p) {
+ p=NULL;
+}
+#endif
+
+#if (SEED_METHOD==SEED_VOLATILE)
+#if VALIDATION_RUN
+ volatile ee_s32 seed1_volatile=0x3415;
+ volatile ee_s32 seed2_volatile=0x3415;
+ volatile ee_s32 seed3_volatile=0x66;
+#endif
+#if PERFORMANCE_RUN
+ volatile ee_s32 seed1_volatile=0x0;
+ volatile ee_s32 seed2_volatile=0x0;
+ volatile ee_s32 seed3_volatile=0x66;
+#endif
+#if PROFILE_RUN
+ volatile ee_s32 seed1_volatile=0x8;
+ volatile ee_s32 seed2_volatile=0x8;
+ volatile ee_s32 seed3_volatile=0x8;
+#endif
+ volatile ee_s32 seed4_volatile=ITERATIONS;
+ volatile ee_s32 seed5_volatile=0;
+#endif
+/* Porting: Timing functions
+ How to capture time and convert to seconds must be ported to whatever is supported by the platform.
+ e.g. Read value from on board RTC, read value from cpu clock cycles performance counter etc.
+ Sample implementation for standard time.h and windows.h definitions included.
+*/
+/* Define: TIMER_RES_DIVIDER
+ Divider to trade off timer resolution and total time that can be measured.
+
+ Use lower values to increase resolution, but make sure that overflow does not occur.
+ If there are issues with the return value overflowing, increase this value.
+ */
+#if USE_CLOCK
+ #define NSECS_PER_SEC CLOCKS_PER_SEC
+ #define EE_TIMER_TICKER_RATE 1000
+ #define CORETIMETYPE clock_t
+ #define GETMYTIME(_t) (*_t=clock())
+ #define MYTIMEDIFF(fin,ini) ((fin)-(ini))
+ #define TIMER_RES_DIVIDER 1
+ #define SAMPLE_TIME_IMPLEMENTATION 1
+#elif defined(_MSC_VER)
+ #define NSECS_PER_SEC 10000000
+ #define EE_TIMER_TICKER_RATE 1000
+ #define CORETIMETYPE FILETIME
+ #define GETMYTIME(_t) GetSystemTimeAsFileTime(_t)
+ #define MYTIMEDIFF(fin,ini) (((*(__int64*)&fin)-(*(__int64*)&ini))/TIMER_RES_DIVIDER)
+ /* setting to millisces resolution by default with MSDEV */
+ #ifndef TIMER_RES_DIVIDER
+ #define TIMER_RES_DIVIDER 1000
+ #endif
+ #define SAMPLE_TIME_IMPLEMENTATION 1
+#elif HAS_TIME_H
+ #define NSECS_PER_SEC 1000000000
+ #define EE_TIMER_TICKER_RATE 1000
+ #define CORETIMETYPE struct timespec
+ #define GETMYTIME(_t) clock_gettime(CLOCK_REALTIME,_t)
+ #define MYTIMEDIFF(fin,ini) ((fin.tv_sec-ini.tv_sec)*(NSECS_PER_SEC/TIMER_RES_DIVIDER)+(fin.tv_nsec-ini.tv_nsec)/TIMER_RES_DIVIDER)
+ /* setting to 1/1000 of a second resolution by default with linux */
+ #ifndef TIMER_RES_DIVIDER
+ #define TIMER_RES_DIVIDER 1000000
+ #endif
+ #define SAMPLE_TIME_IMPLEMENTATION 1
+#else
+ #define SAMPLE_TIME_IMPLEMENTATION 0
+#endif
+#define EE_TICKS_PER_SEC (NSECS_PER_SEC / TIMER_RES_DIVIDER)
+
+#if SAMPLE_TIME_IMPLEMENTATION
+/** Define Host specific (POSIX), or target specific global time variables. */
+static CORETIMETYPE start_time_val, stop_time_val;
+
+/* Function: start_time
+ This function will be called right before starting the timed portion of the benchmark.
+
+ Implementation may be capturing a system timer (as implemented in the example code)
+ or zeroing some system parameters - e.g. setting the cpu clocks cycles to 0.
+*/
+void start_time(void) {
+ GETMYTIME(&start_time_val );
+#if CALLGRIND_RUN
+ CALLGRIND_START_INSTRUMENTATION
+#endif
+#if MICA
+ asm volatile("int3");/*1 */
+#endif
+}
+/* Function: stop_time
+ This function will be called right after ending the timed portion of the benchmark.
+
+ Implementation may be capturing a system timer (as implemented in the example code)
+ or other system parameters - e.g. reading the current value of cpu cycles counter.
+*/
+void stop_time(void) {
+#if CALLGRIND_RUN
+ CALLGRIND_STOP_INSTRUMENTATION
+#endif
+#if MICA
+ asm volatile("int3");/*1 */
+#endif
+ GETMYTIME(&stop_time_val );
+}
+/* Function: get_time
+ Return an abstract "ticks" number that signifies time on the system.
+
+ Actual value returned may be cpu cycles, milliseconds or any other value,
+ as long as it can be converted to seconds by <time_in_secs>.
+ This methodology is taken to accomodate any hardware or simulated platform.
+ The sample implementation returns millisecs by default,
+ and the resolution is controlled by <TIMER_RES_DIVIDER>
+*/
+CORE_TICKS get_time(void) {
+ CORE_TICKS elapsed=(CORE_TICKS)(MYTIMEDIFF(stop_time_val, start_time_val));
+ return elapsed;
+}
+/* Function: time_in_secs
+ Convert the value returned by get_time to seconds.
+
+ The <secs_ret> type is used to accomodate systems with no support for floating point.
+ Default implementation implemented by the EE_TICKS_PER_SEC macro above.
+*/
+secs_ret time_in_secs(CORE_TICKS ticks) {
+ secs_ret retval=((secs_ret)ticks) / (secs_ret)EE_TICKS_PER_SEC;
+ return retval;
+}
+#else
+#error "Please implement timing functionality in core_portme.c"
+#endif /* SAMPLE_TIME_IMPLEMENTATION */
+
+ee_u32 default_num_contexts=MULTITHREAD;
+
+/* Function: portable_init
+ Target specific initialization code
+ Test for some common mistakes.
+*/
+void portable_init(core_portable *p, int *argc, char *argv[])
+{
+#if PRINT_ARGS
+ int i;
+ for (i=0; i<*argc; i++) {
+ ee_printf("Arg[%d]=%s\n",i,argv[i]);
+ }
+#endif
+ if (sizeof(ee_ptr_int) != sizeof(ee_u8 *)) {
+ ee_printf("ERROR! Please define ee_ptr_int to a type that holds a pointer!\n");
+ }
+ if (sizeof(ee_u32) != 4) {
+ ee_printf("ERROR! Please define ee_u32 to a 32b unsigned type!\n");
+ }
+#if (MAIN_HAS_NOARGC && (SEED_METHOD==SEED_ARG))
+ ee_printf("ERROR! Main has no argc, but SEED_METHOD defined to SEED_ARG!\n");
+#endif
+
+#if (MULTITHREAD>1) && (SEED_METHOD==SEED_ARG)
+ {
+ int nargs=*argc,i;
+ if ((nargs>1) && (*argv[1]=='M')) {
+ default_num_contexts=parseval(argv[1]+1);
+ if (default_num_contexts>MULTITHREAD)
+ default_num_contexts=MULTITHREAD;
+ /* Shift args since first arg is directed to the portable part and not to coremark main */
+ --nargs;
+ for (i=1; i<nargs; i++)
+ argv[i]=argv[i+1];
+ *argc=nargs;
+ }
+ }
+#endif /* sample of potential platform specific init via command line, reset the number of contexts being used if first argument is M<n>*/
+ p->portable_id=1;
+}
+/* Function: portable_fini
+ Target specific final code
+*/
+void portable_fini(core_portable *p)
+{
+ p->portable_id=0;
+}
+
+#if (MULTITHREAD>1)
+
+/* Function: core_start_parallel
+ Start benchmarking in a parallel context.
+
+ Three implementations are provided, one using pthreads, one using fork and shared mem, and one using fork and sockets.
+ Other implementations using MCAPI or other standards can easily be devised.
+*/
+/* Function: core_stop_parallel
+ Stop a parallel context execution of coremark, and gather the results.
+
+ Three implementations are provided, one using pthreads, one using fork and shared mem, and one using fork and sockets.
+ Other implementations using MCAPI or other standards can easily be devised.
+*/
+#if USE_PTHREAD
+ee_u8 core_start_parallel(core_results *res) {
+ return (ee_u8)pthread_create(&(res->port.thread),NULL,iterate,(void *)res);
+}
+ee_u8 core_stop_parallel(core_results *res) {
+ void *retval;
+ return (ee_u8)pthread_join(res->port.thread,&retval);
+}
+#elif USE_FORK
+static int key_id=0;
+ee_u8 core_start_parallel(core_results *res) {
+ key_t key=4321+key_id;
+ key_id++;
+ res->port.pid=fork();
+ res->port.shmid=shmget(key, 8, IPC_CREAT | 0666);
+ if (res->port.shmid<0) {
+ ee_printf("ERROR in shmget!\n");
+ }
+ if (res->port.pid==0) {
+ iterate(res);
+ res->port.shm=shmat(res->port.shmid, NULL, 0);
+ /* copy the validation values to the shared memory area and quit*/
+ if (res->port.shm == (char *) -1) {
+ ee_printf("ERROR in child shmat!\n");
+ } else {
+ memcpy(res->port.shm,&(res->crc),8);
+ shmdt(res->port.shm);
+ }
+ exit(0);
+ }
+ return 1;
+}
+ee_u8 core_stop_parallel(core_results *res) {
+ int status;
+ pid_t wpid = waitpid(res->port.pid,&status,WUNTRACED);
+ if (wpid != res->port.pid) {
+ ee_printf("ERROR waiting for child.\n");
+ if (errno == ECHILD) ee_printf("errno=No such child %d\n",res->port.pid);
+ if (errno == EINTR) ee_printf("errno=Interrupted\n");
+ return 0;
+ }
+ /* after process is done, get the values from the shared memory area */
+ res->port.shm=shmat(res->port.shmid, NULL, 0);
+ if (res->port.shm == (char *) -1) {
+ ee_printf("ERROR in parent shmat!\n");
+ return 0;
+ }
+ memcpy(&(res->crc),res->port.shm,8);
+ shmdt(res->port.shm);
+ return 1;
+}
+#elif USE_SOCKET
+static int key_id=0;
+ee_u8 core_start_parallel(core_results *res) {
+ int bound, buffer_length=8;
+ res->port.sa.sin_family = AF_INET;
+ res->port.sa.sin_addr.s_addr = htonl(0x7F000001);
+ res->port.sa.sin_port = htons(7654+key_id);
+ key_id++;
+ res->port.pid=fork();
+ if (res->port.pid==0) { /* benchmark child */
+ iterate(res);
+ res->port.sock = socket(PF_INET, SOCK_DGRAM, IPPROTO_UDP);
+ if (-1 == res->port.sock) /* if socket failed to initialize, exit */ {
+ ee_printf("Error Creating Socket");
+ } else {
+ int bytes_sent = sendto(res->port.sock, &(res->crc), buffer_length, 0,(struct sockaddr*)&(res->port.sa), sizeof (struct sockaddr_in));
+ if (bytes_sent < 0)
+ ee_printf("Error sending packet: %s\n", strerror(errno));
+ close(res->port.sock); /* close the socket */
+ }
+ exit(0);
+ }
+ /* parent process, open the socket */
+ res->port.sock = socket(PF_INET, SOCK_DGRAM, IPPROTO_UDP);
+ bound = bind(res->port.sock,(struct sockaddr*)&(res->port.sa), sizeof(struct sockaddr));
+ if (bound < 0)
+ ee_printf("bind(): %s\n",strerror(errno));
+ return 1;
+}
+ee_u8 core_stop_parallel(core_results *res) {
+ int status;
+ int fromlen=sizeof(struct sockaddr);
+ int recsize = recvfrom(res->port.sock, &(res->crc), 8, 0, (struct sockaddr*)&(res->port.sa), &fromlen);
+ if (recsize < 0) {
+ ee_printf("Error in receive: %s\n", strerror(errno));
+ return 0;
+ }
+ pid_t wpid = waitpid(res->port.pid,&status,WUNTRACED);
+ if (wpid != res->port.pid) {
+ ee_printf("ERROR waiting for child.\n");
+ if (errno == ECHILD) ee_printf("errno=No such child %d\n",res->port.pid);
+ if (errno == EINTR) ee_printf("errno=Interrupted\n");
+ return 0;
+ }
+ return 1;
+}
+#else /* no standard multicore implementation */
+#error "Please implement multicore functionality in core_portme.c to use multiple contexts."
+#endif /* multithread implementations */
+#endif
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/linux/core_portme.h b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/linux/core_portme.h
new file mode 100755
index 0000000..2cf4659
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/linux/core_portme.h
@@ -0,0 +1,290 @@
+/*
+Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Original Author: Shay Gal-on
+*/
+
+#ifndef CORE_PORTME_H
+#define CORE_PORTME_H
+/************************/
+/* Data types and settings */
+/************************/
+/* Configuration: HAS_FLOAT
+ Define to 1 if the platform supports floating point.
+*/
+#ifndef HAS_FLOAT
+#define HAS_FLOAT 1
+#endif
+/* Configuration: HAS_TIME_H
+ Define to 1 if platform has the time.h header file,
+ and implementation of functions thereof.
+*/
+#ifndef HAS_TIME_H
+#define HAS_TIME_H 1
+#endif
+/* Configuration: USE_CLOCK
+ Define to 1 if platform has the time.h header file,
+ and implementation of functions thereof.
+*/
+#ifndef USE_CLOCK
+#define USE_CLOCK 0
+#endif
+/* Configuration: HAS_STDIO
+ Define to 1 if the platform has stdio.h.
+*/
+#ifndef HAS_STDIO
+#define HAS_STDIO 1
+#endif
+/* Configuration: HAS_PRINTF
+ Define to 1 if the platform has stdio.h and implements the printf function.
+*/
+#ifndef HAS_PRINTF
+#define HAS_PRINTF 1
+#endif
+
+/* Configuration: CORE_TICKS
+ Define type of return from the timing functions.
+ */
+#if defined(_MSC_VER)
+#include <windows.h>
+typedef size_t CORE_TICKS;
+#elif HAS_TIME_H
+#include <time.h>
+typedef clock_t CORE_TICKS;
+#else
+#error "Please define type of CORE_TICKS and implement start_time, end_time get_time and time_in_secs functions!"
+#endif
+
+/* Definitions: COMPILER_VERSION, COMPILER_FLAGS, MEM_LOCATION
+ Initialize these strings per platform
+*/
+#ifndef COMPILER_VERSION
+ #ifdef __GNUC__
+ #define COMPILER_VERSION "GCC"__VERSION__
+ #else
+ #define COMPILER_VERSION "Please put compiler version here (e.g. gcc 4.1)"
+ #endif
+#endif
+#ifndef COMPILER_FLAGS
+ #define COMPILER_FLAGS FLAGS_STR /* "Please put compiler flags here (e.g. -o3)" */
+#endif
+#ifndef MEM_LOCATION
+ #define MEM_LOCATION "Please put data memory location here\n\t\t\t(e.g. code in flash, data on heap etc)"
+ #define MEM_LOCATION_UNSPEC 1
+#endif
+
+/* Data Types:
+ To avoid compiler issues, define the data types that need ot be used for 8b, 16b and 32b in <core_portme.h>.
+
+ *Imprtant*:
+ ee_ptr_int needs to be the data type used to hold pointers, otherwise coremark may fail!!!
+*/
+typedef signed short ee_s16;
+typedef unsigned short ee_u16;
+typedef signed int ee_s32;
+typedef double ee_f32;
+typedef unsigned char ee_u8;
+typedef unsigned int ee_u32;
+typedef ee_u32 ee_ptr_int;
+typedef size_t ee_size_t;
+/* align_mem:
+ This macro is used to align an offset to point to a 32b value. It is used in the Matrix algorithm to initialize the input memory blocks.
+*/
+#define align_mem(x) (void *)(4 + (((ee_ptr_int)(x) - 1) & ~3))
+
+/* Configuration: SEED_METHOD
+ Defines method to get seed values that cannot be computed at compile time.
+
+ Valid values:
+ SEED_ARG - from command line.
+ SEED_FUNC - from a system function.
+ SEED_VOLATILE - from volatile variables.
+*/
+#ifndef SEED_METHOD
+#define SEED_METHOD SEED_ARG
+#endif
+
+/* Configuration: MEM_METHOD
+ Defines method to get a block of memry.
+
+ Valid values:
+ MEM_MALLOC - for platforms that implement malloc and have malloc.h.
+ MEM_STATIC - to use a static memory array.
+ MEM_STACK - to allocate the data block on the stack (NYI).
+*/
+#ifndef MEM_METHOD
+#define MEM_METHOD MEM_MALLOC
+#endif
+
+/* Configuration: MULTITHREAD
+ Define for parallel execution
+
+ Valid values:
+ 1 - only one context (default).
+ N>1 - will execute N copies in parallel.
+
+ Note:
+ If this flag is defined to more then 1, an implementation for launching parallel contexts must be defined.
+
+ Two sample implementations are provided. Use <USE_PTHREAD> or <USE_FORK> to enable them.
+
+ It is valid to have a different implementation of <core_start_parallel> and <core_end_parallel> in <core_portme.c>,
+ to fit a particular architecture.
+*/
+#ifndef MULTITHREAD
+#define MULTITHREAD 1
+#endif
+
+/* Configuration: USE_PTHREAD
+ Sample implementation for launching parallel contexts
+ This implementation uses pthread_thread_create and pthread_join.
+
+ Valid values:
+ 0 - Do not use pthreads API.
+ 1 - Use pthreads API
+
+ Note:
+ This flag only matters if MULTITHREAD has been defined to a value greater then 1.
+*/
+#ifndef USE_PTHREAD
+#define USE_PTHREAD 0
+#endif
+
+/* Configuration: USE_FORK
+ Sample implementation for launching parallel contexts
+ This implementation uses fork, waitpid, shmget,shmat and shmdt.
+
+ Valid values:
+ 0 - Do not use fork API.
+ 1 - Use fork API
+
+ Note:
+ This flag only matters if MULTITHREAD has been defined to a value greater then 1.
+*/
+#ifndef USE_FORK
+#define USE_FORK 0
+#endif
+
+/* Configuration: USE_SOCKET
+ Sample implementation for launching parallel contexts
+ This implementation uses fork, socket, sendto and recvfrom
+
+ Valid values:
+ 0 - Do not use fork and sockets API.
+ 1 - Use fork and sockets API
+
+ Note:
+ This flag only matters if MULTITHREAD has been defined to a value greater then 1.
+*/
+#ifndef USE_SOCKET
+#define USE_SOCKET 0
+#endif
+
+/* Configuration: MAIN_HAS_NOARGC
+ Needed if platform does not support getting arguments to main.
+
+ Valid values:
+ 0 - argc/argv to main is supported
+ 1 - argc/argv to main is not supported
+*/
+#ifndef MAIN_HAS_NOARGC
+#define MAIN_HAS_NOARGC 0
+#endif
+
+/* Configuration: MAIN_HAS_NORETURN
+ Needed if platform does not support returning a value from main.
+
+ Valid values:
+ 0 - main returns an int, and return value will be 0.
+ 1 - platform does not support returning a value from main
+*/
+#ifndef MAIN_HAS_NORETURN
+#define MAIN_HAS_NORETURN 0
+#endif
+
+/* Variable: default_num_contexts
+ Number of contexts to spawn in multicore context.
+ Override this global value to change number of contexts used.
+
+ Note:
+ This value may not be set higher then the <MULTITHREAD> define.
+
+ To experiment, you can set the <MULTITHREAD> define to the highest value expected, and use argc/argv in the <portable_init> to set this value from the command line.
+*/
+extern ee_u32 default_num_contexts;
+
+#if (MULTITHREAD>1)
+#if USE_PTHREAD
+ #include <pthread.h>
+ #define PARALLEL_METHOD "PThreads"
+#elif USE_FORK
+ #include <unistd.h>
+ #include <errno.h>
+ #include <sys/wait.h>
+ #include <sys/shm.h>
+ #include <string.h> /* for memcpy */
+ #define PARALLEL_METHOD "Fork"
+#elif USE_SOCKET
+ #include <sys/types.h>
+ #include <sys/socket.h>
+ #include <netinet/in.h>
+ #include <arpa/inet.h>
+ #include <sys/wait.h>
+ #include <stdio.h>
+ #include <stdlib.h>
+ #include <string.h>
+ #include <unistd.h>
+ #include <errno.h>
+ #define PARALLEL_METHOD "Sockets"
+#else
+ #define PARALLEL_METHOD "Proprietary"
+ #error "Please implement multicore functionality in core_portme.c to use multiple contexts."
+#endif /* Method for multithreading */
+#endif /* MULTITHREAD > 1 */
+
+typedef struct CORE_PORTABLE_S {
+#if (MULTITHREAD>1)
+ #if USE_PTHREAD
+ pthread_t thread;
+ #elif USE_FORK
+ pid_t pid;
+ int shmid;
+ void *shm;
+ #elif USE_SOCKET
+ pid_t pid;
+ int sock;
+ struct sockaddr_in sa;
+ #endif /* Method for multithreading */
+#endif /* MULTITHREAD>1 */
+ ee_u8 portable_id;
+} core_portable;
+
+/* target specific init/fini */
+void portable_init(core_portable *p, int *argc, char *argv[]);
+void portable_fini(core_portable *p);
+
+#if (SEED_METHOD==SEED_VOLATILE)
+ #if (VALIDATION_RUN || PERFORMANCE_RUN || PROFILE_RUN)
+ #define RUN_TYPE_FLAG 1
+ #else
+ #if (TOTAL_DATA_SIZE==1200)
+ #define PROFILE_RUN 1
+ #else
+ #define PERFORMANCE_RUN 1
+ #endif
+ #endif
+#endif /* SEED_METHOD==SEED_VOLATILE */
+
+#endif /* CORE_PORTME_H */
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/linux/core_portme.mak b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/linux/core_portme.mak
new file mode 100755
index 0000000..5cfabee
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/linux/core_portme.mak
@@ -0,0 +1,140 @@
+# Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# Original Author: Shay Gal-on
+
+#File: core_portme.mak
+
+# Flag: OUTFLAG
+# Use this flag to define how to to get an executable (e.g -o)
+OUTFLAG= -o
+# Flag: CC
+# Use this flag to define compiler to use
+CC = gcc
+# Flag: CFLAGS
+# Use this flag to define compiler options. Note, you can add compiler options from the command line using XCFLAGS="other flags"
+PORT_CFLAGS = -O2
+FLAGS_STR = "$(PORT_CFLAGS) $(XCFLAGS) $(XLFLAGS) $(LFLAGS_END)"
+CFLAGS = $(PORT_CFLAGS) -I$(PORT_DIR) -I. -DFLAGS_STR=\"$(FLAGS_STR)\"
+#Flag: LFLAGS_END
+# Define any libraries needed for linking or other flags that should come at the end of the link line (e.g. linker scripts).
+# Note: On certain platforms, the default clock_gettime implementation is supported but requires linking of librt.
+LFLAGS_END += -lrt
+# Flag: PORT_SRCS
+# Port specific source files can be added here
+PORT_SRCS = $(PORT_DIR)/core_portme.c
+# Flag: LOAD
+# Define this flag if you need to load to a target, as in a cross compile environment.
+
+# Flag: RUN
+# Define this flag if running does not consist of simple invocation of the binary.
+# In a cross compile environment, you need to define this.
+
+#For flashing and using a tera term macro, you could use
+#LOAD = flash ADDR
+#RUN = ttpmacro coremark.ttl
+
+#For copying to target and executing via SSH connection, you could use
+#LOAD = scp $(OUTFILE) user@target:~
+#RUN = ssh user@target -c
+
+#For native compilation and execution
+LOAD = echo Loading done
+RUN =
+
+OEXT = .o
+EXE = .exe
+
+# Flag: SEPARATE_COMPILE
+# Define if you need to separate compilation from link stage.
+# In this case, you also need to define below how to create an object file, and how to link.
+ifdef SEPARATE_COMPILE
+
+LD = gcc
+OBJOUT = -o
+LFLAGS =
+OFLAG = -o
+COUT = -c
+# Flag: PORT_OBJS
+# Port specific object files can be added here
+PORT_OBJS = $(PORT_DIR)/core_portme$(OEXT)
+PORT_CLEAN = *$(OEXT)
+
+$(OPATH)%$(OEXT) : %.c
+ $(CC) $(CFLAGS) $(XCFLAGS) $(COUT) $< $(OBJOUT) $@
+
+endif
+
+# Target: port_prebuild
+# Generate any files that are needed before actual build starts.
+# E.g. generate profile guidance files. Sample PGO generation for gcc enabled with PGO=1
+# - First, check if PGO was defined on the command line, if so, need to add -fprofile-use to compile line.
+# - Second, if PGO reference has not yet been generated, add a step to the prebuild that will build a profile-generate version and run it.
+# Note - Using REBUILD=1
+#
+# Use make PGO=1 to invoke this sample processing.
+
+ifdef PGO
+ ifeq (,$(findstring $(PGO),gen))
+ PGO_STAGE=build_pgo_gcc
+ CFLAGS+=-fprofile-use
+ endif
+ PORT_CLEAN+=*.gcda *.gcno gmon.out
+endif
+
+.PHONY: port_prebuild
+port_prebuild: $(PGO_STAGE)
+
+.PHONY: build_pgo_gcc
+build_pgo_gcc:
+ $(MAKE) PGO=gen XCFLAGS="$(XCFLAGS) -fprofile-generate -DTOTAL_DATA_SIZE=1200" ITERATIONS=10 gen_pgo_data REBUILD=1
+
+# Target: port_postbuild
+# Generate any files that are needed after actual build end.
+# E.g. change format to srec, bin, zip in order to be able to load into flash
+.PHONY: port_postbuild
+port_postbuild:
+
+# Target: port_postrun
+# Do platform specific after run stuff.
+# E.g. reset the board, backup the logfiles etc.
+.PHONY: port_postrun
+port_postrun:
+
+# Target: port_prerun
+# Do platform specific after run stuff.
+# E.g. reset the board, backup the logfiles etc.
+.PHONY: port_prerun
+port_prerun:
+
+# Target: port_postload
+# Do platform specific after load stuff.
+# E.g. reset the reset power to the flash eraser
+.PHONY: port_postload
+port_postload:
+
+# Target: port_preload
+# Do platform specific before load stuff.
+# E.g. reset the reset power to the flash eraser
+.PHONY: port_preload
+port_preload:
+
+# FLAG: OPATH
+# Path to the output folder. Default - current folder.
+OPATH = ./
+MKDIR = mkdir -p
+
+# FLAG: PERL
+# Define perl executable to calculate the geomean if running separate.
+PERL=/usr/bin/perl
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/linux64/core_portme.c b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/linux64/core_portme.c
new file mode 100755
index 0000000..fe8d299
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/linux64/core_portme.c
@@ -0,0 +1,336 @@
+/*
+Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Original Author: Shay Gal-on
+*/
+
+#include <stdio.h>
+#include <stdlib.h>
+#include "coremark.h"
+#if CALLGRIND_RUN
+#include <valgrind/callgrind.h>
+#endif
+
+#if (MEM_METHOD==MEM_MALLOC)
+#include <malloc.h>
+/* Function: portable_malloc
+ Provide malloc() functionality in a platform specific way.
+*/
+void *portable_malloc(size_t size) {
+ return malloc(size);
+}
+/* Function: portable_free
+ Provide free() functionality in a platform specific way.
+*/
+void portable_free(void *p) {
+ free(p);
+}
+#else
+void *portable_malloc(size_t size) {
+ return NULL;
+}
+void portable_free(void *p) {
+ p=NULL;
+}
+#endif
+
+#if (SEED_METHOD==SEED_VOLATILE)
+#if VALIDATION_RUN
+ volatile ee_s32 seed1_volatile=0x3415;
+ volatile ee_s32 seed2_volatile=0x3415;
+ volatile ee_s32 seed3_volatile=0x66;
+#endif
+#if PERFORMANCE_RUN
+ volatile ee_s32 seed1_volatile=0x0;
+ volatile ee_s32 seed2_volatile=0x0;
+ volatile ee_s32 seed3_volatile=0x66;
+#endif
+#if PROFILE_RUN
+ volatile ee_s32 seed1_volatile=0x8;
+ volatile ee_s32 seed2_volatile=0x8;
+ volatile ee_s32 seed3_volatile=0x8;
+#endif
+ volatile ee_s32 seed4_volatile=ITERATIONS;
+ volatile ee_s32 seed5_volatile=0;
+#endif
+/* Porting: Timing functions
+ How to capture time and convert to seconds must be ported to whatever is supported by the platform.
+ e.g. Read value from on board RTC, read value from cpu clock cycles performance counter etc.
+ Sample implementation for standard time.h and windows.h definitions included.
+*/
+/* Define: TIMER_RES_DIVIDER
+ Divider to trade off timer resolution and total time that can be measured.
+
+ Use lower values to increase resolution, but make sure that overflow does not occur.
+ If there are issues with the return value overflowing, increase this value.
+ */
+#if USE_CLOCK
+ #define NSECS_PER_SEC CLOCKS_PER_SEC
+ #define EE_TIMER_TICKER_RATE 1000
+ #define CORETIMETYPE clock_t
+ #define GETMYTIME(_t) (*_t=clock())
+ #define MYTIMEDIFF(fin,ini) ((fin)-(ini))
+ #define TIMER_RES_DIVIDER 1
+ #define SAMPLE_TIME_IMPLEMENTATION 1
+#elif defined(_MSC_VER)
+ #define NSECS_PER_SEC 10000000
+ #define EE_TIMER_TICKER_RATE 1000
+ #define CORETIMETYPE FILETIME
+ #define GETMYTIME(_t) GetSystemTimeAsFileTime(_t)
+ #define MYTIMEDIFF(fin,ini) (((*(__int64*)&fin)-(*(__int64*)&ini))/TIMER_RES_DIVIDER)
+ /* setting to millisces resolution by default with MSDEV */
+ #ifndef TIMER_RES_DIVIDER
+ #define TIMER_RES_DIVIDER 1000
+ #endif
+ #define SAMPLE_TIME_IMPLEMENTATION 1
+#elif HAS_TIME_H
+ #define NSECS_PER_SEC 1000000000
+ #define EE_TIMER_TICKER_RATE 1000
+ #define CORETIMETYPE struct timespec
+ #define GETMYTIME(_t) clock_gettime(CLOCK_REALTIME,_t)
+ #define MYTIMEDIFF(fin,ini) ((fin.tv_sec-ini.tv_sec)*(NSECS_PER_SEC/TIMER_RES_DIVIDER)+(fin.tv_nsec-ini.tv_nsec)/TIMER_RES_DIVIDER)
+ /* setting to 1/1000 of a second resolution by default with linux */
+ #ifndef TIMER_RES_DIVIDER
+ #define TIMER_RES_DIVIDER 1000000
+ #endif
+ #define SAMPLE_TIME_IMPLEMENTATION 1
+#else
+ #define SAMPLE_TIME_IMPLEMENTATION 0
+#endif
+#define EE_TICKS_PER_SEC (NSECS_PER_SEC / TIMER_RES_DIVIDER)
+
+#if SAMPLE_TIME_IMPLEMENTATION
+/** Define Host specific (POSIX), or target specific global time variables. */
+static CORETIMETYPE start_time_val, stop_time_val;
+
+/* Function: start_time
+ This function will be called right before starting the timed portion of the benchmark.
+
+ Implementation may be capturing a system timer (as implemented in the example code)
+ or zeroing some system parameters - e.g. setting the cpu clocks cycles to 0.
+*/
+void start_time(void) {
+ GETMYTIME(&start_time_val );
+#if CALLGRIND_RUN
+ CALLGRIND_START_INSTRUMENTATION
+#endif
+#if MICA
+ asm volatile("int3");/*1 */
+#endif
+}
+/* Function: stop_time
+ This function will be called right after ending the timed portion of the benchmark.
+
+ Implementation may be capturing a system timer (as implemented in the example code)
+ or other system parameters - e.g. reading the current value of cpu cycles counter.
+*/
+void stop_time(void) {
+#if CALLGRIND_RUN
+ CALLGRIND_STOP_INSTRUMENTATION
+#endif
+#if MICA
+ asm volatile("int3");/*1 */
+#endif
+ GETMYTIME(&stop_time_val );
+}
+/* Function: get_time
+ Return an abstract "ticks" number that signifies time on the system.
+
+ Actual value returned may be cpu cycles, milliseconds or any other value,
+ as long as it can be converted to seconds by <time_in_secs>.
+ This methodology is taken to accomodate any hardware or simulated platform.
+ The sample implementation returns millisecs by default,
+ and the resolution is controlled by <TIMER_RES_DIVIDER>
+*/
+CORE_TICKS get_time(void) {
+ CORE_TICKS elapsed=(CORE_TICKS)(MYTIMEDIFF(stop_time_val, start_time_val));
+ return elapsed;
+}
+/* Function: time_in_secs
+ Convert the value returned by get_time to seconds.
+
+ The <secs_ret> type is used to accomodate systems with no support for floating point.
+ Default implementation implemented by the EE_TICKS_PER_SEC macro above.
+*/
+secs_ret time_in_secs(CORE_TICKS ticks) {
+ secs_ret retval=((secs_ret)ticks) / (secs_ret)EE_TICKS_PER_SEC;
+ return retval;
+}
+#else
+#error "Please implement timing functionality in core_portme.c"
+#endif /* SAMPLE_TIME_IMPLEMENTATION */
+
+ee_u32 default_num_contexts=MULTITHREAD;
+
+/* Function: portable_init
+ Target specific initialization code
+ Test for some common mistakes.
+*/
+void portable_init(core_portable *p, int *argc, char *argv[])
+{
+#if PRINT_ARGS
+ int i;
+ for (i=0; i<*argc; i++) {
+ ee_printf("Arg[%d]=%s\n",i,argv[i]);
+ }
+#endif
+ if (sizeof(ee_ptr_int) != sizeof(ee_u8 *)) {
+ ee_printf("ERROR! Please define ee_ptr_int to a type that holds a pointer!\n");
+ }
+ if (sizeof(ee_u32) != 4) {
+ ee_printf("ERROR! Please define ee_u32 to a 32b unsigned type!\n");
+ }
+#if (MAIN_HAS_NOARGC && (SEED_METHOD==SEED_ARG))
+ ee_printf("ERROR! Main has no argc, but SEED_METHOD defined to SEED_ARG!\n");
+#endif
+
+#if (MULTITHREAD>1) && (SEED_METHOD==SEED_ARG)
+ int nargs=*argc,i;
+ if ((nargs>1) && (*argv[1]=='M')) {
+ default_num_contexts=parseval(argv[1]+1);
+ if (default_num_contexts>MULTITHREAD)
+ default_num_contexts=MULTITHREAD;
+ /* Shift args since first arg is directed to the portable part and not to coremark main */
+ --nargs;
+ for (i=1; i<nargs; i++)
+ argv[i]=argv[i+1];
+ *argc=nargs;
+ }
+#endif /* sample of potential platform specific init via command line, reset the number of contexts being used if first argument is M<n>*/
+ p->portable_id=1;
+}
+/* Function: portable_fini
+ Target specific final code
+*/
+void portable_fini(core_portable *p)
+{
+ p->portable_id=0;
+}
+
+#if (MULTITHREAD>1)
+
+/* Function: core_start_parallel
+ Start benchmarking in a parallel context.
+
+ Three implementations are provided, one using pthreads, one using fork and shared mem, and one using fork and sockets.
+ Other implementations using MCAPI or other standards can easily be devised.
+*/
+/* Function: core_stop_parallel
+ Stop a parallel context execution of coremark, and gather the results.
+
+ Three implementations are provided, one using pthreads, one using fork and shared mem, and one using fork and sockets.
+ Other implementations using MCAPI or other standards can easily be devised.
+*/
+#if USE_PTHREAD
+ee_u8 core_start_parallel(core_results *res) {
+ return (ee_u8)pthread_create(&(res->port.thread),NULL,iterate,(void *)res);
+}
+ee_u8 core_stop_parallel(core_results *res) {
+ void *retval;
+ return (ee_u8)pthread_join(res->port.thread,&retval);
+}
+#elif USE_FORK
+static int key_id=0;
+ee_u8 core_start_parallel(core_results *res) {
+ key_t key=4321+key_id;
+ key_id++;
+ res->port.pid=fork();
+ res->port.shmid=shmget(key, 8, IPC_CREAT | 0666);
+ if (res->port.shmid<0) {
+ ee_printf("ERROR in shmget!\n");
+ }
+ if (res->port.pid==0) {
+ iterate(res);
+ res->port.shm=shmat(res->port.shmid, NULL, 0);
+ /* copy the validation values to the shared memory area and quit*/
+ if (res->port.shm == (char *) -1) {
+ ee_printf("ERROR in child shmat!\n");
+ } else {
+ memcpy(res->port.shm,&(res->crc),8);
+ shmdt(res->port.shm);
+ }
+ exit(0);
+ }
+ return 1;
+}
+ee_u8 core_stop_parallel(core_results *res) {
+ int status;
+ pid_t wpid = waitpid(res->port.pid,&status,WUNTRACED);
+ if (wpid != res->port.pid) {
+ ee_printf("ERROR waiting for child.\n");
+ if (errno == ECHILD) ee_printf("errno=No such child %d\n",res->port.pid);
+ if (errno == EINTR) ee_printf("errno=Interrupted\n");
+ return 0;
+ }
+ /* after process is done, get the values from the shared memory area */
+ res->port.shm=shmat(res->port.shmid, NULL, 0);
+ if (res->port.shm == (char *) -1) {
+ ee_printf("ERROR in parent shmat!\n");
+ return 0;
+ }
+ memcpy(&(res->crc),res->port.shm,8);
+ shmdt(res->port.shm);
+ return 1;
+}
+#elif USE_SOCKET
+static int key_id=0;
+ee_u8 core_start_parallel(core_results *res) {
+ int bound, buffer_length=8;
+ res->port.sa.sin_family = AF_INET;
+ res->port.sa.sin_addr.s_addr = htonl(0x7F000001);
+ res->port.sa.sin_port = htons(7654+key_id);
+ key_id++;
+ res->port.pid=fork();
+ if (res->port.pid==0) { /* benchmark child */
+ iterate(res);
+ res->port.sock = socket(PF_INET, SOCK_DGRAM, IPPROTO_UDP);
+ if (-1 == res->port.sock) /* if socket failed to initialize, exit */ {
+ ee_printf("Error Creating Socket");
+ } else {
+ int bytes_sent = sendto(res->port.sock, &(res->crc), buffer_length, 0,(struct sockaddr*)&(res->port.sa), sizeof (struct sockaddr_in));
+ if (bytes_sent < 0)
+ ee_printf("Error sending packet: %s\n", strerror(errno));
+ close(res->port.sock); /* close the socket */
+ }
+ exit(0);
+ }
+ /* parent process, open the socket */
+ res->port.sock = socket(PF_INET, SOCK_DGRAM, IPPROTO_UDP);
+ bound = bind(res->port.sock,(struct sockaddr*)&(res->port.sa), sizeof(struct sockaddr));
+ if (bound < 0)
+ ee_printf("bind(): %s\n",strerror(errno));
+ return 1;
+}
+ee_u8 core_stop_parallel(core_results *res) {
+ int status;
+ int fromlen=sizeof(struct sockaddr);
+ int recsize = recvfrom(res->port.sock, &(res->crc), 8, 0, (struct sockaddr*)&(res->port.sa), &fromlen);
+ if (recsize < 0) {
+ ee_printf("Error in receive: %s\n", strerror(errno));
+ return 0;
+ }
+ pid_t wpid = waitpid(res->port.pid,&status,WUNTRACED);
+ if (wpid != res->port.pid) {
+ ee_printf("ERROR waiting for child.\n");
+ if (errno == ECHILD) ee_printf("errno=No such child %d\n",res->port.pid);
+ if (errno == EINTR) ee_printf("errno=Interrupted\n");
+ return 0;
+ }
+ return 1;
+}
+#else /* no standard multicore implementation */
+#error "Please implement multicore functionality in core_portme.c to use multiple contexts."
+#endif /* multithread implementations */
+#endif
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/linux64/core_portme.h b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/linux64/core_portme.h
new file mode 100755
index 0000000..1228a67
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/linux64/core_portme.h
@@ -0,0 +1,291 @@
+/*
+Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Original Author: Shay Gal-on
+*/
+
+/* Topic: Description
+ This file contains configuration constants required to execute on different platforms
+*/
+#ifndef CORE_PORTME_H
+#define CORE_PORTME_H
+/************************/
+/* Data types and settings */
+/************************/
+/* Configuration: HAS_FLOAT
+ Define to 1 if the platform supports floating point.
+*/
+#ifndef HAS_FLOAT
+#define HAS_FLOAT 1
+#endif
+/* Configuration: HAS_TIME_H
+ Define to 1 if platform has the time.h header file,
+ and implementation of functions thereof.
+*/
+#ifndef HAS_TIME_H
+#define HAS_TIME_H 1
+#endif
+/* Configuration: USE_CLOCK
+ Define to 1 if platform has the time.h header file,
+ and implementation of functions thereof.
+*/
+#ifndef USE_CLOCK
+#define USE_CLOCK 0
+#endif
+/* Configuration: HAS_STDIO
+ Define to 1 if the platform has stdio.h.
+*/
+#ifndef HAS_STDIO
+#define HAS_STDIO 1
+#endif
+/* Configuration: HAS_PRINTF
+ Define to 1 if the platform has stdio.h and implements the printf function.
+*/
+#ifndef HAS_PRINTF
+#define HAS_PRINTF 1
+#endif
+
+/* Configuration: CORE_TICKS
+ Define type of return from the timing functions.
+ */
+#if defined(_MSC_VER)
+#include <windows.h>
+typedef size_t CORE_TICKS;
+#elif HAS_TIME_H
+#include <time.h>
+typedef clock_t CORE_TICKS;
+#else
+#error "Please define type of CORE_TICKS and implement start_time, end_time get_time and time_in_secs functions!"
+#endif
+
+/* Definitions: COMPILER_VERSION, COMPILER_FLAGS, MEM_LOCATION
+ Initialize these strings per platform
+*/
+#ifndef COMPILER_VERSION
+ #ifdef __GNUC__
+ #define COMPILER_VERSION "GCC"__VERSION__
+ #else
+ #define COMPILER_VERSION "Please put compiler version here (e.g. gcc 4.1)"
+ #endif
+#endif
+#ifndef COMPILER_FLAGS
+ #define COMPILER_FLAGS FLAGS_STR /* "Please put compiler flags here (e.g. -o3)" */
+#endif
+#ifndef MEM_LOCATION
+ #define MEM_LOCATION "Please put data memory location here\n\t\t\t(e.g. code in flash, data on heap etc)"
+ #define MEM_LOCATION_UNSPEC 1
+#endif
+
+/* Data Types:
+ To avoid compiler issues, define the data types that need ot be used for 8b, 16b and 32b in <core_portme.h>.
+
+ *Imprtant*:
+ ee_ptr_int needs to be the data type used to hold pointers, otherwise coremark may fail!!!
+*/
+typedef signed short ee_s16;
+typedef unsigned short ee_u16;
+typedef signed int ee_s32;
+typedef double ee_f32;
+typedef unsigned char ee_u8;
+typedef unsigned int ee_u32;
+typedef unsigned long long ee_ptr_int;
+typedef size_t ee_size_t;
+/* align an offset to point to a 32b value */
+#define align_mem(x) (void *)(4 + (((ee_ptr_int)(x) - 1) & ~3))
+
+/* Configuration: SEED_METHOD
+ Defines method to get seed values that cannot be computed at compile time.
+
+ Valid values:
+ SEED_ARG - from command line.
+ SEED_FUNC - from a system function.
+ SEED_VOLATILE - from volatile variables.
+*/
+#ifndef SEED_METHOD
+#define SEED_METHOD SEED_ARG
+#endif
+
+/* Configuration: MEM_METHOD
+ Defines method to get a block of memry.
+
+ Valid values:
+ MEM_MALLOC - for platforms that implement malloc and have malloc.h.
+ MEM_STATIC - to use a static memory array.
+ MEM_STACK - to allocate the data block on the stack (NYI).
+*/
+#ifndef MEM_METHOD
+#define MEM_METHOD MEM_MALLOC
+#endif
+
+/* Configuration: MULTITHREAD
+ Define for parallel execution
+
+ Valid values:
+ 1 - only one context (default).
+ N>1 - will execute N copies in parallel.
+
+ Note:
+ If this flag is defined to more then 1, an implementation for launching parallel contexts must be defined.
+
+ Two sample implementations are provided. Use <USE_PTHREAD> or <USE_FORK> to enable them.
+
+ It is valid to have a different implementation of <core_start_parallel> and <core_end_parallel> in <core_portme.c>,
+ to fit a particular architecture.
+*/
+#ifndef MULTITHREAD
+#define MULTITHREAD 1
+#endif
+
+/* Configuration: USE_PTHREAD
+ Sample implementation for launching parallel contexts
+ This implementation uses pthread_thread_create and pthread_join.
+
+ Valid values:
+ 0 - Do not use pthreads API.
+ 1 - Use pthreads API
+
+ Note:
+ This flag only matters if MULTITHREAD has been defined to a value greater then 1.
+*/
+#ifndef USE_PTHREAD
+#define USE_PTHREAD 0
+#endif
+
+/* Configuration: USE_FORK
+ Sample implementation for launching parallel contexts
+ This implementation uses fork, waitpid, shmget,shmat and shmdt.
+
+ Valid values:
+ 0 - Do not use fork API.
+ 1 - Use fork API
+
+ Note:
+ This flag only matters if MULTITHREAD has been defined to a value greater then 1.
+*/
+#ifndef USE_FORK
+#define USE_FORK 0
+#endif
+
+/* Configuration: USE_SOCKET
+ Sample implementation for launching parallel contexts
+ This implementation uses fork, socket, sendto and recvfrom
+
+ Valid values:
+ 0 - Do not use fork and sockets API.
+ 1 - Use fork and sockets API
+
+ Note:
+ This flag only matters if MULTITHREAD has been defined to a value greater then 1.
+*/
+#ifndef USE_SOCKET
+#define USE_SOCKET 0
+#endif
+
+/* Configuration: MAIN_HAS_NOARGC
+ Needed if platform does not support getting arguments to main.
+
+ Valid values:
+ 0 - argc/argv to main is supported
+ 1 - argc/argv to main is not supported
+*/
+#ifndef MAIN_HAS_NOARGC
+#define MAIN_HAS_NOARGC 0
+#endif
+
+/* Configuration: MAIN_HAS_NORETURN
+ Needed if platform does not support returning a value from main.
+
+ Valid values:
+ 0 - main returns an int, and return value will be 0.
+ 1 - platform does not support returning a value from main
+*/
+#ifndef MAIN_HAS_NORETURN
+#define MAIN_HAS_NORETURN 0
+#endif
+
+/* Variable: default_num_contexts
+ Number of contexts to spawn in multicore context.
+ Override this global value to change number of contexts used.
+
+ Note:
+ This value may not be set higher then the <MULTITHREAD> define.
+
+ To experiment, you can set the <MULTITHREAD> define to the highest value expected, and use argc/argv in the <portable_init> to set this value from the command line.
+*/
+extern ee_u32 default_num_contexts;
+
+#if (MULTITHREAD>1)
+#if USE_PTHREAD
+ #include <pthread.h>
+ #define PARALLEL_METHOD "PThreads"
+#elif USE_FORK
+ #include <unistd.h>
+ #include <errno.h>
+ #include <sys/wait.h>
+ #include <sys/shm.h>
+ #include <string.h> /* for memcpy */
+ #define PARALLEL_METHOD "Fork"
+#elif USE_SOCKET
+ #include <sys/types.h>
+ #include <sys/socket.h>
+ #include <netinet/in.h>
+ #include <arpa/inet.h>
+ #include <sys/wait.h>
+ #include <stdio.h>
+ #include <stdlib.h>
+ #include <string.h>
+ #include <unistd.h>
+ #include <errno.h>
+ #define PARALLEL_METHOD "Sockets"
+#else
+ #define PARALLEL_METHOD "Proprietary"
+ #error "Please implement multicore functionality in core_portme.c to use multiple contexts."
+#endif /* Method for multithreading */
+#endif /* MULTITHREAD > 1 */
+
+typedef struct CORE_PORTABLE_S {
+#if (MULTITHREAD>1)
+ #if USE_PTHREAD
+ pthread_t thread;
+ #elif USE_FORK
+ pid_t pid;
+ int shmid;
+ void *shm;
+ #elif USE_SOCKET
+ pid_t pid;
+ int sock;
+ struct sockaddr_in sa;
+ #endif /* Method for multithreading */
+#endif /* MULTITHREAD>1 */
+ ee_u8 portable_id;
+} core_portable;
+
+/* target specific init/fini */
+void portable_init(core_portable *p, int *argc, char *argv[]);
+void portable_fini(core_portable *p);
+
+#if (SEED_METHOD==SEED_VOLATILE)
+ #if (VALIDATION_RUN || PERFORMANCE_RUN || PROFILE_RUN)
+ #define RUN_TYPE_FLAG 1
+ #else
+ #if (TOTAL_DATA_SIZE==1200)
+ #define PROFILE_RUN 1
+ #else
+ #define PERFORMANCE_RUN 1
+ #endif
+ #endif
+#endif /* SEED_METHOD==SEED_VOLATILE */
+
+#endif /* CORE_PORTME_H */
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/linux64/core_portme.mak b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/linux64/core_portme.mak
new file mode 100755
index 0000000..5cfabee
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/linux64/core_portme.mak
@@ -0,0 +1,140 @@
+# Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# Original Author: Shay Gal-on
+
+#File: core_portme.mak
+
+# Flag: OUTFLAG
+# Use this flag to define how to to get an executable (e.g -o)
+OUTFLAG= -o
+# Flag: CC
+# Use this flag to define compiler to use
+CC = gcc
+# Flag: CFLAGS
+# Use this flag to define compiler options. Note, you can add compiler options from the command line using XCFLAGS="other flags"
+PORT_CFLAGS = -O2
+FLAGS_STR = "$(PORT_CFLAGS) $(XCFLAGS) $(XLFLAGS) $(LFLAGS_END)"
+CFLAGS = $(PORT_CFLAGS) -I$(PORT_DIR) -I. -DFLAGS_STR=\"$(FLAGS_STR)\"
+#Flag: LFLAGS_END
+# Define any libraries needed for linking or other flags that should come at the end of the link line (e.g. linker scripts).
+# Note: On certain platforms, the default clock_gettime implementation is supported but requires linking of librt.
+LFLAGS_END += -lrt
+# Flag: PORT_SRCS
+# Port specific source files can be added here
+PORT_SRCS = $(PORT_DIR)/core_portme.c
+# Flag: LOAD
+# Define this flag if you need to load to a target, as in a cross compile environment.
+
+# Flag: RUN
+# Define this flag if running does not consist of simple invocation of the binary.
+# In a cross compile environment, you need to define this.
+
+#For flashing and using a tera term macro, you could use
+#LOAD = flash ADDR
+#RUN = ttpmacro coremark.ttl
+
+#For copying to target and executing via SSH connection, you could use
+#LOAD = scp $(OUTFILE) user@target:~
+#RUN = ssh user@target -c
+
+#For native compilation and execution
+LOAD = echo Loading done
+RUN =
+
+OEXT = .o
+EXE = .exe
+
+# Flag: SEPARATE_COMPILE
+# Define if you need to separate compilation from link stage.
+# In this case, you also need to define below how to create an object file, and how to link.
+ifdef SEPARATE_COMPILE
+
+LD = gcc
+OBJOUT = -o
+LFLAGS =
+OFLAG = -o
+COUT = -c
+# Flag: PORT_OBJS
+# Port specific object files can be added here
+PORT_OBJS = $(PORT_DIR)/core_portme$(OEXT)
+PORT_CLEAN = *$(OEXT)
+
+$(OPATH)%$(OEXT) : %.c
+ $(CC) $(CFLAGS) $(XCFLAGS) $(COUT) $< $(OBJOUT) $@
+
+endif
+
+# Target: port_prebuild
+# Generate any files that are needed before actual build starts.
+# E.g. generate profile guidance files. Sample PGO generation for gcc enabled with PGO=1
+# - First, check if PGO was defined on the command line, if so, need to add -fprofile-use to compile line.
+# - Second, if PGO reference has not yet been generated, add a step to the prebuild that will build a profile-generate version and run it.
+# Note - Using REBUILD=1
+#
+# Use make PGO=1 to invoke this sample processing.
+
+ifdef PGO
+ ifeq (,$(findstring $(PGO),gen))
+ PGO_STAGE=build_pgo_gcc
+ CFLAGS+=-fprofile-use
+ endif
+ PORT_CLEAN+=*.gcda *.gcno gmon.out
+endif
+
+.PHONY: port_prebuild
+port_prebuild: $(PGO_STAGE)
+
+.PHONY: build_pgo_gcc
+build_pgo_gcc:
+ $(MAKE) PGO=gen XCFLAGS="$(XCFLAGS) -fprofile-generate -DTOTAL_DATA_SIZE=1200" ITERATIONS=10 gen_pgo_data REBUILD=1
+
+# Target: port_postbuild
+# Generate any files that are needed after actual build end.
+# E.g. change format to srec, bin, zip in order to be able to load into flash
+.PHONY: port_postbuild
+port_postbuild:
+
+# Target: port_postrun
+# Do platform specific after run stuff.
+# E.g. reset the board, backup the logfiles etc.
+.PHONY: port_postrun
+port_postrun:
+
+# Target: port_prerun
+# Do platform specific after run stuff.
+# E.g. reset the board, backup the logfiles etc.
+.PHONY: port_prerun
+port_prerun:
+
+# Target: port_postload
+# Do platform specific after load stuff.
+# E.g. reset the reset power to the flash eraser
+.PHONY: port_postload
+port_postload:
+
+# Target: port_preload
+# Do platform specific before load stuff.
+# E.g. reset the reset power to the flash eraser
+.PHONY: port_preload
+port_preload:
+
+# FLAG: OPATH
+# Path to the output folder. Default - current folder.
+OPATH = ./
+MKDIR = mkdir -p
+
+# FLAG: PERL
+# Define perl executable to calculate the geomean if running separate.
+PERL=/usr/bin/perl
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/simple/core_portme.c b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/simple/core_portme.c
new file mode 100755
index 0000000..33c863d
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/simple/core_portme.c
@@ -0,0 +1,128 @@
+/*
+Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Original Author: Shay Gal-on
+*/
+
+#include <stdio.h>
+#include <stdlib.h>
+#include "coremark.h"
+
+#if VALIDATION_RUN
+ volatile ee_s32 seed1_volatile=0x3415;
+ volatile ee_s32 seed2_volatile=0x3415;
+ volatile ee_s32 seed3_volatile=0x66;
+#endif
+#if PERFORMANCE_RUN
+ volatile ee_s32 seed1_volatile=0x0;
+ volatile ee_s32 seed2_volatile=0x0;
+ volatile ee_s32 seed3_volatile=0x66;
+#endif
+#if PROFILE_RUN
+ volatile ee_s32 seed1_volatile=0x8;
+ volatile ee_s32 seed2_volatile=0x8;
+ volatile ee_s32 seed3_volatile=0x8;
+#endif
+ volatile ee_s32 seed4_volatile=ITERATIONS;
+ volatile ee_s32 seed5_volatile=0;
+/* Porting : Timing functions
+ How to capture time and convert to seconds must be ported to whatever is supported by the platform.
+ e.g. Read value from on board RTC, read value from cpu clock cycles performance counter etc.
+ Sample implementation for standard time.h and windows.h definitions included.
+*/
+/* Define : TIMER_RES_DIVIDER
+ Divider to trade off timer resolution and total time that can be measured.
+
+ Use lower values to increase resolution, but make sure that overflow does not occur.
+ If there are issues with the return value overflowing, increase this value.
+ */
+#define NSECS_PER_SEC CLOCKS_PER_SEC
+#define CORETIMETYPE clock_t
+#define GETMYTIME(_t) (*_t=clock())
+#define MYTIMEDIFF(fin,ini) ((fin)-(ini))
+#define TIMER_RES_DIVIDER 1
+#define SAMPLE_TIME_IMPLEMENTATION 1
+#define EE_TICKS_PER_SEC (NSECS_PER_SEC / TIMER_RES_DIVIDER)
+
+/** Define Host specific (POSIX), or target specific global time variables. */
+static CORETIMETYPE start_time_val, stop_time_val;
+
+/* Function : start_time
+ This function will be called right before starting the timed portion of the benchmark.
+
+ Implementation may be capturing a system timer (as implemented in the example code)
+ or zeroing some system parameters - e.g. setting the cpu clocks cycles to 0.
+*/
+void start_time(void) {
+ GETMYTIME(&start_time_val );
+}
+/* Function : stop_time
+ This function will be called right after ending the timed portion of the benchmark.
+
+ Implementation may be capturing a system timer (as implemented in the example code)
+ or other system parameters - e.g. reading the current value of cpu cycles counter.
+*/
+void stop_time(void) {
+ GETMYTIME(&stop_time_val );
+}
+/* Function : get_time
+ Return an abstract "ticks" number that signifies time on the system.
+
+ Actual value returned may be cpu cycles, milliseconds or any other value,
+ as long as it can be converted to seconds by <time_in_secs>.
+ This methodology is taken to accomodate any hardware or simulated platform.
+ The sample implementation returns millisecs by default,
+ and the resolution is controlled by <TIMER_RES_DIVIDER>
+*/
+CORE_TICKS get_time(void) {
+ CORE_TICKS elapsed=(CORE_TICKS)(MYTIMEDIFF(stop_time_val, start_time_val));
+ return elapsed;
+}
+/* Function : time_in_secs
+ Convert the value returned by get_time to seconds.
+
+ The <secs_ret> type is used to accomodate systems with no support for floating point.
+ Default implementation implemented by the EE_TICKS_PER_SEC macro above.
+*/
+secs_ret time_in_secs(CORE_TICKS ticks) {
+ secs_ret retval=((secs_ret)ticks) / (secs_ret)EE_TICKS_PER_SEC;
+ return retval;
+}
+
+ee_u32 default_num_contexts=1;
+
+/* Function : portable_init
+ Target specific initialization code
+ Test for some common mistakes.
+*/
+void portable_init(core_portable *p, int *argc, char *argv[])
+{
+ if (sizeof(ee_ptr_int) != sizeof(ee_u8 *)) {
+ ee_printf("ERROR! Please define ee_ptr_int to a type that holds a pointer!\n");
+ }
+ if (sizeof(ee_u32) != 4) {
+ ee_printf("ERROR! Please define ee_u32 to a 32b unsigned type!\n");
+ }
+ p->portable_id=1;
+}
+/* Function : portable_fini
+ Target specific final code
+*/
+void portable_fini(core_portable *p)
+{
+ p->portable_id=0;
+}
+
+
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/simple/core_portme.h b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/simple/core_portme.h
new file mode 100755
index 0000000..a3607bf
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/simple/core_portme.h
@@ -0,0 +1,196 @@
+/*
+Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Original Author: Shay Gal-on
+*/
+
+/* Topic : Description
+ This file contains configuration constants required to execute on different platforms
+*/
+#ifndef CORE_PORTME_H
+#define CORE_PORTME_H
+/************************/
+/* Data types and settings */
+/************************/
+/* Configuration : HAS_FLOAT
+ Define to 1 if the platform supports floating point.
+*/
+#ifndef HAS_FLOAT
+#define HAS_FLOAT 1
+#endif
+/* Configuration : HAS_TIME_H
+ Define to 1 if platform has the time.h header file,
+ and implementation of functions thereof.
+*/
+#ifndef HAS_TIME_H
+#define HAS_TIME_H 1
+#endif
+/* Configuration : USE_CLOCK
+ Define to 1 if platform has the time.h header file,
+ and implementation of functions thereof.
+*/
+#ifndef USE_CLOCK
+#define USE_CLOCK 1
+#endif
+/* Configuration : HAS_STDIO
+ Define to 1 if the platform has stdio.h.
+*/
+#ifndef HAS_STDIO
+#define HAS_STDIO 1
+#endif
+/* Configuration : HAS_PRINTF
+ Define to 1 if the platform has stdio.h and implements the printf function.
+*/
+#ifndef HAS_PRINTF
+#define HAS_PRINTF 1
+#endif
+
+/* Configuration : CORE_TICKS
+ Define type of return from the timing functions.
+ */
+#include <time.h>
+typedef clock_t CORE_TICKS;
+
+/* Definitions : COMPILER_VERSION, COMPILER_FLAGS, MEM_LOCATION
+ Initialize these strings per platform
+*/
+#ifndef COMPILER_VERSION
+ #ifdef __GNUC__
+ #define COMPILER_VERSION "GCC"__VERSION__
+ #else
+ #define COMPILER_VERSION "Please put compiler version here (e.g. gcc 4.1)"
+ #endif
+#endif
+#ifndef COMPILER_FLAGS
+ #define COMPILER_FLAGS FLAGS_STR /* "Please put compiler flags here (e.g. -o3)" */
+#endif
+#ifndef MEM_LOCATION
+ #define MEM_LOCATION "STACK"
+#endif
+
+/* Data Types :
+ To avoid compiler issues, define the data types that need ot be used for 8b, 16b and 32b in <core_portme.h>.
+
+ *Imprtant* :
+ ee_ptr_int needs to be the data type used to hold pointers, otherwise coremark may fail!!!
+*/
+typedef signed short ee_s16;
+typedef unsigned short ee_u16;
+typedef signed int ee_s32;
+typedef double ee_f32;
+typedef unsigned char ee_u8;
+typedef unsigned int ee_u32;
+typedef ee_u32 ee_ptr_int;
+typedef size_t ee_size_t;
+/* align_mem :
+ This macro is used to align an offset to point to a 32b value. It is used in the Matrix algorithm to initialize the input memory blocks.
+*/
+#define align_mem(x) (void *)(4 + (((ee_ptr_int)(x) - 1) & ~3))
+
+/* Configuration : SEED_METHOD
+ Defines method to get seed values that cannot be computed at compile time.
+
+ Valid values :
+ SEED_ARG - from command line.
+ SEED_FUNC - from a system function.
+ SEED_VOLATILE - from volatile variables.
+*/
+#ifndef SEED_METHOD
+#define SEED_METHOD SEED_VOLATILE
+#endif
+
+/* Configuration : MEM_METHOD
+ Defines method to get a block of memry.
+
+ Valid values :
+ MEM_MALLOC - for platforms that implement malloc and have malloc.h.
+ MEM_STATIC - to use a static memory array.
+ MEM_STACK - to allocate the data block on the stack (NYI).
+*/
+#ifndef MEM_METHOD
+#define MEM_METHOD MEM_STACK
+#endif
+
+/* Configuration : MULTITHREAD
+ Define for parallel execution
+
+ Valid values :
+ 1 - only one context (default).
+ N>1 - will execute N copies in parallel.
+
+ Note :
+ If this flag is defined to more then 1, an implementation for launching parallel contexts must be defined.
+
+ Two sample implementations are provided. Use <USE_PTHREAD> or <USE_FORK> to enable them.
+
+ It is valid to have a different implementation of <core_start_parallel> and <core_end_parallel> in <core_portme.c>,
+ to fit a particular architecture.
+*/
+#ifndef MULTITHREAD
+#define MULTITHREAD 1
+#define USE_PTHREAD 0
+#define USE_FORK 0
+#define USE_SOCKET 0
+#endif
+
+/* Configuration : MAIN_HAS_NOARGC
+ Needed if platform does not support getting arguments to main.
+
+ Valid values :
+ 0 - argc/argv to main is supported
+ 1 - argc/argv to main is not supported
+
+ Note :
+ This flag only matters if MULTITHREAD has been defined to a value greater then 1.
+*/
+#ifndef MAIN_HAS_NOARGC
+#define MAIN_HAS_NOARGC 0
+#endif
+
+/* Configuration : MAIN_HAS_NORETURN
+ Needed if platform does not support returning a value from main.
+
+ Valid values :
+ 0 - main returns an int, and return value will be 0.
+ 1 - platform does not support returning a value from main
+*/
+#ifndef MAIN_HAS_NORETURN
+#define MAIN_HAS_NORETURN 0
+#endif
+
+/* Variable : default_num_contexts
+ Not used for this simple port, must cintain the value 1.
+*/
+extern ee_u32 default_num_contexts;
+
+typedef struct CORE_PORTABLE_S {
+ ee_u8 portable_id;
+} core_portable;
+
+/* target specific init/fini */
+void portable_init(core_portable *p, int *argc, char *argv[]);
+void portable_fini(core_portable *p);
+
+#if !defined(PROFILE_RUN) && !defined(PERFORMANCE_RUN) && !defined(VALIDATION_RUN)
+#if (TOTAL_DATA_SIZE==1200)
+#define PROFILE_RUN 1
+#elif (TOTAL_DATA_SIZE==2000)
+#define PERFORMANCE_RUN 1
+#else
+#define VALIDATION_RUN 1
+#endif
+#endif
+
+#endif /* CORE_PORTME_H */
diff --git a/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/simple/core_portme.mak b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/simple/core_portme.mak
new file mode 100755
index 0000000..61c3db6
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/eembc_coremark/simple/core_portme.mak
@@ -0,0 +1,60 @@
+# Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# Original Author: Shay Gal-on
+
+#File : core_portme.mak
+
+# Flag : OUTFLAG
+# Use this flag to define how to to get an executable (e.g -o)
+OUTFLAG= -o
+# Flag : CC
+# Use this flag to define compiler to use
+CC = gcc
+# Flag : CFLAGS
+# Use this flag to define compiler options. Note, you can add compiler options from the command line using XCFLAGS="other flags"
+PORT_CFLAGS = -O2
+FLAGS_STR = "$(PORT_CFLAGS) $(XCFLAGS) $(XLFLAGS) $(LFLAGS_END)"
+CFLAGS = $(PORT_CFLAGS) -I$(PORT_DIR) -I. -DFLAGS_STR=\"$(FLAGS_STR)\"
+#Flag : LFLAGS_END
+# Define any libraries needed for linking or other flags that should come at the end of the link line (e.g. linker scripts).
+# Note : On certain platforms, the default clock_gettime implementation is supported but requires linking of librt.
+LFLAGS_END =
+# Flag : PORT_SRCS
+# Port specific source files can be added here
+PORT_SRCS = $(PORT_DIR)/core_portme.c
+# Flag : LOAD
+# For a simple port, we assume self hosted compile and run, no load needed.
+
+# Flag : RUN
+# For a simple port, we assume self hosted compile and run, simple invocation of the executable
+
+#For native compilation and execution
+LOAD = echo Loading done
+RUN =
+
+OEXT = .o
+EXE = .exe
+
+# Target : port_pre% and port_post%
+# For the purpose of this simple port, no pre or post steps needed.
+
+.PHONY : port_prebuild port_postbuild port_prerun port_postrun port_preload port_postload
+port_pre% port_post% :
+
+# FLAG : OPATH
+# Path to the output folder. Default - current folder.
+OPATH = ./
+MKDIR = mkdir -p
+
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv.lock.hjson b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv.lock.hjson
index 21ded15..64e4d30 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv.lock.hjson
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv.lock.hjson
@@ -9,6 +9,6 @@
upstream:
{
url: https://github.com/google/riscv-dv
- rev: 4583049cc2b3469ba9dea56b5e2d75809a89d8f3
+ rev: 76753158d940fffc53fbb92942ae5d1d768a7cdc
}
}
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/run.py b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/run.py
index 9e1a6af..bae34b7 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/run.py
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/run.py
@@ -250,6 +250,7 @@
if verbose:
cmd += "+UVM_VERBOSITY=UVM_HIGH "
cmd = re.sub("<seed>", str(rand_seed), cmd)
+ cmd = re.sub("<test_id>", test_id, cmd)
sim_seed[test_id] = str(rand_seed)
if "gen_opts" in test:
cmd += test['gen_opts']
@@ -730,6 +731,8 @@
help="Stop on detecting first error")
parser.add_argument("--noclean", action="store_true", default=True,
help="Do not clean the output of the previous runs")
+ parser.add_argument("--verilog_style_check", action="store_true", default=False,
+ help="Run verilog style check")
parser.add_argument("-d", "--debug", type=str, default="",
help="Generate debug command log file")
return parser
@@ -772,6 +775,9 @@
elif args.target == "multi_harts":
args.mabi = "ilp32"
args.isa = "rv32gc"
+ elif args.target == "rv32imcb":
+ args.mabi = "ilp32"
+ args.isa = "rv32imcb"
elif args.target == "rv32i":
args.mabi = "ilp32"
args.isa = "rv32i"
@@ -813,6 +819,11 @@
# Create output directory
output_dir = create_output(args.o, args.noclean)
+ if args.verilog_style_check:
+ logging.debug("Run style check")
+ style_err = run_cmd("verilog_style/run.sh")
+ if style_err: logging.info("Found style error: \nERROR: " + style_err)
+
# Run any handcoded/directed assembly tests specified by args.asm_tests
if args.asm_tests != "":
asm_test = args.asm_tests.split(',')
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/scripts/spike_log_to_trace_csv.py b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/scripts/spike_log_to_trace_csv.py
index edba18b..e099ab7 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/scripts/spike_log_to_trace_csv.py
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/scripts/spike_log_to_trace_csv.py
@@ -34,70 +34,6 @@
LOGGER = logging.getLogger()
-def process_spike_sim_log(spike_log, csv, full_trace = 0):
- """Process SPIKE simulation log.
-
- Extract instruction and affected register information from spike simulation
- log and save to a list.
- """
- logging.info("Processing spike log : %s" % spike_log)
- instr_cnt = 0
- spike_instr = ""
-
- # Remove all the init spike boot instructions
- cmd = ("sed -i '/core.*0x0000000000001010/,$!d' %s" % spike_log)
- os.system(cmd)
- # Remove all instructions after ecall (end of program excecution)
- cmd = ("sed -i '/ecall/q' %s" % spike_log)
- os.system(cmd)
-
- with open(spike_log, "r") as f, open(csv, "w") as csv_fd:
- trace_csv = RiscvInstructionTraceCsv(csv_fd)
- trace_csv.start_new_trace()
- for line in f:
- # Extract instruction infromation
- m = CORE_RE.search(line)
- if m:
- instr_cnt += 1
- spike_instr = m.group("instr").replace("pc + ", "")
- spike_instr = spike_instr.replace("pc - ", "-")
- rv_instr_trace = RiscvInstructionTraceEntry()
- rv_instr_trace.pc = m.group("addr")
- rv_instr_trace.instr_str = spike_instr
- rv_instr_trace.binary = m.group("bin")
- if full_trace:
- rv_instr_trace.instr = spike_instr.split(" ")[0]
- rv_instr_trace.operand = spike_instr[len(rv_instr_trace.instr):]
- rv_instr_trace.operand = rv_instr_trace.operand.replace(" ", "")
- rv_instr_trace.instr, rv_instr_trace.operand = convert_pseudo_instr(
- rv_instr_trace.instr, rv_instr_trace.operand, rv_instr_trace.binary)
- process_instr(rv_instr_trace)
- if spike_instr == "wfi":
- trace_csv.write_trace_entry(rv_instr_trace)
- continue
- nextline = f.readline()
- if nextline != "":
- if ILLE_RE.search(nextline):
- if full_trace:
- logging.debug("Illegal instruction: %s, opcode:%s" %
- (rv_instr_trace.instr_str, rv_instr_trace.binary))
- trace_csv.write_trace_entry(rv_instr_trace)
- continue
- m = RD_RE.search(nextline)
- if m:
- # Extract RD information
- rv_instr_trace.gpr.append(
- gpr_to_abi(m.group("reg").replace(" ","")) + ":" + m.group("val"))
- rv_instr_trace.mode = m.group("pri")
- else:
- # If full trace is not enabled, skip the entry that doesn't have
- # architectural state update.
- if not full_trace:
- continue
- trace_csv.write_trace_entry(rv_instr_trace)
- logging.info("Processed instruction count : %d" % instr_cnt)
- logging.info("CSV saved to : %s" % csv)
-
def process_instr(trace):
if trace.instr == "jal":
@@ -113,6 +49,171 @@
trace.operand = trace.operand.replace(")", "")
+def read_spike_instr(match, full_trace):
+ '''Unpack a regex match for CORE_RE to a RiscvInstructionTraceEntry
+
+ If full_trace is true, extract operand data from the disassembled
+ instruction.
+
+ '''
+
+ # Extract the disassembled instruction.
+ disasm = match.group('instr')
+
+ # Spike's disassembler shows a relative jump as something like "j pc +
+ # 0x123" or "j pc - 0x123". We just want the relative offset.
+ disasm = disasm.replace('pc + ', '').replace('pc - ', '-')
+
+ instr = RiscvInstructionTraceEntry()
+ instr.pc = match.group('addr')
+ instr.instr_str = disasm
+ instr.binary = match.group('bin')
+
+ if full_trace:
+ opcode = disasm.split(' ')[0]
+ operand = disasm[len(opcode):].replace(' ', '')
+ instr.instr, instr.operand = \
+ convert_pseudo_instr(opcode, operand, instr.binary)
+
+ process_instr(instr)
+
+ return instr
+
+
+def read_spike_trace(path, full_trace):
+ '''Read a Spike simulation log at <path>, yielding executed instructions.
+
+ This assumes that the log was generated with the -l and --log-commits options
+ to Spike.
+
+ If full_trace is true, extract operands from the disassembled instructions.
+
+ Since Spike has a strange trampoline that always runs at the start, we skip
+ instructions up to and including the one at PC 0x1010 (the end of the
+ trampoline). At the end of a DV program, there's an ECALL instruction, which
+ we take as a signal to stop checking, so we ditch everything that follows
+ that instruction.
+
+ This function yields instructions as it parses them as tuples of the form
+ (entry, illegal). entry is a RiscvInstructionTraceEntry. illegal is a
+ boolean, which is true if the instruction caused an illegal instruction trap.
+
+ '''
+
+ # This loop is a simple FSM with states TRAMPOLINE, INSTR, EFFECT. The idea
+ # is that we're in state TRAMPOLINE until we get to the end of Spike's
+ # trampoline, then we switch between INSTR (where we expect to read an
+ # instruction) and EFFECT (where we expect to read commit information).
+ #
+ # We yield a RiscvInstructionTraceEntry object each time we leave EFFECT
+ # (going back to INSTR), we loop back from INSTR to itself, or we get to the
+ # end of the file and have an instruction in hand.
+ #
+ # On entry to the loop body, we are in state TRAMPOLINE if in_trampoline is
+ # true. Otherwise, we are in state EFFECT if instr is not None, otherwise we
+ # are in state INSTR.
+
+ end_trampoline_re = re.compile(r'core.*: 0x0*1010 ')
+
+ in_trampoline = True
+ instr = None
+
+ with open(path, 'r') as handle:
+ for line in handle:
+ if in_trampoline:
+ # The TRAMPOLINE state
+ if end_trampoline_re.match(line):
+ in_trampoline = False
+ continue
+
+ if instr is None:
+ # The INSTR state. We expect to see a line matching CORE_RE. We'll
+ # discard any other lines.
+ instr_match = CORE_RE.match(line)
+ if not instr_match:
+ continue
+
+ instr = read_spike_instr(instr_match, full_trace)
+
+ # If instr.instr_str is 'ecall', we should stop.
+ if instr.instr_str == 'ecall':
+ break
+
+ continue
+
+ # The EFFECT state. If the line matches CORE_RE, we should have been in
+ # state INSTR, so we yield the instruction we had, read the new
+ # instruction and continue. As above, if the new instruction is 'ecall',
+ # we need to stop immediately.
+ instr_match = CORE_RE.match(line)
+ if instr_match:
+ yield (instr, False)
+ instr = read_spike_instr(instr_match, full_trace)
+ if instr.instr_str == 'ecall':
+ break
+ continue
+
+ # The line doesn't match CORE_RE, so we are definitely on a follow-on
+ # line in the log. First, check for illegal instructions
+ if 'trap_illegal_instruction' in line:
+ yield (instr, True)
+ instr = None
+ continue
+
+ # The instruction seems to have been fine. Do we have commit data (from
+ # the --log-commits Spike option)?
+ commit_match = RD_RE.match(line)
+ if commit_match:
+ instr.gpr.append(gpr_to_abi(commit_match.group('reg')
+ .replace(' ', '')) +
+ ':' + commit_match.group('val'))
+ instr.mode = commit_match.group('pri')
+
+ # At EOF, we might have an instruction in hand. Yield it if so.
+ if instr is not None:
+ yield (instr, False)
+
+
+def process_spike_sim_log(spike_log, csv, full_trace = 0):
+ """Process SPIKE simulation log.
+
+ Extract instruction and affected register information from spike simulation
+ log and write the results to a CSV file at csv. Returns the number of
+ instructions written.
+
+ """
+ logging.info("Processing spike log : %s" % spike_log)
+ instrs_in = 0
+ instrs_out = 0
+
+ with open(csv, "w") as csv_fd:
+ trace_csv = RiscvInstructionTraceCsv(csv_fd)
+ trace_csv.start_new_trace()
+
+ for (entry, illegal) in read_spike_trace(spike_log, full_trace):
+ instrs_in += 1
+
+ if illegal and full_trace:
+ logging.debug("Illegal instruction: {}, opcode:{}"
+ .format(entry.instr_str, entry.binary))
+
+ # Instructions that cause no architectural update (which includes illegal
+ # instructions) are ignored if full_trace is false.
+ #
+ # We say that an instruction caused an architectural update if either we
+ # saw a commit line (in which case, entry.gpr will contain a single
+ # entry) or the instruction was 'wfi' or 'ecall'.
+ if not (full_trace or entry.gpr or entry.instr_str in ['wfi', 'ecall']):
+ continue
+
+ trace_csv.write_trace_entry(entry)
+ instrs_out += 1
+
+ logging.info("Processed instruction count : %d" % instrs_in)
+ logging.info("CSV saved to : %s" % csv)
+ return instrs_out
+
+
def main():
# Parse input arguments
parser = argparse.ArgumentParser()
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/isa/riscv_b_instr.sv b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/isa/riscv_b_instr.sv
new file mode 100755
index 0000000..48e2415
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/isa/riscv_b_instr.sv
@@ -0,0 +1,476 @@
+/*
+ * Copyright 2019 Google LLC
+ * Copyright 2019 Mellanox Technologies Ltd
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+class riscv_b_instr extends riscv_instr;
+
+ rand riscv_reg_t rs3;
+ bit has_rs3 = 1'b0;
+
+ constraint single_bit_shift_c {
+ if (category == SHIFT) {
+ imm inside {[0:31]};
+ }
+ }
+
+ constraint shuffle_c {
+ if (instr_name inside {SHFLI, UNSHFLI}) {
+ imm inside {[0:15]};
+ }
+ }
+
+ constraint or_combine_c {
+ if (instr_name inside {GORCI}) {
+ imm inside {[0:31]};
+ }
+ if (instr_name inside {GORCIW}) {
+ imm inside {[0:63]};
+ }
+ }
+
+ `uvm_object_utils(riscv_b_instr)
+
+ function new(string name = "");
+ super.new(name);
+ endfunction
+
+ virtual function void set_rand_mode();
+ super.set_rand_mode();
+ has_rs3 = 1'b0;
+ case (format) inside
+ R4_FORMAT: begin
+ has_imm = 1'b0;
+ has_rs3 = 1'b1;
+ end
+ I_FORMAT: begin
+ has_rs2 = 1'b0;
+ if (instr_name inside {FSRI, FSRIW}) begin
+ has_rs3 = 1'b1;
+ end
+ end
+ endcase
+
+ endfunction
+
+ function void pre_randomize();
+ super.pre_randomize();
+ rs3.rand_mode(has_rs3);
+ endfunction
+
+
+ virtual function void set_imm_len();
+
+ if (format inside {I_FORMAT}) begin
+ if (category inside {SHIFT, LOGICAL}) begin
+ imm_len = 7;
+
+ if (group == RV64B) begin
+ imm_len = 5;
+ if (instr_name inside {SLLIU_W}) begin
+ imm_len = 6;
+ end
+ end
+
+ if ((group == RV32B) && (imm_type == UIMM)) begin
+ imm_len = 6;
+ end
+ end
+
+ if ((category inside {ARITHMETIC}) && (group == RV32B)) begin
+ imm_len = 5;
+ end
+
+ if ((category inside {ARITHMETIC}) && (group == RV64B)) begin
+ imm_len = 12;
+ end
+ end
+
+ imm_mask = imm_mask << imm_len;
+ endfunction
+
+ // Convert the instruction to assembly code
+ virtual function string convert2asm(string prefix = "");
+ string asm_str_final, asm_str;
+ asm_str = format_string(get_instr_name(), MAX_INSTR_STR_LEN);
+
+ case (format)
+ I_FORMAT: begin
+ if (instr_name inside {FSRI, FSRIW}) begin // instr rd,rs1,rs3,imm
+ asm_str_final = $sformatf("%0s%0s, %0s, %0s, %0s", asm_str, rd.name(), rs1.name(),
+ rs3.name(), get_imm());
+ end
+ end
+
+ R_FORMAT: begin //instr rd rs1
+ if (instr_name inside {CLZW, CTZW, PCNTW, SEXT_B, SEXT_H, CLZ, CTZ, PCNT, BMATFLIP,
+ CRC32_B, CRC32_H, CRC32_W, CRC32C_B, CRC32C_H, CRC32C_W, CRC32_D,
+ CRC32C_D}) begin
+ asm_str_final = $sformatf("%0s%0s, %0s", asm_str, rd.name(), rs1.name());
+ end
+ end
+
+ R4_FORMAT: begin // instr rd,rs1,rs2,rs3
+ asm_str_final = $sformatf("%0s%0s, %0s, %0s, %0s", asm_str, rd.name(), rs1.name(),
+ rs2.name(), rs3.name());
+ end
+ default: `uvm_info(`gfn, $sformatf("Unsupported format %0s", format.name()), UVM_LOW)
+ endcase
+
+ if (asm_str_final == "") begin
+ return super.convert2asm(prefix);
+ end
+
+ if (comment != "") asm_str_final = {asm_str, " #", comment};
+ return asm_str_final.tolower();
+ endfunction
+
+ function bit [6:0] get_opcode();
+ case (instr_name) inside
+ ANDN, ORN, XNOR, GORC, SLO, SRO, ROL, ROR, SBCLR, SBSET, SBINV, SBEXT,
+ GREV: get_opcode = 7'b0110011;
+ SLOI, SROI, RORI, SBCLRI, SBSETI, SBINVI, SBEXTI, GORCI, GREVI, CMIX, CMOV,
+ FSL: get_opcode = 7'b0010011;
+ FSR, FSRI, CLZ, CTZ, PCNT, BMATFLIP, SEXT_B, SEXT_H, CRC32_B, CRC32_H, CRC32_W, CRC32C_B,
+ CRC32C_H: get_opcode = 7'b0010011;
+ CRC32C_W, CRC32_D, CRC32C_D: get_opcode = 7'b0010011;
+ CLMUL, CLMULR, CLMULH, MIN, MAX, MINU, MAXU, SHFL, UNSHFL, BDEP, BEXT, PACK, PACKU, BMATOR,
+ BMATXOR, PACKH, BFP: get_opcode = 7'b0110011;
+ SHFLI, UNSHFLI: get_opcode = 7'b0010011;
+ ADDIWU, SLLIU_W: get_opcode = 7'b0011011;
+ ADDWU, SUBWU, ADDU_W, SUBU_W, SLOW, SROW, ROLW, RORW, SBCLRW, SBSETW, SBINVW, SBEXTW, GORCW,
+ GREVW: get_opcode = 7'b0111011;
+ SLOIW, SROIW, RORIW, SBCLRIW, SBSETIW, SBINVIW, GORCIW, GREVIW: get_opcode = 7'b0011011;
+ FSLW, FSRW: get_opcode = 7'b0111011;
+ FSRIW, CLZW, CTZW, PCNTW: get_opcode = 7'b0011011;
+ CLMULW, CLMULRW, CLMULHW, SHFLW, UNSHFLW, BDEPW, BEXTW, PACKW, PACKUW,
+ BFPW: get_opcode = 7'b0111011;
+ default: get_opcode = super.get_opcode();
+ endcase
+ endfunction
+
+ virtual function bit [2:0] get_func3();
+ case (instr_name) inside
+ ANDN: get_func3 = 3'b111;
+ ORN: get_func3 = 3'b110;
+ XNOR: get_func3 = 3'b100;
+ GORC: get_func3 = 3'b101;
+ SLO: get_func3 = 3'b001;
+ SRO: get_func3 = 3'b101;
+ ROL: get_func3 = 3'b001;
+ ROR: get_func3 = 3'b101;
+ SBCLR: get_func3 = 3'b001;
+ SBSET: get_func3 = 3'b001;
+ SBINV: get_func3 = 3'b001;
+ SBEXT: get_func3 = 3'b101;
+ GREV: get_func3 = 3'b101;
+ SLOI: get_func3 = 3'b001;
+ SROI: get_func3 = 3'b101;
+ RORI: get_func3 = 3'b101;
+ SBCLRI: get_func3 = 3'b001;
+ SBSETI: get_func3 = 3'b001;
+ SBINVI: get_func3 = 3'b001;
+ SBEXTI: get_func3 = 3'b101;
+ GORCI: get_func3 = 3'b101;
+ GREVI: get_func3 = 3'b101;
+ CMIX: get_func3 = 3'b001;
+ CMOV: get_func3 = 3'b101;
+ FSL: get_func3 = 3'b001;
+ FSR: get_func3 = 3'b101;
+ FSRI: get_func3 = 3'b101;
+ CLZ: get_func3 = 3'b001;
+ CTZ: get_func3 = 3'b001;
+ PCNT: get_func3 = 3'b001;
+ BMATFLIP: get_func3 = 3'b001;
+ SEXT_B: get_func3 = 3'b001;
+ SEXT_H: get_func3 = 3'b001;
+ CRC32_B: get_func3 = 3'b001;
+ CRC32_H: get_func3 = 3'b001;
+ CRC32_W: get_func3 = 3'b001;
+ CRC32C_B: get_func3 = 3'b001;
+ CRC32C_H: get_func3 = 3'b001;
+ CRC32C_W: get_func3 = 3'b001;
+ CRC32_D: get_func3 = 3'b001;
+ CRC32C_D: get_func3 = 3'b001;
+ CLMUL: get_func3 = 3'b001;
+ CLMULR: get_func3 = 3'b010;
+ CLMULH: get_func3 = 3'b011;
+ MIN: get_func3 = 3'b100;
+ MAX: get_func3 = 3'b101;
+ MINU: get_func3 = 3'b110;
+ MAXU: get_func3 = 3'b111;
+ SHFL: get_func3 = 3'b001;
+ UNSHFL: get_func3 = 3'b101;
+ BDEP: get_func3 = 3'b110;
+ BEXT: get_func3 = 3'b110;
+ PACK: get_func3 = 3'b100;
+ PACKU: get_func3 = 3'b100;
+ BMATOR: get_func3 = 3'b011;
+ BMATXOR: get_func3 = 3'b011;
+ PACKH: get_func3 = 3'b111;
+ BFP: get_func3 = 3'b111;
+ SHFLI: get_func3 = 3'b001;
+ UNSHFLI: get_func3 = 3'b101;
+ ADDIWU: get_func3 = 3'b100;
+ SLLIU_W: get_func3 = 3'b001;
+ ADDWU: get_func3 = 3'b000;
+ SUBWU: get_func3 = 3'b000;
+ ADDU_W: get_func3 = 3'b000;
+ SUBU_W: get_func3 = 3'b000;
+ SLOW: get_func3 = 3'b001;
+ SROW: get_func3 = 3'b101;
+ ROLW: get_func3 = 3'b001;
+ RORW: get_func3 = 3'b101;
+ SBCLRW: get_func3 = 3'b001;
+ SBSETW: get_func3 = 3'b001;
+ SBINVW: get_func3 = 3'b001;
+ SBEXTW: get_func3 = 3'b101;
+ GORCW: get_func3 = 3'b101;
+ GREVW: get_func3 = 3'b101;
+ SLOIW: get_func3 = 3'b001;
+ SROIW: get_func3 = 3'b101;
+ RORIW: get_func3 = 3'b101;
+ SBCLRIW: get_func3 = 3'b001;
+ SBSETIW: get_func3 = 3'b001;
+ SBINVIW: get_func3 = 3'b001;
+ GORCIW: get_func3 = 3'b101;
+ GREVIW: get_func3 = 3'b101;
+ FSLW: get_func3 = 3'b001;
+ FSRW: get_func3 = 3'b101;
+ FSRIW: get_func3 = 3'b101;
+ CLZW: get_func3 = 3'b001;
+ CTZW: get_func3 = 3'b001;
+ PCNTW: get_func3 = 3'b001;
+ CLMULW: get_func3 = 3'b001;
+ CLMULRW: get_func3 = 3'b010;
+ CLMULHW: get_func3 = 3'b011;
+ SHFLW: get_func3 = 3'b001;
+ UNSHFLW: get_func3 = 3'b101;
+ BDEPW: get_func3 = 3'b110;
+ BEXTW: get_func3 = 3'b110;
+ PACKW: get_func3 = 3'b100;
+ PACKUW: get_func3 = 3'b100;
+ BFPW: get_func3 = 3'b111;
+ default: get_func3 = super.get_func3();
+ endcase
+ ;
+ endfunction
+
+ function bit [6:0] get_func7();
+ case (instr_name) inside
+ ANDN: get_func7 = 7'b0100000;
+ ORN: get_func7 = 7'b0100000;
+ XNOR: get_func7 = 7'b0100000;
+ GORC: get_func7 = 7'b0010100;
+ SLO: get_func7 = 7'b0010000;
+ SRO: get_func7 = 7'b0010000;
+ ROL: get_func7 = 7'b0110000;
+ ROR: get_func7 = 7'b0110000;
+ SBCLR: get_func7 = 7'b0100100;
+ SBSET: get_func7 = 7'b0010100;
+ SBINV: get_func7 = 7'b0110100;
+ SBEXT: get_func7 = 7'b0100100;
+ GREV: get_func7 = 7'b0110100;
+ CLZ: get_func7 = 7'b0110000;
+ CTZ: get_func7 = 7'b0110000;
+ PCNT: get_func7 = 7'b0110000;
+ BMATFLIP: get_func7 = 7'b0110000;
+ SEXT_B: get_func7 = 7'b0110000;
+ SEXT_H: get_func7 = 7'b0110000;
+ CRC32_B: get_func7 = 7'b0110000;
+ CRC32_H: get_func7 = 7'b0110000;
+ CRC32_W: get_func7 = 7'b0110000;
+ CRC32C_B: get_func7 = 7'b0110000;
+ CRC32C_H: get_func7 = 7'b0110000;
+ CRC32C_W: get_func7 = 7'b0110000;
+ CRC32_D: get_func7 = 7'b0110000;
+ CRC32C_D: get_func7 = 7'b0110000;
+ CLMUL: get_func7 = 7'b0000101;
+ CLMULR: get_func7 = 7'b0000101;
+ CLMULH: get_func7 = 7'b0000101;
+ MIN: get_func7 = 7'b0000101;
+ MAX: get_func7 = 7'b0000101;
+ MINU: get_func7 = 7'b0000101;
+ MAXU: get_func7 = 7'b0000101;
+ SHFL: get_func7 = 7'b0000100;
+ UNSHFL: get_func7 = 7'b0000100;
+ BDEP: get_func7 = 7'b0100100;
+ BEXT: get_func7 = 7'b0000100;
+ PACK: get_func7 = 7'b0000100;
+ PACKU: get_func7 = 7'b0100100;
+ BMATOR: get_func7 = 7'b0000100;
+ BMATXOR: get_func7 = 7'b0100100;
+ PACKH: get_func7 = 7'b0000100;
+ BFP: get_func7 = 7'b0100100;
+ ADDWU: get_func7 = 7'b0000101;
+ SUBWU: get_func7 = 7'b0100101;
+ ADDU_W: get_func7 = 7'b0000100;
+ SUBU_W: get_func7 = 7'b0100100;
+ SLOW: get_func7 = 7'b0010000;
+ SROW: get_func7 = 7'b0010000;
+ ROLW: get_func7 = 7'b0110000;
+ RORW: get_func7 = 7'b0110000;
+ SBCLRW: get_func7 = 7'b0100100;
+ SBSETW: get_func7 = 7'b0010100;
+ SBINVW: get_func7 = 7'b0110100;
+ SBEXTW: get_func7 = 7'b0100100;
+ GORCW: get_func7 = 7'b0010100;
+ GREVW: get_func7 = 7'b0110100;
+ SLOIW: get_func7 = 7'b0010000;
+ SROIW: get_func7 = 7'b0010000;
+ RORIW: get_func7 = 7'b0110000;
+ SBCLRIW: get_func7 = 7'b0100100;
+ SBSETIW: get_func7 = 7'b0010100;
+ SBINVIW: get_func7 = 7'b0110100;
+ GORCIW: get_func7 = 7'b0010100;
+ GREVIW: get_func7 = 7'b0110100;
+ CLZW: get_func7 = 7'b0110000;
+ CTZW: get_func7 = 7'b0110000;
+ PCNTW: get_func7 = 7'b0110000;
+ CLMULW: get_func7 = 7'b0000101;
+ CLMULRW: get_func7 = 7'b0000101;
+ CLMULHW: get_func7 = 7'b0000101;
+ SHFLW: get_func7 = 7'b0000100;
+ UNSHFLW: get_func7 = 7'b0000100;
+ BDEPW: get_func7 = 7'b0100100;
+ BEXTW: get_func7 = 7'b0000100;
+ PACKW: get_func7 = 7'b0000100;
+ PACKUW: get_func7 = 7'b0100100;
+ BFPW: get_func7 = 7'b0100100;
+ default: get_func7 = super.get_func7();
+ endcase
+
+ endfunction
+
+ function bit [4:0] get_func5();
+ case (instr_name) inside
+ SLOI: get_func5 = 5'b00100;
+ SROI: get_func5 = 5'b00100;
+ RORI: get_func5 = 5'b01100;
+ SBCLRI: get_func5 = 5'b01001;
+ SBSETI: get_func5 = 5'b01001;
+ SBINVI: get_func5 = 5'b01101;
+ SBEXTI: get_func5 = 5'b01001;
+ GORCI: get_func5 = 5'b00101;
+ GREVI: get_func5 = 5'b01101;
+
+ CLZW: get_func5 = 5'b00000;
+ CTZW: get_func5 = 5'b00001;
+ PCNTW: get_func5 = 5'b00010;
+
+ CRC32_B: get_func5 = 5'b10000;
+ CRC32_H: get_func5 = 5'b10001;
+ CRC32_W: get_func5 = 5'b10010;
+ CRC32C_B: get_func5 = 5'b11000;
+ CRC32C_H: get_func5 = 5'b11001;
+ CRC32C_W: get_func5 = 5'b11010;
+ CRC32_D: get_func5 = 5'b10011;
+ CRC32C_D: get_func5 = 5'b11011;
+
+ CLZ: get_func5 = 5'b00000;
+ CTZ: get_func5 = 5'b00001;
+ PCNT: get_func5 = 5'b00010;
+ BMATFLIP: get_func5 = 5'b00011;
+ SEXT_B: get_func5 = 5'b00100;
+ SEXT_H: get_func5 = 5'b00101;
+ default: `uvm_fatal(`gfn, $sformatf("Unsupported instruction %0s", instr_name.name()))
+ endcase
+ endfunction
+
+ function bit [1:0] get_func2();
+ case (instr_name) inside
+ CMIX: get_func2 = 2'b11;
+ CMOV: get_func2 = 2'b11;
+ FSL: get_func2 = 2'b10;
+ FSR: get_func2 = 2'b10;
+ FSLW: get_func2 = 2'b10;
+ FSRW: get_func2 = 2'b10;
+ FSRIW: get_func2 = 2'b10;
+ default: `uvm_fatal(`gfn, $sformatf("Unsupported instruction %0s", instr_name.name()))
+ endcase
+ endfunction
+
+ // Convert the instruction to assembly code
+ virtual function string convert2bin(string prefix = "");
+ string binary = "";
+ case (format)
+ R_FORMAT: begin
+ if ((category inside {LOGICAL}) && (group == RV32B)) begin
+ if (instr_name inside {SEXT_B, SEXT_H}) begin
+ binary =
+ $sformatf("%8h", {get_func7(), get_func5(), rs1, get_func3(), rd, get_opcode()});
+ end
+ end
+
+ if ((category inside {ARITHMETIC}) && (group == RV32B)) begin
+ if (instr_name inside {CRC32_B, CRC32_H, CRC32_W, CRC32C_B, CRC32C_H, CRC32C_W, CLZ, CTZ,
+ PCNT}) begin
+ binary =
+ $sformatf("%8h", {get_func7(), get_func5(), rs1, get_func3(), rd, get_opcode()});
+ end
+ end
+
+ if ((category inside {ARITHMETIC}) && (group == RV64B)) begin
+ if (instr_name inside {CLZW, CTZW, PCNTW, CRC32_D, CRC32C_D, BMATFLIP}) begin
+ binary =
+ $sformatf("%8h", {get_func7(), get_func5(), rs1, get_func3(), rd, get_opcode()});
+ end
+ end
+ end
+
+ I_FORMAT: begin
+ if ((category inside {SHIFT, LOGICAL}) && (group == RV32B)) begin
+ binary = $sformatf("%8h", {get_func5(), imm[6:0], rs1, get_func3(), rd, get_opcode()});
+ end else if ((category inside {SHIFT, LOGICAL}) && (group == RV64B)) begin
+ binary = $sformatf("%8h", {get_func7(), imm[4:0], rs1, get_func3(), rd, get_opcode()});
+ if (instr_name == SLLIU_W)
+ binary = $sformatf("%8h", {5'b0_0001, imm[6:0], rs1, get_func3(), rd, get_opcode()});
+ end
+
+ if (instr_name inside {FSRI}) begin
+ binary = $sformatf("%8h", {rs3, 1'b1, imm[5:0], rs1, get_func3(), rd, get_opcode()});
+ end
+
+ if ((category inside {ARITHMETIC}) && (group == RV32B)) begin
+ binary = $sformatf("%8h", {6'b00_0010, imm[5:0], rs1, get_func3(), rd, get_opcode()});
+ end
+
+ if ((category inside {ARITHMETIC}) && (group == RV64B)) begin
+ binary = $sformatf("%8h", {imm[11:0], rs1, get_func3(), rd, get_opcode()});
+ end
+ end
+
+ R4_FORMAT: begin
+ binary = $sformatf("%8h", {rs3, get_func2(), rs2, rs1, get_func3(), rd, get_opcode()});
+ end
+ default: begin
+ if (binary == "") binary = super.convert2bin(prefix);
+ end
+ endcase
+ return {prefix, binary};
+ endfunction
+
+ virtual function void do_copy(uvm_object rhs);
+ riscv_b_instr rhs_;
+ super.copy(rhs);
+ assert($cast(rhs_, rhs));
+ this.rs3 = rhs_.rs3;
+ this.has_rs3 = rhs_.has_rs3;
+ endfunction : do_copy
+
+endclass
+
+
+
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/isa/riscv_compressed_instr.sv b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/isa/riscv_compressed_instr.sv
index c91fd7c..760649d 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/isa/riscv_compressed_instr.sv
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/isa/riscv_compressed_instr.sv
@@ -217,6 +217,7 @@
end
CJ_FORMAT:
asm_str = $sformatf("%0s%0s", asm_str, get_imm());
+ default: `uvm_info(`gfn, $sformatf("Unsupported format %0s", format.name()), UVM_LOW)
endcase
end else begin
// For EBREAK,C.EBREAK, making sure pc+4 is a valid instruction boundary
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/isa/riscv_floating_point_instr.sv b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/isa/riscv_floating_point_instr.sv
index 43bf47c..e65c5b1 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/isa/riscv_floating_point_instr.sv
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/isa/riscv_floating_point_instr.sv
@@ -138,6 +138,7 @@
has_fs1 = 1'b0;
has_fd = 1'b0;
end
+ default: `uvm_info(`gfn, $sformatf("Unsupported format %0s", format.name()), UVM_LOW)
endcase
endfunction
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/isa/riscv_instr.sv b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/isa/riscv_instr.sv
index ce56488..0a1b32a 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/isa/riscv_instr.sv
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/isa/riscv_instr.sv
@@ -123,7 +123,9 @@
!(cfg.disable_compressed_instr &&
(instr_inst.group inside {RV32C, RV64C, RV32DC, RV32FC, RV128C})) &&
!(!cfg.enable_floating_point &&
- (instr_inst.group inside {RV32F, RV64F, RV32D, RV64D}))) begin
+ (instr_inst.group inside {RV32F, RV64F, RV32D, RV64D})) &&
+ !(!cfg.enable_b_extension &&
+ (instr_inst.group inside {RV32B, RV64B}))) begin
instr_category[instr_inst.category].push_back(instr_name);
instr_group[instr_inst.group].push_back(instr_name);
instr_names.push_back(instr_name);
@@ -374,6 +376,8 @@
end else begin
asm_str = $sformatf("%0s%0s, %0s, %0s", asm_str, rd.name(), rs1.name(), rs2.name());
end
+ default: `uvm_fatal(`gfn, $sformatf("Unsupported format %0s [%0s]",
+ format.name(), instr_name.name()))
endcase
end else begin
// For EBREAK,C.EBREAK, making sure pc+4 is a valid instruction boundary
@@ -580,6 +584,7 @@
else
binary = $sformatf("%8h", {get_func7(), rs2, rs1, get_func3(), rd, get_opcode()});
end
+ default: `uvm_fatal(`gfn, $sformatf("Unsupported format %0s", format.name()))
endcase
return {prefix, binary};
endfunction
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/isa/riscv_vector_instr.sv b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/isa/riscv_vector_instr.sv
index fe98b3b..def31c9 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/isa/riscv_vector_instr.sv
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/isa/riscv_vector_instr.sv
@@ -103,6 +103,7 @@
VV: asm_str = $sformatf("vmv.v.v %s,%s", vd.name(), vs1.name());
VX: asm_str = $sformatf("vmv.v.x %s,%s", vd.name(), rs1.name());
VI: asm_str = $sformatf("vmv.v.i %s,%s", vd.name(), imm_str);
+ default: `uvm_info(`gfn, $sformatf("Unsupported va_variant %0s", va_variant), UVM_LOW)
endcase
end else if (instr_name == VFMV) begin
asm_str = $sformatf("vfmv.v.f %s,%s", vd.name(), fs1.name());
@@ -156,6 +157,7 @@
end
end
end
+ default: `uvm_info(`gfn, $sformatf("Unsupported format %0s", format.name()), UVM_LOW)
endcase
if(comment != "") begin
asm_str = {asm_str, " #",comment};
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/isa/rv32b_instr.sv b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/isa/rv32b_instr.sv
new file mode 100755
index 0000000..984a1d4
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/isa/rv32b_instr.sv
@@ -0,0 +1,76 @@
+/*
+ * Copyright 2019 Google LLC
+ * Copyright 2019 Mellanox Technologies Ltd
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+// LOGICAL instructions
+`DEFINE_B_INSTR(SEXT_B, R_FORMAT, LOGICAL, RV32B)
+`DEFINE_B_INSTR(SEXT_H, R_FORMAT, LOGICAL, RV32B)
+`DEFINE_B_INSTR(ANDN, R_FORMAT, LOGICAL, RV32B)
+`DEFINE_B_INSTR(ORN , R_FORMAT, LOGICAL, RV32B)
+`DEFINE_B_INSTR(XNOR, R_FORMAT, LOGICAL, RV32B)
+`DEFINE_B_INSTR(GORC, R_FORMAT, LOGICAL, RV32B)
+`DEFINE_B_INSTR(GORCI, I_FORMAT, LOGICAL, RV32B, UIMM)
+`DEFINE_B_INSTR(CMIX, R4_FORMAT, LOGICAL, RV32B)
+`DEFINE_B_INSTR(CMOV, R4_FORMAT, LOGICAL, RV32B)
+`DEFINE_B_INSTR(PACK, R_FORMAT, LOGICAL, RV32B)
+`DEFINE_B_INSTR(PACKU, R_FORMAT, LOGICAL, RV32B)
+`DEFINE_B_INSTR(PACKH, R_FORMAT, LOGICAL, RV32B)
+// SHIFT intructions
+`DEFINE_B_INSTR(SLO, R_FORMAT, SHIFT, RV32B)
+`DEFINE_B_INSTR(SRO, R_FORMAT, SHIFT, RV32B)
+`DEFINE_B_INSTR(ROL, R_FORMAT, SHIFT, RV32B)
+`DEFINE_B_INSTR(ROR, R_FORMAT, SHIFT, RV32B)
+`DEFINE_B_INSTR(SBCLR, R_FORMAT, SHIFT, RV32B)
+`DEFINE_B_INSTR(SBSET, R_FORMAT, SHIFT, RV32B)
+`DEFINE_B_INSTR(SBINV, R_FORMAT, SHIFT, RV32B)
+`DEFINE_B_INSTR(SBEXT, R_FORMAT, SHIFT, RV32B)
+`DEFINE_B_INSTR(GREV, R_FORMAT, SHIFT, RV32B)
+`DEFINE_B_INSTR(GREVI, I_FORMAT, SHIFT, RV32B , UIMM)
+`DEFINE_B_INSTR(SLOI , I_FORMAT, SHIFT, RV32B ,UIMM)
+`DEFINE_B_INSTR(SROI , I_FORMAT, SHIFT, RV32B ,UIMM)
+`DEFINE_B_INSTR(RORI , I_FORMAT, SHIFT, RV32B ,UIMM)
+`DEFINE_B_INSTR(SBCLRI , I_FORMAT, SHIFT, RV32B ,UIMM)
+`DEFINE_B_INSTR(SBSETI , I_FORMAT, SHIFT, RV32B ,UIMM)
+`DEFINE_B_INSTR(SBINVI , I_FORMAT, SHIFT, RV32B ,UIMM)
+`DEFINE_B_INSTR(SBEXTI , I_FORMAT, SHIFT, RV32B ,UIMM)
+`DEFINE_B_INSTR(FSL, R4_FORMAT, SHIFT, RV32B)
+`DEFINE_B_INSTR(FSR, R4_FORMAT, SHIFT, RV32B)
+`DEFINE_B_INSTR(FSRI, I_FORMAT, SHIFT, RV32B ,UIMM)
+// ARITHMETIC intructions
+`DEFINE_B_INSTR(CLZ, R_FORMAT, ARITHMETIC, RV32B)
+`DEFINE_B_INSTR(CTZ, R_FORMAT, ARITHMETIC, RV32B)
+`DEFINE_B_INSTR(PCNT, R_FORMAT, ARITHMETIC, RV32B)
+`DEFINE_B_INSTR(CRC32_B, R_FORMAT, ARITHMETIC, RV32B)
+`DEFINE_B_INSTR(CRC32_H, R_FORMAT, ARITHMETIC, RV32B)
+`DEFINE_B_INSTR(CRC32_W, R_FORMAT, ARITHMETIC, RV32B)
+`DEFINE_B_INSTR(CRC32C_B, R_FORMAT, ARITHMETIC, RV32B)
+`DEFINE_B_INSTR(CRC32C_H, R_FORMAT, ARITHMETIC, RV32B)
+`DEFINE_B_INSTR(CRC32C_W, R_FORMAT, ARITHMETIC, RV32B)
+`DEFINE_B_INSTR(CLMUL, R_FORMAT, ARITHMETIC, RV32B)
+`DEFINE_B_INSTR(CLMULR, R_FORMAT, ARITHMETIC, RV32B)
+`DEFINE_B_INSTR(CLMULH, R_FORMAT, ARITHMETIC, RV32B)
+`DEFINE_B_INSTR(MIN, R_FORMAT, ARITHMETIC, RV32B)
+`DEFINE_B_INSTR(MAX, R_FORMAT, ARITHMETIC, RV32B)
+`DEFINE_B_INSTR(MINU, R_FORMAT, ARITHMETIC, RV32B)
+`DEFINE_B_INSTR(MAXU, R_FORMAT, ARITHMETIC, RV32B)
+`DEFINE_B_INSTR(SHFL, R_FORMAT, ARITHMETIC, RV32B)
+`DEFINE_B_INSTR(UNSHFL, R_FORMAT, ARITHMETIC, RV32B)
+`DEFINE_B_INSTR(BDEP, R_FORMAT, ARITHMETIC, RV32B)
+`DEFINE_B_INSTR(BEXT, R_FORMAT, ARITHMETIC, RV32B)
+`DEFINE_B_INSTR(BFP, R_FORMAT, ARITHMETIC, RV32B)
+`DEFINE_B_INSTR(SHFLI, I_FORMAT, ARITHMETIC, RV32B, UIMM)
+`DEFINE_B_INSTR(UNSHFLI, I_FORMAT, ARITHMETIC, RV32B, UIMM)
+
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/isa/rv64b_instr.sv b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/isa/rv64b_instr.sv
new file mode 100755
index 0000000..9c681c4
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/isa/rv64b_instr.sv
@@ -0,0 +1,68 @@
+/*
+ * Copyright 2019 Google LLC
+ * Copyright 2019 Mellanox Technologies Ltd
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+// ARITHMETIC intructions
+`DEFINE_B_INSTR(BMATOR, R_FORMAT, ARITHMETIC, RV64B)
+`DEFINE_B_INSTR(BMATXOR, R_FORMAT, ARITHMETIC, RV64B)
+`DEFINE_B_INSTR(BMATFLIP, R_FORMAT, ARITHMETIC, RV64B)
+`DEFINE_B_INSTR(CRC32_D, R_FORMAT, ARITHMETIC, RV64B)
+`DEFINE_B_INSTR(CRC32C_D, R_FORMAT, ARITHMETIC, RV64B)
+`DEFINE_B_INSTR(ADDIWU, I_FORMAT, ARITHMETIC, RV64B)
+`DEFINE_B_INSTR(ADDWU, R_FORMAT, ARITHMETIC, RV64B)
+`DEFINE_B_INSTR(SUBWU, R_FORMAT, ARITHMETIC, RV64B)
+`DEFINE_B_INSTR(ADDU_W, R_FORMAT, ARITHMETIC, RV64B)
+`DEFINE_B_INSTR(SUBU_W, R_FORMAT, ARITHMETIC, RV64B)
+`DEFINE_B_INSTR(CLZW, R_FORMAT, ARITHMETIC, RV64B)
+`DEFINE_B_INSTR(CTZW, R_FORMAT, ARITHMETIC, RV64B)
+`DEFINE_B_INSTR(PCNTW, R_FORMAT, ARITHMETIC, RV64B)
+`DEFINE_B_INSTR(CLMULW, R_FORMAT, ARITHMETIC, RV64B)
+`DEFINE_B_INSTR(CLMULRW, R_FORMAT, ARITHMETIC, RV64B)
+`DEFINE_B_INSTR(CLMULHW, R_FORMAT, ARITHMETIC, RV64B)
+`DEFINE_B_INSTR(SHFLW, R_FORMAT, ARITHMETIC, RV64B)
+`DEFINE_B_INSTR(UNSHFLW, R_FORMAT, ARITHMETIC, RV64B)
+`DEFINE_B_INSTR(BDEPW, R_FORMAT, ARITHMETIC, RV64B)
+`DEFINE_B_INSTR(BEXTW, R_FORMAT, ARITHMETIC, RV64B)
+`DEFINE_B_INSTR(BFPW, R_FORMAT, ARITHMETIC, RV64B)
+
+// SHIFT intructions
+`DEFINE_B_INSTR(SLLIU_W, I_FORMAT, SHIFT, RV64B, UIMM)
+`DEFINE_B_INSTR(SLOW, R_FORMAT, SHIFT, RV64B)
+`DEFINE_B_INSTR(SROW, R_FORMAT, SHIFT, RV64B)
+`DEFINE_B_INSTR(ROLW, R_FORMAT, SHIFT, RV64B)
+`DEFINE_B_INSTR(RORW, R_FORMAT, SHIFT, RV64B)
+`DEFINE_B_INSTR(SBCLRW, R_FORMAT, SHIFT, RV64B)
+`DEFINE_B_INSTR(SBSETW, R_FORMAT, SHIFT, RV64B)
+`DEFINE_B_INSTR(SBINVW, R_FORMAT, SHIFT, RV64B)
+`DEFINE_B_INSTR(SBEXTW, R_FORMAT, SHIFT, RV64B)
+`DEFINE_B_INSTR(GREVW, R_FORMAT, SHIFT, RV64B)
+`DEFINE_B_INSTR(SLOIW , I_FORMAT, SHIFT, RV64B, UIMM)
+`DEFINE_B_INSTR(SROIW , I_FORMAT, SHIFT, RV64B, UIMM)
+`DEFINE_B_INSTR(RORIW , I_FORMAT, SHIFT, RV64B, UIMM)
+`DEFINE_B_INSTR(SBCLRIW , I_FORMAT, SHIFT, RV64B, UIMM)
+`DEFINE_B_INSTR(SBSETIW , I_FORMAT, SHIFT, RV64B, UIMM)
+`DEFINE_B_INSTR(SBINVIW , I_FORMAT, SHIFT, RV64B, UIMM)
+`DEFINE_B_INSTR(GREVIW, I_FORMAT, SHIFT, RV64B, UIMM)
+`DEFINE_B_INSTR(FSLW, R4_FORMAT, SHIFT, RV64B)
+`DEFINE_B_INSTR(FSRW, R4_FORMAT, SHIFT, RV64B)
+`DEFINE_B_INSTR(FSRIW, I_FORMAT, SHIFT, RV64B, UIMM)
+
+// LOGICAL instructions
+`DEFINE_B_INSTR(GORCW, R_FORMAT, LOGICAL, RV64B)
+`DEFINE_B_INSTR(GORCIW, I_FORMAT, LOGICAL, RV64B, UIMM)
+`DEFINE_B_INSTR(PACKW, R_FORMAT, LOGICAL, RV64B)
+`DEFINE_B_INSTR(PACKUW, R_FORMAT, LOGICAL, RV64B)
+
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_amo_instr_lib.sv b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_amo_instr_lib.sv
index 8464aa5..4258854 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_amo_instr_lib.sv
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_amo_instr_lib.sv
@@ -19,60 +19,72 @@
rand int unsigned num_amo;
rand int unsigned num_mixed_instr;
- rand int base;
- rand riscv_reg_t rs1_reg;
- rand int unsigned data_page_id;
- rand int max_load_store_offset;
+ rand int offset[];
+ rand riscv_reg_t rs1_reg[];
+ rand int num_of_rs1_reg;
+ int unsigned data_page_id;
+ int unsigned max_offset;
// User can specify a small group of available registers to generate various hazard condition
rand riscv_reg_t avail_regs[];
- `uvm_object_utils(riscv_amo_base_instr_stream)
+ constraint num_of_rs1_reg_c {
+ num_of_rs1_reg == 1;
+ }
constraint rs1_c {
- !(rs1_reg inside {cfg.reserved_regs, reserved_rd, ZERO});
+ solve num_of_rs1_reg before rs1_reg;
+ rs1_reg.size() == num_of_rs1_reg;
+ offset.size() == num_of_rs1_reg;
+ foreach (rs1_reg[i]) {
+ !(rs1_reg[i] inside {cfg.reserved_regs, reserved_rd, ZERO});
+ }
+ unique {rs1_reg};
}
constraint addr_range_c {
- data_page_id < max_data_page_id;
- base inside {[0 : max_load_store_offset-1]};
- }
-
- constraint aligned_amo_c {
- if (XLEN == 32) {
- base % 4 == 0;
- } else {
- base % 8 == 0;
+ foreach (offset[i]) {
+ offset[i] inside {[0 : max_offset - 1]};
}
}
- function new(string name = "");
- super.new(name);
- endfunction
+ constraint aligned_amo_c {
+ foreach (offset[i]) {
+ if (XLEN == 32) {
+ offset[i] % 4 == 0;
+ } else {
+ offset[i] % 8 == 0;
+ }
+ }
+ }
+
+ `uvm_object_utils(riscv_amo_base_instr_stream)
+ `uvm_object_new
function void pre_randomize();
data_page = cfg.amo_region;
max_data_page_id = data_page.size();
+ data_page_id = $urandom_range(0, max_data_page_id - 1);
+ max_offset = data_page[data_page_id].size_in_bytes;
endfunction
- // Use "la" instruction to initialize the base regiseter
- virtual function void add_rs1_init_la_instr(riscv_reg_t gpr, int id, int base = 0);
- riscv_pseudo_instr la_instr;
- la_instr = riscv_pseudo_instr::type_id::create("la_instr");
- la_instr.pseudo_instr_name = LA;
- la_instr.rd = gpr;
- la_instr.imm_str = $sformatf("%0s+%0d", cfg.amo_region[id].name, base);
- instr_list.push_front(la_instr);
+ // Use "la" instruction to initialize the offset regiseter
+ virtual function void init_offset_reg();
+ foreach (rs1_reg[i]) begin
+ riscv_pseudo_instr la_instr;
+ la_instr = riscv_pseudo_instr::type_id::create("la_instr");
+ la_instr.pseudo_instr_name = LA;
+ la_instr.rd = rs1_reg[i];
+ la_instr.imm_str = $sformatf("%0s+%0d", cfg.amo_region[data_page_id].name, offset[i]);
+ instr_list.push_front(la_instr);
+ end
endfunction
function void post_randomize();
gen_amo_instr();
- // rs1 cannot be modified by other instructions
- if(!(rs1_reg inside {reserved_rd})) begin
- reserved_rd = {reserved_rd, rs1_reg};
- end
+ reserved_rd = {reserved_rd, rs1_reg};
add_mixed_instr(num_mixed_instr);
- add_rs1_init_la_instr(rs1_reg, data_page_id);
+ init_offset_reg();
super.post_randomize();
endfunction
@@ -113,24 +125,24 @@
lr_instr = riscv_instr::get_rand_instr(.include_instr({allowed_lr_instr}));
sc_instr = riscv_instr::get_rand_instr(.include_instr({allowed_sc_instr}));
`DV_CHECK_RANDOMIZE_WITH_FATAL(lr_instr,
- rs1 == rs1_reg;
+ rs1 == rs1_reg[0];
if (reserved_rd.size() > 0) {
!(rd inside {reserved_rd});
}
if (cfg.reserved_regs.size() > 0) {
!(rd inside {cfg.reserved_regs});
}
- rd != rs1_reg;
+ rd != rs1_reg[0];
)
`DV_CHECK_RANDOMIZE_WITH_FATAL(sc_instr,
- rs1 == rs1_reg;
+ rs1 == rs1_reg[0];
if (reserved_rd.size() > 0) {
!(rd inside {reserved_rd});
}
if (cfg.reserved_regs.size() > 0) {
!(rd inside {cfg.reserved_regs});
}
- rd != rs1_reg;
+ rd != rs1_reg[0];
)
instr_list.push_back(lr_instr);
instr_list.push_back(sc_instr);
@@ -144,8 +156,14 @@
constraint reasonable_c {
solve num_amo before num_mixed_instr;
- num_amo inside {[1:10]};
- num_mixed_instr inside {[0:2*num_amo]};
+ num_amo inside {[1 : 10]};
+ num_mixed_instr inside {[0 : num_amo]};
+ }
+
+ constraint num_of_rs1_reg_c {
+ solve num_amo before num_of_rs1_reg;
+ num_of_rs1_reg inside {[1 : num_amo]};
+ num_of_rs1_reg < 5;
}
`uvm_object_utils(riscv_amo_instr_stream)
@@ -162,8 +180,8 @@
if (cfg.reserved_regs.size() > 0) {
!(rd inside {cfg.reserved_regs});
}
- rs1 == rs1_reg;
- rd != rs1_reg;
+ rs1 inside {rs1_reg};
+ !(rd inside {rs1_reg});
)
instr_list.push_front(amo_instr[i]);
end
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_asm_program_gen.sv b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_asm_program_gen.sv
index ae18ede..f664be4 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_asm_program_gen.sv
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_asm_program_gen.sv
@@ -106,7 +106,8 @@
`DV_CHECK_RANDOMIZE_FATAL(main_program[hart])
main_program[hart].gen_instr(.is_main_program(1), .no_branch(cfg.no_branch_jump));
// Setup jump instruction among main program and sub programs
- gen_callstack(main_program[hart], sub_program[hart], sub_program_name, cfg.num_of_sub_program);
+ gen_callstack(main_program[hart], sub_program[hart], sub_program_name,
+ cfg.num_of_sub_program);
`uvm_info(`gfn, "Generating callstack...done", UVM_LOW)
main_program[hart].post_process_instr();
`uvm_info(`gfn, "Post-processing main program...done", UVM_LOW)
@@ -128,8 +129,10 @@
// Program end
gen_program_end(hart);
if (!cfg.bare_program_mode) begin
- // Privileged mode switch routine
- gen_privileged_mode_switch_routine(hart);
+ if (!riscv_instr_pkg::support_pmp) begin
+ // Privileged mode switch routine
+ gen_privileged_mode_switch_routine(hart);
+ end
// Generate debug rom section
if (riscv_instr_pkg::support_debug_mode) begin
gen_debug_rom(hart);
@@ -165,7 +168,12 @@
// Generate kernel program/data/stack sections
//---------------------------------------------------------------------------------------
virtual function void gen_kernel_sections(int hart);
- instr_stream.push_back(get_label("kernel_instr_start: .align 12", hart));
+ if (SATP_MODE != BARE) begin
+ instr_stream.push_back(".align 12");
+ end else begin
+ instr_stream.push_back(".align 2");
+ end
+ instr_stream.push_back(get_label("kernel_instr_start:", hart));
instr_stream.push_back(".text");
// Kernel programs
if (cfg.virtual_addr_translation_on) begin
@@ -189,8 +197,13 @@
// User stack and data pages may not be accessible when executing trap handling programs in
// machine/supervisor mode. Generate separate kernel data/stack sections to solve it.
if (cfg.virtual_addr_translation_on) begin
+ if (SATP_MODE != BARE) begin
+ instr_stream.push_back(".align 12");
+ end else begin
+ instr_stream.push_back(".align 2");
+ end
// Kernel data pages
- instr_stream.push_back(get_label("kernel_data_start: .align 12", hart));
+ instr_stream.push_back(get_label("kernel_data_start:", hart));
if(!cfg.no_data_page) begin
// Data section
gen_data_page(hart, 1'b1);
@@ -347,8 +360,15 @@
if (cfg.use_push_data_section) begin
instr_stream.push_back($sformatf(".pushsection .%0suser_stack,\"aw\",@progbits;",
hart_prefix(hart)));
+ end else begin
+ instr_stream.push_back($sformatf(".section .%0suser_stack,\"aw\",@progbits;",
+ hart_prefix(hart)));
end
- instr_stream.push_back(".align 12");
+ if (SATP_MODE != BARE) begin
+ instr_stream.push_back(".align 12");
+ end else begin
+ instr_stream.push_back(".align 2");
+ end
instr_stream.push_back(get_label("user_stack_start:", hart));
instr_stream.push_back($sformatf(".rept %0d", cfg.stack_len - 1));
instr_stream.push_back($sformatf(".%0dbyte 0x0", XLEN/8));
@@ -365,8 +385,15 @@
if (cfg.use_push_data_section) begin
instr_stream.push_back($sformatf(".pushsection .%0skernel_stack,\"aw\",@progbits;",
hart_prefix(hart)));
+ end else begin
+ instr_stream.push_back($sformatf(".section .%0skernel_stack,\"aw\",@progbits;",
+ hart_prefix(hart)));
end
- instr_stream.push_back(".align 12");
+ if (SATP_MODE != BARE) begin
+ instr_stream.push_back(".align 12");
+ end else begin
+ instr_stream.push_back(".align 2");
+ end
instr_stream.push_back(get_label("kernel_stack_start:", hart));
instr_stream.push_back($sformatf(".rept %0d", cfg.kernel_stack_len - 1));
instr_stream.push_back($sformatf(".%0dbyte 0x0", XLEN/8));
@@ -386,10 +413,6 @@
// Init stack pointer to point to the end of the user stack
str = {indent, $sformatf("la x%0d, %0suser_stack_end", cfg.sp, hart_prefix(hart))};
instr_stream.push_back(str);
- if (support_pmp) begin
- str = {indent, "j main"};
- instr_stream.push_back(str);
- end
if (cfg.enable_floating_point) begin
init_floating_point_gpr();
end
@@ -398,6 +421,10 @@
end
core_is_initialized();
gen_dummy_csr_write(); // TODO add a way to disable xStatus read
+ if (support_pmp) begin
+ str = {indent, "j main"};
+ instr_stream.push_back(str);
+ end
endfunction
// Setup MISA based on supported extensions
@@ -414,6 +441,7 @@
RV32I, RV64I, RV128I : misa[MISA_EXT_I] = 1'b1;
RV32M, RV64M : misa[MISA_EXT_M] = 1'b1;
RV32A, RV64A : misa[MISA_EXT_A] = 1'b1;
+ RV32B, RV64B : misa[MISA_EXT_B] = 1'b1;
RV32F, RV64F, RV32FC : misa[MISA_EXT_F] = 1'b1;
RV32D, RV64D, RV32DC : misa[MISA_EXT_D] = 1'b1;
RV32V, RV64V : misa[MISA_EXT_V] = 1'b1;
@@ -591,6 +619,12 @@
end
// Setup mepc register, jump to init entry
setup_epc(hart);
+ // Move privileged mode support to the "safe" section of the program
+ // if PMP is supported
+ if (riscv_instr_pkg::support_pmp) begin
+ // Privileged mode switch routine
+ gen_privileged_mode_switch_routine(hart);
+ end
endfunction
virtual function void gen_privileged_mode_switch_routine(int hart);
@@ -623,6 +657,8 @@
.csr(USTATUS));
gen_signature_handshake(.instr(csr_handshake), .signature_type(WRITE_CSR), .csr(UIE));
end
+ default: `uvm_info(`gfn, $sformatf("Unsupported privileged_mode %0s",
+ riscv_instr_pkg::supported_privileged_mode[i]), UVM_LOW)
endcase
// Write M-mode CSRs to testbench by default, as these should be implemented
gen_signature_handshake(.instr(csr_handshake), .signature_type(WRITE_CSR), .csr(MSTATUS));
@@ -636,7 +672,7 @@
// Setup EPC before entering target privileged mode
virtual function void setup_epc(int hart);
- string instr[];
+ string instr[$];
string mode_name;
instr = {$sformatf("la x%0d, %0sinit", cfg.gpr[0], hart_prefix(hart))};
if(cfg.virtual_addr_translation_on) begin
@@ -648,10 +684,10 @@
$sformatf("srli x%0d, x%0d, %0d", cfg.gpr[0], cfg.gpr[0], XLEN - 12)};
end
mode_name = cfg.init_privileged_mode.name();
- instr = {instr,
- $sformatf("csrw mepc, x%0d", cfg.gpr[0]),
- $sformatf("j %0sinit_%0s", hart_prefix(hart), mode_name.tolower())
- };
+ instr.push_back($sformatf("csrw mepc, x%0d", cfg.gpr[0]));
+ if (!riscv_instr_pkg::support_pmp) begin
+ instr.push_back($sformatf("j %0sinit_%0s", hart_prefix(hart), mode_name.tolower()));
+ end
gen_section(get_label("mepc_setup", hart), instr);
endfunction
@@ -723,6 +759,8 @@
MACHINE_MODE: trap_vec_reg = MTVEC;
SUPERVISOR_MODE: trap_vec_reg = STVEC;
USER_MODE: trap_vec_reg = UTVEC;
+ default: `uvm_info(`gfn, $sformatf("Unsupported privileged_mode %0s",
+ riscv_instr_pkg::supported_privileged_mode[i]), UVM_LOW)
endcase
// Skip utvec init if trap delegation to u_mode is not supported
if ((riscv_instr_pkg::supported_privileged_mode[i] == USER_MODE) &&
@@ -796,6 +834,8 @@
gen_trap_handler_section(hart, "u", UCAUSE, UTVEC, UTVAL,
UEPC, USCRATCH, USTATUS, UIE, UIP);
end
+ default: `uvm_fatal(`gfn, $sformatf("Unsupported privileged_mode %0s",
+ riscv_instr_pkg::supported_privileged_mode[i]))
endcase
end
endfunction
@@ -834,7 +874,11 @@
end
// The trap handler will occupy one 4KB page, it will be allocated one entry in the page table
// with a specific privileged mode.
- instr_stream.push_back(".align 12");
+ if (SATP_MODE != BARE) begin
+ instr_stream.push_back(".align 12");
+ end else begin
+ instr_stream.push_back($sformatf(".align %d", cfg.tvec_alignment));
+ end
tvec_name = tvec.name();
gen_section(get_label($sformatf("%0s_handler", tvec_name.tolower()), hart), instr);
// Exception handler
@@ -1059,6 +1103,9 @@
if (cfg.use_push_data_section) begin
instr_stream.push_back($sformatf(".pushsection .%0spage_table,\"aw\",@progbits;",
hart_prefix(hart)));
+ end else begin
+ instr_stream.push_back($sformatf(".section .%0spage_table,\"aw\",@progbits;",
+ hart_prefix(hart)));
end
foreach(page_table_list.page_table[i]) begin
page_table_list.page_table[i].gen_page_table_section(page_table_section);
@@ -1129,6 +1176,7 @@
USTATUS: begin
interrupt_handler_instr.push_back($sformatf("csrsi 0x%0x, 0x%0x", status, 1));
end
+ default: `uvm_fatal(`gfn, $sformatf("Unsupported status %0s", status))
endcase
interrupt_handler_instr.push_back($sformatf("1: csrwi 0x%0x,0", scratch));
end
@@ -1150,8 +1198,12 @@
interrupt_handler_instr = {interrupt_handler_instr,
$sformatf("%0sret;", mode_prefix)
};
- // The interrupt handler will use one 4KB page
- instr_stream.push_back(".align 12");
+ if (SATP_MODE != BARE) begin
+ // The interrupt handler will use one 4KB page
+ instr_stream.push_back(".align 12");
+ end else begin
+ instr_stream.push_back(".align 2");
+ end
gen_section(get_label($sformatf("%0smode_intr_handler", mode_prefix), hart),
interrupt_handler_instr);
endfunction
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_data_page_gen.sv b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_data_page_gen.sv
index e79d8cc..5ed9017 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_data_page_gen.sv
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_data_page_gen.sv
@@ -75,12 +75,18 @@
if (cfg.use_push_data_section) begin
data_page_str.push_back($sformatf(".pushsection .%0s,\"aw\",@progbits;",
mem_region_setting[i].name));
+ end else begin
+ data_page_str.push_back($sformatf(".section .%0s,\"aw\",@progbits;",
+ mem_region_setting[i].name));
end
data_page_str.push_back($sformatf("%0s:", mem_region_setting[i].name));
end else begin
if (cfg.use_push_data_section) begin
data_page_str.push_back($sformatf(".pushsection .%0s,\"aw\",@progbits;",
{hart_prefix(hart_id), mem_region_setting[i].name}));
+ end else begin
+ data_page_str.push_back($sformatf(".section .%0s,\"aw\",@progbits;",
+ {hart_prefix(hart_id), mem_region_setting[i].name}));
end
data_page_str.push_back($sformatf("%0s:",
{hart_prefix(hart_id), mem_region_setting[i].name}));
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_defines.svh b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_defines.svh
index e423f76..ac46845 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_defines.svh
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_defines.svh
@@ -90,7 +90,7 @@
`INSTR_BODY(instr_n, instr_format, instr_category, instr_group, imm_tp)
// Vector arithmetic instruction
-`define DEFINE_VA_INSTR(instr_n, instr_format, instr_category, instr_group, vav = {}, imm_tp = IMM) \
+`define DEFINE_VA_INSTR(instr_n, instr_format, instr_category, instr_group, vav = {}, imm_tp = IMM)\
class riscv_``instr_n``_instr extends riscv_vector_instr; \
`VA_INSTR_BODY(instr_n, instr_format, instr_category, instr_group, vav, imm_tp)
@@ -98,3 +98,9 @@
`define DEFINE_CUSTOM_INSTR(instr_n, instr_format, instr_category, instr_group, imm_tp = IMM) \
class riscv_``instr_n``_instr extends riscv_custom_instr; \
`INSTR_BODY(instr_n, instr_format, instr_category, instr_group, imm_tp)
+
+//B-extension instruction
+`define DEFINE_B_INSTR(instr_n, instr_format, instr_category, instr_group, imm_tp = IMM) \
+ class riscv_``instr_n``_instr extends riscv_b_instr; \
+ `INSTR_BODY(instr_n, instr_format, instr_category, instr_group, imm_tp)
+
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_directed_instr_lib.sv b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_directed_instr_lib.sv
index 64984ff..3dfba5d 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_directed_instr_lib.sv
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_directed_instr_lib.sv
@@ -44,13 +44,16 @@
class riscv_mem_access_stream extends riscv_directed_instr_stream;
int max_data_page_id;
+ bit load_store_shared_memory;
mem_region_t data_page[$];
`uvm_object_utils(riscv_mem_access_stream)
`uvm_object_new
function void pre_randomize();
- if(kernel_mode) begin
+ if (load_store_shared_memory) begin
+ data_page = cfg.amo_region;
+ end else if(kernel_mode) begin
data_page = cfg.s_mem_region;
end else begin
data_page = cfg.mem_region;
@@ -64,11 +67,14 @@
la_instr = riscv_pseudo_instr::type_id::create("la_instr");
la_instr.pseudo_instr_name = LA;
la_instr.rd = gpr;
- if(kernel_mode) begin
- la_instr.imm_str = $sformatf("%0s%s+%0d",
+ if (load_store_shared_memory) begin
+ la_instr.imm_str = $sformatf("%0s+%0d", cfg.amo_region[id].name, base);
+
+ end else if(kernel_mode) begin
+ la_instr.imm_str = $sformatf("%0s%0s+%0d",
hart_prefix(hart), cfg.s_mem_region[id].name, base);
end else begin
- la_instr.imm_str = $sformatf("%0s%s+%0d",
+ la_instr.imm_str = $sformatf("%0s%0s+%0d",
hart_prefix(hart), cfg.mem_region[id].name, base);
end
instr_list.push_front(la_instr);
@@ -187,8 +193,7 @@
end
jump.has_label = 1'b1;
jump.label = "1";
- jump.comment = $sformatf("%s jump %0s -> %0s",
- hart_prefix(hart), label, target_program_label);
+ jump.comment = $sformatf("jump %0s -> %0s", label, target_program_label);
branch.imm_str = "1f";
branch.comment = "branch to jump instr";
branch.branch_assigned = 1'b1;
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_illegal_instr.sv b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_illegal_instr.sv
index fe5be8c..e06a622 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_illegal_instr.sv
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_illegal_instr.sv
@@ -165,6 +165,14 @@
c_op != 2'b11;
}
+ // Avoid generating illegal func3/func7 errors for opcode used by B-extension
+ constraint b_extension_c {
+ if (RV32B inside {supported_isa}) {
+ if (exception inside {kIllegalFunc3, kIllegalFunc7}) {
+ !(opcode inside {7'b0011011, 7'b0010011, 7'b0111011});
+ }
+ }
+ }
constraint illegal_compressed_op_c {
if (exception == kIllegalCompressedOpcode) {
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_instr_cov_item.sv b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_instr_cov_item.sv
index 703a966..abcab92 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_instr_cov_item.sv
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_instr_cov_item.sv
@@ -23,8 +23,13 @@
rand bit [XLEN-1:0] rs1_value;
rand bit [XLEN-1:0] rs2_value;
rand bit [XLEN-1:0] rd_value;
+ rand riscv_fpr_t fs1;
+ rand riscv_fpr_t fs2;
+ rand riscv_fpr_t fs3;
+ rand riscv_fpr_t fd;
rand bit [XLEN-1:0] fs1_value;
rand bit [XLEN-1:0] fs2_value;
+ rand bit [XLEN-1:0] fs3_value;
rand bit [XLEN-1:0] fd_value;
bit [31:0] binary;
bit [XLEN-1:0] pc;
@@ -37,8 +42,12 @@
div_result_e div_result;
operand_sign_e rs1_sign;
operand_sign_e rs2_sign;
+ operand_sign_e fs1_sign;
+ operand_sign_e fs2_sign;
+ operand_sign_e fs3_sign;
operand_sign_e imm_sign;
operand_sign_e rd_sign;
+ operand_sign_e fd_sign;
hazard_e gpr_hazard;
hazard_e lsu_hazard;
special_val_e rs1_special_val;
@@ -59,6 +68,10 @@
rs1_sign = get_operand_sign(rs1_value);
rs2_sign = get_operand_sign(rs2_value);
rd_sign = get_operand_sign(rd_value);
+ fs1_sign = get_operand_sign(fs1_value);
+ fs2_sign = get_operand_sign(fs2_value);
+ fs3_sign = get_operand_sign(fs2_value);
+ fd_sign = get_operand_sign(fd_value);
imm_sign = get_imm_sign(imm);
rs1_special_val = get_operand_special_val(rs1_value);
rd_special_val = get_operand_special_val(rd_value);
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_instr_cover_group.sv b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_instr_cover_group.sv
index 72fef81..b0db34e 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_instr_cover_group.sv
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_instr_cover_group.sv
@@ -216,6 +216,47 @@
`INSTR_CG_BEGIN(INSTR_NAME) \
cp_imm_sign : coverpoint instr.imm_sign;
+// TODO, will handle special value later
+// single-precision floating point special values coverpoint
+`define FP_SPECIAL_VALUES_CP(VAR, NAME) \
+ cp_fp_special_values_on_``NAME`` : coverpoint VAR { \
+ bins infinity[] = {32'h7f80_0000, 32'hff80_0000}; \
+ bins largest[] = {32'h7f7f_ffff, 32'hff7f_ffff}; \
+ bins zeros[] = {32'h0000_0000, 32'h1000_0000}; \
+ bins NaN[] = {32'h7fc0_0000, 32'h7f80_0000}; \
+ }
+
+`define FP_R_INSTR_CG_BEGIN(INSTR_NAME) \
+ `INSTR_CG_BEGIN(INSTR_NAME) \
+ cp_fs1 : coverpoint instr.fs1; \
+ cp_fs2 : coverpoint instr.fs2; \
+ cp_fd : coverpoint instr.fd; \
+ cp_fs1_sign : coverpoint instr.fs1_sign; \
+ cp_fs2_sign : coverpoint instr.fs2_sign; \
+ cp_fd_sign : coverpoint instr.fd_sign; \
+ `DV(cp_gpr_hazard : coverpoint instr.gpr_hazard;) \
+
+`define FP_R4_INSTR_CG_BEGIN(INSTR_NAME) \
+ `INSTR_CG_BEGIN(INSTR_NAME) \
+ cp_fs1 : coverpoint instr.fs1; \
+ cp_fs2 : coverpoint instr.fs2; \
+ cp_fs3 : coverpoint instr.fs3; \
+ cp_fd : coverpoint instr.fd; \
+ cp_fs1_sign : coverpoint instr.fs1_sign; \
+ cp_fs2_sign : coverpoint instr.fs2_sign; \
+ cp_fs3_sign : coverpoint instr.fs3_sign; \
+ cp_fd_sign : coverpoint instr.fd_sign; \
+ cp_sign_cross: cross cp_fs1_sign, cp_fs2_sign, cp_fs3_sign, cp_fd_sign; \
+ `DV(cp_gpr_hazard : coverpoint instr.gpr_hazard;) \
+
+`define FSQRT_INSTR_CG_BEGIN(INSTR_NAME) \
+ `INSTR_CG_BEGIN(INSTR_NAME) \
+ cp_fs1 : coverpoint instr.fs1; \
+ cp_fd : coverpoint instr.fd; \
+ cp_fs1_sign : coverpoint instr.fs1_sign; \
+ cp_fd_sign : coverpoint instr.fd_sign; \
+ `DV(cp_gpr_hazard : coverpoint instr.gpr_hazard;) \
+
`define CG_END endgroup
`define CG_SELECTOR_BEGIN(CG_ISA) \
@@ -446,6 +487,73 @@
cp_ras : cross cp_rs1_link, cp_rd_link;
`CG_END
+ // floating instructions
+ `INSTR_CG_BEGIN(flw)
+ cp_rs1 : coverpoint instr.rs1 {
+ `DV(ignore_bins zero = {ZERO};)
+ }
+ cp_fd : coverpoint instr.fd;
+ cp_imm_sign : coverpoint instr.imm_sign;
+ `DV(cp_gpr_hazard : coverpoint instr.gpr_hazard;)
+ `DV(cp_lsu_hazard : coverpoint instr.lsu_hazard {
+ bins valid_hazard[] = {NO_HAZARD, RAW_HAZARD};
+ })
+ `CG_END
+
+ `INSTR_CG_BEGIN(fsw)
+ cp_rs1 : coverpoint instr.rs1 {
+ `DV(ignore_bins zero = {ZERO};)
+ }
+ cp_fs2 : coverpoint instr.fs2;
+ cp_imm_sign : coverpoint instr.imm_sign;
+ `DV(cp_gpr_hazard : coverpoint instr.gpr_hazard {
+ bins valid_hazard[] = {NO_HAZARD, RAW_HAZARD};
+ })
+ `DV(cp_lsu_hazard : coverpoint instr.lsu_hazard {
+ bins valid_hazard[] = {NO_HAZARD, WAR_HAZARD, WAW_HAZARD};
+ })
+ `CG_END
+
+ `FP_R_INSTR_CG_BEGIN(fadd_s)
+ cp_sign_cross: cross cp_fs1_sign, cp_fs2_sign, cp_fd_sign;
+ `CG_END
+
+ `FP_R_INSTR_CG_BEGIN(fsub_s)
+ cp_sign_cross: cross cp_fs1_sign, cp_fs2_sign, cp_fd_sign;
+ `CG_END
+
+ `FP_R_INSTR_CG_BEGIN(fmul_s)
+ cp_sign_cross: cross cp_fs1_sign, cp_fs2_sign;
+ `CG_END
+
+ `FP_R_INSTR_CG_BEGIN(fdiv_s)
+ cp_div_result: coverpoint instr.div_result;
+ cp_sign_cross: cross cp_fs1_sign, cp_fs2_sign;
+ `CG_END
+
+ `FSQRT_INSTR_CG_BEGIN(fsqrt_s)
+ `CG_END
+
+ `FP_R_INSTR_CG_BEGIN(fmin_s)
+ cp_sign_cross: cross cp_fs1_sign, cp_fs2_sign;
+ `CG_END
+
+ `FP_R_INSTR_CG_BEGIN(fmax_s)
+ cp_sign_cross: cross cp_fs1_sign, cp_fs2_sign;
+ `CG_END
+
+ `FP_R4_INSTR_CG_BEGIN(fmadd_s)
+ `CG_END
+
+ `FP_R4_INSTR_CG_BEGIN(fnmadd_s)
+ `CG_END
+
+ `FP_R4_INSTR_CG_BEGIN(fmsub_s)
+ `CG_END
+
+ `FP_R4_INSTR_CG_BEGIN(fnmsub_s)
+ `CG_END
+
// CSR instructions
`CSR_INSTR_CG_BEGIN(csrrw)
cp_rs1 : coverpoint instr.rs1;
@@ -901,6 +1009,13 @@
cp_mpp : coverpoint val[12:11];
endgroup
+ covergroup fcsr_cg with function sample(bit [XLEN-1:0] val);
+ cp_fflags : coverpoint val[4:0];
+ cp_frm : coverpoint val[7:5] {
+ ignore_bins invalid = {3'b101, 3'b110};
+ }
+ endgroup
+
`VECTOR_INCLUDE("riscv_instr_cover_group_inc_cg_add.sv")
function new(riscv_instr_gen_config cfg);
@@ -1089,6 +1204,22 @@
c_addw_cg = new();
`CG_SELECTOR_END
+ `CG_SELECTOR_BEGIN(RV32F)
+ flw_cg = new();
+ fsw_cg = new();
+ fadd_s_cg = new();
+ fsub_s_cg = new();
+ fmul_s_cg = new();
+ fdiv_s_cg = new();
+ fsqrt_s_cg = new();
+ fmin_s_cg = new();
+ fmax_s_cg = new();
+ fmadd_s_cg = new();
+ fnmadd_s_cg = new();
+ fmsub_s_cg = new();
+ fnmsub_s_cg = new();
+ `CG_SELECTOR_END
+
// Ignore the exception which cannot be covered when running with ISS
if (iss_mode) begin
int i;
@@ -1111,6 +1242,7 @@
mcause_exception_cg = new();
mcause_interrupt_cg = new();
mstatus_m_cg = new();
+ fcsr_cg = new();
end
if (!cfg.disable_compressed_instr) begin
mepc_alignment_cg = new();
@@ -1242,6 +1374,19 @@
C_SUBW : `SAMPLE(c_subw_cg, instr)
C_ADDW : `SAMPLE(c_addw_cg, instr)
C_ADDIW : `SAMPLE(c_addiw_cg, instr)
+ FLW : `SAMPLE(flw_cg, instr)
+ FSW : `SAMPLE(fsw_cg, instr)
+ FADD_S : `SAMPLE(fadd_s_cg, instr)
+ FSUB_S : `SAMPLE(fsub_s_cg, instr)
+ FMUL_S : `SAMPLE(fmul_s_cg, instr)
+ FDIV_S : `SAMPLE(fdiv_s_cg, instr)
+ FSQRT_S : `SAMPLE(fsqrt_s_cg, instr)
+ FMIN_S : `SAMPLE(fmin_s_cg, instr)
+ FMAX_S : `SAMPLE(fmax_s_cg, instr)
+ FMADD_S : `SAMPLE(fmadd_s_cg, instr)
+ FNMADD_S : `SAMPLE(fnmadd_s_cg, instr)
+ FMSUB_S : `SAMPLE(fmsub_s_cg, instr)
+ FNMSUB_S : `SAMPLE(fnmsub_s_cg, instr)
`VECTOR_INCLUDE("riscv_instr_cover_group_inc_cg_sample.sv")
default: begin
if (instr.group == RV32I) begin
@@ -1280,6 +1425,9 @@
MSTATUS: begin
`SAMPLE(mstatus_m_cg, instr.rd_value);
end
+ FCSR: begin
+ `SAMPLE(fcsr_cg, instr.rd_value);
+ end
endcase
end
if (instr_cnt > 1) begin
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_instr_gen_config.sv b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_instr_gen_config.sv
index 907fbc0..dc921ef 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_instr_gen_config.sv
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_instr_gen_config.sv
@@ -63,6 +63,11 @@
rand bit [1:0] mstatus_vs;
rand mtvec_mode_t mtvec_mode;
+ // TVEC alignment
+ // This value is the log_2 of the byte-alignment of TVEC.BASE field
+ // As per RISC-V privileged spec, default will be set to 2 (4-byte aligned)
+ int tvec_alignment = 2;
+
// Floating point rounding mode
rand f_rounding_mode_t fcsr_rm;
@@ -197,7 +202,7 @@
bit disable_compressed_instr;
// "Memory mapped" address that when written to will indicate some event to
// the testbench - testbench will take action based on the value written
- int signature_addr = 32'hdead_beef;
+ bit [XLEN - 1 : 0] signature_addr = 32'hdead_beef;
bit require_signature_addr = 1'b0;
// Enable a full or empty debug_rom section.
// Full debug_rom will contain random instruction streams.
@@ -232,6 +237,8 @@
bit enable_floating_point;
// Vector extension support
bit enable_vector_extension;
+ // Bit manipulation extension support
+ bit enable_b_extension;
//-----------------------------------------------------------------------------
// Command line options for instruction distribution control
@@ -396,7 +403,7 @@
constraint addr_translaction_rnd_order_c {
solve init_privileged_mode before virtual_addr_translation_on;
}
-
+
constraint addr_translaction_c {
if ((init_privileged_mode != MACHINE_MODE) && (SATP_MODE != BARE)) {
virtual_addr_translation_on == 1'b1;
@@ -431,6 +438,7 @@
`uvm_field_enum(riscv_reg_t, ra, UVM_DEFAULT)
`uvm_field_enum(riscv_reg_t, sp, UVM_DEFAULT)
`uvm_field_enum(riscv_reg_t, tp, UVM_DEFAULT)
+ `uvm_field_int(tvec_alignment, UVM_DEFAULT)
`uvm_field_int(no_data_page, UVM_DEFAULT)
`uvm_field_int(no_branch_jump, UVM_DEFAULT)
`uvm_field_int(no_load_store, UVM_DEFAULT)
@@ -474,6 +482,7 @@
`uvm_field_int(max_directed_instr_stream_seq, UVM_DEFAULT)
`uvm_field_int(enable_floating_point, UVM_DEFAULT)
`uvm_field_int(enable_vector_extension, UVM_DEFAULT)
+ `uvm_field_int(enable_b_extension, UVM_DEFAULT)
`uvm_field_int(use_push_data_section, UVM_DEFAULT)
`uvm_object_utils_end
@@ -489,6 +498,7 @@
get_bool_arg_value("+enable_timer_irq=", enable_timer_irq);
get_int_arg_value("+num_of_sub_program=", num_of_sub_program);
get_int_arg_value("+instr_cnt=", instr_cnt);
+ get_int_arg_value("+tvec_alignment=", tvec_alignment);
get_bool_arg_value("+no_ebreak=", no_ebreak);
get_bool_arg_value("+no_dret=", no_dret);
get_bool_arg_value("+no_wfi=", no_wfi);
@@ -527,6 +537,7 @@
get_bool_arg_value("+set_mstatus_tw=", set_mstatus_tw);
get_bool_arg_value("+enable_floating_point=", enable_floating_point);
get_bool_arg_value("+enable_vector_extension=", enable_vector_extension);
+ get_bool_arg_value("+enable_b_extension=", enable_b_extension);
if(inst.get_arg_value("+boot_mode=", boot_mode_opts)) begin
`uvm_info(get_full_name(), $sformatf(
"Got boot mode option - %0s", boot_mode_opts), UVM_LOW)
@@ -566,6 +577,7 @@
vector_cfg = riscv_vector_cfg::type_id::create("vector_cfg");
pmp_cfg = riscv_pmp_cfg::type_id::create("pmp_cfg");
pmp_cfg.rand_mode(pmp_cfg.pmp_randomize);
+ pmp_cfg.initialize(require_signature_addr);
setup_instr_distribution();
get_invalid_priv_lvl_csr();
endfunction
@@ -642,7 +654,8 @@
bit support_64b;
bit support_128b;
foreach (riscv_instr_pkg::supported_isa[i]) begin
- if (riscv_instr_pkg::supported_isa[i] inside {RV64I, RV64M, RV64A, RV64F, RV64D, RV64C}) begin
+ if (riscv_instr_pkg::supported_isa[i] inside {RV64I, RV64M, RV64A, RV64F, RV64D, RV64C,
+ RV64B}) begin
support_64b = 1'b1;
end else if (riscv_instr_pkg::supported_isa[i] inside {RV128I, RV128C}) begin
support_128b = 1'b1;
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_instr_pkg.sv b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_instr_pkg.sv
index 3a06a71..139ba98 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_instr_pkg.sv
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_instr_pkg.sv
@@ -147,6 +147,108 @@
CSRRWI,
CSRRSI,
CSRRCI,
+ // RV32B instructions
+ ANDN,
+ ORN,
+ XNOR,
+ GORC,
+ SLO,
+ SRO,
+ ROL,
+ ROR,
+ SBCLR,
+ SBSET,
+ SBINV,
+ SBEXT,
+ GREV,
+ SLOI,
+ SROI,
+ RORI,
+ SBCLRI,
+ SBSETI,
+ SBINVI,
+ SBEXTI,
+ GORCI,
+ GREVI,
+ CMIX,
+ CMOV,
+ FSL,
+ FSR,
+ FSRI,
+ CLZ,
+ CTZ,
+ PCNT,
+ SEXT_B,
+ SEXT_H,
+ CRC32_B,
+ CRC32_H,
+ CRC32_W,
+ CRC32C_B,
+ CRC32C_H,
+ CRC32C_W,
+ CLMUL,
+ CLMULR,
+ CLMULH,
+ MIN,
+ MAX,
+ MINU,
+ MAXU,
+ SHFL,
+ UNSHFL,
+ BDEP,
+ BEXT,
+ PACK,
+ PACKU,
+ BMATOR,
+ BMATXOR,
+ PACKH,
+ BFP,
+ SHFLI,
+ UNSHFLI,
+ //RV64B instructions
+ ADDIWU,
+ SLLIU_W,
+ ADDWU,
+ SUBWU,
+ BMATFLIP,
+ CRC32_D,
+ CRC32C_D,
+ ADDU_W,
+ SUBU_W,
+ SLOW,
+ SROW,
+ ROLW,
+ RORW,
+ SBCLRW,
+ SBSETW,
+ SBINVW,
+ SBEXTW,
+ GORCW,
+ GREVW,
+ SLOIW,
+ SROIW,
+ RORIW,
+ SBCLRIW,
+ SBSETIW,
+ SBINVIW,
+ GORCIW,
+ GREVIW,
+ FSLW,
+ FSRW,
+ FSRIW,
+ CLZW,
+ CTZW,
+ PCNTW,
+ CLMULW,
+ CLMULRW,
+ CLMULHW,
+ SHFLW,
+ UNSHFLW,
+ BDEPW,
+ BEXTW,
+ PACKW,
+ PACKUW,
+ BFPW,
// RV32M instructions
MUL,
MULH,
@@ -511,8 +613,8 @@
} riscv_reg_t;
typedef enum bit [4:0] {
- F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15,
- F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30, F31
+ FT0, FT1, FT2, FT3, FT4, FT5, FT6, FT7, FS0, FS1, FA0, FA1, FA2, FA3, FA4, FA5,
+ FA6, FA7, FS2, FS3, FS4, FS5, FS6, FS7, FS8, FS9, FS10, FS11, FT8, FT9, FT10, FT11
} riscv_fpr_t;
typedef enum bit [4:0] {
@@ -1124,7 +1226,8 @@
endfunction
// Get a hex argument from command line
- function automatic void get_hex_arg_value(string cmdline_str, ref int val);
+ function automatic void get_hex_arg_value(string cmdline_str,
+ ref bit [XLEN - 1 : 0] val);
string s;
if(inst.get_arg_value(cmdline_str, s)) begin
val = s.atohex();
@@ -1148,6 +1251,7 @@
`include "riscv_instr_gen_config.sv"
`include "isa/riscv_instr.sv"
`include "isa/riscv_amo_instr.sv"
+ `include "isa/riscv_b_instr.sv"
`include "isa/riscv_floating_point_instr.sv"
`include "isa/riscv_vector_instr.sv"
`include "isa/riscv_compressed_instr.sv"
@@ -1158,8 +1262,10 @@
`include "isa/rv32fc_instr.sv"
`include "isa/rv32f_instr.sv"
`include "isa/rv32i_instr.sv"
+ `include "isa/rv32b_instr.sv"
`include "isa/rv32m_instr.sv"
`include "isa/rv64a_instr.sv"
+ `include "isa/rv64b_instr.sv"
`include "isa/rv64c_instr.sv"
`include "isa/rv64d_instr.sv"
`include "isa/rv64f_instr.sv"
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_instr_sequence.sv b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_instr_sequence.sv
index 913616e..f6e4481 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_instr_sequence.sv
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_instr_sequence.sv
@@ -305,6 +305,7 @@
C_JALR : str = {prefix, $sformatf("c.jalr x%0d", ra)};
C_JR : str = {prefix, $sformatf("c.jr x%0d", ra)};
JALR : str = {prefix, $sformatf("jalr x%0d, x%0d, 0", ra, ra)};
+ default: `uvm_fatal(`gfn, $sformatf("Unsupported jump_instr %0s", jump_instr[i]))
endcase
instr_string_list.push_back(str);
endfunction
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_load_store_instr_lib.sv b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_load_store_instr_lib.sv
index 235178a..94c771e 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_load_store_instr_lib.sv
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_load_store_instr_lib.sv
@@ -42,7 +42,7 @@
constraint sp_rnd_order_c {
solve use_sp_as_rs1 before rs1_reg;
}
-
+
constraint sp_c {
use_sp_as_rs1 dist {1 := 1, 0 := 2};
if (use_sp_as_rs1) {
@@ -245,6 +245,20 @@
endclass
+
+// Back to back load/store instructions
+class riscv_load_store_shared_mem_stream extends riscv_load_store_stress_instr_stream;
+
+ `uvm_object_utils(riscv_load_store_shared_mem_stream)
+ `uvm_object_new
+
+ function void pre_randomize();
+ load_store_shared_memory = 1;
+ super.pre_randomize();
+ endfunction
+
+endclass
+
// Random load/store sequence
// A random mix of load/store instructions and other instructions
class riscv_load_store_rand_instr_stream extends riscv_load_store_base_instr_stream;
@@ -374,6 +388,7 @@
load_store_instr_stream[i].min_instr_cnt = 5;
load_store_instr_stream[i].max_instr_cnt = 10;
load_store_instr_stream[i].cfg = cfg;
+ load_store_instr_stream[i].hart = hart;
load_store_instr_stream[i].sp_c.constraint_mode(0);
// Make sure each load/store sequence doesn't override the rs1 of other sequences.
foreach(rs1_reg[j]) begin
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_page_table_entry.sv b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_page_table_entry.sv
index dfb00f4..b7eaf71 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_page_table_entry.sv
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_page_table_entry.sv
@@ -146,6 +146,7 @@
1 : return PPN0_WIDTH;
2 : return PPN0_WIDTH + PPN1_WIDTH;
3 : return PPN0_WIDTH + PPN1_WIDTH + PPN2_WIDTH;
+ default: `uvm_fatal(`gfn, $sformatf("Unsupported page_level %0x", page_level))
endcase
endfunction
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_pmp_cfg.sv b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_pmp_cfg.sv
index 8abf685..812fc6f 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_pmp_cfg.sv
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_pmp_cfg.sv
@@ -25,8 +25,11 @@
// pmp CSR configurations
rand pmp_cfg_reg_t pmp_cfg[];
// PMP maximum address - used to set defaults
- // TODO(udinator) - make this address configurable?
bit [XLEN - 1 : 0] pmp_max_address = {XLEN{1'b1}};
+ // PMP "minimum" address - the address written to pmpaddr0
+ // to create a "safe region", which contains important setup code,
+ // and cannot throw a PMP fault
+ bit [XLEN - 1 : 0] pmp_min_address = 0;
// used to parse addr_mode configuration from cmdline
typedef uvm_enum_wrapper#(pmp_addr_mode_t) addr_mode_wrapper;
@@ -64,6 +67,7 @@
get_bool_arg_value("+pmp_randomize=", pmp_randomize);
get_int_arg_value("+pmp_granularity=", pmp_granularity);
get_int_arg_value("+pmp_num_regions=", pmp_num_regions);
+ get_hex_arg_value("+pmp_max_address=", pmp_max_address);
pmp_cfg = new[pmp_num_regions];
// As per privileged spec, the top 10 bits of a rv64 PMP address are all 0.
if (XLEN == 64) begin
@@ -75,6 +79,21 @@
end
endfunction
+ function void initialize(bit require_signature_addr);
+ // We want to set the "minimum" pmp address to just after the location of the <main>
+ // section of the program to allow all initialization routines to not be interrupted
+ // by PMP faults.
+ // The location of <main> itself will change depending on whether the handshaking
+ // mechanism is enabled or disabled, so we check if it is enabled and then
+ // round up the address of <main>.
+ pmp_min_address = (require_signature_addr) ? 'h80002910 : 'h80001580;
+
+ if (!pmp_randomize) begin
+ set_defaults();
+ setup_pmp();
+ end
+ endfunction
+
// This will only get called if pmp_randomize is set, in which case we apply command line
// arguments after randomization
function void post_randomize();
@@ -88,13 +107,16 @@
pmp_cfg[i].x = 1'b1;
pmp_cfg[i].w = 1'b1;
pmp_cfg[i].r = 1'b1;
- pmp_cfg[i].addr = assign_default_addr(pmp_num_regions, i + 1);
+ pmp_cfg[i].addr = (i == 0) ? pmp_min_address : assign_default_addr(pmp_num_regions, i);
end
endfunction
// Helper function to break down
function bit [XLEN - 1 : 0] assign_default_addr(int num_regions, int index);
- return pmp_max_address / num_regions * index;
+ bit [XLEN - 1 : 0] total_addr_space, offset;
+ total_addr_space = pmp_max_address - pmp_min_address;
+ offset = total_addr_space / (num_regions - 1) * index;
+ return pmp_min_address + offset;
endfunction
function void setup_pmp();
@@ -163,6 +185,7 @@
64: begin
return {10'b0, shifted_addr[XLEN - 11 : 0]};
end
+ default: `uvm_fatal(`gfn, $sformatf("Unsupported XLEN %0s", XLEN))
endcase
endfunction
@@ -177,7 +200,7 @@
// CSR, this function waits until it has reached this maximum to write to the physical CSR to
// save some extraneous instructions from being performed.
function void gen_pmp_instr(ref string instr[$], riscv_reg_t scratch_reg);
- int cfg_per_csr = XLEN / 4;
+ int cfg_per_csr = XLEN / 8;
bit [XLEN - 1 : 0] pmp_word;
bit [XLEN - 1 : 0] cfg_bitmask;
bit [7 : 0] cfg_byte;
@@ -195,7 +218,7 @@
pmp_word = pmp_word | cfg_bitmask;
`uvm_info(`gfn, $sformatf("pmp_word: 0x%0x", pmp_word), UVM_DEBUG)
cfg_bitmask = 0;
- `uvm_info(`gfn, $sformatf("pmp_addr: 0x%0x", pmp_cfg[i].addr), UVM_DEBUG)
+ `uvm_info(`gfn, $sformatf("pmp_addr_%d: 0x%0x", i, pmp_cfg[i].addr), UVM_DEBUG)
instr.push_back($sformatf("li x%0d, 0x%0x", scratch_reg, pmp_cfg[i].addr));
instr.push_back($sformatf("csrw 0x%0x, x%0d", base_pmp_addr + i, scratch_reg));
// short circuit if end of list
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/target/multi_harts/testlist.yaml b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/target/multi_harts/testlist.yaml
index c491ae7..3bdfdcc 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/target/multi_harts/testlist.yaml
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/target/multi_harts/testlist.yaml
@@ -54,16 +54,28 @@
rtl_test: core_base_test
+- test: riscv_load_store_shared_mem_test
+ description: >
+ Multi-harts load/store from shared memory regions
+ iterations: 2
+ gen_test: riscv_rand_instr_test
+ gen_opts: >
+ +instr_cnt=5000
+ +num_of_sub_program=5
+ +directed_instr_0=riscv_load_store_shared_mem_stream,10
+ rtl_test: core_base_test
+
+
- test: riscv_amo_test
description: >
RISC-V atomic instruction extension test
iterations: 2
gen_test: riscv_rand_instr_test
gen_opts: >
- +instr_cnt=5000
- +num_of_sub_program=5
- +directed_instr_0=riscv_lr_sc_instr_stream,10
- +directed_instr_1=riscv_amo_instr_stream,10
+ +instr_cnt=2000
+ +num_of_sub_program=2
+ +directed_instr_0=riscv_lr_sc_instr_stream,50
+ +directed_instr_1=riscv_amo_instr_stream,50
rtl_test: core_base_test
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/target/rv32imcb/riscvOVPsim.ic b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/target/rv32imcb/riscvOVPsim.ic
new file mode 100644
index 0000000..bad4864
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/target/rv32imcb/riscvOVPsim.ic
@@ -0,0 +1,22 @@
+# riscOVPsim configuration file converted from YAML
+--variant RV32I
+--override iscvOVPsim/cpu/add_Extensions=MCB
+--override riscvOVPsim/cpu/misa_MXL=1
+--override riscvOVPsim/cpu/misa_MXL_mask=0x0 # 0
+--override riscvOVPsim/cpu/misa_Extensions_mask=0x0 # 0
+--override riscvOVPsim/cpu/unaligned=T
+--override riscvOVPsim/cpu/mtvec_mask=0x0 # 0
+--override riscvOVPsim/cpu/user_version=2.3
+--override riscvOVPsim/cpu/priv_version=1.11
+--override riscvOVPsim/cpu/mvendorid=0
+--override riscvOVPsim/cpu/marchid=0
+--override riscvOVPsim/cpu/mimpid=0
+--override riscvOVPsim/cpu/mhartid=0
+--override riscvOVPsim/cpu/cycle_undefined=F
+--override riscvOVPsim/cpu/instret_undefined=F
+--override riscvOVPsim/cpu/time_undefined=T
+--override riscvOVPsim/cpu/reset_address=0x80000000
+--override riscvOVPsim/cpu/simulateexceptions=T
+--override riscvOVPsim/cpu/defaultsemihost=F
+--override riscvOVPsim/cpu/wfi_is_nop=T
+--exitonsymbol _exit
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/target/rv32imcb/riscv_core_setting.sv b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/target/rv32imcb/riscv_core_setting.sv
new file mode 100644
index 0000000..31f3c61
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/target/rv32imcb/riscv_core_setting.sv
@@ -0,0 +1,118 @@
+/*
+ * Copyright 2019 Google LLC
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+//-----------------------------------------------------------------------------
+// Processor feature configuration
+//-----------------------------------------------------------------------------
+// XLEN
+parameter int XLEN = 32;
+
+// Parameter for SATP mode, set to BARE if address translation is not supported
+parameter satp_mode_t SATP_MODE = BARE;
+
+// Supported Privileged mode
+privileged_mode_t supported_privileged_mode[] = {MACHINE_MODE};
+
+// Unsupported instructions
+riscv_instr_name_t unsupported_instr[];
+
+// ISA supported by the processor
+riscv_instr_group_t supported_isa[$] = {RV32I, RV32M, RV32C, RV32B};
+
+// Interrupt mode support
+mtvec_mode_t supported_interrupt_mode[$] = {DIRECT, VECTORED};
+
+// The number of interrupt vectors to be generated, only used if VECTORED interrupt mode is
+// supported
+int max_interrupt_vector_num = 16;
+
+// Physical memory protection support
+bit support_pmp = 0;
+
+// Debug mode support
+bit support_debug_mode = 0;
+
+// Support delegate trap to user mode
+bit support_umode_trap = 0;
+
+// Support sfence.vma instruction
+bit support_sfence = 0;
+
+// Support unaligned load/store
+bit support_unaligned_load_store = 1'b1;
+
+// Parameter for vector extension
+parameter int VECTOR_EXTENSION_ENABLE = 0;
+parameter int VLEN = 512;
+parameter int ELEN = 64;
+parameter int SLEN = 64;
+
+// Number of harts
+parameter int NUM_HARTS = 1;
+
+// ----------------------------------------------------------------------------
+// Previleged CSR implementation
+// ----------------------------------------------------------------------------
+
+// Implemented previlieged CSR list
+`ifdef DSIM
+privileged_reg_t implemented_csr[] = {
+`else
+parameter privileged_reg_t implemented_csr[] = {
+`endif
+ // Machine mode mode CSR
+ MVENDORID, // Vendor ID
+ MARCHID, // Architecture ID
+ MIMPID, // Implementation ID
+ MHARTID, // Hardware thread ID
+ MSTATUS, // Machine status
+ MISA, // ISA and extensions
+ MIE, // Machine interrupt-enable register
+ MTVEC, // Machine trap-handler base address
+ MCOUNTEREN, // Machine counter enable
+ MSCRATCH, // Scratch register for machine trap handlers
+ MEPC, // Machine exception program counter
+ MCAUSE, // Machine trap cause
+ MTVAL, // Machine bad address or instruction
+ MIP // Machine interrupt pending
+};
+
+// ----------------------------------------------------------------------------
+// Supported interrupt/exception setting, used for functional coverage
+// ----------------------------------------------------------------------------
+
+`ifdef DSIM
+interrupt_cause_t implemented_interrupt[] = {
+`else
+parameter interrupt_cause_t implemented_interrupt[] = {
+`endif
+ M_SOFTWARE_INTR,
+ M_TIMER_INTR,
+ M_EXTERNAL_INTR
+};
+
+`ifdef DSIM
+exception_cause_t implemented_exception[] = {
+`else
+parameter exception_cause_t implemented_exception[] = {
+`endif
+ INSTRUCTION_ACCESS_FAULT,
+ ILLEGAL_INSTRUCTION,
+ BREAKPOINT,
+ LOAD_ADDRESS_MISALIGNED,
+ LOAD_ACCESS_FAULT,
+ ECALL_MMODE
+};
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/target/rv32imcb/testlist.yaml b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/target/rv32imcb/testlist.yaml
new file mode 100644
index 0000000..bbede2b
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/target/rv32imcb/testlist.yaml
@@ -0,0 +1,43 @@
+# Copyright Google LLC
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# ================================================================================
+# Regression test list format
+# --------------------------------------------------------------------------------
+# test : Assembly test name
+# description : Description of this test
+# gen_opts : Instruction generator options
+# iterations : Number of iterations of this test
+# no_iss : Enable/disable ISS simulator (Optional)
+# gen_test : Test name used by the instruction generator
+# asm_tests : Path to directed, hand-coded assembly test file or directory
+# rtl_test : RTL simulation test name
+# cmp_opts : Compile options passed to the instruction generator
+# sim_opts : Simulation options passed to the instruction generator
+# no_post_compare : Enable/disable comparison of trace log and ISS log (Optional)
+# compare_opts : Options for the RTL & ISS trace comparison
+# gcc_opts : gcc compile options
+# --------------------------------------------------------------------------------
+
+- import: <riscv_dv_root>/target/rv32imc/testlist.yaml
+
+
+- test: riscv_b_ext_test
+ description: >
+ Random instruction test with b extension
+ iterations: 1
+ gen_test: riscv_rand_instr_test
+ gen_opts: >
+ +enable_b_extension=1
+ rtl_test: core_base_test
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/test/riscv_instr_cov_test.sv b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/test/riscv_instr_cov_test.sv
index cfbb318..668df7e 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/test/riscv_instr_cov_test.sv
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/test/riscv_instr_cov_test.sv
@@ -3,6 +3,7 @@
typedef uvm_enum_wrapper#(riscv_instr_name_t) instr_enum;
typedef uvm_enum_wrapper#(riscv_reg_t) gpr_enum;
+ typedef uvm_enum_wrapper#(riscv_fpr_t) fpr_enum;
typedef uvm_enum_wrapper#(privileged_reg_t) preg_enum;
riscv_instr_gen_config cfg;
@@ -136,7 +137,8 @@
if (instr_enum::from_name(process_instr_name(trace["instr"]), instr_name)) begin
if (riscv_instr::instr_template.exists(instr_name)) begin
instr.copy(riscv_instr::instr_template[instr_name]);
- if (instr.group inside {RV32I, RV32M, RV32C, RV64I, RV64M, RV64C}) begin
+ if (instr.group inside {RV32I, RV32M, RV32C, RV64I, RV64M, RV64C,
+ RV32F}) begin
assign_trace_info_to_instr(instr);
end
instr.pre_sample();
@@ -169,6 +171,8 @@
get_val(operands[1], instr.imm);
end
I_FORMAT: begin
+ // TODO, support I_FORMAT floating point later
+ if (instr.group == RV32F) return;
`DV_CHECK_FATAL(operands.size() == 3, trace["instr_str"])
if(instr.category == LOAD) begin
// load rd, imm(rs1)
@@ -194,8 +198,10 @@
`DV_CHECK_FATAL(operands.size() == 3)
if(instr.category == STORE) begin
// sw rs2,imm(rs1)
- instr.rs2 = get_gpr(operands[0]);
- instr.rs2_value = get_gpr_state(operands[0]);
+ update_instr_reg_by_abi_name(operands[0], // FSW rs2 is fp
+ instr.rs2, instr.rs2_value,
+ instr.fs2, instr.fs2_value);
+
instr.rs1 = get_gpr(operands[2]);
instr.rs1_value = get_gpr_state(operands[2]);
get_val(operands[1], instr.imm);
@@ -209,7 +215,8 @@
end
end
R_FORMAT: begin
- `DV_CHECK_FATAL(operands.size() == 3)
+ if (!instr.instr_name inside {FCLASS_S, FCLASS_D}) `DV_CHECK_FATAL(operands.size() == 3)
+ else `DV_CHECK_FATAL(operands.size() == 2)
if(instr.category == CSR) begin
// csrrw rd, csr, rs1
if (preg_enum::from_name(operands[1].toupper(), preg)) begin
@@ -219,6 +226,16 @@
end
instr.rs1 = get_gpr(operands[2]);
instr.rs1_value = get_gpr_state(operands[2]);
+ end
+ else if (instr.group inside {RV32F, RV64F, RV32D, RV64D}) begin
+ // fs1
+ instr.fs1 = get_fpr(operands[1]);
+ instr.fs1_value = get_gpr_state(operands[1]);
+ // fs2
+ if (!instr.instr_name inside {FCLASS_S, FCLASS_D}) begin
+ instr.fs2 = get_fpr(operands[2]);
+ instr.fs2_value = get_gpr_state(operands[2]);
+ end
end else begin
// add rd, rs1, rs2
instr.rs1 = get_gpr(operands[1]);
@@ -227,6 +244,15 @@
instr.rs2_value = get_gpr_state(operands[2]);
end
end
+ R4_FORMAT: begin
+ `DV_CHECK_FATAL(operands.size() == 4)
+ instr.fs1 = get_fpr(operands[1]);
+ instr.fs1_value = get_gpr_state(operands[1]);
+ instr.fs2 = get_fpr(operands[2]);
+ instr.fs2_value = get_gpr_state(operands[2]);
+ instr.fs3 = get_fpr(operands[3]);
+ instr.fs3_value = get_gpr_state(operands[3]);
+ end
CI_FORMAT, CIW_FORMAT: begin
if (instr.instr_name == C_ADDI16SP) begin
get_val(operands[1], instr.imm);
@@ -303,8 +329,7 @@
`uvm_fatal(`gfn, $sformatf("Illegal gpr update format: %0s", gpr_update[i]))
end
get_val(pair[1], gpr_state[pair[0]], .hex(1));
- instr.rd = get_gpr(pair[0]);
- instr.rd_value = get_gpr_state(pair[0]);
+ update_instr_reg_by_abi_name(pair[0], instr.rd, instr.rd_value, instr.fd, instr.fd_value);
end
endfunction : assign_trace_info_to_instr
@@ -315,6 +340,13 @@
end
endfunction : get_gpr
+ function riscv_fpr_t get_fpr(input string str);
+ str = str.toupper();
+ if (!fpr_enum::from_name(str, get_fpr)) begin
+ `uvm_fatal(`gfn, $sformatf("Cannot convert %0s to FPR", str))
+ end
+ endfunction : get_fpr
+
function bit [XLEN-1:0] get_gpr_state(string name);
if (name inside {"zero", "x0"}) begin
return 0;
@@ -347,6 +379,26 @@
`uvm_info(`gfn, $sformatf("imm:%0s -> 0x%0x/%0d", str, val, $signed(val)), UVM_FULL)
endfunction : get_val
+ function bit is_fp_reg(input string str);
+ riscv_fpr_t tmp;
+ str = str.toupper();
+ return fpr_enum::from_name(str, tmp);
+ endfunction : is_fp_reg
+
+ function void update_instr_reg_by_abi_name(string abi_name,
+ ref riscv_reg_t rs,
+ ref bit [XLEN-1:0] rs_value,
+ ref riscv_fpr_t fs,
+ ref bit [XLEN-1:0] fs_value);
+ if (is_fp_reg(abi_name)) begin
+ fs = get_fpr(abi_name);
+ fs_value = get_gpr_state(abi_name);
+ end else begin
+ rs = get_gpr(abi_name);
+ rs_value = get_gpr_state(abi_name);
+ end
+ endfunction : update_instr_reg_by_abi_name
+
function string process_instr_name(string instr_name);
instr_name = instr_name.toupper();
foreach (instr_name[i]) begin
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/test/riscv_instr_test_lib.sv b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/test/riscv_instr_test_lib.sv
index 36ed566..a290e61 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/test/riscv_instr_test_lib.sv
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/test/riscv_instr_test_lib.sv
@@ -48,13 +48,12 @@
virtual function void randomize_cfg();
cfg.no_fence = 0;
- cfg.no_ebreak = 0;
cfg.init_privileged_mode = MACHINE_MODE;
cfg.init_privileged_mode.rand_mode(0);
cfg.enable_unaligned_load_store = 1'b1;
cfg.addr_translaction_rnd_order_c.constraint_mode(0);
`DV_CHECK_RANDOMIZE_FATAL(cfg)
- cfg.addr_translaction_rnd_order_c.constraint_mode(1);
+ cfg.addr_translaction_rnd_order_c.constraint_mode(1);
`uvm_info(`gfn, $sformatf("riscv_instr_gen_config is randomized:\n%0s",
cfg.sprint()), UVM_LOW)
endfunction
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/verilog_style/build-verible.sh b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/verilog_style/build-verible.sh
index f4d3a6a..764af22 100755
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/verilog_style/build-verible.sh
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/verilog_style/build-verible.sh
@@ -14,7 +14,7 @@
# See the License for the specific language governing permissions and
# limitations under the License.
-VERIBLE_VERSION=03c7102ab8ed63037159f479ce17b3487401f082
+VERIBLE_VERSION=751d4d8e57741ab22806f91982f59c71ecf37d9d
INSTALL_DIR=/tools/verible
# this requires the bazel build system and GCC7
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/verilog_style/exclude_filelist.f b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/verilog_style/exclude_filelist.f
index ac20326..44b8680 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/verilog_style/exclude_filelist.f
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/verilog_style/exclude_filelist.f
@@ -5,6 +5,3 @@
riscv_instr_pkg.sv
# tool does not support included file very well. Issue at github.com/google/verible/issues/178
riscv_custom_instr_enum.sv
-# tool bug. Issue at github.com/google/verible/issues/172
-riscv_instr_stream.sv
-riscv_reg.sv
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/yaml/simulator.yaml b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/yaml/simulator.yaml
index d926809..06e29c8 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/yaml/simulator.yaml
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/yaml/simulator.yaml
@@ -29,7 +29,7 @@
cmd: >
<out>/vcs_simv +vcs+lic+wait <sim_opts> +ntb_random_seed=<seed> <cov_opts>
cov_opts: >
- -cm_dir <out>/test.vdb -cm_log /dev/null -cm_name test_<seed>
+ -cm_dir <out>/test.vdb -cm_log /dev/null -cm_name test_<seed>_<test_id>
- tool: ius
compile:
diff --git a/hw/vendor/lowrisc_ibex/vendor/lowrisc_common_ifs.lock.hjson b/hw/vendor/lowrisc_ibex/vendor/lowrisc_common_ifs.lock.hjson
new file mode 100644
index 0000000..c57dd37
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/lowrisc_common_ifs.lock.hjson
@@ -0,0 +1,15 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// This file is generated by the util/vendor script. Please do not modify it
+// manually.
+
+{
+ upstream:
+ {
+ url: https://github.com/lowRISC/opentitan
+ rev: 0d7f7ac755d4e00811257027dd814edb2afca050
+ only_subdir: hw/dv/sv/common_ifs
+ }
+}
diff --git a/hw/vendor/lowrisc_ibex/vendor/lowrisc_common_ifs.vendor.hjson b/hw/vendor/lowrisc_ibex/vendor/lowrisc_common_ifs.vendor.hjson
new file mode 100644
index 0000000..647e521
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/lowrisc_common_ifs.vendor.hjson
@@ -0,0 +1,13 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+{
+ name: "common_ifs",
+ target_dir: "lowrisc_ip/common_ifs",
+
+ upstream: {
+ url: "https://github.com/lowRISC/opentitan"
+ rev: "master"
+ only_subdir: "hw/dv/sv/common_ifs"
+ }
+}
diff --git a/hw/vendor/lowrisc_ibex/vendor/lowrisc_csr_utils.lock.hjson b/hw/vendor/lowrisc_ibex/vendor/lowrisc_csr_utils.lock.hjson
new file mode 100644
index 0000000..faf766f
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/lowrisc_csr_utils.lock.hjson
@@ -0,0 +1,15 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// This file is generated by the util/vendor script. Please do not modify it
+// manually.
+
+{
+ upstream:
+ {
+ url: https://github.com/lowRISC/opentitan
+ rev: 0d7f7ac755d4e00811257027dd814edb2afca050
+ only_subdir: hw/dv/sv/csr_utils
+ }
+}
diff --git a/hw/vendor/lowrisc_ibex/vendor/lowrisc_csr_utils.vendor.hjson b/hw/vendor/lowrisc_ibex/vendor/lowrisc_csr_utils.vendor.hjson
new file mode 100644
index 0000000..015c073
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/lowrisc_csr_utils.vendor.hjson
@@ -0,0 +1,13 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+{
+ name: "csr_utils",
+ target_dir: "lowrisc_ip/csr_utils",
+
+ upstream: {
+ url: "https://github.com/lowRISC/opentitan"
+ rev: "master"
+ only_subdir: "hw/dv/sv/csr_utils"
+ }
+}
diff --git a/hw/vendor/lowrisc_ibex/vendor/lowrisc_dv_lib.lock.hjson b/hw/vendor/lowrisc_ibex/vendor/lowrisc_dv_lib.lock.hjson
new file mode 100644
index 0000000..b8f4afd
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/lowrisc_dv_lib.lock.hjson
@@ -0,0 +1,15 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// This file is generated by the util/vendor script. Please do not modify it
+// manually.
+
+{
+ upstream:
+ {
+ url: https://github.com/lowRISC/opentitan
+ rev: 0d7f7ac755d4e00811257027dd814edb2afca050
+ only_subdir: hw/dv/sv/dv_lib
+ }
+}
diff --git a/hw/vendor/lowrisc_ibex/vendor/lowrisc_dv_lib.vendor.hjson b/hw/vendor/lowrisc_ibex/vendor/lowrisc_dv_lib.vendor.hjson
new file mode 100644
index 0000000..adafe41
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/lowrisc_dv_lib.vendor.hjson
@@ -0,0 +1,13 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+{
+ name: "dv_lib",
+ target_dir: "lowrisc_ip/dv_lib",
+
+ upstream: {
+ url: "https://github.com/lowRISC/opentitan"
+ rev: "master"
+ only_subdir: "hw/dv/sv/dv_lib"
+ }
+}
diff --git a/hw/vendor/lowrisc_ibex/vendor/lowrisc_dv_utils.lock.hjson b/hw/vendor/lowrisc_ibex/vendor/lowrisc_dv_utils.lock.hjson
new file mode 100644
index 0000000..fb08a74
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/lowrisc_dv_utils.lock.hjson
@@ -0,0 +1,15 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// This file is generated by the util/vendor script. Please do not modify it
+// manually.
+
+{
+ upstream:
+ {
+ url: https://github.com/lowRISC/opentitan
+ rev: 0d7f7ac755d4e00811257027dd814edb2afca050
+ only_subdir: hw/dv/sv/dv_utils
+ }
+}
diff --git a/hw/vendor/lowrisc_ibex/vendor/lowrisc_dv_utils.vendor.hjson b/hw/vendor/lowrisc_ibex/vendor/lowrisc_dv_utils.vendor.hjson
new file mode 100644
index 0000000..8fb2fc1
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/lowrisc_dv_utils.vendor.hjson
@@ -0,0 +1,14 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+{
+ name: "dv_utils",
+ target_dir: "lowrisc_ip/dv_utils",
+ patch_dir: "patches/lowrisc_dv_utils",
+
+ upstream: {
+ url: "https://github.com/lowRISC/opentitan"
+ rev: "master"
+ only_subdir: "hw/dv/sv/dv_utils"
+ }
+}
diff --git a/hw/vendor/lowrisc_ibex/vendor/lowrisc_dvsim.lock.hjson b/hw/vendor/lowrisc_ibex/vendor/lowrisc_dvsim.lock.hjson
new file mode 100644
index 0000000..e1bd75c
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/lowrisc_dvsim.lock.hjson
@@ -0,0 +1,15 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// This file is generated by the util/vendor script. Please do not modify it
+// manually.
+
+{
+ upstream:
+ {
+ url: https://github.com/lowRISC/opentitan
+ rev: 0d7f7ac755d4e00811257027dd814edb2afca050
+ only_subdir: util/dvsim
+ }
+}
diff --git a/hw/vendor/lowrisc_ibex/vendor/lowrisc_dvsim.vendor.hjson b/hw/vendor/lowrisc_ibex/vendor/lowrisc_dvsim.vendor.hjson
new file mode 100644
index 0000000..3d31646
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/lowrisc_dvsim.vendor.hjson
@@ -0,0 +1,13 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+{
+ name: "dvsim",
+ target_dir: "lowrisc_ip/dvsim",
+
+ upstream: {
+ url: "https://github.com/lowRISC/opentitan"
+ rev: "master"
+ only_subdir: "util/dvsim"
+ }
+}
diff --git a/hw/vendor/lowrisc_ibex/vendor/lowrisc_uvmdvgen.lock.hjson b/hw/vendor/lowrisc_ibex/vendor/lowrisc_uvmdvgen.lock.hjson
new file mode 100644
index 0000000..2855291
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/lowrisc_uvmdvgen.lock.hjson
@@ -0,0 +1,15 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// This file is generated by the util/vendor script. Please do not modify it
+// manually.
+
+{
+ upstream:
+ {
+ url: https://github.com/lowRISC/opentitan
+ rev: 0d7f7ac755d4e00811257027dd814edb2afca050
+ only_subdir: util/uvmdvgen
+ }
+}
diff --git a/hw/vendor/lowrisc_ibex/vendor/lowrisc_uvmdvgen.vendor.hjson b/hw/vendor/lowrisc_ibex/vendor/lowrisc_uvmdvgen.vendor.hjson
new file mode 100644
index 0000000..59eff14
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/lowrisc_uvmdvgen.vendor.hjson
@@ -0,0 +1,13 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+{
+ name: "uvmdvgen",
+ target_dir: "lowrisc_ip/uvmdvgen",
+
+ upstream: {
+ url: "https://github.com/lowRISC/opentitan"
+ rev: "master"
+ only_subdir: "util/uvmdvgen"
+ }
+}
diff --git a/hw/vendor/lowrisc_ibex/vendor/patches/eembc_coremark/0001-no-minimum-run-time.patch b/hw/vendor/lowrisc_ibex/vendor/patches/eembc_coremark/0001-no-minimum-run-time.patch
new file mode 100644
index 0000000..71927aa
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/patches/eembc_coremark/0001-no-minimum-run-time.patch
@@ -0,0 +1,25 @@
+diff --git a/core_main.c b/core_main.c
+index 6161974..cca596c 100644
+--- a/core_main.c
++++ b/core_main.c
+@@ -295,10 +295,16 @@ MAIN_RETURN_TYPE main(int argc, char *argv[]) {
+ if (time_in_secs(total_time) > 0)
+ ee_printf("Iterations/Sec : %d\n",default_num_contexts*results[0].iterations/time_in_secs(total_time));
+ #endif
+- if (time_in_secs(total_time) < 10) {
+- ee_printf("ERROR! Must execute for at least 10 secs for a valid result!\n");
+- total_errors++;
+- }
++ // Remove error report if execution time low.
++ // On Ibex a few loops suffices to get an accurate result. With this check in
++ // the verilator simulation of coremark will report failure (unless left running
++ // for a significant number of iterations greatly increasing simulation time).
++ // The other error checking is useful to determine if the benchmark has been
++ // broken in some way which is masked if this check is left in.
++ //if (time_in_secs(total_time) < 10) {
++ // ee_printf("ERROR! Must execute for at least 10 secs for a valid result!\n");
++ // total_errors++;
++ //}
+
+ ee_printf("Iterations : %lu\n", (long unsigned) default_num_contexts*results[0].iterations);
+ ee_printf("Compiler version : %s\n",COMPILER_VERSION);
