commit | 13ed3e95572168f7db0e3178d06a72e72ee5a745 | [log] [tgz] |
---|---|---|
author | Timothy Chen <timothytim@google.com> | Mon Nov 29 17:51:57 2021 -0800 |
committer | tjaychen <timothytim@google.com> | Tue Nov 30 09:55:00 2021 -0800 |
tree | 190c31dca810d9a437ffb493278f15a897d38071 | |
parent | 798ad2892fe5c83ca333a62128a7babc1999abbf [diff] |
[flash_ctrl] First step fix for flash ECC - Should address #9397 - Merge the separate flash data / metadata memories back into one - Update the backdoor path to use the full 76_68 ECC scheme - Update flash backdoor load to create the extra 4-bits of integrity ECC for the purposes of backdoor load. - The flash routine is responsible for the 4-bit integrity ECC, while the mem_bkdr_util routine is responsible for the 8-bit reliability ECC - In the future, the same routine that creates the 4-bit integrity ECC will also be responsible for scramble, the final backdoor load will only be aware of the 8-bit reliability ECC. Signed-off-by: Timothy Chen <timothytim@google.com>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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