commit 05bb91126147592d9b1666da30339071846f464d
author Pirmin Vogel <vogelpi@lowrisc.org> Tue Jul 20 12:20:15 2021 +0200
committer Pirmin Vogel <vogelpi@lowrisc.org> Tue Aug 03 09:48:45 2021 +0200
tree 5a331e7002c72a2f8890a2af0f9d49c7735d9920
parent 502a20f19fb13853332a0f0a7ad4992400b04c1e

[top] Fix typos and indentation

Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>

hw/top_earlgrey/data/top_earlgrey.hjson

diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson
index 3d784b5..6c9df7a 100644
--- a/hw/top_earlgrey/data/top_earlgrey.hjson
+++ b/hw/top_earlgrey/data/top_earlgrey.hjson
@@ -1381,7 +1381,7 @@
         ],
 
         add_pads: [
-          // Additional infrastucture pads
+          // Additional infrastructure pads
           { name: 'IO_CLK',           type: 'InputStd', bank: 'VCC', connection: 'manual', desc: 'Extra clock input for FPGA target'}
           { name: 'IO_JSRST_N',       type: 'InputStd', bank: 'VCC', connection: 'manual', desc: 'Dedicated JTAG system reset input'}
           // Custom USB pads
@@ -1399,7 +1399,7 @@
         ],
       },
 
-pinmux: {
+      pinmux: {
         special_signals: [
           // Straps
           { name: 'tap0',   pad: 'IOC0' ,        desc: 'TAP strap signal, maps to a stubbed-off MIO.'  },
@@ -1431,7 +1431,7 @@
         ],
 
         add_pads: [
-          // Additional infrastucture pads
+          // Additional infrastructure pads
           { name: 'IO_CLK',           type: 'InputStd', bank: 'VCC', connection: 'manual', desc: 'Extra clock input for FPGA target'}
           { name: 'IO_JSRST_N',       type: 'InputStd', bank: 'VCC', connection: 'manual', desc: 'Dedicated JTAG system reset input'}
           // Custom USB pads
@@ -1449,7 +1449,7 @@
         ],
       },
 
-pinmux: {
+      pinmux: {
         special_signals: [
           // Straps
           { name: 'tap0',   pad: 'IOC0' ,        desc: 'TAP strap signal, maps to a stubbed-off MIO.'  },