[topgen] - Generate top clock groups variable
- clock_groups will eventually be fed to clock_controller for generation
- clock_groups walks through all modules, memories and xbars and associates
the correct clock given the grouping and source attributes
- top_earlgrey.gen.hjson clock_connections looks very different from the
original input
Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/util/topgen/lib.py b/util/topgen/lib.py
index 6ee4fc7..887b2ef 100644
--- a/util/topgen/lib.py
+++ b/util/topgen/lib.py
@@ -220,6 +220,14 @@
return "[{}]".format(i) if i != -1 else ""
+def get_clk_name(clk):
+ """Return the appropriate clk name
+ """
+ if clk == 'main':
+ return 'clk_i'
+ else:
+ return "clk_{}_i".format(clk)
+
def get_reset_path(resets, name):
"""Return the appropriate reset path given name
"""
