[top_earlgrey] Multi-tiered Xbar
Problem (Need-to-Improve):
tlgen puts many Async FIFOs if the devices' clocks are different
from the main Xbar clock. If the top has multiple Xbars, the address
for lower-tiered Xbar isn't aggregated into the device port of the
main crossbar.
This commit is to separate the main crossbar into two crossbars, one for
main crossbar having the peripherals, memories having main clock,
another for the peri crossbar having the peripherals using fixed clock
for their main clocks.
Signed-off-by: Eunchan Kim <eunchan@opentitan.org>
diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson
index f3c41d7..aa0c919 100644
--- a/hw/top_earlgrey/data/top_earlgrey.hjson
+++ b/hw/top_earlgrey/data/top_earlgrey.hjson
@@ -157,6 +157,11 @@
reset: "sys",
reset_connections: {rst_main_ni: "sys", rst_fixed_ni: "sys_fixed"}
},
+ { name: "peri",
+ clock_connections: {clk_peri_i: "fixed"},
+ reset: "sys_fixed",
+ reset_connections: {rst_peri_ni: "sys_fixed"},
+ }
],
// ===== INTERRUPT CTRL =====================================================
diff --git a/hw/top_earlgrey/data/xbar_main.hjson b/hw/top_earlgrey/data/xbar_main.hjson
index e95d0b0..97f0d3a 100644
--- a/hw/top_earlgrey/data/xbar_main.hjson
+++ b/hw/top_earlgrey/data/xbar_main.hjson
@@ -51,19 +51,7 @@
reset: "rst_main_ni",
pipeline: "false",
},
- { name: "uart",
- type: "device",
- clock: "clk_fixed_i",
- reset: "rst_fixed_ni",
- pipeline_byp: "false"
- },
- { name: "gpio",
- type: "device",
- clock: "clk_fixed_i",
- reset: "rst_fixed_ni",
- pipeline_byp: "false"
- },
- { name: "spi_device",
+ { name: "peri",
type: "device",
clock: "clk_fixed_i",
reset: "rst_fixed_ni",
@@ -75,12 +63,6 @@
reset: "rst_main_ni",
pipeline_byp: "false"
},
- { name: "rv_timer",
- type: "device",
- clock: "clk_fixed_i",
- reset: "rst_fixed_ni",
- pipeline_byp: "false"
- },
{ name: "hmac",
type: "device",
clock: "clk_main_i",
@@ -128,9 +110,9 @@
],
connections: {
corei: ["rom", "debug_mem", "ram_main", "eflash"],
- cored: ["rom", "debug_mem", "ram_main", "eflash", "uart", "gpio", "spi_device", "flash_ctrl",
- "rv_timer", "aes", "hmac", "rv_plic", "pinmux", "alert_handler", "nmi_gen"],
- dm_sba: ["rom", "ram_main", "eflash", "uart", "gpio", "spi_device", "flash_ctrl",
- "rv_timer", "aes", "hmac", "rv_plic", "pinmux", "alert_handler", "nmi_gen"],
+ cored: ["rom", "debug_mem", "ram_main", "eflash", "peri", "flash_ctrl",
+ "aes", "hmac", "rv_plic", "pinmux", "alert_handler", "nmi_gen"],
+ dm_sba: ["rom", "ram_main", "eflash", "peri", "flash_ctrl",
+ "aes", "hmac", "rv_plic", "pinmux", "alert_handler", "nmi_gen"],
},
}
diff --git a/hw/top_earlgrey/data/xbar_peri.hjson b/hw/top_earlgrey/data/xbar_peri.hjson
new file mode 100644
index 0000000..0786baa
--- /dev/null
+++ b/hw/top_earlgrey/data/xbar_peri.hjson
@@ -0,0 +1,43 @@
+{ name: "peri",
+ type: "xbar",
+ clock_primary: "clk_peri_i", // Main clock, used in sockets
+ reset_primary: "rst_peri_ni", // Main reset, used in sockets
+
+ nodes: [
+ { name: "main",
+ type: "host",
+ clock: "clk_peri_i",
+ reset: "rst_peri_ni",
+ xbar: "true",
+ pipeline: "false"
+
+ },
+ { name: "uart",
+ type: "device",
+ clock: "clk_peri_i",
+ reset: "rst_peri_ni",
+ pipeline: "false"
+ },
+ { name: "gpio",
+ type: "device",
+ clock: "clk_peri_i",
+ reset: "rst_peri_ni",
+ pipeline: "false"
+ },
+ { name: "spi_device",
+ type: "device",
+ clock: "clk_peri_i",
+ reset: "rst_peri_ni",
+ pipeline: "false"
+ },
+ { name: "rv_timer",
+ type: "device",
+ clock: "clk_peri_i",
+ reset: "rst_peri_ni",
+ pipeline: "false"
+ }
+ ],
+ connections: {
+ main: ["uart", "gpio", "spi_device", "rv_timer"],
+ },
+}
