[fpga] Constrain JTAG and SPI clocks
This commit makes sure the JTAG and SPI clock signals are constrained
(currently to 10 MHz just like the main system clock on FPGA).
Previously, they were both unconstrained which might have caused issues.
This is related to lowRISC/OpenTitan#3606.
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
diff --git a/hw/top_earlgrey/data/clocks.xdc b/hw/top_earlgrey/data/clocks.xdc
index 694c0a5..632b7a5 100644
--- a/hw/top_earlgrey/data/clocks.xdc
+++ b/hw/top_earlgrey/data/clocks.xdc
@@ -20,4 +20,9 @@
set u_div4 top_earlgrey/u_clkmgr/u_io_div4_div
create_generated_clock -name clk_io_div4 -source [get_pin ${u_pll}/CLKOUT0] -divide_by 4 [get_pin ${u_div4}/u_clk_div_buf/gen_xilinx.u_impl_xilinx/bufg_i/O]
-set_clock_groups -group ${clks_10_unbuf} -group ${clks_48_unbuf} -group clk_io_div2 -group clk_io_div4 -asynchronous
+## JTAG and SPI clocks
+create_clock -add -name jtag_tck -period 100.00 -waveform {0 5} [get_nets jtag_tck_buf]
+create_clock -add -name clk_spi_in -period 100.00 -waveform {0 5} [get_pin top_earlgrey/u_spi_device/u_clk_spi_in_buf/gen_xilinx.u_impl_xilinx/bufg_i/O]
+create_clock -add -name clk_spi_out -period 100.00 -waveform {0 5} [get_pin top_earlgrey/u_spi_device/u_clk_spi_out_buf/gen_xilinx.u_impl_xilinx/bufg_i/O]
+
+set_clock_groups -group ${clks_10_unbuf} -group ${clks_48_unbuf} -group clk_io_div2 -group clk_io_div4 -group jtag_tck -group clk_spi_in -group clk_spi_out -asynchronous
