[sysrst_ctrl] Enable autogenerated CDC regs for config CSRs
Signed-off-by: Michael Schaffner <msf@opentitan.org>
diff --git a/hw/ip/sysrst_ctrl/data/sysrst_ctrl.hjson b/hw/ip/sysrst_ctrl/data/sysrst_ctrl.hjson
index 782d8e0..dc668b0 100644
--- a/hw/ip/sysrst_ctrl/data/sysrst_ctrl.hjson
+++ b/hw/ip/sysrst_ctrl/data/sysrst_ctrl.hjson
@@ -38,6 +38,12 @@
desc: "Number of keyboard combos",
local: "true",
}
+ { name: "TimerWidth",
+ type: "int",
+ default: "16",
+ desc: "Number of timer bits",
+ local: "true",
+ }
],
available_input_list: [
{ name: "ac_present", desc: "A/C power is present" }
@@ -93,9 +99,9 @@
desc: "EC reset control register",
swaccess: "rw",
hwaccess: "hro",
- hwqe: "true",
regwen: "REGWEN",
resval: "2000",
+ async: "clk_aon_i",
fields: [
{ bits: "15:0",
name: "ec_rst_pulse",
@@ -107,9 +113,9 @@
desc: "Ultra low power AC debounce control register",
swaccess: "rw",
hwaccess: "hro",
- hwqe: "true",
regwen: "REGWEN",
resval: "8000",
+ async: "clk_aon_i",
fields: [
{ bits: "15:0",
name: "ulp_ac_debounce_timer",
@@ -121,9 +127,9 @@
desc: "Ultra low power lid debounce control register",
swaccess: "rw",
hwaccess: "hro",
- hwqe: "true",
regwen: "REGWEN",
resval: "8000",
+ async: "clk_aon_i",
fields: [
{ bits: "15:0",
name: "ulp_lid_debounce_timer",
@@ -135,9 +141,9 @@
desc: "Ultra low power pwrb debounce control register",
swaccess: "rw",
hwaccess: "hro",
- hwqe: "true",
regwen: "REGWEN",
resval: "8000",
+ async: "clk_aon_i",
fields: [
{ bits: "15:0",
name: "ulp_pwrb_debounce_timer",
@@ -150,6 +156,7 @@
swaccess: "rw",
hwaccess: "hro",
resval: "0",
+ async: "clk_aon_i",
fields: [
{ bits: "0",
name: "ulp_enable",
@@ -162,6 +169,7 @@
swaccess: "rw1c",
hwaccess: "hwo",
resval: "0",
+ async: "clk_aon_i",
tags: [ // the value of these regs is determined by the
// value on the pins, hence it cannot be predicted.
"excl:CsrNonInitTests:CsrExclCheck"],
@@ -193,6 +201,7 @@
hwaccess: "hro",
regwen: "REGWEN",
resval: "0",
+ async: "clk_aon_i",
fields: [
{ bits: "0",
name: "key0_in",
@@ -250,6 +259,7 @@
hwaccess: "hro",
regwen: "REGWEN",
resval: "2",
+ async: "clk_aon_i",
fields: [
{ bits: "0",
name: "bat_disable_0",
@@ -314,6 +324,7 @@
swaccess: "rw",
hwaccess: "hro",
resval: "2",
+ async: "clk_aon_i",
fields: [
{ bits: "0",
name: "bat_disable",
@@ -350,6 +361,7 @@
swaccess: "rw",
hwaccess: "hro",
resval: "0",
+ async: "clk_aon_i",
fields: [
{ bits: "0",
name: "bat_disable",
@@ -426,6 +438,7 @@
hwaccess: "hro",
regwen: "REGWEN",
resval: "0",
+ async: "clk_aon_i",
fields: [
{ bits: "0",
name: "pwrb_in_H2L",
@@ -481,11 +494,11 @@
desc: "Debounce timer control register for key-triggered interrupt",
swaccess: "rw",
hwaccess: "hro",
- hwqe: "true",
regwen: "REGWEN",
resval: "0",
+ async: "clk_aon_i",
fields: [
- { bits: "15:0",
+ { bits: "TimerWidth-1:0",
name: "debounce_timer",
desc: "Define the timer valure so that the key or input is not oscillating for 0-200ms, each step is 5us(200KHz clock)",
}
@@ -495,9 +508,9 @@
desc: "Debounce timer control register for pwrb_in H2L transition",
swaccess: "rw",
hwaccess: "hro",
- hwqe: "true",
regwen: "REGWEN",
resval: "0",
+ async: "clk_aon_i",
fields: [
{ bits: "15:0",
name: "debounce_timer",
@@ -515,6 +528,7 @@
hwaccess: "hro",
regwen: "REGWEN",
resval: "0",
+ async: "clk_aon_i",
fields: [
{ bits: "0",
name: "key0_out_sel",
@@ -559,6 +573,7 @@
hwaccess: "hro",
regwen: "REGWEN",
resval: "0",
+ async: "clk_aon_i",
fields: [
{ bits: "0",
name: "key0_in_sel",
@@ -590,11 +605,11 @@
''',
count: "NumCombo",
cname: "sysrst_ctrl",
- hwqe: "true",
swaccess: "rw",
hwaccess: "hro",
regwen: "REGWEN",
resval: "0",
+ async: "clk_aon_i",
fields: [
{ bits: "31:0",
name: "detection_timer",
@@ -618,6 +633,7 @@
hwaccess: "hro",
regwen: "REGWEN",
resval: "0",
+ async: "clk_aon_i",
fields: [
{ bits: "0",
name: "bat_disable",
diff --git a/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl.sv b/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl.sv
index bcaa934..0a8d0b1 100644
--- a/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl.sv
+++ b/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl.sv
@@ -61,7 +61,7 @@
logic z3_wakeup_hw;
logic pwrb_out_int, key0_out_int, key1_out_int, key2_out_int, bat_disable_int, z3_wakeup_int;
logic sysrst_ctrl_combo_intr, sysrst_ctrl_key_intr;
- logic ulp_wakeup_int;
+ logic ulp_wakeup_pulse_int;
//Always-on pins
assign cio_ec_rst_out_l_en_o = 1'b1;
@@ -99,6 +99,8 @@
sysrst_ctrl_reg_top u_reg (
.clk_i,
.rst_ni,
+ .clk_aon_i,
+ .rst_aon_ni,
.tl_i,
.tl_o,
.reg2hw,
@@ -109,8 +111,6 @@
//Instantiate the autoblock module
sysrst_ctrl_autoblock u_autoblock (
- .clk_i,
- .rst_ni,
.clk_aon_i,
.rst_aon_ni,
.pwrb_int_i(pwrb_int),
@@ -127,8 +127,6 @@
//Instantiate the ULP module
sysrst_ctrl_ulp u_ulp (
- .clk_i,
- .rst_ni,
.clk_aon_i,
.rst_aon_ni,
.pwrb_int_i(pwrb_int),
@@ -139,14 +137,12 @@
.ulp_pwrb_debounce_ctl_i(reg2hw.ulp_pwrb_debounce_ctl),
.ulp_ctl_i(reg2hw.ulp_ctl),
.ulp_status_o(hw2reg.ulp_status),
- .ulp_wakeup_o(ulp_wakeup_int),
+ .ulp_wakeup_pulse_o(ulp_wakeup_pulse_int),
.z3_wakeup_hw_o(z3_wakeup_hw)
);
//Instantiate the pin inversion module
sysrst_ctrl_inv u_inversion (
- .clk_aon_i,
- .rst_aon_ni,
.cio_pwrb_in_i,
.cio_key0_in_i,
.cio_key1_in_i,
@@ -178,8 +174,6 @@
sysrst_ctrl_pin u_pin_vis_ovd (
.clk_i,
.rst_ni,
- .clk_aon_i,
- .rst_aon_ni,
.cio_pwrb_in_i,
.cio_key0_in_i,
.cio_key1_in_i,
@@ -249,10 +243,11 @@
.ec_rst_l_hw_o(ec_rst_l_hw)
);
+ // TODO: does ulp_wakeup_pulse_int have to be on the AON domain or not?
// GSC wakeup signal to pwrmgr
// see #6323
assign gsc_wk_o = reg2hw.wk_status.q;
- assign hw2reg.wk_status.de = ulp_wakeup_int ||
+ assign hw2reg.wk_status.de = ulp_wakeup_pulse_int ||
sysrst_ctrl_combo_intr || sysrst_ctrl_key_intr;
assign hw2reg.wk_status.d = 1'b1;
diff --git a/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_autoblock.sv b/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_autoblock.sv
index 6d6a566..e1afb27 100644
--- a/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_autoblock.sv
+++ b/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_autoblock.sv
@@ -7,8 +7,6 @@
module sysrst_ctrl_autoblock import sysrst_ctrl_reg_pkg::*; (
input clk_aon_i,
input rst_aon_ni,
- input clk_i,
- input rst_ni,
input pwrb_int_i,
input key0_int_i,
@@ -24,116 +22,9 @@
output key2_out_hw_o
);
- logic cfg_auto_block_en;
- logic load_auto_block_timer;
- logic [15:0] cfg_auto_block_timer;
- logic [15:0] cfg_auto_block_timer_d;
- logic cfg_key0_o_sel;
- logic cfg_key1_o_sel;
- logic cfg_key2_o_sel;
- logic cfg_key0_o_q;
- logic cfg_key1_o_q;
- logic cfg_key2_o_q;
-
logic ab_cond_met;
logic pwrb_int;
- //unused_ means no connect
- logic unused_auto_block_enable;
-
- //synchronize between cfg(24MHz) and always-on(200KHz)
- prim_flop_2sync # (
- .Width(1)
- ) u_cfg_auto_block_en (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(auto_block_debounce_ctl_i.auto_block_enable.q),
- .q_o(cfg_auto_block_en)
- );
-
- assign unused_auto_block_enable = auto_block_debounce_ctl_i.auto_block_enable.qe;
-
- prim_fifo_async #(
- .Width(16),
- .Depth(2)
- ) u_cfg_auto_block_timer (
- .clk_wr_i (clk_i),
- .rst_wr_ni (rst_ni),
- .wvalid_i (auto_block_debounce_ctl_i.debounce_timer.qe),
- .wready_o (),
- .wdata_i (auto_block_debounce_ctl_i.debounce_timer.q),
- .wdepth_o (),
-
- .clk_rd_i (clk_aon_i),
- .rst_rd_ni (rst_aon_ni),
- .rvalid_o (load_auto_block_timer),
- .rready_i (1'b1),
- .rdata_o (cfg_auto_block_timer_d),
- .rdepth_o ()
- );
-
- always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin: u_cfg_auto_block_timer_reg
- if (!rst_aon_ni) begin
- cfg_auto_block_timer <= '0;
- end else if (load_auto_block_timer) begin
- cfg_auto_block_timer <= cfg_auto_block_timer_d;
- end
- end
-
- prim_flop_2sync # (
- .Width(1)
- ) u_cfg_key0_o_sel (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(auto_block_out_ctl_i.key0_out_sel.q),
- .q_o(cfg_key0_o_sel)
- );
-
- prim_flop_2sync # (
- .Width(1)
- ) u_cfg_key1_o_sel (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(auto_block_out_ctl_i.key1_out_sel.q),
- .q_o(cfg_key1_o_sel)
- );
-
- prim_flop_2sync # (
- .Width(1)
- ) u_cfg_key2_o_sel (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(auto_block_out_ctl_i.key2_out_sel.q),
- .q_o(cfg_key2_o_sel)
- );
-
- prim_flop_2sync # (
- .Width(1)
- ) u_cfg_key0_o_q (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(auto_block_out_ctl_i.key0_out_value.q),
- .q_o(cfg_key0_o_q)
- );
-
- prim_flop_2sync # (
- .Width(1)
- ) u_cfg_key1_o_q (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(auto_block_out_ctl_i.key1_out_value.q),
- .q_o(cfg_key1_o_q)
- );
-
- prim_flop_2sync # (
- .Width(1)
- ) u_cfg_key2_o_q (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(auto_block_out_ctl_i.key2_out_value.q),
- .q_o(cfg_key2_o_q)
- );
-
//synchronize between GPIO and always-on(200KHz)
prim_flop_2sync # (
.Width(1)
@@ -150,16 +41,19 @@
.clk_aon_i,
.rst_aon_ni,
.trigger_i(pwrb_int),
- .cfg_timer_i(cfg_auto_block_timer),
+ .cfg_timer_i(auto_block_debounce_ctl_i.debounce_timer.q),
.cfg_l2h_en_i(1'b0),
- .cfg_h2l_en_i(cfg_auto_block_en),
+ .cfg_h2l_en_i(auto_block_debounce_ctl_i.auto_block_enable.q),
.timer_l2h_cond_met(),
.timer_h2l_cond_met(ab_cond_met)
);
assign pwrb_out_hw_o = pwrb_int;
- assign key0_out_hw_o = (ab_cond_met & cfg_key0_o_sel) ? cfg_key0_o_q : key0_int_i;
- assign key1_out_hw_o = (ab_cond_met & cfg_key1_o_sel) ? cfg_key1_o_q : key1_int_i;
- assign key2_out_hw_o = (ab_cond_met & cfg_key2_o_sel) ? cfg_key2_o_q : key2_int_i;
+ assign key0_out_hw_o = (ab_cond_met & auto_block_out_ctl_i.key0_out_sel.q) ?
+ auto_block_out_ctl_i.key0_out_value.q : key0_int_i;
+ assign key1_out_hw_o = (ab_cond_met & auto_block_out_ctl_i.key1_out_sel.q) ?
+ auto_block_out_ctl_i.key1_out_value.q : key1_int_i;
+ assign key2_out_hw_o = (ab_cond_met & auto_block_out_ctl_i.key2_out_sel.q) ?
+ auto_block_out_ctl_i.key2_out_value.q : key2_int_i;
endmodule
diff --git a/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_combo.sv b/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_combo.sv
index b75a897..1c6000c 100644
--- a/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_combo.sv
+++ b/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_combo.sv
@@ -31,28 +31,8 @@
output ec_rst_l_hw_o
);
- //There are four possible combos
- //Each key combo can select different triggers
- logic [NumCombo-1:0] cfg_key0_in_sel_com;
- logic [NumCombo-1:0] cfg_key1_in_sel_com;
- logic [NumCombo-1:0] cfg_key2_in_sel_com;
- logic [NumCombo-1:0] cfg_pwrb_in_sel_com;
- logic [NumCombo-1:0] cfg_ac_present_sel_com;
-
- logic [31:0] cfg_combo_timer [NumCombo];
- logic [15:0] cfg_debounce_timer;
-
- logic [NumCombo-1:0] load_combo_timer;
- logic load_debounce_timer;
-
- logic [31:0] cfg_combo_timer_d [NumCombo];
- logic [15:0] cfg_debounce_timer_d;
-
- logic [NumCombo-1:0] cfg_bat_disable_com;
- logic [NumCombo-1:0] cfg_intr_com;
- logic [NumCombo-1:0] cfg_ec_rst_com;
- logic [NumCombo-1:0] cfg_gsc_rst_com;
-
+ // There are four possible combos
+ // Each key combo can select different triggers
logic pwrb_int;
logic key0_int, key1_int, key2_int;
logic ac_present_int;
@@ -64,12 +44,12 @@
logic [NumCombo-1:0] combo_bat_disable;
logic [NumCombo-1:0] combo_intr_pulse;
+ logic [NumCombo-1:0] combo_intr_pulse_synced;
logic [NumCombo-1:0] combo_ec_rst_l;
logic [NumCombo-1:0] combo_gsc_rst;
logic ec_rst_l_int;
- logic combo0_h2l_intr, combo1_h2l_intr, combo2_h2l_intr, combo3_h2l_intr;
//synchronize between GPIO and always-on(200KHz)
prim_flop_2sync # (
@@ -81,148 +61,6 @@
.q_o(ec_rst_l_int)
);
- //synchronize between cfg(24MHz) and always-on(200KHz)
- for (genvar k = 0 ; k < NumCombo ; k++) begin : gen_com_sel
- prim_flop_2sync # (
- .Width(1)
- ) u_cfg_com_sel_key0 (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(com_sel_ctl_i[k].key0_in_sel.q),
- .q_o(cfg_key0_in_sel_com[k])
- );
-
- prim_flop_2sync # (
- .Width(1)
- ) u_cfg_com_sel_key1 (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(com_sel_ctl_i[k].key1_in_sel.q),
- .q_o(cfg_key1_in_sel_com[k])
- );
-
- prim_flop_2sync # (
- .Width(1)
- ) u_cfg_com_sel_key2 (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(com_sel_ctl_i[k].key2_in_sel.q),
- .q_o(cfg_key2_in_sel_com[k])
- );
-
- prim_flop_2sync # (
- .Width(1)
- ) u_cfg_com_sel_pwrb (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(com_sel_ctl_i[k].pwrb_in_sel.q),
- .q_o(cfg_pwrb_in_sel_com[k])
- );
-
- prim_flop_2sync # (
- .Width(1)
- ) u_cfg_com_sel_ac_present (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(com_sel_ctl_i[k].ac_present_sel.q),
- .q_o(cfg_ac_present_sel_com[k])
- );
- end
-
- for (genvar k = 0 ; k < NumCombo ; k++) begin : gen_com_det
- prim_fifo_async #(
- .Width(32),
- .Depth(2)
- ) u_cfg_combo_timer (
- .clk_wr_i (clk_i),
- .rst_wr_ni (rst_ni),
- .wvalid_i (com_det_ctl_i[k].qe),
- .wready_o (),
- .wdata_i (com_det_ctl_i[k].q),
- .wdepth_o (),
-
- .clk_rd_i (clk_aon_i),
- .rst_rd_ni (rst_aon_ni),
- .rvalid_o (load_combo_timer[k]),
- .rready_i (1'b1),
- .rdata_o (cfg_combo_timer_d[k]),
- .rdepth_o ()
- );
-
- always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin: i_cfg_combo_timer_reg
- if (!rst_aon_ni) begin
- cfg_combo_timer[k] <= '0;
- end else if (load_combo_timer[k]) begin
- cfg_combo_timer[k] <= cfg_combo_timer_d[k];
- end
- end
- end
-
- prim_fifo_async #(
- .Width(16),
- .Depth(2)
- ) u_cfg_debounce_timer (
- .clk_wr_i (clk_i),
- .rst_wr_ni (rst_ni),
- .wvalid_i (key_intr_debounce_ctl_i.qe),
- .wready_o (),
- .wdata_i (key_intr_debounce_ctl_i.q),
- .wdepth_o (),
-
- .clk_rd_i (clk_aon_i),
- .rst_rd_ni (rst_aon_ni),
- .rvalid_o (load_debounce_timer),
- .rready_i (1'b1),
- .rdata_o (cfg_debounce_timer_d),
- .rdepth_o ()
- );
-
- always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin: i_cfg_debounce_timer_reg
- if (!rst_aon_ni) begin
- cfg_debounce_timer <= '0;
- end else if (load_debounce_timer) begin
- cfg_debounce_timer <= cfg_debounce_timer_d;
- end
- end
-
- for (genvar k = 0 ; k < NumCombo ; k++) begin : gen_com_out
- prim_flop_2sync # (
- .Width(1)
- ) u_cfg_com_bat_disable (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(com_out_ctl_i[k].bat_disable.q),
- .q_o(cfg_bat_disable_com[k])
- );
-
- prim_flop_2sync # (
- .Width(1)
- ) u_cfg_com_intr (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(com_out_ctl_i[k].interrupt.q),
- .q_o(cfg_intr_com[k])
- );
-
- prim_flop_2sync # (
- .Width(1)
- ) u_cfg_com_ec_rst (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(com_out_ctl_i[k].ec_rst.q),
- .q_o(cfg_ec_rst_com[k])
- );
-
- prim_flop_2sync # (
- .Width(1)
- ) u_cfg_com_gsc_rst (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(com_out_ctl_i[k].gsc_rst.q),
- .q_o(cfg_gsc_rst_com[k])
- );
- end
-
//synchronize between GPIO and always-on(200KHz)
prim_flop_2sync # (
.Width(1)
@@ -269,14 +107,14 @@
.q_o(ac_present_int)
);
- //generate the trigger for each combo
for (genvar k = 0 ; k < NumCombo ; k++) begin : gen_combo_trigger
+ // generate the trigger for each combo
sysrst_ctrl_combotrg u_combo_trg (
- .cfg_in0_sel(cfg_pwrb_in_sel_com[k]),
- .cfg_in1_sel(cfg_key0_in_sel_com[k]),
- .cfg_in2_sel(cfg_key1_in_sel_com[k]),
- .cfg_in3_sel(cfg_key2_in_sel_com[k]),
- .cfg_in4_sel(cfg_ac_present_sel_com[k]),
+ .cfg_in0_sel(com_sel_ctl_i[k].pwrb_in_sel.q),
+ .cfg_in1_sel(com_sel_ctl_i[k].key0_in_sel.q),
+ .cfg_in2_sel(com_sel_ctl_i[k].key1_in_sel.q),
+ .cfg_in3_sel(com_sel_ctl_i[k].key2_in_sel.q),
+ .cfg_in4_sel(com_sel_ctl_i[k].ac_present_sel.q),
.in0(pwrb_int),
.in1(key0_int),
.in2(key1_int),
@@ -285,39 +123,36 @@
.trigger_h_o(trigger_h[k]),
.trigger_l_o(trigger_l[k])
);
- assign cfg_combo_en[k] = cfg_pwrb_in_sel_com[k] | cfg_key0_in_sel_com[k] |
- cfg_key1_in_sel_com[k] | cfg_key2_in_sel_com[k] |
- cfg_ac_present_sel_com[k];
- end
- //Instantiate the combo detection state machine
- for (genvar k = 0 ; k < NumCombo ; k++) begin : gen_combofsm
+ assign cfg_combo_en[k] = com_sel_ctl_i[k].pwrb_in_sel.q |
+ com_sel_ctl_i[k].key0_in_sel.q |
+ com_sel_ctl_i[k].key1_in_sel.q |
+ com_sel_ctl_i[k].key2_in_sel.q |
+ com_sel_ctl_i[k].ac_present_sel.q;
+
+ //Instantiate the combo detection state machine
sysrst_ctrl_combofsm # (
.TIMER1BIT(16),
.TIMER2BIT(32)
) u_combo_fsm (
- .clk_aon_i(clk_aon_i),
- .rst_aon_ni(rst_aon_ni),
+ .clk_aon_i,
+ .rst_aon_ni,
.trigger_h_i(trigger_h[k]),
.trigger_l_i(trigger_l[k]),
- .cfg_timer1_i(cfg_debounce_timer),
- .cfg_timer2_i(cfg_combo_timer[k]),
+ .cfg_timer1_i(key_intr_debounce_ctl_i.q),
+ .cfg_timer2_i(com_det_ctl_i[k].q),
.cfg_h2l_en_i(cfg_combo_en[k]),
.timer_h2l_cond_met(combo_det[k])
);
- end
- //Instantiate the combo action module
- for (genvar k = 0 ; k < NumCombo ; k++) begin : gen_combo_act
+ //Instantiate the combo action module
sysrst_ctrl_comboact u_combo_act (
- .clk_aon_i(clk_aon_i),
- .rst_aon_ni(rst_aon_ni),
- .clk_i(clk_i),
- .rst_ni(rst_ni),
- .cfg_intr_en(cfg_intr_com[k]),
- .cfg_bat_disable_en(cfg_bat_disable_com[k]),
- .cfg_ec_rst_en(cfg_ec_rst_com[k]),
- .cfg_gsc_rst_en(cfg_gsc_rst_com[k]),
+ .clk_aon_i,
+ .rst_aon_ni,
+ .cfg_intr_en(com_out_ctl_i[k].interrupt.q),
+ .cfg_bat_disable_en(com_out_ctl_i[k].bat_disable.q),
+ .cfg_ec_rst_en(com_out_ctl_i[k].ec_rst.q),
+ .cfg_gsc_rst_en(com_out_ctl_i[k].gsc_rst.q),
.combo_det(combo_det[k]),
.ec_rst_l_i(ec_rst_l_int),
.ec_rst_ctl_i(ec_rst_ctl_i),
@@ -326,67 +161,34 @@
.gsc_rst_o(combo_gsc_rst[k]),
.ec_rst_l_o(combo_ec_rst_l[k])
);
+
+ // Synchronize IRQ pulsefrom 200KHz always-onclock to 24MHz cfg clock
+ prim_pulse_sync u_combo0_intr (
+ .clk_src_i (clk_aon_i),
+ .clk_dst_i (clk_i),
+ .rst_src_ni (rst_aon_ni),
+ .rst_dst_ni (rst_ni),
+ .src_pulse_i (combo_intr_pulse[k]),
+ .dst_pulse_o (combo_intr_pulse_synced[k])
+ );
end
- //bat_disable
- //If any combo triggers bat_disable, assert the signal
+ // bat_disable
+ // If any combo triggers bat_disable, assert the signal
assign bat_disable_hw_o = |(combo_bat_disable);
- //If any combo triggers GSC or EC RST(active low), assert the signal
+ // If any combo triggers GSC or EC RST(active low), assert the signal
assign gsc_rst_o = |(combo_gsc_rst);
assign ec_rst_l_hw_o = &(combo_ec_rst_l);
- //Synchronize from 200KHz always-onclock to 24MHz cfg clock
- prim_pulse_sync u_combo0_intr (
- .clk_src_i (clk_aon_i),
- .clk_dst_i (clk_i),
- .rst_src_ni (rst_aon_ni),
- .rst_dst_ni (rst_ni),
- .src_pulse_i (combo_intr_pulse[0]),
- .dst_pulse_o (combo0_h2l_intr)
- );
+ // Write interrupt status registers using the synced IRQ pulses.
+ assign {combo_intr_status_o.combo3_h2l.de,
+ combo_intr_status_o.combo2_h2l.de,
+ combo_intr_status_o.combo1_h2l.de,
+ combo_intr_status_o.combo0_h2l.de} = combo_intr_pulse_synced;
- assign combo_intr_status_o.combo0_h2l.de = combo0_h2l_intr;
+ assign sysrst_ctrl_combo_intr_o = |combo_intr_pulse_synced;
- prim_pulse_sync u_combo1_intr (
- .clk_src_i (clk_aon_i),
- .clk_dst_i (clk_i),
- .rst_src_ni (rst_aon_ni),
- .rst_dst_ni (rst_ni),
- .src_pulse_i (combo_intr_pulse[1]),
- .dst_pulse_o (combo1_h2l_intr)
- );
-
- assign combo_intr_status_o.combo1_h2l.de = combo1_h2l_intr;
-
- prim_pulse_sync u_combo2_intr (
- .clk_src_i (clk_aon_i),
- .clk_dst_i (clk_i),
- .rst_src_ni (rst_aon_ni),
- .rst_dst_ni (rst_ni),
- .src_pulse_i (combo_intr_pulse[2]),
- .dst_pulse_o (combo2_h2l_intr)
- );
-
- assign combo_intr_status_o.combo2_h2l.de = combo2_h2l_intr;
-
- prim_pulse_sync u_combo3_intr (
- .clk_src_i (clk_aon_i),
- .clk_dst_i (clk_i),
- .rst_src_ni (rst_aon_ni),
- .rst_dst_ni (rst_ni),
- .src_pulse_i (combo_intr_pulse[3]),
- .dst_pulse_o (combo3_h2l_intr)
- );
-
- assign combo_intr_status_o.combo3_h2l.de = combo3_h2l_intr;
-
- assign sysrst_ctrl_combo_intr_o = combo0_h2l_intr |
- combo1_h2l_intr |
- combo2_h2l_intr |
- combo3_h2l_intr;
-
- //To write into interrupt status register
assign combo_intr_status_o.combo0_h2l.d = 1'b1;
assign combo_intr_status_o.combo1_h2l.d = 1'b1;
assign combo_intr_status_o.combo2_h2l.d = 1'b1;
diff --git a/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_comboact.sv b/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_comboact.sv
index 4d2810f..44158e1 100644
--- a/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_comboact.sv
+++ b/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_comboact.sv
@@ -7,8 +7,6 @@
module sysrst_ctrl_comboact import sysrst_ctrl_reg_pkg::*; (
input clk_aon_i,
input rst_aon_ni,
- input clk_i,
- input rst_ni,
input cfg_intr_en,
input cfg_bat_disable_en,
@@ -25,10 +23,6 @@
output ec_rst_l_o
);
- logic [15:0] cfg_ec_rst_timer;
- logic load_ec_rst_timer;
- logic [15:0] cfg_ec_rst_timer_d;
-
logic combo_det_q;
logic combo_gsc_pulse;
logic combo_bat_disable_pulse;
@@ -71,34 +65,6 @@
assign combo_intr_pulse = cfg_intr_en && (combo_det_q == 1'b0) && (combo_det == 1'b1);
//ec_rst_logic
- //synchronize between cfg(24MHz) and always-on(200KHz)
- prim_fifo_async #(
- .Width(16),
- .Depth(2)
- ) i_cfg_ec_rst_pulse (
- .clk_wr_i (clk_i),
- .rst_wr_ni (rst_ni),
- .wvalid_i (ec_rst_ctl_i.qe),
- .wready_o (),
- .wdata_i (ec_rst_ctl_i.q),
- .wdepth_o (),
-
- .clk_rd_i (clk_aon_i),
- .rst_rd_ni (rst_aon_ni),
- .rvalid_o (load_ec_rst_timer),
- .rready_i (1'b1),
- .rdata_o (cfg_ec_rst_timer_d),
- .rdepth_o ()
- );
-
- always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin: u_cfg_ec_rst_timer_reg
- if (!rst_aon_ni) begin
- cfg_ec_rst_timer <= '0;
- end else if (load_ec_rst_timer) begin
- cfg_ec_rst_timer <= cfg_ec_rst_timer_d;
- end
- end
-
always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin: u_ec_rst_l_int
if (!rst_aon_ni) begin
ec_rst_l_int <= 1'b1;//active low signal
@@ -127,7 +93,7 @@
assign timer_cnt_en = (ec_rst_l_q == 1'b0);
- assign timer_cnt_clr = (ec_rst_l_q == 1'b0) && (timer_cnt_q == cfg_ec_rst_timer);
+ assign timer_cnt_clr = (ec_rst_l_q == 1'b0) && (timer_cnt_q == ec_rst_ctl_i.q);
assign timer_cnt_d = (timer_cnt_en) ? timer_cnt_q + 1'b1 : timer_cnt_q;
diff --git a/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_inv.sv b/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_inv.sv
index 6ef73ad..62af05f 100644
--- a/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_inv.sv
+++ b/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_inv.sv
@@ -6,9 +6,6 @@
//
module sysrst_ctrl_inv import sysrst_ctrl_reg_pkg::*; (
- input clk_aon_i,
- input rst_aon_ni,
-
input cio_pwrb_in_i,
input cio_key0_in_i,
input cio_key1_in_i,
@@ -41,140 +38,18 @@
);
- logic cfg_pwrb_i_inv;
- logic cfg_key0_i_inv;
- logic cfg_key1_i_inv;
- logic cfg_key2_i_inv;
- logic cfg_ac_present_i_inv;
- logic cfg_lid_open_i_inv;
- logic cfg_pwrb_o_inv;
- logic cfg_key0_o_inv;
- logic cfg_key1_o_inv;
- logic cfg_key2_o_inv;
- logic cfg_bat_disable_o_inv;
- logic cfg_z3_wakeup_o_inv;
+ assign cio_pwrb_out_o = key_invert_ctl_i.pwrb_out.q ^ pwrb_out_int_i;
+ assign cio_key0_out_o = key_invert_ctl_i.key0_out.q ^ key0_out_int_i;
+ assign cio_key1_out_o = key_invert_ctl_i.key1_out.q ^ key1_out_int_i;
+ assign cio_key2_out_o = key_invert_ctl_i.key2_out.q ^ key2_out_int_i;
+ assign cio_bat_disable_o = key_invert_ctl_i.bat_disable.q ^ bat_disable_int_i;
+ assign cio_z3_wakeup_o = key_invert_ctl_i.z3_wakeup.q ^ z3_wakeup_int_i;
- //synchronize between cfg(24MHz) and always-on(200KHz)
- prim_flop_2sync # (
- .Width(1)
- ) u_cfg_pwrb_i_inv (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(key_invert_ctl_i.pwrb_in.q),
- .q_o(cfg_pwrb_i_inv)
- );
-
- prim_flop_2sync # (
- .Width(1)
- ) u_cfg_key0_i_inv (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(key_invert_ctl_i.key0_in.q),
- .q_o(cfg_key0_i_inv)
- );
-
- prim_flop_2sync # (
- .Width(1)
- ) u_cfg_key1_i_inv (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(key_invert_ctl_i.key1_in.q),
- .q_o(cfg_key1_i_inv)
- );
-
- prim_flop_2sync # (
- .Width(1)
- ) u_cfg_key2_i_inv (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(key_invert_ctl_i.key2_in.q),
- .q_o(cfg_key2_i_inv)
- );
-
- prim_flop_2sync # (
- .Width(1)
- ) u_cfg_ac_present_i_inv (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(key_invert_ctl_i.ac_present.q),
- .q_o(cfg_ac_present_i_inv)
- );
-
- prim_flop_2sync # (
- .Width(1)
- ) u_cfg_lid_open_i_inv (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(key_invert_ctl_i.lid_open.q),
- .q_o(cfg_lid_open_i_inv)
- );
-
- prim_flop_2sync # (
- .Width(1)
- ) u_cfg_pwrb_o_inv (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(key_invert_ctl_i.pwrb_out.q),
- .q_o(cfg_pwrb_o_inv)
- );
-
- prim_flop_2sync # (
- .Width(1)
- ) u_cfg_key0_o_inv (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(key_invert_ctl_i.key0_out.q),
- .q_o(cfg_key0_o_inv)
- );
-
- prim_flop_2sync # (
- .Width(1)
- ) u_cfg_key1_o_inv (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(key_invert_ctl_i.key1_out.q),
- .q_o(cfg_key1_o_inv)
- );
-
- prim_flop_2sync # (
- .Width(1)
- ) u_cfg_key2_o_inv (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(key_invert_ctl_i.key2_out.q),
- .q_o(cfg_key2_o_inv)
- );
-
- prim_flop_2sync # (
- .Width(1)
- ) u_cfg_bat_disable_o_inv (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(key_invert_ctl_i.bat_disable.q),
- .q_o(cfg_bat_disable_o_inv)
- );
-
- prim_flop_2sync # (
- .Width(1)
- ) u_cfg_z3_wakeup_o_inv (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(key_invert_ctl_i.z3_wakeup.q),
- .q_o(cfg_z3_wakeup_o_inv)
- );
-
- assign cio_pwrb_out_o = cfg_pwrb_o_inv ? ~pwrb_out_int_i : pwrb_out_int_i;
- assign cio_key0_out_o = cfg_key0_o_inv ? ~key0_out_int_i : key0_out_int_i;
- assign cio_key1_out_o = cfg_key1_o_inv ? ~key1_out_int_i : key1_out_int_i;
- assign cio_key2_out_o = cfg_key2_o_inv ? ~key2_out_int_i : key2_out_int_i;
- assign cio_bat_disable_o = cfg_bat_disable_o_inv ? ~bat_disable_int_i : bat_disable_int_i;
- assign cio_z3_wakeup_o = cfg_z3_wakeup_o_inv ? ~z3_wakeup_int_i : z3_wakeup_int_i;
-
- assign pwrb_int_o = cfg_pwrb_i_inv ? ~cio_pwrb_in_i : cio_pwrb_in_i;
- assign key0_int_o = cfg_key0_i_inv ? ~cio_key0_in_i : cio_key0_in_i;
- assign key1_int_o = cfg_key1_i_inv ? ~cio_key1_in_i : cio_key1_in_i;
- assign key2_int_o = cfg_key2_i_inv ? ~cio_key2_in_i : cio_key2_in_i;
- assign ac_present_int_o = cfg_ac_present_i_inv ? ~cio_ac_present_i : cio_ac_present_i;
- assign lid_open_int_o = cfg_lid_open_i_inv ? ~cio_lid_open_i : cio_lid_open_i;
+ assign pwrb_int_o = key_invert_ctl_i.pwrb_in.q ^ cio_pwrb_in_i;
+ assign key0_int_o = key_invert_ctl_i.key0_in.q ^ cio_key0_in_i;
+ assign key1_int_o = key_invert_ctl_i.key1_in.q ^ cio_key1_in_i;
+ assign key2_int_o = key_invert_ctl_i.key2_in.q ^ cio_key2_in_i;
+ assign ac_present_int_o = key_invert_ctl_i.ac_present.q ^ cio_ac_present_i;
+ assign lid_open_int_o = key_invert_ctl_i.lid_open.q ^ cio_lid_open_i;
endmodule
diff --git a/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_keyfsm.sv b/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_keyfsm.sv
index ffc6a7c..a21c54e 100644
--- a/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_keyfsm.sv
+++ b/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_keyfsm.sv
@@ -5,12 +5,12 @@
// Description sysrst_ctrl key press and release FSM module
module sysrst_ctrl_keyfsm #(
- parameter int unsigned TIMERBIT = 16
+ parameter int unsigned TimerWidth = 16
) (
input clk_aon_i,
input rst_aon_ni,
input trigger_i,
- input [TIMERBIT-1:0] cfg_timer_i,
+ input [TimerWidth-1:0] cfg_timer_i,
input cfg_l2h_en_i,
input cfg_h2l_en_i,
output logic timer_l2h_cond_met,
@@ -22,7 +22,7 @@
logic trigger_h2l, trigger_l2h, trigger_l2l, trigger_h2h;
//logic trigger_tgl, trigger_sty;
- logic [TIMERBIT-1:0] timer_cnt_d, timer_cnt_q;
+ logic [TimerWidth-1:0] timer_cnt_d, timer_cnt_q;
logic timer_cnt_clr, timer_cnt_en;
always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin: p_trigger_reg
diff --git a/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_keyintr.sv b/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_keyintr.sv
index eb7b227..e2aae36 100644
--- a/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_keyintr.sv
+++ b/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_keyintr.sv
@@ -25,182 +25,10 @@
);
- logic cfg_pwrb_in_h2l;
- logic cfg_key0_in_h2l;
- logic cfg_key1_in_h2l;
- logic cfg_key2_in_h2l;
- logic cfg_ac_present_h2l;
- logic cfg_ec_rst_l_h2l;
- logic cfg_pwrb_in_l2h;
- logic cfg_key0_in_l2h;
- logic cfg_key1_in_l2h;
- logic cfg_key2_in_l2h;
- logic cfg_ac_present_l2h;
- logic cfg_ec_rst_l_l2h;
-
- logic [15:0] cfg_key_intr_timer;
- logic load_key_intr_timer;
- logic [15:0] cfg_key_intr_timer_d;
-
logic pwrb_int;
logic key0_int, key1_int, key2_int;
logic ac_present_int;
logic ec_rst_l_int;
- logic pwrb_intr_h2l_det, pwrb_intr_h2l_det_q, pwrb_intr_h2l_pulse;
- logic pwrb_intr_l2h_det, pwrb_intr_l2h_det_q, pwrb_intr_l2h_pulse;
- logic key0_intr_h2l_det, key0_intr_h2l_det_q, key0_intr_h2l_pulse;
- logic key0_intr_l2h_det, key0_intr_l2h_det_q, key0_intr_l2h_pulse;
- logic key1_intr_h2l_det, key1_intr_h2l_det_q, key1_intr_h2l_pulse;
- logic key1_intr_l2h_det, key1_intr_l2h_det_q, key1_intr_l2h_pulse;
- logic key2_intr_h2l_det, key2_intr_h2l_det_q, key2_intr_h2l_pulse;
- logic key2_intr_l2h_det, key2_intr_l2h_det_q, key2_intr_l2h_pulse;
- logic ac_present_intr_h2l_det, ac_present_intr_h2l_det_q, ac_present_intr_h2l_pulse;
- logic ac_present_intr_l2h_det, ac_present_intr_l2h_det_q, ac_present_intr_l2h_pulse;
- logic ec_rst_l_intr_h2l_det, ec_rst_l_intr_h2l_det_q, ec_rst_l_intr_h2l_pulse;
- logic ec_rst_l_intr_l2h_det, ec_rst_l_intr_l2h_det_q, ec_rst_l_intr_l2h_pulse;
-
- logic pwrb_h2l_intr, pwrb_l2h_intr;
- logic key0_in_h2l_intr, key0_in_l2h_intr;
- logic key1_in_h2l_intr, key1_in_l2h_intr;
- logic key2_in_h2l_intr, key2_in_l2h_intr;
- logic ac_present_h2l_intr, ac_present_l2h_intr;
- logic ec_rst_l_h2l_intr, ec_rst_l_l2h_intr;
-
- //synchronize between cfg(24MHz) and always-on(200KHz)
- prim_flop_2sync # (
- .Width(1)
- ) u_cfg_pwrb_in_h2l (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(key_intr_ctl_i.pwrb_in_h2l.q),
- .q_o(cfg_pwrb_in_h2l)
- );
-
- prim_flop_2sync # (
- .Width(1)
- ) u_cfg_key0_in_h2l (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(key_intr_ctl_i.key0_in_h2l.q),
- .q_o(cfg_key0_in_h2l)
- );
-
- prim_flop_2sync # (
- .Width(1)
- ) u_cfg_key1_in_h2l (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(key_intr_ctl_i.key1_in_h2l.q),
- .q_o(cfg_key1_in_h2l)
- );
-
- prim_flop_2sync # (
- .Width(1)
- ) u_cfg_key2_in_h2l (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(key_intr_ctl_i.key2_in_h2l.q),
- .q_o(cfg_key2_in_h2l)
- );
-
- prim_flop_2sync # (
- .Width(1)
- ) u_cfg_ac_present_h2l (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(key_intr_ctl_i.ac_present_h2l.q),
- .q_o(cfg_ac_present_h2l)
- );
-
- prim_flop_2sync # (
- .Width(1)
- ) u_cfg_ec_rst_l_h2l (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(key_intr_ctl_i.ec_rst_l_h2l.q),
- .q_o(cfg_ec_rst_l_h2l)
- );
-
- prim_flop_2sync # (
- .Width(1)
- ) u_cfg_pwrb_in_l2h (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(key_intr_ctl_i.pwrb_in_l2h.q),
- .q_o(cfg_pwrb_in_l2h)
- );
-
- prim_flop_2sync # (
- .Width(1)
- ) u_cfg_key0_in_l2h (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(key_intr_ctl_i.key0_in_l2h.q),
- .q_o(cfg_key0_in_l2h)
- );
-
- prim_flop_2sync # (
- .Width(1)
- ) u_cfg_key1_in_l2h (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(key_intr_ctl_i.key1_in_l2h.q),
- .q_o(cfg_key1_in_l2h)
- );
-
- prim_flop_2sync # (
- .Width(1)
- ) u_cfg_key2_in_l2h (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(key_intr_ctl_i.key2_in_l2h.q),
- .q_o(cfg_key2_in_l2h)
- );
-
- prim_flop_2sync # (
- .Width(1)
- ) u_cfg_ac_present_l2h (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(key_intr_ctl_i.ac_present_l2h.q),
- .q_o(cfg_ac_present_l2h)
- );
-
- prim_flop_2sync # (
- .Width(1)
- ) u_cfg_ec_rst_l_l2h (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(key_intr_ctl_i.ec_rst_l_l2h.q),
- .q_o(cfg_ec_rst_l_l2h)
- );
-
- prim_fifo_async #(
- .Width(16),
- .Depth(2)
- ) u_cfg_key_intr_timer (
- .clk_wr_i (clk_i),
- .rst_wr_ni (rst_ni),
- .wvalid_i (key_intr_debounce_ctl_i.qe),
- .wready_o (),
- .wdata_i (key_intr_debounce_ctl_i.q),
- .wdepth_o (),
-
- .clk_rd_i (clk_aon_i),
- .rst_rd_ni (rst_aon_ni),
- .rvalid_o (load_key_intr_timer),
- .rready_i (1'b1),
- .rdata_o (cfg_key_intr_timer_d),
- .rdepth_o ()
- );
-
- always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin: p_cfg_key_intr_timer_reg
- if (!rst_aon_ni) begin
- cfg_key_intr_timer <= '0;
- end else if (load_key_intr_timer) begin
- cfg_key_intr_timer <= cfg_key_intr_timer_d;
- end
- end
//synchronize between GPIO and always-on(200KHz)
prim_flop_2sync # (
@@ -257,342 +85,99 @@
.q_o(ec_rst_l_int)
);
- //Instantiate the key state machine
- sysrst_ctrl_keyfsm # (
- .TIMERBIT(16)
- ) u_pwrbintr_fsm (
- .clk_aon_i(clk_aon_i),
- .rst_aon_ni(rst_aon_ni),
- .trigger_i(pwrb_int),
- .cfg_timer_i(cfg_key_intr_timer),
- .cfg_l2h_en_i(cfg_pwrb_in_l2h),
- .cfg_h2l_en_i(cfg_pwrb_in_h2l),
- .timer_l2h_cond_met(pwrb_intr_l2h_det),
- .timer_h2l_cond_met(pwrb_intr_h2l_det)
- );
+ localparam int TimerWidth = 16;
+ localparam int NumKeyIntr = 6;
+ logic [NumKeyIntr-1:0] triggers, l2h_en, h2l_en;
+ assign triggers = {pwrb_int,
+ key0_int,
+ key1_int,
+ key2_int,
+ ac_present_int,
+ ec_rst_l_int};
+ assign l2h_en = {key_intr_ctl_i.pwrb_in_l2h.q,
+ key_intr_ctl_i.key0_in_l2h.q,
+ key_intr_ctl_i.key1_in_l2h.q,
+ key_intr_ctl_i.key2_in_l2h.q,
+ key_intr_ctl_i.ac_present_l2h.q,
+ key_intr_ctl_i.ec_rst_l_l2h.q};
+ assign h2l_en = {key_intr_ctl_i.pwrb_in_h2l.q,
+ key_intr_ctl_i.key0_in_h2l.q,
+ key_intr_ctl_i.key1_in_h2l.q,
+ key_intr_ctl_i.key2_in_h2l.q,
+ key_intr_ctl_i.ac_present_h2l.q,
+ key_intr_ctl_i.ec_rst_l_h2l.q};
- sysrst_ctrl_keyfsm # (
- .TIMERBIT(16)
- ) u_key0intr_fsm (
- .clk_aon_i(clk_aon_i),
- .rst_aon_ni(rst_aon_ni),
- .trigger_i(key0_int),
- .cfg_timer_i(cfg_key_intr_timer),
- .cfg_l2h_en_i(cfg_key0_in_l2h),
- .cfg_h2l_en_i(cfg_key0_in_h2l),
- .timer_l2h_cond_met(key0_intr_l2h_det),
- .timer_h2l_cond_met(key0_intr_h2l_det)
- );
+ logic [NumKeyIntr-1:0] l2h_met_pulse_synced, h2l_met_pulse_synced;
+ for (genvar k = 0; k < NumKeyIntr; k ++) begin : gen_keyfsm
+ // Instantiate the key state machine
+ logic l2h_met_d, h2l_met_d;
+ sysrst_ctrl_keyfsm # (
+ .TimerWidth(TimerWidth)
+ ) u_pwrbintr_fsm (
+ .clk_aon_i,
+ .rst_aon_ni,
+ .trigger_i(triggers[k]),
+ .cfg_timer_i(key_intr_debounce_ctl_i.q),
+ .cfg_l2h_en_i(l2h_en[k]),
+ .cfg_h2l_en_i(h2l_en[k]),
+ .timer_l2h_cond_met(l2h_met_d),
+ .timer_h2l_cond_met(h2l_met_d)
+ );
- sysrst_ctrl_keyfsm # (
- .TIMERBIT(16)
- ) u_key1intr_fsm (
- .clk_aon_i(clk_aon_i),
- .rst_aon_ni(rst_aon_ni),
- .trigger_i(key1_int),
- .cfg_timer_i(cfg_key_intr_timer),
- .cfg_l2h_en_i(cfg_key1_in_l2h),
- .cfg_h2l_en_i(cfg_key1_in_h2l),
- .timer_l2h_cond_met(key1_intr_l2h_det),
- .timer_h2l_cond_met(key1_intr_h2l_det)
- );
-
- sysrst_ctrl_keyfsm # (
- .TIMERBIT(16)
- ) u_key2intr_fsm (
- .clk_aon_i(clk_aon_i),
- .rst_aon_ni(rst_aon_ni),
- .trigger_i(key2_int),
- .cfg_timer_i(cfg_key_intr_timer),
- .cfg_l2h_en_i(cfg_key2_in_l2h),
- .cfg_h2l_en_i(cfg_key2_in_h2l),
- .timer_l2h_cond_met(key2_intr_l2h_det),
- .timer_h2l_cond_met(key2_intr_h2l_det)
- );
-
- sysrst_ctrl_keyfsm # (
- .TIMERBIT(16)
- ) u_ac_presentintr_fsm (
- .clk_aon_i(clk_aon_i),
- .rst_aon_ni(rst_aon_ni),
- .trigger_i(ac_present_int),
- .cfg_timer_i(cfg_key_intr_timer),
- .cfg_l2h_en_i(cfg_ac_present_l2h),
- .cfg_h2l_en_i(cfg_ac_present_h2l),
- .timer_l2h_cond_met(ac_present_intr_l2h_det),
- .timer_h2l_cond_met(ac_present_intr_h2l_det)
- );
-
- sysrst_ctrl_keyfsm # (
- .TIMERBIT(16)
- ) u_ec_rst_lintr_fsm (
- .clk_aon_i(clk_aon_i),
- .rst_aon_ni(rst_aon_ni),
- .trigger_i(ec_rst_l_int),
- .cfg_timer_i(cfg_key_intr_timer),
- .cfg_l2h_en_i(cfg_ec_rst_l_l2h),
- .cfg_h2l_en_i(cfg_ec_rst_l_h2l),
- .timer_l2h_cond_met(ec_rst_l_intr_l2h_det),
- .timer_h2l_cond_met(ec_rst_l_intr_h2l_det)
- );
-
-
- //delay the level signal to generate a pulse
- always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin: p_pwrb_intr_h2l_det
- if (!rst_aon_ni) begin
- pwrb_intr_h2l_det_q <= 1'b0;
- end else begin
- pwrb_intr_h2l_det_q <= pwrb_intr_h2l_det;
+ // generate a pulses for interrupt status CSR
+ logic l2h_met_q, h2l_met_q;
+ always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin : p_pulse_reg
+ if (!rst_aon_ni) begin
+ l2h_met_q <= '0;
+ h2l_met_q <= '0;
+ end else begin
+ l2h_met_q <= l2h_met_d;
+ h2l_met_q <= h2l_met_d;
+ end
end
+
+ logic l2h_met_pulse, h2l_met_pulse;
+ assign l2h_met_pulse = l2h_met_d & ~l2h_met_q;
+ assign h2l_met_pulse = ~h2l_met_d & h2l_met_q;
+
+ prim_pulse_sync u_prim_pulse_sync_l2h (
+ .clk_src_i (clk_aon_i),
+ .rst_src_ni (rst_aon_ni),
+ .src_pulse_i(l2h_met_pulse),
+ .clk_dst_i (clk_i),
+ .rst_dst_ni (rst_ni),
+ .dst_pulse_o(l2h_met_pulse_synced[k])
+ );
+ prim_pulse_sync u_prim_pulse_sync_h2l (
+ .clk_src_i (clk_aon_i),
+ .rst_src_ni (rst_aon_ni),
+ .src_pulse_i(h2l_met_pulse),
+ .clk_dst_i (clk_i),
+ .rst_dst_ni (rst_ni),
+ .dst_pulse_o(h2l_met_pulse_synced[k])
+ );
end
- always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin: p_pwrb_intr_l2h_det
- if (!rst_aon_ni) begin
- pwrb_intr_l2h_det_q <= 1'b0;
- end else begin
- pwrb_intr_l2h_det_q <= pwrb_intr_l2h_det;
- end
- end
+ // Assign to CSRs
+ assign {key_intr_status_o.pwrb_l2h.de,
+ key_intr_status_o.key0_in_l2h.de,
+ key_intr_status_o.key1_in_l2h.de,
+ key_intr_status_o.key2_in_l2h.de,
+ key_intr_status_o.ac_present_l2h.de,
+ key_intr_status_o.ec_rst_l_l2h.de} = l2h_met_pulse_synced;
- always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin: p_key0_intr_h2l_det
- if (!rst_aon_ni) begin
- key0_intr_h2l_det_q <= 1'b0;
- end else begin
- key0_intr_h2l_det_q <= key0_intr_h2l_det;
- end
- end
+ assign {key_intr_status_o.pwrb_h2l.de,
+ key_intr_status_o.key0_in_h2l.de,
+ key_intr_status_o.key1_in_h2l.de,
+ key_intr_status_o.key2_in_h2l.de,
+ key_intr_status_o.ac_present_h2l.de,
+ key_intr_status_o.ec_rst_l_h2l.de} = h2l_met_pulse_synced;
- always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin: p_key0_intr_l2h_det
- if (!rst_aon_ni) begin
- key0_intr_l2h_det_q <= 1'b0;
- end else begin
- key0_intr_l2h_det_q <= key0_intr_l2h_det;
- end
- end
+ // Send out aggregated interrupt pulse
+ assign sysrst_ctrl_key_intr_o = |l2h_met_pulse_synced |
+ |h2l_met_pulse_synced;
- always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin: p_key1_intr_h2l_det
- if (!rst_aon_ni) begin
- key1_intr_h2l_det_q <= 1'b0;
- end else begin
- key1_intr_h2l_det_q <= key1_intr_h2l_det;
- end
- end
-
- always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin: p_key1_intr_l2h_det
- if (!rst_aon_ni) begin
- key1_intr_l2h_det_q <= 1'b0;
- end else begin
- key1_intr_l2h_det_q <= key1_intr_l2h_det;
- end
- end
-
- always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin: p_key2_intr_h2l_det
- if (!rst_aon_ni) begin
- key2_intr_h2l_det_q <= 1'b0;
- end else begin
- key2_intr_h2l_det_q <= key2_intr_h2l_det;
- end
- end
-
- always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin: p_key2_intr_l2h_det
- if (!rst_aon_ni) begin
- key2_intr_l2h_det_q <= 1'b0;
- end else begin
- key2_intr_l2h_det_q <= key2_intr_l2h_det;
- end
- end
-
- always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin: p_ac_present_intr_h2l_det
- if (!rst_aon_ni) begin
- ac_present_intr_h2l_det_q <= 1'b0;
- end else begin
- ac_present_intr_h2l_det_q <= ac_present_intr_h2l_det;
- end
- end
-
- always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin: p_ac_present_intr_l2h_det
- if (!rst_aon_ni) begin
- ac_present_intr_l2h_det_q <= 1'b0;
- end else begin
- ac_present_intr_l2h_det_q <= ac_present_intr_l2h_det;
- end
- end
-
- always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin: p_ec_rst_l_intr_h2l_det
- if (!rst_aon_ni) begin
- ec_rst_l_intr_h2l_det_q <= 1'b0;
- end else begin
- ec_rst_l_intr_h2l_det_q <= ec_rst_l_intr_h2l_det;
- end
- end
-
- always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin: p_ec_rst_l_intr_l2h_det
- if (!rst_aon_ni) begin
- ec_rst_l_intr_l2h_det_q <= 1'b0;
- end else begin
- ec_rst_l_intr_l2h_det_q <= ec_rst_l_intr_l2h_det;
- end
- end
-
- //generate a pulse for interrupt status CSR
- assign pwrb_intr_l2h_pulse = (pwrb_intr_l2h_det_q == 1'b0) && (pwrb_intr_l2h_det == 1'b1);
- assign pwrb_intr_h2l_pulse = (pwrb_intr_h2l_det_q == 1'b1) && (pwrb_intr_h2l_det == 1'b0);
- assign key0_intr_l2h_pulse = (key0_intr_l2h_det_q == 1'b0) && (key0_intr_l2h_det == 1'b1);
- assign key0_intr_h2l_pulse = (key0_intr_h2l_det_q == 1'b1) && (key0_intr_h2l_det == 1'b0);
- assign key1_intr_l2h_pulse = (key1_intr_l2h_det_q == 1'b0) && (key1_intr_l2h_det == 1'b1);
- assign key1_intr_h2l_pulse = (key1_intr_h2l_det_q == 1'b1) && (key1_intr_h2l_det == 1'b0);
- assign key2_intr_l2h_pulse = (key2_intr_l2h_det_q == 1'b0) && (key2_intr_l2h_det == 1'b1);
- assign key2_intr_h2l_pulse = (key2_intr_h2l_det_q == 1'b1) && (key2_intr_h2l_det == 1'b0);
- assign ac_present_intr_l2h_pulse = (ac_present_intr_l2h_det_q == 1'b0) &&
- (ac_present_intr_l2h_det == 1'b1);
- assign ac_present_intr_h2l_pulse = (ac_present_intr_h2l_det_q == 1'b1) &&
- (ac_present_intr_h2l_det == 1'b0);
- assign ec_rst_l_intr_l2h_pulse = (ec_rst_l_intr_l2h_det_q == 1'b0) &&
- (ec_rst_l_intr_l2h_det == 1'b1);
- assign ec_rst_l_intr_h2l_pulse = (ec_rst_l_intr_h2l_det_q == 1'b1) &&
- (ec_rst_l_intr_h2l_det == 1'b0);
-
- //Synchronize from 200KHz always-onclock to 24MHz cfg clock
- prim_pulse_sync u_pwrb_h2l (
- .clk_src_i (clk_aon_i),
- .clk_dst_i (clk_i),
- .rst_src_ni (rst_aon_ni),
- .rst_dst_ni (rst_ni),
- .src_pulse_i (pwrb_intr_h2l_pulse),
- .dst_pulse_o (pwrb_h2l_intr)
- );
-
- assign key_intr_status_o.pwrb_h2l.de = pwrb_h2l_intr;
-
- prim_pulse_sync u_pwrb_l2h (
- .clk_src_i (clk_aon_i),
- .clk_dst_i (clk_i),
- .rst_src_ni (rst_aon_ni),
- .rst_dst_ni (rst_ni),
- .src_pulse_i (pwrb_intr_l2h_pulse),
- .dst_pulse_o (pwrb_l2h_intr)
- );
-
- assign key_intr_status_o.pwrb_l2h.de = pwrb_l2h_intr;
-
- prim_pulse_sync u_key0_in_h2l (
- .clk_src_i (clk_aon_i),
- .clk_dst_i (clk_i),
- .rst_src_ni (rst_aon_ni),
- .rst_dst_ni (rst_ni),
- .src_pulse_i (key0_intr_h2l_pulse),
- .dst_pulse_o (key0_in_h2l_intr)
- );
-
- assign key_intr_status_o.key0_in_h2l.de = key0_in_h2l_intr;
-
- prim_pulse_sync u_key0_in_l2h (
- .clk_src_i (clk_aon_i),
- .clk_dst_i (clk_i),
- .rst_src_ni (rst_aon_ni),
- .rst_dst_ni (rst_ni),
- .src_pulse_i (key0_intr_l2h_pulse),
- .dst_pulse_o (key0_in_l2h_intr)
- );
-
- assign key_intr_status_o.key0_in_l2h.de = key0_in_l2h_intr;
-
- prim_pulse_sync u_key1_in_h2l (
- .clk_src_i (clk_aon_i),
- .clk_dst_i (clk_i),
- .rst_src_ni (rst_aon_ni),
- .rst_dst_ni (rst_ni),
- .src_pulse_i (key1_intr_h2l_pulse),
- .dst_pulse_o (key1_in_h2l_intr)
- );
-
- assign key_intr_status_o.key1_in_h2l.de = key1_in_h2l_intr;
-
- prim_pulse_sync u_key1_in_l2h (
- .clk_src_i (clk_aon_i),
- .clk_dst_i (clk_i),
- .rst_src_ni (rst_aon_ni),
- .rst_dst_ni (rst_ni),
- .src_pulse_i (key1_intr_l2h_pulse),
- .dst_pulse_o (key1_in_l2h_intr)
- );
-
- assign key_intr_status_o.key1_in_l2h.de = key1_in_l2h_intr;
-
- prim_pulse_sync u_key2_in_h2l (
- .clk_src_i (clk_aon_i),
- .clk_dst_i (clk_i),
- .rst_src_ni (rst_aon_ni),
- .rst_dst_ni (rst_ni),
- .src_pulse_i (key2_intr_h2l_pulse),
- .dst_pulse_o (key2_in_h2l_intr)
- );
-
- assign key_intr_status_o.key2_in_h2l.de = key2_in_h2l_intr;
-
- prim_pulse_sync u_key2_in_l2h (
- .clk_src_i (clk_aon_i),
- .clk_dst_i (clk_i),
- .rst_src_ni (rst_aon_ni),
- .rst_dst_ni (rst_ni),
- .src_pulse_i (key2_intr_l2h_pulse),
- .dst_pulse_o (key2_in_l2h_intr)
- );
-
- assign key_intr_status_o.key2_in_l2h.de = key2_in_l2h_intr;
-
- prim_pulse_sync u_ac_present_h2l (
- .clk_src_i (clk_aon_i),
- .clk_dst_i (clk_i),
- .rst_src_ni (rst_aon_ni),
- .rst_dst_ni (rst_ni),
- .src_pulse_i (ac_present_intr_h2l_pulse),
- .dst_pulse_o (ac_present_h2l_intr)
- );
-
- assign key_intr_status_o.ac_present_h2l.de = ac_present_h2l_intr;
-
- prim_pulse_sync u_ac_present_l2h (
- .clk_src_i (clk_aon_i),
- .clk_dst_i (clk_i),
- .rst_src_ni (rst_aon_ni),
- .rst_dst_ni (rst_ni),
- .src_pulse_i (ac_present_intr_l2h_pulse),
- .dst_pulse_o (ac_present_l2h_intr)
- );
-
- assign key_intr_status_o.ac_present_l2h.de = ac_present_l2h_intr;
-
- prim_pulse_sync u_ec_rst_l_h2l (
- .clk_src_i (clk_aon_i),
- .clk_dst_i (clk_i),
- .rst_src_ni (rst_aon_ni),
- .rst_dst_ni (rst_ni),
- .src_pulse_i (ec_rst_l_intr_h2l_pulse),
- .dst_pulse_o (ec_rst_l_h2l_intr)
- );
-
- assign key_intr_status_o.ec_rst_l_h2l.de = ec_rst_l_h2l_intr;
-
- prim_pulse_sync u_ec_rst_l_l2h (
- .clk_src_i (clk_aon_i),
- .clk_dst_i (clk_i),
- .rst_src_ni (rst_aon_ni),
- .rst_dst_ni (rst_ni),
- .src_pulse_i (ec_rst_l_intr_l2h_pulse),
- .dst_pulse_o (ec_rst_l_l2h_intr)
- );
-
- assign key_intr_status_o.ec_rst_l_l2h.de = ec_rst_l_l2h_intr;
-
- assign sysrst_ctrl_key_intr_o = pwrb_h2l_intr | pwrb_l2h_intr |
- key0_in_h2l_intr | key0_in_l2h_intr |
- key1_in_h2l_intr | key1_in_l2h_intr |
- key2_in_h2l_intr | key2_in_l2h_intr |
- ac_present_h2l_intr | ac_present_l2h_intr |
- ec_rst_l_h2l_intr | ec_rst_l_l2h_intr;
-
- //To write into interrupt status register
+ // To write into interrupt status register
assign key_intr_status_o.pwrb_h2l.d = 1'b1;
assign key_intr_status_o.pwrb_l2h.d = 1'b1;
assign key_intr_status_o.key0_in_h2l.d = 1'b1;
diff --git a/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_pin.sv b/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_pin.sv
index ced3e69..2a893a7 100644
--- a/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_pin.sv
+++ b/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_pin.sv
@@ -6,8 +6,6 @@
//
module sysrst_ctrl_pin import sysrst_ctrl_reg_pkg::*; (
- input clk_aon_i,
- input rst_aon_ni,
input clk_i,
input rst_ni,
@@ -43,428 +41,87 @@
);
- logic cfg_ac_present_i_pin;
- logic cfg_ec_rst_l_i_pin;
- logic cfg_pwrb_in_i_pin;
- logic cfg_key0_in_i_pin;
- logic cfg_key1_in_i_pin;
- logic cfg_key2_in_i_pin;
- logic cfg_lid_open_i_pin;
-
- logic cfg_bat_disable_0_allow;
- logic cfg_ec_rst_l_0_allow;
- logic cfg_pwrb_out_0_allow;
- logic cfg_key0_out_0_allow;
- logic cfg_key1_out_0_allow;
- logic cfg_key2_out_0_allow;
- logic cfg_z3_wakeup_0_allow;
- logic cfg_bat_disable_1_allow;
- logic cfg_ec_rst_l_1_allow;
- logic cfg_pwrb_out_1_allow;
- logic cfg_key0_out_1_allow;
- logic cfg_key1_out_1_allow;
- logic cfg_key2_out_1_allow;
- logic cfg_z3_wakeup_1_allow;
-
- logic cfg_bat_disable_ov;
- logic cfg_ec_rst_l_ov;
- logic cfg_pwrb_out_ov;
- logic cfg_key0_out_ov;
- logic cfg_key1_out_ov;
- logic cfg_key2_out_ov;
- logic cfg_z3_wakeup_ov;
-
- logic cfg_bat_disable_q;
- logic cfg_ec_rst_l_q;
- logic cfg_pwrb_out_q;
- logic cfg_key0_out_q;
- logic cfg_key1_out_q;
- logic cfg_key2_out_q;
- logic cfg_z3_wakeup_q;
-
- //Synchronize between GPIO and cfg(24MHz)
+ // Synchronize between GPIO and cfg(24MHz)
+ // Use the raw input values here (not the inverted pass through values)
prim_flop_2sync # (
- .Width(1)
+ .Width(7)
) u_cfg_ac_present_i_pin (
- .clk_i(clk_i),
- .rst_ni(rst_ni),
- .d_i(cio_ac_present_i),
- .q_o(cfg_ac_present_i_pin)
+ .clk_i,
+ .rst_ni,
+ .d_i({cio_ac_present_i,
+ cio_ec_rst_in_l_i,
+ cio_pwrb_in_i,
+ cio_key0_in_i,
+ cio_key1_in_i,
+ cio_key2_in_i,
+ cio_lid_open_i}),
+ .q_o({pin_in_value_o.ac_present.d,
+ pin_in_value_o.ec_rst_l.d,
+ pin_in_value_o.pwrb_in.d,
+ pin_in_value_o.key0_in.d,
+ pin_in_value_o.key1_in.d,
+ pin_in_value_o.key2_in.d,
+ pin_in_value_o.lid_open.d})
);
- prim_flop_2sync # (
- .Width(1)
- ) u_cfg_ec_rst_l_i_pin (
- .clk_i(clk_i),
- .rst_ni(rst_ni),
- .d_i(cio_ec_rst_in_l_i),
- .q_o(cfg_ec_rst_l_i_pin)
- );
-
- prim_flop_2sync # (
- .Width(1)
- ) u_cfg_pwrb_in_i_pin (
- .clk_i(clk_i),
- .rst_ni(rst_ni),
- .d_i(cio_pwrb_in_i),
- .q_o(cfg_pwrb_in_i_pin)
- );
-
- prim_flop_2sync # (
- .Width(1)
- ) u_cfg_key0_in_i_pin (
- .clk_i(clk_i),
- .rst_ni(rst_ni),
- .d_i(cio_key0_in_i),
- .q_o(cfg_key0_in_i_pin)
- );
-
- prim_flop_2sync # (
- .Width(1)
- ) u_cfg_key1_in_i_pin (
- .clk_i(clk_i),
- .rst_ni(rst_ni),
- .d_i(cio_key1_in_i),
- .q_o(cfg_key1_in_i_pin)
- );
-
- prim_flop_2sync # (
- .Width(1)
- ) u_cfg_key2_in_i_pin (
- .clk_i(clk_i),
- .rst_ni(rst_ni),
- .d_i(cio_key2_in_i),
- .q_o(cfg_key2_in_i_pin)
- );
-
- prim_flop_2sync # (
- .Width(1)
- ) u_cfg_lid_open_i_pin (
- .clk_i(clk_i),
- .rst_ni(rst_ni),
- .d_i(cio_lid_open_i),
- .q_o(cfg_lid_open_i_pin)
- );
-
- //Use the raw input(not inverted)
- assign pin_in_value_o.ac_present.d = cfg_ac_present_i_pin;
- assign pin_in_value_o.ec_rst_l.d = cfg_ec_rst_l_i_pin;
- assign pin_in_value_o.pwrb_in.d = cfg_pwrb_in_i_pin;
- assign pin_in_value_o.key0_in.d = cfg_key0_in_i_pin;
- assign pin_in_value_o.key1_in.d = cfg_key1_in_i_pin;
- assign pin_in_value_o.key2_in.d = cfg_key2_in_i_pin;
- assign pin_in_value_o.lid_open.d = cfg_lid_open_i_pin;
-
assign pin_in_value_o.ac_present.de = 1'b1;
- assign pin_in_value_o.ec_rst_l.de = 1'b1;
- assign pin_in_value_o.pwrb_in.de = 1'b1;
- assign pin_in_value_o.key0_in.de = 1'b1;
- assign pin_in_value_o.key1_in.de = 1'b1;
- assign pin_in_value_o.key2_in.de = 1'b1;
- assign pin_in_value_o.lid_open.de = 1'b1;
+ assign pin_in_value_o.ec_rst_l.de = 1'b1;
+ assign pin_in_value_o.pwrb_in.de = 1'b1;
+ assign pin_in_value_o.key0_in.de = 1'b1;
+ assign pin_in_value_o.key1_in.de = 1'b1;
+ assign pin_in_value_o.key2_in.de = 1'b1;
+ assign pin_in_value_o.lid_open.de = 1'b1;
- //synchronize between cfg(24MHz) and always-on(200KHz)
- prim_flop_2sync # (
- .Width(1),
- .ResetValue('0)
- ) u_cfg_bat_disable_0_allow (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(pin_allowed_ctl_i.bat_disable_0.q),
- .q_o(cfg_bat_disable_0_allow)
- );
+ // Pin override logic.
+ localparam int NumSignals = 7;
+ logic [NumSignals-1:0] inputs, outputs, enabled, values, allowed0, allowed1;
+ assign inputs = {pwrb_out_hw_i,
+ key0_out_hw_i,
+ key1_out_hw_i,
+ key2_out_hw_i,
+ z3_wakeup_hw_i,
+ bat_disable_hw_i,
+ ec_rst_l_hw_i};
+ assign enabled = {pin_out_ctl_i.pwrb_out.q,
+ pin_out_ctl_i.key0_out.q,
+ pin_out_ctl_i.key1_out.q,
+ pin_out_ctl_i.key2_out.q,
+ pin_out_ctl_i.z3_wakeup.q,
+ pin_out_ctl_i.bat_disable.q,
+ pin_out_ctl_i.ec_rst_l.q};
+ assign values = {pin_out_value_i.pwrb_out.q,
+ pin_out_value_i.key0_out.q,
+ pin_out_value_i.key1_out.q,
+ pin_out_value_i.key2_out.q,
+ pin_out_value_i.z3_wakeup.q,
+ pin_out_value_i.bat_disable.q,
+ pin_out_value_i.ec_rst_l.q};
+ assign allowed0 = {pin_allowed_ctl_i.pwrb_out_0.q,
+ pin_allowed_ctl_i.key0_out_0.q,
+ pin_allowed_ctl_i.key1_out_0.q,
+ pin_allowed_ctl_i.key2_out_0.q,
+ pin_allowed_ctl_i.z3_wakeup_0.q,
+ pin_allowed_ctl_i.bat_disable_0.q,
+ pin_allowed_ctl_i.ec_rst_l_0.q};
+ assign allowed1 = {pin_allowed_ctl_i.pwrb_out_1.q,
+ pin_allowed_ctl_i.key0_out_1.q,
+ pin_allowed_ctl_i.key1_out_1.q,
+ pin_allowed_ctl_i.key2_out_1.q,
+ pin_allowed_ctl_i.z3_wakeup_1.q,
+ pin_allowed_ctl_i.bat_disable_1.q,
+ pin_allowed_ctl_i.ec_rst_l_1.q};
- prim_flop_2sync # (
- .Width(1),
- .ResetValue(1'b1)//ec_rst_l_0_allow is enabled by default
- ) u_cfg_ec_rst_l_0_allow (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(pin_allowed_ctl_i.ec_rst_l_0.q),
- .q_o(cfg_ec_rst_l_0_allow)
- );
+ for (genvar k = 0; k < NumSignals; k++) begin : gen_override_logic
+ assign outputs[k] = (enabled[k] && allowed0[k] && !values[k]) ? 1'b0 :
+ (enabled[k] && allowed1[k] && values[k]) ? 1'b1 : inputs[k];
+ end
- prim_flop_2sync # (
- .Width(1),
- .ResetValue('0)
- ) u_cfg_pwrb_out_0_allow (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(pin_allowed_ctl_i.pwrb_out_0.q),
- .q_o(cfg_pwrb_out_0_allow)
- );
-
- prim_flop_2sync # (
- .Width(1),
- .ResetValue('0)
- ) u_cfg_key0_out_0_allow (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(pin_allowed_ctl_i.key0_out_0.q),
- .q_o(cfg_key0_out_0_allow)
- );
-
- prim_flop_2sync # (
- .Width(1),
- .ResetValue('0)
- ) u_cfg_key1_out_0_allow (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(pin_allowed_ctl_i.key1_out_0.q),
- .q_o(cfg_key1_out_0_allow)
- );
-
- prim_flop_2sync # (
- .Width(1),
- .ResetValue('0)
- ) u_cfg_key2_out_0_allow (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(pin_allowed_ctl_i.key2_out_0.q),
- .q_o(cfg_key2_out_0_allow)
- );
-
- prim_flop_2sync # (
- .Width(1),
- .ResetValue('0)
- ) u_cfg_z3_wakeup_0_allow (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(pin_allowed_ctl_i.z3_wakeup_0.q),
- .q_o(cfg_z3_wakeup_0_allow)
- );
-
- prim_flop_2sync # (
- .Width(1),
- .ResetValue('0)
- ) u_cfg_bat_disable_1_allow (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(pin_allowed_ctl_i.bat_disable_1.q),
- .q_o(cfg_bat_disable_1_allow)
- );
-
- prim_flop_2sync # (
- .Width(1),
- .ResetValue('0)
- ) u_cfg_ec_rst_l_1_allow (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(pin_allowed_ctl_i.ec_rst_l_1.q),
- .q_o(cfg_ec_rst_l_1_allow)
- );
-
- prim_flop_2sync # (
- .Width(1),
- .ResetValue('0)
- ) u_cfg_pwrb_out_1_allow (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(pin_allowed_ctl_i.pwrb_out_1.q),
- .q_o(cfg_pwrb_out_1_allow)
- );
-
- prim_flop_2sync # (
- .Width(1),
- .ResetValue('0)
- ) u_cfg_key0_out_1_allow (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(pin_allowed_ctl_i.key0_out_1.q),
- .q_o(cfg_key0_out_1_allow)
- );
-
- prim_flop_2sync # (
- .Width(1),
- .ResetValue('0)
- ) u_cfg_key1_out_1_allow (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(pin_allowed_ctl_i.key1_out_1.q),
- .q_o(cfg_key1_out_1_allow)
- );
-
- prim_flop_2sync # (
- .Width(1),
- .ResetValue('0)
- ) u_cfg_key2_out_1_allow (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(pin_allowed_ctl_i.key2_out_1.q),
- .q_o(cfg_key2_out_1_allow)
- );
-
- prim_flop_2sync # (
- .Width(1),
- .ResetValue('0)
- ) u_cfg_z3_wakeup_1_allow (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(pin_allowed_ctl_i.z3_wakeup_1.q),
- .q_o(cfg_z3_wakeup_1_allow)
- );
-
- prim_flop_2sync # (
- .Width(1),
- .ResetValue('0)
- ) u_cfg_bat_disable_ov (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(pin_out_ctl_i.bat_disable.q),
- .q_o(cfg_bat_disable_ov)
- );
-
- prim_flop_2sync # (
- .Width(1),
- .ResetValue(1'b1)//ec_rst_l override is enabled by default
- ) u_cfg_ec_rst_l_ov (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(pin_out_ctl_i.ec_rst_l.q),
- .q_o(cfg_ec_rst_l_ov)
- );
-
- prim_flop_2sync # (
- .Width(1),
- .ResetValue('0)
- ) u_cfg_pwrb_out_ov (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(pin_out_ctl_i.pwrb_out.q),
- .q_o(cfg_pwrb_out_ov)
- );
-
- prim_flop_2sync # (
- .Width(1),
- .ResetValue('0)
- ) u_cfg_key0_out_ov (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(pin_out_ctl_i.key0_out.q),
- .q_o(cfg_key0_out_ov)
- );
-
- prim_flop_2sync # (
- .Width(1),
- .ResetValue('0)
- ) u_cfg_key1_out_ov (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(pin_out_ctl_i.key1_out.q),
- .q_o(cfg_key1_out_ov)
- );
-
- prim_flop_2sync # (
- .Width(1),
- .ResetValue('0)
- ) u_cfg_key2_out_ov (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(pin_out_ctl_i.key2_out.q),
- .q_o(cfg_key2_out_ov)
- );
-
- prim_flop_2sync # (
- .Width(1),
- .ResetValue('0)
- ) u_cfg_z3_wakeup_ov (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(pin_out_ctl_i.z3_wakeup.q),
- .q_o(cfg_z3_wakeup_ov)
- );
-
- prim_flop_2sync # (
- .Width(1),
- .ResetValue('0)
- ) u_cfg_bat_disable_q (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(pin_out_value_i.bat_disable.q),
- .q_o(cfg_bat_disable_q)
- );
-
- prim_flop_2sync # (
- .Width(1),
- .ResetValue('0)
- ) u_cfg_ec_rst_l_q (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(pin_out_value_i.ec_rst_l.q),
- .q_o(cfg_ec_rst_l_q)
- );
-
- prim_flop_2sync # (
- .Width(1),
- .ResetValue('0)
- ) u_cfg_pwrb_out_q (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(pin_out_value_i.pwrb_out.q),
- .q_o(cfg_pwrb_out_q)
- );
-
- prim_flop_2sync # (
- .Width(1),
- .ResetValue('0)
- ) u_cfg_key0_out_q (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(pin_out_value_i.key0_out.q),
- .q_o(cfg_key0_out_q)
- );
-
- prim_flop_2sync # (
- .Width(1),
- .ResetValue('0)
- ) u_cfg_key1_out_q (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(pin_out_value_i.key1_out.q),
- .q_o(cfg_key1_out_q)
- );
-
- prim_flop_2sync # (
- .Width(1),
- .ResetValue('0)
- ) u_cfg_key2_out_q (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(pin_out_value_i.key2_out.q),
- .q_o(cfg_key2_out_q)
- );
-
- prim_flop_2sync # (
- .Width(1),
- .ResetValue('0)
- ) u_cfg_z3_wakeup_q (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(pin_out_value_i.z3_wakeup.q),
- .q_o(cfg_z3_wakeup_q)
- );
-
- assign pwrb_out_int_o = (cfg_pwrb_out_ov && cfg_pwrb_out_0_allow && !cfg_pwrb_out_q) ? 1'b0 :
- ((cfg_pwrb_out_ov && cfg_pwrb_out_1_allow && cfg_pwrb_out_q) ? 1'b1 : pwrb_out_hw_i);
-
- assign key0_out_int_o = (cfg_key0_out_ov && cfg_key0_out_0_allow && !cfg_key0_out_q) ? 1'b0 :
- ((cfg_key0_out_ov && cfg_key0_out_1_allow && cfg_key0_out_q) ? 1'b1 : key0_out_hw_i);
-
- assign key1_out_int_o = (cfg_key1_out_ov && cfg_key1_out_0_allow && !cfg_key1_out_q) ? 1'b0 :
- ((cfg_key1_out_ov && cfg_key1_out_1_allow && cfg_key1_out_q) ? 1'b1 : key1_out_hw_i);
-
- assign key2_out_int_o = (cfg_key2_out_ov && cfg_key2_out_0_allow && !cfg_key2_out_q) ? 1'b0 :
- ((cfg_key2_out_ov && cfg_key2_out_1_allow && cfg_key2_out_q) ? 1'b1 : key2_out_hw_i);
-
- assign z3_wakeup_int_o = (cfg_z3_wakeup_ov && cfg_z3_wakeup_0_allow && !cfg_z3_wakeup_q) ? 1'b0 :
- ((cfg_z3_wakeup_ov && cfg_z3_wakeup_1_allow && cfg_z3_wakeup_q) ? 1'b1 : z3_wakeup_hw_i);
-
- assign bat_disable_int_o =
- (cfg_bat_disable_ov && cfg_bat_disable_0_allow && !cfg_bat_disable_q) ? 1'b0 :
- ((cfg_bat_disable_ov && cfg_bat_disable_1_allow && cfg_bat_disable_q) ? 1'b1 :
- bat_disable_hw_i);
-
- assign cio_ec_rst_out_l_o = (cfg_ec_rst_l_ov && cfg_ec_rst_l_0_allow && !cfg_ec_rst_l_q) ? 1'b0 :
- ((cfg_ec_rst_l_ov && cfg_ec_rst_l_1_allow && cfg_ec_rst_l_q) ? 1'b1 : ec_rst_l_hw_i);
+ assign {pwrb_out_int_o,
+ key0_out_int_o,
+ key1_out_int_o,
+ key2_out_int_o,
+ z3_wakeup_int_o,
+ bat_disable_int_o,
+ cio_ec_rst_out_l_o} = outputs;
endmodule
diff --git a/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_reg_pkg.sv b/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_reg_pkg.sv
index 2e369d2..7d57efa 100644
--- a/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_reg_pkg.sv
+++ b/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_reg_pkg.sv
@@ -8,6 +8,7 @@
// Param list
parameter int NumCombo = 4;
+ parameter int TimerWidth = 16;
parameter int NumAlerts = 1;
// Address widths within the block
@@ -37,22 +38,18 @@
typedef struct packed {
logic [15:0] q;
- logic qe;
} sysrst_ctrl_reg2hw_ec_rst_ctl_reg_t;
typedef struct packed {
logic [15:0] q;
- logic qe;
} sysrst_ctrl_reg2hw_ulp_ac_debounce_ctl_reg_t;
typedef struct packed {
logic [15:0] q;
- logic qe;
} sysrst_ctrl_reg2hw_ulp_lid_debounce_ctl_reg_t;
typedef struct packed {
logic [15:0] q;
- logic qe;
} sysrst_ctrl_reg2hw_ulp_pwrb_debounce_ctl_reg_t;
typedef struct packed {
@@ -236,17 +233,14 @@
typedef struct packed {
logic [15:0] q;
- logic qe;
} sysrst_ctrl_reg2hw_key_intr_debounce_ctl_reg_t;
typedef struct packed {
struct packed {
logic [15:0] q;
- logic qe;
} debounce_timer;
struct packed {
logic q;
- logic qe;
} auto_block_enable;
} sysrst_ctrl_reg2hw_auto_block_debounce_ctl_reg_t;
@@ -291,7 +285,6 @@
typedef struct packed {
logic [31:0] q;
- logic qe;
} sysrst_ctrl_reg2hw_com_det_ctl_mreg_t;
typedef struct packed {
@@ -427,26 +420,26 @@
// Register -> HW type
typedef struct packed {
- sysrst_ctrl_reg2hw_intr_state_reg_t intr_state; // [337:337]
- sysrst_ctrl_reg2hw_intr_enable_reg_t intr_enable; // [336:336]
- sysrst_ctrl_reg2hw_intr_test_reg_t intr_test; // [335:334]
- sysrst_ctrl_reg2hw_alert_test_reg_t alert_test; // [333:332]
- sysrst_ctrl_reg2hw_ec_rst_ctl_reg_t ec_rst_ctl; // [331:315]
- sysrst_ctrl_reg2hw_ulp_ac_debounce_ctl_reg_t ulp_ac_debounce_ctl; // [314:298]
- sysrst_ctrl_reg2hw_ulp_lid_debounce_ctl_reg_t ulp_lid_debounce_ctl; // [297:281]
- sysrst_ctrl_reg2hw_ulp_pwrb_debounce_ctl_reg_t ulp_pwrb_debounce_ctl; // [280:264]
- sysrst_ctrl_reg2hw_ulp_ctl_reg_t ulp_ctl; // [263:263]
- sysrst_ctrl_reg2hw_wk_status_reg_t wk_status; // [262:262]
- sysrst_ctrl_reg2hw_key_invert_ctl_reg_t key_invert_ctl; // [261:250]
- sysrst_ctrl_reg2hw_pin_allowed_ctl_reg_t pin_allowed_ctl; // [249:236]
- sysrst_ctrl_reg2hw_pin_out_ctl_reg_t pin_out_ctl; // [235:229]
- sysrst_ctrl_reg2hw_pin_out_value_reg_t pin_out_value; // [228:222]
- sysrst_ctrl_reg2hw_key_intr_ctl_reg_t key_intr_ctl; // [221:210]
- sysrst_ctrl_reg2hw_key_intr_debounce_ctl_reg_t key_intr_debounce_ctl; // [209:193]
- sysrst_ctrl_reg2hw_auto_block_debounce_ctl_reg_t auto_block_debounce_ctl; // [192:174]
- sysrst_ctrl_reg2hw_auto_block_out_ctl_reg_t auto_block_out_ctl; // [173:168]
- sysrst_ctrl_reg2hw_com_sel_ctl_mreg_t [3:0] com_sel_ctl; // [167:148]
- sysrst_ctrl_reg2hw_com_det_ctl_mreg_t [3:0] com_det_ctl; // [147:16]
+ sysrst_ctrl_reg2hw_intr_state_reg_t intr_state; // [326:326]
+ sysrst_ctrl_reg2hw_intr_enable_reg_t intr_enable; // [325:325]
+ sysrst_ctrl_reg2hw_intr_test_reg_t intr_test; // [324:323]
+ sysrst_ctrl_reg2hw_alert_test_reg_t alert_test; // [322:321]
+ sysrst_ctrl_reg2hw_ec_rst_ctl_reg_t ec_rst_ctl; // [320:305]
+ sysrst_ctrl_reg2hw_ulp_ac_debounce_ctl_reg_t ulp_ac_debounce_ctl; // [304:289]
+ sysrst_ctrl_reg2hw_ulp_lid_debounce_ctl_reg_t ulp_lid_debounce_ctl; // [288:273]
+ sysrst_ctrl_reg2hw_ulp_pwrb_debounce_ctl_reg_t ulp_pwrb_debounce_ctl; // [272:257]
+ sysrst_ctrl_reg2hw_ulp_ctl_reg_t ulp_ctl; // [256:256]
+ sysrst_ctrl_reg2hw_wk_status_reg_t wk_status; // [255:255]
+ sysrst_ctrl_reg2hw_key_invert_ctl_reg_t key_invert_ctl; // [254:243]
+ sysrst_ctrl_reg2hw_pin_allowed_ctl_reg_t pin_allowed_ctl; // [242:229]
+ sysrst_ctrl_reg2hw_pin_out_ctl_reg_t pin_out_ctl; // [228:222]
+ sysrst_ctrl_reg2hw_pin_out_value_reg_t pin_out_value; // [221:215]
+ sysrst_ctrl_reg2hw_key_intr_ctl_reg_t key_intr_ctl; // [214:203]
+ sysrst_ctrl_reg2hw_key_intr_debounce_ctl_reg_t key_intr_debounce_ctl; // [202:187]
+ sysrst_ctrl_reg2hw_auto_block_debounce_ctl_reg_t auto_block_debounce_ctl; // [186:170]
+ sysrst_ctrl_reg2hw_auto_block_out_ctl_reg_t auto_block_out_ctl; // [169:164]
+ sysrst_ctrl_reg2hw_com_sel_ctl_mreg_t [3:0] com_sel_ctl; // [163:144]
+ sysrst_ctrl_reg2hw_com_det_ctl_mreg_t [3:0] com_det_ctl; // [143:16]
sysrst_ctrl_reg2hw_com_out_ctl_mreg_t [3:0] com_out_ctl; // [15:0]
} sysrst_ctrl_reg2hw_t;
diff --git a/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_reg_top.sv b/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_reg_top.sv
index 999f324..e6d402f 100644
--- a/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_reg_top.sv
+++ b/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_reg_top.sv
@@ -9,6 +9,8 @@
module sysrst_ctrl_reg_top (
input clk_i,
input rst_ni,
+ input clk_aon_i,
+ input rst_aon_ni,
input tlul_pkg::tl_h2d_t tl_i,
output tlul_pkg::tl_d2h_t tl_o,
@@ -102,6 +104,15 @@
);
// cdc oversampling signals
+ logic sync_aon_update;
+ prim_pulse_sync u_aon_tgl (
+ .clk_src_i(clk_aon_i),
+ .rst_src_ni(rst_aon_ni),
+ .src_pulse_i(1'b1),
+ .clk_dst_i(clk_i),
+ .rst_dst_ni(rst_ni),
+ .dst_pulse_o(sync_aon_update)
+ );
assign reg_rdata = reg_rdata_next ;
assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
@@ -125,108 +136,154 @@
logic ec_rst_ctl_we;
logic [15:0] ec_rst_ctl_qs;
logic [15:0] ec_rst_ctl_wd;
+ logic ec_rst_ctl_busy;
logic ulp_ac_debounce_ctl_we;
logic [15:0] ulp_ac_debounce_ctl_qs;
logic [15:0] ulp_ac_debounce_ctl_wd;
+ logic ulp_ac_debounce_ctl_busy;
logic ulp_lid_debounce_ctl_we;
logic [15:0] ulp_lid_debounce_ctl_qs;
logic [15:0] ulp_lid_debounce_ctl_wd;
+ logic ulp_lid_debounce_ctl_busy;
logic ulp_pwrb_debounce_ctl_we;
logic [15:0] ulp_pwrb_debounce_ctl_qs;
logic [15:0] ulp_pwrb_debounce_ctl_wd;
+ logic ulp_pwrb_debounce_ctl_busy;
logic ulp_ctl_we;
logic ulp_ctl_qs;
logic ulp_ctl_wd;
+ logic ulp_ctl_busy;
logic ulp_status_we;
logic ulp_status_qs;
logic ulp_status_wd;
+ logic ulp_status_busy;
logic wk_status_we;
logic wk_status_qs;
logic wk_status_wd;
logic key_invert_ctl_we;
logic key_invert_ctl_key0_in_qs;
logic key_invert_ctl_key0_in_wd;
+ logic key_invert_ctl_key0_in_busy;
logic key_invert_ctl_key0_out_qs;
logic key_invert_ctl_key0_out_wd;
+ logic key_invert_ctl_key0_out_busy;
logic key_invert_ctl_key1_in_qs;
logic key_invert_ctl_key1_in_wd;
+ logic key_invert_ctl_key1_in_busy;
logic key_invert_ctl_key1_out_qs;
logic key_invert_ctl_key1_out_wd;
+ logic key_invert_ctl_key1_out_busy;
logic key_invert_ctl_key2_in_qs;
logic key_invert_ctl_key2_in_wd;
+ logic key_invert_ctl_key2_in_busy;
logic key_invert_ctl_key2_out_qs;
logic key_invert_ctl_key2_out_wd;
+ logic key_invert_ctl_key2_out_busy;
logic key_invert_ctl_pwrb_in_qs;
logic key_invert_ctl_pwrb_in_wd;
+ logic key_invert_ctl_pwrb_in_busy;
logic key_invert_ctl_pwrb_out_qs;
logic key_invert_ctl_pwrb_out_wd;
+ logic key_invert_ctl_pwrb_out_busy;
logic key_invert_ctl_ac_present_qs;
logic key_invert_ctl_ac_present_wd;
+ logic key_invert_ctl_ac_present_busy;
logic key_invert_ctl_bat_disable_qs;
logic key_invert_ctl_bat_disable_wd;
+ logic key_invert_ctl_bat_disable_busy;
logic key_invert_ctl_lid_open_qs;
logic key_invert_ctl_lid_open_wd;
+ logic key_invert_ctl_lid_open_busy;
logic key_invert_ctl_z3_wakeup_qs;
logic key_invert_ctl_z3_wakeup_wd;
+ logic key_invert_ctl_z3_wakeup_busy;
logic pin_allowed_ctl_we;
logic pin_allowed_ctl_bat_disable_0_qs;
logic pin_allowed_ctl_bat_disable_0_wd;
+ logic pin_allowed_ctl_bat_disable_0_busy;
logic pin_allowed_ctl_ec_rst_l_0_qs;
logic pin_allowed_ctl_ec_rst_l_0_wd;
+ logic pin_allowed_ctl_ec_rst_l_0_busy;
logic pin_allowed_ctl_pwrb_out_0_qs;
logic pin_allowed_ctl_pwrb_out_0_wd;
+ logic pin_allowed_ctl_pwrb_out_0_busy;
logic pin_allowed_ctl_key0_out_0_qs;
logic pin_allowed_ctl_key0_out_0_wd;
+ logic pin_allowed_ctl_key0_out_0_busy;
logic pin_allowed_ctl_key1_out_0_qs;
logic pin_allowed_ctl_key1_out_0_wd;
+ logic pin_allowed_ctl_key1_out_0_busy;
logic pin_allowed_ctl_key2_out_0_qs;
logic pin_allowed_ctl_key2_out_0_wd;
+ logic pin_allowed_ctl_key2_out_0_busy;
logic pin_allowed_ctl_z3_wakeup_0_qs;
logic pin_allowed_ctl_z3_wakeup_0_wd;
+ logic pin_allowed_ctl_z3_wakeup_0_busy;
logic pin_allowed_ctl_bat_disable_1_qs;
logic pin_allowed_ctl_bat_disable_1_wd;
+ logic pin_allowed_ctl_bat_disable_1_busy;
logic pin_allowed_ctl_ec_rst_l_1_qs;
logic pin_allowed_ctl_ec_rst_l_1_wd;
+ logic pin_allowed_ctl_ec_rst_l_1_busy;
logic pin_allowed_ctl_pwrb_out_1_qs;
logic pin_allowed_ctl_pwrb_out_1_wd;
+ logic pin_allowed_ctl_pwrb_out_1_busy;
logic pin_allowed_ctl_key0_out_1_qs;
logic pin_allowed_ctl_key0_out_1_wd;
+ logic pin_allowed_ctl_key0_out_1_busy;
logic pin_allowed_ctl_key1_out_1_qs;
logic pin_allowed_ctl_key1_out_1_wd;
+ logic pin_allowed_ctl_key1_out_1_busy;
logic pin_allowed_ctl_key2_out_1_qs;
logic pin_allowed_ctl_key2_out_1_wd;
+ logic pin_allowed_ctl_key2_out_1_busy;
logic pin_allowed_ctl_z3_wakeup_1_qs;
logic pin_allowed_ctl_z3_wakeup_1_wd;
+ logic pin_allowed_ctl_z3_wakeup_1_busy;
logic pin_out_ctl_we;
logic pin_out_ctl_bat_disable_qs;
logic pin_out_ctl_bat_disable_wd;
+ logic pin_out_ctl_bat_disable_busy;
logic pin_out_ctl_ec_rst_l_qs;
logic pin_out_ctl_ec_rst_l_wd;
+ logic pin_out_ctl_ec_rst_l_busy;
logic pin_out_ctl_pwrb_out_qs;
logic pin_out_ctl_pwrb_out_wd;
+ logic pin_out_ctl_pwrb_out_busy;
logic pin_out_ctl_key0_out_qs;
logic pin_out_ctl_key0_out_wd;
+ logic pin_out_ctl_key0_out_busy;
logic pin_out_ctl_key1_out_qs;
logic pin_out_ctl_key1_out_wd;
+ logic pin_out_ctl_key1_out_busy;
logic pin_out_ctl_key2_out_qs;
logic pin_out_ctl_key2_out_wd;
+ logic pin_out_ctl_key2_out_busy;
logic pin_out_ctl_z3_wakeup_qs;
logic pin_out_ctl_z3_wakeup_wd;
+ logic pin_out_ctl_z3_wakeup_busy;
logic pin_out_value_we;
logic pin_out_value_bat_disable_qs;
logic pin_out_value_bat_disable_wd;
+ logic pin_out_value_bat_disable_busy;
logic pin_out_value_ec_rst_l_qs;
logic pin_out_value_ec_rst_l_wd;
+ logic pin_out_value_ec_rst_l_busy;
logic pin_out_value_pwrb_out_qs;
logic pin_out_value_pwrb_out_wd;
+ logic pin_out_value_pwrb_out_busy;
logic pin_out_value_key0_out_qs;
logic pin_out_value_key0_out_wd;
+ logic pin_out_value_key0_out_busy;
logic pin_out_value_key1_out_qs;
logic pin_out_value_key1_out_wd;
+ logic pin_out_value_key1_out_busy;
logic pin_out_value_key2_out_qs;
logic pin_out_value_key2_out_wd;
+ logic pin_out_value_key2_out_busy;
logic pin_out_value_z3_wakeup_qs;
logic pin_out_value_z3_wakeup_wd;
+ logic pin_out_value_z3_wakeup_busy;
logic pin_in_value_ac_present_qs;
logic pin_in_value_ec_rst_l_qs;
logic pin_in_value_pwrb_in_qs;
@@ -237,141 +294,202 @@
logic key_intr_ctl_we;
logic key_intr_ctl_pwrb_in_h2l_qs;
logic key_intr_ctl_pwrb_in_h2l_wd;
+ logic key_intr_ctl_pwrb_in_h2l_busy;
logic key_intr_ctl_key0_in_h2l_qs;
logic key_intr_ctl_key0_in_h2l_wd;
+ logic key_intr_ctl_key0_in_h2l_busy;
logic key_intr_ctl_key1_in_h2l_qs;
logic key_intr_ctl_key1_in_h2l_wd;
+ logic key_intr_ctl_key1_in_h2l_busy;
logic key_intr_ctl_key2_in_h2l_qs;
logic key_intr_ctl_key2_in_h2l_wd;
+ logic key_intr_ctl_key2_in_h2l_busy;
logic key_intr_ctl_ac_present_h2l_qs;
logic key_intr_ctl_ac_present_h2l_wd;
+ logic key_intr_ctl_ac_present_h2l_busy;
logic key_intr_ctl_ec_rst_l_h2l_qs;
logic key_intr_ctl_ec_rst_l_h2l_wd;
+ logic key_intr_ctl_ec_rst_l_h2l_busy;
logic key_intr_ctl_pwrb_in_l2h_qs;
logic key_intr_ctl_pwrb_in_l2h_wd;
+ logic key_intr_ctl_pwrb_in_l2h_busy;
logic key_intr_ctl_key0_in_l2h_qs;
logic key_intr_ctl_key0_in_l2h_wd;
+ logic key_intr_ctl_key0_in_l2h_busy;
logic key_intr_ctl_key1_in_l2h_qs;
logic key_intr_ctl_key1_in_l2h_wd;
+ logic key_intr_ctl_key1_in_l2h_busy;
logic key_intr_ctl_key2_in_l2h_qs;
logic key_intr_ctl_key2_in_l2h_wd;
+ logic key_intr_ctl_key2_in_l2h_busy;
logic key_intr_ctl_ac_present_l2h_qs;
logic key_intr_ctl_ac_present_l2h_wd;
+ logic key_intr_ctl_ac_present_l2h_busy;
logic key_intr_ctl_ec_rst_l_l2h_qs;
logic key_intr_ctl_ec_rst_l_l2h_wd;
+ logic key_intr_ctl_ec_rst_l_l2h_busy;
logic key_intr_debounce_ctl_we;
logic [15:0] key_intr_debounce_ctl_qs;
logic [15:0] key_intr_debounce_ctl_wd;
+ logic key_intr_debounce_ctl_busy;
logic auto_block_debounce_ctl_we;
logic [15:0] auto_block_debounce_ctl_debounce_timer_qs;
logic [15:0] auto_block_debounce_ctl_debounce_timer_wd;
+ logic auto_block_debounce_ctl_debounce_timer_busy;
logic auto_block_debounce_ctl_auto_block_enable_qs;
logic auto_block_debounce_ctl_auto_block_enable_wd;
+ logic auto_block_debounce_ctl_auto_block_enable_busy;
logic auto_block_out_ctl_we;
logic auto_block_out_ctl_key0_out_sel_qs;
logic auto_block_out_ctl_key0_out_sel_wd;
+ logic auto_block_out_ctl_key0_out_sel_busy;
logic auto_block_out_ctl_key1_out_sel_qs;
logic auto_block_out_ctl_key1_out_sel_wd;
+ logic auto_block_out_ctl_key1_out_sel_busy;
logic auto_block_out_ctl_key2_out_sel_qs;
logic auto_block_out_ctl_key2_out_sel_wd;
+ logic auto_block_out_ctl_key2_out_sel_busy;
logic auto_block_out_ctl_key0_out_value_qs;
logic auto_block_out_ctl_key0_out_value_wd;
+ logic auto_block_out_ctl_key0_out_value_busy;
logic auto_block_out_ctl_key1_out_value_qs;
logic auto_block_out_ctl_key1_out_value_wd;
+ logic auto_block_out_ctl_key1_out_value_busy;
logic auto_block_out_ctl_key2_out_value_qs;
logic auto_block_out_ctl_key2_out_value_wd;
+ logic auto_block_out_ctl_key2_out_value_busy;
logic com_sel_ctl_0_we;
logic com_sel_ctl_0_key0_in_sel_0_qs;
logic com_sel_ctl_0_key0_in_sel_0_wd;
+ logic com_sel_ctl_0_key0_in_sel_0_busy;
logic com_sel_ctl_0_key1_in_sel_0_qs;
logic com_sel_ctl_0_key1_in_sel_0_wd;
+ logic com_sel_ctl_0_key1_in_sel_0_busy;
logic com_sel_ctl_0_key2_in_sel_0_qs;
logic com_sel_ctl_0_key2_in_sel_0_wd;
+ logic com_sel_ctl_0_key2_in_sel_0_busy;
logic com_sel_ctl_0_pwrb_in_sel_0_qs;
logic com_sel_ctl_0_pwrb_in_sel_0_wd;
+ logic com_sel_ctl_0_pwrb_in_sel_0_busy;
logic com_sel_ctl_0_ac_present_sel_0_qs;
logic com_sel_ctl_0_ac_present_sel_0_wd;
+ logic com_sel_ctl_0_ac_present_sel_0_busy;
logic com_sel_ctl_1_we;
logic com_sel_ctl_1_key0_in_sel_1_qs;
logic com_sel_ctl_1_key0_in_sel_1_wd;
+ logic com_sel_ctl_1_key0_in_sel_1_busy;
logic com_sel_ctl_1_key1_in_sel_1_qs;
logic com_sel_ctl_1_key1_in_sel_1_wd;
+ logic com_sel_ctl_1_key1_in_sel_1_busy;
logic com_sel_ctl_1_key2_in_sel_1_qs;
logic com_sel_ctl_1_key2_in_sel_1_wd;
+ logic com_sel_ctl_1_key2_in_sel_1_busy;
logic com_sel_ctl_1_pwrb_in_sel_1_qs;
logic com_sel_ctl_1_pwrb_in_sel_1_wd;
+ logic com_sel_ctl_1_pwrb_in_sel_1_busy;
logic com_sel_ctl_1_ac_present_sel_1_qs;
logic com_sel_ctl_1_ac_present_sel_1_wd;
+ logic com_sel_ctl_1_ac_present_sel_1_busy;
logic com_sel_ctl_2_we;
logic com_sel_ctl_2_key0_in_sel_2_qs;
logic com_sel_ctl_2_key0_in_sel_2_wd;
+ logic com_sel_ctl_2_key0_in_sel_2_busy;
logic com_sel_ctl_2_key1_in_sel_2_qs;
logic com_sel_ctl_2_key1_in_sel_2_wd;
+ logic com_sel_ctl_2_key1_in_sel_2_busy;
logic com_sel_ctl_2_key2_in_sel_2_qs;
logic com_sel_ctl_2_key2_in_sel_2_wd;
+ logic com_sel_ctl_2_key2_in_sel_2_busy;
logic com_sel_ctl_2_pwrb_in_sel_2_qs;
logic com_sel_ctl_2_pwrb_in_sel_2_wd;
+ logic com_sel_ctl_2_pwrb_in_sel_2_busy;
logic com_sel_ctl_2_ac_present_sel_2_qs;
logic com_sel_ctl_2_ac_present_sel_2_wd;
+ logic com_sel_ctl_2_ac_present_sel_2_busy;
logic com_sel_ctl_3_we;
logic com_sel_ctl_3_key0_in_sel_3_qs;
logic com_sel_ctl_3_key0_in_sel_3_wd;
+ logic com_sel_ctl_3_key0_in_sel_3_busy;
logic com_sel_ctl_3_key1_in_sel_3_qs;
logic com_sel_ctl_3_key1_in_sel_3_wd;
+ logic com_sel_ctl_3_key1_in_sel_3_busy;
logic com_sel_ctl_3_key2_in_sel_3_qs;
logic com_sel_ctl_3_key2_in_sel_3_wd;
+ logic com_sel_ctl_3_key2_in_sel_3_busy;
logic com_sel_ctl_3_pwrb_in_sel_3_qs;
logic com_sel_ctl_3_pwrb_in_sel_3_wd;
+ logic com_sel_ctl_3_pwrb_in_sel_3_busy;
logic com_sel_ctl_3_ac_present_sel_3_qs;
logic com_sel_ctl_3_ac_present_sel_3_wd;
+ logic com_sel_ctl_3_ac_present_sel_3_busy;
logic com_det_ctl_0_we;
logic [31:0] com_det_ctl_0_qs;
logic [31:0] com_det_ctl_0_wd;
+ logic com_det_ctl_0_busy;
logic com_det_ctl_1_we;
logic [31:0] com_det_ctl_1_qs;
logic [31:0] com_det_ctl_1_wd;
+ logic com_det_ctl_1_busy;
logic com_det_ctl_2_we;
logic [31:0] com_det_ctl_2_qs;
logic [31:0] com_det_ctl_2_wd;
+ logic com_det_ctl_2_busy;
logic com_det_ctl_3_we;
logic [31:0] com_det_ctl_3_qs;
logic [31:0] com_det_ctl_3_wd;
+ logic com_det_ctl_3_busy;
logic com_out_ctl_0_we;
logic com_out_ctl_0_bat_disable_0_qs;
logic com_out_ctl_0_bat_disable_0_wd;
+ logic com_out_ctl_0_bat_disable_0_busy;
logic com_out_ctl_0_interrupt_0_qs;
logic com_out_ctl_0_interrupt_0_wd;
+ logic com_out_ctl_0_interrupt_0_busy;
logic com_out_ctl_0_ec_rst_0_qs;
logic com_out_ctl_0_ec_rst_0_wd;
+ logic com_out_ctl_0_ec_rst_0_busy;
logic com_out_ctl_0_gsc_rst_0_qs;
logic com_out_ctl_0_gsc_rst_0_wd;
+ logic com_out_ctl_0_gsc_rst_0_busy;
logic com_out_ctl_1_we;
logic com_out_ctl_1_bat_disable_1_qs;
logic com_out_ctl_1_bat_disable_1_wd;
+ logic com_out_ctl_1_bat_disable_1_busy;
logic com_out_ctl_1_interrupt_1_qs;
logic com_out_ctl_1_interrupt_1_wd;
+ logic com_out_ctl_1_interrupt_1_busy;
logic com_out_ctl_1_ec_rst_1_qs;
logic com_out_ctl_1_ec_rst_1_wd;
+ logic com_out_ctl_1_ec_rst_1_busy;
logic com_out_ctl_1_gsc_rst_1_qs;
logic com_out_ctl_1_gsc_rst_1_wd;
+ logic com_out_ctl_1_gsc_rst_1_busy;
logic com_out_ctl_2_we;
logic com_out_ctl_2_bat_disable_2_qs;
logic com_out_ctl_2_bat_disable_2_wd;
+ logic com_out_ctl_2_bat_disable_2_busy;
logic com_out_ctl_2_interrupt_2_qs;
logic com_out_ctl_2_interrupt_2_wd;
+ logic com_out_ctl_2_interrupt_2_busy;
logic com_out_ctl_2_ec_rst_2_qs;
logic com_out_ctl_2_ec_rst_2_wd;
+ logic com_out_ctl_2_ec_rst_2_busy;
logic com_out_ctl_2_gsc_rst_2_qs;
logic com_out_ctl_2_gsc_rst_2_wd;
+ logic com_out_ctl_2_gsc_rst_2_busy;
logic com_out_ctl_3_we;
logic com_out_ctl_3_bat_disable_3_qs;
logic com_out_ctl_3_bat_disable_3_wd;
+ logic com_out_ctl_3_bat_disable_3_busy;
logic com_out_ctl_3_interrupt_3_qs;
logic com_out_ctl_3_interrupt_3_wd;
+ logic com_out_ctl_3_interrupt_3_busy;
logic com_out_ctl_3_ec_rst_3_qs;
logic com_out_ctl_3_ec_rst_3_wd;
+ logic com_out_ctl_3_ec_rst_3_busy;
logic com_out_ctl_3_gsc_rst_3_qs;
logic com_out_ctl_3_gsc_rst_3_wd;
+ logic com_out_ctl_3_gsc_rst_3_busy;
logic combo_intr_status_we;
logic combo_intr_status_combo0_h2l_qs;
logic combo_intr_status_combo0_h2l_wd;
@@ -523,163 +641,139 @@
// R[ec_rst_ctl]: V(False)
- prim_subreg #(
+ prim_subreg_async #(
.DW (16),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (16'h7d0)
) u_ec_rst_ctl (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (ec_rst_ctl_we & regwen_qs),
- .wd (ec_rst_ctl_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (reg2hw.ec_rst_ctl.qe),
- .q (reg2hw.ec_rst_ctl.q),
-
- // to register interface (read)
- .qs (ec_rst_ctl_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (ec_rst_ctl_we & regwen_qs),
+ .src_wd_i (ec_rst_ctl_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (ec_rst_ctl_busy),
+ .src_qs_o (ec_rst_ctl_qs),
+ .dst_qe_o (),
+ .q (reg2hw.ec_rst_ctl.q)
);
// R[ulp_ac_debounce_ctl]: V(False)
- prim_subreg #(
+ prim_subreg_async #(
.DW (16),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (16'h1f40)
) u_ulp_ac_debounce_ctl (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (ulp_ac_debounce_ctl_we & regwen_qs),
- .wd (ulp_ac_debounce_ctl_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (reg2hw.ulp_ac_debounce_ctl.qe),
- .q (reg2hw.ulp_ac_debounce_ctl.q),
-
- // to register interface (read)
- .qs (ulp_ac_debounce_ctl_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (ulp_ac_debounce_ctl_we & regwen_qs),
+ .src_wd_i (ulp_ac_debounce_ctl_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (ulp_ac_debounce_ctl_busy),
+ .src_qs_o (ulp_ac_debounce_ctl_qs),
+ .dst_qe_o (),
+ .q (reg2hw.ulp_ac_debounce_ctl.q)
);
// R[ulp_lid_debounce_ctl]: V(False)
- prim_subreg #(
+ prim_subreg_async #(
.DW (16),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (16'h1f40)
) u_ulp_lid_debounce_ctl (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (ulp_lid_debounce_ctl_we & regwen_qs),
- .wd (ulp_lid_debounce_ctl_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (reg2hw.ulp_lid_debounce_ctl.qe),
- .q (reg2hw.ulp_lid_debounce_ctl.q),
-
- // to register interface (read)
- .qs (ulp_lid_debounce_ctl_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (ulp_lid_debounce_ctl_we & regwen_qs),
+ .src_wd_i (ulp_lid_debounce_ctl_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (ulp_lid_debounce_ctl_busy),
+ .src_qs_o (ulp_lid_debounce_ctl_qs),
+ .dst_qe_o (),
+ .q (reg2hw.ulp_lid_debounce_ctl.q)
);
// R[ulp_pwrb_debounce_ctl]: V(False)
- prim_subreg #(
+ prim_subreg_async #(
.DW (16),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (16'h1f40)
) u_ulp_pwrb_debounce_ctl (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (ulp_pwrb_debounce_ctl_we & regwen_qs),
- .wd (ulp_pwrb_debounce_ctl_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (reg2hw.ulp_pwrb_debounce_ctl.qe),
- .q (reg2hw.ulp_pwrb_debounce_ctl.q),
-
- // to register interface (read)
- .qs (ulp_pwrb_debounce_ctl_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (ulp_pwrb_debounce_ctl_we & regwen_qs),
+ .src_wd_i (ulp_pwrb_debounce_ctl_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (ulp_pwrb_debounce_ctl_busy),
+ .src_qs_o (ulp_pwrb_debounce_ctl_qs),
+ .dst_qe_o (),
+ .q (reg2hw.ulp_pwrb_debounce_ctl.q)
);
// R[ulp_ctl]: V(False)
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_ulp_ctl (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (ulp_ctl_we),
- .wd (ulp_ctl_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.ulp_ctl.q),
-
- // to register interface (read)
- .qs (ulp_ctl_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (ulp_ctl_we),
+ .src_wd_i (ulp_ctl_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (ulp_ctl_busy),
+ .src_qs_o (ulp_ctl_qs),
+ .dst_qe_o (),
+ .q (reg2hw.ulp_ctl.q)
);
// R[ulp_status]: V(False)
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW1C),
.RESVAL (1'h0)
) u_ulp_status (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (ulp_status_we),
- .wd (ulp_status_wd),
-
- // from internal hardware
- .de (hw2reg.ulp_status.de),
- .d (hw2reg.ulp_status.d),
-
- // to internal hardware
- .qe (),
- .q (),
-
- // to register interface (read)
- .qs (ulp_status_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (ulp_status_we),
+ .src_wd_i (ulp_status_wd),
+ .dst_de_i (hw2reg.ulp_status.de),
+ .dst_d_i (hw2reg.ulp_status.d),
+ .src_busy_o (ulp_status_busy),
+ .src_qs_o (ulp_status_qs),
+ .dst_qe_o (),
+ .q ()
);
@@ -713,1048 +807,888 @@
// R[key_invert_ctl]: V(False)
// F[key0_in]: 0:0
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_key_invert_ctl_key0_in (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (key_invert_ctl_we & regwen_qs),
- .wd (key_invert_ctl_key0_in_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.key_invert_ctl.key0_in.q),
-
- // to register interface (read)
- .qs (key_invert_ctl_key0_in_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (key_invert_ctl_we & regwen_qs),
+ .src_wd_i (key_invert_ctl_key0_in_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (key_invert_ctl_key0_in_busy),
+ .src_qs_o (key_invert_ctl_key0_in_qs),
+ .dst_qe_o (),
+ .q (reg2hw.key_invert_ctl.key0_in.q)
);
// F[key0_out]: 1:1
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_key_invert_ctl_key0_out (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (key_invert_ctl_we & regwen_qs),
- .wd (key_invert_ctl_key0_out_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.key_invert_ctl.key0_out.q),
-
- // to register interface (read)
- .qs (key_invert_ctl_key0_out_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (key_invert_ctl_we & regwen_qs),
+ .src_wd_i (key_invert_ctl_key0_out_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (key_invert_ctl_key0_out_busy),
+ .src_qs_o (key_invert_ctl_key0_out_qs),
+ .dst_qe_o (),
+ .q (reg2hw.key_invert_ctl.key0_out.q)
);
// F[key1_in]: 2:2
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_key_invert_ctl_key1_in (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (key_invert_ctl_we & regwen_qs),
- .wd (key_invert_ctl_key1_in_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.key_invert_ctl.key1_in.q),
-
- // to register interface (read)
- .qs (key_invert_ctl_key1_in_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (key_invert_ctl_we & regwen_qs),
+ .src_wd_i (key_invert_ctl_key1_in_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (key_invert_ctl_key1_in_busy),
+ .src_qs_o (key_invert_ctl_key1_in_qs),
+ .dst_qe_o (),
+ .q (reg2hw.key_invert_ctl.key1_in.q)
);
// F[key1_out]: 3:3
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_key_invert_ctl_key1_out (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (key_invert_ctl_we & regwen_qs),
- .wd (key_invert_ctl_key1_out_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.key_invert_ctl.key1_out.q),
-
- // to register interface (read)
- .qs (key_invert_ctl_key1_out_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (key_invert_ctl_we & regwen_qs),
+ .src_wd_i (key_invert_ctl_key1_out_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (key_invert_ctl_key1_out_busy),
+ .src_qs_o (key_invert_ctl_key1_out_qs),
+ .dst_qe_o (),
+ .q (reg2hw.key_invert_ctl.key1_out.q)
);
// F[key2_in]: 4:4
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_key_invert_ctl_key2_in (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (key_invert_ctl_we & regwen_qs),
- .wd (key_invert_ctl_key2_in_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.key_invert_ctl.key2_in.q),
-
- // to register interface (read)
- .qs (key_invert_ctl_key2_in_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (key_invert_ctl_we & regwen_qs),
+ .src_wd_i (key_invert_ctl_key2_in_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (key_invert_ctl_key2_in_busy),
+ .src_qs_o (key_invert_ctl_key2_in_qs),
+ .dst_qe_o (),
+ .q (reg2hw.key_invert_ctl.key2_in.q)
);
// F[key2_out]: 5:5
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_key_invert_ctl_key2_out (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (key_invert_ctl_we & regwen_qs),
- .wd (key_invert_ctl_key2_out_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.key_invert_ctl.key2_out.q),
-
- // to register interface (read)
- .qs (key_invert_ctl_key2_out_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (key_invert_ctl_we & regwen_qs),
+ .src_wd_i (key_invert_ctl_key2_out_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (key_invert_ctl_key2_out_busy),
+ .src_qs_o (key_invert_ctl_key2_out_qs),
+ .dst_qe_o (),
+ .q (reg2hw.key_invert_ctl.key2_out.q)
);
// F[pwrb_in]: 6:6
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_key_invert_ctl_pwrb_in (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (key_invert_ctl_we & regwen_qs),
- .wd (key_invert_ctl_pwrb_in_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.key_invert_ctl.pwrb_in.q),
-
- // to register interface (read)
- .qs (key_invert_ctl_pwrb_in_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (key_invert_ctl_we & regwen_qs),
+ .src_wd_i (key_invert_ctl_pwrb_in_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (key_invert_ctl_pwrb_in_busy),
+ .src_qs_o (key_invert_ctl_pwrb_in_qs),
+ .dst_qe_o (),
+ .q (reg2hw.key_invert_ctl.pwrb_in.q)
);
// F[pwrb_out]: 7:7
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_key_invert_ctl_pwrb_out (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (key_invert_ctl_we & regwen_qs),
- .wd (key_invert_ctl_pwrb_out_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.key_invert_ctl.pwrb_out.q),
-
- // to register interface (read)
- .qs (key_invert_ctl_pwrb_out_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (key_invert_ctl_we & regwen_qs),
+ .src_wd_i (key_invert_ctl_pwrb_out_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (key_invert_ctl_pwrb_out_busy),
+ .src_qs_o (key_invert_ctl_pwrb_out_qs),
+ .dst_qe_o (),
+ .q (reg2hw.key_invert_ctl.pwrb_out.q)
);
// F[ac_present]: 8:8
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_key_invert_ctl_ac_present (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (key_invert_ctl_we & regwen_qs),
- .wd (key_invert_ctl_ac_present_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.key_invert_ctl.ac_present.q),
-
- // to register interface (read)
- .qs (key_invert_ctl_ac_present_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (key_invert_ctl_we & regwen_qs),
+ .src_wd_i (key_invert_ctl_ac_present_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (key_invert_ctl_ac_present_busy),
+ .src_qs_o (key_invert_ctl_ac_present_qs),
+ .dst_qe_o (),
+ .q (reg2hw.key_invert_ctl.ac_present.q)
);
// F[bat_disable]: 9:9
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_key_invert_ctl_bat_disable (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (key_invert_ctl_we & regwen_qs),
- .wd (key_invert_ctl_bat_disable_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.key_invert_ctl.bat_disable.q),
-
- // to register interface (read)
- .qs (key_invert_ctl_bat_disable_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (key_invert_ctl_we & regwen_qs),
+ .src_wd_i (key_invert_ctl_bat_disable_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (key_invert_ctl_bat_disable_busy),
+ .src_qs_o (key_invert_ctl_bat_disable_qs),
+ .dst_qe_o (),
+ .q (reg2hw.key_invert_ctl.bat_disable.q)
);
// F[lid_open]: 10:10
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_key_invert_ctl_lid_open (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (key_invert_ctl_we & regwen_qs),
- .wd (key_invert_ctl_lid_open_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.key_invert_ctl.lid_open.q),
-
- // to register interface (read)
- .qs (key_invert_ctl_lid_open_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (key_invert_ctl_we & regwen_qs),
+ .src_wd_i (key_invert_ctl_lid_open_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (key_invert_ctl_lid_open_busy),
+ .src_qs_o (key_invert_ctl_lid_open_qs),
+ .dst_qe_o (),
+ .q (reg2hw.key_invert_ctl.lid_open.q)
);
// F[z3_wakeup]: 11:11
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_key_invert_ctl_z3_wakeup (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (key_invert_ctl_we & regwen_qs),
- .wd (key_invert_ctl_z3_wakeup_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.key_invert_ctl.z3_wakeup.q),
-
- // to register interface (read)
- .qs (key_invert_ctl_z3_wakeup_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (key_invert_ctl_we & regwen_qs),
+ .src_wd_i (key_invert_ctl_z3_wakeup_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (key_invert_ctl_z3_wakeup_busy),
+ .src_qs_o (key_invert_ctl_z3_wakeup_qs),
+ .dst_qe_o (),
+ .q (reg2hw.key_invert_ctl.z3_wakeup.q)
);
// R[pin_allowed_ctl]: V(False)
// F[bat_disable_0]: 0:0
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_pin_allowed_ctl_bat_disable_0 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (pin_allowed_ctl_we & regwen_qs),
- .wd (pin_allowed_ctl_bat_disable_0_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.pin_allowed_ctl.bat_disable_0.q),
-
- // to register interface (read)
- .qs (pin_allowed_ctl_bat_disable_0_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (pin_allowed_ctl_we & regwen_qs),
+ .src_wd_i (pin_allowed_ctl_bat_disable_0_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (pin_allowed_ctl_bat_disable_0_busy),
+ .src_qs_o (pin_allowed_ctl_bat_disable_0_qs),
+ .dst_qe_o (),
+ .q (reg2hw.pin_allowed_ctl.bat_disable_0.q)
);
// F[ec_rst_l_0]: 1:1
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h1)
) u_pin_allowed_ctl_ec_rst_l_0 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (pin_allowed_ctl_we & regwen_qs),
- .wd (pin_allowed_ctl_ec_rst_l_0_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.pin_allowed_ctl.ec_rst_l_0.q),
-
- // to register interface (read)
- .qs (pin_allowed_ctl_ec_rst_l_0_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (pin_allowed_ctl_we & regwen_qs),
+ .src_wd_i (pin_allowed_ctl_ec_rst_l_0_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (pin_allowed_ctl_ec_rst_l_0_busy),
+ .src_qs_o (pin_allowed_ctl_ec_rst_l_0_qs),
+ .dst_qe_o (),
+ .q (reg2hw.pin_allowed_ctl.ec_rst_l_0.q)
);
// F[pwrb_out_0]: 2:2
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_pin_allowed_ctl_pwrb_out_0 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (pin_allowed_ctl_we & regwen_qs),
- .wd (pin_allowed_ctl_pwrb_out_0_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.pin_allowed_ctl.pwrb_out_0.q),
-
- // to register interface (read)
- .qs (pin_allowed_ctl_pwrb_out_0_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (pin_allowed_ctl_we & regwen_qs),
+ .src_wd_i (pin_allowed_ctl_pwrb_out_0_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (pin_allowed_ctl_pwrb_out_0_busy),
+ .src_qs_o (pin_allowed_ctl_pwrb_out_0_qs),
+ .dst_qe_o (),
+ .q (reg2hw.pin_allowed_ctl.pwrb_out_0.q)
);
// F[key0_out_0]: 3:3
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_pin_allowed_ctl_key0_out_0 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (pin_allowed_ctl_we & regwen_qs),
- .wd (pin_allowed_ctl_key0_out_0_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.pin_allowed_ctl.key0_out_0.q),
-
- // to register interface (read)
- .qs (pin_allowed_ctl_key0_out_0_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (pin_allowed_ctl_we & regwen_qs),
+ .src_wd_i (pin_allowed_ctl_key0_out_0_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (pin_allowed_ctl_key0_out_0_busy),
+ .src_qs_o (pin_allowed_ctl_key0_out_0_qs),
+ .dst_qe_o (),
+ .q (reg2hw.pin_allowed_ctl.key0_out_0.q)
);
// F[key1_out_0]: 4:4
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_pin_allowed_ctl_key1_out_0 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (pin_allowed_ctl_we & regwen_qs),
- .wd (pin_allowed_ctl_key1_out_0_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.pin_allowed_ctl.key1_out_0.q),
-
- // to register interface (read)
- .qs (pin_allowed_ctl_key1_out_0_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (pin_allowed_ctl_we & regwen_qs),
+ .src_wd_i (pin_allowed_ctl_key1_out_0_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (pin_allowed_ctl_key1_out_0_busy),
+ .src_qs_o (pin_allowed_ctl_key1_out_0_qs),
+ .dst_qe_o (),
+ .q (reg2hw.pin_allowed_ctl.key1_out_0.q)
);
// F[key2_out_0]: 5:5
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_pin_allowed_ctl_key2_out_0 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (pin_allowed_ctl_we & regwen_qs),
- .wd (pin_allowed_ctl_key2_out_0_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.pin_allowed_ctl.key2_out_0.q),
-
- // to register interface (read)
- .qs (pin_allowed_ctl_key2_out_0_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (pin_allowed_ctl_we & regwen_qs),
+ .src_wd_i (pin_allowed_ctl_key2_out_0_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (pin_allowed_ctl_key2_out_0_busy),
+ .src_qs_o (pin_allowed_ctl_key2_out_0_qs),
+ .dst_qe_o (),
+ .q (reg2hw.pin_allowed_ctl.key2_out_0.q)
);
// F[z3_wakeup_0]: 6:6
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_pin_allowed_ctl_z3_wakeup_0 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (pin_allowed_ctl_we & regwen_qs),
- .wd (pin_allowed_ctl_z3_wakeup_0_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.pin_allowed_ctl.z3_wakeup_0.q),
-
- // to register interface (read)
- .qs (pin_allowed_ctl_z3_wakeup_0_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (pin_allowed_ctl_we & regwen_qs),
+ .src_wd_i (pin_allowed_ctl_z3_wakeup_0_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (pin_allowed_ctl_z3_wakeup_0_busy),
+ .src_qs_o (pin_allowed_ctl_z3_wakeup_0_qs),
+ .dst_qe_o (),
+ .q (reg2hw.pin_allowed_ctl.z3_wakeup_0.q)
);
// F[bat_disable_1]: 7:7
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_pin_allowed_ctl_bat_disable_1 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (pin_allowed_ctl_we & regwen_qs),
- .wd (pin_allowed_ctl_bat_disable_1_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.pin_allowed_ctl.bat_disable_1.q),
-
- // to register interface (read)
- .qs (pin_allowed_ctl_bat_disable_1_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (pin_allowed_ctl_we & regwen_qs),
+ .src_wd_i (pin_allowed_ctl_bat_disable_1_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (pin_allowed_ctl_bat_disable_1_busy),
+ .src_qs_o (pin_allowed_ctl_bat_disable_1_qs),
+ .dst_qe_o (),
+ .q (reg2hw.pin_allowed_ctl.bat_disable_1.q)
);
// F[ec_rst_l_1]: 8:8
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_pin_allowed_ctl_ec_rst_l_1 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (pin_allowed_ctl_we & regwen_qs),
- .wd (pin_allowed_ctl_ec_rst_l_1_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.pin_allowed_ctl.ec_rst_l_1.q),
-
- // to register interface (read)
- .qs (pin_allowed_ctl_ec_rst_l_1_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (pin_allowed_ctl_we & regwen_qs),
+ .src_wd_i (pin_allowed_ctl_ec_rst_l_1_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (pin_allowed_ctl_ec_rst_l_1_busy),
+ .src_qs_o (pin_allowed_ctl_ec_rst_l_1_qs),
+ .dst_qe_o (),
+ .q (reg2hw.pin_allowed_ctl.ec_rst_l_1.q)
);
// F[pwrb_out_1]: 9:9
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_pin_allowed_ctl_pwrb_out_1 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (pin_allowed_ctl_we & regwen_qs),
- .wd (pin_allowed_ctl_pwrb_out_1_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.pin_allowed_ctl.pwrb_out_1.q),
-
- // to register interface (read)
- .qs (pin_allowed_ctl_pwrb_out_1_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (pin_allowed_ctl_we & regwen_qs),
+ .src_wd_i (pin_allowed_ctl_pwrb_out_1_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (pin_allowed_ctl_pwrb_out_1_busy),
+ .src_qs_o (pin_allowed_ctl_pwrb_out_1_qs),
+ .dst_qe_o (),
+ .q (reg2hw.pin_allowed_ctl.pwrb_out_1.q)
);
// F[key0_out_1]: 10:10
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_pin_allowed_ctl_key0_out_1 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (pin_allowed_ctl_we & regwen_qs),
- .wd (pin_allowed_ctl_key0_out_1_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.pin_allowed_ctl.key0_out_1.q),
-
- // to register interface (read)
- .qs (pin_allowed_ctl_key0_out_1_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (pin_allowed_ctl_we & regwen_qs),
+ .src_wd_i (pin_allowed_ctl_key0_out_1_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (pin_allowed_ctl_key0_out_1_busy),
+ .src_qs_o (pin_allowed_ctl_key0_out_1_qs),
+ .dst_qe_o (),
+ .q (reg2hw.pin_allowed_ctl.key0_out_1.q)
);
// F[key1_out_1]: 11:11
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_pin_allowed_ctl_key1_out_1 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (pin_allowed_ctl_we & regwen_qs),
- .wd (pin_allowed_ctl_key1_out_1_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.pin_allowed_ctl.key1_out_1.q),
-
- // to register interface (read)
- .qs (pin_allowed_ctl_key1_out_1_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (pin_allowed_ctl_we & regwen_qs),
+ .src_wd_i (pin_allowed_ctl_key1_out_1_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (pin_allowed_ctl_key1_out_1_busy),
+ .src_qs_o (pin_allowed_ctl_key1_out_1_qs),
+ .dst_qe_o (),
+ .q (reg2hw.pin_allowed_ctl.key1_out_1.q)
);
// F[key2_out_1]: 12:12
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_pin_allowed_ctl_key2_out_1 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (pin_allowed_ctl_we & regwen_qs),
- .wd (pin_allowed_ctl_key2_out_1_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.pin_allowed_ctl.key2_out_1.q),
-
- // to register interface (read)
- .qs (pin_allowed_ctl_key2_out_1_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (pin_allowed_ctl_we & regwen_qs),
+ .src_wd_i (pin_allowed_ctl_key2_out_1_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (pin_allowed_ctl_key2_out_1_busy),
+ .src_qs_o (pin_allowed_ctl_key2_out_1_qs),
+ .dst_qe_o (),
+ .q (reg2hw.pin_allowed_ctl.key2_out_1.q)
);
// F[z3_wakeup_1]: 13:13
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_pin_allowed_ctl_z3_wakeup_1 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (pin_allowed_ctl_we & regwen_qs),
- .wd (pin_allowed_ctl_z3_wakeup_1_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.pin_allowed_ctl.z3_wakeup_1.q),
-
- // to register interface (read)
- .qs (pin_allowed_ctl_z3_wakeup_1_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (pin_allowed_ctl_we & regwen_qs),
+ .src_wd_i (pin_allowed_ctl_z3_wakeup_1_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (pin_allowed_ctl_z3_wakeup_1_busy),
+ .src_qs_o (pin_allowed_ctl_z3_wakeup_1_qs),
+ .dst_qe_o (),
+ .q (reg2hw.pin_allowed_ctl.z3_wakeup_1.q)
);
// R[pin_out_ctl]: V(False)
// F[bat_disable]: 0:0
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_pin_out_ctl_bat_disable (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (pin_out_ctl_we),
- .wd (pin_out_ctl_bat_disable_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.pin_out_ctl.bat_disable.q),
-
- // to register interface (read)
- .qs (pin_out_ctl_bat_disable_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (pin_out_ctl_we),
+ .src_wd_i (pin_out_ctl_bat_disable_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (pin_out_ctl_bat_disable_busy),
+ .src_qs_o (pin_out_ctl_bat_disable_qs),
+ .dst_qe_o (),
+ .q (reg2hw.pin_out_ctl.bat_disable.q)
);
// F[ec_rst_l]: 1:1
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h1)
) u_pin_out_ctl_ec_rst_l (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (pin_out_ctl_we),
- .wd (pin_out_ctl_ec_rst_l_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.pin_out_ctl.ec_rst_l.q),
-
- // to register interface (read)
- .qs (pin_out_ctl_ec_rst_l_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (pin_out_ctl_we),
+ .src_wd_i (pin_out_ctl_ec_rst_l_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (pin_out_ctl_ec_rst_l_busy),
+ .src_qs_o (pin_out_ctl_ec_rst_l_qs),
+ .dst_qe_o (),
+ .q (reg2hw.pin_out_ctl.ec_rst_l.q)
);
// F[pwrb_out]: 2:2
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_pin_out_ctl_pwrb_out (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (pin_out_ctl_we),
- .wd (pin_out_ctl_pwrb_out_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.pin_out_ctl.pwrb_out.q),
-
- // to register interface (read)
- .qs (pin_out_ctl_pwrb_out_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (pin_out_ctl_we),
+ .src_wd_i (pin_out_ctl_pwrb_out_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (pin_out_ctl_pwrb_out_busy),
+ .src_qs_o (pin_out_ctl_pwrb_out_qs),
+ .dst_qe_o (),
+ .q (reg2hw.pin_out_ctl.pwrb_out.q)
);
// F[key0_out]: 3:3
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_pin_out_ctl_key0_out (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (pin_out_ctl_we),
- .wd (pin_out_ctl_key0_out_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.pin_out_ctl.key0_out.q),
-
- // to register interface (read)
- .qs (pin_out_ctl_key0_out_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (pin_out_ctl_we),
+ .src_wd_i (pin_out_ctl_key0_out_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (pin_out_ctl_key0_out_busy),
+ .src_qs_o (pin_out_ctl_key0_out_qs),
+ .dst_qe_o (),
+ .q (reg2hw.pin_out_ctl.key0_out.q)
);
// F[key1_out]: 4:4
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_pin_out_ctl_key1_out (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (pin_out_ctl_we),
- .wd (pin_out_ctl_key1_out_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.pin_out_ctl.key1_out.q),
-
- // to register interface (read)
- .qs (pin_out_ctl_key1_out_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (pin_out_ctl_we),
+ .src_wd_i (pin_out_ctl_key1_out_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (pin_out_ctl_key1_out_busy),
+ .src_qs_o (pin_out_ctl_key1_out_qs),
+ .dst_qe_o (),
+ .q (reg2hw.pin_out_ctl.key1_out.q)
);
// F[key2_out]: 5:5
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_pin_out_ctl_key2_out (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (pin_out_ctl_we),
- .wd (pin_out_ctl_key2_out_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.pin_out_ctl.key2_out.q),
-
- // to register interface (read)
- .qs (pin_out_ctl_key2_out_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (pin_out_ctl_we),
+ .src_wd_i (pin_out_ctl_key2_out_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (pin_out_ctl_key2_out_busy),
+ .src_qs_o (pin_out_ctl_key2_out_qs),
+ .dst_qe_o (),
+ .q (reg2hw.pin_out_ctl.key2_out.q)
);
// F[z3_wakeup]: 6:6
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_pin_out_ctl_z3_wakeup (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (pin_out_ctl_we),
- .wd (pin_out_ctl_z3_wakeup_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.pin_out_ctl.z3_wakeup.q),
-
- // to register interface (read)
- .qs (pin_out_ctl_z3_wakeup_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (pin_out_ctl_we),
+ .src_wd_i (pin_out_ctl_z3_wakeup_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (pin_out_ctl_z3_wakeup_busy),
+ .src_qs_o (pin_out_ctl_z3_wakeup_qs),
+ .dst_qe_o (),
+ .q (reg2hw.pin_out_ctl.z3_wakeup.q)
);
// R[pin_out_value]: V(False)
// F[bat_disable]: 0:0
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_pin_out_value_bat_disable (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (pin_out_value_we),
- .wd (pin_out_value_bat_disable_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.pin_out_value.bat_disable.q),
-
- // to register interface (read)
- .qs (pin_out_value_bat_disable_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (pin_out_value_we),
+ .src_wd_i (pin_out_value_bat_disable_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (pin_out_value_bat_disable_busy),
+ .src_qs_o (pin_out_value_bat_disable_qs),
+ .dst_qe_o (),
+ .q (reg2hw.pin_out_value.bat_disable.q)
);
// F[ec_rst_l]: 1:1
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_pin_out_value_ec_rst_l (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (pin_out_value_we),
- .wd (pin_out_value_ec_rst_l_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.pin_out_value.ec_rst_l.q),
-
- // to register interface (read)
- .qs (pin_out_value_ec_rst_l_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (pin_out_value_we),
+ .src_wd_i (pin_out_value_ec_rst_l_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (pin_out_value_ec_rst_l_busy),
+ .src_qs_o (pin_out_value_ec_rst_l_qs),
+ .dst_qe_o (),
+ .q (reg2hw.pin_out_value.ec_rst_l.q)
);
// F[pwrb_out]: 2:2
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_pin_out_value_pwrb_out (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (pin_out_value_we),
- .wd (pin_out_value_pwrb_out_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.pin_out_value.pwrb_out.q),
-
- // to register interface (read)
- .qs (pin_out_value_pwrb_out_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (pin_out_value_we),
+ .src_wd_i (pin_out_value_pwrb_out_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (pin_out_value_pwrb_out_busy),
+ .src_qs_o (pin_out_value_pwrb_out_qs),
+ .dst_qe_o (),
+ .q (reg2hw.pin_out_value.pwrb_out.q)
);
// F[key0_out]: 3:3
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_pin_out_value_key0_out (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (pin_out_value_we),
- .wd (pin_out_value_key0_out_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.pin_out_value.key0_out.q),
-
- // to register interface (read)
- .qs (pin_out_value_key0_out_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (pin_out_value_we),
+ .src_wd_i (pin_out_value_key0_out_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (pin_out_value_key0_out_busy),
+ .src_qs_o (pin_out_value_key0_out_qs),
+ .dst_qe_o (),
+ .q (reg2hw.pin_out_value.key0_out.q)
);
// F[key1_out]: 4:4
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_pin_out_value_key1_out (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (pin_out_value_we),
- .wd (pin_out_value_key1_out_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.pin_out_value.key1_out.q),
-
- // to register interface (read)
- .qs (pin_out_value_key1_out_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (pin_out_value_we),
+ .src_wd_i (pin_out_value_key1_out_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (pin_out_value_key1_out_busy),
+ .src_qs_o (pin_out_value_key1_out_qs),
+ .dst_qe_o (),
+ .q (reg2hw.pin_out_value.key1_out.q)
);
// F[key2_out]: 5:5
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_pin_out_value_key2_out (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (pin_out_value_we),
- .wd (pin_out_value_key2_out_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.pin_out_value.key2_out.q),
-
- // to register interface (read)
- .qs (pin_out_value_key2_out_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (pin_out_value_we),
+ .src_wd_i (pin_out_value_key2_out_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (pin_out_value_key2_out_busy),
+ .src_qs_o (pin_out_value_key2_out_qs),
+ .dst_qe_o (),
+ .q (reg2hw.pin_out_value.key2_out.q)
);
// F[z3_wakeup]: 6:6
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_pin_out_value_z3_wakeup (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (pin_out_value_we),
- .wd (pin_out_value_z3_wakeup_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.pin_out_value.z3_wakeup.q),
-
- // to register interface (read)
- .qs (pin_out_value_z3_wakeup_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (pin_out_value_we),
+ .src_wd_i (pin_out_value_z3_wakeup_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (pin_out_value_z3_wakeup_busy),
+ .src_qs_o (pin_out_value_z3_wakeup_qs),
+ .dst_qe_o (),
+ .q (reg2hw.pin_out_value.z3_wakeup.q)
);
@@ -1945,553 +1879,469 @@
// R[key_intr_ctl]: V(False)
// F[pwrb_in_h2l]: 0:0
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_key_intr_ctl_pwrb_in_h2l (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (key_intr_ctl_we & regwen_qs),
- .wd (key_intr_ctl_pwrb_in_h2l_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.key_intr_ctl.pwrb_in_h2l.q),
-
- // to register interface (read)
- .qs (key_intr_ctl_pwrb_in_h2l_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (key_intr_ctl_we & regwen_qs),
+ .src_wd_i (key_intr_ctl_pwrb_in_h2l_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (key_intr_ctl_pwrb_in_h2l_busy),
+ .src_qs_o (key_intr_ctl_pwrb_in_h2l_qs),
+ .dst_qe_o (),
+ .q (reg2hw.key_intr_ctl.pwrb_in_h2l.q)
);
// F[key0_in_h2l]: 1:1
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_key_intr_ctl_key0_in_h2l (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (key_intr_ctl_we & regwen_qs),
- .wd (key_intr_ctl_key0_in_h2l_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.key_intr_ctl.key0_in_h2l.q),
-
- // to register interface (read)
- .qs (key_intr_ctl_key0_in_h2l_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (key_intr_ctl_we & regwen_qs),
+ .src_wd_i (key_intr_ctl_key0_in_h2l_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (key_intr_ctl_key0_in_h2l_busy),
+ .src_qs_o (key_intr_ctl_key0_in_h2l_qs),
+ .dst_qe_o (),
+ .q (reg2hw.key_intr_ctl.key0_in_h2l.q)
);
// F[key1_in_h2l]: 2:2
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_key_intr_ctl_key1_in_h2l (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (key_intr_ctl_we & regwen_qs),
- .wd (key_intr_ctl_key1_in_h2l_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.key_intr_ctl.key1_in_h2l.q),
-
- // to register interface (read)
- .qs (key_intr_ctl_key1_in_h2l_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (key_intr_ctl_we & regwen_qs),
+ .src_wd_i (key_intr_ctl_key1_in_h2l_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (key_intr_ctl_key1_in_h2l_busy),
+ .src_qs_o (key_intr_ctl_key1_in_h2l_qs),
+ .dst_qe_o (),
+ .q (reg2hw.key_intr_ctl.key1_in_h2l.q)
);
// F[key2_in_h2l]: 3:3
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_key_intr_ctl_key2_in_h2l (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (key_intr_ctl_we & regwen_qs),
- .wd (key_intr_ctl_key2_in_h2l_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.key_intr_ctl.key2_in_h2l.q),
-
- // to register interface (read)
- .qs (key_intr_ctl_key2_in_h2l_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (key_intr_ctl_we & regwen_qs),
+ .src_wd_i (key_intr_ctl_key2_in_h2l_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (key_intr_ctl_key2_in_h2l_busy),
+ .src_qs_o (key_intr_ctl_key2_in_h2l_qs),
+ .dst_qe_o (),
+ .q (reg2hw.key_intr_ctl.key2_in_h2l.q)
);
// F[ac_present_h2l]: 4:4
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_key_intr_ctl_ac_present_h2l (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (key_intr_ctl_we & regwen_qs),
- .wd (key_intr_ctl_ac_present_h2l_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.key_intr_ctl.ac_present_h2l.q),
-
- // to register interface (read)
- .qs (key_intr_ctl_ac_present_h2l_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (key_intr_ctl_we & regwen_qs),
+ .src_wd_i (key_intr_ctl_ac_present_h2l_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (key_intr_ctl_ac_present_h2l_busy),
+ .src_qs_o (key_intr_ctl_ac_present_h2l_qs),
+ .dst_qe_o (),
+ .q (reg2hw.key_intr_ctl.ac_present_h2l.q)
);
// F[ec_rst_l_h2l]: 5:5
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_key_intr_ctl_ec_rst_l_h2l (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (key_intr_ctl_we & regwen_qs),
- .wd (key_intr_ctl_ec_rst_l_h2l_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.key_intr_ctl.ec_rst_l_h2l.q),
-
- // to register interface (read)
- .qs (key_intr_ctl_ec_rst_l_h2l_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (key_intr_ctl_we & regwen_qs),
+ .src_wd_i (key_intr_ctl_ec_rst_l_h2l_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (key_intr_ctl_ec_rst_l_h2l_busy),
+ .src_qs_o (key_intr_ctl_ec_rst_l_h2l_qs),
+ .dst_qe_o (),
+ .q (reg2hw.key_intr_ctl.ec_rst_l_h2l.q)
);
// F[pwrb_in_l2h]: 8:8
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_key_intr_ctl_pwrb_in_l2h (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (key_intr_ctl_we & regwen_qs),
- .wd (key_intr_ctl_pwrb_in_l2h_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.key_intr_ctl.pwrb_in_l2h.q),
-
- // to register interface (read)
- .qs (key_intr_ctl_pwrb_in_l2h_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (key_intr_ctl_we & regwen_qs),
+ .src_wd_i (key_intr_ctl_pwrb_in_l2h_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (key_intr_ctl_pwrb_in_l2h_busy),
+ .src_qs_o (key_intr_ctl_pwrb_in_l2h_qs),
+ .dst_qe_o (),
+ .q (reg2hw.key_intr_ctl.pwrb_in_l2h.q)
);
// F[key0_in_l2h]: 9:9
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_key_intr_ctl_key0_in_l2h (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (key_intr_ctl_we & regwen_qs),
- .wd (key_intr_ctl_key0_in_l2h_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.key_intr_ctl.key0_in_l2h.q),
-
- // to register interface (read)
- .qs (key_intr_ctl_key0_in_l2h_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (key_intr_ctl_we & regwen_qs),
+ .src_wd_i (key_intr_ctl_key0_in_l2h_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (key_intr_ctl_key0_in_l2h_busy),
+ .src_qs_o (key_intr_ctl_key0_in_l2h_qs),
+ .dst_qe_o (),
+ .q (reg2hw.key_intr_ctl.key0_in_l2h.q)
);
// F[key1_in_l2h]: 10:10
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_key_intr_ctl_key1_in_l2h (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (key_intr_ctl_we & regwen_qs),
- .wd (key_intr_ctl_key1_in_l2h_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.key_intr_ctl.key1_in_l2h.q),
-
- // to register interface (read)
- .qs (key_intr_ctl_key1_in_l2h_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (key_intr_ctl_we & regwen_qs),
+ .src_wd_i (key_intr_ctl_key1_in_l2h_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (key_intr_ctl_key1_in_l2h_busy),
+ .src_qs_o (key_intr_ctl_key1_in_l2h_qs),
+ .dst_qe_o (),
+ .q (reg2hw.key_intr_ctl.key1_in_l2h.q)
);
// F[key2_in_l2h]: 11:11
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_key_intr_ctl_key2_in_l2h (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (key_intr_ctl_we & regwen_qs),
- .wd (key_intr_ctl_key2_in_l2h_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.key_intr_ctl.key2_in_l2h.q),
-
- // to register interface (read)
- .qs (key_intr_ctl_key2_in_l2h_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (key_intr_ctl_we & regwen_qs),
+ .src_wd_i (key_intr_ctl_key2_in_l2h_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (key_intr_ctl_key2_in_l2h_busy),
+ .src_qs_o (key_intr_ctl_key2_in_l2h_qs),
+ .dst_qe_o (),
+ .q (reg2hw.key_intr_ctl.key2_in_l2h.q)
);
// F[ac_present_l2h]: 12:12
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_key_intr_ctl_ac_present_l2h (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (key_intr_ctl_we & regwen_qs),
- .wd (key_intr_ctl_ac_present_l2h_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.key_intr_ctl.ac_present_l2h.q),
-
- // to register interface (read)
- .qs (key_intr_ctl_ac_present_l2h_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (key_intr_ctl_we & regwen_qs),
+ .src_wd_i (key_intr_ctl_ac_present_l2h_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (key_intr_ctl_ac_present_l2h_busy),
+ .src_qs_o (key_intr_ctl_ac_present_l2h_qs),
+ .dst_qe_o (),
+ .q (reg2hw.key_intr_ctl.ac_present_l2h.q)
);
// F[ec_rst_l_l2h]: 13:13
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_key_intr_ctl_ec_rst_l_l2h (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (key_intr_ctl_we & regwen_qs),
- .wd (key_intr_ctl_ec_rst_l_l2h_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.key_intr_ctl.ec_rst_l_l2h.q),
-
- // to register interface (read)
- .qs (key_intr_ctl_ec_rst_l_l2h_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (key_intr_ctl_we & regwen_qs),
+ .src_wd_i (key_intr_ctl_ec_rst_l_l2h_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (key_intr_ctl_ec_rst_l_l2h_busy),
+ .src_qs_o (key_intr_ctl_ec_rst_l_l2h_qs),
+ .dst_qe_o (),
+ .q (reg2hw.key_intr_ctl.ec_rst_l_l2h.q)
);
// R[key_intr_debounce_ctl]: V(False)
- prim_subreg #(
+ prim_subreg_async #(
.DW (16),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (16'h0)
) u_key_intr_debounce_ctl (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (key_intr_debounce_ctl_we & regwen_qs),
- .wd (key_intr_debounce_ctl_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (reg2hw.key_intr_debounce_ctl.qe),
- .q (reg2hw.key_intr_debounce_ctl.q),
-
- // to register interface (read)
- .qs (key_intr_debounce_ctl_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (key_intr_debounce_ctl_we & regwen_qs),
+ .src_wd_i (key_intr_debounce_ctl_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (key_intr_debounce_ctl_busy),
+ .src_qs_o (key_intr_debounce_ctl_qs),
+ .dst_qe_o (),
+ .q (reg2hw.key_intr_debounce_ctl.q)
);
// R[auto_block_debounce_ctl]: V(False)
// F[debounce_timer]: 15:0
- prim_subreg #(
+ prim_subreg_async #(
.DW (16),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (16'h0)
) u_auto_block_debounce_ctl_debounce_timer (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (auto_block_debounce_ctl_we & regwen_qs),
- .wd (auto_block_debounce_ctl_debounce_timer_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (reg2hw.auto_block_debounce_ctl.debounce_timer.qe),
- .q (reg2hw.auto_block_debounce_ctl.debounce_timer.q),
-
- // to register interface (read)
- .qs (auto_block_debounce_ctl_debounce_timer_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (auto_block_debounce_ctl_we & regwen_qs),
+ .src_wd_i (auto_block_debounce_ctl_debounce_timer_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (auto_block_debounce_ctl_debounce_timer_busy),
+ .src_qs_o (auto_block_debounce_ctl_debounce_timer_qs),
+ .dst_qe_o (),
+ .q (reg2hw.auto_block_debounce_ctl.debounce_timer.q)
);
// F[auto_block_enable]: 16:16
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_auto_block_debounce_ctl_auto_block_enable (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (auto_block_debounce_ctl_we & regwen_qs),
- .wd (auto_block_debounce_ctl_auto_block_enable_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (reg2hw.auto_block_debounce_ctl.auto_block_enable.qe),
- .q (reg2hw.auto_block_debounce_ctl.auto_block_enable.q),
-
- // to register interface (read)
- .qs (auto_block_debounce_ctl_auto_block_enable_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (auto_block_debounce_ctl_we & regwen_qs),
+ .src_wd_i (auto_block_debounce_ctl_auto_block_enable_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (auto_block_debounce_ctl_auto_block_enable_busy),
+ .src_qs_o (auto_block_debounce_ctl_auto_block_enable_qs),
+ .dst_qe_o (),
+ .q (reg2hw.auto_block_debounce_ctl.auto_block_enable.q)
);
// R[auto_block_out_ctl]: V(False)
// F[key0_out_sel]: 0:0
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_auto_block_out_ctl_key0_out_sel (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (auto_block_out_ctl_we & regwen_qs),
- .wd (auto_block_out_ctl_key0_out_sel_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.auto_block_out_ctl.key0_out_sel.q),
-
- // to register interface (read)
- .qs (auto_block_out_ctl_key0_out_sel_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (auto_block_out_ctl_we & regwen_qs),
+ .src_wd_i (auto_block_out_ctl_key0_out_sel_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (auto_block_out_ctl_key0_out_sel_busy),
+ .src_qs_o (auto_block_out_ctl_key0_out_sel_qs),
+ .dst_qe_o (),
+ .q (reg2hw.auto_block_out_ctl.key0_out_sel.q)
);
// F[key1_out_sel]: 1:1
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_auto_block_out_ctl_key1_out_sel (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (auto_block_out_ctl_we & regwen_qs),
- .wd (auto_block_out_ctl_key1_out_sel_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.auto_block_out_ctl.key1_out_sel.q),
-
- // to register interface (read)
- .qs (auto_block_out_ctl_key1_out_sel_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (auto_block_out_ctl_we & regwen_qs),
+ .src_wd_i (auto_block_out_ctl_key1_out_sel_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (auto_block_out_ctl_key1_out_sel_busy),
+ .src_qs_o (auto_block_out_ctl_key1_out_sel_qs),
+ .dst_qe_o (),
+ .q (reg2hw.auto_block_out_ctl.key1_out_sel.q)
);
// F[key2_out_sel]: 2:2
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_auto_block_out_ctl_key2_out_sel (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (auto_block_out_ctl_we & regwen_qs),
- .wd (auto_block_out_ctl_key2_out_sel_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.auto_block_out_ctl.key2_out_sel.q),
-
- // to register interface (read)
- .qs (auto_block_out_ctl_key2_out_sel_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (auto_block_out_ctl_we & regwen_qs),
+ .src_wd_i (auto_block_out_ctl_key2_out_sel_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (auto_block_out_ctl_key2_out_sel_busy),
+ .src_qs_o (auto_block_out_ctl_key2_out_sel_qs),
+ .dst_qe_o (),
+ .q (reg2hw.auto_block_out_ctl.key2_out_sel.q)
);
// F[key0_out_value]: 4:4
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_auto_block_out_ctl_key0_out_value (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (auto_block_out_ctl_we & regwen_qs),
- .wd (auto_block_out_ctl_key0_out_value_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.auto_block_out_ctl.key0_out_value.q),
-
- // to register interface (read)
- .qs (auto_block_out_ctl_key0_out_value_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (auto_block_out_ctl_we & regwen_qs),
+ .src_wd_i (auto_block_out_ctl_key0_out_value_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (auto_block_out_ctl_key0_out_value_busy),
+ .src_qs_o (auto_block_out_ctl_key0_out_value_qs),
+ .dst_qe_o (),
+ .q (reg2hw.auto_block_out_ctl.key0_out_value.q)
);
// F[key1_out_value]: 5:5
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_auto_block_out_ctl_key1_out_value (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (auto_block_out_ctl_we & regwen_qs),
- .wd (auto_block_out_ctl_key1_out_value_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.auto_block_out_ctl.key1_out_value.q),
-
- // to register interface (read)
- .qs (auto_block_out_ctl_key1_out_value_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (auto_block_out_ctl_we & regwen_qs),
+ .src_wd_i (auto_block_out_ctl_key1_out_value_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (auto_block_out_ctl_key1_out_value_busy),
+ .src_qs_o (auto_block_out_ctl_key1_out_value_qs),
+ .dst_qe_o (),
+ .q (reg2hw.auto_block_out_ctl.key1_out_value.q)
);
// F[key2_out_value]: 6:6
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_auto_block_out_ctl_key2_out_value (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (auto_block_out_ctl_we & regwen_qs),
- .wd (auto_block_out_ctl_key2_out_value_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.auto_block_out_ctl.key2_out_value.q),
-
- // to register interface (read)
- .qs (auto_block_out_ctl_key2_out_value_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (auto_block_out_ctl_we & regwen_qs),
+ .src_wd_i (auto_block_out_ctl_key2_out_value_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (auto_block_out_ctl_key2_out_value_busy),
+ .src_qs_o (auto_block_out_ctl_key2_out_value_qs),
+ .dst_qe_o (),
+ .q (reg2hw.auto_block_out_ctl.key2_out_value.q)
);
@@ -2500,132 +2350,112 @@
// R[com_sel_ctl_0]: V(False)
// F[key0_in_sel_0]: 0:0
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_com_sel_ctl_0_key0_in_sel_0 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (com_sel_ctl_0_we & regwen_qs),
- .wd (com_sel_ctl_0_key0_in_sel_0_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.com_sel_ctl[0].key0_in_sel.q),
-
- // to register interface (read)
- .qs (com_sel_ctl_0_key0_in_sel_0_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (com_sel_ctl_0_we & regwen_qs),
+ .src_wd_i (com_sel_ctl_0_key0_in_sel_0_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (com_sel_ctl_0_key0_in_sel_0_busy),
+ .src_qs_o (com_sel_ctl_0_key0_in_sel_0_qs),
+ .dst_qe_o (),
+ .q (reg2hw.com_sel_ctl[0].key0_in_sel.q)
);
// F[key1_in_sel_0]: 1:1
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_com_sel_ctl_0_key1_in_sel_0 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (com_sel_ctl_0_we & regwen_qs),
- .wd (com_sel_ctl_0_key1_in_sel_0_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.com_sel_ctl[0].key1_in_sel.q),
-
- // to register interface (read)
- .qs (com_sel_ctl_0_key1_in_sel_0_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (com_sel_ctl_0_we & regwen_qs),
+ .src_wd_i (com_sel_ctl_0_key1_in_sel_0_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (com_sel_ctl_0_key1_in_sel_0_busy),
+ .src_qs_o (com_sel_ctl_0_key1_in_sel_0_qs),
+ .dst_qe_o (),
+ .q (reg2hw.com_sel_ctl[0].key1_in_sel.q)
);
// F[key2_in_sel_0]: 2:2
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_com_sel_ctl_0_key2_in_sel_0 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (com_sel_ctl_0_we & regwen_qs),
- .wd (com_sel_ctl_0_key2_in_sel_0_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.com_sel_ctl[0].key2_in_sel.q),
-
- // to register interface (read)
- .qs (com_sel_ctl_0_key2_in_sel_0_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (com_sel_ctl_0_we & regwen_qs),
+ .src_wd_i (com_sel_ctl_0_key2_in_sel_0_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (com_sel_ctl_0_key2_in_sel_0_busy),
+ .src_qs_o (com_sel_ctl_0_key2_in_sel_0_qs),
+ .dst_qe_o (),
+ .q (reg2hw.com_sel_ctl[0].key2_in_sel.q)
);
// F[pwrb_in_sel_0]: 3:3
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_com_sel_ctl_0_pwrb_in_sel_0 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (com_sel_ctl_0_we & regwen_qs),
- .wd (com_sel_ctl_0_pwrb_in_sel_0_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.com_sel_ctl[0].pwrb_in_sel.q),
-
- // to register interface (read)
- .qs (com_sel_ctl_0_pwrb_in_sel_0_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (com_sel_ctl_0_we & regwen_qs),
+ .src_wd_i (com_sel_ctl_0_pwrb_in_sel_0_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (com_sel_ctl_0_pwrb_in_sel_0_busy),
+ .src_qs_o (com_sel_ctl_0_pwrb_in_sel_0_qs),
+ .dst_qe_o (),
+ .q (reg2hw.com_sel_ctl[0].pwrb_in_sel.q)
);
// F[ac_present_sel_0]: 4:4
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_com_sel_ctl_0_ac_present_sel_0 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (com_sel_ctl_0_we & regwen_qs),
- .wd (com_sel_ctl_0_ac_present_sel_0_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.com_sel_ctl[0].ac_present_sel.q),
-
- // to register interface (read)
- .qs (com_sel_ctl_0_ac_present_sel_0_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (com_sel_ctl_0_we & regwen_qs),
+ .src_wd_i (com_sel_ctl_0_ac_present_sel_0_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (com_sel_ctl_0_ac_present_sel_0_busy),
+ .src_qs_o (com_sel_ctl_0_ac_present_sel_0_qs),
+ .dst_qe_o (),
+ .q (reg2hw.com_sel_ctl[0].ac_present_sel.q)
);
@@ -2633,132 +2463,112 @@
// R[com_sel_ctl_1]: V(False)
// F[key0_in_sel_1]: 0:0
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_com_sel_ctl_1_key0_in_sel_1 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (com_sel_ctl_1_we & regwen_qs),
- .wd (com_sel_ctl_1_key0_in_sel_1_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.com_sel_ctl[1].key0_in_sel.q),
-
- // to register interface (read)
- .qs (com_sel_ctl_1_key0_in_sel_1_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (com_sel_ctl_1_we & regwen_qs),
+ .src_wd_i (com_sel_ctl_1_key0_in_sel_1_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (com_sel_ctl_1_key0_in_sel_1_busy),
+ .src_qs_o (com_sel_ctl_1_key0_in_sel_1_qs),
+ .dst_qe_o (),
+ .q (reg2hw.com_sel_ctl[1].key0_in_sel.q)
);
// F[key1_in_sel_1]: 1:1
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_com_sel_ctl_1_key1_in_sel_1 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (com_sel_ctl_1_we & regwen_qs),
- .wd (com_sel_ctl_1_key1_in_sel_1_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.com_sel_ctl[1].key1_in_sel.q),
-
- // to register interface (read)
- .qs (com_sel_ctl_1_key1_in_sel_1_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (com_sel_ctl_1_we & regwen_qs),
+ .src_wd_i (com_sel_ctl_1_key1_in_sel_1_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (com_sel_ctl_1_key1_in_sel_1_busy),
+ .src_qs_o (com_sel_ctl_1_key1_in_sel_1_qs),
+ .dst_qe_o (),
+ .q (reg2hw.com_sel_ctl[1].key1_in_sel.q)
);
// F[key2_in_sel_1]: 2:2
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_com_sel_ctl_1_key2_in_sel_1 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (com_sel_ctl_1_we & regwen_qs),
- .wd (com_sel_ctl_1_key2_in_sel_1_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.com_sel_ctl[1].key2_in_sel.q),
-
- // to register interface (read)
- .qs (com_sel_ctl_1_key2_in_sel_1_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (com_sel_ctl_1_we & regwen_qs),
+ .src_wd_i (com_sel_ctl_1_key2_in_sel_1_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (com_sel_ctl_1_key2_in_sel_1_busy),
+ .src_qs_o (com_sel_ctl_1_key2_in_sel_1_qs),
+ .dst_qe_o (),
+ .q (reg2hw.com_sel_ctl[1].key2_in_sel.q)
);
// F[pwrb_in_sel_1]: 3:3
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_com_sel_ctl_1_pwrb_in_sel_1 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (com_sel_ctl_1_we & regwen_qs),
- .wd (com_sel_ctl_1_pwrb_in_sel_1_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.com_sel_ctl[1].pwrb_in_sel.q),
-
- // to register interface (read)
- .qs (com_sel_ctl_1_pwrb_in_sel_1_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (com_sel_ctl_1_we & regwen_qs),
+ .src_wd_i (com_sel_ctl_1_pwrb_in_sel_1_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (com_sel_ctl_1_pwrb_in_sel_1_busy),
+ .src_qs_o (com_sel_ctl_1_pwrb_in_sel_1_qs),
+ .dst_qe_o (),
+ .q (reg2hw.com_sel_ctl[1].pwrb_in_sel.q)
);
// F[ac_present_sel_1]: 4:4
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_com_sel_ctl_1_ac_present_sel_1 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (com_sel_ctl_1_we & regwen_qs),
- .wd (com_sel_ctl_1_ac_present_sel_1_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.com_sel_ctl[1].ac_present_sel.q),
-
- // to register interface (read)
- .qs (com_sel_ctl_1_ac_present_sel_1_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (com_sel_ctl_1_we & regwen_qs),
+ .src_wd_i (com_sel_ctl_1_ac_present_sel_1_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (com_sel_ctl_1_ac_present_sel_1_busy),
+ .src_qs_o (com_sel_ctl_1_ac_present_sel_1_qs),
+ .dst_qe_o (),
+ .q (reg2hw.com_sel_ctl[1].ac_present_sel.q)
);
@@ -2766,132 +2576,112 @@
// R[com_sel_ctl_2]: V(False)
// F[key0_in_sel_2]: 0:0
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_com_sel_ctl_2_key0_in_sel_2 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (com_sel_ctl_2_we & regwen_qs),
- .wd (com_sel_ctl_2_key0_in_sel_2_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.com_sel_ctl[2].key0_in_sel.q),
-
- // to register interface (read)
- .qs (com_sel_ctl_2_key0_in_sel_2_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (com_sel_ctl_2_we & regwen_qs),
+ .src_wd_i (com_sel_ctl_2_key0_in_sel_2_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (com_sel_ctl_2_key0_in_sel_2_busy),
+ .src_qs_o (com_sel_ctl_2_key0_in_sel_2_qs),
+ .dst_qe_o (),
+ .q (reg2hw.com_sel_ctl[2].key0_in_sel.q)
);
// F[key1_in_sel_2]: 1:1
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_com_sel_ctl_2_key1_in_sel_2 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (com_sel_ctl_2_we & regwen_qs),
- .wd (com_sel_ctl_2_key1_in_sel_2_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.com_sel_ctl[2].key1_in_sel.q),
-
- // to register interface (read)
- .qs (com_sel_ctl_2_key1_in_sel_2_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (com_sel_ctl_2_we & regwen_qs),
+ .src_wd_i (com_sel_ctl_2_key1_in_sel_2_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (com_sel_ctl_2_key1_in_sel_2_busy),
+ .src_qs_o (com_sel_ctl_2_key1_in_sel_2_qs),
+ .dst_qe_o (),
+ .q (reg2hw.com_sel_ctl[2].key1_in_sel.q)
);
// F[key2_in_sel_2]: 2:2
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_com_sel_ctl_2_key2_in_sel_2 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (com_sel_ctl_2_we & regwen_qs),
- .wd (com_sel_ctl_2_key2_in_sel_2_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.com_sel_ctl[2].key2_in_sel.q),
-
- // to register interface (read)
- .qs (com_sel_ctl_2_key2_in_sel_2_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (com_sel_ctl_2_we & regwen_qs),
+ .src_wd_i (com_sel_ctl_2_key2_in_sel_2_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (com_sel_ctl_2_key2_in_sel_2_busy),
+ .src_qs_o (com_sel_ctl_2_key2_in_sel_2_qs),
+ .dst_qe_o (),
+ .q (reg2hw.com_sel_ctl[2].key2_in_sel.q)
);
// F[pwrb_in_sel_2]: 3:3
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_com_sel_ctl_2_pwrb_in_sel_2 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (com_sel_ctl_2_we & regwen_qs),
- .wd (com_sel_ctl_2_pwrb_in_sel_2_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.com_sel_ctl[2].pwrb_in_sel.q),
-
- // to register interface (read)
- .qs (com_sel_ctl_2_pwrb_in_sel_2_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (com_sel_ctl_2_we & regwen_qs),
+ .src_wd_i (com_sel_ctl_2_pwrb_in_sel_2_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (com_sel_ctl_2_pwrb_in_sel_2_busy),
+ .src_qs_o (com_sel_ctl_2_pwrb_in_sel_2_qs),
+ .dst_qe_o (),
+ .q (reg2hw.com_sel_ctl[2].pwrb_in_sel.q)
);
// F[ac_present_sel_2]: 4:4
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_com_sel_ctl_2_ac_present_sel_2 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (com_sel_ctl_2_we & regwen_qs),
- .wd (com_sel_ctl_2_ac_present_sel_2_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.com_sel_ctl[2].ac_present_sel.q),
-
- // to register interface (read)
- .qs (com_sel_ctl_2_ac_present_sel_2_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (com_sel_ctl_2_we & regwen_qs),
+ .src_wd_i (com_sel_ctl_2_ac_present_sel_2_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (com_sel_ctl_2_ac_present_sel_2_busy),
+ .src_qs_o (com_sel_ctl_2_ac_present_sel_2_qs),
+ .dst_qe_o (),
+ .q (reg2hw.com_sel_ctl[2].ac_present_sel.q)
);
@@ -2899,132 +2689,112 @@
// R[com_sel_ctl_3]: V(False)
// F[key0_in_sel_3]: 0:0
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_com_sel_ctl_3_key0_in_sel_3 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (com_sel_ctl_3_we & regwen_qs),
- .wd (com_sel_ctl_3_key0_in_sel_3_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.com_sel_ctl[3].key0_in_sel.q),
-
- // to register interface (read)
- .qs (com_sel_ctl_3_key0_in_sel_3_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (com_sel_ctl_3_we & regwen_qs),
+ .src_wd_i (com_sel_ctl_3_key0_in_sel_3_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (com_sel_ctl_3_key0_in_sel_3_busy),
+ .src_qs_o (com_sel_ctl_3_key0_in_sel_3_qs),
+ .dst_qe_o (),
+ .q (reg2hw.com_sel_ctl[3].key0_in_sel.q)
);
// F[key1_in_sel_3]: 1:1
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_com_sel_ctl_3_key1_in_sel_3 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (com_sel_ctl_3_we & regwen_qs),
- .wd (com_sel_ctl_3_key1_in_sel_3_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.com_sel_ctl[3].key1_in_sel.q),
-
- // to register interface (read)
- .qs (com_sel_ctl_3_key1_in_sel_3_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (com_sel_ctl_3_we & regwen_qs),
+ .src_wd_i (com_sel_ctl_3_key1_in_sel_3_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (com_sel_ctl_3_key1_in_sel_3_busy),
+ .src_qs_o (com_sel_ctl_3_key1_in_sel_3_qs),
+ .dst_qe_o (),
+ .q (reg2hw.com_sel_ctl[3].key1_in_sel.q)
);
// F[key2_in_sel_3]: 2:2
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_com_sel_ctl_3_key2_in_sel_3 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (com_sel_ctl_3_we & regwen_qs),
- .wd (com_sel_ctl_3_key2_in_sel_3_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.com_sel_ctl[3].key2_in_sel.q),
-
- // to register interface (read)
- .qs (com_sel_ctl_3_key2_in_sel_3_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (com_sel_ctl_3_we & regwen_qs),
+ .src_wd_i (com_sel_ctl_3_key2_in_sel_3_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (com_sel_ctl_3_key2_in_sel_3_busy),
+ .src_qs_o (com_sel_ctl_3_key2_in_sel_3_qs),
+ .dst_qe_o (),
+ .q (reg2hw.com_sel_ctl[3].key2_in_sel.q)
);
// F[pwrb_in_sel_3]: 3:3
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_com_sel_ctl_3_pwrb_in_sel_3 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (com_sel_ctl_3_we & regwen_qs),
- .wd (com_sel_ctl_3_pwrb_in_sel_3_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.com_sel_ctl[3].pwrb_in_sel.q),
-
- // to register interface (read)
- .qs (com_sel_ctl_3_pwrb_in_sel_3_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (com_sel_ctl_3_we & regwen_qs),
+ .src_wd_i (com_sel_ctl_3_pwrb_in_sel_3_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (com_sel_ctl_3_pwrb_in_sel_3_busy),
+ .src_qs_o (com_sel_ctl_3_pwrb_in_sel_3_qs),
+ .dst_qe_o (),
+ .q (reg2hw.com_sel_ctl[3].pwrb_in_sel.q)
);
// F[ac_present_sel_3]: 4:4
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_com_sel_ctl_3_ac_present_sel_3 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (com_sel_ctl_3_we & regwen_qs),
- .wd (com_sel_ctl_3_ac_present_sel_3_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.com_sel_ctl[3].ac_present_sel.q),
-
- // to register interface (read)
- .qs (com_sel_ctl_3_ac_present_sel_3_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (com_sel_ctl_3_we & regwen_qs),
+ .src_wd_i (com_sel_ctl_3_ac_present_sel_3_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (com_sel_ctl_3_ac_present_sel_3_busy),
+ .src_qs_o (com_sel_ctl_3_ac_present_sel_3_qs),
+ .dst_qe_o (),
+ .q (reg2hw.com_sel_ctl[3].ac_present_sel.q)
);
@@ -3033,109 +2803,93 @@
// Subregister 0 of Multireg com_det_ctl
// R[com_det_ctl_0]: V(False)
- prim_subreg #(
+ prim_subreg_async #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (32'h0)
) u_com_det_ctl_0 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (com_det_ctl_0_we & regwen_qs),
- .wd (com_det_ctl_0_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (reg2hw.com_det_ctl[0].qe),
- .q (reg2hw.com_det_ctl[0].q),
-
- // to register interface (read)
- .qs (com_det_ctl_0_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (com_det_ctl_0_we & regwen_qs),
+ .src_wd_i (com_det_ctl_0_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (com_det_ctl_0_busy),
+ .src_qs_o (com_det_ctl_0_qs),
+ .dst_qe_o (),
+ .q (reg2hw.com_det_ctl[0].q)
);
// Subregister 1 of Multireg com_det_ctl
// R[com_det_ctl_1]: V(False)
- prim_subreg #(
+ prim_subreg_async #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (32'h0)
) u_com_det_ctl_1 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (com_det_ctl_1_we & regwen_qs),
- .wd (com_det_ctl_1_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (reg2hw.com_det_ctl[1].qe),
- .q (reg2hw.com_det_ctl[1].q),
-
- // to register interface (read)
- .qs (com_det_ctl_1_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (com_det_ctl_1_we & regwen_qs),
+ .src_wd_i (com_det_ctl_1_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (com_det_ctl_1_busy),
+ .src_qs_o (com_det_ctl_1_qs),
+ .dst_qe_o (),
+ .q (reg2hw.com_det_ctl[1].q)
);
// Subregister 2 of Multireg com_det_ctl
// R[com_det_ctl_2]: V(False)
- prim_subreg #(
+ prim_subreg_async #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (32'h0)
) u_com_det_ctl_2 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (com_det_ctl_2_we & regwen_qs),
- .wd (com_det_ctl_2_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (reg2hw.com_det_ctl[2].qe),
- .q (reg2hw.com_det_ctl[2].q),
-
- // to register interface (read)
- .qs (com_det_ctl_2_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (com_det_ctl_2_we & regwen_qs),
+ .src_wd_i (com_det_ctl_2_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (com_det_ctl_2_busy),
+ .src_qs_o (com_det_ctl_2_qs),
+ .dst_qe_o (),
+ .q (reg2hw.com_det_ctl[2].q)
);
// Subregister 3 of Multireg com_det_ctl
// R[com_det_ctl_3]: V(False)
- prim_subreg #(
+ prim_subreg_async #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (32'h0)
) u_com_det_ctl_3 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (com_det_ctl_3_we & regwen_qs),
- .wd (com_det_ctl_3_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (reg2hw.com_det_ctl[3].qe),
- .q (reg2hw.com_det_ctl[3].q),
-
- // to register interface (read)
- .qs (com_det_ctl_3_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (com_det_ctl_3_we & regwen_qs),
+ .src_wd_i (com_det_ctl_3_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (com_det_ctl_3_busy),
+ .src_qs_o (com_det_ctl_3_qs),
+ .dst_qe_o (),
+ .q (reg2hw.com_det_ctl[3].q)
);
@@ -3144,106 +2898,90 @@
// R[com_out_ctl_0]: V(False)
// F[bat_disable_0]: 0:0
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_com_out_ctl_0_bat_disable_0 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (com_out_ctl_0_we & regwen_qs),
- .wd (com_out_ctl_0_bat_disable_0_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.com_out_ctl[0].bat_disable.q),
-
- // to register interface (read)
- .qs (com_out_ctl_0_bat_disable_0_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (com_out_ctl_0_we & regwen_qs),
+ .src_wd_i (com_out_ctl_0_bat_disable_0_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (com_out_ctl_0_bat_disable_0_busy),
+ .src_qs_o (com_out_ctl_0_bat_disable_0_qs),
+ .dst_qe_o (),
+ .q (reg2hw.com_out_ctl[0].bat_disable.q)
);
// F[interrupt_0]: 1:1
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_com_out_ctl_0_interrupt_0 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (com_out_ctl_0_we & regwen_qs),
- .wd (com_out_ctl_0_interrupt_0_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.com_out_ctl[0].interrupt.q),
-
- // to register interface (read)
- .qs (com_out_ctl_0_interrupt_0_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (com_out_ctl_0_we & regwen_qs),
+ .src_wd_i (com_out_ctl_0_interrupt_0_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (com_out_ctl_0_interrupt_0_busy),
+ .src_qs_o (com_out_ctl_0_interrupt_0_qs),
+ .dst_qe_o (),
+ .q (reg2hw.com_out_ctl[0].interrupt.q)
);
// F[ec_rst_0]: 2:2
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_com_out_ctl_0_ec_rst_0 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (com_out_ctl_0_we & regwen_qs),
- .wd (com_out_ctl_0_ec_rst_0_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.com_out_ctl[0].ec_rst.q),
-
- // to register interface (read)
- .qs (com_out_ctl_0_ec_rst_0_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (com_out_ctl_0_we & regwen_qs),
+ .src_wd_i (com_out_ctl_0_ec_rst_0_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (com_out_ctl_0_ec_rst_0_busy),
+ .src_qs_o (com_out_ctl_0_ec_rst_0_qs),
+ .dst_qe_o (),
+ .q (reg2hw.com_out_ctl[0].ec_rst.q)
);
// F[gsc_rst_0]: 3:3
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_com_out_ctl_0_gsc_rst_0 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (com_out_ctl_0_we & regwen_qs),
- .wd (com_out_ctl_0_gsc_rst_0_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.com_out_ctl[0].gsc_rst.q),
-
- // to register interface (read)
- .qs (com_out_ctl_0_gsc_rst_0_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (com_out_ctl_0_we & regwen_qs),
+ .src_wd_i (com_out_ctl_0_gsc_rst_0_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (com_out_ctl_0_gsc_rst_0_busy),
+ .src_qs_o (com_out_ctl_0_gsc_rst_0_qs),
+ .dst_qe_o (),
+ .q (reg2hw.com_out_ctl[0].gsc_rst.q)
);
@@ -3251,106 +2989,90 @@
// R[com_out_ctl_1]: V(False)
// F[bat_disable_1]: 0:0
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_com_out_ctl_1_bat_disable_1 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (com_out_ctl_1_we & regwen_qs),
- .wd (com_out_ctl_1_bat_disable_1_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.com_out_ctl[1].bat_disable.q),
-
- // to register interface (read)
- .qs (com_out_ctl_1_bat_disable_1_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (com_out_ctl_1_we & regwen_qs),
+ .src_wd_i (com_out_ctl_1_bat_disable_1_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (com_out_ctl_1_bat_disable_1_busy),
+ .src_qs_o (com_out_ctl_1_bat_disable_1_qs),
+ .dst_qe_o (),
+ .q (reg2hw.com_out_ctl[1].bat_disable.q)
);
// F[interrupt_1]: 1:1
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_com_out_ctl_1_interrupt_1 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (com_out_ctl_1_we & regwen_qs),
- .wd (com_out_ctl_1_interrupt_1_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.com_out_ctl[1].interrupt.q),
-
- // to register interface (read)
- .qs (com_out_ctl_1_interrupt_1_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (com_out_ctl_1_we & regwen_qs),
+ .src_wd_i (com_out_ctl_1_interrupt_1_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (com_out_ctl_1_interrupt_1_busy),
+ .src_qs_o (com_out_ctl_1_interrupt_1_qs),
+ .dst_qe_o (),
+ .q (reg2hw.com_out_ctl[1].interrupt.q)
);
// F[ec_rst_1]: 2:2
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_com_out_ctl_1_ec_rst_1 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (com_out_ctl_1_we & regwen_qs),
- .wd (com_out_ctl_1_ec_rst_1_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.com_out_ctl[1].ec_rst.q),
-
- // to register interface (read)
- .qs (com_out_ctl_1_ec_rst_1_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (com_out_ctl_1_we & regwen_qs),
+ .src_wd_i (com_out_ctl_1_ec_rst_1_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (com_out_ctl_1_ec_rst_1_busy),
+ .src_qs_o (com_out_ctl_1_ec_rst_1_qs),
+ .dst_qe_o (),
+ .q (reg2hw.com_out_ctl[1].ec_rst.q)
);
// F[gsc_rst_1]: 3:3
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_com_out_ctl_1_gsc_rst_1 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (com_out_ctl_1_we & regwen_qs),
- .wd (com_out_ctl_1_gsc_rst_1_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.com_out_ctl[1].gsc_rst.q),
-
- // to register interface (read)
- .qs (com_out_ctl_1_gsc_rst_1_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (com_out_ctl_1_we & regwen_qs),
+ .src_wd_i (com_out_ctl_1_gsc_rst_1_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (com_out_ctl_1_gsc_rst_1_busy),
+ .src_qs_o (com_out_ctl_1_gsc_rst_1_qs),
+ .dst_qe_o (),
+ .q (reg2hw.com_out_ctl[1].gsc_rst.q)
);
@@ -3358,106 +3080,90 @@
// R[com_out_ctl_2]: V(False)
// F[bat_disable_2]: 0:0
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_com_out_ctl_2_bat_disable_2 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (com_out_ctl_2_we & regwen_qs),
- .wd (com_out_ctl_2_bat_disable_2_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.com_out_ctl[2].bat_disable.q),
-
- // to register interface (read)
- .qs (com_out_ctl_2_bat_disable_2_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (com_out_ctl_2_we & regwen_qs),
+ .src_wd_i (com_out_ctl_2_bat_disable_2_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (com_out_ctl_2_bat_disable_2_busy),
+ .src_qs_o (com_out_ctl_2_bat_disable_2_qs),
+ .dst_qe_o (),
+ .q (reg2hw.com_out_ctl[2].bat_disable.q)
);
// F[interrupt_2]: 1:1
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_com_out_ctl_2_interrupt_2 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (com_out_ctl_2_we & regwen_qs),
- .wd (com_out_ctl_2_interrupt_2_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.com_out_ctl[2].interrupt.q),
-
- // to register interface (read)
- .qs (com_out_ctl_2_interrupt_2_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (com_out_ctl_2_we & regwen_qs),
+ .src_wd_i (com_out_ctl_2_interrupt_2_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (com_out_ctl_2_interrupt_2_busy),
+ .src_qs_o (com_out_ctl_2_interrupt_2_qs),
+ .dst_qe_o (),
+ .q (reg2hw.com_out_ctl[2].interrupt.q)
);
// F[ec_rst_2]: 2:2
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_com_out_ctl_2_ec_rst_2 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (com_out_ctl_2_we & regwen_qs),
- .wd (com_out_ctl_2_ec_rst_2_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.com_out_ctl[2].ec_rst.q),
-
- // to register interface (read)
- .qs (com_out_ctl_2_ec_rst_2_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (com_out_ctl_2_we & regwen_qs),
+ .src_wd_i (com_out_ctl_2_ec_rst_2_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (com_out_ctl_2_ec_rst_2_busy),
+ .src_qs_o (com_out_ctl_2_ec_rst_2_qs),
+ .dst_qe_o (),
+ .q (reg2hw.com_out_ctl[2].ec_rst.q)
);
// F[gsc_rst_2]: 3:3
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_com_out_ctl_2_gsc_rst_2 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (com_out_ctl_2_we & regwen_qs),
- .wd (com_out_ctl_2_gsc_rst_2_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.com_out_ctl[2].gsc_rst.q),
-
- // to register interface (read)
- .qs (com_out_ctl_2_gsc_rst_2_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (com_out_ctl_2_we & regwen_qs),
+ .src_wd_i (com_out_ctl_2_gsc_rst_2_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (com_out_ctl_2_gsc_rst_2_busy),
+ .src_qs_o (com_out_ctl_2_gsc_rst_2_qs),
+ .dst_qe_o (),
+ .q (reg2hw.com_out_ctl[2].gsc_rst.q)
);
@@ -3465,106 +3171,90 @@
// R[com_out_ctl_3]: V(False)
// F[bat_disable_3]: 0:0
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_com_out_ctl_3_bat_disable_3 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (com_out_ctl_3_we & regwen_qs),
- .wd (com_out_ctl_3_bat_disable_3_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.com_out_ctl[3].bat_disable.q),
-
- // to register interface (read)
- .qs (com_out_ctl_3_bat_disable_3_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (com_out_ctl_3_we & regwen_qs),
+ .src_wd_i (com_out_ctl_3_bat_disable_3_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (com_out_ctl_3_bat_disable_3_busy),
+ .src_qs_o (com_out_ctl_3_bat_disable_3_qs),
+ .dst_qe_o (),
+ .q (reg2hw.com_out_ctl[3].bat_disable.q)
);
// F[interrupt_3]: 1:1
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_com_out_ctl_3_interrupt_3 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (com_out_ctl_3_we & regwen_qs),
- .wd (com_out_ctl_3_interrupt_3_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.com_out_ctl[3].interrupt.q),
-
- // to register interface (read)
- .qs (com_out_ctl_3_interrupt_3_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (com_out_ctl_3_we & regwen_qs),
+ .src_wd_i (com_out_ctl_3_interrupt_3_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (com_out_ctl_3_interrupt_3_busy),
+ .src_qs_o (com_out_ctl_3_interrupt_3_qs),
+ .dst_qe_o (),
+ .q (reg2hw.com_out_ctl[3].interrupt.q)
);
// F[ec_rst_3]: 2:2
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_com_out_ctl_3_ec_rst_3 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (com_out_ctl_3_we & regwen_qs),
- .wd (com_out_ctl_3_ec_rst_3_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.com_out_ctl[3].ec_rst.q),
-
- // to register interface (read)
- .qs (com_out_ctl_3_ec_rst_3_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (com_out_ctl_3_we & regwen_qs),
+ .src_wd_i (com_out_ctl_3_ec_rst_3_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (com_out_ctl_3_ec_rst_3_busy),
+ .src_qs_o (com_out_ctl_3_ec_rst_3_qs),
+ .dst_qe_o (),
+ .q (reg2hw.com_out_ctl[3].ec_rst.q)
);
// F[gsc_rst_3]: 3:3
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_com_out_ctl_3_gsc_rst_3 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (com_out_ctl_3_we & regwen_qs),
- .wd (com_out_ctl_3_gsc_rst_3_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.com_out_ctl[3].gsc_rst.q),
-
- // to register interface (read)
- .qs (com_out_ctl_3_gsc_rst_3_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (com_out_ctl_3_we & regwen_qs),
+ .src_wd_i (com_out_ctl_3_gsc_rst_3_wd),
+ .dst_de_i (1'b0),
+ .dst_d_i ('0),
+ .src_busy_o (com_out_ctl_3_gsc_rst_3_busy),
+ .src_qs_o (com_out_ctl_3_gsc_rst_3_qs),
+ .dst_qe_o (),
+ .q (reg2hw.com_out_ctl[3].gsc_rst.q)
);
@@ -4620,6 +4310,180 @@
always_comb begin
reg_busy = '0;
unique case (1'b1)
+ addr_hit[5]: begin
+ reg_busy = ec_rst_ctl_busy;
+ end
+ addr_hit[6]: begin
+ reg_busy = ulp_ac_debounce_ctl_busy;
+ end
+ addr_hit[7]: begin
+ reg_busy = ulp_lid_debounce_ctl_busy;
+ end
+ addr_hit[8]: begin
+ reg_busy = ulp_pwrb_debounce_ctl_busy;
+ end
+ addr_hit[9]: begin
+ reg_busy = ulp_ctl_busy;
+ end
+ addr_hit[10]: begin
+ reg_busy = ulp_status_busy;
+ end
+ addr_hit[12]: begin
+ reg_busy =
+ key_invert_ctl_key0_in_busy |
+ key_invert_ctl_key0_out_busy |
+ key_invert_ctl_key1_in_busy |
+ key_invert_ctl_key1_out_busy |
+ key_invert_ctl_key2_in_busy |
+ key_invert_ctl_key2_out_busy |
+ key_invert_ctl_pwrb_in_busy |
+ key_invert_ctl_pwrb_out_busy |
+ key_invert_ctl_ac_present_busy |
+ key_invert_ctl_bat_disable_busy |
+ key_invert_ctl_lid_open_busy |
+ key_invert_ctl_z3_wakeup_busy;
+ end
+ addr_hit[13]: begin
+ reg_busy =
+ pin_allowed_ctl_bat_disable_0_busy |
+ pin_allowed_ctl_ec_rst_l_0_busy |
+ pin_allowed_ctl_pwrb_out_0_busy |
+ pin_allowed_ctl_key0_out_0_busy |
+ pin_allowed_ctl_key1_out_0_busy |
+ pin_allowed_ctl_key2_out_0_busy |
+ pin_allowed_ctl_z3_wakeup_0_busy |
+ pin_allowed_ctl_bat_disable_1_busy |
+ pin_allowed_ctl_ec_rst_l_1_busy |
+ pin_allowed_ctl_pwrb_out_1_busy |
+ pin_allowed_ctl_key0_out_1_busy |
+ pin_allowed_ctl_key1_out_1_busy |
+ pin_allowed_ctl_key2_out_1_busy |
+ pin_allowed_ctl_z3_wakeup_1_busy;
+ end
+ addr_hit[14]: begin
+ reg_busy =
+ pin_out_ctl_bat_disable_busy |
+ pin_out_ctl_ec_rst_l_busy |
+ pin_out_ctl_pwrb_out_busy |
+ pin_out_ctl_key0_out_busy |
+ pin_out_ctl_key1_out_busy |
+ pin_out_ctl_key2_out_busy |
+ pin_out_ctl_z3_wakeup_busy;
+ end
+ addr_hit[15]: begin
+ reg_busy =
+ pin_out_value_bat_disable_busy |
+ pin_out_value_ec_rst_l_busy |
+ pin_out_value_pwrb_out_busy |
+ pin_out_value_key0_out_busy |
+ pin_out_value_key1_out_busy |
+ pin_out_value_key2_out_busy |
+ pin_out_value_z3_wakeup_busy;
+ end
+ addr_hit[17]: begin
+ reg_busy =
+ key_intr_ctl_pwrb_in_h2l_busy |
+ key_intr_ctl_key0_in_h2l_busy |
+ key_intr_ctl_key1_in_h2l_busy |
+ key_intr_ctl_key2_in_h2l_busy |
+ key_intr_ctl_ac_present_h2l_busy |
+ key_intr_ctl_ec_rst_l_h2l_busy |
+ key_intr_ctl_pwrb_in_l2h_busy |
+ key_intr_ctl_key0_in_l2h_busy |
+ key_intr_ctl_key1_in_l2h_busy |
+ key_intr_ctl_key2_in_l2h_busy |
+ key_intr_ctl_ac_present_l2h_busy |
+ key_intr_ctl_ec_rst_l_l2h_busy;
+ end
+ addr_hit[18]: begin
+ reg_busy = key_intr_debounce_ctl_busy;
+ end
+ addr_hit[19]: begin
+ reg_busy =
+ auto_block_debounce_ctl_debounce_timer_busy |
+ auto_block_debounce_ctl_auto_block_enable_busy;
+ end
+ addr_hit[20]: begin
+ reg_busy =
+ auto_block_out_ctl_key0_out_sel_busy |
+ auto_block_out_ctl_key1_out_sel_busy |
+ auto_block_out_ctl_key2_out_sel_busy |
+ auto_block_out_ctl_key0_out_value_busy |
+ auto_block_out_ctl_key1_out_value_busy |
+ auto_block_out_ctl_key2_out_value_busy;
+ end
+ addr_hit[21]: begin
+ reg_busy =
+ com_sel_ctl_0_key0_in_sel_0_busy |
+ com_sel_ctl_0_key1_in_sel_0_busy |
+ com_sel_ctl_0_key2_in_sel_0_busy |
+ com_sel_ctl_0_pwrb_in_sel_0_busy |
+ com_sel_ctl_0_ac_present_sel_0_busy;
+ end
+ addr_hit[22]: begin
+ reg_busy =
+ com_sel_ctl_1_key0_in_sel_1_busy |
+ com_sel_ctl_1_key1_in_sel_1_busy |
+ com_sel_ctl_1_key2_in_sel_1_busy |
+ com_sel_ctl_1_pwrb_in_sel_1_busy |
+ com_sel_ctl_1_ac_present_sel_1_busy;
+ end
+ addr_hit[23]: begin
+ reg_busy =
+ com_sel_ctl_2_key0_in_sel_2_busy |
+ com_sel_ctl_2_key1_in_sel_2_busy |
+ com_sel_ctl_2_key2_in_sel_2_busy |
+ com_sel_ctl_2_pwrb_in_sel_2_busy |
+ com_sel_ctl_2_ac_present_sel_2_busy;
+ end
+ addr_hit[24]: begin
+ reg_busy =
+ com_sel_ctl_3_key0_in_sel_3_busy |
+ com_sel_ctl_3_key1_in_sel_3_busy |
+ com_sel_ctl_3_key2_in_sel_3_busy |
+ com_sel_ctl_3_pwrb_in_sel_3_busy |
+ com_sel_ctl_3_ac_present_sel_3_busy;
+ end
+ addr_hit[25]: begin
+ reg_busy = com_det_ctl_0_busy;
+ end
+ addr_hit[26]: begin
+ reg_busy = com_det_ctl_1_busy;
+ end
+ addr_hit[27]: begin
+ reg_busy = com_det_ctl_2_busy;
+ end
+ addr_hit[28]: begin
+ reg_busy = com_det_ctl_3_busy;
+ end
+ addr_hit[29]: begin
+ reg_busy =
+ com_out_ctl_0_bat_disable_0_busy |
+ com_out_ctl_0_interrupt_0_busy |
+ com_out_ctl_0_ec_rst_0_busy |
+ com_out_ctl_0_gsc_rst_0_busy;
+ end
+ addr_hit[30]: begin
+ reg_busy =
+ com_out_ctl_1_bat_disable_1_busy |
+ com_out_ctl_1_interrupt_1_busy |
+ com_out_ctl_1_ec_rst_1_busy |
+ com_out_ctl_1_gsc_rst_1_busy;
+ end
+ addr_hit[31]: begin
+ reg_busy =
+ com_out_ctl_2_bat_disable_2_busy |
+ com_out_ctl_2_interrupt_2_busy |
+ com_out_ctl_2_ec_rst_2_busy |
+ com_out_ctl_2_gsc_rst_2_busy;
+ end
+ addr_hit[32]: begin
+ reg_busy =
+ com_out_ctl_3_bat_disable_3_busy |
+ com_out_ctl_3_interrupt_3_busy |
+ com_out_ctl_3_ec_rst_3_busy |
+ com_out_ctl_3_gsc_rst_3_busy;
+ end
default: begin
reg_busy = '0;
end
diff --git a/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_ulp.sv b/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_ulp.sv
index 4f5925b..0f3e4d7 100644
--- a/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_ulp.sv
+++ b/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_ulp.sv
@@ -7,8 +7,6 @@
module sysrst_ctrl_ulp import sysrst_ctrl_reg_pkg::*; (
input clk_aon_i,
input rst_aon_ni,
- input clk_i,
- input rst_ni,
input lid_open_int_i,
input ac_present_int_i,
@@ -20,125 +18,14 @@
input sysrst_ctrl_reg2hw_ulp_ctl_reg_t ulp_ctl_i,
output sysrst_ctrl_hw2reg_ulp_status_reg_t ulp_status_o,
- output ulp_wakeup_o,
+ output ulp_wakeup_pulse_o,
output z3_wakeup_hw_o
);
- logic cfg_ulp_en;
- logic load_ulp_ac_timer;
- logic [15:0] cfg_ulp_ac_timer;
- logic [15:0] cfg_ulp_ac_timer_d;
- logic load_ulp_lid_timer;
- logic [15:0] cfg_ulp_lid_timer;
- logic [15:0] cfg_ulp_lid_timer_d;
- logic load_ulp_pwrb_timer;
- logic [15:0] cfg_ulp_pwrb_timer;
- logic [15:0] cfg_ulp_pwrb_timer_d;
-
- logic pwrb_cond_met, pwrb_cond_met_q;
- logic lid_open_cond_met, lid_open_cond_met_q;
- logic ac_present_cond_met, ac_present_cond_met_q;
logic pwrb_int;
logic lid_open_int;
logic ac_present_int;
- logic pwrb_det_pulse;
- logic lid_open_det_pulse;
- logic ac_present_det_pulse;
- logic cfg_pwrb_det_pulse;
- logic cfg_lid_open_det_pulse;
- logic cfg_ac_present_det_pulse;
-
- //synchronize between cfg(24MHz) and always-on(200KHz)
- prim_flop_2sync # (
- .Width(1)
- ) u_cfg_ulp_en (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(ulp_ctl_i.q),
- .q_o(cfg_ulp_en)
- );
-
- prim_fifo_async #(
- .Width(16),
- .Depth(2)
- ) u_cfg_ulp_ac_timer (
- .clk_wr_i (clk_i),
- .rst_wr_ni (rst_ni),
- .wvalid_i (ulp_ac_debounce_ctl_i.qe),
- .wready_o (),
- .wdata_i (ulp_ac_debounce_ctl_i.q),
- .wdepth_o (),
-
- .clk_rd_i (clk_aon_i),
- .rst_rd_ni (rst_aon_ni),
- .rvalid_o (load_ulp_ac_timer),
- .rready_i (1'b1),
- .rdata_o (cfg_ulp_ac_timer_d),
- .rdepth_o ()
- );
-
- prim_fifo_async #(
- .Width(16),
- .Depth(2)
- ) u_cfg_ulp_lid_timer (
- .clk_wr_i (clk_i),
- .rst_wr_ni (rst_ni),
- .wvalid_i (ulp_lid_debounce_ctl_i.qe),
- .wready_o (),
- .wdata_i (ulp_lid_debounce_ctl_i.q),
- .wdepth_o (),
-
- .clk_rd_i (clk_aon_i),
- .rst_rd_ni (rst_aon_ni),
- .rvalid_o (load_ulp_lid_timer),
- .rready_i (1'b1),
- .rdata_o (cfg_ulp_lid_timer_d),
- .rdepth_o ()
- );
-
- prim_fifo_async #(
- .Width(16),
- .Depth(2)
- ) u_cfg_ulp_pwrb_timer (
- .clk_wr_i (clk_i),
- .rst_wr_ni (rst_ni),
- .wvalid_i (ulp_pwrb_debounce_ctl_i.qe),
- .wready_o (),
- .wdata_i (ulp_pwrb_debounce_ctl_i.q),
- .wdepth_o (),
-
- .clk_rd_i (clk_aon_i),
- .rst_rd_ni (rst_aon_ni),
- .rvalid_o (load_ulp_pwrb_timer),
- .rready_i (1'b1),
- .rdata_o (cfg_ulp_pwrb_timer_d),
- .rdepth_o ()
- );
-
- always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin: p_cfg_ulp_ac_timer_reg
- if (!rst_aon_ni) begin
- cfg_ulp_ac_timer <= '0;
- end else if (load_ulp_ac_timer) begin
- cfg_ulp_ac_timer <= cfg_ulp_ac_timer_d;
- end
- end
-
- always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin: p_cfg_ulp_lid_timer_reg
- if (!rst_aon_ni) begin
- cfg_ulp_lid_timer <= '0;
- end else if (load_ulp_lid_timer) begin
- cfg_ulp_lid_timer <= cfg_ulp_lid_timer_d;
- end
- end
-
- always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin: p_cfg_ulp_pwrb_timer_reg
- if (!rst_aon_ni) begin
- cfg_ulp_pwrb_timer <= '0;
- end else if (load_ulp_pwrb_timer) begin
- cfg_ulp_pwrb_timer <= cfg_ulp_pwrb_timer_d;
- end
- end
//synchronize between GPIO and always-on(200KHz)
prim_flop_2sync # (
@@ -175,9 +62,9 @@
.clk_aon_i,
.rst_aon_ni,
.trigger_i(pwrb_int),
- .cfg_timer_i(cfg_ulp_pwrb_timer),
- .cfg_en_i(cfg_ulp_en),
- .timer_cond_met_o(pwrb_cond_met)
+ .cfg_timer_i(ulp_pwrb_debounce_ctl_i.q),
+ .cfg_en_i(ulp_ctl_i.q),
+ .timer_cond_met_o(pwrb_cond_met_d)
);
sysrst_ctrl_ulpfsm # (
@@ -187,9 +74,9 @@
.clk_aon_i,
.rst_aon_ni,
.trigger_i(lid_open_int),
- .cfg_timer_i(cfg_ulp_lid_timer),
- .cfg_en_i(cfg_ulp_en),
- .timer_cond_met_o(lid_open_cond_met)
+ .cfg_timer_i(ulp_lid_debounce_ctl_i.q),
+ .cfg_en_i(ulp_ctl_i.q),
+ .timer_cond_met_o(lid_open_cond_met_d)
);
sysrst_ctrl_ulpfsm # (
@@ -199,67 +86,44 @@
.clk_aon_i,
.rst_aon_ni,
.trigger_i(ac_present_int),
- .cfg_timer_i(cfg_ulp_ac_timer),
- .cfg_en_i(cfg_ulp_en),
- .timer_cond_met_o(ac_present_cond_met)
+ .cfg_timer_i(ulp_ac_debounce_ctl_i.q),
+ .cfg_en_i(ulp_ctl_i.q),
+ .timer_cond_met_o(ac_present_cond_met_d)
);
//delay the level signal to generate a pulse
+ logic pwrb_cond_met_d, pwrb_cond_met_q;
+ logic lid_open_cond_met_d, lid_open_cond_met_q;
+ logic ac_present_cond_met_d, ac_present_cond_met_q;
always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin: p_ulp_cond_met
if (!rst_aon_ni) begin
- pwrb_cond_met_q <= 1'b0;
- lid_open_cond_met_q <= 1'b0;
- ac_present_cond_met_q <= 1'b0;
+ pwrb_cond_met_q <= 1'b0;
+ lid_open_cond_met_q <= 1'b0;
+ ac_present_cond_met_q <= 1'b0;
end else begin
- pwrb_cond_met_q <= pwrb_cond_met;
- lid_open_cond_met_q <= lid_open_cond_met;
- ac_present_cond_met_q <= ac_present_cond_met;
+ pwrb_cond_met_q <= pwrb_cond_met_d;
+ lid_open_cond_met_q <= lid_open_cond_met_d;
+ ac_present_cond_met_q <= ac_present_cond_met_d;
end
end
- assign pwrb_det_pulse = cfg_ulp_en &&
- (pwrb_cond_met_q == 1'b0) && (pwrb_cond_met == 1'b1);
- assign lid_open_det_pulse = cfg_ulp_en &&
- (lid_open_cond_met_q == 1'b0) && (lid_open_cond_met == 1'b1);
- assign ac_present_det_pulse = cfg_ulp_en &&
- (ac_present_cond_met_q == 1'b0) && (ac_present_cond_met == 1'b1);
+ logic pwrb_det_pulse;
+ logic lid_open_det_pulse;
+ logic ac_present_det_pulse;
+ assign pwrb_det_pulse = pwrb_cond_met_d & ~pwrb_cond_met_q;
+ assign lid_open_det_pulse = lid_open_cond_met_d & ~lid_open_cond_met_q;
+ assign ac_present_det_pulse = ac_present_cond_met_d & ~ac_present_cond_met_q;
- //Synchronize from 200KHz always-onclock to 24MHz cfg clock
- prim_pulse_sync u_pwrb_det_pulse (
- .clk_src_i (clk_aon_i),
- .clk_dst_i (clk_i),
- .rst_src_ni (rst_aon_ni),
- .rst_dst_ni (rst_ni),
- .src_pulse_i (pwrb_det_pulse),
- .dst_pulse_o (cfg_pwrb_det_pulse)
- );
+ // aggregate pulses
+ assign ulp_wakeup_pulse_o = ulp_ctl_i.q & (pwrb_det_pulse |
+ lid_open_det_pulse |
+ ac_present_det_pulse);
- prim_pulse_sync u_lid_open_det_pulse (
- .clk_src_i (clk_aon_i),
- .clk_dst_i (clk_i),
- .rst_src_ni (rst_aon_ni),
- .rst_dst_ni (rst_ni),
- .src_pulse_i (lid_open_det_pulse),
- .dst_pulse_o (cfg_lid_open_det_pulse)
- );
-
- prim_pulse_sync u_ac_present_det_pulse (
- .clk_src_i (clk_aon_i),
- .clk_dst_i (clk_i),
- .rst_src_ni (rst_aon_ni),
- .rst_dst_ni (rst_ni),
- .src_pulse_i (ac_present_det_pulse),
- .dst_pulse_o (cfg_ac_present_det_pulse)
- );
-
- assign ulp_status_o.de =
- cfg_pwrb_det_pulse || cfg_lid_open_det_pulse || cfg_ac_present_det_pulse;
+ assign z3_wakeup_hw_o = pwrb_cond_met_d |
+ lid_open_cond_met_d |
+ ac_present_cond_met_d;
assign ulp_status_o.d = 1'b1;
-
- assign ulp_wakeup_o =
- cfg_pwrb_det_pulse || cfg_lid_open_det_pulse || cfg_ac_present_det_pulse;
-
- assign z3_wakeup_hw_o = pwrb_cond_met || lid_open_cond_met || ac_present_cond_met;
+ assign ulp_status_o.de = ulp_wakeup_pulse_o;
endmodule
