[top] Updates for silver - rename pwrmgr clamp envelope signal - minor correction for ast2pinmux bit width Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/ip/pwrmgr/rtl/pwrmgr_slow_fsm.sv b/hw/ip/pwrmgr/rtl/pwrmgr_slow_fsm.sv index e0a904e..9a7dbee 100644 --- a/hw/ip/pwrmgr/rtl/pwrmgr_slow_fsm.sv +++ b/hw/ip/pwrmgr/rtl/pwrmgr_slow_fsm.sv
@@ -46,7 +46,7 @@ // All power signals and signals going to analog logic are flopped to avoid transitional glitches logic pd_nq, pd_nd; logic pwr_clamp_q, pwr_clamp_d; - logic pwr_clamp_early_q, pwr_clamp_early_d; + logic pwr_clamp_env_q, pwr_clamp_env_d; logic core_clk_en_q, core_clk_en_d; logic io_clk_en_q, io_clk_en_d; logic usb_clk_en_q, usb_clk_en_d; @@ -74,7 +74,7 @@ // pwrmgr resets assuming main power domain is already ready pd_nq <= 1'b1; pwr_clamp_q <= 1'b0; - pwr_clamp_early_q <= 1'b0; + pwr_clamp_env_q <= 1'b0; core_clk_en_q <= 1'b0; io_clk_en_q <= 1'b0; usb_clk_en_q <= 1'b0; @@ -86,7 +86,7 @@ cause_toggle_q <= cause_toggle_d; pd_nq <= pd_nd; pwr_clamp_q <= pwr_clamp_d; - pwr_clamp_early_q <= pwr_clamp_early_d; + pwr_clamp_env_q <= pwr_clamp_env_d; core_clk_en_q <= core_clk_en_d; io_clk_en_q <= io_clk_en_d; usb_clk_en_q <= usb_clk_en_d; @@ -101,7 +101,7 @@ pd_nd = pd_nq; cause_toggle_d = cause_toggle_q; pwr_clamp_d = pwr_clamp_q; - pwr_clamp_early_d = pwr_clamp_early_q; + pwr_clamp_env_d = pwr_clamp_env_q; core_clk_en_d = core_clk_en_q; io_clk_en_d = io_clk_en_q; usb_clk_en_d = usb_clk_en_q; @@ -130,7 +130,7 @@ pd_nd = 1'b1; if (ast_i.main_pok) begin - pwr_clamp_early_d = 1'b0; + pwr_clamp_env_d = 1'b0; state_d = SlowPwrStatePwrClampOff; end end @@ -187,14 +187,14 @@ if (all_clks_invalid) begin // if main power is turned off, assert early clamp ahead - pwr_clamp_early_d = ~main_pd_ni; + pwr_clamp_env_d = ~main_pd_ni; state_d = SlowPwrStatePwrClampOn; end end SlowPwrStatePwrClampOn: begin // if main power is turned off, assert clamp ahead - pwr_clamp_d = pwr_clamp_early_q; + pwr_clamp_d = pwr_clamp_env_q; state_d = SlowPwrStateMainPowerOff; end @@ -230,7 +230,7 @@ assign ast_o.io_clk_en = io_clk_en_q; assign ast_o.usb_clk_en = usb_clk_en_q; assign ast_o.main_pd_n = pd_nq; - assign ast_o.pwr_clamp_early = pwr_clamp_early_q; + assign ast_o.pwr_clamp_env = pwr_clamp_env_q; assign ast_o.pwr_clamp = pwr_clamp_q; // This is hardwired to 1 all the time assign ast_o.slow_clk_en = 1'b1;