commit 01e57369053afc164ab77d7f85522271ab3ecfde
author Timothy Chen <timothytim@google.com> Fri Aug 12 17:30:36 2022 -0700
committer tjaychen <timothytim@google.com> Fri Aug 19 18:43:41 2022 -0700
tree 02ea2012b61fb9bea20f975daa01d02c209f13b4
parent 19a07f8d8987b9b9e8afe9d167e6024fbd5bf880

[prim] Tweak code slightly to avoid UNR entries

- there is no functional change
- the code is tweaked slightly to make UNR spit out fewer
  unreachable sections.
- the original code made the intent clearer, so to compensate,
  an assertion was added for the original spirit of operation.

Signed-off-by: Timothy Chen <timothytim@google.com>

hw/ip/prim/rtl/prim_reg_cdc.sv

diff --git a/hw/ip/prim/rtl/prim_reg_cdc.sv b/hw/ip/prim/rtl/prim_reg_cdc.sv
index b8bda09..3c4b648 100644
--- a/hw/ip/prim/rtl/prim_reg_cdc.sv
+++ b/hw/ip/prim/rtl/prim_reg_cdc.sv
@@ -3,6 +3,14 @@
 // SPDX-License-Identifier: Apache-2.0
 //
 // Component handling register CDC
+//
+// Currently, this module only works correctly when paired with tlul_adapter_reg.
+// This is because tlul_adapter_reg does not emit a new transaction to the same
+// register if it discovers it is currently busy. Please see the BusySrcReqChk_A
+// assertion below for more details.
+//
+// If in the future this assumption changes, we can modify this module easily to
+// support the new behavior.
 
 `include "prim_assert.sv"
 
@@ -91,7 +99,8 @@
     if (!rst_src_ni) begin
       src_q <= ResetVal;
       txn_bits_q <= '0;
-    end else if (src_req && !busy) begin
+    end else if (src_req) begin
+      // See assertion below
       // At the beginning of a software initiated transaction, the following
       // values are captured in the src_q/txn_bits_q flops to ensure they cannot
       // change for the duration of the synchronization operation.
@@ -111,6 +120,15 @@
     end
   end
 
+  // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
+  // (decoded from address) is busy. So this creates a situation in the current design where
+  // src_req_i and busy can never be high at the same time.
+  // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
+  // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
+  // condition cannot be met.
+  // Thus we add an assertion here to ensure the condition is always satisfied.
+  `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
+
   // reserved bits are not used
   logic unused_wd;
   assign unused_wd = ^src_wd_i;