| commit | 018dac54829f0309e6cd215f63e670c933e3fa6e | [log] [tgz] |
|---|---|---|
| author | Rupert Swarbrick <rswarbrick@lowrisc.org> | Thu Feb 03 11:31:46 2022 +0000 |
| committer | Rupert Swarbrick <rswarbrick@gmail.com> | Thu Feb 10 14:18:49 2022 +0000 |
| tree | 9136e029daeb238ade96c224e1e8b7b960788b00 | |
| parent | f63a2bce8ce882829bf584d273dee0b77ce7c131 [diff] |
[otbn,dv] Properly represent DMEM store latency in ISS This wouldn't matter except that we want to support a test where we invalidate the whole of DMEM (to trigger integrity errors) at some arbitrary point in the run. If we're unlucky and happen to do this just after executing a store then the RTL will apply the store on the following cycle (leaving valid integrity bits) but the ISS, which had applied the store already, would mark the location as having bad integrity. The correct fix is easy enough: keep an extra "pending" queue that only gets applied on the following cycle. Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
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