[top] Minor lint fixes
Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/ip/flash_ctrl/rtl/flash_phy.sv b/hw/ip/flash_ctrl/rtl/flash_phy.sv
index 7ec5c70..9de316f 100644
--- a/hw/ip/flash_ctrl/rtl/flash_phy.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_phy.sv
@@ -22,6 +22,7 @@
input flash_req_t flash_ctrl_i,
output flash_rsp_t flash_ctrl_o,
input scanmode_i,
+ input scan_en_i,
input scan_rst_ni,
input flash_power_ready_h_i,
input flash_power_down_h_i,
@@ -265,6 +266,7 @@
.tdo_o(tdo),
.bist_enable_i(flash_bist_enable_i & lc_nvm_debug_en[FlashBistSel]),
.scanmode_i,
+ .scan_en_i,
.scan_rst_ni,
.flash_power_ready_h_i,
.flash_power_down_h_i,
diff --git a/hw/ip/prim/lint/prim_clock_div.waiver b/hw/ip/prim/lint/prim_clock_div.waiver
index c9b4a73..bd6e48c 100644
--- a/hw/ip/prim/lint/prim_clock_div.waiver
+++ b/hw/ip/prim/lint/prim_clock_div.waiver
@@ -6,3 +6,6 @@
waive -rules DUAL_EDGE_CLOCK -location {prim_clock_div.sv} -regexp {.*} \
-comment "The clock switch signal is synchronized on negative edge to ensure it is away from any transition"
+
+waive -rules CLOCK_MUX -location {prim_clock_div.sv} -regexp {.*reaches a multiplexer here, used as a clock.*} \
+ -comment "A mux is used during scan bypass, and for switching between div by 2 and div by 1 clocks"
diff --git a/hw/ip/rstmgr/rtl/rstmgr_por.sv b/hw/ip/rstmgr/rtl/rstmgr_por.sv
index 74aed24..01eaa97 100644
--- a/hw/ip/rstmgr/rtl/rstmgr_por.sv
+++ b/hw/ip/rstmgr/rtl/rstmgr_por.sv
@@ -62,18 +62,31 @@
assign cnt_en = rst_stable & !rst_no;
// stretch the POR
+ logic rst_nd, rst_nq;
+
+ assign rst_nd = ~rst_stable ? 1'b0 :
+ cnt_en & (cnt == StretchCount) ? 1'b1 : rst_nq;
+
always_ff @(posedge clk_i or negedge rst_clean_n) begin
if (!rst_clean_n) begin
cnt <= '0;
- rst_no <= '0;
end else if (!rst_stable) begin
cnt <= '0;
- rst_no <= '0;
- end else if (cnt_en && cnt == StretchCount) begin
- rst_no <= 1'b1;
end else if (cnt_en) begin
cnt <= cnt + 1'b1;
end
end
+ prim_flop #(
+ .Width(1),
+ .ResetValue('0)
+ ) u_rst_flop (
+ .clk_i,
+ .rst_ni(rst_clean_n),
+ .d_i(rst_nd),
+ .q_o(rst_nq)
+ );
+
+ assign rst_no = rst_nq;
+
endmodule // rstmgr_por
diff --git a/hw/ip/sram_ctrl/rtl/sram_ctrl.sv b/hw/ip/sram_ctrl/rtl/sram_ctrl.sv
index 5e98bd4..25c5f0e 100644
--- a/hw/ip/sram_ctrl/rtl/sram_ctrl.sv
+++ b/hw/ip/sram_ctrl/rtl/sram_ctrl.sv
@@ -84,6 +84,10 @@
assign hw2reg.error_address.de = sram_scr_i.rerror[1];
assign parity_error_d = parity_error_q | sram_scr_i.rerror[1];
+ // Correctable RAM errors are not supported
+ logic unused_error;
+ assign unused_error = sram_scr_i.rerror[0];
+
//////////////////
// Alert Sender //
diff --git a/hw/top_earlgrey/data/top_earlgrey.sv.tpl b/hw/top_earlgrey/data/top_earlgrey.sv.tpl
index 39ea30f..bca5798 100644
--- a/hw/top_earlgrey/data/top_earlgrey.sv.tpl
+++ b/hw/top_earlgrey/data/top_earlgrey.sv.tpl
@@ -86,6 +86,7 @@
% endfor
% endif
input scan_rst_ni, // reset used for test mode
+ input scan_en_i,
input scanmode_i // 1 for Scan
);
@@ -498,6 +499,7 @@
.flash_test_mode_a_i,
.flash_test_voltage_h_i,
.scanmode_i,
+ .scan_en_i,
.scan_rst_ni
);
diff --git a/hw/top_earlgrey/lint/top_earlgrey.waiver b/hw/top_earlgrey/lint/top_earlgrey.waiver
index 78340ab..d608017 100644
--- a/hw/top_earlgrey/lint/top_earlgrey.waiver
+++ b/hw/top_earlgrey/lint/top_earlgrey.waiver
@@ -12,6 +12,10 @@
waive -rules RESET_MUX -location {top_earlgrey.sv} -regexp {Asynchronous reset .*rstmgr_aon_resets\.rst.* is driven by a multiplexer} \
-comment "This is dedicated reset infrastructure, and hence permissible"
+waive -rules CLOCK_MUX -location {clkmgr.sv top_earlgrey.sv} -regexp {.*clk_io_div.* is driven by a multiplexer here} \
+ -comment "Divided clocks go through prim_clock_div, which use muxes for scan bypass and clock step down"
+
+
## xbar
#waive -rules HIER_NET_NOT_READ -location {tlul_xbar.sv} -regexp {a_source.* is not read from} \
# -comment "upper bits of a_source are shifted off when going through M:1 sockets"
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index 93ab59a..b982134 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -78,6 +78,7 @@
output clkmgr_pkg::clkmgr_ast_out_t clks_ast_o,
output rstmgr_pkg::rstmgr_ast_out_t rsts_ast_o,
input scan_rst_ni, // reset used for test mode
+ input scan_en_i,
input scanmode_i // 1 for Scan
);
@@ -871,6 +872,7 @@
.flash_test_mode_a_i,
.flash_test_voltage_h_i,
.scanmode_i,
+ .scan_en_i,
.scan_rst_ni
);
diff --git a/hw/top_earlgrey/rtl/top_earlgrey_asic.sv b/hw/top_earlgrey/rtl/top_earlgrey_asic.sv
index 0a1a69c..e97a99c 100644
--- a/hw/top_earlgrey/rtl/top_earlgrey_asic.sv
+++ b/hw/top_earlgrey/rtl/top_earlgrey_asic.sv
@@ -306,6 +306,7 @@
// DFT signals
.scan_rst_ni ( 1'b1 ),
+ .scan_en_i ( 1'b0 ),
.scanmode_i ( 1'b0 )
);
diff --git a/hw/top_earlgrey/rtl/top_earlgrey_nexysvideo.sv b/hw/top_earlgrey/rtl/top_earlgrey_nexysvideo.sv
index 1f0551d..37e90c7 100644
--- a/hw/top_earlgrey/rtl/top_earlgrey_nexysvideo.sv
+++ b/hw/top_earlgrey/rtl/top_earlgrey_nexysvideo.sv
@@ -437,6 +437,7 @@
// DFT signals
.scan_rst_ni ( 1'b1 ),
+ .scan_en_i ( 1'b0 ),
.scanmode_i ( 1'b0 )
);
diff --git a/hw/top_earlgrey/rtl/top_earlgrey_verilator.sv b/hw/top_earlgrey/rtl/top_earlgrey_verilator.sv
index eaba896..f5754df 100644
--- a/hw/top_earlgrey/rtl/top_earlgrey_verilator.sv
+++ b/hw/top_earlgrey/rtl/top_earlgrey_verilator.sv
@@ -142,6 +142,7 @@
// DFT signals
.scan_rst_ni (1'b1),
+ .scan_en_i (1'b0),
.scanmode_i (1'b0)
);
