Initial ISPYocto commit Change-Id: Ic0aed4fe52adff407c27a7dae74bd9708f5cd17f
diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md new file mode 100644 index 0000000..593455a --- /dev/null +++ b/CONTRIBUTING.md
@@ -0,0 +1,28 @@ +# How to Contribute + +We'd love to accept your patches and contributions to this project. There are +just a few small guidelines you need to follow. + +## Contributor License Agreement + +Contributions to this project must be accompanied by a Contributor License +Agreement. You (or your employer) retain the copyright to your contribution; +this simply gives us permission to use and redistribute your contributions as +part of the project. Head over to <https://cla.developers.google.com/> to see +your current agreements on file or to sign a new one. + +You generally only need to submit a CLA once, so if you've already submitted one +(even if it was for a different project), you probably don't need to do it +again. + +## Code Reviews + +All submissions, including submissions by project members, require review. We +use Gerrit code review for this purpose. Consult +[Gerrit User Guide](https://gerrit-documentation.storage.googleapis.com/Documentation/3.8.2/intro-user.html) +for more information. + +## Community Guidelines + +This project follows +[Google's Open Source Community Guidelines](https://opensource.google/conduct/).
diff --git a/LICENSE b/LICENSE new file mode 100644 index 0000000..7a4a3ea --- /dev/null +++ b/LICENSE
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diff --git a/ispyocto/rtl/inc/vsisp_AQ_timescale.vh b/ispyocto/rtl/inc/vsisp_AQ_timescale.vh new file mode 100644 index 0000000..7c100af --- /dev/null +++ b/ispyocto/rtl/inc/vsisp_AQ_timescale.vh
@@ -0,0 +1,22 @@ +//**************************************************************************** +// +// Copyright 2023 Vivante Corp. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +`timescale 1ps / 1ps
diff --git a/ispyocto/rtl/inc/vsisp_f_sqrt_8bit.vh b/ispyocto/rtl/inc/vsisp_f_sqrt_8bit.vh new file mode 100644 index 0000000..6d79df5 --- /dev/null +++ b/ispyocto/rtl/inc/vsisp_f_sqrt_8bit.vh
@@ -0,0 +1,129 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +function [7:0] f_sqrt_8bit; + input [11:0] in_data_12bit; + reg [1:0] v_mux; + reg [7:0] v_in_mux; + reg [3:0] v_segment; + reg [1:0] v_p2_dx; + reg [7:0] v_y_i; + reg [4:0] v_dy; + reg [2:0] v_x_int; + reg [4:0] v_delta_x; + reg [9:0] v_prod_1; + reg [6:0] v_delta_y4; + reg [9:0] v_y_sum; + reg [7:0] v_y_out; + reg [7:0] v_out_sqrt; + reg [8:0] v_out_sqrt_mux; + reg [8:0] v_sqrt_round; + begin + v_mux = (in_data_12bit[11: 8] == 4'h0) ? 2'h0 : + (in_data_12bit[11:10] == 2'h0) ? 2'h1 : 2'h2; + case (v_mux) + 2'd0 : v_in_mux = in_data_12bit[7:0]; + 2'd1 : v_in_mux = in_data_12bit[9:2]; + default: v_in_mux = in_data_12bit[11:4]; + endcase + if (v_in_mux[7:4] == 4'd0) begin + if (v_in_mux[3:0] == 4'd0) v_segment=0; + else if (v_in_mux[3:2] == 2'd0) v_segment=1; + else if (v_in_mux[3 ] == 1'd0) v_segment=2; + else v_segment=3; + end else if (v_in_mux[7] == 1'd0) begin + if (v_in_mux[6:4] == 3'd1) v_segment=4; + else if (v_in_mux[6:4] == 3'd2) v_segment=5; + else if (v_in_mux[6:5] == 2'd1) v_segment=6; + else if (v_in_mux[6:5] == 2'd2) v_segment=7; + else v_segment=8; + end else begin + case (v_in_mux[6:5]) + 2'd0 : v_segment=9; + 2'd1 : v_segment=10; + 2'd2 : v_segment=11; + default : v_segment=12; + endcase + end + case(v_segment) + 4'd0 : v_y_i = 8'd0; + 4'd1 : v_y_i = 8'd11; + 4'd2 : v_y_i = 8'd32; + 4'd3 : v_y_i = 8'd46; + 4'd4 : v_y_i = 8'd65; + 4'd5 : v_y_i = 8'd91; + 4'd6 : v_y_i = 8'd111; + 4'd7 : v_y_i = 8'd128; + 4'd8 : v_y_i = 8'd157; + 4'd9 : v_y_i = 8'd181; + 4'd10 : v_y_i = 8'd203; + 4'd11 : v_y_i = 8'd222; + default: v_y_i = 8'd240; + endcase + case(v_segment) + 4'd0 : v_dy = 5'd0; + 4'd1 : v_dy = 5'd21; + 4'd2 : v_dy = 5'd14; + 4'd3 : v_dy = 5'd19; + 4'd4 : v_dy = 5'd26; + 4'd5 : v_dy = 5'd20; + 4'd6 : v_dy = 5'd17; + 4'd7 : v_dy = 5'd29; + 4'd8 : v_dy = 5'd24; + 4'd9 : v_dy = 5'd22; + 4'd10 : v_dy = 5'd19; + 4'd11 : v_dy = 5'd18; + default: v_dy = 5'd16; + endcase + case (v_segment) + 4'd2 : v_x_int = 3'd1; + 4'd3 : v_x_int = 3'd2; + 4'd4 : v_x_int = 3'd4; + 4'd6 : v_x_int = 3'd4; + default: v_x_int = 3'd0; + endcase + case(v_segment) + 4'd0 : v_p2_dx = 2'd0; + 4'd1 : v_p2_dx = 2'd0; + 4'd2 : v_p2_dx = 2'd0; + 4'd3 : v_p2_dx = 2'd1; + 4'd4 : v_p2_dx = 2'd2; + 4'd5 : v_p2_dx = 2'd2; + 4'd6 : v_p2_dx = 2'd2; + default: v_p2_dx = 2'd3; + endcase + v_delta_x = {(v_in_mux[4:2] - v_x_int), v_in_mux[1:0]}; + v_prod_1 = v_delta_x * v_dy; + v_delta_y4 = v_prod_1 >> v_p2_dx; + v_y_sum = {2'b0, v_delta_y4[6:1]} + {1'b0, v_y_i, 1'b1}; + v_y_out = v_y_sum[8:1]; + v_out_sqrt = (v_y_sum[9]) ? 8'd255 : v_y_out; + case (v_mux) + 2'd0 : v_out_sqrt_mux = {2'b0,v_out_sqrt[7:1]}; + 2'd1 : v_out_sqrt_mux = {1'b0,v_out_sqrt} ; + default: v_out_sqrt_mux = {v_out_sqrt, 1'b0}; + endcase + v_sqrt_round = v_out_sqrt_mux +1; + f_sqrt_8bit = v_sqrt_round[8:1]; + end +endfunction
diff --git a/ispyocto/rtl/inc/vsisp_gc_allDefinesForBench.vh b/ispyocto/rtl/inc/vsisp_gc_allDefinesForBench.vh new file mode 100644 index 0000000..b90bd35 --- /dev/null +++ b/ispyocto/rtl/inc/vsisp_gc_allDefinesForBench.vh
@@ -0,0 +1,33 @@ +//**************************************************************************** +// +// Copyright 2023 Vivante Corp. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** +`define VIVANTE_ASYNC_RESET +`define RAM_IF_OUT +`define MI_BURST_16_DMAFIFO_16 +`define AQ_TIMESCALE_ON +`define MARVIN_USE_SRAMFIFO_MIBP +`define MARVIN_SCLK_MUX_DISABLE +`define MARVIN_USE_SELF_PATH +`define VIVANTE_RESET_DATA_FLOPS +`define YUV_STREAM_OUT +`define ISP_USE_TPG +`define MARVIN_USE_SRAMFIFO_MIMP +`define VS_USE_SRAMFIFO_MIMP +`define ISP_USE_DGAIN
diff --git a/ispyocto/rtl/inc/vsisp_isp.vh b/ispyocto/rtl/inc/vsisp_isp.vh new file mode 100644 index 0000000..c380d76 --- /dev/null +++ b/ispyocto/rtl/inc/vsisp_isp.vh
@@ -0,0 +1,252 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +parameter c_dw_si = 12; +parameter c_dw_do = 10; +parameter c_irq_bw = 20; +parameter c_isp_err_bw = 3; +parameter c_cfg_aw = 6; +parameter c_dpcc_fix_median = 1'b0; +parameter exp_v2_input_width = 10; +parameter exp_v2_output_width = 8; +parameter c_dw_ni = 10; +parameter c_dw_nf = 10; +parameter c_xr = 0; +parameter c_dw_spc = 5; +parameter c_white_cnt = 27; +parameter c_awb_acc_width = 35; +parameter c_dw_crt_coeff = 11; +parameter c_dw_csm_coeff = 9; +parameter c_div_state_0 = 3'd0; +parameter c_div_state_1 = 3'd1; +parameter c_div_state_2 = 3'd2; +parameter c_div_state_3 = 3'd3; +parameter c_div_state_4 = 3'd4; +parameter c_reset_state = 3'd5; +parameter c_r = 2'b00; +parameter c_gr = 2'b01; +parameter c_gb = 2'b10; +parameter c_b = 2'b11; +parameter c_idle = 3'd0; +parameter c_cap_delay = 3'd1; +parameter c_prelight = 3'd2; +parameter c_dly = 3'd3; +parameter c_flash = 3'd4; +parameter c_sh_idle = 2'd0; +parameter c_sh_dly = 2'd1; +parameter c_sh_open = 2'd2; +parameter c_single_end = 2'd3; +parameter c_pre0 = 2'd0; +parameter c_pre1 = 2'd1; +parameter c_pre2 = 2'd2; +parameter c_status = 2'd3; +parameter c_reset = 3'h0; +parameter c_rd_p0 = 3'h4; +parameter c_rd_p1 = 3'h5; +parameter c_even = 3'h6; +parameter c_odd_wr = 3'h7; +parameter c_line_end_even = 3'h2; +parameter c_line_end_odd_wr = 3'h3; +parameter c_dpf_last_line = 4'h8; +parameter c_dpf_line_delay = 4'h4; +parameter c_dpcc_last_line = 3'h4; +parameter c_dpcc_line_delay = 3'h2; +parameter c_last_line = 4'h8; +parameter c_line_delay = 4'h4; +parameter c_cfg_afm = 6; +parameter c_h_aw_afm = 13; +parameter c_v_aw_afm = 13; +parameter c_iw = c_dw_si; +parameter c_dw = 8; +parameter c_gw = 11; +parameter c_sqrw = 22; +parameter c_sw = 32; +parameter c_ow = 32; +parameter c_red = 2'd0; +parameter c_green0 = 2'd1; +parameter c_blue = 2'd2; +parameter c_green1 = 2'd3; +parameter c_cfg_is = 6; +parameter c_hist_bin_cnt_width = 20; +parameter c_cfg_lsc = 7; +parameter c_cfg_awb = 9; +parameter c_cfg_wdrt = 14; +parameter c_isp_base_adr = 14'h400; +parameter c_tpg_base_adr = 14'h500; +parameter c_fps_crop_binning_base_adr = 14'h600; +parameter c_bls_base_adr = 14'h700; +parameter c_dgain_base_adr = 14'h800; +parameter c_filt_base_adr = 14'h810; +parameter c_cac_base_adr = c_filt_base_adr + 14'h060; +parameter c_exp_base_adr = 14'h0720; +parameter c_gamma_out_base_adr = 14'h900; +parameter c_csm_base_adr = 14'ha00; +parameter c_cross_talk_base_adr = 14'ha30; +parameter c_isp_int_base_adr = 14'hb00; +parameter c_awb_meas_old_base_adr = 14'h950; +parameter c_ctrl = c_isp_base_adr + 14'h000; +parameter c_acq_prop = c_isp_base_adr + 14'h004; +parameter c_acq_h_offs = c_isp_base_adr + 14'h008; +parameter c_acq_v_offs = c_isp_base_adr + 14'h00C; +parameter c_acq_h_size = c_isp_base_adr + 14'h010; +parameter c_acq_v_size = c_isp_base_adr + 14'h014; +parameter c_tpg_global = c_tpg_base_adr + 14'h000; +parameter c_tpg_total = c_tpg_base_adr + 14'h004; +parameter c_tpg_act = c_tpg_base_adr + 14'h008; +parameter c_tpg_fp = c_tpg_base_adr + 14'h00c; +parameter c_tpg_bp = c_tpg_base_adr + 14'h010; +parameter c_tpg_w = c_tpg_base_adr + 14'h014; +parameter c_tpg_gap = c_tpg_base_adr + 14'h018; +parameter c_tpg_gap_std = c_tpg_base_adr + 14'h01c; +parameter c_tpg_seed = c_tpg_base_adr + 14'h020; +parameter c_tpg_frm_num = c_tpg_base_adr + 14'h024; +parameter c_frame_rate_ctrl = c_fps_crop_binning_base_adr + 14'h000; +parameter c_out_h_offs = c_fps_crop_binning_base_adr + 14'h004; +parameter c_out_v_offs = c_fps_crop_binning_base_adr + 14'h008; +parameter c_out_h_size = c_fps_crop_binning_base_adr + 14'h00c; +parameter c_out_v_size = c_fps_crop_binning_base_adr + 14'h010; +parameter c_out_h_offs_shd = c_fps_crop_binning_base_adr + 14'h014; +parameter c_out_v_offs_shd = c_fps_crop_binning_base_adr + 14'h018; +parameter c_out_h_size_shd = c_fps_crop_binning_base_adr + 14'h01c; +parameter c_out_v_size_shd = c_fps_crop_binning_base_adr + 14'h020; +parameter c_binning_step = c_fps_crop_binning_base_adr + 14'h024; +parameter c_binning_num = c_fps_crop_binning_base_adr + 14'h028; +parameter c_binning_step_shd = c_fps_crop_binning_base_adr + 14'h02c; +parameter c_binning_num_shd = c_fps_crop_binning_base_adr + 14'h030; +parameter c_cfg_bls = 7; +parameter c_bls_ctrl = c_bls_base_adr + 14'h000; +parameter c_bls_a_fixed = c_bls_base_adr + 14'h004; +parameter c_bls_b_fixed = c_bls_base_adr + 14'h008; +parameter c_bls_c_fixed = c_bls_base_adr + 14'h00c; +parameter c_bls_d_fixed = c_bls_base_adr + 14'h010; +parameter c_dgain_0 = c_dgain_base_adr + 14'h000; +parameter c_dgain_1 = c_dgain_base_adr + 14'h004; +parameter c_dgain_0_shd = c_dgain_base_adr + 14'h008; +parameter c_dgain_1_shd = c_dgain_base_adr + 14'h00c; +parameter c_cfg_filt = 8; +parameter c_demosaic = c_filt_base_adr + 14'h000; +parameter c_filt_mode = c_filt_base_adr + 14'h004; +parameter c_filt_thres_bl0 = c_filt_base_adr + 14'h008; +parameter c_filt_thres_bl1 = c_filt_base_adr + 14'h00c; +parameter c_filt_thres_sh0 = c_filt_base_adr + 14'h010; +parameter c_filt_thres_sh1 = c_filt_base_adr + 14'h014; +parameter c_filt_lum_weigt = c_filt_base_adr + 14'h018; +parameter c_filt_fac_sh1 = c_filt_base_adr + 14'h01c; +parameter c_filt_fac_sh0 = c_filt_base_adr + 14'h020; +parameter c_filt_fac_mid = c_filt_base_adr + 14'h024; +parameter c_filt_fac_bl0 = c_filt_base_adr + 14'h028; +parameter c_filt_fac_bl1 = c_filt_base_adr + 14'h02c; +parameter c_cac_ctrl = c_cac_base_adr + 14'h000; +parameter c_cac_count_start = c_cac_base_adr + 14'h004; +parameter c_cac_a = c_cac_base_adr + 14'h008; +parameter c_cac_b = c_cac_base_adr + 14'h00C; +parameter c_cac_c = c_cac_base_adr + 14'h010; +parameter c_cac_x_norm = c_cac_base_adr + 14'h014; +parameter c_cac_y_norm = c_cac_base_adr + 14'h018; +parameter c_gamma_out_mod = c_gamma_out_base_adr + 14'h000; +parameter c_gamma_out_y0 = c_gamma_out_base_adr + 14'h004; +parameter c_gamma_out_y1 = c_gamma_out_base_adr + 14'h008; +parameter c_gamma_out_y2 = c_gamma_out_base_adr + 14'h00c; +parameter c_gamma_out_y3 = c_gamma_out_base_adr + 14'h010; +parameter c_gamma_out_y4 = c_gamma_out_base_adr + 14'h014; +parameter c_gamma_out_y5 = c_gamma_out_base_adr + 14'h018; +parameter c_gamma_out_y6 = c_gamma_out_base_adr + 14'h01c; +parameter c_gamma_out_y7 = c_gamma_out_base_adr + 14'h020; +parameter c_gamma_out_y8 = c_gamma_out_base_adr + 14'h024; +parameter c_gamma_out_y9 = c_gamma_out_base_adr + 14'h028; +parameter c_gamma_out_y10 = c_gamma_out_base_adr + 14'h02c; +parameter c_gamma_out_y11 = c_gamma_out_base_adr + 14'h030; +parameter c_gamma_out_y12 = c_gamma_out_base_adr + 14'h034; +parameter c_gamma_out_y13 = c_gamma_out_base_adr + 14'h038; +parameter c_gamma_out_y14 = c_gamma_out_base_adr + 14'h03c; +parameter c_gamma_out_y15 = c_gamma_out_base_adr + 14'h040; +parameter c_gamma_out_y16 = c_gamma_out_base_adr + 14'h044; +parameter c_cc_coeff_0 = c_csm_base_adr + 14'h000; +parameter c_cc_coeff_1 = c_csm_base_adr + 14'h004; +parameter c_cc_coeff_2 = c_csm_base_adr + 14'h008; +parameter c_cc_coeff_3 = c_csm_base_adr + 14'h00c; +parameter c_cc_coeff_4 = c_csm_base_adr + 14'h010; +parameter c_cc_coeff_5 = c_csm_base_adr + 14'h014; +parameter c_cc_coeff_6 = c_csm_base_adr + 14'h018; +parameter c_cc_coeff_7 = c_csm_base_adr + 14'h01c; +parameter c_cc_coeff_8 = c_csm_base_adr + 14'h020; +parameter c_format_conv_ctrl = c_csm_base_adr + 14'h024; +parameter c_ct_coeff_0 = c_cross_talk_base_adr + 14'h000; +parameter c_ct_coeff_1 = c_cross_talk_base_adr + 14'h004; +parameter c_ct_coeff_2 = c_cross_talk_base_adr + 14'h008; +parameter c_ct_coeff_3 = c_cross_talk_base_adr + 14'h00c; +parameter c_ct_coeff_4 = c_cross_talk_base_adr + 14'h010; +parameter c_ct_coeff_5 = c_cross_talk_base_adr + 14'h014; +parameter c_ct_coeff_6 = c_cross_talk_base_adr + 14'h018; +parameter c_ct_coeff_7 = c_cross_talk_base_adr + 14'h01c; +parameter c_ct_coeff_8 = c_cross_talk_base_adr + 14'h020; +parameter c_ct_offset_r = c_cross_talk_base_adr + 14'h024; +parameter c_ct_offset_g = c_cross_talk_base_adr + 14'h028; +parameter c_ct_offset_b = c_cross_talk_base_adr + 14'h02c; +parameter c_imsc = c_isp_int_base_adr + 14'h000; +parameter c_ris = c_isp_int_base_adr + 14'h004; +parameter c_mis = c_isp_int_base_adr + 14'h008; +parameter c_icr = c_isp_int_base_adr + 14'h00c; +parameter c_isr = c_isp_int_base_adr + 14'h010; +parameter c_isp_err = c_isp_int_base_adr + 14'h014; +parameter c_isp_err_clear = c_isp_int_base_adr + 14'h018; +parameter c_exp_conf = c_exp_base_adr + 14'h000; +parameter c_exp_h_offset = c_exp_base_adr + 14'h004; +parameter c_exp_v_offset = c_exp_base_adr + 14'h008; +parameter c_exp_h_size = c_exp_base_adr + 14'h00C; +parameter c_exp_v_size = c_exp_base_adr + 14'h010; +parameter c_exp_mean_00 = c_exp_base_adr + 14'h014; +parameter c_exp_mean_10 = c_exp_base_adr + 14'h018; +parameter c_exp_mean_20 = c_exp_base_adr + 14'h01c; +parameter c_exp_mean_30 = c_exp_base_adr + 14'h020; +parameter c_exp_mean_40 = c_exp_base_adr + 14'h024; +parameter c_exp_mean_01 = c_exp_base_adr + 14'h028; +parameter c_exp_mean_11 = c_exp_base_adr + 14'h02c; +parameter c_exp_mean_21 = c_exp_base_adr + 14'h030; +parameter c_exp_mean_31 = c_exp_base_adr + 14'h034; +parameter c_exp_mean_41 = c_exp_base_adr + 14'h038; +parameter c_exp_mean_02 = c_exp_base_adr + 14'h03c; +parameter c_exp_mean_12 = c_exp_base_adr + 14'h040; +parameter c_exp_mean_22 = c_exp_base_adr + 14'h044; +parameter c_exp_mean_32 = c_exp_base_adr + 14'h048; +parameter c_exp_mean_42 = c_exp_base_adr + 14'h04c; +parameter c_exp_mean_03 = c_exp_base_adr + 14'h050; +parameter c_exp_mean_13 = c_exp_base_adr + 14'h054; +parameter c_exp_mean_23 = c_exp_base_adr + 14'h058; +parameter c_exp_mean_33 = c_exp_base_adr + 14'h05c; +parameter c_exp_mean_43 = c_exp_base_adr + 14'h060; +parameter c_exp_mean_04 = c_exp_base_adr + 14'h064; +parameter c_exp_mean_14 = c_exp_base_adr + 14'h068; +parameter c_exp_mean_24 = c_exp_base_adr + 14'h06c; +parameter c_exp_mean_34 = c_exp_base_adr + 14'h070; +parameter c_exp_mean_44 = c_exp_base_adr + 14'h074; +parameter c_awb_prop = c_awb_meas_old_base_adr + 14'h000; +parameter c_awb_h_offs_old = c_awb_meas_old_base_adr + 14'h004; +parameter c_awb_v_offs_old = c_awb_meas_old_base_adr + 14'h008; +parameter c_awb_h_size_old = c_awb_meas_old_base_adr + 14'h00C; +parameter c_awb_v_size_old = c_awb_meas_old_base_adr + 14'h010; +parameter c_awb_frames = c_awb_meas_old_base_adr + 14'h014; +parameter c_awb_ref = c_awb_meas_old_base_adr + 14'h018; +parameter c_awb_thres = c_awb_meas_old_base_adr + 14'h01C; +parameter c_awb_white_cnt = c_awb_meas_old_base_adr + 14'h030; +parameter c_awb_mean = c_awb_meas_old_base_adr + 14'h034;
diff --git a/ispyocto/rtl/inc/vsisp_jpeg_r2b.vh b/ispyocto/rtl/inc/vsisp_jpeg_r2b.vh new file mode 100644 index 0000000..317d6a2 --- /dev/null +++ b/ispyocto/rtl/inc/vsisp_jpeg_r2b.vh
@@ -0,0 +1,37 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + + parameter c_rot_line_length = 13'd1920; + parameter c_rot_ram_aw = 8'd14; + parameter c_img_w = 16'd13; + parameter c_img_h = 16'd14; + parameter c_mcu_cnt_w = 16'd20; + parameter c_jpeg_in = c_img_w +1 ; + parameter c_ram1_aw = c_img_w +1 ; + parameter c_ram2_aw = c_rot_ram_aw; + parameter c_ram_dw = 16'd32; + parameter c_jpeg_r2bram_pipelined = 1'b0; + parameter c_share_rams = 1'b0; + parameter c_ram1_size = 16'd16384; + parameter c_rot_ram_size = 16'd15360; + parameter c_ram2_size = c_share_rams ? c_ram1_size + c_rot_ram_size : c_ram1_size;
diff --git a/ispyocto/rtl/inc/vsisp_marvin_ctrl.vh b/ispyocto/rtl/inc/vsisp_marvin_ctrl.vh new file mode 100644 index 0000000..897246d --- /dev/null +++ b/ispyocto/rtl/inc/vsisp_marvin_ctrl.vh
@@ -0,0 +1,50 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +parameter c_paddr_word = 32; +parameter c_pwdata_word = 32; +parameter c_prdata_word = 32; +parameter c_iccl_word = 7; +parameter c_ircl_word = 8; +parameter c_vi_ccl_addr = 8'h00; +parameter c_vi_iccl_addr = 8'h10; +parameter c_vi_ircl_addr = 8'h14; +parameter c_vi_dpcl_addr = 8'h18; +parameter c_vi_id_rsv0_addr = 8'h34; +parameter c_vi_id_rsv1_addr = 8'h38; +parameter c_vi_id_rsv2_addr = 8'h3c; +parameter c_vi_id_rsv3_addr = 8'h40; +parameter c_vi_id_rsv4_addr = 8'h44; +parameter c_vi_id_rsv5_addr = 8'h48; +parameter c_vi_id_rsv6_addr = 8'h4c; +parameter c_vi_id_rsv7_addr = 8'h50; +parameter c_ctrl_addr = 5'b00000; +parameter c_isp_start_addr = 5'b00100; +parameter c_isp_end_addr = 5'b01100; +parameter c_mrsz_addr = 5'b01100; +parameter c_srsz_addr = 6'b100000; +parameter c_mi_addr = 4'hd; +parameter c_cfg_addr_word = 32; +parameter c_cfg_wdata_word = 32; +parameter c_cfg_rdata32_word = 32; +parameter c_prdata_ctrl_off = 32'hDEADDEAD;
diff --git a/ispyocto/rtl/inc/vsisp_marvin_id.vh b/ispyocto/rtl/inc/vsisp_marvin_id.vh new file mode 100644 index 0000000..9da0d81 --- /dev/null +++ b/ispyocto/rtl/inc/vsisp_marvin_id.vh
@@ -0,0 +1,59 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +parameter c_isp_id_custom_id = 32'h500000B9; +parameter c_product_id_aux = 4'h0; +parameter c_product_id_type = 4'h0; +parameter c_product_id_num = 20'h08000; +parameter c_product_id_grade_level = 4'h6; +parameter c_isp_id_product_id = {c_product_id_aux,c_product_id_type,c_product_id_num,c_product_id_grade_level}; +parameter c_isp_id_chip_id = 32'h00008000; +parameter c_isp_id_eco_id = 32'h0; +parameter c_isp_id_chip_revision = 32'h00007100; +parameter c_isp_id_patch_revision = 32'd6; +parameter c_isp_id_chip_date = 32'h20231017; +parameter c_isp_id_chip_time = 32'h1800; +parameter c_marvin_id_0 = 32'ha100; +parameter c_marvin_id_1 = 32'ha1; +parameter c_marvin_id_2 = 32'ha2; +parameter c_marvin_id_3 = 32'ha3; +parameter c_marvin_id_4 = 32'ha4; +parameter c_marvin_id_5 = 32'ha5; +parameter c_marvin_id_6 = 32'ha6; +parameter c_marvin_id_7 = 32'ha7; +parameter c_marvin_id_rsv0 = 32'ha100; +parameter c_marvin_id_rsv1 = 32'ha1; +parameter c_marvin_id_rsv2 = 32'ha2; +parameter c_marvin_id_rsv3 = 32'ha3; +parameter c_marvin_id_rsv4 = 32'ha4; +parameter c_marvin_id_rsv5 = 32'ha5; +parameter c_marvin_id_rsv6 = 32'ha6; +parameter c_marvin_id_rsv7 = 32'ha7; +parameter c_isp_id_custom_id_addr = 8'h04; +parameter c_isp_id_product_id_addr = 8'h08; +parameter c_isp_id_chip_id_addr = 8'h0c; +parameter c_isp_id_eco_id_addr = 8'h20; +parameter c_isp_id_chip_revision_addr = 8'h24; +parameter c_isp_id_patch_revision_addr = 8'h28; +parameter c_isp_id_chip_date_addr = 8'h2c; +parameter c_isp_id_chip_time_addr = 8'h30;
diff --git a/ispyocto/rtl/inc/vsisp_marvin_mi.vh b/ispyocto/rtl/inc/vsisp_marvin_mi.vh new file mode 100644 index 0000000..60e6e20 --- /dev/null +++ b/ispyocto/rtl/inc/vsisp_marvin_mi.vh
@@ -0,0 +1,35 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + + parameter c_bursts_supported = 5'd16; + parameter c_fifo_depth = (c_bursts_supported == 5'd16) ? 32 : + (c_bursts_supported == 5'd8) ? 16 : 8; + parameter c_addr_width = (c_fifo_depth == 32) ? 5 : + (c_fifo_depth == 16) ? 4 : 3; + parameter c_burst_len_bw = 5; + parameter c_fifo_depth_bw = 6; + parameter c_bufsize = 28; + parameter c_mi_data_addr = 28; + parameter c_dma_y_fifo_depth = 10'd16; + parameter c_dma_cb_fifo_depth = 10'd16; + parameter c_dma_cr_fifo_depth = 10'd16;
diff --git a/ispyocto/rtl/inc/vsisp_ram_sizes.vh b/ispyocto/rtl/inc/vsisp_ram_sizes.vh new file mode 100644 index 0000000..78d1f99 --- /dev/null +++ b/ispyocto/rtl/inc/vsisp_ram_sizes.vh
@@ -0,0 +1,63 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +parameter c_ispfifo_aw = 7; +parameter c_ispfifo_dw = 2*(c_dw_si + 2); +parameter c_lsc_ram_ad_bw = 9; +parameter c_lsc_ram_d_bw = 24; +parameter c_dw_dpmem = 9*c_dw_si; +parameter c_aw_dpmem = 12; +parameter c_h_aw_bpt = 13; +parameter c_v_aw_bpt = 12; +parameter c_dw_bpt = c_h_aw_bpt + + c_v_aw_bpt; +parameter c_aw_bpt = 11; +parameter c_dw_dpf_mem = 8*c_dw_si; +parameter c_aw_dpf_mem = 12; +parameter c_dw_dem_mem = 14*c_dw_si; +parameter c_aw_dem_mem = 9; +parameter c_aw_vsm_h = 10; +parameter c_aw_vsm_v = 10; +parameter c_r2b_ram0_aw = 3'd5; +parameter c_r2b_ram1_aw = 3'd4; +parameter c_vlc_ram_aw = 3'd5; +parameter c_vlc_fifo0_dw = 7'd35; +parameter c_vlc_fifo1_dw = 7'd37; +parameter c_vlc_ram0_dw = (c_vlc_fifo0_dw)*2; +parameter c_vlc_ram1_dw = (c_vlc_fifo1_dw)*2; +parameter c_mipi_data_aw = 11; +parameter c_mipi_data_dw = 32; +parameter c_smia_data_aw = 8; +parameter c_smia_data_dw = 32; +parameter c_aw_ie = 12; +parameter c_ie_ram_size = 2560; +parameter c_aw_mrsz = 9; +parameter c_aw_srsz = 9; +parameter c_srsz_ram_size = 1024; +parameter c_aw_cnr = 12; +parameter c_cnr_ram_g_dw = 2*c_dw_si; +parameter c_cnr_ram_c12_dw = 4*(c_dw_si+1); +parameter c_aw_wdrt = 13; +parameter c_mi_mp_y_aw = 7; +parameter c_mi_mp_c_aw = 6; +parameter c_mi_bp_aw = 7;
diff --git a/ispyocto/rtl/inc/vsisp_self_resize.vh b/ispyocto/rtl/inc/vsisp_self_resize.vh new file mode 100644 index 0000000..72145c8 --- /dev/null +++ b/ispyocto/rtl/inc/vsisp_self_resize.vh
@@ -0,0 +1,67 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + + parameter c_max_hsize = 8192; + parameter c_ram_width = 12; + parameter size_width =13; + parameter resize_data_width =8; + parameter c_scale_h = 16; + parameter c_scale_v = 16; + parameter c_phase_h = 16; + parameter c_phase_v = 16; + parameter c_scale_lut_addr = 6; + parameter c_scale_lut = 6; + parameter c_lbuf_h = resize_data_width+7; + parameter c_lbuf_v = resize_data_width+7; + parameter c_number_of_lut = 64; + parameter c_resize_ctrl = 5'b00000; + parameter c_resize_scale_hy = 5'b00001; + parameter c_resize_scale_hcb = 5'b00010; + parameter c_resize_scale_hcr = 5'b00011; + parameter c_resize_scale_vy = 5'b00100; + parameter c_resize_scale_vc = 5'b00101; + parameter c_resize_phase_hy = 5'b00110; + parameter c_resize_phase_hc = 5'b00111; + parameter c_resize_phase_vy = 5'b01000; + parameter c_resize_phase_vc = 5'b01001; + parameter c_resize_scale_lut_addr = 5'b01010; + parameter c_resize_scale_lut = 5'b01011; + parameter c_resize_ctrl_sdw = 5'b01100; + parameter c_resize_scale_hy_sdw = 5'b01101; + parameter c_resize_scale_hcb_sdw = 5'b01110; + parameter c_resize_scale_hcr_sdw = 5'b01111; + parameter c_resize_scale_vy_sdw = 5'b10000; + parameter c_resize_scale_vc_sdw = 5'b10001; + parameter c_resize_phase_hy_sdw = 5'b10010; + parameter c_resize_phase_hc_sdw = 5'b10011; + parameter c_resize_phase_vy_sdw = 5'b10100; + parameter c_resize_phase_vc_sdw = 5'b10101; + parameter c_resize_crop_x_direction = 5'b10110; + parameter c_resize_crop_y_direction = 5'b10111; + parameter c_resize_crop_x_direction_sdw = 5'b11000; + parameter c_resize_crop_y_direction_sdw = 5'b11001; + parameter c_resize_frame_rate = 5'b11010; + parameter format_conv_ctrl = 5'b11011; + parameter c_err_flags0 = 5'b11100; + parameter c_err_flags1 = 5'b11101; + parameter c_err_flags2 = 5'b11110;
diff --git a/ispyocto/rtl/isp8000_filelist.txt b/ispyocto/rtl/isp8000_filelist.txt new file mode 100644 index 0000000..857da62 --- /dev/null +++ b/ispyocto/rtl/isp8000_filelist.txt
@@ -0,0 +1,140 @@ ++incdir+./inc +isp8000/vsisp_add_h_end.v +isp8000/vsisp_ahb2pvci.v +isp8000/vsisp_AQSync.v +isp8000/vsisp_bvci2axi_wr.v +isp8000/vsisp_CLOCKGATER.v +isp8000/vsisp_conv_422to444.v +isp8000/vsisp_conv_dpsbe.v +isp8000/vsisp_conv_dpsfe.v +isp8000/vsisp_conv_dpsfifo.v +isp8000/vsisp_conv_gen_streaming_interface.v +isp8000/vsisp_conv.v +isp8000/vsisp_conv_yuv2rgb.v +isp8000/vsisp_dreg_en_1d.v +isp8000/vsisp_dreg_en_2d.v +isp8000/vsisp_fifo4fe.v +isp8000/vsisp_fifo.v +isp8000/vsisp_GC_CG_MOD.v +isp8000/vsisp_gc_den_reg.v +isp8000/vsisp_gc_dr_reg.v +isp8000/vsisp_isp_422_conv.v +isp8000/vsisp_isp_awb_acc.v +isp8000/vsisp_isp_awb_div.v +isp8000/vsisp_isp_awb_meas.v +isp8000/vsisp_isp_awb_th.v +isp8000/vsisp_isp_awb_wnd.v +isp8000/vsisp_isp_bls_regs.v +isp8000/vsisp_isp_bls_subtr.v +isp8000/vsisp_isp_bls_v2.v +isp8000/vsisp_isp_cac_ctrl.v +isp8000/vsisp_isp_cac_delay.v +isp8000/vsisp_isp_cac_hor_buf.v +isp8000/vsisp_isp_cac_hor.v +isp8000/vsisp_isp_cac_ver.v +isp8000/vsisp_isp_cross_talk.v +isp8000/vsisp_isp_crt_tri_mul_add.v +isp8000/vsisp_isp_csm_fix.v +isp8000/vsisp_isp_csm_tri_mul_add.v +isp8000/vsisp_isp_csm.v +isp8000/vsisp_isp_demosaic_3x2.v +isp8000/vsisp_isp_demosaic_3x3_crcb.v +isp8000/vsisp_isp_demosaic5x.v +isp8000/vsisp_isp_demosaic_buf_5lines.v +isp8000/vsisp_isp_demosaic_dpsbe.v +isp8000/vsisp_isp_digi_gain.v +isp8000/vsisp_isp_dpsfe.v +isp8000/vsisp_isp_exp_ctrl.v +isp8000/vsisp_isp_exp_regs.v +isp8000/vsisp_isp_exp.v +isp8000/vsisp_isp_filt_chr_buf.v +isp8000/vsisp_isp_filt_chr_core.v +isp8000/vsisp_isp_filt_ctrl.v +isp8000/vsisp_isp_filt_hp_core.v +isp8000/vsisp_isp_filt_lp_core.v +isp8000/vsisp_isp_filt_out_mux.v +isp8000/vsisp_isp_filt_regs.v +isp8000/vsisp_isp_filt_txtdet.v +isp8000/vsisp_isp_filt.v +isp8000/vsisp_isp_gamma_channel_fix.v +isp8000/vsisp_isp_gamma_out.v +isp8000/vsisp_isp_inform.v +isp8000/vsisp_isp_irq_handler.v +isp8000/vsisp_isp_isp_fifo_wrapper.v +isp8000/vsisp_isp_isp_ram_wrapper.v +isp8000/vsisp_isp_line_mem_if.v +isp8000/vsisp_isp_miv1_mp_sramy_wrapper.v +isp8000/vsisp_isp_outform.v +isp8000/vsisp_isp_pseudo_random_gen.v +isp8000/vsisp_isp_regs.v +isp8000/vsisp_isp_rgb_yuv_sel.v +isp8000/vsisp_isp_srsz_c_wrapper.v +isp8000/vsisp_isp_srsz_y_wrapper.v +isp8000/vsisp_isp_tpg_cfg.v +isp8000/vsisp_isp.v +isp8000/vsisp_m4_clock_gating.v +isp8000/vsisp_marvin_ctrl_pvcidis.v +isp8000/vsisp_marvin_ctrl_pvci.v +isp8000/vsisp_marvin_ctrl_reset_gen.v +isp8000/vsisp_marvin_ctrl.v +isp8000/vsisp_marvin_dpsfe.v +isp8000/vsisp_marvin_dpsfifo.v +isp8000/vsisp_marvin_irq_handler.v +isp8000/vsisp_marvin_mi_2to3.v +isp8000/vsisp_marvin_mi_bp.v +isp8000/vsisp_marvin_mi_dpsbe.v +isp8000/vsisp_marvin_mi_fifo_bp.v +isp8000/vsisp_marvin_mi_fifo.v +isp8000/vsisp_marvin_mi_handshake.v +isp8000/vsisp_marvin_mi_in_distrib.v +isp8000/vsisp_marvin_mi_in.v +isp8000/vsisp_marvin_mi_out_addrgen_mp.v +isp8000/vsisp_marvin_mi_out_addrgen_sp.v +isp8000/vsisp_marvin_mi_out_arbit_mp.v +isp8000/vsisp_marvin_mi_out_arbit_sp.v +isp8000/vsisp_marvin_mi_out_bp.v +isp8000/vsisp_marvin_mi_out_ctrl_mp.v +isp8000/vsisp_marvin_mi_out_ctrl_sp.v +isp8000/vsisp_marvin_mi_out_mp.v +isp8000/vsisp_marvin_mi_out_sp.v +isp8000/vsisp_marvin_mi_out_updlogic_mp.v +isp8000/vsisp_marvin_mi_out_updlogic_sp.v +isp8000/vsisp_marvin_mi_out.v +isp8000/vsisp_marvin_mi_regs.v +isp8000/vsisp_marvin_mi_swap.v +isp8000/vsisp_marvin_mi.v +isp8000/vsisp_marvin_pvci_reg_stage.v +isp8000/vsisp_marvin_top_a.v +isp8000/VSISP_MARVIN_TOP_X.v +isp8000/vsisp_mi_bayer_split.v +isp8000/vsisp_mi_dp_outstage.v +isp8000/vsisp_mi_dp_raw.v +isp8000/vsisp_mi_fifo_core.v +isp8000/vsisp_mi_fifo_ram.v +isp8000/vsisp_mi_jpeg_ctrl.v +isp8000/vsisp_pvci_mux.v +isp8000/vsisp_pvci_sync.v +isp8000/vsisp_resize_conv_ctrl.v +isp8000/vsisp_resize_conv.v +isp8000/vsisp_resize_to_conv_2to3.v +isp8000/vsisp_self_hor_c_scale.v +isp8000/vsisp_self_hor_mult.v +isp8000/vsisp_self_hor_scale.v +isp8000/vsisp_self_resize_c_scale.v +isp8000/vsisp_self_resize_scale.v +isp8000/vsisp_self_resize.v +isp8000/vsisp_self_rsz_dpsbe.v +isp8000/vsisp_self_vert_mult.v +isp8000/vsisp_self_vert_scale.v +isp8000/vsisp_sensor_fifo.v +isp8000/vsisp_sync_fifo_core.v +isp8000/vsisp_sync_fifo_outp.v +isp8000/vsisp_sync_fifo_reset_gen_rd.v +isp8000/vsisp_sync_fifo_reset_gen_wr.v +isp8000/vsisp_vs_marvin_ramshell.v +isp8000/vsisp_yc_split.v +rams/vsisp_RAM1P128W28B_SS.v +rams/vsisp_RAM1P320W168B_SS.v +rams/vsisp_RAM1P320W32B_SS.v +rams/vsisp_RAM1P80W66B_SS.v +undef/vsisp_vsi_undef.v
diff --git a/ispyocto/rtl/ispyocto/VSISP_MARVIN_TOP_X.v b/ispyocto/rtl/ispyocto/VSISP_MARVIN_TOP_X.v new file mode 100644 index 0000000..2340e6f --- /dev/null +++ b/ispyocto/rtl/ispyocto/VSISP_MARVIN_TOP_X.v
@@ -0,0 +1,448 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module VSISP_MARVIN_TOP_X + ( + clk, + reset_n, + sclk, + s_hclk, + m_hclk, + axi_m1_marvin_awvalid, + axi_m1_marvin_awaddr, + axi_m1_marvin_awlen, + axi_m1_marvin_awsize, + axi_m1_marvin_awburst, + axi_m1_marvin_awlock, + axi_m1_marvin_awcache, + axi_m1_marvin_awprot, + axi_m1_marvin_awid, + axi_m1_marvin_awready, + axi_m1_marvin_wvalid, + axi_m1_marvin_wlast, + axi_m1_marvin_wdata, + axi_m1_marvin_wstrb, + axi_m1_marvin_wid, + axi_m1_marvin_wready, + axi_m1_marvin_bvalid, + axi_m1_marvin_bresp, + axi_m1_marvin_bid, + axi_m1_marvin_bready, + axi_m2_marvin_awvalid, + axi_m2_marvin_awaddr, + axi_m2_marvin_awlen, + axi_m2_marvin_awsize, + axi_m2_marvin_awburst, + axi_m2_marvin_awlock, + axi_m2_marvin_awcache, + axi_m2_marvin_awprot, + axi_m2_marvin_awid, + axi_m2_marvin_awready, + axi_m2_marvin_wvalid, + axi_m2_marvin_wlast, + axi_m2_marvin_wdata, + axi_m2_marvin_wstrb, + axi_m2_marvin_wid, + axi_m2_marvin_wready, + axi_m2_marvin_bvalid, + axi_m2_marvin_bresp, + axi_m2_marvin_bid, + axi_m2_marvin_bready, + hsel_s, + haddr_s, + htrans_s, + hwrite_s, + hwdata_s, + hrdata_s, + hresp_s, + hready_s, + s_data, + s_hsync, + s_vsync, + s_valid, + disable_isp, + scan_mode, + mi_irq, + isp_irq, + out_y_r_frame_start, + out_y_r_frame_end, + out_y_r_line_start, + out_y_r_line_end, + out_cb_g_frame_start, + out_cb_g_frame_end, + out_cb_g_line_start, + out_cb_g_line_end, + out_cr_b_frame_start, + out_cr_b_frame_end, + out_cr_b_line_start, + out_cr_b_line_end, + out_y_r_ack_stream, + out_cb_g_ack_stream, + out_cr_b_ack_stream, + out_y_r_val_stream, + out_y_r_data_stream, + out_cb_g_val_stream, + out_cb_g_data_stream, + out_cr_b_val_stream, + out_cr_b_data_stream + ); +`include "vsisp_marvin_id.vh" +`include "vsisp_isp.vh" +`include "vsisp_ram_sizes.vh" + input clk; + input reset_n; + input sclk; + input s_hclk; + input m_hclk; + output axi_m1_marvin_awvalid; + output [31:3] axi_m1_marvin_awaddr; + output [3:0] axi_m1_marvin_awlen; + output [2:0] axi_m1_marvin_awsize; + output [1:0] axi_m1_marvin_awburst; + output [1:0] axi_m1_marvin_awlock; + output [3:0] axi_m1_marvin_awcache; + output [2:0] axi_m1_marvin_awprot; + output [3:0] axi_m1_marvin_awid; + input axi_m1_marvin_awready; + output axi_m1_marvin_wvalid; + output axi_m1_marvin_wlast; + output [63:0] axi_m1_marvin_wdata; + output [7:0] axi_m1_marvin_wstrb; + output [3:0] axi_m1_marvin_wid; + input axi_m1_marvin_wready; + input axi_m1_marvin_bvalid; + input [1:0] axi_m1_marvin_bresp; + input [3:0] axi_m1_marvin_bid; + output axi_m1_marvin_bready; + output axi_m2_marvin_awvalid; + output [31:3] axi_m2_marvin_awaddr; + output [3:0] axi_m2_marvin_awlen; + output [2:0] axi_m2_marvin_awsize; + output [1:0] axi_m2_marvin_awburst; + output [1:0] axi_m2_marvin_awlock; + output [3:0] axi_m2_marvin_awcache; + output [2:0] axi_m2_marvin_awprot; + output [3:0] axi_m2_marvin_awid; + input axi_m2_marvin_awready; + output axi_m2_marvin_wvalid; + output axi_m2_marvin_wlast; + output [63:0] axi_m2_marvin_wdata; + output [7:0] axi_m2_marvin_wstrb; + output [3:0] axi_m2_marvin_wid; + input axi_m2_marvin_wready; + input axi_m2_marvin_bvalid; + input [1:0] axi_m2_marvin_bresp; + input [3:0] axi_m2_marvin_bid; + output axi_m2_marvin_bready; + wire axi_rd_marvin_arvalid; + wire [31:3] axi_rd_marvin_araddr; + wire [3:0] axi_rd_marvin_arlen; + wire [2:0] axi_rd_marvin_arsize; + wire [1:0] axi_rd_marvin_arburst; + wire [1:0] axi_rd_marvin_arlock; + wire [3:0] axi_rd_marvin_arcache; + wire [2:0] axi_rd_marvin_arprot; + wire [3:0] axi_rd_marvin_arid; + wire axi_rd_marvin_arready; + wire axi_rd_marvin_rvalid; + wire axi_rd_marvin_rlast; + wire [63:0] axi_rd_marvin_rdata; + wire [1:0] axi_rd_marvin_rresp; + wire [3:0] axi_rd_marvin_rid; + wire axi_rd_marvin_rready; + input hsel_s; + input [31:0] haddr_s; + input [1:0] htrans_s; + input hwrite_s; + input [31:0] hwdata_s; + output [31:0] hrdata_s; + output [1:0] hresp_s; + output hready_s; + input [11:0] s_data; + input s_hsync; + input s_vsync; + input s_valid; + input disable_isp; + input scan_mode; + output mi_irq; + output isp_irq; + output out_y_r_frame_start; + output out_y_r_frame_end; + output out_y_r_line_start; + output out_y_r_line_end; + output out_cb_g_frame_start; + output out_cb_g_frame_end; + output out_cb_g_line_start; + output out_cb_g_line_end; + output out_cr_b_frame_start; + output out_cr_b_frame_end; + output out_cr_b_line_start; + output out_cr_b_line_end; + output out_y_r_val_stream; + output wire [ 7: 0] out_y_r_data_stream; + output out_cb_g_val_stream; + output wire [ 7: 0] out_cb_g_data_stream; + output out_cr_b_val_stream; + output wire [ 7: 0] out_cr_b_data_stream; + input out_y_r_ack_stream; + input out_cb_g_ack_stream; + input out_cr_b_ack_stream; + wire isp_fifo_ram_clk; + wire isp_fifo_cs_n; + wire isp_fifo_wr_n; + wire [c_ispfifo_aw-1:0] isp_fifo_addr; + wire [c_ispfifo_dw-1:0] isp_fifo_wdata; + wire [c_ispfifo_dw-1:0] isp_fifo_rdata; + wire isp_rgb_ram_clk; + wire [c_aw_dem_mem-1:0] isp_ispram_addr; + wire [c_dw_dem_mem-1:0] isp_ispram_wdata; + wire [c_dw_dem_mem-1:0] isp_ispram_rdata; + wire isp_ispram_wr_n; + wire isp_ispram_cs_n; + wire rszm_mram_clk; + wire rszm_mramy_wr_n; + wire rszm_mramy_cs_n; + wire [c_aw_mrsz-1:0] rszm_mramy_addr; + wire [31:0] rszm_mramy_wdata; + wire [31:0] rszm_mramy_rdata; + wire rszm_mramc_wr_n; + wire rszm_mramc_cs_n; + wire [c_aw_mrsz-1:0] rszm_mramc_addr; + wire [31:0] rszm_mramc_wdata; + wire [31:0] rszm_mramc_rdata; + wire rszs_sram_clk; + wire rszs_sramy_wr_n; + wire rszs_sramy_cs_n; + wire [c_aw_srsz-1:0] rszs_sramy_addr; + wire [31:0] rszs_sramy_wdata; + wire [31:0] rszs_sramy_rdata; + wire rszs_sramc_wr_n; + wire rszs_sramc_cs_n; + wire [c_aw_srsz-1:0] rszs_sramc_addr; + wire [31:0] rszs_sramc_wdata; + wire [31:0] rszs_sramc_rdata; + wire [65:0] mp_y_fifo_sram_wdata ; + wire [65:0] mp_y_fifo_sram_rdata ; + wire [ c_mi_mp_y_aw -1:0] mp_y_fifo_sram_addr ; + wire mp_y_fifo_sram_cs_n ; + wire mp_y_fifo_sram_we_n ; + wire [65:0] mp_cb_fifo_sram_wdata ; + wire [65:0] mp_cb_fifo_sram_rdata ; + wire [ c_mi_mp_c_aw -1:0] mp_cb_fifo_sram_addr ; + wire mp_cb_fifo_sram_cs_n ; + wire mp_cb_fifo_sram_we_n ; + wire [65:0] mp_cr_fifo_sram_wdata ; + wire [65:0] mp_cr_fifo_sram_rdata ; + wire [ c_mi_mp_c_aw- 1:0] mp_cr_fifo_sram_addr ; + wire mp_cr_fifo_sram_cs_n ; + wire mp_cr_fifo_sram_we_n ; + vsisp_marvin_top_a u_marvin_top_a_0 ( + .clk (clk ), + .reset_n (reset_n ), + .sclk (sclk ), + .s_hclk (s_hclk ), + .m_hclk (m_hclk ), + .scan_mode (scan_mode ), + .regs_disable_isp_clk (regs_disable_isp_clk), + .axi_m1_marvin_awvalid (axi_m1_marvin_awvalid), + .axi_m1_marvin_awaddr (axi_m1_marvin_awaddr ), + .axi_m1_marvin_awlen (axi_m1_marvin_awlen ), + .axi_m1_marvin_awsize (axi_m1_marvin_awsize ), + .axi_m1_marvin_awburst (axi_m1_marvin_awburst), + .axi_m1_marvin_awlock (axi_m1_marvin_awlock ), + .axi_m1_marvin_awcache (axi_m1_marvin_awcache), + .axi_m1_marvin_awprot (axi_m1_marvin_awprot ), + .axi_m1_marvin_awid (axi_m1_marvin_awid ), + .axi_m1_marvin_awready (axi_m1_marvin_awready), + .axi_m1_marvin_wvalid (axi_m1_marvin_wvalid), + .axi_m1_marvin_wlast (axi_m1_marvin_wlast ), + .axi_m1_marvin_wdata (axi_m1_marvin_wdata ), + .axi_m1_marvin_wstrb (axi_m1_marvin_wstrb ), + .axi_m1_marvin_wid (axi_m1_marvin_wid ), + .axi_m1_marvin_wready (axi_m1_marvin_wready), + .axi_m1_marvin_bvalid (axi_m1_marvin_bvalid), + .axi_m1_marvin_bresp (axi_m1_marvin_bresp ), + .axi_m1_marvin_bid (axi_m1_marvin_bid ), + .axi_m1_marvin_bready (axi_m1_marvin_bready), + .axi_m2_marvin_awvalid (axi_m2_marvin_awvalid), + .axi_m2_marvin_awaddr (axi_m2_marvin_awaddr ), + .axi_m2_marvin_awlen (axi_m2_marvin_awlen ), + .axi_m2_marvin_awsize (axi_m2_marvin_awsize ), + .axi_m2_marvin_awburst (axi_m2_marvin_awburst), + .axi_m2_marvin_awlock (axi_m2_marvin_awlock ), + .axi_m2_marvin_awcache (axi_m2_marvin_awcache), + .axi_m2_marvin_awprot (axi_m2_marvin_awprot ), + .axi_m2_marvin_awid (axi_m2_marvin_awid ), + .axi_m2_marvin_awready (axi_m2_marvin_awready), + .axi_m2_marvin_wvalid (axi_m2_marvin_wvalid), + .axi_m2_marvin_wlast (axi_m2_marvin_wlast ), + .axi_m2_marvin_wdata (axi_m2_marvin_wdata ), + .axi_m2_marvin_wstrb (axi_m2_marvin_wstrb ), + .axi_m2_marvin_wid (axi_m2_marvin_wid ), + .axi_m2_marvin_wready (axi_m2_marvin_wready), + .axi_m2_marvin_bvalid (axi_m2_marvin_bvalid), + .axi_m2_marvin_bresp (axi_m2_marvin_bresp ), + .axi_m2_marvin_bid (axi_m2_marvin_bid ), + .axi_m2_marvin_bready (axi_m2_marvin_bready), + .hsel_s (hsel_s ), + .haddr_s (haddr_s ), + .htrans_s (htrans_s ), + .hwrite_s (hwrite_s ), + .hwdata_s (hwdata_s ), + .hrdata_s (hrdata_s ), + .hresp_s (hresp_s ), + .hready_s (hready_s ), + .s_data (s_data), + .s_hsync (s_hsync), + .s_vsync (s_vsync), + .s_valid (s_valid), + .disable_isp (disable_isp ), + .mi_irq (mi_irq), + .isp_irq (isp_irq), + .isp_fifo_ram_clk (isp_fifo_ram_clk), + .isp_fifo_cs_n (isp_fifo_cs_n), + .isp_fifo_wr_n (isp_fifo_wr_n), + .isp_fifo_addr (isp_fifo_addr), + .isp_fifo_wdata (isp_fifo_wdata), + .isp_fifo_rdata (isp_fifo_rdata), + .isp_rgb_ram_clk (isp_rgb_ram_clk), + .isp_ispram_addr (isp_ispram_addr), + .isp_ispram_wdata (isp_ispram_wdata), + .isp_ispram_rdata (isp_ispram_rdata), + .isp_ispram_wr_n (isp_ispram_wr_n), + .isp_ispram_cs_n (isp_ispram_cs_n), + .rszm_mram_clk (rszm_mram_clk), + .rszm_mramy_wr_n (rszm_mramy_wr_n), + .rszm_mramy_cs_n (rszm_mramy_cs_n), + .rszm_mramy_addr (rszm_mramy_addr), + .rszm_mramy_wdata (rszm_mramy_wdata), + .rszm_mramy_rdata (rszm_mramy_rdata), + .rszm_mramc_wr_n (rszm_mramc_wr_n), + .rszm_mramc_cs_n (rszm_mramc_cs_n), + .rszm_mramc_addr (rszm_mramc_addr), + .rszm_mramc_wdata (rszm_mramc_wdata), + .rszm_mramc_rdata (rszm_mramc_rdata), + .mp_y_fifo_sram_wdata (mp_y_fifo_sram_wdata ), + .mp_y_fifo_sram_rdata (mp_y_fifo_sram_rdata ), + .mp_y_fifo_sram_addr (mp_y_fifo_sram_addr ), + .mp_y_fifo_sram_cs_n (mp_y_fifo_sram_cs_n ), + .mp_y_fifo_sram_we_n (mp_y_fifo_sram_we_n ), + .mp_cb_fifo_sram_wdata (mp_cb_fifo_sram_wdata ), + .mp_cb_fifo_sram_rdata (mp_cb_fifo_sram_rdata ), + .mp_cb_fifo_sram_addr (mp_cb_fifo_sram_addr ), + .mp_cb_fifo_sram_cs_n (mp_cb_fifo_sram_cs_n ), + .mp_cb_fifo_sram_we_n (mp_cb_fifo_sram_we_n ), + .mp_cr_fifo_sram_wdata (mp_cr_fifo_sram_wdata ), + .mp_cr_fifo_sram_rdata (mp_cr_fifo_sram_rdata ), + .mp_cr_fifo_sram_addr (mp_cr_fifo_sram_addr ), + .mp_cr_fifo_sram_cs_n (mp_cr_fifo_sram_cs_n ), + .mp_cr_fifo_sram_we_n (mp_cr_fifo_sram_we_n ), + .rszs_sram_clk ( rszs_sram_clk ) , + .rszs_sramy_wr_n ( rszs_sramy_wr_n ) , + .rszs_sramy_cs_n ( rszs_sramy_cs_n ) , + .rszs_sramy_addr ( rszs_sramy_addr ) , + .rszs_sramy_wdata ( rszs_sramy_wdata ) , + .rszs_sramy_rdata ( rszs_sramy_rdata ) , + .rszs_sramc_wr_n ( rszs_sramc_wr_n ) , + .rszs_sramc_cs_n ( rszs_sramc_cs_n ) , + .rszs_sramc_addr ( rszs_sramc_addr ) , + .rszs_sramc_wdata ( rszs_sramc_wdata ) , + .rszs_sramc_rdata ( rszs_sramc_rdata ) , + .out_y_r_val_stream (out_y_r_val_stream), + .out_y_r_data_stream (out_y_r_data_stream), + .out_cb_g_val_stream (out_cb_g_val_stream), + .out_cb_g_data_stream (out_cb_g_data_stream), + .out_cr_b_val_stream (out_cr_b_val_stream), + .out_cr_b_data_stream (out_cr_b_data_stream), + .out_y_r_ack_stream(out_y_r_ack_stream), + .out_cb_g_ack_stream(out_cb_g_ack_stream), + .out_cr_b_ack_stream(out_cr_b_ack_stream), + .out_y_r_frame_start (out_y_r_frame_start), + .out_y_r_frame_end (out_y_r_frame_end), + .out_y_r_line_start (out_y_r_line_start), + .out_y_r_line_end (out_y_r_line_end), + .out_cb_g_frame_start (out_cb_g_frame_start), + .out_cb_g_frame_end (out_cb_g_frame_end), + .out_cb_g_line_start (out_cb_g_line_start), + .out_cb_g_line_end (out_cb_g_line_end), + .out_cr_b_frame_start (out_cr_b_frame_start), + .out_cr_b_frame_end (out_cr_b_frame_end), + .out_cr_b_line_start (out_cr_b_line_start), + .out_cr_b_line_end (out_cr_b_line_end) + ); + vsisp_vs_marvin_ramshell u_marvin_ramshell + ( + .reset_ (reset_n), + .scan_mode (scan_mode ), + .regs_disable_isp_clk (regs_disable_isp_clk), + .isp_fifo_ram_clk (isp_fifo_ram_clk), + .isp_fifo_cs_n (isp_fifo_cs_n), + .isp_fifo_wr_n (isp_fifo_wr_n), + .isp_fifo_addr (isp_fifo_addr), + .isp_fifo_wdata (isp_fifo_wdata), + .isp_fifo_rdata (isp_fifo_rdata), + .isp_rgb_ram_clk (isp_rgb_ram_clk), + .isp_ispram_addr (isp_ispram_addr), + .isp_ispram_wdata (isp_ispram_wdata), + .isp_ispram_rdata (isp_ispram_rdata), + .isp_ispram_wr_n (isp_ispram_wr_n), + .isp_ispram_cs_n (isp_ispram_cs_n), + .rszm_mram_clk (rszm_mram_clk), + .rszm_mramy_wr_n (rszm_mramy_wr_n), + .rszm_mramy_cs_n (rszm_mramy_cs_n), + .rszm_mramy_addr (rszm_mramy_addr), + .rszm_mramy_wdata (rszm_mramy_wdata), + .rszm_mramy_rdata (rszm_mramy_rdata), + .rszm_mramc_wr_n (rszm_mramc_wr_n), + .rszm_mramc_cs_n (rszm_mramc_cs_n), + .rszm_mramc_addr (rszm_mramc_addr), + .rszm_mramc_wdata (rszm_mramc_wdata), + .rszm_mramc_rdata (rszm_mramc_rdata), + .rszs_sram_clk (rszs_sram_clk), + .rszs_sramy_wr_n (rszs_sramy_wr_n), + .rszs_sramy_cs_n (rszs_sramy_cs_n), + .rszs_sramy_addr (rszs_sramy_addr), + .rszs_sramy_wdata (rszs_sramy_wdata), + .rszs_sramy_rdata (rszs_sramy_rdata), + .rszs_sramc_wr_n (rszs_sramc_wr_n), + .rszs_sramc_cs_n (rszs_sramc_cs_n), + .rszs_sramc_addr (rszs_sramc_addr), + .rszs_sramc_wdata (rszs_sramc_wdata), + .rszs_sramc_rdata (rszs_sramc_rdata), + .mp_y_fifo_sram_wdata (mp_y_fifo_sram_wdata ), + .mp_y_fifo_sram_rdata (mp_y_fifo_sram_rdata ), + .mp_y_fifo_sram_addr (mp_y_fifo_sram_addr ), + .mp_y_fifo_sram_cs_n (mp_y_fifo_sram_cs_n ), + .mp_y_fifo_sram_we_n (mp_y_fifo_sram_we_n ), + .mp_cb_fifo_sram_wdata (mp_cb_fifo_sram_wdata ), + .mp_cb_fifo_sram_rdata (mp_cb_fifo_sram_rdata ), + .mp_cb_fifo_sram_addr (mp_cb_fifo_sram_addr ), + .mp_cb_fifo_sram_cs_n (mp_cb_fifo_sram_cs_n ), + .mp_cb_fifo_sram_we_n (mp_cb_fifo_sram_we_n ), + .mp_cr_fifo_sram_wdata (mp_cr_fifo_sram_wdata ), + .mp_cr_fifo_sram_rdata (mp_cr_fifo_sram_rdata ), + .mp_cr_fifo_sram_addr (mp_cr_fifo_sram_addr ), + .mp_cr_fifo_sram_cs_n (mp_cr_fifo_sram_cs_n ), + .mp_cr_fifo_sram_we_n (mp_cr_fifo_sram_we_n ) + ); +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_AQSync.v b/ispyocto/rtl/ispyocto/vsisp_AQSync.v new file mode 100644 index 0000000..4d69f6e --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_AQSync.v
@@ -0,0 +1,35 @@ +//**************************************************************************** +// +// Copyright 2023 Vivante Corp. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_AQSync( + bitSync, + clk, bitIn, reset_ + ); +parameter RESET_STATE=0; + input clk; + input reset_; + input bitIn; + output bitSync; + wire viv_s0; + wire bitSync; + vsisp_gc_dr_reg #(1,RESET_STATE) metaReg (.out(viv_s0), .clk(clk), .reset_(reset_), .in(bitIn)); + vsisp_gc_dr_reg #(1,RESET_STATE) AQSyncReg (.out(bitSync), .clk(clk), .reset_(reset_), .in(viv_s0)); +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_CLOCKGATER.v b/ispyocto/rtl/ispyocto/vsisp_CLOCKGATER.v new file mode 100644 index 0000000..1754b40 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_CLOCKGATER.v
@@ -0,0 +1,37 @@ +//**************************************************************************** +// +// Copyright 2023 Vivante Corp. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_CLOCKGATER (enable, ck_in, ck_out, test); + input enable, ck_in, test; + output ck_out; + wire enable, ck_in, test; + wire ck_out; + reg enLatched; + always @(ck_in or enable) + if (!ck_in) + enLatched = enable; + wire enQual = enLatched | test; + `ifdef VIVANTE_NO_BLOCK_CG + assign ck_out = ck_in; + `else + assign ck_out = ck_in & enQual; + `endif +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_GC_CG_MOD.v b/ispyocto/rtl/ispyocto/vsisp_GC_CG_MOD.v new file mode 100644 index 0000000..35d41dc --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_GC_CG_MOD.v
@@ -0,0 +1,116 @@ +//**************************************************************************** +// +// Copyright 2023 Vivante Corp. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_GC_CG_MOD (enable, ck_in, ck_out, test); + input enable, ck_in, test; + output ck_out; + wire enable, ck_in, test; + wire ck_out; + `ifdef AQ_TSMC28HPM35_9T_LIB + CKLNQD4BWP35 GC_CG_INST( + .E (enable), + .CP (ck_in), + .TE (test), + .Q (ck_out)); + `else + `ifdef AQ_TSMC28HPM35_7T_LIB + CKLNQD4BWP7T35P140 GC_CG_INST( + .E (enable), + .CP (ck_in), + .TE (test), + .Q (ck_out)); + `else + `ifdef AQ_SEC14LPP_A9TR_C14_LIB + PREICG_X4N_A9PP84TR_C14 GC_CG_INST( + .E (enable), + .CK (ck_in), + .SE (test), + .ECK (ck_out)); + `else + `ifdef AQ_TSMC16FFC_7T5_SVT_LIB + PREICG_X4R_A7P5PP96PTS_C16 GC_CG_INST( + .E (enable), + .CK (ck_in), + .SE (test), + .ECK (ck_out)); + `else + `ifdef AQ_TSMC16FFC_9T_SVT_LIB + PREICG_X4R_A9PP96CTS_C16 GC_CG_INST( + .E (enable), + .CK (ck_in), + .SE (test), + .ECK (ck_out)); + `else + `ifdef AQ_TSMC12FFC_6T_SVT_LIB + CKLNQD4BWP6T16P96CPD GC_CG_INST( + .E (enable), + .CP (ck_in), + .TE (test), + .Q (ck_out)); + `else + `ifdef AQ_TSMC12FFC_7T5_SVT_LIB + CKLNQD4BWP7D5T16P96CPD GC_CG_INST( + .E (enable), + .CP (ck_in), + .TE (test), + .Q (ck_out)); + `else + `ifdef AQ_TSMC12FFC_9T_SVT_LIB + CKLNQD4BWP16P90CPD GC_CG_INST( + .E (enable), + .CP (ck_in), + .TE (test), + .Q (ck_out)); + `else + `ifdef AQ_TSMC7FF_6T_SVT_LIB + CKLNQD4BWP240H8P57PDSVT GC_CG_INST( + .E (enable), + .CP (ck_in), + .TE (test), + .Q (ck_out)); + `else + `ifdef AQ_TSMC7FF_7T5_SVT_LIB + CKLNQD4BWP300H8P64PDSVT GC_CG_INST( + .E (enable), + .CP (ck_in), + .TE (test), + .Q (ck_out)); + `else + `ifdef FPGA + assign ck_out = ck_in; + `else + vsisp_CLOCKGATER COMMON_GATER( + .enable(enable), + .ck_in(ck_in), + .ck_out(ck_out), + .test(test)); + `endif + `endif + `endif + `endif + `endif + `endif + `endif + `endif + `endif + `endif + `endif +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_add_h_end.v b/ispyocto/rtl/ispyocto/vsisp_add_h_end.v new file mode 100644 index 0000000..0d16c80 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_add_h_end.v
@@ -0,0 +1,100 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_add_h_end + ( + clk, + reset_n, + soft_rst, + in_c_data_i, + in_c_h_end_i, + in_c_v_end_i, + in_c_cfg_upd_i, + in_c_val_i, + in_c_ack_o, + out_c_data_o, + out_c_h_end_o, + out_c_v_end_o, + out_c_cfg_upd_o, + out_c_val_o, + out_c_ack_i + ); + parameter c_data_width = 8; + input clk; + input reset_n; + input soft_rst; + input [c_data_width-1:0] in_c_data_i; + input in_c_h_end_i; + input in_c_v_end_i; + input in_c_cfg_upd_i; + input in_c_val_i; + output in_c_ack_o; + output [c_data_width-1:0] out_c_data_o; + output out_c_h_end_o; + output out_c_v_end_o; + output out_c_cfg_upd_o; + output out_c_val_o; + input out_c_ack_i; + reg [10:0] vsisp_fifo[1:0]; + reg [1:0] viv_s0; + reg [1:0] viv_s1; + wire [10:0] viv_s2; + wire [10:0] viv_s3; + wire viv_s4; + wire viv_s5; + assign in_c_ack_o = ~viv_s4 | (out_c_val_o & out_c_ack_i); + assign out_c_data_o = viv_s2[7:0]; + assign out_c_h_end_o = viv_s2[8] || viv_s3[8]; + assign out_c_v_end_o = viv_s2[9]; + assign out_c_cfg_upd_o = viv_s2[10]; + assign out_c_val_o = viv_s4 || (~viv_s5 & viv_s2[8]); + assign viv_s2 = vsisp_fifo[viv_s1[0]]; + assign viv_s3 = vsisp_fifo[~viv_s1[0]]; + assign viv_s4 = (viv_s1[0] == viv_s0[0]) & (viv_s1[1] == ~viv_s0[1]); + assign viv_s5 = (viv_s1 == viv_s0); + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + viv_s0 <= 2'd0; + viv_s1 <= 2'd0; + vsisp_fifo[0] <= 11'd0; + vsisp_fifo[1] <= 11'd0; + end + else begin + if (soft_rst) begin + viv_s0 <= 2'd0; + viv_s1 <= 2'd0; + vsisp_fifo[0] <= 11'd0; + vsisp_fifo[1] <= 11'd0; + end else begin + if (in_c_val_i & in_c_ack_o) begin + vsisp_fifo[viv_s0[0]] <= {in_c_cfg_upd_i, in_c_v_end_i, + in_c_h_end_i, in_c_data_i}; + viv_s0 <= viv_s0 + 2'd1; + end + if (out_c_val_o & out_c_ack_i) begin + viv_s1 <= viv_s1 + 2'd1; + end + end + end + end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_ahb2pvci.v b/ispyocto/rtl/ispyocto/vsisp_ahb2pvci.v new file mode 100644 index 0000000..c06b985 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_ahb2pvci.v
@@ -0,0 +1,126 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_ahb2pvci + ( + hclk, + hreset_n, + pval, + paddress, + pwdata, + prd, + pack, + prdata, + hsel, + hrdata, + haddr, + hwdata, + hwrite, + hready_in, + htrans, + hresp, + hready + ); + parameter g_data_width = 32; + parameter g_addr_width = 32; + input hclk; + input hreset_n; + output pval; + wire pval; + output [g_addr_width - 1:0] paddress; + wire [g_addr_width - 1:0] paddress; + output [g_data_width - 1:0] pwdata; + wire [g_data_width - 1:0] pwdata; + output prd; + wire prd; + input pack; + input [g_data_width - 1:0] prdata; + input hsel; + output [g_data_width - 1:0] hrdata; + wire [g_data_width - 1:0] hrdata; + input [g_addr_width - 1:0] haddr; + input [g_data_width - 1:0] hwdata; + input hwrite; + input hready_in; + input [1:0] htrans; + output [1:0] hresp; + wire [1:0] hresp; + output hready; + wire hready; + reg [g_addr_width - 1:0] viv_s0; + reg viv_s1; + reg viv_s2; + wire viv_s3 ; + reg viv_s4; + reg [7:0] viv_s5; + assign viv_s3 = (((htrans[1]) == 1'b1) & (hsel == 1'b1) & + (hready_in == 1'b1) & + ((viv_s1 == 1'b0) | (pack == 1'b1)|viv_s4)); + assign paddress = viv_s0; + assign pval = viv_s1; + assign pwdata = hwdata; + assign hready = ~viv_s1 | pack |viv_s4 ; + assign prd = viv_s2; + assign hresp = 2'b00; + assign hrdata = prdata; + always @(negedge hreset_n or posedge hclk) + begin : sequ_proc + if (hreset_n == 1'b0) + begin + viv_s0 <= {g_addr_width{1'b0}} ; + viv_s1 <= 1'b0 ; + viv_s2 <= 1'b1 ; + end + else + begin + if ((viv_s1 == 1'b1) & (pack == 1'b1)) + begin + viv_s1 <= 1'b0 ; + end + else if (viv_s3) begin + viv_s1 <= 1'b1 ; + end + if (viv_s3) + begin + viv_s0 <= haddr ; + viv_s2 <= ~hwrite ; + end + end + end + always @(negedge hreset_n or posedge hclk)begin + if (hreset_n == 1'b0) + viv_s5 <= 8'b0; + else if(hready) + viv_s5 <= 8'b0; + else if((viv_s1 == 1'b1) &&(~pack)) + viv_s5 <= viv_s5 + 1'b1; + end + always @(negedge hreset_n or posedge hclk)begin + if (hreset_n == 1'b0) + viv_s4 <= 1'b0; + else if(~viv_s1 | pack) + viv_s4 <= 1'b0; + else if(viv_s1 &&(viv_s5==8'hff)) + viv_s4 <= 1'b1; + end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_bvci2axi_wr.v b/ispyocto/rtl/ispyocto/vsisp_bvci2axi_wr.v new file mode 100644 index 0000000..8c2d5ca --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_bvci2axi_wr.v
@@ -0,0 +1,229 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_bvci2axi_wr + ( + clk, + reset_n, + bvci_cmdval, + bvci_cmdack, + bvci_cmd, + bvci_plen, + bvci_contig, + bvci_wrap, + bvci_address, + bvci_be, + bvci_eop, + bvci_rspval, + bvci_rspack, + bvci_reop, + bvci_wdata, + axi_wr_marvin_awvalid, + axi_wr_marvin_awaddr, + axi_wr_marvin_awlen, + axi_wr_marvin_awsize, + axi_wr_marvin_awburst, + axi_wr_marvin_awlock, + axi_wr_marvin_awcache, + axi_wr_marvin_awprot, + axi_wr_marvin_awid, + axi_wr_marvin_awready, + axi_wr_marvin_wvalid, + axi_wr_marvin_wlast, + axi_wr_marvin_wdata, + axi_wr_marvin_wstrb, + axi_wr_marvin_wid, + axi_wr_marvin_wready, + axi_wr_marvin_bvalid, + axi_wr_marvin_bresp, + axi_wr_marvin_bid, + axi_wr_marvin_bready + ); + input clk; + input reset_n; + input bvci_cmdval; + output bvci_cmdack; + input [1:0] bvci_cmd; + input [8:0] bvci_plen; + input bvci_contig; + input bvci_wrap; + input [31:3] bvci_address; + input [7:0] bvci_be; + input bvci_eop; + output bvci_rspval; + input bvci_rspack; + output bvci_reop; + input [63:0] bvci_wdata; + output axi_wr_marvin_awvalid; + output [31:3] axi_wr_marvin_awaddr; + output [3:0] axi_wr_marvin_awlen; + output [2:0] axi_wr_marvin_awsize; + output [1:0] axi_wr_marvin_awburst; + output [1:0] axi_wr_marvin_awlock; + output [3:0] axi_wr_marvin_awcache; + output [2:0] axi_wr_marvin_awprot; + output [3:0] axi_wr_marvin_awid; + input axi_wr_marvin_awready; + output axi_wr_marvin_wvalid; + output axi_wr_marvin_wlast; + output [63:0] axi_wr_marvin_wdata; + output [7:0] axi_wr_marvin_wstrb; + output [3:0] axi_wr_marvin_wid; + input axi_wr_marvin_wready; + input axi_wr_marvin_bvalid; + input [1:0] axi_wr_marvin_bresp; + input [3:0] axi_wr_marvin_bid; + output axi_wr_marvin_bready; + reg [31:3] axi_wr_marvin_awaddr; + reg [63:0] axi_wr_marvin_wdata; + reg axi_wr_marvin_wvalid; + reg axi_wr_marvin_awvalid; + reg [3:0] axi_wr_marvin_awlen; + reg axi_wr_marvin_wlast; + reg [1:0] viv_s0; + parameter c_cmd_idle = 2'b00; + parameter c_cmd_set = 2'b01; + parameter c_cmd_hold = 2'b10; + parameter c_cmd_late = 2'b11; + reg bvci_rspval; + reg bvci_reop; + wire [4:0] viv_s1; + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + axi_wr_marvin_awvalid <= 1'b0; + viv_s0 <= c_cmd_idle; + end else begin + case (viv_s0) + c_cmd_set : begin + case ({axi_wr_marvin_awready, + axi_wr_marvin_wlast & axi_wr_marvin_wready}) + 2'b10: begin + axi_wr_marvin_awvalid <= 1'b0; + viv_s0 <= c_cmd_hold; + end + 2'b11: begin + axi_wr_marvin_awvalid <= 1'b0; + viv_s0 <= c_cmd_idle; + end + 2'b01: begin + axi_wr_marvin_awvalid <= 1'b1; + viv_s0 <= c_cmd_late; + end + default: begin + axi_wr_marvin_awvalid <= 1'b1; + viv_s0 <= c_cmd_set; + end + endcase + end + c_cmd_hold : begin + if (axi_wr_marvin_wlast & axi_wr_marvin_wready) begin + axi_wr_marvin_awvalid <= 1'b0; + viv_s0 <= c_cmd_idle; + end else begin + axi_wr_marvin_awvalid <= 1'b0; + viv_s0 <= c_cmd_hold; + end + end + c_cmd_late : begin + if (axi_wr_marvin_awready) begin + axi_wr_marvin_awvalid <= 1'b0; + viv_s0 <= c_cmd_idle; + end else begin + axi_wr_marvin_awvalid <= 1'b1; + viv_s0 <= c_cmd_late; + end + end + default : begin + if ((bvci_cmd == 2'b10) && bvci_cmdval) begin + axi_wr_marvin_awvalid <= 1'b1; + viv_s0 <= c_cmd_set; + end else begin + axi_wr_marvin_awvalid <= 1'b0; + viv_s0 <= c_cmd_idle; + end + end + endcase + end + end + assign viv_s1 = bvci_plen[7:3] - 5'b1; + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + axi_wr_marvin_wvalid <= 1'd0; + axi_wr_marvin_awlen <= 4'd0; + axi_wr_marvin_awaddr <= 29'd0; + axi_wr_marvin_wdata <= 64'd0; + axi_wr_marvin_wlast <= 1'b0; + end else begin + if (axi_wr_marvin_wlast & axi_wr_marvin_wready) begin + axi_wr_marvin_wvalid <= 1'b0; + axi_wr_marvin_wlast <= 1'b0; + end else if ((!axi_wr_marvin_wvalid | axi_wr_marvin_wready) && + (viv_s0 != c_cmd_late)) begin + axi_wr_marvin_wvalid <= bvci_cmdval; + axi_wr_marvin_awlen <= viv_s1[3:0]; + axi_wr_marvin_wdata <= bvci_wdata; + if (bvci_cmdval && bvci_cmdack) begin + axi_wr_marvin_wlast <= bvci_eop; + end + if (viv_s0 == c_cmd_idle) begin + axi_wr_marvin_awaddr <= bvci_address; + end + end + end + end + assign axi_wr_marvin_awsize = 3'b011; + assign axi_wr_marvin_awburst = 2'b01; + assign axi_wr_marvin_awlock = 2'b00; + assign axi_wr_marvin_awcache = 4'b0000; + assign axi_wr_marvin_awprot = 3'b000; + assign axi_wr_marvin_awid = 4'b0000; + assign axi_wr_marvin_wstrb = 8'b11111111; + assign axi_wr_marvin_wid = 4'b0; + assign axi_wr_marvin_bready = 1'b1; + assign bvci_cmdack = ((!axi_wr_marvin_wvalid | axi_wr_marvin_wready) & + !axi_wr_marvin_wlast & (viv_s0 != c_cmd_late)); + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + bvci_rspval <= 1'h0; + end else begin + if (axi_wr_marvin_wready) begin + bvci_rspval <= 1'b1; + end + else begin + bvci_rspval <= 1'b0; + end + end + end + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + bvci_reop <= 1'h0; + end else begin + if (axi_wr_marvin_bvalid) begin + bvci_reop <= 1'b1; + end + else begin + bvci_reop <= 1'b0; + end + end + end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_conv.v b/ispyocto/rtl/ispyocto/vsisp_conv.v new file mode 100644 index 0000000..40e31d1 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_conv.v
@@ -0,0 +1,543 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_conv( + clk, + reset_n, + soft_rst, + in_y_val, + in_y_data, + in_y_h_end, + in_y_v_end, + in_y_cfg_upd, + in_y_ack, + in_cb_val, + in_cb_data, + in_cb_h_end, + in_cb_v_end, + in_cb_cfg_upd, + in_cb_ack, + in_cr_val, + in_cr_data, + in_cr_h_end, + in_cr_v_end, + in_cr_cfg_upd, + in_cr_ack, + out_y_r_val, + out_y_r_data, + out_y_r_h_end, + out_y_r_v_end, + out_y_r_cfg_upd, + out_y_r_ack, + out_cb_g_val, + out_cb_g_data, + out_cb_g_h_end, + out_cb_g_v_end, + out_cb_g_cfg_upd, + out_cb_g_ack, + out_cr_b_val, + out_cr_b_data, + out_cr_b_h_end, + out_cr_b_v_end, + out_cr_b_cfg_upd, + out_cr_b_ack, + sp_input_format, + cfg_y_full, + cfg_crcb_full, + cfg_422noncosited, + sp_output_format, + out_y_r_frame_start, + out_y_r_frame_end, + out_y_r_line_start, + out_y_r_line_end, + out_cb_g_frame_start, + out_cb_g_frame_end, + out_cb_g_line_start, + out_cb_g_line_end, + out_cr_b_frame_start, + out_cr_b_frame_end, + out_cr_b_line_start, + out_cr_b_line_end, + out_y_r_val_stream, + out_cb_g_val_stream, + out_cr_b_val_stream +); +`include "vsisp_self_resize.vh" +parameter c_dither_enable = 1'b1; +parameter fifo_addr_width=4; +localparam fifo_depth = 2**(fifo_addr_width-1); +input clk; +input reset_n; +input soft_rst; +input in_y_val; +input [ 8-1: 0] in_y_data; +input in_y_h_end; +input in_y_v_end; +input in_y_cfg_upd; +output in_y_ack; +input in_cb_val; +input [ 8-1: 0] in_cb_data; +input in_cb_h_end; +input in_cb_v_end; +input in_cb_cfg_upd; +output in_cb_ack; +input in_cr_val; +input [ 8-1: 0] in_cr_data; +input in_cr_h_end; +input in_cr_v_end; +input in_cr_cfg_upd; +output in_cr_ack; +output out_y_r_val; +output [ 7: 0] out_y_r_data; +output out_y_r_h_end; +output out_y_r_v_end; +output out_y_r_cfg_upd; +input out_y_r_ack; +output out_cb_g_val; +output [ 7: 0] out_cb_g_data; +output out_cb_g_h_end; +output out_cb_g_v_end; +output out_cb_g_cfg_upd; +input out_cb_g_ack; +output out_cr_b_val; +output [ 7: 0] out_cr_b_data; +output out_cr_b_h_end; +output out_cr_b_v_end; +output out_cr_b_cfg_upd; +input out_cr_b_ack; +input [ 1: 0] sp_input_format; +input cfg_y_full; +input cfg_crcb_full; +input cfg_422noncosited; +input [ 2: 0] sp_output_format; +output out_y_r_frame_start; +output out_y_r_frame_end; +output out_y_r_line_start; +output out_y_r_line_end; +output out_cb_g_frame_start; +output out_cb_g_frame_end; +output out_cb_g_line_start; +output out_cb_g_line_end; +output out_cr_b_frame_start; +output out_cr_b_frame_end; +output out_cr_b_line_start; +output out_cr_b_line_end; +output out_y_r_val_stream; +output out_cb_g_val_stream; +output out_cr_b_val_stream; +wire [8-1:0] viv_s0; +wire viv_s1; +wire viv_s2; +wire viv_s3; +wire viv_s4; +wire viv_s5; +wire [8-1:0] viv_s6; +wire viv_s7; +wire viv_s8; +wire viv_s9; +wire viv_s10; +wire viv_s11; +reg viv_s12; +reg viv_s13; +wire [8-1:0] viv_s14; +wire viv_s15; +wire viv_s16; +wire viv_s17; +wire viv_s18; +wire viv_s19; +wire viv_s20; +wire viv_s21; +wire viv_s22; +wire viv_s23; +wire viv_s24; +wire viv_s25; +wire viv_s26; +wire viv_s27; +wire [8-1:0] viv_s28; +wire viv_s29; +wire viv_s30; +wire viv_s31; +wire viv_s32; +wire viv_s33; +wire [8-1:0] viv_s34; +wire viv_s35; +wire viv_s36; +wire viv_s37; +wire viv_s38; +wire viv_s39; +wire [8-1:0] viv_s40; +wire viv_s41; +wire viv_s42; +wire viv_s43; +wire viv_s44; +wire viv_s45; +wire [8+3-1:0] viv_s46; +wire [8+3-1:0] viv_s47; +wire [8+3-1:0] viv_s48; +wire [8+3-1:0] viv_s49; +wire [8+3-1:0] viv_s50; +wire [8+3-1:0] viv_s51; +reg [8+3-1:0] viv_s52; +reg [8+3-1:0] viv_s53; +reg [8+3-1:0] viv_s54; +reg viv_s55; +reg viv_s56; +reg viv_s57; +wire viv_s58; +wire viv_s59; +wire viv_s60; +wire [7: 0] viv_s61; +wire [7: 0] viv_s62; +wire [7: 0] viv_s63; +reg [ 8-1: 0] viv_s64; +reg [ 8-1: 0] viv_s65; +reg [ 8-1: 0] viv_s66; +reg viv_s67; +reg viv_s68; +reg viv_s69; +wire [1:0] viv_s70; +reg [1:0] viv_s71; +reg [1:0] viv_s72; +reg [1:0] viv_s73; +reg [2:0] viv_s74; +vsisp_conv_422to444 u_conv422to444 ( + .clk (clk), + .reset_n (reset_n), + .soft_rst (soft_rst), + .in_y_val (in_y_val), + .in_y_data (in_y_data), + .in_y_h_end (in_y_h_end), + .in_y_v_end (in_y_v_end), + .in_y_cfg_upd (in_y_cfg_upd), + .in_y_ack (in_y_ack), + .in_cb_val (in_cb_val), + .in_cb_data (in_cb_data), + .in_cb_h_end (in_cb_h_end), + .in_cb_v_end (in_cb_v_end), + .in_cb_cfg_upd (in_cb_cfg_upd), + .in_cb_ack (in_cb_ack), + .in_cr_val (in_cr_val), + .in_cr_data (in_cr_data), + .in_cr_h_end (in_cr_h_end), + .in_cr_v_end (in_cr_v_end), + .in_cr_cfg_upd (in_cr_cfg_upd), + .in_cr_ack (in_cr_ack), + .conv422to444_y_val (viv_s18), + .conv422to444_y_data (viv_s14), + .conv422to444_y_h_end (viv_s15), + .conv422to444_y_v_end (viv_s16), + .conv422to444_y_cfg_upd (viv_s17), + .conv422to444_y_ack (viv_s19), + .conv422to444_cb_val (viv_s10), + .conv422to444_cb_data (viv_s6), + .conv422to444_cb_h_end (viv_s7), + .conv422to444_cb_v_end (viv_s8), + .conv422to444_cb_cfg_upd(viv_s9), + .conv422to444_cb_ack (viv_s11), + .conv422to444_cr_val (viv_s4), + .conv422to444_cr_data (viv_s0), + .conv422to444_cr_h_end (viv_s1), + .conv422to444_cr_v_end (viv_s2), + .conv422to444_cr_cfg_upd(viv_s3), + .conv422to444_cr_ack (viv_s5), + .cfg_422noncosited(viv_s69), + .sp_input_format(sp_input_format), + .sp_output_format(sp_output_format) +); +assign viv_s20 = (sp_output_format[2] == 1'b1); +assign viv_s21 = (sp_output_format == 3'b100); +assign viv_s22 = (sp_output_format == 3'b011); +assign viv_s23 = viv_s18 && viv_s10 && viv_s4; +assign viv_s24 = viv_s45 && viv_s39 && viv_s33; +assign viv_s25 = viv_s45 && viv_s39; +assign viv_s26 = viv_s23 && viv_s24; +assign viv_s27 = viv_s23 && viv_s25; +assign viv_s44 = (viv_s21) ? viv_s27 : + (viv_s20) ? viv_s26 : + viv_s18; +assign viv_s38 = (viv_s21) ? viv_s27 : + (viv_s20) ? viv_s26 : + viv_s10; +assign viv_s32 = (viv_s21) ? 1'b0 : + (viv_s20) ? viv_s26 : + viv_s4; +assign viv_s19 = (viv_s21) ? viv_s27 : + (viv_s20) ? viv_s26 : + viv_s45; +assign viv_s11 = (viv_s21) ? viv_s27 : + (viv_s20) ? viv_s26 : + viv_s39; +assign viv_s5 = (viv_s21) ? viv_s27 : + (viv_s20) ? viv_s26 : + viv_s33; +assign viv_s35 = (viv_s20) ? viv_s15 : viv_s7 ; +assign viv_s36 = (viv_s20) ? viv_s16 : viv_s8 ; +assign viv_s37 = (viv_s20) ? viv_s17 : viv_s9 ; +assign viv_s29 = (viv_s20) ? viv_s15 : viv_s1 ; +assign viv_s30 = (viv_s20) ? viv_s16 : viv_s2 ; +assign viv_s31 = (viv_s20) ? viv_s17 : viv_s3 ; +assign viv_s34 = viv_s6; +assign viv_s28 = viv_s0; +assign viv_s40 = viv_s14; +assign viv_s41 = viv_s15; +assign viv_s42 = viv_s16; +assign viv_s43 = viv_s17; +always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + viv_s67 <= 1'b0; + viv_s68 <= 1'b0; + viv_s69 <= 1'b0; + end else begin + viv_s67 <= cfg_y_full; + viv_s68 <= cfg_crcb_full; + viv_s69 <= cfg_422noncosited; + end +end +always @(posedge clk or negedge reset_n) begin + if (reset_n == 1'b0) begin + viv_s12 <= 0; + viv_s13 <= 0; + end else begin + if(soft_rst) begin + viv_s12 <= 0; + viv_s13 <= 0; + end else begin + if (viv_s18 && viv_s19) begin + if (viv_s15) begin + viv_s12 <= 0; + if (viv_s16) begin + viv_s13 <= 0; + end else begin + viv_s13 <= ~viv_s13; + end + end else begin + viv_s12 <= ~viv_s12; + end + end + end + end +end +assign viv_s70 = {viv_s13, viv_s12}; +always @(*) begin + case (viv_s70) + 2'b00 : viv_s71 = 2'd0; + 2'b01 : viv_s71 = 2'd2; + 2'b10 : viv_s71 = 2'd3; + default : viv_s71 = 2'd1; + endcase +end +always @(*) begin + case (viv_s70) + 2'b00 : viv_s72 = 2'd3; + 2'b01 : viv_s72 = 2'd1; + 2'b10 : viv_s72 = 2'd0; + default : viv_s72 = 2'd2; + endcase +end +always @(*) begin + if (c_dither_enable && (sp_output_format == 3'b101)) begin + viv_s73 = viv_s71; + viv_s74 = {1'b0, viv_s72}; + end else if (c_dither_enable && viv_s21) begin + viv_s73 = viv_s71; + viv_s74 = {viv_s72, 1'b0}; + end else begin + viv_s73 = 2'b00; + viv_s74 = 3'b000; + end +end +vsisp_conv_yuv2rgb u1_conv_yuv2rgb( + .cfg_y_full (viv_s67), + .cfg_crcb_full(viv_s68), + .dith_offs_g (viv_s73 ), + .dith_offs_rb (viv_s74 ), + .y (viv_s40 ), + .cb (viv_s34 ), + .cr (viv_s28 ), + .r (viv_s61 ), + .g (viv_s62 ), + .b (viv_s63 ) +); +always @( viv_s40 or + viv_s34 or + viv_s28 or + viv_s61 or viv_s63 or viv_s62 or + sp_output_format) begin + if (sp_output_format[2] == 1'b1) begin + if (sp_output_format[1:0]== 2'b01) begin + viv_s66 = {2'b00, viv_s61[7:2]}; + viv_s65 = {2'b00, viv_s62[7:2]}; + viv_s64 = {2'b00, viv_s63[7:2]}; + end + else if (sp_output_format[1:0]== 2'b00) begin + viv_s66 = {viv_s61[7:3], viv_s62[7:5]}; + viv_s65 = {viv_s62[4:2], viv_s63[7:3]}; + viv_s64 = 8'h0; + end + else begin + viv_s66 = viv_s61; + viv_s65 = viv_s62; + viv_s64 = viv_s63; + end + end + else begin + viv_s66 = viv_s40; + viv_s65 = viv_s34; + viv_s64 = viv_s28; + end +end +assign viv_s48 = {viv_s43, viv_s42, + viv_s41, viv_s66}; +assign viv_s47 = {viv_s37, viv_s36, + viv_s35, viv_s65}; +assign viv_s46 = {viv_s31, viv_s30, + viv_s29, viv_s64}; +always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + viv_s54 <= {8+3{1'b0}}; + viv_s53 <= {8+3{1'b0}}; + viv_s52 <= {8+3{1'b0}}; + viv_s57 <= 1'b0; + viv_s56 <= 1'b0; + viv_s55 <= 1'b0; + end else if (soft_rst) begin + viv_s57 <= 1'b0; + viv_s56 <= 1'b0; + viv_s55 <= 1'b0; + end else begin + if (viv_s45) begin + viv_s57 <= viv_s44; + viv_s54 <= viv_s48; + end + if (viv_s39) begin + viv_s56 <= viv_s38; + viv_s53 <= viv_s47; + end + if (viv_s33) begin + viv_s55 <= viv_s32; + viv_s52 <= viv_s46; + end + end +end +assign viv_s45 = viv_s60 | (~viv_s57); +assign viv_s39 = viv_s59 | (~viv_s56); +assign viv_s33 = viv_s58 | (~viv_s55); +wire viv_s75; +vsisp_conv_dpsbe #(.c_dpsbe_data_width(8+3)) u_y_conv_dpsbe( + .clk ( clk ), + .reset_n ( reset_n ), + .soft_rst ( soft_rst ), + .dpsbe_data_i ( viv_s54 ), + .dpsbe_val_i ( viv_s57 ), + .dpsbe_ack_o ( viv_s60 ), + .dpsbe_data_o ( viv_s49 ), + .dpsbe_val_o ( viv_s75 ), + .dpsbe_ack_i ( out_y_r_ack ) +); +assign out_y_r_data = viv_s49[8-1:0]; +assign out_y_r_h_end = viv_s49[8]; +assign out_y_r_v_end = viv_s49[8+1]; +assign out_y_r_cfg_upd = viv_s49[8+2]; +vsisp_conv_gen_streaming_interface u_y_r_conv_gen_streaming_interface( + .clk (clk), + .reset_n (reset_n), + .soft_rst (soft_rst), + .val (out_y_r_val), + .ack (out_y_r_ack), + .h_end (out_y_r_h_end), + .v_end (out_y_r_v_end), + .frame_start (out_y_r_frame_start), + .frame_end (out_y_r_frame_end), + .line_start (out_y_r_line_start), + .line_end (out_y_r_line_end) +); +wire viv_s76; +vsisp_conv_dpsbe #(.c_dpsbe_data_width(8+3)) u_cb_conv_dpsbe( + .clk ( clk ), + .reset_n ( reset_n ), + .soft_rst ( soft_rst ), + .dpsbe_data_i ( viv_s53 ), + .dpsbe_val_i ( viv_s56 ), + .dpsbe_ack_o ( viv_s59 ), + .dpsbe_data_o ( viv_s51 ), + .dpsbe_val_o ( viv_s76 ), + .dpsbe_ack_i ( out_cb_g_ack ) +); +assign out_cb_g_data = viv_s51[8-1:0]; +assign out_cb_g_h_end = viv_s51[8]; +assign out_cb_g_v_end = viv_s51[8+1]; +assign out_cb_g_cfg_upd = viv_s51[8+2]; +vsisp_conv_gen_streaming_interface u_cb_g_conv_gen_streaming_interface( + .clk (clk), + .reset_n (reset_n), + .soft_rst (soft_rst), + .val (out_cb_g_val), + .ack (out_cb_g_ack), + .h_end (out_cb_g_h_end), + .v_end (out_cb_g_v_end), + .frame_start (out_cb_g_frame_start), + .frame_end (out_cb_g_frame_end), + .line_start (out_cb_g_line_start), + .line_end (out_cb_g_line_end) +); +wire viv_s77; +vsisp_conv_dpsbe #(.c_dpsbe_data_width(8+3)) u_cr_conv_dpsbe( + .clk ( clk ), + .reset_n ( reset_n ), + .soft_rst ( soft_rst ), + .dpsbe_data_i ( viv_s52 ), + .dpsbe_val_i ( viv_s55 ), + .dpsbe_ack_o ( viv_s58 ), + .dpsbe_data_o ( viv_s50 ), + .dpsbe_val_o ( viv_s77 ), + .dpsbe_ack_i ( out_cr_b_ack ) +); +assign out_cr_b_data = viv_s50[8-1:0]; +assign out_cr_b_h_end = viv_s50[8]; +assign out_cr_b_v_end = viv_s50[8+1]; +assign out_cr_b_cfg_upd = viv_s50[8+2]; +vsisp_conv_gen_streaming_interface u_cr_b_conv_gen_streaming_interface( + .clk (clk), + .reset_n (reset_n), + .soft_rst (soft_rst), + .val (out_cr_b_val), + .ack (out_cr_b_ack), + .h_end (out_cr_b_h_end), + .v_end (out_cr_b_v_end), + .frame_start (out_cr_b_frame_start), + .frame_end (out_cr_b_frame_end), + .line_start (out_cr_b_line_start), + .line_end (out_cr_b_line_end) +); +wire viv_s78; +wire viv_s79; +wire viv_s80; +wire viv_s81; +wire viv_s82; +wire out_y_r_val = viv_s75 & out_y_r_ack; +wire out_cb_g_val = viv_s76 & out_cb_g_ack; +wire out_cr_b_val = viv_s77 & out_cr_b_ack; +wire out_y_r_val_stream = out_y_r_val; +wire out_cb_g_val_stream = out_cb_g_val; +wire out_cr_b_val_stream = out_cr_b_val; +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_conv_422to444.v b/ispyocto/rtl/ispyocto/vsisp_conv_422to444.v new file mode 100644 index 0000000..f1f3cc5 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_conv_422to444.v
@@ -0,0 +1,409 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_conv_422to444 ( + clk, + reset_n, + soft_rst, + in_y_val, + in_y_data, + in_y_h_end, + in_y_v_end, + in_y_cfg_upd, + in_y_ack, + in_cb_val, + in_cb_data, + in_cb_h_end, + in_cb_v_end, + in_cb_cfg_upd, + in_cb_ack, + in_cr_val, + in_cr_data, + in_cr_h_end, + in_cr_v_end, + in_cr_cfg_upd, + in_cr_ack, + conv422to444_y_val, + conv422to444_y_data, + conv422to444_y_h_end, + conv422to444_y_v_end, + conv422to444_y_cfg_upd, + conv422to444_y_ack, + conv422to444_cb_val, + conv422to444_cb_data, + conv422to444_cb_h_end, + conv422to444_cb_v_end, + conv422to444_cb_cfg_upd, + conv422to444_cb_ack, + conv422to444_cr_val, + conv422to444_cr_data, + conv422to444_cr_h_end, + conv422to444_cr_v_end, + conv422to444_cr_cfg_upd, + conv422to444_cr_ack, + cfg_422noncosited, + sp_input_format, + sp_output_format +); +input clk; +input reset_n; +input soft_rst; +input in_y_val; +input [7:0] in_y_data; +input in_y_h_end; +input in_y_v_end; +input in_y_cfg_upd; +output in_y_ack; +input in_cb_val; +input [7:0] in_cb_data; +input in_cb_h_end; +input in_cb_v_end; +input in_cb_cfg_upd; +output in_cb_ack; +input in_cr_val; +input [7:0] in_cr_data; +input in_cr_h_end; +input in_cr_v_end; +input in_cr_cfg_upd; +output in_cr_ack; +output conv422to444_y_val; +output [7:0] conv422to444_y_data; +output conv422to444_y_h_end; +output conv422to444_y_v_end; +output conv422to444_y_cfg_upd; +input conv422to444_y_ack; +output conv422to444_cb_val; +output [7:0] conv422to444_cb_data; +output conv422to444_cb_h_end; +output conv422to444_cb_v_end; +output conv422to444_cb_cfg_upd; +input conv422to444_cb_ack; +output conv422to444_cr_val; +output [7:0] conv422to444_cr_data; +output conv422to444_cr_h_end; +output conv422to444_cr_v_end; +output conv422to444_cr_cfg_upd; +input conv422to444_cr_ack; +input cfg_422noncosited; +input [1:0] sp_input_format; +input [2:0] sp_output_format; +wire [10:0] viv_s0; +wire [10:0] viv_s1; +wire viv_s2; +wire viv_s3; +wire [10:0] viv_s4; +wire viv_s5; +wire viv_s6; +wire [10:0] viv_s7; +wire [10:0] viv_s8; +wire [10:0] viv_s9; +wire [10:0] viv_s10; +wire [10:0] viv_s11; +wire viv_s12; +wire [7:0] viv_s13; +wire viv_s14; +wire viv_s15; +wire viv_s16; +wire viv_s17; +wire viv_s18; +wire [7:0] viv_s19; +wire viv_s20; +wire viv_s21; +wire viv_s22; +wire viv_s23; +wire viv_s24; +wire viv_s25; +wire viv_s26; +wire viv_s27; +reg conv422to444_cb_val; +reg [7:0] conv422to444_cb_data; +reg conv422to444_cb_h_end; +reg conv422to444_cb_v_end; +reg conv422to444_cb_cfg_upd; +reg conv422to444_cr_val; +reg [7:0] conv422to444_cr_data; +reg conv422to444_cr_h_end; +reg conv422to444_cr_v_end; +reg conv422to444_cr_cfg_upd; +reg [7:0] viv_s28; +reg [7:0] viv_s29; +wire viv_s30; +wire viv_s31; +reg viv_s32; +reg viv_s33; +reg viv_s34; +reg viv_s35; +reg viv_s36; +reg viv_s37; +reg viv_s38; +reg viv_s39; +wire viv_s40; +wire viv_s41; +wire viv_s42; +wire viv_s43; +wire viv_s44; +wire viv_s45; +wire viv_s46; +wire viv_s47; +wire viv_s48; +wire viv_s49; +wire viv_s50; +wire viv_s51; +wire viv_s52; +wire viv_s53; +wire viv_s54; +wire [7:0] viv_s55; +wire [7:0] viv_s56; +wire viv_s57; +wire viv_s58; +wire viv_s59; +wire viv_s60; +wire viv_s61; +wire viv_s62; +wire viv_s63; +wire viv_s64; +wire [7:0] viv_s65; +wire [7:0] viv_s66; +wire [7:0] viv_s67; +wire [7:0] viv_s68; +wire [9:0] viv_s69; +wire [9:0] viv_s70; +wire [7:0] viv_s71; +wire [7:0] viv_s72; +wire [9:0] viv_s73; +wire [9:0] viv_s74; +assign viv_s0 = {in_y_cfg_upd, + in_y_v_end, + in_y_h_end, + in_y_data} ; +vsisp_conv_dpsbe #(11) u1_conv_dpsbe( + .clk ( clk ), + .reset_n ( reset_n ), + .soft_rst ( soft_rst ), + .dpsbe_data_i ( viv_s0 ), + .dpsbe_val_i ( in_y_val ), + .dpsbe_ack_o ( in_y_ack ), + .dpsbe_data_o ( viv_s1 ), + .dpsbe_val_o ( viv_s2 ), + .dpsbe_ack_i ( viv_s3 ) +); +vsisp_conv_dpsfifo #(11) u1_conv_dpsfifo( + .clk ( clk ), + .reset_n ( reset_n ), + .soft_rst ( soft_rst ), + .fifo_data_i ( viv_s1 ), + .fifo_val_i ( viv_s2 ), + .fifo_ack_o ( viv_s3 ), + .fifo_data_o ( viv_s4 ), + .fifo_val_o ( viv_s5 ), + .fifo_ack_i ( viv_s6 ) +); +assign viv_s7 = {in_cb_cfg_upd, + in_cb_v_end, + in_cb_h_end, + in_cb_data} ; +assign {viv_s16, + viv_s15, + viv_s14, + viv_s13 } = viv_s8; +vsisp_conv_dpsbe #(11) u3_conv_dpsbe( + .clk ( clk ), + .reset_n ( reset_n ), + .soft_rst ( soft_rst ), + .dpsbe_data_i ( viv_s7 ), + .dpsbe_val_i ( in_cb_val ), + .dpsbe_ack_o ( in_cb_ack ), + .dpsbe_data_o ( viv_s8 ), + .dpsbe_val_o ( viv_s12 ), + .dpsbe_ack_i ( viv_s17 ) +); +assign viv_s17 = viv_s26; +assign viv_s9 = {in_cr_cfg_upd, + in_cr_v_end, + in_cr_h_end, + in_cr_data} ; +assign {viv_s22, + viv_s21, + viv_s20, + viv_s19 } = viv_s10; +vsisp_conv_dpsbe #(11) u2_conv_dpsbe( + .clk ( clk ), + .reset_n ( reset_n ), + .soft_rst ( soft_rst ), + .dpsbe_data_i ( viv_s9 ), + .dpsbe_val_i ( in_cr_val ), + .dpsbe_ack_o ( in_cr_ack ), + .dpsbe_data_o ( viv_s10 ), + .dpsbe_val_o ( viv_s18 ), + .dpsbe_ack_i ( viv_s23 ) +); +assign viv_s23 = viv_s27; +assign viv_s46 = (sp_input_format == 2'b10) && + ((sp_output_format == 3'b011) | + (sp_output_format[2] == 1'b1)); +assign viv_s30 = viv_s47 && viv_s24; +assign viv_s31 = viv_s48 && viv_s25; +assign viv_s40 = viv_s34 && ~viv_s32; +assign viv_s42 = viv_s36 && ~viv_s32; +assign viv_s44 = viv_s49 && ~viv_s38 && ~viv_s34; +assign viv_s41 = viv_s35 && ~viv_s33; +assign viv_s43 = viv_s37 && ~viv_s33; +assign viv_s45 = viv_s50 && ~viv_s39 && ~viv_s35; +assign viv_s57 = (viv_s46) ? viv_s30 && ~viv_s40 && ~viv_s42 : viv_s47; +assign viv_s58 = (viv_s46) ? viv_s31 && ~viv_s41 && ~viv_s43 : viv_s48; +assign viv_s26 = (viv_s46) ? viv_s30 && viv_s32 && ~viv_s44 : viv_s24; +assign viv_s27 = (viv_s46) ? viv_s31 && viv_s33 && ~viv_s45 : viv_s25; +assign viv_s59 = (viv_s46) ? viv_s38 : viv_s49; +assign viv_s63 = (viv_s46 && ~viv_s32) ? 1'b0 : viv_s53; +assign viv_s61 = (viv_s46) ? viv_s39 : viv_s50; +assign viv_s64 = (viv_s46 && ~viv_s33) ? 1'b0 : viv_s54; +assign viv_s60 = viv_s51; +assign viv_s62 = viv_s52; +always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + viv_s32 <= 1'b0; + viv_s33 <= 1'b0; + viv_s28 <= 8'b0; + viv_s29 <= 8'b0; + viv_s38 <= 1'b0; + viv_s39 <= 1'b0; + viv_s34 <= 1'b1; + viv_s35 <= 1'b1; + viv_s36 <= 1'b0; + viv_s37 <= 1'b0; + end + else begin + if (soft_rst) begin + viv_s32 <= 1'b0; + viv_s33 <= 1'b0; + viv_s34 <= 1'b1; + viv_s35 <= 1'b1; + viv_s36 <= 1'b0; + viv_s37 <= 1'b0; + end else begin + if (viv_s46) begin + if (viv_s30) begin + viv_s32 <= ~viv_s32; + if (viv_s32) begin + viv_s34 <= viv_s38 && ~viv_s34; + viv_s28 <= viv_s55; + viv_s38 <= viv_s49 && ~viv_s38 && ~viv_s34; + viv_s36 <= viv_s49 && ~viv_s36 && ~viv_s34; + end + end + if (viv_s31) begin + viv_s33 <= ~viv_s33; + if (viv_s33) begin + viv_s35 <= viv_s39 && ~viv_s35; + viv_s29 <= viv_s56; + viv_s39 <= viv_s50 && ~viv_s39 && ~viv_s35; + viv_s37 <= viv_s50 && ~viv_s37 && ~viv_s35; + end + end + end else begin + viv_s32 <= 1'b0; + viv_s33 <= 1'b0; + viv_s28 <= 8'b0; + viv_s29 <= 8'b0; + viv_s38 <= 1'b0; + viv_s39 <= 1'b0; + viv_s34 <= 1'b1; + viv_s35 <= 1'b1; + viv_s36 <= 1'b0; + viv_s37 <= 1'b0; + end + end + end +end +assign viv_s67 = (~viv_s32 || viv_s34) ? viv_s55 : viv_s28; +assign viv_s71 = (~viv_s33 || viv_s35) ? viv_s56 : viv_s29; +assign viv_s68 = (~viv_s32 && ~viv_s34) ? viv_s28 : viv_s55; +assign viv_s72 = (~viv_s33 && ~viv_s35) ? viv_s29 : viv_s56; +assign viv_s69 = {1'b0,viv_s68,1'b0} + viv_s68; +assign viv_s73 = {1'b0,viv_s72,1'b0} + viv_s72; +assign viv_s70 = cfg_422noncosited ? viv_s69 + {1'b0,viv_s67} : + {1'b0,viv_s68,1'b0} + {viv_s55,1'b0}; +assign viv_s74 = cfg_422noncosited ? viv_s73 + {1'b0,viv_s71} : + {1'b0,viv_s72,1'b0} + {viv_s56,1'b0}; +assign viv_s65 = viv_s46 ? viv_s70[9:2] : viv_s55; +assign viv_s66 = viv_s46 ? viv_s74[9:2] : viv_s56; +assign viv_s55 = viv_s13; +assign viv_s49 = viv_s14; +assign viv_s51 = viv_s15; +assign viv_s53 = viv_s16; +assign viv_s47 = viv_s12; +assign viv_s56 = viv_s19; +assign viv_s50 = viv_s20; +assign viv_s52 = viv_s21; +assign viv_s54 = viv_s22; +assign viv_s48 = viv_s18; +always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + conv422to444_cb_data <= {8'b0}; + conv422to444_cb_h_end <= 1'b0; + conv422to444_cb_v_end <= 1'b0; + conv422to444_cb_cfg_upd <= 1'b0; + conv422to444_cr_data <= {8'b0}; + conv422to444_cr_h_end <= 1'b0; + conv422to444_cr_v_end <= 1'b0; + conv422to444_cr_cfg_upd <= 1'b0; + conv422to444_cb_val <= 1'b0; + conv422to444_cr_val <= 1'b0; + end else if (soft_rst) begin + conv422to444_cb_val <= 1'b0; + conv422to444_cr_val <= 1'b0; + end else begin + if (viv_s24) begin + conv422to444_cb_val <= viv_s57; + conv422to444_cb_data <= viv_s65; + conv422to444_cb_h_end <= viv_s59; + conv422to444_cb_v_end <= viv_s60; + conv422to444_cb_cfg_upd <= viv_s63; + end + if (viv_s25) begin + conv422to444_cr_val <= viv_s58; + conv422to444_cr_data <= viv_s66; + conv422to444_cr_h_end <= viv_s61; + conv422to444_cr_v_end <= viv_s62; + conv422to444_cr_cfg_upd <= viv_s64; + end + end +end +assign viv_s24 = conv422to444_cb_ack | (~conv422to444_cb_val); +assign viv_s25 = conv422to444_cr_ack | (~conv422to444_cr_val); +assign {conv422to444_y_cfg_upd, + conv422to444_y_v_end, + conv422to444_y_h_end, + conv422to444_y_data } = viv_s11; +vsisp_conv_dpsfe #(11) u1_conv_dpsfe( + .clk ( clk ), + .reset_n ( reset_n ), + .soft_rst ( soft_rst ), + .dpsfe_data_i ( viv_s4 ), + .dpsfe_val_i ( viv_s5 ), + .dpsfe_ack_o ( viv_s6 ), + .dpsfe_data_o ( viv_s11 ), + .dpsfe_val_o ( conv422to444_y_val ), + .dpsfe_ack_i ( conv422to444_y_ack ) +); +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_conv_dpsbe.v b/ispyocto/rtl/ispyocto/vsisp_conv_dpsbe.v new file mode 100644 index 0000000..541ed4a --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_conv_dpsbe.v
@@ -0,0 +1,74 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_conv_dpsbe +( clk, + reset_n, + soft_rst, + dpsbe_data_i, + dpsbe_val_i, + dpsbe_ack_o, + dpsbe_data_o, + dpsbe_val_o, + dpsbe_ack_i +); + parameter c_dpsbe_data_width = 8; + input clk; + input reset_n; + input soft_rst; + input [c_dpsbe_data_width-1:0] dpsbe_data_i; + input dpsbe_val_i; + output dpsbe_ack_o; + output [c_dpsbe_data_width-1:0] dpsbe_data_o; + output dpsbe_val_o; + input dpsbe_ack_i; + reg [c_dpsbe_data_width-1:0] viv_s0; + reg viv_s1; + reg viv_s2; + wire viv_s3; + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + viv_s0 <= {c_dpsbe_data_width{1'b0}}; + viv_s1 <= 1'b0; + viv_s2 <= 1'b0; + end + else if (soft_rst) begin + viv_s0 <= {c_dpsbe_data_width{1'b0}}; + viv_s1 <= 1'b0; + viv_s2 <= 1'b0; + end + else begin + viv_s2 <= dpsbe_ack_i | (!viv_s3); + if (viv_s2) begin + viv_s1 <= dpsbe_val_i; + end + if (viv_s2) begin + viv_s0 <= dpsbe_data_i; + end + end + end + assign dpsbe_data_o = viv_s2 ? dpsbe_data_i : viv_s0; + assign viv_s3 = viv_s2 ? dpsbe_val_i : viv_s1; + assign dpsbe_val_o = viv_s3; + assign dpsbe_ack_o = viv_s2; +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_conv_dpsfe.v b/ispyocto/rtl/ispyocto/vsisp_conv_dpsfe.v new file mode 100644 index 0000000..28c6af3 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_conv_dpsfe.v
@@ -0,0 +1,67 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_conv_dpsfe +( clk, + reset_n, + soft_rst, + dpsfe_data_i, + dpsfe_val_i, + dpsfe_ack_o, + dpsfe_data_o, + dpsfe_val_o, + dpsfe_ack_i +); + parameter c_dpsfe_data_width = 8; + input clk; + input reset_n; + input soft_rst; + input [c_dpsfe_data_width-1:0] dpsfe_data_i; + input dpsfe_val_i; + output dpsfe_ack_o; + output [c_dpsfe_data_width-1:0] dpsfe_data_o; + output dpsfe_val_o; + input dpsfe_ack_i; + reg [c_dpsfe_data_width-1:0] dpsfe_data_o; + reg viv_s0; + wire viv_s1; + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + dpsfe_data_o <= {c_dpsfe_data_width{1'b0}}; + viv_s0 <= 1'b0; + end + else if (soft_rst) begin + dpsfe_data_o <= {c_dpsfe_data_width{1'b0}}; + viv_s0 <= 1'b0; + end + else begin + if (viv_s1) begin + viv_s0 <= dpsfe_val_i; + dpsfe_data_o <= dpsfe_data_i; + end + end + end + assign viv_s1 = dpsfe_ack_i | (~viv_s0); + assign dpsfe_ack_o = viv_s1; + assign dpsfe_val_o = viv_s0; +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_conv_dpsfifo.v b/ispyocto/rtl/ispyocto/vsisp_conv_dpsfifo.v new file mode 100644 index 0000000..7088278 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_conv_dpsfifo.v
@@ -0,0 +1,66 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_conv_dpsfifo +( clk, + reset_n, + soft_rst, + fifo_data_i, + fifo_val_i, + fifo_ack_o, + fifo_data_o, + fifo_val_o, + fifo_ack_i +); + parameter c_fifo_data_width = 11; + input clk; + input reset_n; + input soft_rst; + input [c_fifo_data_width-1:0] fifo_data_i; + input fifo_val_i; + output fifo_ack_o; + output [c_fifo_data_width-1:0] fifo_data_o; + output fifo_val_o; + input fifo_ack_i; + reg [c_fifo_data_width-1:0] viv_s0; + reg viv_s1; + wire viv_s2; + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + viv_s0 <= {c_fifo_data_width{1'b0}}; + viv_s1 <= 1'b0; + end + else if (soft_rst) begin + viv_s1 <= 1'b0; + end + else begin + viv_s1 <= (~fifo_ack_i && fifo_val_i) || (~fifo_ack_i && viv_s1) || (viv_s1 && fifo_val_i); + if (fifo_val_i && viv_s2) + viv_s0 <= fifo_data_i; + end + end + assign fifo_data_o = viv_s1 ? viv_s0 : fifo_data_i; + assign fifo_val_o = fifo_val_i || viv_s1; + assign viv_s2 = fifo_ack_i || ~viv_s1; + assign fifo_ack_o = viv_s2; +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_conv_gen_streaming_interface.v b/ispyocto/rtl/ispyocto/vsisp_conv_gen_streaming_interface.v new file mode 100644 index 0000000..cce72ea --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_conv_gen_streaming_interface.v
@@ -0,0 +1,104 @@ +//**************************************************************************** +// +// Copyright 2023 Vivante Corp. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_conv_gen_streaming_interface +(clk, + reset_n, + soft_rst, + val, + ack, + h_end, + v_end, + frame_start, + frame_end, + line_start, + line_end + ); + input clk; + input reset_n; + input soft_rst; + input val; + input ack; + input h_end; + input v_end; + output frame_start; + output frame_end; + output line_start; + output line_end; +reg viv_s0; +always @(posedge clk or negedge reset_n) begin + if (reset_n == 1'b0) begin + viv_s0 <= 1; + end else begin + if(soft_rst) begin + viv_s0 <= 1; + end else begin + if (val && ack) begin + if(viv_s0) begin + viv_s0 <= 0; + end + if(h_end && v_end) begin + viv_s0 <= 1; + end + end + end + end +end +assign frame_start = viv_s0 & val & ack; +reg viv_s1; +always @(posedge clk or negedge reset_n) begin + if(!reset_n) begin + viv_s1 <= 1'b0; + end else begin + if(soft_rst) begin + viv_s1 <= 1'b0; + end else begin + if(v_end && h_end && val && ack) begin + viv_s1<= 1'b0; + end else if(val && ack && v_end) begin + viv_s1<= 1'b1; + end + end + end +end +assign frame_end = val && ack && v_end || viv_s1; +reg viv_s2; +always @(posedge clk or negedge reset_n) begin + if (reset_n == 1'b0) begin + viv_s2 <= 1; + end else begin + if(soft_rst) begin + viv_s2 <= 1; + end else begin + if (val && ack) begin + if(viv_s2) begin + viv_s2 <= 0; + end + if(h_end) begin + viv_s2 <= 1; + end + end + end + end +end +assign line_start = viv_s2 & val & ack; +assign line_end = h_end & val & ack; +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_conv_yuv2rgb.v b/ispyocto/rtl/ispyocto/vsisp_conv_yuv2rgb.v new file mode 100644 index 0000000..02fe5bf --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_conv_yuv2rgb.v
@@ -0,0 +1,127 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_conv_yuv2rgb( + cfg_y_full, + cfg_crcb_full, + dith_offs_g, + dith_offs_rb, + y, + cb, + cr, + r, + g, + b); + input cfg_y_full; + input cfg_crcb_full; + input [1:0] dith_offs_g; + input [2:0] dith_offs_rb; + input [7:0] y; + input [7:0] cb; + input [7:0] cr; + output [7:0] r; + output [7:0] g; + output [7:0] b; + wire [ 8:0] viv_s0; + wire [11:0] viv_s1; + wire [11:0] viv_s2; + wire [11:0] viv_s3; + wire [ 7:0] viv_s4; + wire [ 7:0] viv_s5; + wire [ 9:0] viv_s6; + wire [10:0] viv_s7; + wire [13:0] viv_s8; + wire [13:0] viv_s9; + wire [ 9:0] viv_s10; + wire [10:0] viv_s11; + wire [ 9:0] viv_s12; + wire [11:0] viv_s13; + wire [12:0] viv_s14; + wire [11:0] viv_s15; + wire [ 5:0] viv_s16; + wire [11:0] viv_s17; + wire [ 6:0] viv_s18; + wire [ 9:0] viv_s19; + wire [12:0] viv_s20; + wire [ 5:0] viv_s21; + wire [11:0] viv_s22; + wire [11:0] viv_s23; + wire [12:0] viv_s24; + wire [10:0] viv_s25; + wire [10:0] viv_s26; + wire [11:0] viv_s27; + wire [12:0] viv_s28; + wire [12:0] viv_s29; + wire [12:0] viv_s30; + wire [7:0] r; + wire [7:0] g; + wire [7:0] b; + assign viv_s0 = {1'b0,y} + y[7:2]; + assign viv_s1 = {1'b0,y, 3'h0} + y; + assign viv_s2 = viv_s1 + viv_s0[8:2]; + assign viv_s3 = cfg_y_full ? {1'b0,y,3'd0} : + (y[7:4]==4'h0) ? 12'd0 + 8'd149 : + (y > 8'hEB) ? {9'd255,3'd0}+ 8'd149 : + viv_s2; + assign viv_s5 = cr; + assign viv_s4 = cb; + assign viv_s6 = {1'b0,viv_s5,1'b0} + viv_s5; + assign viv_s7 = {1'b0,viv_s5,2'b0} + viv_s6; + assign viv_s8 = (cfg_crcb_full ? {3'b0,viv_s5,3'b0} : + {viv_s6,4'b0}); + assign viv_s9 = viv_s8 + viv_s6; + assign viv_s10 = {1'b0,viv_s4,1'b0} + viv_s4; + assign viv_s11 = {1'b0,viv_s4,2'b0} + viv_s10; + assign viv_s12 = (cfg_crcb_full ? viv_s10 : + {2'b0,viv_s4}); + assign viv_s13 = {1'b0,viv_s4,3'b0} + viv_s12; + assign viv_s14 = {1'b0,viv_s4,4'b0} + viv_s13; + assign viv_s15 = cfg_crcb_full ? viv_s9[11:0] : viv_s9[13:2]; + assign viv_s16 = cfg_crcb_full ? viv_s7 [10:5] : {4'b0,viv_s5 [7:6]}; + assign viv_s17 = cfg_crcb_full ? {1'b0,viv_s9[11:1]}: {1'b0,viv_s6, 1'b0}; + assign viv_s18 = cfg_crcb_full ? {1'b0, viv_s7 [10:5]}: viv_s5 [7:1] ; + assign viv_s19 = cfg_crcb_full ? viv_s13[11:2] : viv_s14[12:3]; + assign viv_s20 = cfg_crcb_full ? {1'b0, viv_s11 ,1'b0} : {1'b0,viv_s4, 4'b0}; + assign viv_s21 = viv_s13[11:6]; + assign viv_s22 = viv_s15 + viv_s16; + assign viv_s23 = viv_s17 + viv_s18 + viv_s19; + assign viv_s24 = viv_s20 + viv_s21; + assign viv_s25 = ( cfg_crcb_full && cfg_y_full) ? {10'd718 ,1'b0} : + ( cfg_crcb_full && ~cfg_y_full) ? {10'd718 ,1'b0}+149 : + (~cfg_crcb_full && cfg_y_full) ? {10'd817 ,1'b0} : + {10'd817 ,1'b0}+149 ; + assign viv_s26 = ( cfg_crcb_full && cfg_y_full) ? {10'd366 ,1'b0}+{10'd176,1'b0} : + ( cfg_crcb_full && ~cfg_y_full) ? {10'd366 ,1'b0}+{10'd176,1'b0}-149 : + (~cfg_crcb_full && cfg_y_full) ? {10'd416 ,1'b0}+{10'd200,1'b0} : + {10'd416 ,1'b0}+{10'd200,1'b0}-149 ; + assign viv_s27 = ( cfg_crcb_full && cfg_y_full) ? {11'd907 ,1'b0} : + ( cfg_crcb_full && ~cfg_y_full) ? {11'd907 ,1'b0}+149 : + (~cfg_crcb_full && cfg_y_full) ? {11'd1033,1'b0} : + {11'd1033,1'b0}+149 ; + assign viv_s28 = ({1'b0,viv_s3} + viv_s22 + {dith_offs_rb, 3'h4}) - viv_s25; + assign viv_s29 = ({1'b0,viv_s3} + viv_s26 + {dith_offs_g , 3'h4}) - viv_s23; + assign viv_s30 = ({1'b0,viv_s3} + viv_s24 + {dith_offs_rb, 3'h4}) - viv_s27; + assign r = viv_s28[12] ? 8'h00 : viv_s28[11] ? 8'hff : viv_s28[10:3]; + assign g = viv_s29[12] ? 8'h00 : viv_s29[11] ? 8'hff : viv_s29[10:3]; + assign b = viv_s30[12] ? 8'h00 : viv_s30[11] ? 8'hff : viv_s30[10:3]; +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_dreg_en_1d.v b/ispyocto/rtl/ispyocto/vsisp_dreg_en_1d.v new file mode 100644 index 0000000..f93e2e9 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_dreg_en_1d.v
@@ -0,0 +1,50 @@ +//**************************************************************************** +// +// Copyright 2023 Vivante Corp. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_dreg_en_1d( +clk, +reset_n, +soft_reset, +in, +out, +en +); +parameter WIDTH = 32; +parameter RESET_STATE = 0; +input clk; +input reset_n, soft_reset; +input [WIDTH-1 : 0 ] in ; +input en; +output [WIDTH-1 : 0 ] out; +reg [WIDTH-1:0] out; +reg [WIDTH-1:0] viv_s0; +always @(posedge clk or negedge reset_n)begin + if(!reset_n) begin + out <= RESET_STATE; + end + else if(soft_reset) begin + out <= RESET_STATE; + end + else if(en) begin + out <= in; + end +end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_dreg_en_2d.v b/ispyocto/rtl/ispyocto/vsisp_dreg_en_2d.v new file mode 100644 index 0000000..077762b --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_dreg_en_2d.v
@@ -0,0 +1,61 @@ +//**************************************************************************** +// +// Copyright 2023 Vivante Corp. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_dreg_en_2d( +clk, +reset_n, +soft_reset, +in, +out, +en +); +parameter WIDTH = 32; +parameter RESET_STATE = 0; +input clk; +input reset_n, soft_reset; +input [WIDTH-1 : 0 ] in ; +input en; +output [WIDTH-1 : 0 ] out; +reg [WIDTH-1:0] out; +reg [WIDTH-1:0] viv_s0; +always @(posedge clk or negedge reset_n)begin + if(!reset_n) begin + viv_s0 <= RESET_STATE; + end + else if(soft_reset) begin + viv_s0 <= RESET_STATE; + end + else if(en) begin + viv_s0 <= in; + end +end +always @(posedge clk or negedge reset_n)begin + if(!reset_n) begin + out <= RESET_STATE; + end + else if(soft_reset) begin + out <= RESET_STATE; + end + else if(en) begin + out <= viv_s0; + end +end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_fifo.v b/ispyocto/rtl/ispyocto/vsisp_fifo.v new file mode 100644 index 0000000..b8824bd --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_fifo.v
@@ -0,0 +1,369 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_fifo (clk, + reset_n, + soft_rst, + wr_val, + wr_ack, + wr_h_end, + wr_v_end, + wr_data, + rd_val, + rd_ack, + rd_h_end, + rd_v_end, + rd_data, + ram_cs_n, + ram_we_n, + ram_addr, + ram_wdata, + ram_rdata); + parameter c_dw = 32; + parameter c_aw = 13; + parameter c_ram_dw = 2*(c_dw+2); + input clk; + input reset_n; + input soft_rst; + input wr_val; + output wr_ack; + input wr_h_end; + input wr_v_end; + input [c_dw-1:0] wr_data; + output rd_val; + input rd_ack; + output rd_h_end; + output rd_v_end; + output [c_dw-1:0] rd_data; + output ram_cs_n; + output ram_we_n; + output [c_aw-1:0] ram_addr; + output [c_ram_dw-1:0] ram_wdata; + input [c_ram_dw-1:0] ram_rdata; + reg viv_s0; + reg viv_s1; + reg [c_ram_dw-1:0] viv_s2; + wire viv_s3; + wire viv_s4; + wire viv_s5; + wire viv_s6; + wire viv_s7; + wire viv_s8; + wire wr_ack; + wire viv_s9; + wire viv_s10; + wire viv_s11; + wire viv_s12; + wire [1:0] viv_s13; + wire [1:0] viv_s14; + wire [2:0] viv_s15; + wire [2:0] viv_s16; + reg ram_cs_n; + reg ram_we_n; + reg [c_ram_dw-1:0] ram_wdata; + reg [c_aw:0] viv_s17; + wire [c_aw:0] viv_s18; + reg [c_aw-1:0] ram_addr; + reg [c_aw:0] viv_s19; + wire [c_aw:0] viv_s20; + reg viv_s21; + reg viv_s22; + reg [c_ram_dw-1:0] viv_s23; + reg viv_s24; + reg viv_s25; + wire [c_ram_dw-1:0] viv_s26; + wire viv_s27; + wire viv_s28; + reg [c_ram_dw-1:0] viv_s29; + reg viv_s30; + reg viv_s31; + wire [c_ram_dw-1:0] viv_s32; + wire viv_s33; + reg viv_s34; + reg [c_ram_dw-1:0] viv_s35; + wire viv_s36; + wire viv_s37; + wire viv_s38; + wire [c_ram_dw-1:0] viv_s39; + reg viv_s40; + reg viv_s41; + reg viv_s42; + reg [c_dw-1:0] viv_s43; + wire viv_s44; + wire viv_s45; + reg viv_s46; + reg rd_h_end; + reg rd_v_end; + reg [c_dw-1:0] rd_data; + wire viv_s47; + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + viv_s0 <= 1'b0; + viv_s2 <= {c_ram_dw{1'd0}}; + viv_s1 <= 1'b0; + end + else begin + if (soft_rst) begin + viv_s0 <= 1'b0; + viv_s2 <= {c_ram_dw{1'd0}}; + viv_s1 <= 1'b0; + end else begin + if (wr_val & wr_ack) begin + if (wr_h_end) begin + viv_s0 <= 1'b0; + end + else begin + viv_s0 <= !viv_s0; + end + end + if (viv_s3) begin + if (viv_s0 | wr_h_end) begin + viv_s1 <= wr_val; + end + else begin + viv_s1 <= 1'b0; + end + if (viv_s0) begin + viv_s2[c_ram_dw-1:c_dw+2] <= {wr_h_end, + wr_v_end, + wr_data}; + end + else begin + viv_s2[c_dw+1: 0] <= {wr_h_end, + wr_v_end, + wr_data}; + end + end + end + end + end + assign viv_s3 = viv_s4 | (~viv_s1); + assign wr_ack = viv_s3; + assign viv_s5 = viv_s1; + assign viv_s6 = viv_s5 & viv_s4; + assign viv_s7 = (!viv_s12 && + (viv_s16 < 3'h3)) ? 1'b1 : + 1'b0; + assign viv_s8 = !viv_s6 & viv_s7; + assign viv_s13 = {1'b0, viv_s21} + {1'b0, viv_s22}; + assign viv_s14 = {1'b0, !viv_s25} + {1'b0, !viv_s31} + {1'h0, viv_s34}; + assign viv_s15 = {1'h0, viv_s13} + {1'h0, viv_s14}; + assign viv_s16 = (viv_s15 == 3'h0) ? 3'h0 : viv_s15 - {2'h0, viv_s38}; + assign viv_s9 = (viv_s18[c_aw-1:0] == viv_s19[c_aw-1:0]) ? 1'b1 : 1'b0; + assign viv_s10 = (viv_s18[c_aw] == viv_s19[c_aw]) ? 1'b1 : 1'b0; + assign viv_s11 = (viv_s9 & !viv_s10) ? 1'b1 : 1'b0; + assign viv_s12 = (viv_s9 & viv_s10) ? 1'b1 : 1'b0; + assign viv_s4 = !viv_s11; + assign viv_s18 = viv_s17 + 1; + assign viv_s20 = viv_s19 + 1; + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + ram_cs_n <= 1'b1; + ram_we_n <= 1'b1; + ram_wdata <= {c_ram_dw{1'b0}}; + ram_addr <= {c_aw{1'b0}}; + viv_s17 <= {(c_aw+1){1'b1}}; + viv_s19 <= {(c_aw+1){1'b0}}; + end + else begin + if (soft_rst) begin + ram_cs_n <= 1'b1; + ram_we_n <= 1'b1; + ram_wdata <= {c_ram_dw{1'b0}}; + ram_addr <= {c_aw{1'b0}}; + viv_s17 <= {(c_aw+1){1'b1}}; + viv_s19 <= {(c_aw+1){1'b0}}; + end + else begin + if (viv_s6) begin + ram_cs_n <= 1'b0; + ram_we_n <= 1'b0; + ram_wdata <= viv_s2; + viv_s17 <= viv_s18; + ram_addr <= viv_s18[c_aw-1:0]; + end + else begin + ram_we_n <= 1'b1; + ram_addr <= viv_s19[c_aw-1:0]; + if (viv_s7) begin + ram_cs_n <= 1'b0; + viv_s19 <= viv_s20; + end + else begin + ram_cs_n <= 1'b1; + end + end + end + end + end + always @( posedge clk or negedge reset_n ) begin + if ( !reset_n ) begin + viv_s21 <= 1'b0; + viv_s22 <= 1'b0; + end + else begin + if ( soft_rst ) begin + viv_s21 <= 1'b0; + viv_s22 <= 1'b0; + end + else begin + viv_s21 <= viv_s8; + viv_s22 <= viv_s21; + end + end + end + always @( posedge clk or negedge reset_n ) begin + if ( !reset_n ) begin + viv_s23 <= 0; + viv_s24 <= 0; + viv_s25 <= 0; + end + else begin + if ( soft_rst) begin + viv_s24 <= 1'b0; + viv_s25 <= 1'b1; + end + else begin + viv_s25 <= viv_s28 | !viv_s27; + if (viv_s25) begin + viv_s24 <= viv_s22; + viv_s23 <= ram_rdata; + end + end + end + end + assign viv_s26 = !viv_s25 ? viv_s23 : + ram_rdata; + assign viv_s27 = !viv_s25 ? viv_s24 : viv_s22; + always @( posedge clk or negedge reset_n ) begin + if ( !reset_n ) begin + viv_s29 <= 0; + viv_s30 <= 1'b0; + viv_s31 <= 1'b0; + end + else begin + if ( soft_rst ) begin + viv_s30 <= 1'b0; + viv_s31 <= 1'b1; + end + else begin + viv_s31 <= viv_s36 | !viv_s33; + if ( viv_s31 ) begin + viv_s30 <= viv_s27; + viv_s29 <= viv_s26; + end + end + end + end + assign viv_s32 = !viv_s31 ? viv_s29 : viv_s26; + assign viv_s33 = !viv_s31 ? viv_s30 : viv_s27; + assign viv_s28 = viv_s31; + always @( posedge clk or negedge reset_n ) begin + if ( reset_n == 1'b0 ) begin + viv_s34 <= 1'b0; + viv_s35 <= 0; + end + else begin + if( soft_rst ) begin + viv_s34 <= 1'b0; + viv_s35 <= 0; + end else begin + if ( viv_s36 ) begin + viv_s34 <= viv_s33; + viv_s35 <= viv_s32; + end + end + end + end + assign viv_s36 = viv_s38 | !viv_s34; + assign viv_s39 = viv_s35; + assign viv_s37 = viv_s34; + assign viv_s38 = ~viv_s40 & viv_s45; + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + viv_s40 <= 1'b0; + viv_s41 <= 1'b0; + viv_s42 <= 1'b0; + viv_s43 <= {c_dw{1'd0}}; + end + else begin + if (soft_rst) begin + viv_s40 <= 1'b0; + viv_s41 <= 1'b0; + viv_s42 <= 1'b0; + viv_s43 <= {c_dw{1'd0}}; + end + else begin + if (viv_s45) begin + if (~viv_s40) begin + viv_s40 <= viv_s37 & + ~viv_s39[c_dw+1]; + if (viv_s37)begin + viv_s41 <= viv_s39[c_ram_dw-1]; + viv_s42 <= viv_s39[c_ram_dw-2]; + viv_s43 <= viv_s39[c_ram_dw-3:c_dw+2]; + end + end + else begin + viv_s40 <= 1'b0; + end + end + end + end + end + assign viv_s44 = viv_s40; + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + viv_s46 <= 1'b0; + rd_h_end <= 1'b0; + rd_v_end <= 1'b0; + rd_data <= {c_dw{1'd0}}; + end + else begin + if (soft_rst) begin + viv_s46 <= 1'b0; + rd_h_end <= 1'b0; + rd_v_end <= 1'b0; + rd_data <= {c_dw{1'd0}}; + end + else begin + if (viv_s47) begin + viv_s46 <= viv_s37 | viv_s44; + if (viv_s44) begin + rd_h_end <= viv_s41; + rd_v_end <= viv_s42; + rd_data <= viv_s43; + end + else if (viv_s37)begin + rd_h_end <= viv_s39[c_dw+1]; + rd_v_end <= viv_s39[c_dw]; + rd_data <= viv_s39[c_dw-1:0]; + end + end + end + end + end + assign viv_s47 = rd_ack | ~viv_s46; + assign viv_s45 = viv_s47; + assign rd_val = viv_s46; +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_fifo4fe.v b/ispyocto/rtl/ispyocto/vsisp_fifo4fe.v new file mode 100644 index 0000000..57d5233 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_fifo4fe.v
@@ -0,0 +1,112 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_fifo4fe +( clk, + reset_n, + soft_rst, + fifo_data_i, + fifo_val_i, + fifo_ack_o, + fifo_data_o, + fifo_val_o, + fifo_ack_i +); + parameter c_fifo_data_width = 11; + input clk; + input reset_n; + input soft_rst; + input [c_fifo_data_width-1:0] fifo_data_i; + input fifo_val_i; + output fifo_ack_o; + output [c_fifo_data_width-1:0] fifo_data_o; + output fifo_val_o; + input fifo_ack_i; + wire [c_fifo_data_width-1:0] viv_s0; + wire viv_s1; + wire viv_s2; + wire [c_fifo_data_width-1:0] viv_s3; + wire viv_s4; + wire viv_s5; + wire [c_fifo_data_width-1:0] viv_s6; + wire viv_s7; + wire viv_s8; + wire [c_fifo_data_width-1:0] viv_s9; + wire viv_s10; + wire viv_s11; + vsisp_marvin_dpsfifo #(c_fifo_data_width) u1_marvin_dpsfifo( + .clk ( clk ), + .reset_n ( reset_n ), + .soft_rst ( soft_rst ), + .fifo_data_i ( fifo_data_i ), + .fifo_val_i ( fifo_val_i ), + .fifo_ack_o ( fifo_ack_o ), + .fifo_data_o ( viv_s0 ), + .fifo_val_o ( viv_s1 ), + .fifo_ack_i ( viv_s2 ) + ); + vsisp_marvin_dpsfifo #(c_fifo_data_width) u2_marvin_dpsfifo( + .clk ( clk ), + .reset_n ( reset_n ), + .soft_rst ( soft_rst ), + .fifo_data_i ( viv_s0 ), + .fifo_val_i ( viv_s1 ), + .fifo_ack_o ( viv_s2 ), + .fifo_data_o ( viv_s3 ), + .fifo_val_o ( viv_s4 ), + .fifo_ack_i ( viv_s5 ) + ); + vsisp_marvin_dpsfifo #(c_fifo_data_width) u3_marvin_dpsfifo( + .clk ( clk ), + .reset_n ( reset_n ), + .soft_rst ( soft_rst ), + .fifo_data_i ( viv_s3 ), + .fifo_val_i ( viv_s4 ), + .fifo_ack_o ( viv_s5 ), + .fifo_data_o ( viv_s6 ), + .fifo_val_o ( viv_s7 ), + .fifo_ack_i ( viv_s8 ) + ); + vsisp_marvin_dpsfifo #(c_fifo_data_width) u4_marvin_dpsfifo( + .clk ( clk ), + .reset_n ( reset_n ), + .soft_rst ( soft_rst ), + .fifo_data_i ( viv_s6 ), + .fifo_val_i ( viv_s7 ), + .fifo_ack_o ( viv_s8 ), + .fifo_data_o ( viv_s9 ), + .fifo_val_o ( viv_s10 ), + .fifo_ack_i ( viv_s11 ) + ); + vsisp_marvin_dpsfe #(c_fifo_data_width) u1_marvin_dpsfe( + .clk ( clk ), + .reset_n ( reset_n ), + .soft_rst ( soft_rst ), + .dpsfe_data_i ( viv_s9 ), + .dpsfe_val_i ( viv_s10 ), + .dpsfe_ack_o ( viv_s11 ), + .dpsfe_data_o ( fifo_data_o ), + .dpsfe_val_o ( fifo_val_o ), + .dpsfe_ack_i ( fifo_ack_i ) + ); +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_gc_den_reg.v b/ispyocto/rtl/ispyocto/vsisp_gc_den_reg.v new file mode 100644 index 0000000..ec6455d --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_gc_den_reg.v
@@ -0,0 +1,127 @@ +//**************************************************************************** +// +// Copyright 2023 Vivante Corp. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +`include "vsisp_AQ_timescale.vh" +`ifdef ASSERT_ON +`include "std_ovl_defines.h" +`endif +module vsisp_gc_den_reg ( + out, + clk, reset_, en, in + ); + parameter WIDTH = 32; + parameter RESET_STATE = 0; + input clk; + input reset_; + input en; + input [WIDTH-1 : 0 ] in ; + output [WIDTH-1 : 0 ] out; + `ifdef ASSERT_ON + assert_never_unknown #(0, 1, `OVL_ASSERT, "Enable signal of register should never be unknown!") enable_unknown_check (clk, reset_, 1'b1, en); + `endif + reg [WIDTH-1:0] out; + `ifdef VIVANTE_RANDOM_INITIAL_VALUES + integer seed ; + integer status; + reg viv_s0 ; + reg viv_s1 ; + localparam CONCAT_COUNT = (WIDTH+31)/32; + initial begin + if ($test$plusargs("seed")) begin + status = $value$plusargs("seed=%d", seed); + end else begin + seed = $random ; + end + viv_s0 = 1'b1 ; + `ifdef VIVANTE_RANDOM_INITIAL_ALL1 + viv_s0 = 1'b0; + viv_s1 = 1'b1 ; + `endif + `ifdef VIVANTE_RANDOM_INITIAL_ALL0 + viv_s0 = 1'b0; + viv_s1 = 1'b0 ; + `endif + out = viv_s0 ? {CONCAT_COUNT{$random(seed)}} | 1 : viv_s1 ? {WIDTH{1'b1}} : {WIDTH{1'b0}} ; + end + `endif + always @(posedge clk or negedge reset_) begin + if ( !reset_ ) begin + out <= #1 RESET_STATE; + end else begin + if (en) begin + out <= #1 in; + end + end + end + `ifdef VIVANTE_CHECK_POWER_SAIF + reg viv_s2; + always @(posedge clk) + viv_s2 <= #1 1'b0; + always @(negedge clk) + viv_s2 <= #1 en; + gc_toggle_monitor #(WIDTH,1) toggle_monitor(.clk(clk),.enabledClk(viv_s2),.out(out[WIDTH-1:0])); + `endif + `ifdef VIVANTE_COLLECT_TOGGLE_INFO_IN_FLOPS_AND_RAMS + `ifdef VIVANTE_SAIF_TRIGGER + reg [31:0] viv_s3; + reg [31:0] viv_s4; + reg [31:0] viv_s5; + integer i; + initial begin + viv_s3 = 0; + viv_s4 = 0; + viv_s5 = 0; + end + always @(negedge clk) begin + if(en) begin + viv_s3 <= viv_s3 + 1'b1; + if (in != out) begin + for (i = 0; i <= WIDTH-1; i = i + 1) begin + if(in[i] != out[i]) begin + viv_s4 = viv_s4 + 1'b1; + end + end + end + if(viv_s3[31] | viv_s4[31]) begin + $display("ERROR: %m - Toggle counter overflow."); + #10000; + $finish; + end + end + end + initial begin + forever begin + @(posedge `VIVANTE_SAIF_TRIGGER); + $display ("FLOP TOGGLE: %d : %m : WIDTH: %d, CLK_TOGGLE: %d - %d, OUT_TOGGLE: %d",viv_s5,WIDTH,viv_s3,WIDTH,viv_s4); + viv_s3 = 0; + viv_s4 = 0; + viv_s5 = viv_s5 + 1; + end + end + `endif + `endif + `ifdef VIVANTE_CHECK_CLOCK_GATING + initial begin + @`VIVANTE_SIM_END; + $display ("CLOCK ENABLE: %m : WIDTH: %d, EN: %d",WIDTH,en); + end + `endif +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_gc_dr_reg.v b/ispyocto/rtl/ispyocto/vsisp_gc_dr_reg.v new file mode 100644 index 0000000..86ca4c6 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_gc_dr_reg.v
@@ -0,0 +1,92 @@ +//**************************************************************************** +// +// Copyright 2023 Vivante Corp. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +`include "vsisp_AQ_timescale.vh" +`ifdef ASSERT_ON +`include "std_ovl_defines.h" +`endif +module vsisp_gc_dr_reg ( + out, + clk, reset_, in + ); + parameter WIDTH = 32; + parameter RESET_STATE = 0; + input clk; + input reset_; + input [WIDTH-1 : 0 ] in ; + output [WIDTH-1 : 0 ] out; + reg [WIDTH-1:0] out; + always @(posedge clk or negedge reset_) begin + if ( !reset_ ) begin + out <= #1 RESET_STATE; + end else begin + out <= #1 in; + end + end + `ifdef VIVANTE_CHECK_POWER_SAIF + gc_toggle_monitor #(WIDTH,1) toggle_monitor(.clk(clk),.enabledClk(clk),.out(out[WIDTH-1:0])); + `endif + `ifdef VIVANTE_COLLECT_TOGGLE_INFO_IN_FLOPS_AND_RAMS + `ifdef VIVANTE_SAIF_TRIGGER + reg [31:0] viv_s0; + reg [31:0] viv_s1; + reg [31:0] viv_s2; + integer i; + initial begin + viv_s0 = 0; + viv_s1 = 0; + viv_s2 = 0; + end + always @(negedge clk) begin + if(1) begin + viv_s0 <= viv_s0 + 1'b1; + if (in != out) begin + for (i = 0; i <= WIDTH-1; i = i + 1) begin + if(in[i] != out[i]) begin + viv_s1 = viv_s1 + 1'b1; + end + end + end + if(viv_s0[31] | viv_s1[31]) begin + $display("ERROR: %m - Toggle counter overflow."); + #10000; + $finish; + end + end + end + initial begin + forever begin + @(posedge `VIVANTE_SAIF_TRIGGER); + $display ("FLOP TOGGLE: %d : %m : WIDTH: %d, CLK_TOGGLE: %d - %d, OUT_TOGGLE: %d",viv_s2,WIDTH,viv_s0,WIDTH,viv_s1); + viv_s0 = 0; + viv_s1 = 0; + viv_s2 = viv_s2 + 1; + end + end + `endif + `endif + `ifdef VIVANTE_CHECK_CLOCK_GATING + initial begin + @`VIVANTE_SIM_END; + $display ("CLOCK ENABLE: %m : WIDTH: %d, EN: %d",WIDTH,1); + end + `endif +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp.v b/ispyocto/rtl/ispyocto/vsisp_isp.v new file mode 100644 index 0000000..6e0ae49 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_isp.v
@@ -0,0 +1,1052 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_isp + ( + clk_not_gated, + clk, + reset_clk_n, + clk_isp_rgb_ram, + clk_cfg, + reset_cfg_n, + soft_rst, + s_data, + s_hsync, + s_vsync, + s_data_val, + s_data_ack, + regs_sample_edge, + pipeline_full, + isp_data, + isp_val, + isp_ack, + isp_h_end, + isp_v_end, + isp_cfg_upd, + raw_out_data, + raw_out_h_end, + raw_out_v_end, + raw_out_val, + raw_out_cfg_upd, + raw_out_ack, + raw_mode, + isp_fifo_cs_n, + isp_fifo_we_n, + isp_fifo_addr, + isp_fifo_wdata, + isp_fifo_rdata, + ispram_addr, + ispram_wdata, + ispram_rdata, + ispram_we_n, + ispram_cs_n, + cfg_addr, + cfg_wdata, + cfg_rdata, + cfg_rd, + cfg_val, + cfg_ack, + disable_isp, + regs_disable_isp_clk, + format_conv_ctrl, + isp_int_exp_end, + isp_int_h_start, + isp_int_v_start, + isp_int_frame_in, + isp_int_awb_done, + isp_int_size_err, + isp_int_dataloss, + test_mode, + isp_clk_en + ); +`include "vsisp_isp.vh" +`include "vsisp_ram_sizes.vh" + input clk_not_gated; + input clk; + input reset_clk_n; + output clk_isp_rgb_ram; + input clk_cfg; + input reset_cfg_n; + input soft_rst; + input [c_dw_si-1:0] s_data; + input s_hsync; + input s_vsync; + input s_data_val; + output s_data_ack; + output regs_sample_edge; + input pipeline_full; + output [(2*c_dw_do)-1:0] isp_data; + output isp_val; + input isp_ack; + output isp_h_end; + output isp_v_end; + output isp_cfg_upd; + output wire [16-1:0] raw_out_data; + output raw_out_h_end; + output raw_out_v_end; + output raw_out_val; + output raw_out_cfg_upd; + input raw_out_ack ; + output raw_mode; + output isp_fifo_cs_n; + output isp_fifo_we_n; + output [c_ispfifo_aw-1:0] isp_fifo_addr; + output [c_ispfifo_dw-1:0] isp_fifo_wdata; + input [c_ispfifo_dw-1:0] isp_fifo_rdata; + output [c_aw_dem_mem-1:0] ispram_addr; + output [c_dw_dem_mem-1:0] ispram_wdata; + input [c_dw_dem_mem-1:0] ispram_rdata; + output ispram_we_n; + output ispram_cs_n; + input [31:0] cfg_addr; + input [31:0] cfg_wdata; + output [31:0] cfg_rdata; + input cfg_rd; + input cfg_val; + output cfg_ack; + input disable_isp; + output regs_disable_isp_clk; + output isp_int_h_start; + output isp_int_v_start; + output isp_int_frame_in; + output isp_int_size_err; + output isp_int_dataloss; + output isp_int_exp_end; + output isp_int_awb_done; + input test_mode; + input isp_clk_en; + output format_conv_ctrl; +wire [c_dw_si-1:0] viv_s0; +wire viv_s1; +wire viv_s2; +wire viv_s3; +wire viv_s4; +wire [2:0] viv_s5; +wire [15:0] viv_s6; +wire [1:0] viv_s7; +wire [1:0] viv_s8; +wire viv_s9; +wire viv_s10; +wire [1:0] viv_s11; +wire [13:0] viv_s12; +wire [13:0] viv_s13; +wire [13:0] viv_s14; +wire [13:0] viv_s15; +wire [13:0] viv_s16; +wire [13:0] viv_s17; +wire [13:0] viv_s18; +wire [13:0] viv_s19; +wire [13:0] viv_s20; +wire [13:0] viv_s21; +wire [13:0] viv_s22; +wire [13:0] viv_s23; +wire [13:0] viv_s24; +wire [31:0] viv_s25; + wire [ 15:0] viv_s26; + wire viv_s27; + wire viv_s28; + wire viv_s29; + wire viv_s30; + wire [(2*c_dw_do)-1:0] isp_data; + wire isp_val; + wire isp_h_end; + wire isp_v_end; + wire isp_cfg_upd; + wire viv_s31; + wire viv_s32; + wire viv_s33; + wire viv_s34; + wire [c_dw_si-1:0] viv_s35; + wire viv_s36; + wire viv_s37; + wire viv_s38; + wire viv_s39; + wire [c_dw_si-1:0] viv_s40; + wire viv_s41; + wire viv_s42; + wire viv_s43; + wire viv_s44; + wire [c_dw_si-1:0] viv_s45; + wire viv_s46; + wire viv_s47; + wire viv_s48; + wire [c_dw_si-1:0] viv_s49; + wire viv_s50; + wire viv_s51; + wire viv_s52; + wire viv_s53; + wire viv_s54; + wire viv_s55; + wire viv_s56; + wire [c_dw_si-1:0] viv_s57; + wire [c_ispfifo_aw-1:0] viv_s58; + wire [(2*c_dw_do)-1:0] viv_s59; + wire viv_s60; + wire viv_s61; + wire viv_s62; + wire viv_s63; + wire viv_s64; + wire viv_s65; + wire viv_s66; + wire [c_dw_si-1:0] viv_s67; + wire viv_s68; + wire viv_s69; + wire viv_s70; + wire viv_s71; + wire [(3*c_dw_si)-1:0] viv_s72; + wire viv_s73; + wire viv_s74; + wire viv_s75; + wire viv_s76; + wire [(3*c_dw_do)-1:0] viv_s77; + wire viv_s78; + wire viv_s79; + wire viv_s80; + wire viv_s81; + wire [(3*c_dw_do)-1:0] viv_s82; + wire viv_s83; + wire viv_s84; + wire viv_s85; + wire viv_s86; + wire [(2*c_dw_do)-1:0] viv_s87; + wire viv_s88; + wire viv_s89; + wire viv_s90; + wire viv_s91; + wire viv_s92; + wire viv_s93; + wire viv_s94; + wire viv_s95; + wire viv_s96; + wire viv_s97; + wire viv_s98; + wire [2:0] viv_s99; + wire viv_s100; + wire [7:0] viv_s101; + wire viv_s102; + wire [2:0] viv_s103; + wire [2:0] viv_s104; + wire viv_s105; + wire [1:0] viv_s106; + wire [1:0] viv_s107; + wire [1:0] viv_s108; + wire [1:0] viv_s109; + wire viv_s110; + wire viv_s111; + wire [14:0] viv_s112; + wire [13:0] viv_s113; + wire [14:0] viv_s114; + wire [13:0] viv_s115; + wire [5:0] viv_s116; + wire viv_s117 ; + wire viv_s118; + wire [4:0] viv_s119; + wire [4:0] viv_s120; + wire [4:0] viv_s121; + wire [4:0] viv_s122; + wire [9:0] viv_s123; + wire [9:0] viv_s124; + wire [9:0] viv_s125; + wire [9:0] viv_s126; + wire viv_s127; + wire [15:0] viv_s128; + wire [15:0] viv_s129; + wire [15:0] viv_s130; + wire [15:0] viv_s131; + wire viv_s132; + wire [c_dw_do-1:0] viv_s133; + wire [c_dw_do-1:0] viv_s134; + wire [c_dw_do-1:0] viv_s135; + wire [c_dw_do-1:0] viv_s136; + wire [c_dw_do-1:0] viv_s137; + wire [c_dw_do-1:0] viv_s138; + wire [c_dw_do-1:0] viv_s139; + wire [c_dw_do-1:0] viv_s140; + wire [c_dw_do-1:0] viv_s141; + wire [c_dw_do-1:0] viv_s142; + wire [c_dw_do-1:0] viv_s143; + wire [c_dw_do-1:0] viv_s144; + wire [c_dw_do-1:0] viv_s145; + wire [c_dw_do-1:0] viv_s146; + wire [c_dw_do-1:0] viv_s147; + wire [c_dw_do-1:0] viv_s148; + wire [c_dw_do-1:0] viv_s149; + wire viv_s150; + wire viv_s151; + wire [1:0] viv_s152; + wire [12:0] viv_s153; + wire [12:0] viv_s154; + wire [13:0] viv_s155; + wire [13:0] viv_s156; + wire [ 2:0] viv_s157; + wire [ 7:0] viv_s158; + wire [ 7:0] viv_s159; + wire [ 7:0] viv_s160; + wire [ 7:0] viv_s161; + wire [ 7:0] viv_s162; + wire [ 7:0] viv_s163; + wire [c_white_cnt-1:0] viv_s164; + wire [7:0] viv_s165; + wire [7:0] viv_s166; + wire [7:0] viv_s167; + wire viv_s168; + wire viv_s169; + wire viv_s170; + wire [ 8:0] viv_s171; + wire [ 8:0] viv_s172; + wire [ 8:0] viv_s173; + wire [ 8:0] viv_s174; + wire [ 8:0] viv_s175; + wire [ 8:0] viv_s176; + wire [ 8:0] viv_s177; + wire [ 8:0] viv_s178; + wire [ 8:0] viv_s179; + wire viv_s180; + wire viv_s181; + wire [10:0] viv_s182; + wire [10:0] viv_s183; + wire [10:0] viv_s184; + wire [10:0] viv_s185; + wire [10:0] viv_s186; + wire [10:0] viv_s187; + wire [10:0] viv_s188; + wire [10:0] viv_s189; + wire [10:0] viv_s190; + wire [c_dw_si-1:0] viv_s191; + wire [c_dw_si-1:0] viv_s192; + wire [c_dw_si-1:0] viv_s193; + wire [13:0] viv_s194; + wire [13:0] viv_s195; + wire [14:0] viv_s196; + wire [13:0] viv_s197; + wire [13:0] viv_s198; + wire [13:0] viv_s199; + wire [14:0] viv_s200; + wire [13:0] viv_s201; + wire [1:0] viv_s202; + wire [1:0] viv_s203; + wire viv_s204; + wire viv_s205; + wire viv_s206; + wire viv_s207; + wire viv_s208; + wire [c_irq_bw-1:0] viv_s209; + wire [c_irq_bw-1:0] viv_s210; + wire [c_irq_bw-1:0] viv_s211; + wire [c_irq_bw-1:0] viv_s212; + wire [c_irq_bw-1:0] viv_s213; + wire [c_irq_bw-1:0] viv_s214; + wire [c_isp_err_bw-1:0] viv_s215; + wire [c_isp_err_bw-1:0] viv_s216; + wire [c_isp_err_bw-1:0] viv_s217; + wire viv_s218; + wire viv_s219; + wire viv_s220; + wire [31:0] viv_s221; + wire [31:0] viv_s222; + wire [31:0] viv_s223; + wire viv_s224; + wire viv_s225; + wire raw_mode; + wire viv_s226; + wire viv_s227; + assign clk_isp_rgb_ram = viv_s227; + assign viv_s224 = (viv_s99[2:0] == 3'b011)| + (viv_s99[2:0] == 3'b101); + assign viv_s225 = (viv_s99[2:0] == 3'b001)| + (viv_s99[2:0] == 3'b010); + assign raw_mode = (viv_s99[2:0] == 3'b000)| + (viv_s99[2:0] == 3'b110)| + (viv_s99[2:0] == 3'b100); + assign viv_s226 = (viv_s99[2:0] == 3'b111); + assign viv_s205 = (viv_s225) ? viv_s53 : 1'b0; + assign viv_s206 = (viv_s224 & ~disable_isp) ? viv_s53 & raw_out_ack : 1'b0; + assign viv_s207 = (viv_s226) ? viv_s53 : 1'b0; + assign raw_out_data = {viv_s57,{16-c_dw_si{1'b0}}} ; + assign raw_out_h_end = viv_s55; + assign raw_out_v_end = viv_s56; + assign raw_out_val = viv_s53 & ~viv_s225 & ~viv_s226 & viv_s64 ; + assign raw_out_cfg_upd = raw_out_h_end & raw_out_v_end & viv_s95; + assign viv_s54 = (viv_s225) ? viv_s65 : + viv_s226 ? viv_s66 : + viv_s64 & raw_out_ack ; + assign viv_s208 = viv_s32 | viv_s93; + assign viv_s212 = {1'b0, + viv_s169, + 10'b0, + viv_s33, + viv_s34, + viv_s94, + viv_s168, + viv_s208, + pipeline_full, + 2'b0}; + assign isp_int_exp_end = viv_s214[18]; + assign isp_int_h_start = viv_s214[7]; + assign isp_int_v_start = viv_s214[6]; + assign isp_int_frame_in = viv_s214[5]; + assign isp_int_awb_done = viv_s214[4]; + assign isp_int_size_err = viv_s214[3]; + assign isp_int_dataloss = viv_s214[2]; + assign viv_s215 = {viv_s93, 1'b0, viv_s32}; + assign viv_s218 = cfg_val && ((12'h814 <= cfg_addr[11:0]) && (cfg_addr[11:0] <=12'h888)); + assign viv_s219 = cfg_val && ((12'h700 <= cfg_addr[11:0]) && (cfg_addr[11:0] <=12'h710)); + assign viv_s220 = cfg_val && ((12'h720 <= cfg_addr[11:0]) && (cfg_addr[11:0] <=12'h794)); +vsisp_isp_tpg_cfg u_isp_tpg_cfg( + .clk (clk ), + .rst_n (reset_clk_n ), + .tpg_en (viv_s4 ), + .img_num (viv_s5 ), + .frame_num (viv_s6 ), + .cfa_pat (viv_s7 ), + .color_depth (viv_s8 ), + .def_sync (viv_s9 ), + .max_sync (viv_s10 ), + .tpg_resolution (viv_s11 ), + .vtotal_in (viv_s12 ), + .htotal_in (viv_s13 ), + .v_act_in (viv_s14 ), + .h_act_in (viv_s15 ), + .fp_v_in (viv_s16 ), + .fp_h_in (viv_s17 ), + .bp_v_in (viv_s18 ), + .bp_h_in (viv_s19 ), + .vs_w_in (viv_s20 ), + .hs_w_in (viv_s21 ), + .line_gap_in (viv_s22 ), + .pix_gap_in (viv_s23 ), + .pix_gap_std_in (viv_s24 ), + .random_seed_in (viv_s25 ), + .cfa_out (viv_s26 ), + .vs_out (viv_s27 ), + .hs_out (viv_s28 ), + .vde_out (viv_s29 ), + .hde_out (viv_s30 )); +assign viv_s0 = viv_s4 ? viv_s26[15:16-c_dw_si] : s_data; +assign viv_s1 = viv_s4 ? viv_s28 : s_hsync; +assign viv_s2 = viv_s4 ? viv_s27 : s_vsync; +assign viv_s3 = viv_s4 ? (viv_s29 && viv_s30) : s_data_val; + vsisp_isp_inform u_isp_inform + ( + .clk (clk), + .reset_clk_n (reset_clk_n), + .soft_rst (soft_rst), + .s_data (viv_s0), + .s_hsync (viv_s1), + .s_vsync (viv_s2), + .s_data_val (viv_s3), + .s_data_ack (s_data_ack), + .out_bls_data (), + .out_bls_h_end (), + .out_bls_v_end (), + .out_bls_val (), + .inform_mux_val (viv_s38), + .inform_mux_ack (viv_s39), + .inform_mux_h_end(viv_s36), + .inform_mux_v_end(viv_s37), + .inform_mux_data (viv_s35), + .regs_hsync_pol (viv_s111), + .regs_vsync_pol (viv_s110), + .regs_acq_h_offs (viv_s112), + .regs_acq_v_offs (viv_s113), + .regs_acq_h_size (viv_s114), + .regs_acq_v_size (viv_s115), + .regs_bayer_pat (viv_s109), + .out_h_offs_shd (viv_s198), + .out_v_offs_shd (viv_s199), + .regs_input_pin_map (viv_s103), + .regs_input_selection(viv_s104), + .regs_field_selection(viv_s106), + .regs_field_inv (viv_s105), + .regs_isp_mode (viv_s99), + .regs_inform_enable (viv_s98), + .regs_cfg_upd (viv_s96), + .regs_gen_cfg_upd (viv_s95), + .bayer_pat_act (viv_s202), + .bayer_pat_diff (viv_s203), + .frame_in_irq (viv_s94), + .inform_en_shd (viv_s31), + .field (), + .in_size_err (viv_s32), + .h_start_edge (viv_s33), + .v_start_edge (viv_s34) + ); + vsisp_isp_outform #(c_dw_si) u_isp_outform + ( + .clk (clk), + .reset_clk_n (reset_clk_n), + .soft_rst (soft_rst), + .in_data (viv_s35 ), + .in_h_end (viv_s36 ), + .in_v_end (viv_s37 ), + .in_val (viv_s38 ), + .in_ack (viv_s39 ), + .outform_data (viv_s45), + .outform_h_end (viv_s46), + .outform_v_end (viv_s47), + .outform_val (viv_s48), + .outform_ack (viv_s204), + .regs_out_h_offs (viv_s194), + .regs_out_v_offs (viv_s195), + .regs_out_h_size (viv_s196), + .regs_out_v_size (viv_s197), + .regs_isp_mode (viv_s99), + .regs_cfg_upd (viv_s96), + .regs_gen_cfg_upd(viv_s95), + .isp_on_shd (1'b1), + .h_offs_shd (viv_s198), + .v_offs_shd (viv_s199), + .h_size_shd (viv_s200), + .v_size_shd (viv_s201), + .v_start_pos ( ), + .size_err (viv_s93) + ); + assign isp_fifo_addr[c_ispfifo_aw-1:0] = viv_s58[c_ispfifo_aw-1:0]; + vsisp_fifo #(c_dw_si, c_ispfifo_aw) u_fifo + ( + .clk (clk), + .reset_n (reset_clk_n), + .soft_rst (soft_rst), + .wr_val (viv_s48 ), + .wr_ack (viv_s204 ), + .wr_h_end (viv_s46 ), + .wr_v_end (viv_s47 ), + .wr_data (viv_s45 ), + .rd_val (viv_s53), + .rd_ack (viv_s54), + .rd_h_end (viv_s55), + .rd_v_end (viv_s56), + .rd_data (viv_s57), + .ram_cs_n (isp_fifo_cs_n), + .ram_we_n (isp_fifo_we_n), + .ram_addr (viv_s58), + .ram_wdata (isp_fifo_wdata), + .ram_rdata (isp_fifo_rdata) + ); +vsisp_GC_CG_MOD GC_CG_MOD_0( +.ck_in(clk), +.test(test_mode), +.enable(viv_s225), +.ck_out(clk_yuv_mode) +); +assign viv_s65 = 1; +assign viv_s62 = 0; +assign viv_s60 = 0; +assign viv_s61 = 0; +assign viv_s59 = 'b0; + vsisp_m4_clock_gating u_clock_gating_clk + ( + .per_clk_i (clk_not_gated), + .pdft_scan_mode_i(test_mode), + .gating_en_i (viv_s224 & isp_clk_en), + .clk_o (viv_s227) + ); + vsisp_isp_bls_v2 u_isp_bls_v2 + ( + .clk (viv_s227), + .reset_n (reset_clk_n), + .clk_cfg (clk_cfg), + .reset_cfg_n (reset_cfg_n), + .soft_rst (soft_rst), + .cfg_val (viv_s219), + .cfg_addr (cfg_addr[c_cfg_bls-1:2]), + .cfg_rd (cfg_rd), + .cfg_wdata (cfg_wdata), + .cfg_rdata (viv_s222), + .bayer_pat_diff(viv_s203), + .in_act_data (viv_s57), + .in_act_h_end (viv_s55), + .in_act_v_end (viv_s56), + .in_act_val (viv_s206), + .in_act_ack (viv_s64), + .out_data (viv_s67), + .out_h_end (viv_s69), + .out_v_end (viv_s70), + .out_val (viv_s68), + .out_ack (viv_s71) + ); +wire [c_dw_si-1:0] viv_s228; + vsisp_isp_digi_gain #(.c_dw_si(c_dw_si)) u_digi_gain( + .clk (viv_s227), + .reset_n (reset_clk_n), + .soft_rst (soft_rst), + .regs_bayer_pat (viv_s202), + .in_data (viv_s67), + .in_h_end (viv_s69), + .in_v_end (viv_s70), + .in_val (viv_s68), + .in_ack (viv_s71), + .in_vsync (viv_s34), + .out_vsync (), + .out_h_st (), + .out_v_st (), + .out_data (viv_s228), + .out_h_end (dgain_h_end), + .out_v_end (dgain_v_end), + .out_val (dgain_val), + .out_bayer_ptn (), + .out_ack (dgain_ack), + .gain_r (viv_s128), + .gain_gr (viv_s129), + .gain_gb (viv_s130), + .gain_b (viv_s131), + .regs_dgain_enable (viv_s127) +); + vsisp_isp_filt u_isp_filt + ( + .clk (viv_s227), + .reset_n (reset_clk_n), + .clk_cfg (clk_cfg), + .reset_cfg_n (reset_cfg_n), + .soft_rst (soft_rst), + .cfg_val (viv_s218), + .cfg_addr (cfg_addr[c_cfg_filt-1:2]), + .cfg_rd (cfg_rd), + .cfg_wdata (cfg_wdata), + .cfg_rdata (viv_s221), + .in_data (viv_s228), + .in_h_end (dgain_h_end), + .in_v_end (dgain_v_end), + .in_val (dgain_val), + .in_ack (dgain_ack), + .regs_demosaic_th(viv_s101), + .regs_dem_bypass (viv_s102), + .regs_bayer_pat (viv_s202), + .regs_cfg_upd (viv_s96), + .regs_gen_cfg_upd(viv_s95), + .filt_data (viv_s72), + .filt_h_end (viv_s73), + .filt_v_end (viv_s74), + .filt_val (viv_s75), + .filt_ack (viv_s76), + .meas_val (), + .meas_h_end (), + .meas_v_end (), + .meas_data_t (), + .meas_data_m (), + .meas_data_b (), + .adr (ispram_addr), + .we_n (ispram_we_n), + .cs_n (ispram_cs_n), + .wr_data (ispram_wdata), + .rd_data (ispram_rdata) + ); + wire [(3*c_dw_si)-1:0] viv_s229; + wire viv_s230; + wire viv_s231; + wire viv_s232; + wire viv_s233; + vsisp_isp_cross_talk u_isp_cross_talk + ( + .clk (viv_s227), + .reset_n (reset_clk_n), + .soft_rst (soft_rst), + .in_data (viv_s72), + .in_h_end (viv_s73), + .in_v_end (viv_s74), + .in_val (viv_s75), + .in_ack (viv_s76), + .out_data (viv_s229), + .out_h_end (viv_s230), + .out_v_end (viv_s231), + .out_val (viv_s232), + .out_ack (viv_s233), + .coeff0 (viv_s182), + .coeff1 (viv_s183), + .coeff2 (viv_s184), + .coeff3 (viv_s185), + .coeff4 (viv_s186), + .coeff5 (viv_s187), + .coeff6 (viv_s188), + .coeff7 (viv_s189), + .coeff8 (viv_s190), + .offset_r (viv_s191), + .offset_g (viv_s192), + .offset_b (viv_s193) + ); + wire [3*c_dw_si-1:0] viv_s234 = viv_s117 ? viv_s72 : viv_s229; + wire viv_s235 = viv_s117 ? viv_s75 & viv_s76 : viv_s232 & viv_s233; + wire viv_s236 = viv_s117 ? viv_s73 : viv_s230; + wire viv_s237 = viv_s117 ? viv_s74 : viv_s231; + vsisp_isp_gamma_out u_isp_gamma_out + ( + .clk (viv_s227), + .reset_n (reset_clk_n), + .soft_rst (soft_rst), + .enable (viv_s97), + .equ_segm (viv_s132), + .y0 (viv_s133), + .y1 (viv_s134), + .y2 (viv_s135), + .y3 (viv_s136), + .y4 (viv_s137), + .y5 (viv_s138), + .y6 (viv_s139), + .y7 (viv_s140), + .y8 (viv_s141), + .y9 (viv_s142), + .y10 (viv_s143), + .y11 (viv_s144), + .y12 (viv_s145), + .y13 (viv_s146), + .y14 (viv_s147), + .y15 (viv_s148), + .y16 (viv_s149), + .in_data (viv_s229 ), + .in_h_end (viv_s230 ), + .in_v_end (viv_s231 ), + .in_val (viv_s232 ), + .in_ack (viv_s233 ), + .out_data (viv_s82), + .out_h_end(viv_s83), + .out_v_end(viv_s84), + .out_val (viv_s85), + .out_ack (viv_s86) + ); + wire [23:0] viv_s238; + wire [7:0] viv_s239; + wire viv_s240; + wire viv_s241; + wire viv_s242; + wire viv_s243; + assign viv_s243 = 1'b1; + vsisp_isp_csm_fix u_isp_csm_fix + ( + .clk (viv_s227), + .reset_n (reset_clk_n), + .soft_rst (soft_rst), + .regs_awb_meas_mode(viv_s150), + .exp_alt_mode (viv_s170), + .in_data (viv_s234), + .in_h_end (viv_s236), + .in_v_end (viv_s237), + .in_val (viv_s235), + .out_data (viv_s238), + .out_y_exp (viv_s239), + .out_h_end (viv_s240), + .out_v_end (viv_s241), + .out_val (viv_s242), + .out_ack (viv_s243) + ); + vsisp_isp_exp u_isp_exp + ( + .clk (viv_s227), + .reset_n (reset_clk_n), + .soft_rst (soft_rst), + .clk_cfg (clk_cfg), + .reset_cfg_n (reset_cfg_n), + .regs_gen_cfg_upd (viv_s95), + .regs_cfg_upd (viv_s96), + .cfg_val_i (viv_s220), + .cfg_addr_i ({2'b0,cfg_addr[11:2]}), + .cfg_rd_i (cfg_rd), + .cfg_wdata_i (cfg_wdata), + .cfg_rdata_o (viv_s223), + .y_i (viv_s239), + .h_end_i (viv_s240), + .v_end_i (viv_s241), + .val_i (viv_s242), + .ack_i (viv_s243), + .exp_alt_mode_o (viv_s170), + .measure_complete (viv_s169) + ); + vsisp_isp_awb_meas u_isp_awb_meas_old + ( + .clk (viv_s227), + .reset_n (reset_clk_n), + .soft_rst (soft_rst), + .meas_data (viv_s238), + .meas_h_end (viv_s240), + .meas_v_end (viv_s241), + .meas_val (viv_s242), + .meas_ack (viv_s243), + .mean_y__g (viv_s165), + .mean_cb__b (viv_s166), + .mean_cr__r (viv_s167), + .white_cnt (viv_s164), + .awb_done (viv_s168), + .regs_awb_enable (regs_awb_enable), + .regs_awb_meas_mode (viv_s150), + .regs_awb_max_en (viv_s151), + .regs_awb_mode (viv_s152), + .regs_awb_h_offs (viv_s153), + .regs_awb_v_offs (viv_s154), + .regs_awb_h_size (viv_s155), + .regs_awb_v_size (viv_s156), + .regs_awb_frames (viv_s157), + .regs_awb_ref_cb__max_b(viv_s158), + .regs_awb_ref_cr__max_r(viv_s159), + .regs_awb_max_y (viv_s160), + .regs_awb_min_y__max_g (viv_s161), + .regs_awb_min_c (viv_s162), + .regs_awb_max_csum (viv_s163) + ); + vsisp_isp_csm u_isp_csm + ( + .clk (viv_s227), + .reset_n (reset_clk_n), + .soft_rst (soft_rst), + .in_data (viv_s82), + .in_h_end (viv_s83), + .in_v_end (viv_s84), + .in_val (viv_s85), + .in_ack (viv_s86), + .out_data (viv_s77), + .out_h_end(viv_s79), + .out_v_end(viv_s80), + .out_val (viv_s81), + .out_ack (viv_s78), + .coeff0 (viv_s171), + .coeff1 (viv_s172), + .coeff2 (viv_s173), + .coeff3 (viv_s174), + .coeff4 (viv_s175), + .coeff5 (viv_s176), + .coeff6 (viv_s177), + .coeff7 (viv_s178), + .coeff8 (viv_s179), + .y_range (viv_s180), + .c_range (viv_s181) + ); + vsisp_isp_422_conv u_isp_422_conv + ( + .clk (viv_s227), + .reset_n (reset_clk_n), + .soft_rst (soft_rst), + .in_data (viv_s77), + .in_h_end (viv_s79), + .in_v_end (viv_s80), + .in_val (viv_s81), + .in_ack (viv_s78), + .out_data (viv_s87), + .out_h_end (viv_s89), + .out_v_end (viv_s90), + .out_val (viv_s91), + .out_ack (viv_s88), + .cb_cr_swap (viv_s63), + .regs_method(viv_s108) + ); + vsisp_isp_rgb_yuv_sel u_isp_rgb_yuv_sel + ( + .if_sel (viv_s225), + .yuv_dma_sel (viv_s226), + .s2_val (viv_s207), + .s2_data ({viv_s57[c_dw_si-1:c_dw_si-c_dw_do],{c_dw_do{1'b0}}}), + .s2_h_end (viv_s55), + .s2_v_end (viv_s56), + .s2_ack (viv_s66), + .s1_val (viv_s62), + .s1_data (viv_s59), + .s1_h_end (viv_s60), + .s1_v_end (viv_s61), + .s1_ack (viv_s92), + .s0_val (viv_s91), + .s0_data (viv_s87), + .s0_h_end (viv_s89), + .s0_v_end (viv_s90), + .s0_ack (viv_s88), + .out_val (isp_val), + .out_data (isp_data), + .out_h_end (isp_h_end), + .out_v_end (isp_v_end), + .out_ack (isp_ack) + ); + wire viv_s244 = viv_s96 || viv_s95 && isp_val && isp_ack && isp_h_end && isp_v_end; + wire viv_s245 = viv_s96 || viv_s95 && raw_out_val && raw_out_ack && raw_out_h_end && raw_out_v_end; + reg viv_s246; + always@(posedge clk or negedge reset_clk_n) begin + if(~reset_clk_n) begin + viv_s246 <= 1'b0; + end else if(viv_s244) begin + viv_s246 <= viv_s194[0]; + end + end + reg viv_s247; + always@(posedge clk or negedge reset_clk_n) begin + if(~reset_clk_n) begin + viv_s247 <= 1'b0; + end else if(viv_s244) begin + viv_s247 <= viv_s194[0]; + end + end + assign viv_s63 = raw_mode ? viv_s247 : viv_s246; + assign isp_cfg_upd = viv_s95 & isp_h_end & isp_v_end; + vsisp_isp_regs u_isp_regs + ( + .clk_cfg(clk_cfg), + .reset_cfg_n(reset_cfg_n), + .cfg_addr(cfg_addr), + .cfg_wdata(cfg_wdata), + .cfg_rdata(cfg_rdata), + .cfg_rd(cfg_rd), + .cfg_val(cfg_val), + .cfg_ack(cfg_ack), + .regs_gen_cfg_upd(viv_s95), + .regs_cfg_upd(viv_s96), + .regs_isp_mode(viv_s99), + .regs_isp_enable(viv_s100), + .regs_disable_isp_clk(regs_disable_isp_clk), + .regs_awb_enable (regs_awb_enable), + .regs_statistic_3a_sel (viv_s117 ), + .regs_inform_enable(viv_s98), + .regs_input_selection(viv_s104), + .regs_input_pin_map(viv_s103), + .regs_field_inv(viv_s105), + .regs_field_selection(viv_s106), + .regs_ccir_seq(viv_s107), + .regs_conv_422(viv_s108), + .regs_bayer_pat(viv_s109), + .regs_vsync_pol(viv_s110), + .regs_hsync_pol(viv_s111), + .regs_sample_edge(regs_sample_edge), + .regs_acq_h_offs(viv_s112), + .regs_acq_v_offs(viv_s113), + .regs_acq_h_size(viv_s114), + .regs_acq_v_size(viv_s115), + .regs_out_h_offs(viv_s194), + .regs_out_v_offs(viv_s195), + .regs_out_h_size(viv_s196), + .regs_out_v_size(viv_s197), + .out_h_offs_shd(viv_s198), + .out_v_offs_shd(viv_s199), + .out_h_size_shd(viv_s200), + .out_v_size_shd(viv_s201), + .regs_dgain_enable(viv_s127), + .regs_dgain_r(viv_s128), + .regs_dgain_gr(viv_s129), + .regs_dgain_gb(viv_s130), + .regs_dgain_b(viv_s131), + .regs_demosaic_bypass(viv_s102), + .regs_demosaic_th(viv_s101), + .regs_gamma_out_enable(viv_s97), + .regs_equ_segm(viv_s132), + .regs_gamma_out_y0(viv_s133), + .regs_gamma_out_y1(viv_s134), + .regs_gamma_out_y2(viv_s135), + .regs_gamma_out_y3(viv_s136), + .regs_gamma_out_y4(viv_s137), + .regs_gamma_out_y5(viv_s138), + .regs_gamma_out_y6(viv_s139), + .regs_gamma_out_y7(viv_s140), + .regs_gamma_out_y8(viv_s141), + .regs_gamma_out_y9(viv_s142), + .regs_gamma_out_y10(viv_s143), + .regs_gamma_out_y11(viv_s144), + .regs_gamma_out_y12(viv_s145), + .regs_gamma_out_y13(viv_s146), + .regs_gamma_out_y14(viv_s147), + .regs_gamma_out_y15(viv_s148), + .regs_gamma_out_y16(viv_s149), + .regs_awb_meas_mode (viv_s150), + .regs_awb_max_en (viv_s151), + .regs_awb_mode (viv_s152), + .regs_awb_h_offs (viv_s153), + .regs_awb_v_offs (viv_s154), + .regs_awb_h_size (viv_s155), + .regs_awb_v_size (viv_s156), + .regs_awb_frames (viv_s157), + .regs_awb_ref_cb__max_b(viv_s158), + .regs_awb_ref_cr__max_r(viv_s159), + .regs_awb_max_y (viv_s160), + .regs_awb_min_y__max_g (viv_s161), + .regs_awb_min_c (viv_s162), + .regs_awb_max_csum (viv_s163), + .awb_white_cnt (viv_s164), + .awb_mean_y__g (viv_s165), + .awb_mean_cb__b (viv_s166), + .awb_mean_cr__r (viv_s167), + .regs_cc_coeff0(viv_s171), + .regs_cc_coeff1(viv_s172), + .regs_cc_coeff2(viv_s173), + .regs_cc_coeff3(viv_s174), + .regs_cc_coeff4(viv_s175), + .regs_cc_coeff5(viv_s176), + .regs_cc_coeff6(viv_s177), + .regs_cc_coeff7(viv_s178), + .regs_cc_coeff8(viv_s179), + .regs_csm_y_range(viv_s180), + .regs_csm_c_range(viv_s181), + .format_conv_ctrl(format_conv_ctrl), + .regs_ct_coeff0 (viv_s182), + .regs_ct_coeff1 (viv_s183), + .regs_ct_coeff2 (viv_s184), + .regs_ct_coeff3 (viv_s185), + .regs_ct_coeff4 (viv_s186), + .regs_ct_coeff5 (viv_s187), + .regs_ct_coeff6 (viv_s188), + .regs_ct_coeff7 (viv_s189), + .regs_ct_coeff8 (viv_s190), + .regs_ct_offset_r (viv_s191), + .regs_ct_offset_g (viv_s192), + .regs_ct_offset_b (viv_s193), + .regs_isp_ris(viv_s213), + .regs_isp_mis(viv_s214), + .regs_isp_imsc(viv_s209), + .regs_isp_isr(viv_s210), + .regs_isp_icr(viv_s211), + .regs_err_clr(viv_s217), + .isp_err_status(viv_s216), + .cfg_filt_rdata(viv_s221), + .cfg_bls_rdata(viv_s222), + .cfg_exp_rdata(viv_s223), + .tpg_en ( viv_s4 ), + .img_num ( viv_s5 ), + .frm_num ( viv_s6 ), + .cfa_pat ( viv_s7 ), + .color_depth ( viv_s8 ), + .def_sync ( viv_s9 ), + .max_sync ( viv_s10 ), + .tpg_resolution ( viv_s11 ), + .vtotal_in ( viv_s12 ), + .htotal_in ( viv_s13 ), + .v_act_in ( viv_s14 ), + .h_act_in ( viv_s15 ), + .fp_v_in ( viv_s16 ), + .fp_h_in ( viv_s17 ), + .bp_v_in ( viv_s18 ), + .bp_h_in ( viv_s19 ), + .vs_w_in ( viv_s20 ), + .hs_w_in ( viv_s21 ), + .line_gap_in ( viv_s22 ), + .pix_gap_in ( viv_s23 ), + .pix_gap_std_in ( viv_s24 ), + .random_seed_in ( viv_s25 ), + .clk (clk_not_gated ), + .rst_clk_n (reset_clk_n ), + .frame_end_dgain (dgain_val & dgain_ack & dgain_h_end & dgain_v_end) + ); + vsisp_isp_irq_handler u_isp_irq_handler + ( + .clk (clk), + .reset_n (reset_clk_n), + .soft_rst (soft_rst), + .isp_err_status_set (viv_s215), + .regs_err_clr (viv_s217), + .isp_err_status (viv_s216), + .irq_set (viv_s212), + .regs_isp_ris (viv_s213), + .regs_isp_mis (viv_s214), + .regs_isp_imsc (viv_s209), + .regs_isp_icr (viv_s211), + .regs_isp_isr (viv_s210)); +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_422_conv.v b/ispyocto/rtl/ispyocto/vsisp_isp_422_conv.v new file mode 100644 index 0000000..f071f93 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_isp_422_conv.v
@@ -0,0 +1,229 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_isp_422_conv ( + clk, + reset_n, + soft_rst, + in_data, + in_h_end, + in_v_end, + in_val, + in_ack, + out_data, + out_h_end, + out_v_end, + out_val, + out_ack, + cb_cr_swap, + regs_method + ); +`include "vsisp_isp.vh" +input clk; +input reset_n; +input soft_rst; +input [(3*c_dw_do)-1:0] in_data; +input in_h_end; +input in_v_end; +input in_val; +output in_ack; +output [(2*c_dw_do)-1:0] out_data; +output out_h_end; +output out_v_end; +output out_val; +input out_ack; +input cb_cr_swap; +input [1:0] regs_method; +reg [(3*c_dw_do)-1:0] viv_s0; +reg viv_s1; +reg viv_s2; +reg viv_s3; +reg viv_s4; +reg [c_dw_do-1:0] viv_s5; +reg [c_dw_do-1:0] viv_s6; +reg viv_s7; +reg viv_s8; +reg viv_s9; +wire viv_s10; +wire viv_s11; +reg viv_s12; +reg viv_s13; +reg viv_s14; +wire viv_s15; +wire viv_s16; +wire viv_s17; +wire viv_s18; +wire viv_s19; +wire viv_s20; +wire viv_s21; +wire viv_s22; +wire viv_s23; +wire in_ack; +wire viv_s24; +wire [c_dw_do-1:0] viv_s25; +wire [c_dw_do-1:0] viv_s26; +wire [c_dw_do-1:0] viv_s27; +wire [c_dw_do-1:0] viv_s28; +wire [c_dw_do-1:0] viv_s29; +wire [c_dw_do-1:0] viv_s30; +wire [c_dw_do-1:0] viv_s31; +reg [c_dw_do-1:0] viv_s32; +reg [c_dw_do-1:0] viv_s33; +reg [c_dw_do-1:0] viv_s34; +wire [c_dw_do+2:0] viv_s35; +wire [c_dw_do-1:0] viv_s36; +reg [c_dw_do:0] viv_s37; +reg [c_dw_do+1:0] viv_s38; +reg [c_dw_do:0] viv_s39; +assign viv_s25 = in_data[(2*c_dw_do)-1:c_dw_do]; +assign viv_s26 = in_data[c_dw_do-1:0]; +assign viv_s27 = viv_s0[(3*c_dw_do)-1:2*c_dw_do]; +assign viv_s28 = viv_s0[(2*c_dw_do)-1:c_dw_do]; +assign viv_s30 = viv_s0[c_dw_do-1:0]; +assign viv_s29 = viv_s33; +assign viv_s31 = viv_s33; +assign viv_s15 = (viv_s11 | viv_s1); +assign viv_s16 = viv_s15 & (viv_s12 | viv_s3); +assign viv_s19 = !viv_s12 | (viv_s24 & viv_s15); +assign viv_s20 = !viv_s13 | (out_ack & viv_s16); +assign viv_s24 = !viv_s13 | out_ack; +assign in_ack = (!viv_s12 | viv_s24) & viv_s9; +assign viv_s35 = viv_s37 + {1'b0, viv_s38} + viv_s39; +assign viv_s36 = viv_s35[c_dw_do+2:3]; +assign viv_s11 = in_val & viv_s9; +assign viv_s21 = (!viv_s12 | viv_s24) & viv_s11; +assign viv_s22 = in_h_end & in_val & in_ack; +assign viv_s23 = viv_s3 & viv_s18 & out_ack; + always @(*) begin + case (regs_method) + 2'b01: begin + viv_s32 = viv_s28; + if (viv_s8) begin + viv_s37 = {viv_s25, 1'b1}; + viv_s38 = {viv_s28, 2'b10}; + if (viv_s13) viv_s39 = {viv_s29, 1'b1}; + else viv_s39 = {viv_s28, 1'b1}; + end else begin + if (~viv_s1) viv_s37 = {viv_s26, 1'b1}; + else viv_s37 = {viv_s30, 1'b1}; + viv_s38 = {viv_s30, 2'b10}; + if (viv_s13) viv_s39 = {viv_s34, 1'b1}; + else viv_s39 = {viv_s30, 1'b1}; + end + end + 2'b10: begin + viv_s32 = viv_s28; + if (viv_s8) begin + viv_s37 = {viv_s25, 1'b1}; + viv_s38 = {viv_s28, 2'b10}; + viv_s39 = {viv_s25, 1'b1}; + end else begin + viv_s37 = {viv_s34, 1'b1}; + viv_s38 = {viv_s30, 2'b10}; + viv_s39 = {viv_s34, 1'b1}; + end + end + default: begin + if (viv_s8) begin + if (viv_s13) + viv_s32 = viv_s34; + else + viv_s32 = viv_s30; + viv_s37 = {viv_s25, 1'b1}; + viv_s38 = {viv_s28, 2'b10}; + if (viv_s13) viv_s39 = {viv_s29, 1'b1}; + else viv_s39 = {viv_s28, 1'b1}; + end else begin + viv_s32 = viv_s28; + viv_s37 = {viv_s30, 1'b1}; + if (viv_s13) + viv_s38 = {viv_s34, 2'b10}; + else + viv_s38 = {viv_s30, 2'b10}; + if (viv_s14) + viv_s39 = {viv_s31, 1'b1}; + else if (viv_s13) + viv_s39 = {viv_s34, 1'b1}; + else + viv_s39 = {viv_s30, 1'b1}; + end + end + endcase + end +assign viv_s10 = !viv_s7 & !in_h_end; +always @(posedge clk or negedge reset_n) begin + if (reset_n == 1'b0) begin + viv_s12 <= 1'b0; + viv_s13 <= 1'b0; + viv_s14 <= 1'b0; + viv_s7 <= 1'b0; + viv_s8 <= 1'b0; + viv_s9 <= 1'b1; + viv_s0 <= {3*c_dw_do{1'b0}}; + viv_s1 <= 1'b0; + viv_s2 <= 1'b0; + viv_s33 <= {c_dw_do{1'b0}}; + viv_s34 <= {c_dw_do{1'b0}}; + viv_s5 <= {c_dw_do{1'b0}}; + viv_s6 <= {c_dw_do{1'b0}}; + viv_s3 <= 1'b0; + viv_s4 <= 1'b0; + end else begin + if (soft_rst) begin + viv_s12 <= 1'b0; + viv_s13 <= 1'b0; + viv_s14 <= 1'b0; + viv_s7 <= 1'b0; + viv_s8 <= 1'b0; + viv_s9 <= 1'b1; + end else begin + if (viv_s19) viv_s12 <= viv_s11; + if (viv_s20) viv_s13 <= viv_s17; + if (viv_s20) viv_s14 <= viv_s13; + if (in_ack & in_val) viv_s7 <= viv_s10; + if (in_ack & in_val) viv_s8 <= viv_s10 ^ cb_cr_swap; + if (viv_s22) viv_s9 <= 1'b0; + else if (viv_s23) viv_s9 <= 1'b1; + end + if (viv_s21) begin + viv_s0 <= in_data; + viv_s1 <= in_h_end; + viv_s2 <= in_v_end; + end + if (viv_s20) begin + viv_s33 <= viv_s32; + viv_s34 <= viv_s30; + viv_s5 <= viv_s27; + viv_s6 <= viv_s36; + viv_s3 <= viv_s1; + viv_s4 <= viv_s2; + end + end +end +assign viv_s17 = viv_s12 & (viv_s11 | viv_s1); +assign viv_s18 = viv_s13 & (viv_s17 | viv_s3); +assign out_h_end = viv_s3 & viv_s18; +assign out_v_end = viv_s4 & viv_s18; +assign out_data = {viv_s5, viv_s6}; +assign out_val = viv_s18; +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_awb_acc.v b/ispyocto/rtl/ispyocto/vsisp_isp_awb_acc.v new file mode 100644 index 0000000..da6c029 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_isp_awb_acc.v
@@ -0,0 +1,99 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_isp_awb_acc ( + clk, + reset_n, + soft_rst, + in_data, + in_val, + meas_end, + acc_data_y, + acc_data_cb, + acc_data_cr, + acc_cnt, + acc_val); +`include "vsisp_isp.vh" +input clk; +input reset_n; +input soft_rst; +input [23:0] in_data; +input in_val; +input meas_end; +output [c_awb_acc_width-1:0] acc_data_y; +output [c_awb_acc_width-1:0] acc_data_cb; +output [c_awb_acc_width-1:0] acc_data_cr; +output [c_white_cnt-1:0] acc_cnt; +output acc_val; +reg [c_awb_acc_width-1:0] acc_data_y; +reg [c_awb_acc_width-1:0] acc_data_cb; +reg [c_awb_acc_width-1:0] acc_data_cr; +reg [c_white_cnt-1:0] acc_cnt; +reg acc_val; +wire [c_awb_acc_width:0] viv_s0; +wire [c_awb_acc_width:0] viv_s1; +wire [c_awb_acc_width:0] viv_s2; +assign viv_s0 = {1'b0,acc_data_y } + in_data[23:16]; +assign viv_s1 = {1'b0,acc_data_cb} + in_data[15:8]; +assign viv_s2 = {1'b0,acc_data_cr} + in_data[7:0]; + always @(posedge clk or negedge reset_n) begin + if (reset_n == 1'b0) begin + acc_data_y <= {c_awb_acc_width{1'b0}}; + acc_data_cb <= {c_awb_acc_width{1'b0}}; + acc_data_cr <= {c_awb_acc_width{1'b0}}; + acc_cnt <= {c_white_cnt{1'b0}}; + acc_val <= 1'b0; + end else begin + if (soft_rst == 1'b1) begin + acc_data_y <= {c_awb_acc_width{1'b0}}; + acc_data_cb <= {c_awb_acc_width{1'b0}}; + acc_data_cr <= {c_awb_acc_width{1'b0}}; + acc_cnt <= {c_white_cnt{1'b0}}; + acc_val <= 1'b0; + end else begin + if (meas_end) begin + acc_cnt <= acc_cnt; + acc_val <= 1'b1; + end else begin + acc_val <= 1'b0; + if (acc_val) begin + acc_data_y <= {c_awb_acc_width{1'b0}}; + acc_data_cb <= {c_awb_acc_width{1'b0}}; + acc_data_cr <= {c_awb_acc_width{1'b0}}; + acc_cnt <= {c_white_cnt{1'b0}}; + end else begin + if (in_val) begin + acc_data_y <= viv_s0[c_awb_acc_width] ? {c_awb_acc_width{1'b1}} : + viv_s0[c_awb_acc_width-1:0]; + acc_data_cb <= viv_s1[c_awb_acc_width] ? {c_awb_acc_width{1'b1}} : + viv_s1[c_awb_acc_width-1:0]; + acc_data_cr <= viv_s2[c_awb_acc_width] ? {c_awb_acc_width{1'b1}} : + viv_s2[c_awb_acc_width-1:0]; + acc_cnt <= acc_cnt + 1; + end + end + end + end + end + end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_awb_div.v b/ispyocto/rtl/ispyocto/vsisp_isp_awb_div.v new file mode 100644 index 0000000..e4e1897 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_isp_awb_div.v
@@ -0,0 +1,114 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_isp_awb_div + ( + clk, + reset_n, + soft_rst, + in_data, + in_div, + in_val, + out_data, + out_val, + out_div_zero, + out_div, + out_ack); + parameter c_dw_17 = 35; + parameter c_dw_9 = 27; + parameter c_cw_5 = 6; + input clk; + input reset_n; + input soft_rst; + input [c_dw_17-1:0] in_data; + input [c_dw_9-1:0] in_div; + input in_val; + output [c_dw_17-1:0] out_data; + output out_val; + output out_div_zero; + output [c_dw_9-1:0] out_div; + input out_ack; + reg viv_s0; + reg out_val; + reg out_div_zero; + reg [c_dw_17-1:0] out_data; + reg [c_dw_9-1:0] out_div; + reg [c_dw_9:0] viv_s1; + reg [c_cw_5-1:0] viv_s2; + wire [c_dw_9+1:0] viv_s3; + wire viv_s4; + assign viv_s3 = {1'b0, viv_s1} - {2'b0, out_div}; + assign viv_s4 = (viv_s0 && in_val); + always @(posedge clk or negedge reset_n) begin + if (reset_n == 1'b0) begin + viv_s0 <= 1'b0; + out_val <= 1'b0; + viv_s2 <= {c_cw_5{1'b0}}; + viv_s1 <= {c_dw_9+1{1'b0}}; + out_data <= {c_dw_17{1'b0}}; + out_div <= {c_dw_9{1'b0}}; + out_div_zero <= 1'b0; + end else begin + if (soft_rst == 1'b1) begin + viv_s0 <= 1'b0; + out_val <= 1'b0; + viv_s2 <= {c_cw_5{1'b0}}; + out_div_zero <= 1'b0; + end else begin + if (|viv_s2) begin + if (viv_s3[c_dw_9+1]) begin + out_data <= {out_data[c_dw_17-2:0], 1'b0}; + viv_s1 <= {viv_s1[c_dw_9-1:0], out_data[c_dw_17-1]}; + end else begin + out_data <= {out_data[c_dw_17-2:0], 1'b1}; + viv_s1 <= {viv_s3[c_dw_9-1:0], out_data[c_dw_17-1]}; + end + viv_s2 <= viv_s2 - {{c_cw_5-1{1'b0}}, 1'b1}; + if (viv_s2 == {{c_cw_5-1{1'b0}}, 1'b1}) begin + out_val <= 1'b1; + end + end else begin + if (out_ack) + out_div_zero <= 1'b0; + else if (viv_s4) begin + out_div_zero <= (in_div == {c_dw_9{1'b0}}); + end + if (out_ack) begin + out_val <= 1'b0; + end + if (viv_s4) begin + viv_s0 <= 1'b0; + viv_s2 <= c_dw_17; + out_div <= in_div; + out_data <= {in_data[c_dw_17-2:0], 1'b0}; + viv_s1 <= {{c_dw_9{1'b0}}, in_data[c_dw_17-1]}; + end else begin + if (!out_val) begin + viv_s0 <= 1'b1; + end + end + end + end + end + end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_awb_meas.v b/ispyocto/rtl/ispyocto/vsisp_isp_awb_meas.v new file mode 100644 index 0000000..9160216 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_isp_awb_meas.v
@@ -0,0 +1,222 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_isp_awb_meas ( + clk, + reset_n, + soft_rst, + meas_data, + meas_h_end, + meas_v_end, + meas_val, + meas_ack, + mean_y__g, + mean_cb__b, + mean_cr__r, + white_cnt, + awb_done, + regs_awb_enable, + regs_awb_meas_mode, + regs_awb_max_en, + regs_awb_mode, + regs_awb_h_offs, + regs_awb_v_offs, + regs_awb_h_size, + regs_awb_v_size, + regs_awb_frames, + regs_awb_ref_cb__max_b, + regs_awb_ref_cr__max_r, + regs_awb_max_y, + regs_awb_min_y__max_g, + regs_awb_min_c, + regs_awb_max_csum); +`include "vsisp_isp.vh" +input clk; +input reset_n; +input soft_rst; +input [23:0] meas_data; +input meas_h_end; +input meas_v_end; +input meas_val; +input meas_ack; +output [7:0] mean_y__g; +output [7:0] mean_cb__b; +output [7:0] mean_cr__r; +output [c_white_cnt-1:0] white_cnt; +output awb_done; +input regs_awb_enable; +input regs_awb_meas_mode; +input regs_awb_max_en; +input [1:0] regs_awb_mode; +input [12:0] regs_awb_h_offs; +input [12:0] regs_awb_v_offs; +input [13:0] regs_awb_h_size; +input [13:0] regs_awb_v_size; +input [ 2:0] regs_awb_frames; +input [ 7:0] regs_awb_ref_cb__max_b; +input [ 7:0] regs_awb_ref_cr__max_r; +input [ 7:0] regs_awb_max_y; +input [ 7:0] regs_awb_min_y__max_g; +input [ 7:0] regs_awb_min_c; +input [ 7:0] regs_awb_max_csum; +reg [7:0] mean_y__g; +reg [7:0] mean_cb__b; +reg [7:0] mean_cr__r; +reg [c_white_cnt-1:0] white_cnt; +reg viv_s0; +reg viv_s1; +reg viv_s2; +reg awb_done; +wire viv_s3; +wire viv_s4; +wire viv_s5; +wire [c_awb_acc_width-1:0] viv_s6; +wire [c_awb_acc_width-1:0] viv_s7; +wire [c_awb_acc_width-1:0] viv_s8; +wire [c_white_cnt-1:0] viv_s9; +wire viv_s10; +wire [c_awb_acc_width-1:0] viv_s11; +wire [c_awb_acc_width-1:0] viv_s12; +wire [c_awb_acc_width-1:0] viv_s13; +wire viv_s14; +wire viv_s15; +wire [c_white_cnt-1:0] viv_s16; +wire viv_s17; +wire viv_s18; +wire [c_white_cnt-1:0] viv_s19; +wire viv_s20; +wire viv_s21; +wire [c_white_cnt-1:0] viv_s22; +always @(posedge clk or negedge reset_n) begin + if (reset_n == 1'b0) begin + mean_y__g <= 8'd0; + mean_cb__b <= 8'd0; + mean_cr__r <= 8'd0; + white_cnt <= {c_white_cnt{1'b0}}; + viv_s0 <= 1'b0; + viv_s2 <= 1'b0; + viv_s1 <= 1'b0; + awb_done <= 1'b0; + end else begin + if (soft_rst == 1'b1) begin + viv_s0 <= 1'b0; + viv_s1 <= 1'b0; + awb_done <= 1'b0; + end else begin + viv_s1 <= viv_s0; + awb_done <= viv_s0; + if (viv_s14) begin + mean_y__g <= viv_s11[7:0]; + mean_cb__b <= viv_s12[7:0]; + mean_cr__r <= viv_s13[7:0]; + white_cnt <= viv_s16; + viv_s2 <= viv_s15; + end + if (viv_s0 && viv_s1) begin + viv_s0 <= 1'b0; + end else begin + if (viv_s14) begin + viv_s0 <= 1'b1; + end + end + end + end +end +vsisp_isp_awb_wnd u_isp_awb_wnd ( + .clk(clk), + .reset_n(reset_n), + .soft_rst(soft_rst), + .in_val(meas_val), + .in_ack(meas_ack), + .in_h_end(meas_h_end), + .in_v_end(meas_v_end), + .wnd_val(viv_s4), + .meas_end(viv_s3), + .regs_awb_frames(regs_awb_frames), + .regs_awb_enable(regs_awb_enable), + .regs_awb_h_offs(regs_awb_h_offs), + .regs_awb_v_offs(regs_awb_v_offs), + .regs_awb_h_size(regs_awb_h_size), + .regs_awb_v_size(regs_awb_v_size)); +vsisp_isp_awb_th u_isp_awb_th ( + .meas_data(meas_data), + .wnd_val(viv_s4), + .th_val(viv_s5), + .regs_awb_meas_mode(regs_awb_meas_mode), + .regs_awb_max_en(regs_awb_max_en), + .regs_awb_mode(regs_awb_mode), + .regs_awb_ref_cb__max_b(regs_awb_ref_cb__max_b), + .regs_awb_ref_cr__max_r(regs_awb_ref_cr__max_r), + .regs_awb_max_y(regs_awb_max_y), + .regs_awb_min_y__max_g(regs_awb_min_y__max_g), + .regs_awb_min_c(regs_awb_min_c), + .regs_awb_max_csum(regs_awb_max_csum)); +vsisp_isp_awb_acc u_isp_awb_acc ( + .clk(clk), + .reset_n(reset_n), + .soft_rst(soft_rst), + .in_data(meas_data), + .in_val(viv_s5), + .meas_end(viv_s3), + .acc_data_y(viv_s6), + .acc_data_cb(viv_s7), + .acc_data_cr(viv_s8), + .acc_cnt(viv_s9), + .acc_val(viv_s10)); +vsisp_isp_awb_div #(c_awb_acc_width, c_white_cnt,6) u_isp_awb_div_y ( + .clk(clk), + .reset_n(reset_n), + .soft_rst(soft_rst), + .in_data(viv_s6), + .in_div(viv_s9), + .in_val(viv_s10), + .out_data(viv_s11), + .out_val(viv_s14), + .out_div_zero(viv_s15), + .out_div(viv_s16), + .out_ack(viv_s1)); +vsisp_isp_awb_div #(c_awb_acc_width, c_white_cnt,6) u_isp_awb_div_cb ( + .clk(clk), + .reset_n(reset_n), + .soft_rst(soft_rst), + .in_data(viv_s7), + .in_div(viv_s9), + .in_val(viv_s10), + .out_data(viv_s12), + .out_val(viv_s17), + .out_div_zero(viv_s18), + .out_div(viv_s19), + .out_ack(viv_s1)); +vsisp_isp_awb_div #(c_awb_acc_width, c_white_cnt,6) u_isp_awb_div_cr ( + .clk(clk), + .reset_n(reset_n), + .soft_rst(soft_rst), + .in_data(viv_s8), + .in_div(viv_s9), + .in_val(viv_s10), + .out_data(viv_s13), + .out_val(viv_s20), + .out_div_zero(viv_s21), + .out_div(viv_s22), + .out_ack(viv_s1)); +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_awb_th.v b/ispyocto/rtl/ispyocto/vsisp_isp_awb_th.v new file mode 100644 index 0000000..6e5ffff --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_isp_awb_th.v
@@ -0,0 +1,85 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_isp_awb_th ( + meas_data, + wnd_val, + th_val, + regs_awb_meas_mode, + regs_awb_max_en, + regs_awb_mode, + regs_awb_ref_cb__max_b, + regs_awb_ref_cr__max_r, + regs_awb_max_y, + regs_awb_min_y__max_g, + regs_awb_min_c, + regs_awb_max_csum); +input [23:0] meas_data; +input wnd_val; +output th_val; +input regs_awb_meas_mode; +input regs_awb_max_en; +input [ 1:0] regs_awb_mode; +input [ 7:0] regs_awb_ref_cb__max_b; +input [ 7:0] regs_awb_ref_cr__max_r; +input [ 7:0] regs_awb_max_y; +input [ 7:0] regs_awb_min_y__max_g; +input [ 7:0] regs_awb_min_c; +input [ 7:0] regs_awb_max_csum; +reg [8:0] viv_s0; +reg [8:0] viv_s1; +reg [8:0] viv_s2; +reg [8:0] viv_s3; +reg [9:0] viv_s4; +reg [9:0] viv_s5; +reg [9:0] viv_s6; +reg [10:0] viv_s7; +reg [10:0] viv_s8; +reg viv_s9; +reg viv_s10; +reg th_val; +always @(meas_data or wnd_val or regs_awb_max_en or regs_awb_mode or + regs_awb_max_y or regs_awb_min_y__max_g or regs_awb_meas_mode or + regs_awb_min_c or regs_awb_max_csum or regs_awb_ref_cb__max_b or + regs_awb_ref_cr__max_r) begin + viv_s0 = {1'b0,meas_data[15:8]} - regs_awb_ref_cb__max_b; + viv_s1 = {1'b0,meas_data[ 7:0]} - regs_awb_ref_cr__max_r; + viv_s3 = {1'b0,meas_data[23:16]} - regs_awb_min_y__max_g; + viv_s2 = {1'b0,regs_awb_max_y} - meas_data[23:16]; + viv_s4 = {viv_s0[8], viv_s0} + regs_awb_min_c; + viv_s5 = {viv_s1[8], viv_s1} + regs_awb_min_c; + viv_s6 = {viv_s0[8], viv_s0} + {viv_s1[8], viv_s1}; + viv_s8 = {2'b00, regs_awb_max_csum} - {viv_s6[9], viv_s6}; + viv_s7 = {viv_s6[9], viv_s6} + {2'b00, regs_awb_max_csum}; + viv_s9 = (~viv_s2[8] | ~regs_awb_max_en) && + ~viv_s3[8] && + ~viv_s4[9] && + ~viv_s5[9] && + ~viv_s8[10] && + ~viv_s7[10]; + viv_s10 = viv_s0[8] && viv_s1[8] && viv_s3[8]; + th_val = wnd_val && + (regs_awb_mode != 2'b00) && + (regs_awb_meas_mode ? viv_s10 : viv_s9) ; +end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_awb_wnd.v b/ispyocto/rtl/ispyocto/vsisp_isp_awb_wnd.v new file mode 100644 index 0000000..4fab25f --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_isp_awb_wnd.v
@@ -0,0 +1,156 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_isp_awb_wnd ( + clk, + reset_n, + soft_rst, + in_val, + in_ack, + in_h_end, + in_v_end, + wnd_val, + meas_end, + regs_awb_frames, + regs_awb_enable, + regs_awb_h_offs, + regs_awb_v_offs, + regs_awb_h_size, + regs_awb_v_size); +input clk; +input reset_n; +input soft_rst; +input in_val; +input in_ack; +input in_h_end; +input in_v_end; +output wnd_val; +output meas_end; +input [2:0] regs_awb_frames; +input regs_awb_enable; +input [12:0] regs_awb_h_offs; +input [12:0] regs_awb_v_offs; +input [13:0] regs_awb_h_size; +input [13:0] regs_awb_v_size; +reg [13:0] viv_s0; +reg [13:0] viv_s1; +reg viv_s2; +reg viv_s3; +wire viv_s4; +reg meas_end; +reg [2:0] viv_s5; +wire viv_s6; +wire viv_s7; +wire viv_s8; +assign viv_s6 = (soft_rst || ~regs_awb_enable); +assign viv_s7 = (in_val && in_ack); +assign viv_s8 = ((viv_s0 == 14'd1) && (regs_awb_h_offs == 13'd0)); +assign wnd_val = viv_s2 && viv_s3 && in_val && in_ack; +assign viv_s4 = in_val && in_ack && in_h_end && in_v_end; +always @(posedge clk or negedge reset_n) begin + if (reset_n == 1'b0) begin + viv_s0 <= 14'd1; + viv_s1 <= 14'd1; + viv_s2 <= 1'b0; + viv_s3 <= 1'b0; + viv_s5 <= 3'd0; + meas_end <= 1'b0; + end else begin + if (viv_s6) begin + viv_s0 <= 14'd1; + viv_s1 <= 14'd1; + viv_s2 <= 1'b0; + viv_s3 <= 1'b0; + viv_s5 <= 3'd0; + meas_end <= 1'b0; + end else begin + if (viv_s4) begin + if (viv_s5 == regs_awb_frames) begin + meas_end <= 1'b1; + viv_s5 <= 3'd0; + end else begin + viv_s5 <= viv_s5 + 3'd1; + meas_end <= 1'b0; + end + end else begin + meas_end <= 1'b0; + end + if (viv_s7) begin + if (in_h_end) begin + viv_s0 <= 14'd1; + if (regs_awb_h_offs == 13'd0) begin + viv_s2 <= 1'b1; + end else begin + viv_s2 <= 1'b0; + end + if (in_v_end) begin + viv_s1 <= 14'd1; + if (regs_awb_v_offs == 13'd0) begin + viv_s3 <= 1'b1; + end else begin + viv_s3 <= 1'b0; + end + end else begin + if (viv_s3 && (viv_s1 == regs_awb_v_size)) begin + viv_s1 <= 14'h3FFF; + viv_s3 <= 1'b0; + end else begin + if (!viv_s3 && (viv_s1 == regs_awb_v_offs)) begin + viv_s1 <= 14'd1; + viv_s3 <= 1'b1; + end else begin + if (viv_s1 != 14'h3FFF) begin + viv_s1 <= viv_s1 + 14'd1; + end + end + end + end + end else begin + if (viv_s2 && (viv_s0 == regs_awb_h_size)) begin + viv_s0 <= 14'h3FFF; + viv_s2 <= 1'b0; + end else begin + if (!viv_s2 && (viv_s0 == {1'b0,regs_awb_h_offs})) begin + viv_s0 <= 14'd1; + viv_s2 <= 1'b1; + end else begin + if (viv_s0 != 14'h3FFF) begin + viv_s0 <= viv_s0 + 14'd1; + end + end + end + end + end else begin + if (viv_s8) begin + viv_s2 <= 1'b1; + viv_s0 <= 14'd1; + end + if ((viv_s1 == 14'd1) && (regs_awb_v_offs == 13'd0)) begin + viv_s3 <= 1'b1; + viv_s1 <= 14'd1; + end + end + end + end +end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_bls_regs.v b/ispyocto/rtl/ispyocto/vsisp_isp_bls_regs.v new file mode 100644 index 0000000..2c8d908 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_isp_bls_regs.v
@@ -0,0 +1,91 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_isp_bls_regs ( + clk_cfg, + reset_cfg_n, + cfg_val, + cfg_addr, + cfg_rd, + cfg_wdata, + cfg_rdata, + bls_en, + bls_a_fixed, + bls_b_fixed, + bls_c_fixed, + bls_d_fixed +); +`include "vsisp_isp.vh" +input clk_cfg; +input reset_cfg_n; +input cfg_val; +input [c_cfg_bls-1:2] cfg_addr; +input cfg_rd; +input [31:0] cfg_wdata; +output [31:0] cfg_rdata; +output bls_en; +output [c_dw_si:0] bls_a_fixed; +output [c_dw_si:0] bls_b_fixed; +output [c_dw_si:0] bls_c_fixed; +output [c_dw_si:0] bls_d_fixed; +reg bls_en; +reg [c_dw_si:0] bls_a_fixed; +reg [c_dw_si:0] bls_b_fixed; +reg [c_dw_si:0] bls_c_fixed; +reg [c_dw_si:0] bls_d_fixed; +reg [31:0] cfg_rdata; +always @(*) begin + case (cfg_addr) + c_bls_ctrl[c_cfg_bls-1:2]: cfg_rdata = {31'h0, + bls_en}; + c_bls_a_fixed[c_cfg_bls-1:2]: cfg_rdata = {{31-c_dw_si{1'b0}}, bls_a_fixed}; + c_bls_b_fixed[c_cfg_bls-1:2]: cfg_rdata = {{31-c_dw_si{1'b0}}, bls_b_fixed}; + c_bls_c_fixed[c_cfg_bls-1:2]: cfg_rdata = {{31-c_dw_si{1'b0}}, bls_c_fixed}; + c_bls_d_fixed[c_cfg_bls-1:2]: cfg_rdata = {{31-c_dw_si{1'b0}}, bls_d_fixed}; + default: cfg_rdata = 32'h0; + endcase +end + always @(posedge clk_cfg or negedge reset_cfg_n) begin + if (~reset_cfg_n) begin + bls_en <= 1'b0; + bls_a_fixed <= {c_dw_si+1{1'b0}}; + bls_b_fixed <= {c_dw_si+1{1'b0}}; + bls_c_fixed <= {c_dw_si+1{1'b0}}; + bls_d_fixed <= {c_dw_si+1{1'b0}}; + end + else begin + if (cfg_val && ~cfg_rd) begin + case (cfg_addr) + c_bls_ctrl[c_cfg_bls-1:2]: begin + bls_en <= cfg_wdata[0]; + end + c_bls_a_fixed[c_cfg_bls-1:2] : bls_a_fixed <= cfg_wdata[c_dw_si:0]; + c_bls_b_fixed[c_cfg_bls-1:2] : bls_b_fixed <= cfg_wdata[c_dw_si:0]; + c_bls_c_fixed[c_cfg_bls-1:2] : bls_c_fixed <= cfg_wdata[c_dw_si:0]; + c_bls_d_fixed[c_cfg_bls-1:2] : bls_d_fixed <= cfg_wdata[c_dw_si:0]; + default: begin end + endcase + end + end + end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_bls_subtr.v b/ispyocto/rtl/ispyocto/vsisp_isp_bls_subtr.v new file mode 100644 index 0000000..a9447bd --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_isp_bls_subtr.v
@@ -0,0 +1,178 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_isp_bls_subtr + ( + clk, + reset_n, + soft_rst, + bayer_pat_diff, + in_data, + in_h_end, + in_v_end, + in_val, + in_ack, + out_data, + out_h_end, + out_v_end, + out_val, + out_ack, + bls_en, + bls_mode, + bls_a_fixed, + bls_b_fixed, + bls_c_fixed, + bls_d_fixed, + bls_a_measured, + bls_b_measured, + bls_c_measured, + bls_d_measured + ); +`include "vsisp_isp.vh" + input clk; + input reset_n; + input soft_rst; + input [1:0] bayer_pat_diff; + input [c_dw_si-1:0] in_data; + input in_h_end; + input in_v_end; + input in_val; + output in_ack; + output [c_dw_si-1:0] out_data; + output out_h_end; + output out_v_end; + output out_val; + input out_ack; + input bls_en; + input bls_mode; + input [c_dw_si:0] bls_a_fixed; + input [c_dw_si:0] bls_b_fixed; + input [c_dw_si:0] bls_c_fixed; + input [c_dw_si:0] bls_d_fixed; + input [c_dw_si-1:0] bls_a_measured; + input [c_dw_si-1:0] bls_b_measured; + input [c_dw_si-1:0] bls_c_measured; + input [c_dw_si-1:0] bls_d_measured; + reg [c_dw_si-1:0] out_data; + reg out_h_end; + reg out_v_end; + reg viv_s0; + wire viv_s1; + wire [c_dw_si-1:0] viv_s2; + wire viv_s3; + wire viv_s4; + wire viv_s5; + wire [c_dw_si+1:0] viv_s6; + wire [c_dw_si-1:0] viv_s7; + wire [2:0] viv_s8; + reg [c_dw_si:0] viv_s9; + reg viv_s10; + reg viv_s11; + wire viv_s12; + wire out_val; + reg viv_s13; + reg [1:0] viv_s14; + assign viv_s12 = (in_val && in_ack); + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + viv_s13 <= 1'b0; + viv_s14 <= 2'd0; + viv_s10 <= 1'b0; + viv_s11 <= 1'b0; + end + else begin + if (out_v_end && out_h_end && out_val || soft_rst) begin + viv_s13 <= 1'b0; + end else if (viv_s12) begin + viv_s13 <= 1'b1; + end + if (~viv_s13) begin + viv_s14 <= bayer_pat_diff; + end + if (soft_rst) begin + viv_s10 <= 1'b0; + viv_s11 <= 1'b0; + end else if (viv_s12) begin + if (in_h_end) begin + viv_s10 <= 1'b0; + if(in_v_end) begin + viv_s11 <= 1'b0; + end else begin + viv_s11 <= ~viv_s11; + end + end else begin + viv_s10 <= ~viv_s10; + end + end + end + end + assign viv_s8[0] = viv_s10 ^ viv_s14[0]; + assign viv_s8[1] = viv_s11 ^ viv_s14[1]; + assign viv_s8[2] = bls_mode; + always @(*) begin + case (viv_s8) + 3'd0: viv_s9 = bls_a_fixed; + 3'd1: viv_s9 = bls_b_fixed; + 3'd2: viv_s9 = bls_c_fixed; + 3'd3: viv_s9 = bls_d_fixed; + 3'd4: viv_s9 = {1'b0, bls_a_measured}; + 3'd5: viv_s9 = {1'b0, bls_b_measured}; + 3'd6: viv_s9 = {1'b0, bls_c_measured}; + default: viv_s9 = {1'b0, bls_d_measured}; + endcase + end + assign viv_s5 = in_val; + assign viv_s3 = in_h_end; + assign viv_s4 = in_v_end; + assign viv_s6 = {2'b0, in_data} - {viv_s9[c_dw_si], viv_s9}; + assign viv_s7 = (viv_s6[c_dw_si+1]) ? {c_dw_si{1'b0}} : + (viv_s6[c_dw_si]) ? {c_dw_si{1'b1}} : + viv_s6[c_dw_si-1:0]; + assign viv_s2 = bls_en ? viv_s7 : in_data; + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + out_data <= {c_dw_si{1'b0}}; + out_v_end <= 1'b0; + out_h_end <= 1'b0; + viv_s0 <= 1'b0; + end + else begin + if (soft_rst) begin + viv_s0 <= 1'b0; + out_v_end <= 1'b0; + out_h_end <= 1'b0; + end + else begin + if (viv_s1) begin + viv_s0 <= viv_s5; + out_data <= viv_s2; + out_h_end <= viv_s3; + out_v_end <= viv_s4; + end + end + end + end + assign viv_s1 = out_ack || (~viv_s0); + assign in_ack = viv_s1; + assign out_val = viv_s0; +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_bls_v2.v b/ispyocto/rtl/ispyocto/vsisp_isp_bls_v2.v new file mode 100644 index 0000000..73b2d48 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_isp_bls_v2.v
@@ -0,0 +1,116 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_isp_bls_v2 + ( + clk, + reset_n, + clk_cfg, + reset_cfg_n, + soft_rst, + cfg_val, + cfg_addr, + cfg_rd, + cfg_wdata, + cfg_rdata, + bayer_pat_diff, + in_act_data, + in_act_h_end, + in_act_v_end, + in_act_val, + in_act_ack, + out_data, + out_h_end, + out_v_end, + out_val, + out_ack + ); +`include "vsisp_isp.vh" + input clk; + input reset_n; + input clk_cfg; + input reset_cfg_n; + input soft_rst; + input cfg_val; + input [c_cfg_bls-1:2] cfg_addr; + input cfg_rd; + input [31:0] cfg_wdata; + output [31:0] cfg_rdata; + input [1:0] bayer_pat_diff; + input [c_dw_si-1:0] in_act_data; + input in_act_h_end; + input in_act_v_end; + input in_act_val; + output in_act_ack; + output [c_dw_si-1:0] out_data; + output out_h_end; + output out_v_end; + output out_val; + input out_ack; + wire viv_s0; + wire [c_dw_si:0] viv_s1; + wire [c_dw_si:0] viv_s2; + wire [c_dw_si:0] viv_s3; + wire [c_dw_si:0] viv_s4; +vsisp_isp_bls_regs u_isp_bls_regs ( + .clk_cfg(clk_cfg), + .reset_cfg_n(reset_cfg_n), + .cfg_val(cfg_val), + .cfg_addr(cfg_addr), + .cfg_rd(cfg_rd), + .cfg_wdata(cfg_wdata), + .cfg_rdata(cfg_rdata), + .bls_en(viv_s0), + .bls_a_fixed(viv_s1), + .bls_b_fixed(viv_s2), + .bls_c_fixed(viv_s3), + .bls_d_fixed(viv_s4) + ); + vsisp_isp_bls_subtr u_isp_bls_subtr + ( + .clk(clk), + .reset_n(reset_n), + .soft_rst(soft_rst), + .bayer_pat_diff(bayer_pat_diff), + .in_data(in_act_data), + .in_h_end(in_act_h_end), + .in_v_end(in_act_v_end), + .in_val(in_act_val), + .in_ack(in_act_ack), + .out_data(out_data), + .out_h_end(out_h_end), + .out_v_end(out_v_end), + .out_val(out_val), + .out_ack(out_ack), + .bls_en(viv_s0), + .bls_mode(1'b0), + .bls_a_fixed(viv_s1), + .bls_b_fixed(viv_s2), + .bls_c_fixed(viv_s3), + .bls_d_fixed(viv_s4), + .bls_a_measured({c_dw_si{1'b0}}), + .bls_b_measured({c_dw_si{1'b0}}), + .bls_c_measured({c_dw_si{1'b0}}), + .bls_d_measured({c_dw_si{1'b0}}) + ); +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_cac_ctrl.v b/ispyocto/rtl/ispyocto/vsisp_isp_cac_ctrl.v new file mode 100644 index 0000000..a1a20e1 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_isp_cac_ctrl.v
@@ -0,0 +1,663 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_isp_cac_ctrl + ( + clk, + reset_n, + soft_rst, + memif_h_end, + memif_v_end, + memif_val, + memif_ack, + mem_h_end, + mem_v_end, + mem_val, + mem_ack, + cac_in_val, + cac_in_ack, + alom_stage1_en, + alom_stage2_en, + alom_stage3_en, + alom_stage4_en, + alom_stage5_en, + alom_stage3_val, + alom_stage5_val, + regs_bayer_pat, + cfg_upd, + cac_enable, + cac_h_clip_mode, + cac_v_clip_mode, + cac_h_count_start, + cac_v_count_start, + cac_x_norm_factor, + cac_y_norm_factor, + cac_x_norm_shift, + cac_y_norm_shift, + cac_a_red, + cac_b_red, + cac_c_red, + cac_a_blue, + cac_b_blue, + cac_c_blue, + cac_v_sel_1, + cac_v_sel_2, + cac_v_sel_3, + cac_v_coef, + cac_v_filt_disable, + cac_h_red, + cac_h_blue, + cac_h_red_col); +`include "vsisp_isp.vh" +`include "vsisp_f_sqrt_8bit.vh" + input clk; + input reset_n; + input soft_rst; + input memif_h_end; + input memif_v_end; + input memif_val; + input memif_ack; + input mem_h_end; + input mem_v_end; + input mem_val; + output mem_ack; + output cac_in_val; + input cac_in_ack; + input alom_stage1_en; + input alom_stage2_en; + input alom_stage3_en; + input alom_stage4_en; + input alom_stage5_en; + input alom_stage3_val; + input alom_stage5_val; + input [1:0] regs_bayer_pat; + input cfg_upd; + input cac_enable; + input cac_h_clip_mode; + input [1:0] cac_v_clip_mode; + input [12:0] cac_h_count_start; + input [12:0] cac_v_count_start; + input [4:0] cac_x_norm_factor; + input [4:0] cac_y_norm_factor; + input [3:0] cac_x_norm_shift; + input [3:0] cac_y_norm_shift; + input [8:0] cac_a_red; + input [8:0] cac_b_red; + input [8:0] cac_c_red; + input [8:0] cac_a_blue; + input [8:0] cac_b_blue; + input [8:0] cac_c_blue; + output [3:0] cac_v_sel_1; + output [3:0] cac_v_sel_2; + output [3:0] cac_v_sel_3; + output [4:0] cac_v_coef; + output cac_v_filt_disable; + output [7:0] cac_h_red; + output [7:0] cac_h_blue; + output cac_h_red_col; + wire mem_ack; + reg viv_s0; + reg [1:0] viv_s1; + reg [12:0] viv_s2; + reg [12:0] viv_s3; + reg [4:0] viv_s4; + reg [4:0] viv_s5; + reg [3:0] viv_s6; + reg [3:0] viv_s7; + reg [8:0] viv_s8; + reg [8:0] viv_s9; + reg [8:0] viv_s10; + reg [8:0] viv_s11; + reg [8:0] viv_s12; + reg [8:0] viv_s13; + reg viv_s14; + reg viv_s15; + reg viv_s16; + reg viv_s17; + reg viv_s18; + reg viv_s19; + reg viv_s20; + reg viv_s21; + wire viv_s22; + wire viv_s23; + wire viv_s24; + wire viv_s25; + wire viv_s26; + wire viv_s27; + wire viv_s28; + wire viv_s29; + wire viv_s30; + wire viv_s31; + wire viv_s32; + reg viv_s33; + reg [1:0] viv_s34; + wire viv_s35; + wire viv_s36; + reg [12:0] viv_s37; + reg [12:0] viv_s38; + reg viv_s39; + reg viv_s40; + reg [8:0] viv_s41; + wire viv_s42; + wire viv_s43; + wire viv_s44; + wire [12:0] viv_s45; + wire [4:0] viv_s46; + wire [3:0] viv_s47; + wire [13:0] viv_s48; + reg [7:0] viv_s49; + reg viv_s50; + reg viv_s51; + reg viv_s52; + reg viv_s53; + reg viv_s54; + reg viv_s55; + reg viv_s56; + reg viv_s57; + reg viv_s58; + reg viv_s59; + reg viv_s60; + reg viv_s61; + reg viv_s62; + wire viv_s63; + reg viv_s64; + wire signed [8:0] viv_s65; + reg signed [8:0] viv_s66; + reg signed [8:0] viv_s67; + reg signed [8:0] viv_s68; + reg signed [8:0] viv_s69; + wire [15:0] viv_s70; + reg [11:0] viv_s71; + wire [11:0] viv_s72; + reg [11:0] viv_s73; + reg [7:0] viv_s74; + wire [7:0] viv_s75; + reg [7:0] viv_s76; + wire signed [8:0] viv_s77; + wire signed [8:0] viv_s78; + wire signed [8:0] viv_s79; + wire signed [16:0] viv_s80; + wire signed [16:0] viv_s81; + wire [10:0] viv_s82; + reg signed [10:0] viv_s83; + wire signed [18:0] viv_s84; + wire signed [18:0] viv_s85; + wire [7:0] viv_s86; + wire [7:0] viv_s87; + wire [4:0] viv_s88; + reg [7:0] viv_s89; + reg [7:0] viv_s90; + reg [7:0] viv_s91; + reg [7:0] viv_s92; + reg [7:0] viv_s93; + wire [7:0] viv_s94; + reg viv_s95; + wire [3:0] viv_s96; + wire [2:0] viv_s97; + wire [3:0] viv_s98; + wire [4:0] viv_s99; + wire [10:0] viv_s100; + wire [10:0] viv_s101; + reg viv_s102; + reg viv_s103; + reg viv_s104; + reg viv_s105; + reg viv_s106; + reg viv_s107; + reg [7:0] viv_s108; + reg [7:0] viv_s109; + reg [7:0] viv_s110; + reg [7:0] viv_s111; + reg [7:0] viv_s112; + reg [7:0] viv_s113; + reg [7:0] viv_s114; + wire [8:0] viv_s115; + reg [7:0] viv_s116; + reg [7:0] viv_s117; + reg [7:0] viv_s118; + reg [7:0] viv_s119; + reg [7:0] viv_s120; + reg [7:0] viv_s121; + reg [7:0] viv_s122; + reg [7:0] viv_s123; + reg [7:0] viv_s124; + reg [7:0] viv_s125; + reg [2:0] viv_s126; + reg [2:0] viv_s127; + reg [2:0] viv_s128; + reg viv_s129; + reg cac_v_filt_disable; + reg [4:0] viv_s130; + always @ (posedge clk or negedge reset_n) begin + if (~reset_n) begin + viv_s34 <= 2'b00; + viv_s0 <= 1'b0; + viv_s1 <= 2'h0; + viv_s2 <= 13'h0; + viv_s3 <= 13'h0; + viv_s4 <= 5'h0; + viv_s5 <= 5'h0; + viv_s6 <= 4'h0; + viv_s7 <= 4'h0; + viv_s8 <= 9'h0; + viv_s9 <= 9'h0; + viv_s10 <= 9'h0; + viv_s11 <= 9'h0; + viv_s12 <= 9'h0; + viv_s13 <= 9'h0; + end else if (viv_s14) begin + viv_s34 <= regs_bayer_pat; + viv_s0 <= cac_h_clip_mode; + viv_s1 <= cac_v_clip_mode; + viv_s2 <= cac_h_count_start; + viv_s3 <= cac_v_count_start; + viv_s4 <= cac_x_norm_factor; + viv_s5 <= cac_y_norm_factor; + viv_s6 <= cac_x_norm_shift; + viv_s7 <= cac_y_norm_shift; + viv_s8 <= cac_a_red; + viv_s9 <= cac_b_red; + viv_s10 <= cac_c_red; + viv_s11 <= cac_a_blue; + viv_s12 <= cac_b_blue; + viv_s13 <= cac_c_blue; + end + end + assign mem_ack = cac_in_ack && viv_s21; + assign viv_s27 = cac_in_ack && mem_val ; + assign cac_in_val = mem_val && viv_s21; + assign viv_s36 = cac_in_ack; + assign viv_s28 = viv_s22; + assign viv_s29 = viv_s23; + assign viv_s30 = viv_s24; + assign viv_s31 = viv_s25; + assign viv_s32 = viv_s26; + assign viv_s26 = !mem_val && !viv_s21 || viv_s27; + assign viv_s25 = viv_s26; + assign viv_s24 = !viv_s19 || viv_s25; + assign viv_s23 = !viv_s18 || viv_s24; + assign viv_s22 = !viv_s17 || viv_s23; + always @ (posedge clk or negedge reset_n) begin + if (~reset_n) begin + viv_s33 <= 1'b0; + end else begin + if (soft_rst) + viv_s33 <= 1'b0; + else begin + if (mem_v_end && mem_h_end && mem_val && mem_ack) + viv_s33 <= 1'b0; + else if (memif_val) + viv_s33 <= 1'b1; + end + end + end + assign viv_s42 = memif_h_end && memif_val && memif_ack; + assign viv_s43 = viv_s16 && ~viv_s33; + assign viv_s44 = memif_v_end && viv_s42 || viv_s43; + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + viv_s14 <= 0; + viv_s15 <= 0; + viv_s16 <= 0; + viv_s37 <= 0; + viv_s38 <= 0; + viv_s39 <= 0; + viv_s40 <= 0; + viv_s52 <= 0; + viv_s58 <= 0; + viv_s51 <= 0; + viv_s50 <= 0; + viv_s71 <= 0; + viv_s66 <= 0; + end else begin + viv_s14 <= cfg_upd; + viv_s15 <= viv_s14; + viv_s16 <= viv_s15; + if (viv_s44) begin + viv_s37 <= viv_s2; + viv_s39 <= 0; + viv_s52 <= ~regs_bayer_pat[0]; + viv_s58 <= ~regs_bayer_pat[1]; + viv_s38 <= viv_s3 -1; + viv_s40 <= 0; + end else if (viv_s42) begin + viv_s37 <= viv_s2; + viv_s39 <= 0; + viv_s52 <= ~viv_s34[0]; + viv_s58 <= ~viv_s58 ; + if (viv_s40) + viv_s38 <= viv_s38 +1; + else + viv_s38 <= viv_s38 -1; + if (viv_s38 == 13'h1) + viv_s40 <= 1; + end else if (viv_s28) begin + viv_s52 <= ~viv_s52; + if (viv_s39) + viv_s37 <= viv_s37 +1; + else + viv_s37 <= viv_s37 -1; + if (viv_s37 == 13'h1) + viv_s39 <= 1; + end + viv_s50 <= viv_s43; + viv_s51 <= viv_s42 || viv_s43; + if (viv_s51) begin + viv_s71 <= viv_s70[15:4]; + viv_s66 <= viv_s65; + end + end + end + assign viv_s46 = (viv_s42 || viv_s43) ? viv_s5 : + viv_s4; + assign viv_s47 = (viv_s42 || viv_s43) ? viv_s7 : + viv_s6; + assign viv_s45 = (viv_s44) ? viv_s3 : + (viv_s42) ? viv_s38 : viv_s37; + assign viv_s63 = (viv_s44) ? 1'b0 : + (viv_s42) ? viv_s40 : viv_s39; + always @(*) + begin + case(viv_s47) + 4'd0 : viv_s41 = {viv_s45[4:0], 4'b0}; + 4'd1 : viv_s41 = {viv_s45[5:0], 3'b0}; + 4'd2 : viv_s41 = {viv_s45[6:0], 2'b0}; + 4'd3 : viv_s41 = {viv_s45[7:0], 1'b0}; + 4'd4 : viv_s41 = viv_s45[8:0]; + 4'd5 : viv_s41 = viv_s45[9:1]; + 4'd6 : viv_s41 = viv_s45[10:2]; + 4'd7 : viv_s41 = viv_s45[11:3]; + default: viv_s41 = viv_s45[12:4]; + endcase + end + assign viv_s48 = viv_s41 * viv_s46 + 9'h10; + assign viv_s70 = viv_s49 * viv_s49; + assign viv_s72 = viv_s70[15:4] + viv_s71; + assign viv_s65 = (viv_s64) ? $signed({1'b0, viv_s49}) : $signed(9'h0 - {1'b0, viv_s49}); + assign viv_s75 = f_sqrt_8bit(viv_s73); + assign viv_s77 = (~cac_enable) ? $signed(9'h0) : (viv_s55) ? $signed(viv_s8) : $signed(viv_s11); + assign viv_s78 = (~cac_enable) ? $signed(9'h0) : (viv_s55) ? $signed(viv_s9) : $signed(viv_s12); + assign viv_s79 = (~cac_enable) ? $signed(9'h0) : (viv_s55) ? $signed(viv_s10) : $signed(viv_s13); + assign viv_s80 = viv_s78 * $signed({1'b0,viv_s76}); + assign viv_s81 = viv_s79 * $signed({1'b0,viv_s74}); + assign viv_s82 = {viv_s77[8], viv_s77[8], viv_s77} + + {viv_s80[16], viv_s80[16], viv_s80[16:8]} + + {viv_s81[16], viv_s81[16], viv_s81[16:8]}; + assign viv_s85 = viv_s83 * viv_s66; + assign viv_s84 = viv_s83 * viv_s69; + assign viv_s100 = {~viv_s85[18],viv_s85[17:8]}; + assign viv_s101 = {~viv_s84[18],viv_s84[17:8]}; + assign viv_s87 = (viv_s100 > 11'h440) ? 8'hC0 : + (viv_s100 < 11'h3C0) ? 8'h40 : + {~viv_s85[15],viv_s85[14:8]}; + assign viv_s86 = (viv_s101 > 11'h450) ? 8'hD0 : + (viv_s101 < 11'h3B0) ? 8'h30 : + {~viv_s84[15],viv_s84[14:8]}; + assign viv_s35 = viv_s62 == viv_s56; + assign viv_s88 = (viv_s35) ? 5'h00 : 5'h10; + always @(viv_s1 or viv_s35) + begin + case(viv_s1) + 2'd0 : begin + viv_s89 = 8'hA0; + viv_s90 = 8'h60; + viv_s91 = 8'hA0; + viv_s92 = 8'h60; + end + 2'd1 : begin + viv_s89 = 8'hB0; + viv_s90 = 8'h50; + viv_s91 = 8'hA0; + viv_s92 = 8'h60; + end + default: begin + viv_s89 = (viv_s35) ? 8'hC0 : 8'hB0; + viv_s90 = (viv_s35) ? 8'h40 : 8'h50; + viv_s91 = (viv_s35) ? 8'hB0 : 8'hA0; + viv_s92 = (viv_s35) ? 8'h50 : 8'h60; + end + endcase + end + always @(*) begin + if (viv_s87 > viv_s89) + viv_s93 = viv_s89; + else if (viv_s87 < viv_s90) + viv_s93 = viv_s90; + else + viv_s93 = viv_s87; + end + always @(*) + begin + if (((viv_s1 == 2'd2) || (viv_s1 == 2'd1) && ~viv_s35) + && ((viv_s87 > viv_s91) || (viv_s87 < viv_s92))) + viv_s95 = 1; + else + viv_s95 = 0; + end + assign viv_s94 = viv_s93 - viv_s88; + assign viv_s99 = viv_s94[4:0]; + assign viv_s96 = viv_s94[7:4] - 1; + assign viv_s97 = viv_s94[7:5]; + assign viv_s98 = viv_s94[7:4] + 1; + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + viv_s17 <= 0; + viv_s18 <= 0; + viv_s19 <= 0; + viv_s20 <= 0; + viv_s21 <= 0; + viv_s53 <= 0; + viv_s54 <= 0; + viv_s55 <= 0; + viv_s56 <= 0; + viv_s57 <= 0; + viv_s59 <= 0; + viv_s60 <= 0; + viv_s61 <= 0; + viv_s62 <= 0; + viv_s64 <= 0; + viv_s49 <= 0; + viv_s67 <= 0; + viv_s68 <= 0; + viv_s69 <= 0; + viv_s73 <= 0; + viv_s74 <= 0; + viv_s76 <= 0; + viv_s83 <= 0; + viv_s126 <= 0; + viv_s127 <= 0; + viv_s128 <= 0; + viv_s129 <= 0; + cac_v_filt_disable <= 0; + viv_s130 <= 0; + viv_s108 <= 0; + end else begin + if (viv_s28 || viv_s44) begin + viv_s49 <= viv_s48[12:5]; + viv_s64 <= viv_s63; + end + if (viv_s28) begin + viv_s53 <= viv_s52; + viv_s59 <= viv_s58; + end + if (viv_s29) begin + viv_s67 <= viv_s65; + viv_s73 <= viv_s72; + viv_s54 <= viv_s53; + viv_s60 <= viv_s59; + end + if (viv_s30) begin + viv_s76 <= viv_s75; + viv_s74 <= viv_s73[11:4]; + viv_s68 <= viv_s67; + viv_s55 <= viv_s54; + viv_s61 <= viv_s60; + end + if (viv_s31) begin + viv_s83 <= viv_s82; + viv_s69 <= viv_s68; + viv_s56 <= viv_s55; + viv_s62 <= viv_s61; + end + if (viv_s32) begin + viv_s126 <= viv_s96[3:1]; + viv_s127 <= viv_s97; + viv_s128 <= viv_s98[3:1]; + cac_v_filt_disable <= viv_s95; + viv_s129 <= ~viv_s35; + viv_s130 <= viv_s99; + viv_s108 <= viv_s86; + viv_s57 <= viv_s56; + end + if (viv_s42 || viv_s43) begin + viv_s17 <= 0; + viv_s18 <= 0; + viv_s19 <= 0; + viv_s20 <= 0; + end else begin + if (viv_s28) + viv_s17 <= 1; + if (viv_s29) + viv_s18 <= viv_s17; + if (viv_s30) + viv_s19 <= viv_s18; + if (viv_s31) + viv_s20 <= viv_s19; + end + if (mem_h_end && mem_val && mem_ack || viv_s50) begin + viv_s21 <= 0; + end else begin + if (viv_s32) + viv_s21 <= viv_s20; + end + end + end + always @(*) + begin + if (viv_s0 == 1'b0) begin + viv_s116 = 8'hC0; + viv_s117 = 8'h40; + viv_s118 = 8'hC0; + viv_s119 = 8'h40; + end else begin + viv_s116 = (viv_s106) ? 8'hC0 : 8'hD0; + viv_s117 = (viv_s106) ? 8'h40 : 8'h30; + viv_s118 = (viv_s106) ? 8'hD0 : 8'hC0; + viv_s119 = (viv_s106) ? 8'h30 : 8'h40; + end + end + assign viv_s115 ={1'b0,viv_s112}+viv_s114; + always @(*) begin + if (viv_s106) begin + viv_s120 = viv_s113; + if (alom_stage3_val) + if (alom_stage5_val) + viv_s122 = viv_s115[8:1]; + else + viv_s122 = viv_s112; + else + viv_s122 = viv_s114; + end else begin + if (alom_stage3_val) + if (alom_stage5_val) + viv_s120 = viv_s115[8:1]; + else + viv_s120 = viv_s112; + else + viv_s120 = viv_s114; + viv_s122 = viv_s113; + end + end + always @(*) begin + if (viv_s120 > viv_s116) + viv_s121 = viv_s116; + else if (viv_s120 < viv_s117) + viv_s121 = viv_s117; + else if (viv_s106) + viv_s121 = viv_s120; + else + viv_s121 = viv_s120 - 8'h10; + end + always @(*) begin + if (viv_s122 > viv_s118) + viv_s123 = viv_s118; + else if (viv_s122 < viv_s119) + viv_s123 = viv_s119; + else if (viv_s106) + viv_s123 = viv_s122 - 8'h10; + else + viv_s123 = viv_s122; + end + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + viv_s102 <= 0; + viv_s103 <= 0; + viv_s104 <= 0; + viv_s105 <= 0; + viv_s106 <= 0; + viv_s107 <= 0; + viv_s109 <= 0; + viv_s110 <= 0; + viv_s111 <= 0; + viv_s112 <= 0; + viv_s113 <= 0; + viv_s114 <= 0; + viv_s124 <= 0; + viv_s125 <= 0; + end else begin + if (viv_s36) begin + viv_s102 <= viv_s57; + viv_s109 <= viv_s108; + end + if (alom_stage1_en) begin + viv_s103 <= viv_s102; + viv_s110 <= viv_s109; + end + if (alom_stage2_en) begin + viv_s104 <= viv_s103; + viv_s111 <= viv_s110; + end + if (alom_stage3_en) begin + viv_s105 <= viv_s104; + viv_s112 <= viv_s111; + end + if (alom_stage4_en) begin + viv_s106 <= viv_s105; + viv_s113 <= viv_s112; + end + if (alom_stage5_en) begin + viv_s107 <= viv_s106; + viv_s124 <= viv_s121; + viv_s125 <= viv_s123; + viv_s114 <= viv_s113; + end + end + end + assign cac_v_sel_1 = {viv_s126, viv_s129}; + assign cac_v_sel_2 = {viv_s127, viv_s129}; + assign cac_v_sel_3 = {viv_s128, viv_s129}; + assign cac_v_coef = viv_s130; + assign cac_h_red_col = viv_s107; + assign cac_h_red = viv_s124; + assign cac_h_blue = viv_s125; +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_cac_delay.v b/ispyocto/rtl/ispyocto/vsisp_isp_cac_delay.v new file mode 100644 index 0000000..8a0b470 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_isp_cac_delay.v
@@ -0,0 +1,73 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_isp_cac_delay + ( + clk, + reset_n, + cac_v_clk_en, + mem_data_m2, + mem_data_m3, + mem_data_m4, + mem_data_m5, + mem_data_m6, + dem_in_data_m2, + dem_in_data_m3, + dem_in_data_m4, + dem_in_data_m5, + dem_in_data_m6); +`include "vsisp_isp.vh" + input clk; + input reset_n; + input cac_v_clk_en; + input [c_dw_si-1:0] mem_data_m2; + input [c_dw_si-1:0] mem_data_m3; + input [c_dw_si-1:0] mem_data_m4; + input [c_dw_si-1:0] mem_data_m5; + input [c_dw_si-1:0] mem_data_m6; + output [c_dw_si-1:0] dem_in_data_m2; + output [c_dw_si-1:0] dem_in_data_m3; + output [c_dw_si-1:0] dem_in_data_m4; + output [c_dw_si-1:0] dem_in_data_m5; + output [c_dw_si-1:0] dem_in_data_m6; + reg [c_dw_si-1:0] dem_in_data_m2; + reg [c_dw_si-1:0] dem_in_data_m3; + reg [c_dw_si-1:0] dem_in_data_m4; + reg [c_dw_si-1:0] dem_in_data_m5; + reg [c_dw_si-1:0] dem_in_data_m6; + always @(posedge clk or negedge reset_n) begin + if (~reset_n) begin + dem_in_data_m2 <= {c_dw_si{1'b0}}; + dem_in_data_m3 <= {c_dw_si{1'b0}}; + dem_in_data_m4 <= {c_dw_si{1'b0}}; + dem_in_data_m5 <= {c_dw_si{1'b0}}; + dem_in_data_m6 <= {c_dw_si{1'b0}}; + end else if (cac_v_clk_en) begin + dem_in_data_m2 <= mem_data_m2; + dem_in_data_m3 <= mem_data_m3; + dem_in_data_m4 <= mem_data_m4; + dem_in_data_m5 <= mem_data_m5; + dem_in_data_m6 <= mem_data_m6; + end + end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_cac_hor.v b/ispyocto/rtl/ispyocto/vsisp_isp_cac_hor.v new file mode 100644 index 0000000..a825ee3 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_isp_cac_hor.v
@@ -0,0 +1,308 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_isp_cac_hor + ( + clk, + reset_n, + soft_rst, + in_val, + in_ack, + in_h_end, + in_v_end, + cac_v_data_out, + red_sub, + blue_sub, + regs_dem_bypass, + regs_bayer_pat, + cac_h_red, + cac_h_blue, + cac_h_red_col, + alom_stage1_en, + alom_stage2_en, + alom_stage3_en, + alom_stage4_en, + alom_stage5_en, + alom_stage6_en, + alom_stage7_en, + alom_stage8_en, + alom_stage0_val, + alom_stage1_val, + alom_stage2_val, + alom_stage3_val, + alom_stage4_val, + alom_stage5_val, + alom_stage6_val, + proc_pattern_stg2, + proc_pattern_stg3, + out_cb, + out_cr, + out_h_end, + out_v_end, + out_val, + out_ack); +`include "vsisp_isp.vh" + input clk; + input reset_n; + input soft_rst; + input in_val; + output in_ack; + input in_h_end; + input in_v_end; + input [c_dw_si-1:0] cac_v_data_out; + input [c_dw_si:0] red_sub; + input [c_dw_si:0] blue_sub; + input regs_dem_bypass; + input [1:0] regs_bayer_pat; + input [7:0] cac_h_red; + input [7:0] cac_h_blue; + input cac_h_red_col; + output alom_stage1_en; + output alom_stage2_en; + output alom_stage3_en; + output alom_stage4_en; + output alom_stage5_en; + output alom_stage6_en; + output alom_stage7_en; + output alom_stage8_en; + output alom_stage0_val; + output alom_stage1_val; + output alom_stage2_val; + output alom_stage3_val; + output alom_stage4_val; + output alom_stage5_val; + output alom_stage6_val; + output [1:0] proc_pattern_stg2; + output [1:0] proc_pattern_stg3; + output [c_dw_si:0] out_cb; + output [c_dw_si:0] out_cr; + output out_h_end; + output out_v_end; + output out_val; + input out_ack; + wire [c_dw_si-1:0] viv_s0; + wire [c_dw_si-1:0] viv_s1; + wire [c_dw_si-1:0] viv_s2; + wire [c_dw_si-1:0] viv_s3; + wire [c_dw_si-1:0] viv_s4; + wire [c_dw_si-1:0] viv_s5; + wire [c_dw_si-1:0] viv_s6; + wire [c_dw_si-1:0] viv_s7; + wire [c_dw_si-1:0] viv_s8; + wire [c_dw_si-1:0] viv_s9; + wire [c_dw_si-1:0] viv_s10; + wire alom_stage5_en; + wire alom_stage6_en; + wire alom_stage7_en; + wire alom_stage8_en; + wire [3:0] viv_s11; + wire [3:0] viv_s12; + reg [4:0] viv_s13; + reg [4:0] viv_s14; + reg [c_dw_si-1:0] viv_s15; + reg [c_dw_si-1:0] viv_s16; + reg [c_dw_si-1:0] viv_s17; + reg [c_dw_si-1:0] viv_s18; + wire [c_dw_si-1:0] viv_s19; + wire [c_dw_si-1:0] viv_s20; + wire [c_dw_si-1:0] viv_s21; + wire [c_dw_si-1:0] viv_s22; + wire [c_dw_si-1:0] viv_s23; + wire [c_dw_si-1:0] viv_s24; + wire [c_dw_si-1:0] viv_s25; + wire [c_dw_si-1:0] viv_s26; + wire [c_dw_si-1:0] viv_s27; + wire [c_dw_si-1:0] viv_s28; + wire [c_dw_si+5:0] viv_s29; + wire [c_dw_si+5:0] viv_s30; + reg [c_dw_si:0] viv_s31; + reg [c_dw_si:0] viv_s32; + reg [c_dw_si:0] viv_s33; + reg [c_dw_si:0] viv_s34; + reg [c_dw_si:0] out_cb; + reg [c_dw_si:0] out_cr; + reg viv_s35; + reg viv_s36; + vsisp_isp_cac_hor_buf #(c_dw_si) u_isp_cac_hor_buf + ( + .clk(clk), + .reset_n(reset_n), + .soft_rst(soft_rst), + .in_val(in_val), + .in_ack(in_ack), + .in_h_end(in_h_end), + .in_v_end(in_v_end), + .in_data(cac_v_data_out), + .regs_bayer_pat(regs_bayer_pat), + .out_stage0(viv_s0), + .out_stage1(viv_s1), + .out_stage2(viv_s2), + .out_stage3(viv_s3), + .out_stage4(viv_s4), + .out_stage5(viv_s5), + .out_stage6(viv_s6), + .out_stage7(viv_s7), + .out_stage8(viv_s8), + .out_stage9(viv_s9), + .out_stage10(viv_s10), + .alom_stage1_en(alom_stage1_en), + .alom_stage2_en(alom_stage2_en), + .alom_stage3_en(alom_stage3_en), + .alom_stage4_en(alom_stage4_en), + .alom_stage5_en(alom_stage5_en), + .alom_stage6_en(alom_stage6_en), + .alom_stage7_en(alom_stage7_en), + .alom_stage8_en(alom_stage8_en), + .alom_stage0_val(alom_stage0_val), + .alom_stage1_val(alom_stage1_val), + .alom_stage2_val(alom_stage2_val), + .alom_stage3_val(alom_stage3_val), + .alom_stage4_val(alom_stage4_val), + .alom_stage5_val(alom_stage5_val), + .alom_stage6_val(alom_stage6_val), + .proc_pattern_stg2(proc_pattern_stg2), + .proc_pattern_stg3(proc_pattern_stg3), + .out_h_end(out_h_end), + .out_v_end(out_v_end), + .out_val(out_val), + .out_ack(out_ack)); + assign viv_s11 = {cac_h_red[7:5],~cac_h_red_col}; + assign viv_s12 = {cac_h_blue[7:5],cac_h_red_col}; + always @(posedge clk or negedge reset_n) begin + if (~reset_n) begin + viv_s15 <= {c_dw_si{1'b0}}; + viv_s17 <= {c_dw_si{1'b0}}; + viv_s16 <= {c_dw_si{1'b0}}; + viv_s18 <= {c_dw_si{1'b0}}; + viv_s13 <= 5'b0; + viv_s14 <= 5'b0; + end else begin + if (alom_stage6_en) begin + viv_s13 <= cac_h_red[4:0]; + viv_s14 <= cac_h_blue[4:0]; + case(viv_s11) + 4'd03 : viv_s15 <= viv_s0; + 4'd04 : viv_s15 <= viv_s1; + 4'd05 : viv_s15 <= viv_s2; + 4'd06 : viv_s15 <= viv_s3; + 4'd07 : viv_s15 <= viv_s4; + 4'd08 : viv_s15 <= viv_s5; + 4'd09 : viv_s15 <= viv_s6; + 4'd10 : viv_s15 <= viv_s7; + 4'd11 : viv_s15 <= viv_s8; + 4'd12 : viv_s15 <= viv_s9; + default: viv_s15 <= viv_s10; + endcase + case(viv_s11) + 4'd03 : viv_s17 <= viv_s2; + 4'd04 : viv_s17 <= viv_s3; + 4'd05 : viv_s17 <= viv_s4; + 4'd06 : viv_s17 <= viv_s5; + 4'd07 : viv_s17 <= viv_s6; + 4'd08 : viv_s17 <= viv_s7; + 4'd09 : viv_s17 <= viv_s8; + 4'd10 : viv_s17 <= viv_s9; + 4'd11 : viv_s17 <= viv_s10; + 4'd12 : viv_s17 <= viv_s9; + default: viv_s17 <= viv_s10; + endcase + case(viv_s12) + 4'd03 : viv_s16 <= viv_s0; + 4'd04 : viv_s16 <= viv_s1; + 4'd05 : viv_s16 <= viv_s2; + 4'd06 : viv_s16 <= viv_s3; + 4'd07 : viv_s16 <= viv_s4; + 4'd08 : viv_s16 <= viv_s5; + 4'd09 : viv_s16 <= viv_s6; + 4'd10 : viv_s16 <= viv_s7; + 4'd11 : viv_s16 <= viv_s8; + 4'd12 : viv_s16 <= viv_s9; + default: viv_s16 <= viv_s10; + endcase + case(viv_s12) + 4'd03 : viv_s18 <= viv_s2; + 4'd04 : viv_s18 <= viv_s3; + 4'd05 : viv_s18 <= viv_s4; + 4'd06 : viv_s18 <= viv_s5; + 4'd07 : viv_s18 <= viv_s6; + 4'd08 : viv_s18 <= viv_s7; + 4'd09 : viv_s18 <= viv_s8; + 4'd10 : viv_s18 <= viv_s9; + 4'd11 : viv_s18 <= viv_s10; + 4'd12 : viv_s18 <= viv_s9; + default: viv_s18 <= viv_s10; + endcase + end + end + end + assign viv_s19 = (viv_s13[0]) ? viv_s17 : viv_s15; + assign viv_s20 = (viv_s13[1]) ? viv_s17 : viv_s15; + assign viv_s21 = (viv_s13[2]) ? viv_s17 : viv_s15; + assign viv_s22 = (viv_s13[3]) ? viv_s17 : viv_s15; + assign viv_s23 = (viv_s13[4]) ? viv_s17 : viv_s15; + assign viv_s24 = (viv_s14[0]) ? viv_s18 : viv_s16; + assign viv_s25 = (viv_s14[1]) ? viv_s18 : viv_s16; + assign viv_s26 = (viv_s14[2]) ? viv_s18 : viv_s16; + assign viv_s27 = (viv_s14[3]) ? viv_s18 : viv_s16; + assign viv_s28 = (viv_s14[4]) ? viv_s18 : viv_s16; + assign viv_s29 = viv_s15 + viv_s19 + + {viv_s20, 1'h0} + {viv_s21, 2'h0} + + {viv_s22, 3'h0} + {2'b10,viv_s23, 4'h0} - + {viv_s31, 4'h0}; + assign viv_s30 = viv_s16 + viv_s24 + + {viv_s25, 1'h0} + {viv_s26, 2'h0} + + {viv_s27, 3'h0} + {2'b10,viv_s28, 4'h0} - + {viv_s32, 4'h0}; + always @(posedge clk or negedge reset_n) begin + if (~reset_n) begin + viv_s31 <= {c_dw_si+1{1'b0}}; + viv_s32 <= {c_dw_si+1{1'b0}}; + viv_s33 <= {c_dw_si+1{1'b0}}; + viv_s34 <= {c_dw_si+1{1'b0}}; + out_cr <= {c_dw_si+1{1'b0}}; + out_cb <= {c_dw_si+1{1'b0}}; + viv_s35 <= 1'b0; + viv_s36 <= 1'b0; + end else begin + if (alom_stage6_en) begin + viv_s35 <= regs_dem_bypass; + viv_s31 <= red_sub; + viv_s32 <= blue_sub; + end + if (alom_stage7_en) begin + viv_s36 <= viv_s35; + viv_s33 <= viv_s29[c_dw_si+5:5]; + viv_s34 <= viv_s30[c_dw_si+5:5]; + end + if (alom_stage8_en) begin + if (viv_s36) begin + out_cr <= {1'b1,{c_dw_si{1'b0}}}; + out_cb <= {1'b1,{c_dw_si{1'b0}}}; + end else begin + out_cr <= viv_s33; + out_cb <= viv_s34; + end + end + end + end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_cac_hor_buf.v b/ispyocto/rtl/ispyocto/vsisp_isp_cac_hor_buf.v new file mode 100644 index 0000000..257886c --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_isp_cac_hor_buf.v
@@ -0,0 +1,437 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_isp_cac_hor_buf + ( + clk, + reset_n, + soft_rst, + in_val, + in_ack, + in_h_end, + in_v_end, + in_data, + regs_bayer_pat, + out_stage0, + out_stage1, + out_stage2, + out_stage3, + out_stage4, + out_stage5, + out_stage6, + out_stage7, + out_stage8, + out_stage9, + out_stage10, + alom_stage1_en, + alom_stage2_en, + alom_stage3_en, + alom_stage4_en, + alom_stage5_en, + alom_stage6_en, + alom_stage7_en, + alom_stage8_en, + alom_stage0_val, + alom_stage1_val, + alom_stage2_val, + alom_stage3_val, + alom_stage4_val, + alom_stage5_val, + alom_stage6_val, + proc_pattern_stg2, + proc_pattern_stg3, + out_h_end, + out_v_end, + out_val, + out_ack); + parameter c_dw_in = 10; + input clk; + input reset_n; + input soft_rst; + input in_val; + output in_ack; + input in_h_end; + input in_v_end; + input [c_dw_in-1:0] in_data; + input [1:0] regs_bayer_pat; + output [c_dw_in-1:0] out_stage0; + output [c_dw_in-1:0] out_stage1; + output [c_dw_in-1:0] out_stage2; + output [c_dw_in-1:0] out_stage3; + output [c_dw_in-1:0] out_stage4; + output [c_dw_in-1:0] out_stage5; + output [c_dw_in-1:0] out_stage6; + output [c_dw_in-1:0] out_stage7; + output [c_dw_in-1:0] out_stage8; + output [c_dw_in-1:0] out_stage9; + output [c_dw_in-1:0] out_stage10; + output alom_stage1_en; + output alom_stage2_en; + output alom_stage3_en; + output alom_stage4_en; + output alom_stage5_en; + output alom_stage6_en; + output alom_stage7_en; + output alom_stage8_en; + output alom_stage0_val; + output alom_stage1_val; + output alom_stage2_val; + output alom_stage3_val; + output alom_stage4_val; + output alom_stage5_val; + output alom_stage6_val; + output [1:0] proc_pattern_stg2; + output [1:0] proc_pattern_stg3; + output out_h_end; + output out_v_end; + output out_val; + input out_ack; + parameter c_dw_buf = c_dw_in+2; + reg out_h_end; + reg out_v_end; + reg out_val; + reg [1:0] proc_pattern_stg2; + reg [1:0] proc_pattern_stg3; + reg [c_dw_in-1:0] out_stage0; + reg [c_dw_in-1:0] out_stage1; + reg [c_dw_in-1:0] out_stage2; + reg [c_dw_in-1:0] out_stage3; + reg [c_dw_in-1:0] out_stage4; + reg [c_dw_in-1:0] out_stage5; + reg [c_dw_in-1:0] out_stage6; + reg [c_dw_in-1:0] out_stage7; + reg [c_dw_in-1:0] out_stage8; + reg [c_dw_in-1:0] out_stage9; + reg [c_dw_in-1:0] out_stage10; + reg viv_s0; + reg [1:0] viv_s1; + wire [c_dw_buf-1:0] viv_s2; + wire viv_s3; + reg viv_s4; + reg [c_dw_buf-1:0] viv_s5; + reg [c_dw_buf-1:0] viv_s6; + reg [c_dw_buf-1:0] viv_s7; + reg [c_dw_buf-1:0] viv_s8; + reg [c_dw_buf-1:0] viv_s9; + reg [c_dw_buf-1:0] viv_s10; + reg [c_dw_buf-1:0] viv_s11; + reg [c_dw_buf-1:0] viv_s12; + reg [c_dw_buf-1:0] viv_s13; + reg [c_dw_buf-1:0] viv_s14; + reg viv_s15; + reg viv_s16; + reg viv_s17; + reg viv_s18; + reg viv_s19; + reg viv_s20; + reg viv_s21; + reg viv_s22; + reg viv_s23; + reg viv_s24; + wire viv_s25; + wire viv_s26; + wire viv_s27; + wire viv_s28; + wire viv_s29; + wire viv_s30; + wire viv_s31; + wire viv_s32; + wire viv_s33; + wire viv_s34; + wire viv_s35; + wire viv_s36; + wire viv_s37; + wire viv_s38; + wire viv_s39; + wire viv_s40; + wire viv_s41; + wire viv_s42; + wire viv_s43; + wire viv_s44; + wire viv_s45; + wire viv_s46; + wire viv_s47; + wire viv_s48; + wire viv_s49; + wire viv_s50; + wire viv_s51; + wire viv_s52; + wire viv_s53; + wire viv_s54; + wire viv_s55; + wire viv_s56; + wire viv_s57; + wire viv_s58; + wire viv_s59; + wire viv_s60; + wire viv_s61; + wire viv_s62; + wire viv_s63; + wire viv_s64; + wire viv_s65; + wire viv_s66; + wire viv_s67; + reg viv_s68; + wire viv_s69; + reg viv_s70; + wire viv_s71; + reg viv_s72; + wire viv_s73; + wire viv_s74; + assign viv_s34 = (viv_s3 || viv_s58); + assign viv_s35 = viv_s34 && (viv_s15 || viv_s59); + assign viv_s36 = viv_s35 && (viv_s16 || viv_s60); + assign viv_s37 = viv_s36 && (viv_s17 || viv_s61); + assign viv_s38 = viv_s37 && (viv_s18 || viv_s62); + assign viv_s39 = viv_s38 && (viv_s19 || viv_s63); + assign viv_s41 = !viv_s15 || viv_s42 && viv_s34; + assign viv_s42 = !viv_s16 || viv_s43 && viv_s35; + assign viv_s43 = !viv_s17 || viv_s44 && viv_s36; + assign viv_s44 = !viv_s18 || viv_s45 && viv_s37; + assign viv_s45 = !viv_s19 || viv_s46 && viv_s38; + assign viv_s46 = !viv_s20 || viv_s52 && viv_s39; + assign viv_s47 = viv_s46; + assign viv_s48 = viv_s46; + assign viv_s49 = viv_s46; + assign viv_s50 = viv_s46; + assign viv_s51 = out_ack; + assign viv_s52 = viv_s51; + assign viv_s53 = !viv_s20 || viv_s52; + assign viv_s54 = !viv_s19 || viv_s53; + assign viv_s55 = !viv_s18 || viv_s54; + assign viv_s56 = !viv_s17 || viv_s55; + assign viv_s57 = !viv_s16 || viv_s56; + assign in_ack = (!viv_s15 || viv_s57) && viv_s4; + assign viv_s40 = (!viv_s15 || viv_s57) && viv_s4 && viv_s3; + assign viv_s64 = viv_s6[c_dw_buf-2]; + assign viv_s65 = viv_s7[c_dw_buf-2]; + assign viv_s66 = viv_s10[c_dw_buf-2]; + assign viv_s58 = viv_s5[c_dw_buf-1]; + assign viv_s59 = viv_s6[c_dw_buf-1]; + assign viv_s60 = viv_s7[c_dw_buf-1]; + assign viv_s61 = viv_s8[c_dw_buf-1]; + assign viv_s62 = viv_s9[c_dw_buf-1]; + assign viv_s63 = viv_s10[c_dw_buf-1]; + assign viv_s3 = in_val && viv_s4; + assign viv_s2 = {in_h_end, in_v_end, in_data}; + assign viv_s73 = in_h_end && in_val && in_ack; + assign viv_s74 = viv_s63 && viv_s30 && viv_s52; + always @(posedge clk or negedge reset_n) begin + if (reset_n == 1'b0) begin + viv_s5 <= {c_dw_buf{1'b0}}; + viv_s6 <= {c_dw_buf{1'b0}}; + viv_s7 <= {c_dw_buf{1'b0}}; + viv_s8 <= {c_dw_buf{1'b0}}; + viv_s9 <= {c_dw_buf{1'b0}}; + viv_s10 <= {c_dw_buf{1'b0}}; + viv_s11 <= {c_dw_buf{1'b0}}; + viv_s12 <= {c_dw_buf{1'b0}}; + viv_s13 <= {c_dw_buf{1'b0}}; + viv_s14 <= {c_dw_buf{1'b0}}; + viv_s15 <= 1'b0; + viv_s16 <= 1'b0; + viv_s17 <= 1'b0; + viv_s18 <= 1'b0; + viv_s19 <= 1'b0; + viv_s20 <= 1'b0; + viv_s21 <= 1'b0; + viv_s22 <= 1'b0; + viv_s23 <= 1'b0; + viv_s24 <= 1'b0; + viv_s4 <= 1'b1; + end else begin + if (viv_s40) viv_s5 <= viv_s2; + if (viv_s42) viv_s6 <= viv_s5; + if (viv_s43) viv_s7 <= viv_s6; + if (viv_s44) viv_s8 <= viv_s7; + if (viv_s45) viv_s9 <= viv_s8; + if (viv_s46) viv_s10 <= viv_s9; + if (viv_s47) viv_s11 <= viv_s10; + if (viv_s48) viv_s12 <= viv_s11; + if (viv_s49) viv_s13 <= viv_s12; + if (viv_s50) viv_s14 <= viv_s13; + if (soft_rst) begin + viv_s15 <= 1'b0; + viv_s16 <= 1'b0; + viv_s17 <= 1'b0; + viv_s18 <= 1'b0; + viv_s19 <= 1'b0; + viv_s20 <= 1'b0; + viv_s21 <= 1'b0; + viv_s22 <= 1'b0; + viv_s23 <= 1'b0; + viv_s24 <= 1'b0; + viv_s4 <= 1'b1; + end else begin + if (viv_s41) viv_s15 <= viv_s3; + if (viv_s42) viv_s16 <= viv_s25; + if (viv_s43) viv_s17 <= viv_s26; + if (viv_s44) viv_s18 <= viv_s27; + if (viv_s45) viv_s19 <= viv_s28; + if (viv_s46) viv_s20 <= viv_s29; + if (viv_s47) viv_s21 <= viv_s30; + if (viv_s48) viv_s22 <= viv_s31; + if (viv_s49) viv_s23 <= viv_s32; + if (viv_s50) viv_s24 <= viv_s33; + if (viv_s73) viv_s4 <= 1'b0; + else if (viv_s74) viv_s4 <= 1'b1; + end + end + end + assign viv_s25 = viv_s15 && (viv_s3 || viv_s58); + assign viv_s26 = viv_s16 && (viv_s25 || viv_s59); + assign viv_s27 = viv_s17 && (viv_s26 || viv_s60); + assign viv_s28 = viv_s18 && (viv_s27 || viv_s61); + assign viv_s29 = viv_s19 && (viv_s28 || viv_s62); + assign viv_s30 = viv_s20 && (viv_s29 || viv_s63); + assign viv_s31 = viv_s21 && viv_s30; + assign viv_s32 = viv_s22 && viv_s31; + assign viv_s33 = viv_s23 && viv_s32; + always @(posedge clk or negedge reset_n) begin + if (reset_n == 1'b0) begin + viv_s0 <= 1'b0; + viv_s1 <= 2'd0; + end else begin + if (soft_rst || out_v_end && out_h_end && out_val) begin + viv_s0 <= 1'b0; + end else if (in_val && in_ack) begin + viv_s0 <= 1'b1; + end + if (~viv_s0) + viv_s1 <= regs_bayer_pat; + end + end + always @(posedge clk or negedge reset_n) begin + if (reset_n == 1'b0) begin + proc_pattern_stg2 <= 2'd0; + proc_pattern_stg3 <= 2'd0; + end else if (soft_rst) begin + proc_pattern_stg2 <= 2'd0; + proc_pattern_stg3 <= 2'd0; + end else if (~viv_s0 && ~in_val) begin + proc_pattern_stg2 <= viv_s1; + end else begin + if (viv_s42 && viv_s26) begin + if (viv_s59) begin + proc_pattern_stg2[0] <= viv_s1[0]; + if (viv_s64) begin + proc_pattern_stg2[1] <= viv_s1[1]; + end else begin + proc_pattern_stg2[1] <= ~proc_pattern_stg2[1]; + end + end else begin + proc_pattern_stg2[0] <= ~proc_pattern_stg2[0]; + end + end + if (viv_s43) begin + proc_pattern_stg3 <= proc_pattern_stg2; + end + end + end + always @(*) begin + if (viv_s3) out_stage0 = viv_s2[c_dw_in-1:0]; + else if (viv_s16) out_stage0 = viv_s6[c_dw_in-1:0]; + else if (viv_s18) out_stage0 = viv_s8[c_dw_in-1:0]; + else if (viv_s20) out_stage0 = viv_s10[c_dw_in-1:0]; + else out_stage0 = viv_s2[c_dw_in-1:0]; + if (viv_s15) out_stage1 = viv_s5[c_dw_in-1:0]; + else if (viv_s17) out_stage1 = viv_s7[c_dw_in-1:0]; + else if (viv_s19) out_stage1 = viv_s9[c_dw_in-1:0]; + else out_stage1 = viv_s5[c_dw_in-1:0]; + if (viv_s16) out_stage2 = viv_s6[c_dw_in-1:0]; + else if (viv_s18) out_stage2 = viv_s8[c_dw_in-1:0]; + else if (viv_s20) out_stage2 = viv_s10[c_dw_in-1:0]; + else out_stage2 = viv_s6[c_dw_in-1:0]; + if (viv_s17) out_stage3 = viv_s7[c_dw_in-1:0]; + else if (viv_s19) out_stage3 = viv_s9[c_dw_in-1:0]; + else out_stage3 = viv_s7[c_dw_in-1:0]; + if (viv_s18) out_stage4 = viv_s8[c_dw_in-1:0]; + else if (viv_s20) out_stage4 = viv_s10[c_dw_in-1:0]; + else out_stage4 = viv_s8[c_dw_in-1:0]; + out_stage5 = viv_s9[c_dw_in-1:0]; + if (viv_s20) out_stage6 = viv_s10[c_dw_in-1:0]; + else if (viv_s18) out_stage6 = viv_s8[c_dw_in-1:0]; + else out_stage6 = viv_s10[c_dw_in-1:0]; + if (viv_s21) out_stage7 = viv_s11[c_dw_in-1:0]; + else if (viv_s19) out_stage7 = viv_s9[c_dw_in-1:0]; + else out_stage7 = viv_s11[c_dw_in-1:0]; + if (viv_s22) out_stage8 = viv_s12[c_dw_in-1:0]; + else if (viv_s20) out_stage8 = viv_s10[c_dw_in-1:0]; + else if (viv_s18) out_stage8 = viv_s8[c_dw_in-1:0]; + else out_stage8 = viv_s12[c_dw_in-1:0]; + if (viv_s23) out_stage9 = viv_s13[c_dw_in-1:0]; + else if (viv_s21) out_stage9 = viv_s11[c_dw_in-1:0]; + else if (viv_s19) out_stage9 = viv_s9[c_dw_in-1:0]; + else out_stage9 = viv_s13[c_dw_in-1:0]; + if (viv_s24) out_stage10 = viv_s14[c_dw_in-1:0]; + else if (viv_s22) out_stage10 = viv_s12[c_dw_in-1:0]; + else if (viv_s20) out_stage10 = viv_s10[c_dw_in-1:0]; + else if (viv_s18) out_stage10 = viv_s8[c_dw_in-1:0]; + else out_stage10 = viv_s14[c_dw_in-1:0]; + end + assign viv_s67 = viv_s63 && viv_s30; + assign viv_s69 = viv_s66 && viv_s30; + assign viv_s71 = viv_s30; + assign alom_stage1_en = viv_s40; + assign alom_stage2_en = viv_s42; + assign alom_stage3_en = viv_s43; + assign alom_stage4_en = viv_s44; + assign alom_stage5_en = viv_s45; + assign alom_stage6_en = viv_s46; + assign alom_stage7_en = viv_s52; + assign alom_stage8_en = viv_s51; + assign alom_stage0_val = viv_s3; + assign alom_stage1_val = viv_s15; + assign alom_stage2_val = viv_s16; + assign alom_stage3_val = viv_s17; + assign alom_stage4_val = viv_s18; + assign alom_stage5_val = viv_s19; + assign alom_stage6_val = viv_s20; + always @(posedge clk or negedge reset_n) begin + if (reset_n == 1'b0) begin + viv_s68 <= 0; + viv_s70 <= 0; + viv_s72 <= 0; + out_h_end <= 0; + out_v_end <= 0; + out_val <= 0; + end else begin + if (viv_s52) begin + viv_s68 <= viv_s67; + viv_s70 <= viv_s69; + end + if (viv_s51) begin + out_h_end <= viv_s68; + out_v_end <= viv_s70; + end + if (soft_rst) + viv_s72 <= 1'b0; + else if (viv_s52) + viv_s72 <= viv_s71; + if (soft_rst) + out_val <= 1'b0; + else if (viv_s51) + out_val <= viv_s72; + end + end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_cac_ver.v b/ispyocto/rtl/ispyocto/vsisp_isp_cac_ver.v new file mode 100644 index 0000000..227a531 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_isp_cac_ver.v
@@ -0,0 +1,230 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_isp_cac_ver + ( + clk, + reset_n, + in_val, + in_ack, + in_h_end, + in_v_end, + mem_data_1t, + mem_data_m2, + mem_data_m3, + mem_data_m4, + mem_data_m5, + mem_data_m6, + mem_data_7b, + cv_mask, + regs_dem_bypass, + cac_v_sel_1, + cac_v_sel_2, + cac_v_sel_3, + cac_v_coef, + cac_v_filt_disable, + cac_v_data_out, + out_h_end, + out_v_end, + out_val, + out_ack); +`include "vsisp_isp.vh" + input clk; + input reset_n; + input in_val; + output in_ack; + input in_h_end; + input in_v_end; + input [c_dw_si-1:0] mem_data_1t; + input [c_dw_si-1:0] mem_data_m2; + input [c_dw_si-1:0] mem_data_m3; + input [c_dw_si-1:0] mem_data_m4; + input [c_dw_si-1:0] mem_data_m5; + input [c_dw_si-1:0] mem_data_m6; + input [c_dw_si-1:0] mem_data_7b; + input [1:0] cv_mask; + input regs_dem_bypass; + input [3:0] cac_v_sel_1; + input [3:0] cac_v_sel_2; + input [3:0] cac_v_sel_3; + input [4:0] cac_v_coef; + input cac_v_filt_disable; + output [c_dw_si-1:0] cac_v_data_out; + output out_h_end; + output out_v_end; + output out_val; + input out_ack; + wire viv_s0; + reg [c_dw_si-1:0] viv_s1; + reg [c_dw_si-1:0] viv_s2; + reg [c_dw_si-1:0] viv_s3; + reg [c_dw_si-1:0] viv_s4; + reg [c_dw_si-1:0] viv_s5; + reg [c_dw_si-1:0] viv_s6; + wire [c_dw_si:0] viv_s7; + wire [c_dw_si:0] viv_s8; + wire [c_dw_si:0] viv_s9; + wire [c_dw_si:0] viv_s10; + wire [c_dw_si:0] viv_s11; + wire [c_dw_si:0] viv_s12; + wire [c_dw_si:0] viv_s13; + wire [c_dw_si-1:0] viv_s14; + wire [c_dw_si-1:0] viv_s15; + wire [c_dw_si-1:0] viv_s16; + wire [c_dw_si-1:0] viv_s17; + wire [c_dw_si-1:0] viv_s18; + wire [c_dw_si+5:0] viv_s19; + wire [c_dw_si+4:0] viv_s20; + wire [c_dw_si:0] viv_s21; + wire [c_dw_si-1:0] viv_s22; + wire [c_dw_si+4:0] viv_s23; + wire [c_dw_si+2:0] viv_s24; + wire [c_dw_si+2:0] viv_s25; + wire [c_dw_si+2:0] viv_s26; + wire [c_dw_si+4:0] viv_s27; + reg [c_dw_si-1:0] cac_v_data_out; + reg out_h_end; + reg out_v_end; + reg out_val; + always @(*) + begin + case(cac_v_sel_1) + 4'd4 : viv_s1 = mem_data_1t; + 4'd5 : viv_s1 = mem_data_1t; + 4'd6 : viv_s1 = mem_data_m2; + 4'd7 : viv_s1 = mem_data_m3; + 4'd8 : viv_s1 = mem_data_m4; + 4'd9 : viv_s1 = mem_data_m5; + 4'd10 : viv_s1 = mem_data_m6; + default: viv_s1 = mem_data_7b; + endcase + end + always @(*) + begin + case(cac_v_sel_1) + 4'd4 : viv_s4 = mem_data_m2; + 4'd5 : viv_s4 = mem_data_m3; + 4'd6 : viv_s4 = mem_data_m4; + 4'd7 : viv_s4 = mem_data_m5; + 4'd8 : viv_s4 = mem_data_m6; + default: viv_s4 = mem_data_7b; + endcase + end + always @(*) + begin + case(cac_v_sel_2) + 4'd4 : viv_s2 = mem_data_1t; + 4'd5 : viv_s2 = mem_data_1t; + 4'd6 : viv_s2 = mem_data_m2; + 4'd7 : viv_s2 = mem_data_m3; + 4'd8 : viv_s2 = mem_data_m4; + 4'd9 : viv_s2 = mem_data_m5; + 4'd10 : viv_s2 = mem_data_m6; + default: viv_s2 = mem_data_7b; + endcase + end + always @(*) + begin + case(cac_v_sel_2) + 4'd4 : viv_s5 = mem_data_m2; + 4'd5 : viv_s5 = mem_data_m3; + 4'd6 : viv_s5 = mem_data_m4; + 4'd7 : viv_s5 = mem_data_m5; + 4'd8 : viv_s5 = mem_data_m6; + default: viv_s5 = mem_data_7b; + endcase + end + always @(*) + begin + case(cac_v_sel_3) + 4'd4 : viv_s3 = mem_data_1t; + 4'd5 : viv_s3 = mem_data_1t; + 4'd6 : viv_s3 = mem_data_m2; + 4'd7 : viv_s3 = mem_data_m3; + 4'd8 : viv_s3 = mem_data_m4; + 4'd9 : viv_s3 = mem_data_m5; + 4'd10 : viv_s3 = mem_data_m6; + default: viv_s3 = mem_data_7b; + endcase + end + always @(*) + begin + case(cac_v_sel_3) + 4'd4 : viv_s6 = mem_data_m2; + 4'd5 : viv_s6 = mem_data_m3; + 4'd6 : viv_s6 = mem_data_m4; + 4'd7 : viv_s6 = mem_data_m5; + 4'd8 : viv_s6 = mem_data_m6; + default: viv_s6 = mem_data_7b; + endcase + end + assign viv_s7 = {1'b0, viv_s1} + viv_s3 +1; + assign viv_s8 = {1'b0, viv_s4} + viv_s6 +1; + assign viv_s9 = (cac_v_coef[0]) ? viv_s8 : viv_s7; + assign viv_s10 = (cac_v_coef[1]) ? viv_s8 : viv_s7; + assign viv_s11 = (cac_v_coef[2]) ? viv_s8 : viv_s7; + assign viv_s12 = (cac_v_coef[3]) ? viv_s8 : viv_s7; + assign viv_s13 = (cac_v_coef[4]) ? viv_s7 : viv_s8; + assign viv_s14 = (cac_v_coef[0]) ? viv_s5 : viv_s2; + assign viv_s15 = (cac_v_coef[1]) ? viv_s5 : viv_s2; + assign viv_s16 = (cac_v_coef[2]) ? viv_s5 : viv_s2; + assign viv_s17 = (cac_v_coef[3]) ? viv_s5 : viv_s2; + assign viv_s18 = (cac_v_coef[4]) ? viv_s5 : viv_s2; + assign viv_s19 = {5'h0, viv_s7} + viv_s9 + + {viv_s10, 1'h0} + {viv_s11, 2'h0} + + {viv_s12, 3'h0} + {viv_s13, 4'h0}; + assign viv_s20 = {5'h0, viv_s2} + viv_s14 + + {viv_s15, 1'h0} + {viv_s16, 2'h0} + + {viv_s17, 3'h4} + {viv_s18, 4'hC}; + assign viv_s21 = viv_s19[c_dw_si+5:5]; + assign viv_s22 = viv_s20[c_dw_si+4:5]; + assign viv_s23 = {1'b0, viv_s21,3'b110}; + assign viv_s24 = {viv_s22,3'b110}; + assign viv_s25 = (cv_mask == 2'd1) ? {c_dw_si+3{1'b0}} : + (cv_mask == 2'd2) ? {1'b0, viv_s21,1'b1} : + {viv_s21,2'b10}; + assign viv_s26 = (cv_mask == 2'd1) ? {viv_s22,3'b100} : + (cv_mask == 2'd2) ? {1'b0, viv_s22,2'b11} : + {{c_dw_si+1{1'b0}},2'b10}; + assign viv_s27 = viv_s23 + viv_s24 + viv_s25 + viv_s26; + assign in_ack = ~out_val || out_ack; + assign viv_s0 = ~out_val || out_ack; + always @(posedge clk or negedge reset_n) begin + if (~reset_n) begin + out_v_end <= 1'b0; + out_h_end <= 1'b0; + out_val <= 1'b0; + cac_v_data_out <= {c_dw_si{1'b0}}; + end else if (viv_s0) begin + out_v_end <= in_v_end; + out_h_end <= in_h_end; + out_val <= in_val; + if (regs_dem_bypass) + cac_v_data_out <= {c_dw_si{1'b0}}; + else if ((cv_mask == 2'b00) || cac_v_filt_disable) + cac_v_data_out <= viv_s22; + else + cac_v_data_out <= viv_s27[c_dw_si+4:5]; + end + end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_cross_talk.v b/ispyocto/rtl/ispyocto/vsisp_isp_cross_talk.v new file mode 100644 index 0000000..bce280d --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_isp_cross_talk.v
@@ -0,0 +1,150 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_isp_cross_talk ( + clk, + reset_n, + soft_rst, + in_data, + in_h_end, + in_v_end, + in_val, + in_ack, + out_data, + out_h_end, + out_v_end, + out_val, + out_ack, + coeff0, + coeff1, + coeff2, + coeff3, + coeff4, + coeff5, + coeff6, + coeff7, + coeff8, + offset_r, + offset_g, + offset_b + ); +`include "vsisp_isp.vh" +input clk; +input reset_n; +input soft_rst; +input [(3*c_dw_si)-1:0] in_data; +input in_h_end; +input in_v_end; +input in_val; +output in_ack; +output [(3*c_dw_si)-1:0] out_data; +output out_h_end; +output out_v_end; +output out_val; +input out_ack; +input [c_dw_crt_coeff-1:0] coeff0; +input [c_dw_crt_coeff-1:0] coeff1; +input [c_dw_crt_coeff-1:0] coeff2; +input [c_dw_crt_coeff-1:0] coeff3; +input [c_dw_crt_coeff-1:0] coeff4; +input [c_dw_crt_coeff-1:0] coeff5; +input [c_dw_crt_coeff-1:0] coeff6; +input [c_dw_crt_coeff-1:0] coeff7; +input [c_dw_crt_coeff-1:0] coeff8; +input [c_dw_si-1:0] offset_r; +input [c_dw_si-1:0] offset_g; +input [c_dw_si-1:0] offset_b; +reg [(3*c_dw_si)-1:0] out_data; +reg out_h_end; +reg out_v_end; +reg out_val; +wire in_ack; +wire [c_dw_si-1:0] viv_s0; +wire [c_dw_si-1:0] viv_s1; +wire [c_dw_si-1:0] viv_s2; +wire [c_dw_si-1:0] viv_s3; +wire [c_dw_si-1:0] viv_s4; +wire [c_dw_si-1:0] viv_s5; +wire [c_dw_si+5:0] viv_s6; +wire [c_dw_si+5:0] viv_s7; +wire [c_dw_si+5:0] viv_s8; +vsisp_isp_crt_tri_mul_add u_r_isp_crt_tri_mul_add( + .coeff_r(coeff0), + .coeff_g(coeff1), + .coeff_b(coeff2), + .offset(offset_r), + .data_r(viv_s3), + .data_g(viv_s4), + .data_b(viv_s5), + .data_out(viv_s6)); +vsisp_isp_crt_tri_mul_add u_g_isp_crt_tri_mul_add( + .coeff_r(coeff3), + .coeff_g(coeff4), + .coeff_b(coeff5), + .offset(offset_g), + .data_r(viv_s3), + .data_g(viv_s4), + .data_b(viv_s5), + .data_out(viv_s7)); +vsisp_isp_crt_tri_mul_add u_b_isp_crt_tri_mul_add( + .coeff_r(coeff6), + .coeff_g(coeff7), + .coeff_b(coeff8), + .offset(offset_b), + .data_r(viv_s3), + .data_g(viv_s4), + .data_b(viv_s5), + .data_out(viv_s8)); +assign in_ack = ~out_val | out_ack; +assign viv_s3 = in_data[(3*c_dw_si)-1:2*c_dw_si]; +assign viv_s4 = in_data[(2*c_dw_si)-1:c_dw_si]; +assign viv_s5 = in_data[c_dw_si-1:0]; +assign viv_s0 = (viv_s6[c_dw_si+5] ) ? {c_dw_si{1'b0}} : + ((viv_s6[c_dw_si+4:c_dw_si] > 5'b0) ? {c_dw_si{1'b1}} : + viv_s6[c_dw_si-1:0]); +assign viv_s1 = (viv_s7[c_dw_si+5] ) ? {c_dw_si{1'b0}} : + ((viv_s7[c_dw_si+4:c_dw_si] > 5'b0) ? {c_dw_si{1'b1}} : + viv_s7[c_dw_si-1:0]); +assign viv_s2 = (viv_s8[c_dw_si+5] ) ? {c_dw_si{1'b0}} : + ((viv_s8[c_dw_si+4:c_dw_si] > 5'b0) ? {c_dw_si{1'b1}} : + viv_s8[c_dw_si-1:0]); +always @ (posedge clk or negedge reset_n) begin + if(~reset_n) begin + out_data <= {3*c_dw_si{1'b0}}; + out_h_end <= 1'b0; + out_v_end <= 1'b0; + out_val <= 1'b0; + end else begin + if (soft_rst) begin + out_h_end <= 1'b0; + out_v_end <= 1'b0; + out_val <= 1'b0; + end else if (in_ack) begin + out_data <= {viv_s0,viv_s1,viv_s2}; + out_h_end <= in_h_end; + out_v_end <= in_v_end; + out_val <= in_val; + end + end +end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_crt_tri_mul_add.v b/ispyocto/rtl/ispyocto/vsisp_isp_crt_tri_mul_add.v new file mode 100644 index 0000000..3f3e339 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_isp_crt_tri_mul_add.v
@@ -0,0 +1,68 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_isp_crt_tri_mul_add ( + coeff_r, + coeff_g, + coeff_b, + offset, + data_r, + data_g, + data_b, + data_out + ); +`include "vsisp_isp.vh" +parameter c_dw_prod = c_dw_crt_coeff + (c_dw_si+1) -1; + input [c_dw_crt_coeff-1:0] coeff_r; + input [c_dw_crt_coeff-1:0] coeff_g; + input [c_dw_crt_coeff-1:0] coeff_b; + input [c_dw_si-1:0] offset; + input [c_dw_si-1:0] data_r; + input [c_dw_si-1:0] data_g; + input [c_dw_si-1:0] data_b; + output signed [(c_dw_prod)-6:0] data_out; + wire signed [c_dw_prod-1:0] viv_s0; + wire signed [c_dw_prod-1:0] viv_s1; + wire signed [c_dw_prod-1:0] viv_s2; + wire signed [(c_dw_prod+1)-5:0] viv_s3; + wire signed [c_dw_crt_coeff-1:0] viv_s4; + wire signed [c_dw_si:0] viv_s5; + wire signed [c_dw_crt_coeff-1:0] viv_s6; + wire signed [c_dw_si:0] viv_s7; + wire signed [c_dw_crt_coeff-1:0] viv_s8; + wire signed [c_dw_si:0] viv_s9; + assign viv_s4 = coeff_r; + assign viv_s5 = {1'b0,data_r}; + assign viv_s6 = coeff_g; + assign viv_s7 = {1'b0,data_g}; + assign viv_s8 = coeff_b; + assign viv_s9 = {1'b0,data_b}; + assign viv_s0 = viv_s4 * viv_s5; + assign viv_s1 = viv_s6 * viv_s7; + assign viv_s2 = viv_s8 * viv_s9; + assign viv_s3 = {{2{viv_s0[c_dw_prod-1]}}, viv_s0[c_dw_prod-1:5]} + + {{2{viv_s1[c_dw_prod-1]}}, viv_s1[c_dw_prod-1:5]} + + {{2{viv_s2[c_dw_prod-1]}}, viv_s2[c_dw_prod-1:5]} + + {{(c_dw_crt_coeff-5){offset[c_dw_si-1]}}, offset, 2'd2 }; + assign data_out = viv_s3[c_dw_prod-4:2]; +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_csm.v b/ispyocto/rtl/ispyocto/vsisp_isp_csm.v new file mode 100644 index 0000000..82baef7 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_isp_csm.v
@@ -0,0 +1,178 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_isp_csm ( + clk, + reset_n, + soft_rst, + in_data, + in_h_end, + in_v_end, + in_val, + in_ack, + out_data, + out_h_end, + out_v_end, + out_val, + out_ack, + coeff0, + coeff1, + coeff2, + coeff3, + coeff4, + coeff5, + coeff6, + coeff7, + coeff8, + y_range, + c_range + ); +`include "vsisp_isp.vh" +input clk; +input reset_n; +input soft_rst; +input [(3*c_dw_do)-1:0] in_data; +input in_h_end; +input in_v_end; +input in_val; +output in_ack; +output [(3*c_dw_do)-1:0] out_data; +output out_h_end; +output out_v_end; +output out_val; +input out_ack; +input [c_dw_csm_coeff-1:0] coeff0; +input [c_dw_csm_coeff-1:0] coeff1; +input [c_dw_csm_coeff-1:0] coeff2; +input [c_dw_csm_coeff-1:0] coeff3; +input [c_dw_csm_coeff-1:0] coeff4; +input [c_dw_csm_coeff-1:0] coeff5; +input [c_dw_csm_coeff-1:0] coeff6; +input [c_dw_csm_coeff-1:0] coeff7; +input [c_dw_csm_coeff-1:0] coeff8; +input y_range; +input c_range; +reg [(3*c_dw_do)-1:0] out_data; +reg out_h_end; +reg out_v_end; +reg out_val; +wire in_ack; +reg [c_dw_do-1:0] viv_s0; +reg [c_dw_do-1:0] viv_s1; +reg [c_dw_do-1:0] viv_s2; +wire [c_dw_do-1:0] viv_s3; +wire [c_dw_do-1:0] viv_s4; +wire [c_dw_do-1:0] viv_s5; +wire [c_dw_do+3:0] viv_s6; +wire [c_dw_do+3:0] viv_s7; +wire [c_dw_do+3:0] viv_s8; +wire [c_dw_do+3:0] viv_s9; +wire [c_dw_do+3:0] viv_s10; +wire [c_dw_do+3:0] viv_s11; +wire viv_s12; +wire viv_s13; +wire viv_s14; +vsisp_isp_csm_tri_mul_add #(.c_dw_do(c_dw_do)) u_y_isp_csm_tri_mul_add( + .coeff_r(coeff0), + .coeff_g(coeff1), + .coeff_b(coeff2), + .data_r(viv_s3), + .data_g(viv_s4), + .data_b(viv_s5), + .data_out(viv_s6)); +vsisp_isp_csm_tri_mul_add #(.c_dw_do(c_dw_do)) u_cb_isp_csm_tri_mul_add( + .coeff_r(coeff3), + .coeff_g(coeff4), + .coeff_b(coeff5), + .data_r(viv_s3), + .data_g(viv_s4), + .data_b(viv_s5), + .data_out(viv_s7)); +vsisp_isp_csm_tri_mul_add #(.c_dw_do(c_dw_do)) u_cr_isp_csm_tri_mul_add( + .coeff_r(coeff6), + .coeff_g(coeff7), + .coeff_b(coeff8), + .data_r(viv_s3), + .data_g(viv_s4), + .data_b(viv_s5), + .data_out(viv_s8)); +assign in_ack = ~out_val | out_ack; +assign viv_s3 = in_data[(3*c_dw_do)-1 : 2*c_dw_do]; +assign viv_s4 = in_data[(2*c_dw_do)-1 : c_dw_do]; +assign viv_s5 = in_data[ c_dw_do-1 : 0]; +assign viv_s9 = viv_s6 + {~y_range, 4'd0, {c_dw_do-8{1'b0}}}; +assign viv_s10 = viv_s7 + { 8'd128, {c_dw_do-8{1'b0}}}; +assign viv_s11 = viv_s8 + { 8'd128, {c_dw_do-8{1'b0}}}; +assign viv_s12 = (viv_s9[c_dw_do+3] || (viv_s9[c_dw_do+2 : c_dw_do-4] == 7'd0)); +assign viv_s13 = (viv_s10[c_dw_do+3] || (viv_s10[c_dw_do+2 : c_dw_do-4] == 7'd0)); +assign viv_s14 = (viv_s11[c_dw_do+3] || (viv_s11[c_dw_do+2 : c_dw_do-4] == 7'd0)); +always@(*) + if (y_range) begin + if (viv_s9[c_dw_do+3]) viv_s0 = {c_dw_do {1'b0}}; + else if (viv_s9[c_dw_do+2 : c_dw_do ] != 3'd0) viv_s0 = {c_dw_do {1'b1}}; + else viv_s0 = viv_s9[c_dw_do-1 : 0]; + end else begin + if (viv_s12) viv_s0 = {8'd16 , {c_dw_do-8{1'b0}}}; + else if (viv_s9[c_dw_do+2 : c_dw_do-8] > 11'd235) viv_s0 = {8'd235, {c_dw_do-8{1'b0}}}; + else viv_s0 = viv_s9[c_dw_do-1 : 0]; + end +always@(*) + if (c_range) begin + if (viv_s10[c_dw_do+3]) viv_s1 = {c_dw_do {1'b0}}; + else if (viv_s10[c_dw_do+2 : c_dw_do] != 3'd0) viv_s1 = {c_dw_do {1'b1}}; + else viv_s1 = viv_s10[c_dw_do-1 : 0]; + end else begin + if (viv_s13) viv_s1 = {8'd16 , {c_dw_do-8{1'b0}}}; + else if (viv_s10[c_dw_do+2 : c_dw_do-8] > 11'd240) viv_s1 = {8'd240, {c_dw_do-8{1'b0}}}; + else viv_s1 = viv_s10[c_dw_do-1 : 0]; + end +always@(*) + if (c_range) begin + if (viv_s11[c_dw_do+3]) viv_s2 = {c_dw_do {1'b0}}; + else if (viv_s11[c_dw_do+2 : c_dw_do] != 3'd0) viv_s2 = {c_dw_do {1'b1}}; + else viv_s2 = viv_s11[c_dw_do-1 : 0]; + end else begin + if (viv_s14) viv_s2 = {8'd16 , {c_dw_do-8{1'b0}}}; + else if (viv_s11[c_dw_do+2 : c_dw_do-8] > 11'd240) viv_s2 = {8'd240, {c_dw_do-8{1'b0}}}; + else viv_s2 = viv_s11[c_dw_do-1 : 0]; + end +always @ (posedge clk or negedge reset_n) begin + if(~reset_n) begin + out_data <= {3*c_dw_do{1'b0}}; + out_h_end <= 1'b0; + out_v_end <= 1'b0; + out_val <= 1'b0; + end else begin + if (soft_rst) begin + out_h_end <= 1'b0; + out_v_end <= 1'b0; + out_val <= 1'b0; + end else if (in_ack) begin + out_data <= {viv_s0,viv_s1,viv_s2}; + out_h_end <= in_h_end; + out_v_end <= in_v_end; + out_val <= in_val; + end + end +end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_csm_fix.v b/ispyocto/rtl/ispyocto/vsisp_isp_csm_fix.v new file mode 100644 index 0000000..431301c --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_isp_csm_fix.v
@@ -0,0 +1,127 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_isp_csm_fix ( + clk, + reset_n, + soft_rst, + in_data, + in_h_end, + in_v_end, + in_val, + regs_awb_meas_mode, + exp_alt_mode, + out_data, + out_y_exp, + out_h_end, + out_v_end, + out_val, + out_ack + ); +`include "vsisp_isp.vh" +input clk; +input reset_n; +input soft_rst; +input [(3*c_dw_si)-1:0] in_data; +input in_h_end; +input in_v_end; +input in_val; +input regs_awb_meas_mode; +input exp_alt_mode; +output [23:0] out_data; +output [ 7:0] out_y_exp; +output out_h_end; +output out_v_end; +output out_val; +input out_ack; +reg [23:0] out_data; +reg [ 7:0] out_y_exp; +reg out_h_end; +reg out_v_end; +reg out_val; +wire viv_s0; +wire [7:0] viv_s1; +wire [7:0] viv_s2; +wire [7:0] viv_s3; +wire [7:0] viv_s4; +wire [c_dw_si-1:0] viv_s5; +wire [c_dw_si-1:0] viv_s6; +wire [c_dw_si-1:0] viv_s7; +wire [10:0] viv_s8; +wire [10:0] viv_s9; +wire [10:0] viv_s10; +wire [10:0] viv_s11; +wire [13:0] viv_s12; +wire [13:0] viv_s13; +wire [13:0] viv_s14; +wire [ 9:0] viv_s15; +wire [12:0] viv_s16; +wire [15:0] viv_s17; +assign viv_s0 = ~out_val | out_ack; +assign viv_s5 = in_data[(3*c_dw_si)-1:2*c_dw_si]; +assign viv_s6 = in_data[(2*c_dw_si)-1:c_dw_si]; +assign viv_s7 = in_data[c_dw_si-1:0]; +assign viv_s8 = viv_s7[c_dw_si-1:c_dw_si-10] - viv_s7[c_dw_si-1:c_dw_si-7]; +assign viv_s9 = viv_s6[c_dw_si-1:c_dw_si-8] + viv_s6[c_dw_si-1:c_dw_si-7]; +assign viv_s10 = viv_s5[c_dw_si-1:c_dw_si-10] + viv_s5[c_dw_si-1:c_dw_si-7]; +assign viv_s11 = viv_s5[c_dw_si-1:c_dw_si-10] - viv_s5[c_dw_si-1:c_dw_si-7]; +assign viv_s12 = 13'd64 + viv_s5[c_dw_si-1:c_dw_si-8] + viv_s6[c_dw_si-1:c_dw_si-9] + viv_s8[10:3]; +assign viv_s13 = 13'd512 - viv_s10[10:3] - viv_s6[c_dw_si-1:c_dw_si-8] - viv_s9[10:3] + viv_s8[10:1]; +assign viv_s14 = 13'd512 + viv_s11[10:1] - viv_s9 - viv_s7[c_dw_si-1:c_dw_si-6]; +assign viv_s2 = viv_s12[9:2]; +assign viv_s3 = viv_s13[9:2]; +assign viv_s4 = viv_s14[9:2]; +assign viv_s15 = viv_s5[c_dw_si-1:c_dw_si-8] + viv_s6[c_dw_si-1:c_dw_si-8] + viv_s7[c_dw_si-1:c_dw_si-8]; +assign viv_s16 = {viv_s15,2'b0} + viv_s15; +assign viv_s17 = {viv_s16,4'b0} + viv_s16 ; +assign viv_s1 = viv_s17[15:8]; +always @ (posedge clk or negedge reset_n) begin + if(~reset_n) begin + out_data <= 24'b0; + out_y_exp <= 8'b0; + out_h_end <= 1'b0; + out_v_end <= 1'b0; + out_val <= 1'b0; + end else begin + if (soft_rst) begin + out_h_end <= 1'b0; + out_v_end <= 1'b0; + out_val <= 1'b0; + end else if (viv_s0) begin + if (regs_awb_meas_mode) + out_data <= {viv_s6[c_dw_si-1:c_dw_si-8], + viv_s7[c_dw_si-1:c_dw_si-8], + viv_s5[c_dw_si-1:c_dw_si-8]}; + else + out_data <= {viv_s2,viv_s3,viv_s4}; + if (exp_alt_mode) + out_y_exp <= viv_s1; + else + out_y_exp <= viv_s2; + out_h_end <= in_h_end; + out_v_end <= in_v_end; + out_val <= in_val; + end + end +end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_csm_tri_mul_add.v b/ispyocto/rtl/ispyocto/vsisp_isp_csm_tri_mul_add.v new file mode 100644 index 0000000..ed0d2e5 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_isp_csm_tri_mul_add.v
@@ -0,0 +1,66 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_isp_csm_tri_mul_add ( + coeff_r, + coeff_g, + coeff_b, + data_r, + data_g, + data_b, + data_out + ); +`include "vsisp_isp.vh" +parameter c_dw_prod = c_dw_csm_coeff + (c_dw_do+1) -1; + input [c_dw_csm_coeff-1:0] coeff_r; + input [c_dw_csm_coeff-1:0] coeff_g; + input [c_dw_csm_coeff-1:0] coeff_b; + input [c_dw_do-1:0] data_r; + input [c_dw_do-1:0] data_g; + input [c_dw_do-1:0] data_b; + output signed [c_dw_prod-6:0] data_out; + wire signed [c_dw_prod-1:0] viv_s0; + wire signed [c_dw_prod-1:0] viv_s1; + wire signed [c_dw_prod-1:0] viv_s2; + wire signed [c_dw_prod+1:0] viv_s3; + wire signed [c_dw_csm_coeff-1:0] viv_s4; + wire signed [c_dw_do:0] viv_s5; + wire signed [c_dw_csm_coeff-1:0] viv_s6; + wire signed [c_dw_do:0] viv_s7; + wire signed [c_dw_csm_coeff-1:0] viv_s8; + wire signed [c_dw_do:0] viv_s9; + assign viv_s4 = coeff_r; + assign viv_s5 = {1'b0,data_r}; + assign viv_s6 = coeff_g; + assign viv_s7 = {1'b0,data_g}; + assign viv_s8 = coeff_b; + assign viv_s9 = {1'b0,data_b}; + assign viv_s0 = viv_s4 * viv_s5; + assign viv_s1 = viv_s6 * viv_s7; + assign viv_s2 = viv_s8 * viv_s9; + assign viv_s3 = {{2{viv_s0[c_dw_prod-1]}}, viv_s0} + + {{2{viv_s1[c_dw_prod-1]}}, viv_s1} + + {{2{viv_s2[c_dw_prod-1]}}, viv_s2} + + {{c_dw_do+4 {1'b0}}, 1'b1, {c_dw_csm_coeff-3 {1'b0}}}; + assign data_out = viv_s3[c_dw_prod+1 : c_dw_csm_coeff-2]; +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_demosaic5x.v b/ispyocto/rtl/ispyocto/vsisp_isp_demosaic5x.v new file mode 100644 index 0000000..889ca64 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_isp_demosaic5x.v
@@ -0,0 +1,286 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_isp_demosaic5x + ( + clk, + reset_n, + alom_stage4_en, + alom_stage5_en, + regs_dem_bypass, + cv_mask, + proc_pix_01, + proc_pix_02, + proc_pix_03, + proc_pix_11, + proc_pix_12, + proc_pix_13, + proc_pix_21, + proc_pix_22, + proc_pix_23, + proc_pix_31, + proc_pix_32, + proc_pix_33, + proc_pix_41, + proc_pix_42, + proc_pix_43, + proc_pattern_stg3, + flag_h_1, + flag_v_1, + flag_h_2, + flag_v_2, + flag_h_3, + flag_v_3, + grn_line04, + grn_line13, + grn_line2, + red_sub, + blue_sub); +`include "vsisp_isp.vh" + input clk; + input reset_n; + input alom_stage4_en; + input alom_stage5_en; + input regs_dem_bypass; + input [1:0] cv_mask; + input [c_dw_si-1:0] proc_pix_01; + input [c_dw_si-1:0] proc_pix_02; + input [c_dw_si-1:0] proc_pix_03; + input [c_dw_si-1:0] proc_pix_11; + input [c_dw_si-1:0] proc_pix_12; + input [c_dw_si-1:0] proc_pix_13; + input [c_dw_si-1:0] proc_pix_21; + input [c_dw_si-1:0] proc_pix_22; + input [c_dw_si-1:0] proc_pix_23; + input [c_dw_si-1:0] proc_pix_31; + input [c_dw_si-1:0] proc_pix_32; + input [c_dw_si-1:0] proc_pix_33; + input [c_dw_si-1:0] proc_pix_41; + input [c_dw_si-1:0] proc_pix_42; + input [c_dw_si-1:0] proc_pix_43; + input [1:0] proc_pattern_stg3; + input flag_h_1; + input flag_v_1; + input flag_h_2; + input flag_v_2; + input flag_h_3; + input flag_v_3; + output [c_dw_si:0] grn_line04; + output [c_dw_si:0] grn_line13; + output [c_dw_si-1:0] grn_line2; + output [c_dw_si:0] red_sub; + output [c_dw_si:0] blue_sub; + reg [1:0] viv_s0; + wire [1:0] viv_s1; + wire [1:0] viv_s2; + wire [1:0] viv_s3; + wire [1:0] viv_s4; + wire [1:0] viv_s5; + wire [c_dw_si-1:0] viv_s6; + wire [c_dw_si-1:0] viv_s7; + wire [c_dw_si-1:0] viv_s8; + wire [c_dw_si-1:0] viv_s9; + wire [c_dw_si-1:0] viv_s10; + wire [c_dw_si-1:0] viv_s11; + wire [c_dw_si-1:0] viv_s12; + wire [c_dw_si-1:0] viv_s13; + wire [c_dw_si-1:0] viv_s14; + wire [c_dw_si-1:0] viv_s15; + wire [c_dw_si-1:0] viv_s16; + wire [c_dw_si:0] viv_s17; + wire [c_dw_si:0] viv_s18; + wire [c_dw_si:0] viv_s19; + wire [c_dw_si:0] viv_s20; + reg [c_dw_si:0] viv_s21; + reg [c_dw_si:0] viv_s22; + reg [c_dw_si-1:0] viv_s23; + reg [c_dw_si:0] viv_s24; + reg [c_dw_si:0] viv_s25; + reg [c_dw_si:0] viv_s26; + reg [c_dw_si:0] viv_s27; + reg [c_dw_si-1:0] grn_line2; + reg [c_dw_si:0] grn_line04; + reg [c_dw_si:0] grn_line13; + wire viv_s28; + wire viv_s29; + wire viv_s30; + wire [c_dw_si+2:0] viv_s31; + wire [c_dw_si+1:0] viv_s32; + wire [c_dw_si+1:0] viv_s33; + wire [c_dw_si+1:0] viv_s34; + wire [c_dw_si+3:0] viv_s35; + wire [c_dw_si:0] viv_s36; + wire [c_dw_si+2:0] viv_s37; + wire [c_dw_si+1:0] viv_s38; + wire [c_dw_si+1:0] viv_s39; + wire [c_dw_si+1:0] viv_s40; + wire [c_dw_si+3:0] viv_s41; + wire [c_dw_si:0] viv_s42; + always @(*) begin + case (proc_pattern_stg3) + c_r : viv_s0 = c_gb; + c_gr: viv_s0 = c_b; + c_gb: viv_s0 = c_r; + default: viv_s0 = c_gr; + endcase + end + assign viv_s1 = proc_pattern_stg3; + assign viv_s2 = viv_s0; + assign viv_s3 = proc_pattern_stg3; + assign viv_s4 = viv_s0; + assign viv_s5 = proc_pattern_stg3; + vsisp_isp_demosaic_3x3_crcb u1_isp_demosaic_3x3_crcb + ( + .regs_dem_bypass(regs_dem_bypass), + .proc_pix_01(proc_pix_01), + .proc_pix_02(proc_pix_02), + .proc_pix_03(proc_pix_03), + .proc_pix_11(proc_pix_11), + .proc_pix_12(proc_pix_12), + .proc_pix_13(proc_pix_13), + .proc_pix_21(proc_pix_21), + .proc_pix_22(proc_pix_22), + .proc_pix_23(proc_pix_23), + .proc_pattern(viv_s2), + .flag_h(flag_h_1), + .flag_v(flag_v_1), + .g_data(viv_s7), + .rs_data(viv_s11), + .bs_data(viv_s14)); + vsisp_isp_demosaic_3x3_crcb u2_isp_demosaic_3x3_crcb + ( + .regs_dem_bypass(regs_dem_bypass), + .proc_pix_01(proc_pix_11), + .proc_pix_02(proc_pix_12), + .proc_pix_03(proc_pix_13), + .proc_pix_11(proc_pix_21), + .proc_pix_12(proc_pix_22), + .proc_pix_13(proc_pix_23), + .proc_pix_21(proc_pix_31), + .proc_pix_22(proc_pix_32), + .proc_pix_23(proc_pix_33), + .proc_pattern(viv_s3), + .flag_h(flag_h_2), + .flag_v(flag_v_2), + .g_data(viv_s8), + .rs_data(viv_s12), + .bs_data(viv_s15)); + vsisp_isp_demosaic_3x3_crcb u3_isp_demosaic_3x3_crcb + ( + .regs_dem_bypass(regs_dem_bypass), + .proc_pix_01(proc_pix_21), + .proc_pix_02(proc_pix_22), + .proc_pix_03(proc_pix_23), + .proc_pix_11(proc_pix_31), + .proc_pix_12(proc_pix_32), + .proc_pix_13(proc_pix_33), + .proc_pix_21(proc_pix_41), + .proc_pix_22(proc_pix_42), + .proc_pix_23(proc_pix_43), + .proc_pattern(viv_s4), + .flag_h(flag_h_3), + .flag_v(flag_v_3), + .g_data(viv_s9), + .rs_data(viv_s13), + .bs_data(viv_s16)); +vsisp_isp_demosaic_3x2 u0_isp_demosaic_3x2 + ( + .regs_dem_bypass(regs_dem_bypass), + .proc_pix_c1(proc_pix_01), + .proc_pix_c2(proc_pix_02), + .proc_pix_c3(proc_pix_03), + .proc_pix_n2(proc_pix_12), + .proc_pattern(viv_s1), + .flag_v(flag_v_1), + .g_data(viv_s6)); + vsisp_isp_demosaic_3x2 u4_isp_demosaic_3x2 + ( + .regs_dem_bypass(regs_dem_bypass), + .proc_pix_c1(proc_pix_41), + .proc_pix_c2(proc_pix_42), + .proc_pix_c3(proc_pix_43), + .proc_pix_n2(proc_pix_32), + .proc_pattern(viv_s5), + .flag_v(flag_v_3), + .g_data(viv_s10)); + assign viv_s17 = {1'b0, viv_s6} + viv_s10; + assign viv_s18 = {1'b0, viv_s7} + viv_s9; + assign viv_s19 = {1'b0, viv_s11} + viv_s13; + assign viv_s20 = {1'b0, viv_s14} + viv_s16; + assign viv_s28 = (cv_mask == 2'b00) ? 1'b1 : 1'b0; + assign viv_s29 = (cv_mask == 2'b01) ? 1'b1 : 1'b0; + assign viv_s30 = (cv_mask == 2'b10) ? 1'b1 : 1'b0; + assign viv_s31 = {viv_s20, 2'b00}; + assign viv_s32 = {viv_s15 , 2'b00}; + assign viv_s33 = (viv_s29) ? {c_dw_si+2{1'b0}} : + (viv_s30) ? {1'b0, viv_s20} : + {viv_s20, 1'b0}; + assign viv_s34 = (viv_s29) ? {viv_s15, 2'b00} : + (viv_s30) ? {1'b0, viv_s15, 1'b0} : + {c_dw_si+2{1'b0}}; + assign viv_s35 = {1'b0, viv_s31} + viv_s32 + viv_s33 + viv_s34; + assign viv_s36 = (viv_s28) ? {viv_s15, 1'b0} : + viv_s35[c_dw_si+3:3]; + assign viv_s37 = {viv_s19, 2'b00}; + assign viv_s38 = {viv_s12 , 2'b00}; + assign viv_s39 = (viv_s29) ? {c_dw_si+2{1'b0}} : + (viv_s30) ? {1'b0, viv_s19} : + {viv_s19, 1'b0}; + assign viv_s40 = (viv_s29) ? {viv_s12, 2'b00} : + (viv_s30) ? {1'b0, viv_s12, 1'b0} : + {c_dw_si+2{1'b0}}; + assign viv_s41 = {1'b0, viv_s37} + viv_s38 + viv_s39 + viv_s40; + assign viv_s42 = (viv_s28) ? {viv_s12, 1'b0} : + viv_s41[c_dw_si+3:3]; + assign red_sub = viv_s26; + assign blue_sub = viv_s27; + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + viv_s24 <= 0; + viv_s25 <= 0; + viv_s23 <= 0; + viv_s21 <= 0; + viv_s22 <= 0; + viv_s26 <= 0; + viv_s27 <= 0; + grn_line04 <= 0; + grn_line13 <= 0; + grn_line2 <= 0; + end else begin + if (alom_stage4_en) begin + viv_s24 <= viv_s17; + viv_s25 <= viv_s18; + viv_s23 <= viv_s8; + viv_s21 <= viv_s42; + viv_s22 <= viv_s36; + end + if (alom_stage5_en) begin + grn_line04 <= viv_s24; + grn_line13 <= viv_s25; + grn_line2 <= viv_s23; + viv_s26 <= viv_s21; + viv_s27 <= viv_s22; + end + end + end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_demosaic_3x2.v b/ispyocto/rtl/ispyocto/vsisp_isp_demosaic_3x2.v new file mode 100644 index 0000000..6fbeb6f --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_isp_demosaic_3x2.v
@@ -0,0 +1,68 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_isp_demosaic_3x2 + ( + regs_dem_bypass, + proc_pix_c1, + proc_pix_c2, + proc_pix_c3, + proc_pix_n2, + proc_pattern, + flag_v, + g_data); +`include "vsisp_isp.vh" + input regs_dem_bypass; + input [c_dw_si-1:0] proc_pix_c1; + input [c_dw_si-1:0] proc_pix_c2; + input [c_dw_si-1:0] proc_pix_c3; + input [c_dw_si-1:0] proc_pix_n2; + input [1:0] proc_pattern; + input flag_v; + output [c_dw_si-1:0] g_data; + wire [c_dw_si+1:0] viv_s0; + wire [c_dw_si-1:0] viv_s1; + reg [c_dw_si-1:0] viv_s2; + assign viv_s0 = {1'b0, proc_pix_c1, 1'b1} + {proc_pix_c3, 1'b1}; + assign viv_s1 = viv_s0[c_dw_si+1:2]; + always @(*) begin + if (regs_dem_bypass) begin + viv_s2 = proc_pix_c2; + end else if (flag_v) begin + case (proc_pattern) + c_r : viv_s2 = proc_pix_n2; + c_gr : viv_s2 = proc_pix_c2; + c_gb : viv_s2 = proc_pix_c2; + default : viv_s2 = proc_pix_n2; + endcase + end else begin + case (proc_pattern) + c_r : viv_s2 = viv_s1; + c_gr : viv_s2 = proc_pix_c2; + c_gb : viv_s2 = proc_pix_c2; + default : viv_s2 = viv_s1; + endcase + end + end +assign g_data = viv_s2; +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_demosaic_3x3_crcb.v b/ispyocto/rtl/ispyocto/vsisp_isp_demosaic_3x3_crcb.v new file mode 100644 index 0000000..8d245fb --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_isp_demosaic_3x3_crcb.v
@@ -0,0 +1,153 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_isp_demosaic_3x3_crcb + ( + regs_dem_bypass, + proc_pix_01, + proc_pix_02, + proc_pix_03, + proc_pix_11, + proc_pix_12, + proc_pix_13, + proc_pix_21, + proc_pix_22, + proc_pix_23, + proc_pattern, + flag_h, + flag_v, + g_data, + rs_data, + bs_data); +`include "vsisp_isp.vh" + input regs_dem_bypass; + input [c_dw_si-1:0] proc_pix_01; + input [c_dw_si-1:0] proc_pix_02; + input [c_dw_si-1:0] proc_pix_03; + input [c_dw_si-1:0] proc_pix_11; + input [c_dw_si-1:0] proc_pix_12; + input [c_dw_si-1:0] proc_pix_13; + input [c_dw_si-1:0] proc_pix_21; + input [c_dw_si-1:0] proc_pix_22; + input [c_dw_si-1:0] proc_pix_23; + input [1:0] proc_pattern; + input flag_h; + input flag_v; + output [c_dw_si-1:0] g_data; + output [c_dw_si-1:0] rs_data; + output [c_dw_si-1:0] bs_data; + wire [c_dw_si-1:0] viv_s0; + wire [c_dw_si-1:0] viv_s1; + wire [c_dw_si-1:0] viv_s2; + wire [c_dw_si-1:0] viv_s3; + reg [c_dw_si-1:0] viv_s4; + reg [c_dw_si-1:0] viv_s5; + reg [c_dw_si-1:0] viv_s6; + function [c_dw_si-1:0] f_avg2; + input [c_dw_si-1:0] a, + b; + reg [c_dw_si+1:0] viv_s7; + begin + viv_s7 = {1'b0, a, 1'b1} + {b, 1'b1}; + f_avg2 = viv_s7[c_dw_si+1:2]; + end + endfunction + function [c_dw_si-1:0] f_avg4; + input [c_dw_si-1:0] a, + b, + c, + d; + reg [c_dw_si+2:0] viv_s7; + begin + viv_s7 = {2'b0, a, 1'b1} + {b, 1'b1} + {c, 1'b1} + {d, 1'b1}; + f_avg4 = viv_s7[c_dw_si+2:3]; + end + endfunction + assign viv_s0 = f_avg2(proc_pix_11, proc_pix_13); + assign viv_s1 = f_avg2(proc_pix_02, proc_pix_22); + assign viv_s3 = f_avg4(proc_pix_01, proc_pix_03, proc_pix_21, proc_pix_23); + assign viv_s2 = f_avg2(viv_s0, viv_s1); + always @(*) begin + case(proc_pattern) + c_b : begin + if (flag_h) begin + viv_s4 = viv_s0; + viv_s6 = viv_s0; + viv_s5 = viv_s1; + end else if (flag_v) begin + viv_s4 = viv_s1; + viv_s6 = viv_s1; + viv_s5 = viv_s0; + end else begin + viv_s4 = viv_s2; + viv_s6 = viv_s2; + viv_s5 = viv_s2; + end + end + c_r : begin + if (flag_h) begin + viv_s4 = viv_s0; + viv_s6 = viv_s1; + viv_s5 = viv_s0; + end else if (flag_v) begin + viv_s4 = viv_s1; + viv_s6 = viv_s0; + viv_s5 = viv_s1; + end else begin + viv_s4 = viv_s2; + viv_s6 = viv_s2; + viv_s5 = viv_s2; + end + end + c_gb : begin + viv_s4 = proc_pix_12; + if (flag_h) begin + viv_s6 = proc_pix_12; + viv_s5 = viv_s3; + end else if (flag_v) begin + viv_s6 = viv_s3; + viv_s5 = proc_pix_12; + end else begin + viv_s6 = viv_s3; + viv_s5 = viv_s3; + end + end + default : begin + viv_s4 = proc_pix_12; + if (flag_h) begin + viv_s6 = viv_s3; + viv_s5 = proc_pix_12; + end else if (flag_v) begin + viv_s6 = proc_pix_12; + viv_s5 = viv_s3; + end else begin + viv_s6 = viv_s3; + viv_s5 = viv_s3; + end + end + endcase + end + assign g_data = (regs_dem_bypass) ? proc_pix_12 : viv_s4; + assign rs_data = (regs_dem_bypass) ? {c_dw_si{1'b0}} : viv_s5; + assign bs_data = (regs_dem_bypass) ? {c_dw_si{1'b0}} : viv_s6; +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_demosaic_buf_5lines.v b/ispyocto/rtl/ispyocto/vsisp_isp_demosaic_buf_5lines.v new file mode 100644 index 0000000..9eb869f --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_isp_demosaic_buf_5lines.v
@@ -0,0 +1,229 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_isp_demosaic_buf_5lines + ( + clk, + reset_n, + alom_stage0_val, + alom_stage1_val, + alom_stage2_val, + alom_stage3_val, + alom_stage4_val, + in_data_t, + in_data_m1, + in_data_m2, + in_data_m3, + in_data_b, + alom_stage1_en, + alom_stage2_en, + alom_stage3_en, + alom_stage4_en, + proc_pix_01, + proc_pix_02, + proc_pix_03, + proc_pix_04, + proc_pix_05, + proc_pix_11, + proc_pix_12, + proc_pix_13, + proc_pix_14, + proc_pix_15, + proc_pix_21, + proc_pix_22, + proc_pix_23, + proc_pix_24, + proc_pix_25, + proc_pix_31, + proc_pix_32, + proc_pix_33, + proc_pix_34, + proc_pix_35, + proc_pix_41, + proc_pix_42, + proc_pix_43, + proc_pix_44, + proc_pix_45); +`include "vsisp_isp.vh" + input clk; + input reset_n; + input alom_stage0_val; + input alom_stage1_val; + input alom_stage2_val; + input alom_stage3_val; + input alom_stage4_val; + input [c_dw_si-1:0] in_data_t; + input [c_dw_si-1:0] in_data_m1; + input [c_dw_si-1:0] in_data_m2; + input [c_dw_si-1:0] in_data_m3; + input [c_dw_si-1:0] in_data_b; + input alom_stage1_en; + input alom_stage2_en; + input alom_stage3_en; + input alom_stage4_en; + output [c_dw_si-1:0] proc_pix_01; + output [c_dw_si-1:0] proc_pix_02; + output [c_dw_si-1:0] proc_pix_03; + output [7:0] proc_pix_04; + output [7:0] proc_pix_05; + output [c_dw_si-1:0] proc_pix_11; + output [c_dw_si-1:0] proc_pix_12; + output [c_dw_si-1:0] proc_pix_13; + output [7:0] proc_pix_14; + output [7:0] proc_pix_15; + output [c_dw_si-1:0] proc_pix_21; + output [c_dw_si-1:0] proc_pix_22; + output [c_dw_si-1:0] proc_pix_23; + output [7:0] proc_pix_24; + output [7:0] proc_pix_25; + output [c_dw_si-1:0] proc_pix_31; + output [c_dw_si-1:0] proc_pix_32; + output [c_dw_si-1:0] proc_pix_33; + output [7:0] proc_pix_34; + output [7:0] proc_pix_35; + output [c_dw_si-1:0] proc_pix_41; + output [c_dw_si-1:0] proc_pix_42; + output [c_dw_si-1:0] proc_pix_43; + output [7:0] proc_pix_44; + output [7:0] proc_pix_45; + parameter c_dw_buf = 5*c_dw_si; + reg [c_dw_si-1:0] proc_pix_01; + reg [c_dw_si-1:0] proc_pix_02; + reg [c_dw_si-1:0] proc_pix_03; + reg [7:0] proc_pix_04; + reg [7:0] proc_pix_05; + reg [c_dw_si-1:0] proc_pix_11; + reg [c_dw_si-1:0] proc_pix_12; + reg [c_dw_si-1:0] proc_pix_13; + reg [7:0] proc_pix_14; + reg [7:0] proc_pix_15; + reg [c_dw_si-1:0] proc_pix_21; + reg [c_dw_si-1:0] proc_pix_22; + reg [c_dw_si-1:0] proc_pix_23; + reg [7:0] proc_pix_24; + reg [7:0] proc_pix_25; + reg [c_dw_si-1:0] proc_pix_31; + reg [c_dw_si-1:0] proc_pix_32; + reg [c_dw_si-1:0] proc_pix_33; + reg [7:0] proc_pix_34; + reg [7:0] proc_pix_35; + reg [c_dw_si-1:0] proc_pix_41; + reg [c_dw_si-1:0] proc_pix_42; + reg [c_dw_si-1:0] proc_pix_43; + reg [7:0] proc_pix_44; + reg [7:0] proc_pix_45; + wire [c_dw_buf-1:0] viv_s0; + reg [c_dw_buf-1:0] viv_s1; + reg [c_dw_buf-1:0] viv_s2; + reg [c_dw_buf-1:0] viv_s3; + reg [c_dw_buf-1:0] viv_s4; + assign viv_s0 = {in_data_t,in_data_m1,in_data_m2,in_data_m3,in_data_b}; + always @(posedge clk or negedge reset_n) begin + if (reset_n == 1'b0) begin + viv_s1 <= {c_dw_buf{1'b0}}; + viv_s2 <= {c_dw_buf{1'b0}}; + viv_s3 <= {c_dw_buf{1'b0}}; + viv_s4 <= {c_dw_buf{1'b0}}; + end else begin + if (alom_stage1_en) viv_s1 <= viv_s0; + if (alom_stage2_en) viv_s2 <= viv_s1; + if (alom_stage3_en) viv_s3 <= viv_s2; + if (alom_stage4_en) viv_s4 <= viv_s3; + end + end + always @(*) begin + if (alom_stage0_val || !alom_stage2_val) begin + proc_pix_05 = viv_s0[(5*c_dw_si)-1:(5*c_dw_si)-8]; + proc_pix_15 = viv_s0[(4*c_dw_si)-1:(4*c_dw_si)-8]; + proc_pix_25 = viv_s0[(3*c_dw_si)-1:(3*c_dw_si)-8]; + proc_pix_35 = viv_s0[(2*c_dw_si)-1:(2*c_dw_si)-8]; + proc_pix_45 = viv_s0[ c_dw_si -1: c_dw_si -8]; + end else begin + proc_pix_05 = viv_s2[(5*c_dw_si)-1:(5*c_dw_si)-8]; + proc_pix_15 = viv_s2[(4*c_dw_si)-1:(4*c_dw_si)-8]; + proc_pix_25 = viv_s2[(3*c_dw_si)-1:(3*c_dw_si)-8]; + proc_pix_35 = viv_s2[(2*c_dw_si)-1:(2*c_dw_si)-8]; + proc_pix_45 = viv_s2[ c_dw_si -1: c_dw_si -8]; + end + end + always @(*) begin + if (alom_stage1_val || !alom_stage3_val) begin + proc_pix_04 = viv_s1[(5*c_dw_si)-1:(5*c_dw_si)-8]; + proc_pix_14 = viv_s1[(4*c_dw_si)-1:(4*c_dw_si)-8]; + proc_pix_24 = viv_s1[(3*c_dw_si)-1:(3*c_dw_si)-8]; + proc_pix_34 = viv_s1[(2*c_dw_si)-1:(2*c_dw_si)-8]; + proc_pix_44 = viv_s1[ c_dw_si -1: c_dw_si -8]; + end else begin + proc_pix_04 = viv_s3[(5*c_dw_si)-1:(5*c_dw_si)-8]; + proc_pix_14 = viv_s3[(4*c_dw_si)-1:(4*c_dw_si)-8]; + proc_pix_24 = viv_s3[(3*c_dw_si)-1:(3*c_dw_si)-8]; + proc_pix_34 = viv_s3[(2*c_dw_si)-1:(2*c_dw_si)-8]; + proc_pix_44 = viv_s3[ c_dw_si -1: c_dw_si -8]; + end + end + always @(*) begin + if (alom_stage2_val || !alom_stage4_val) begin + proc_pix_03 = viv_s2[(5*c_dw_si)-1:4*c_dw_si]; + proc_pix_13 = viv_s2[(4*c_dw_si)-1:3*c_dw_si]; + proc_pix_23 = viv_s2[(3*c_dw_si)-1:2*c_dw_si]; + proc_pix_33 = viv_s2[(2*c_dw_si)-1:c_dw_si]; + proc_pix_43 = viv_s2[c_dw_si-1:0]; + end else begin + proc_pix_03 = viv_s4[(5*c_dw_si)-1:4*c_dw_si]; + proc_pix_13 = viv_s4[(4*c_dw_si)-1:3*c_dw_si]; + proc_pix_23 = viv_s4[(3*c_dw_si)-1:2*c_dw_si]; + proc_pix_33 = viv_s4[(2*c_dw_si)-1:c_dw_si]; + proc_pix_43 = viv_s4[c_dw_si-1:0]; + end + end + always @(*) begin + if (alom_stage3_val || !alom_stage1_val) begin + proc_pix_02 = viv_s3[(5*c_dw_si)-1:4*c_dw_si]; + proc_pix_12 = viv_s3[(4*c_dw_si)-1:3*c_dw_si]; + proc_pix_22 = viv_s3[(3*c_dw_si)-1:2*c_dw_si]; + proc_pix_32 = viv_s3[(2*c_dw_si)-1:c_dw_si]; + proc_pix_42 = viv_s3[c_dw_si-1:0]; + end else begin + proc_pix_02 = viv_s1[(5*c_dw_si)-1:4*c_dw_si]; + proc_pix_12 = viv_s1[(4*c_dw_si)-1:3*c_dw_si]; + proc_pix_22 = viv_s1[(3*c_dw_si)-1:2*c_dw_si]; + proc_pix_32 = viv_s1[(2*c_dw_si)-1:c_dw_si]; + proc_pix_42 = viv_s1[c_dw_si-1:0]; + end + end + always @(*) begin + if (alom_stage4_val || !alom_stage2_val) begin + proc_pix_01 = viv_s4[(5*c_dw_si)-1:4*c_dw_si]; + proc_pix_11 = viv_s4[(4*c_dw_si)-1:3*c_dw_si]; + proc_pix_21 = viv_s4[(3*c_dw_si)-1:2*c_dw_si]; + proc_pix_31 = viv_s4[(2*c_dw_si)-1:c_dw_si]; + proc_pix_41 = viv_s4[c_dw_si-1:0]; + end else begin + proc_pix_01 = viv_s2[(5*c_dw_si)-1:4*c_dw_si]; + proc_pix_11 = viv_s2[(4*c_dw_si)-1:3*c_dw_si]; + proc_pix_21 = viv_s2[(3*c_dw_si)-1:2*c_dw_si]; + proc_pix_31 = viv_s2[(2*c_dw_si)-1:c_dw_si]; + proc_pix_41 = viv_s2[c_dw_si-1:0]; + end + end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_demosaic_dpsbe.v b/ispyocto/rtl/ispyocto/vsisp_isp_demosaic_dpsbe.v new file mode 100644 index 0000000..8a7e7f8 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_isp_demosaic_dpsbe.v
@@ -0,0 +1,69 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_isp_demosaic_dpsbe + ( + clk, + reset_n, + soft_rst, + in_data, + in_val, + in_ack, + out_data, + out_val, + out_ack); + parameter c_dw_in = 10; + input clk; + input reset_n; + input soft_rst; + input [c_dw_in-1:0] in_data; + input in_val; + output in_ack; + output [c_dw_in-1:0] out_data; + output out_val; + input out_ack; + reg viv_s0; + reg viv_s1; + reg [c_dw_in-1:0] viv_s2; + wire out_val; + wire [c_dw_in-1:0] out_data; + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + viv_s2 <= {c_dw_in{1'b0}}; + viv_s0 <= 1'b0; + viv_s1 <= 1'b0; + end else begin + if (viv_s0) viv_s2 <= in_data; + if (soft_rst) begin + viv_s0 <= 1'b0; + viv_s1 <= 1'b0; + end else begin + viv_s0 <= ~out_val | out_ack; + if (viv_s0) viv_s1 <= in_val; + end + end + end + assign out_data = viv_s0 ? in_data : viv_s2; + assign out_val = viv_s0 ? in_val : viv_s1; + assign in_ack = viv_s0; +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_digi_gain.v b/ispyocto/rtl/ispyocto/vsisp_isp_digi_gain.v new file mode 100644 index 0000000..4b63c49 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_isp_digi_gain.v
@@ -0,0 +1,227 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_isp_digi_gain ( + clk, + reset_n, + soft_rst, + regs_bayer_pat, + in_data, + in_h_end, + in_v_end, + in_val, + in_ack, + in_vsync, + out_data, + out_h_st, + out_h_end, + out_v_end, + out_v_st, + out_vsync, + out_val, + out_ack, + out_bayer_ptn, + gain_r, + gain_gr, + gain_gb, + gain_b, + regs_dgain_enable); +`include "vsisp_isp.vh" + input clk; + input reset_n; + input soft_rst; + input [1:0] regs_bayer_pat; + input [c_dw_si-1:0] in_data; + input in_h_end; + input in_v_end; + input in_val; + input in_vsync; + output in_ack; + output [c_dw_si-1:0] out_data; + output out_h_end; + output out_h_st; + output out_v_st; + output out_v_end; + output out_val; + output out_vsync; + output [1:0] out_bayer_ptn; + input out_ack; + input [15:0] gain_r; + input [15:0] gain_gr; + input [15:0] gain_gb; + input [15:0] gain_b; + input regs_dgain_enable; + reg [15:0] viv_s0; + wire [c_dw_si+16:0] viv_s1; + wire [c_dw_si+8:0] viv_s2; + wire [c_dw_si-1:0] viv_s3; + wire [c_dw_si-1:0] viv_s4; + wire in_val; + wire in_ack; + wire viv_s5; + reg viv_s6; + reg viv_s7; + reg [c_dw_si-1:0] out_data; + reg out_h_end; + reg out_v_end; + reg out_val; + reg viv_s8; + reg [12:0] viv_s9; + reg [12:0] viv_s10; +assign viv_s5 = in_val && in_ack; + reg [1:0] viv_s11; + reg [1:0] viv_s12; + assign out_bayer_ptn = regs_bayer_pat; +always @ (posedge clk or negedge reset_n) begin + if (~reset_n) begin + viv_s6 <= 1'b0; + viv_s11 <= 2'b00; + viv_s12 <= 2'b00; + viv_s7 <= 1'b0; + end else begin + if (soft_rst) begin + viv_s6 <= 1'b0; + viv_s12 <= viv_s11; + end else begin + if (out_v_end && out_h_end && out_val) begin + viv_s6 <= 1'b0; + end else if (viv_s5) begin + viv_s6 <= 1'b1; + end + if (~viv_s6) begin + case (regs_bayer_pat) + 2'b00 : viv_s11 <= 2'b00; + 2'b01 : viv_s11 <= 2'b11; + 2'b10 : viv_s11 <= 2'b10; + default: viv_s11 <= 2'b01; + endcase + end + if (~viv_s5 && ~viv_s6) begin + viv_s12 <= viv_s11; + viv_s7 <= ~viv_s11[1]; + end else if(viv_s5) begin + if (in_v_end && in_h_end) begin + viv_s12 <= viv_s11; + viv_s7 <= ~viv_s11[1]; + end else if (in_h_end) begin + viv_s12 <= {viv_s7,viv_s11[0]}; + viv_s7 <= ~viv_s7; + end else begin + viv_s12 <= ~viv_s12; + end + end + end + end +end +always @ (*) +begin + if(regs_dgain_enable) begin + case (viv_s12) + 2'b00 : viv_s0 = gain_r; + 2'b01 : viv_s0 = gain_b; + 2'b10 : viv_s0 = gain_gb; + default:viv_s0 = gain_gr; + endcase + end else begin + viv_s0 = 16'h0; + end +end +always @ (posedge clk or negedge reset_n) begin + if (~reset_n) begin + viv_s9 <= 13'b0; + viv_s10 <= 13'b0; + end + else if(soft_rst|in_vsync)begin + viv_s9 <= 13'b0; + viv_s10 <= 13'b0; + end + else if(out_h_end)begin + viv_s9 <= 13'b0; + viv_s10 <= viv_s10 + 1'b1; + end + else if(viv_s5) + viv_s9 <= viv_s9 + 1'b1; +end +wire out_vsync; +reg viv_s13; +always @ (posedge clk or negedge reset_n) begin + if (~reset_n) + viv_s13 <= 1'b0; + else + viv_s13 <= in_vsync; +end +assign out_vsync = ~in_vsync&viv_s13; +wire viv_s14 = (~|viv_s9) && viv_s5; +wire viv_s15 = (~|viv_s10) && viv_s14; + assign viv_s1 = viv_s0 * in_data + {{c_dw_si+1{1'b0}},{10'd128}}; + assign viv_s2 = viv_s1[c_dw_si+16:8]; + assign viv_s3 = (|viv_s2[c_dw_si+8:c_dw_si]) ? {c_dw_si{1'b1}} : viv_s2[c_dw_si-1:0]; + assign viv_s4 = regs_dgain_enable ? viv_s3 : in_data; + assign in_ack = (~out_val || out_ack) && viv_s8; + always @(posedge clk or negedge reset_n) begin + if (reset_n == 1'b0) begin + out_h_end <= 1'b0; + out_v_end <= 1'b0; + out_data <= {c_dw_si{1'b0}}; + out_val <= 1'b0; + viv_s8 <= 1'b0; + end else begin + if (soft_rst == 1'b1) begin + out_h_end <= 1'b0; + out_v_end <= 1'b0; + out_val <= 1'b0; + viv_s8 <= 1'b0; + end else begin + viv_s8 <= 1'b1; + if (~out_val || out_ack) begin + out_h_end <= in_h_end; + out_v_end <= in_v_end; + out_data <= viv_s4; + out_val <= in_val; + end + end + end + end +reg viv_s16; +always @(posedge clk or negedge reset_n) + if(!reset_n) + viv_s16<= 1'b1; + else if(soft_rst) + viv_s16<= 1'b1; + else if(out_h_end&&out_v_end&&out_val&&out_ack) + viv_s16<= 1'b1; + else if(out_val&&out_ack) + viv_s16<= 1'b0; +assign out_v_st=viv_s16&&out_val; +reg viv_s17; +always @(posedge clk or negedge reset_n) + if(!reset_n) + viv_s17<= 1'b1; + else if(soft_rst) + viv_s17<= 1'b1; + else if(out_h_end&&out_val&&out_ack) + viv_s17<= 1'b1; + else if(out_val&&out_ack) + viv_s17<= 1'b0; +assign out_h_st=viv_s17&&out_val; +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_dpsfe.v b/ispyocto/rtl/ispyocto/vsisp_isp_dpsfe.v new file mode 100644 index 0000000..f5afebe --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_isp_dpsfe.v
@@ -0,0 +1,68 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_isp_dpsfe + ( + clk, + reset_n, + soft_rst, + in_data, + in_val, + in_ack, + out_data, + out_val, + out_ack); + parameter c_dw_in = 10; + input clk; + input reset_n; + input soft_rst; + input [c_dw_in-1:0] in_data; + input in_val; + output in_ack; + output [c_dw_in-1:0] out_data; + output out_val; + input out_ack; + reg [c_dw_in-1:0] out_data; + reg out_val; + reg viv_s0; + assign in_ack = (~out_val || out_ack) && viv_s0; + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + out_data <= {c_dw_in{1'b0}}; + out_val <= 1'b0; + viv_s0 <= 1'b0; + end else begin + if (soft_rst) begin + out_data <= {c_dw_in{1'b0}}; + out_val <= 1'b0; + viv_s0 <= 1'b0; + end else begin + viv_s0 <= 1'b1; + if (~out_val || out_ack) begin + out_data <= in_data; + out_val <= in_val; + end + end + end + end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_exp.v b/ispyocto/rtl/ispyocto/vsisp_isp_exp.v new file mode 100644 index 0000000..18acb12 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_isp_exp.v
@@ -0,0 +1,447 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_isp_exp + ( + clk, + reset_n, + soft_rst, + clk_cfg, + reset_cfg_n, + regs_gen_cfg_upd, + regs_cfg_upd, + cfg_val_i, + cfg_addr_i, + cfg_rd_i, + cfg_wdata_i, + cfg_rdata_o, + y_i, + h_end_i, + v_end_i, + val_i, + ack_i, + exp_alt_mode_o, + measure_complete + ); +`include "vsisp_isp.vh" +input clk; +input reset_n; +input soft_rst; +input clk_cfg; +input reset_cfg_n; +input regs_gen_cfg_upd; +input regs_cfg_upd; +input cfg_val_i; +input [13:2] cfg_addr_i; +input cfg_rd_i; +input [31:0] cfg_wdata_i; +output [31:0] cfg_rdata_o; +input [ 7:0] y_i; +input h_end_i; +input v_end_i; +input val_i; +input ack_i; +output exp_alt_mode_o; +output measure_complete; +wire [12:0] viv_s0; +wire [12:0] viv_s1; +wire [10:0] viv_s2; +wire [10:0] viv_s3; +reg [ 7:0] viv_s4; +reg viv_s5; +reg [ 2:0] viv_s6; +reg [ 2:0] viv_s7; +reg [12:0] viv_s8; +reg [12:0] viv_s9; +wire [12:0] viv_s10; +wire [12:0] viv_s11; +reg [10:0] viv_s12; +reg [10:0] viv_s13; +reg [19:0] viv_s14; +reg [19:0] viv_s15; +reg [19:0] viv_s16; +reg [19:0] viv_s17; +reg [19:0] viv_s18; +wire [ 2:0] viv_s19; +wire [ 2:0] viv_s20; +wire viv_s21; +wire viv_s22; +reg [19:0] viv_s23; +wire [ 2:0] viv_s24; +wire [21:0] viv_s25; +wire viv_s26; +wire [10:0] viv_s27; +wire viv_s28; +reg [19:0] viv_s29; +reg [19:0] viv_s30; +reg [19:0] viv_s31; +reg [19:0] viv_s32; +reg [19:0] viv_s33; +wire [ 2:0] viv_s34; +wire [ 2:0] viv_s35; +wire viv_s36; +reg [19:0] viv_s37; +wire [ 2:0] viv_s38; +wire viv_s39; +wire viv_s40; +reg [ 3:0] viv_s41; +wire [22:0] viv_s42; +reg [22:0] viv_s43; +reg [ 9:0] viv_s44; +wire viv_s45; +wire viv_s46; +reg [10:0] viv_s47; +wire [ 7:0] viv_s48; +wire [ 5:0] viv_s49; +wire viv_s50; +wire viv_s51; +reg viv_s52; +wire viv_s53; +reg viv_s54; +reg viv_s55; +reg viv_s56; + vsisp_isp_exp_regs u_isp_exp_regs + ( + .clk (clk), + .reset_n (reset_n), + .clk_cfg (clk_cfg), + .reset_cfg_n (reset_cfg_n), + .cfg_val_i (cfg_val_i), + .cfg_addr_i (cfg_addr_i), + .cfg_rd_i (cfg_rd_i), + .cfg_wdata_i (cfg_wdata_i), + .cfg_rdata_o (cfg_rdata_o), + .exp_h_offset_o (viv_s0), + .exp_v_offset_o (viv_s1), + .exp_h_size_o (viv_s2), + .exp_v_size_o (viv_s3), + .exp_mean_data_i (viv_s48), + .exp_mean_addr_i (viv_s49), + .exp_mean_val_i (viv_s50), + .exp_alt_mode_o (exp_alt_mode_o), + .exp_ena_o (viv_s51), + .exp_ena_rst_i (viv_s52), + .autostop_o (viv_s53) + ); + vsisp_isp_exp_ctrl u_isp_exp_ctrl + ( + .val_buf_i ( viv_s5 ), + .current_x_block_i ( viv_s6 ), + .current_y_block_i ( viv_s7 ), + .x_counter_i ( viv_s8[10:0]), + .y_counter_i ( viv_s9[10:0]), + .exp_h_size_i ( viv_s2 ), + .exp_v_size_i ( viv_s3 ), + .sb_accu_val_o ( viv_s22 ), + .sel_sb_accu_o ( viv_s19 ), + .sel_rst_sb_accu_o ( viv_s20 ), + .rst_sb_accu_o ( viv_s21 ), + .sel_sb_accu_mux_o ( viv_s24 ), + .sel_divider_mux_o ( viv_s26 ), + .sel_divisor_mux_o ( viv_s28 ), + .sb_mean_accu_val_o ( viv_s39 ), + .sel_sb_mean_accu_o ( viv_s34 ), + .sel_rst_sb_mean_accu_o ( viv_s35 ), + .rst_sb_mean_accu_o ( viv_s36 ), + .sel_sb_mean_accu_mux_o ( viv_s38 ), + .denorm_start_o ( viv_s40 ), + .divider_start_o ( viv_s45 ), + .exp_mean_addr_o ( viv_s49 ), + .exp_mean_val_o ( viv_s50 ) + ); + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + viv_s55 <= 1'b0; + viv_s56 <= 1'b0; + end + else begin + if (soft_rst) begin + viv_s55 <= 1'b0; + viv_s56 <= 1'b0; + end else begin + viv_s56 <= 1'b0; + if (regs_gen_cfg_upd) begin + viv_s55 <= 1'b1; + end + if (val_i && ack_i && h_end_i && v_end_i) begin + viv_s55 <= 1'b0; + if (viv_s55) begin + viv_s56 <= viv_s55; + end + end + end + end + end + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + viv_s54 <= 1'b0; + viv_s52 <= 1'b0; + end + else begin + if (soft_rst) begin + viv_s54 <= 1'b0; + viv_s52 <= 1'b1; + end else begin + viv_s52 <= 1'b0; + viv_s54 <= viv_s51; + if (val_i && ack_i && h_end_i && v_end_i) begin + if (viv_s53) begin + viv_s52 <= 1'b1; + end + end + end + end + end + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + viv_s4 <= 8'd0; + viv_s5 <= 1'b0; + end + else begin + if (soft_rst) begin + viv_s4 <= 8'd0; + viv_s5 <= 1'b0; + end else begin + viv_s4 <= y_i; + viv_s5 <= (val_i && ack_i && viv_s54); + end + end + end + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + viv_s6 <= 3'd7; + viv_s7 <= 3'd7; + viv_s8 <= 13'd0; + viv_s9 <= 13'd0; + end + else begin + if (soft_rst) begin + viv_s6 <= 3'd7; + viv_s7 <= 3'd7; + viv_s8 <= 13'd0; + viv_s9 <= 13'd0; + end else begin + if (regs_cfg_upd | viv_s56) begin + viv_s8 <= viv_s0; + viv_s9 <= (viv_s1 == 13'd0) ? + (viv_s1) : + (viv_s1 - 13'd1); + end + if (val_i && ack_i) begin + if (h_end_i && v_end_i) begin + viv_s6 <= 3'd7; + viv_s7 <= 3'd7; + viv_s8 <= viv_s0; + viv_s9 <= (viv_s1 == 13'd0) ? + (viv_s1 ) : + ((viv_s1 - 13'd1 ) ); + end + else begin + if ( h_end_i ) begin + viv_s6 <= 3'd7; + viv_s8 <= viv_s0; + if( viv_s7 != 3'd6) begin + if( viv_s9 == 13'd0 ) begin + viv_s7 <= (viv_s7 + 3'd1); + viv_s9 <= viv_s11; + end + else begin + viv_s9 <= (viv_s9 - 13'd1); + end + end + end + else begin + if ((viv_s7 == 3'd7) && (viv_s1==13'd0)) begin + viv_s7 <= (viv_s7 + 3'd1); + viv_s9 <= viv_s11; + end + if( viv_s6 != 3'd5) begin + if( viv_s8 == 13'd0 ) begin + viv_s6 <= (viv_s6 + 3'd1); + viv_s8 <= viv_s10; + end + else begin + viv_s8 <= (viv_s8 - 13'd1); + end + end + end + end + end + end + end + end + assign viv_s10 = {2'd0, (viv_s2 - 11'd1)}; + assign viv_s11 = {2'd0, (viv_s3 - 11'd1)}; + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + viv_s12 <= 11'd0; + viv_s13 <= 11'd0; + end + else begin + if (regs_cfg_upd | viv_s56) begin + viv_s12 <= viv_s2; + viv_s13 <= viv_s3; + end + end + end + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + viv_s14 <= 20'd0; + viv_s15 <= 20'd0; + viv_s16 <= 20'd0; + viv_s17 <= 20'd0; + viv_s18 <= 20'd0; + end + else begin + if (soft_rst) begin + viv_s14 <= 20'd0; + viv_s15 <= 20'd0; + viv_s16 <= 20'd0; + viv_s17 <= 20'd0; + viv_s18 <= 20'd0; + end + else begin + if (viv_s21) begin + case ( viv_s20 ) + 3'd0: viv_s14 <= 20'd0; + 3'd1: viv_s15 <= 20'd0; + 3'd2: viv_s16 <= 20'd0; + 3'd3: viv_s17 <= 20'd0; + 3'd4: viv_s18 <= 20'd0; + default: begin end + endcase + end + if (viv_s22) begin + case ( viv_s19 ) + 3'd0: viv_s14 <= (viv_s14 + {12'd0, viv_s4}); + 3'd1: viv_s15 <= (viv_s15 + {12'd0, viv_s4}); + 3'd2: viv_s16 <= (viv_s16 + {12'd0, viv_s4}); + 3'd3: viv_s17 <= (viv_s17 + {12'd0, viv_s4}); + 3'd4: viv_s18 <= (viv_s18 + {12'd0, viv_s4}); + default: begin end + endcase + end + end + end + end + always @( viv_s24 or viv_s14 or viv_s15 or viv_s16 or + viv_s17 or viv_s18 ) begin + case ( viv_s24 ) + 3'd0: viv_s23 = viv_s14; + 3'd1: viv_s23 = viv_s15; + 3'd2: viv_s23 = viv_s16; + 3'd3: viv_s23 = viv_s17; + 3'd4: viv_s23 = viv_s18; + default: viv_s23 = 20'd0; + endcase + end + assign viv_s25 = viv_s26 ? {2'b0, viv_s37} : {viv_s23, 2'b0}; + assign viv_s27 = viv_s28 ? viv_s12 : viv_s13 ; + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + viv_s29 <= 20'd0; + viv_s30 <= 20'd0; + viv_s31 <= 20'd0; + viv_s32 <= 20'd0; + viv_s33 <= 20'd0; + end + else begin + if ( soft_rst ) begin + viv_s29 <= 20'd0; + viv_s30 <= 20'd0; + viv_s31 <= 20'd0; + viv_s32 <= 20'd0; + viv_s33 <= 20'd0; + end + else begin + if (viv_s36) begin + case ( viv_s35 ) + 3'd0: viv_s29 <= 20'd0; + 3'd1: viv_s30 <= 20'd0; + 3'd2: viv_s31 <= 20'd0; + 3'd3: viv_s32 <= 20'd0; + 3'd4: viv_s33 <= 20'd0; + default: begin end + endcase + end + else begin + if (viv_s39) begin + case ( viv_s34 ) + 3'd0: viv_s29 <= (viv_s29 + {10'd0, viv_s44}); + 3'd1: viv_s30 <= (viv_s30 + {10'd0, viv_s44}); + 3'd2: viv_s31 <= (viv_s31 + {10'd0, viv_s44}); + 3'd3: viv_s32 <= (viv_s32 + {10'd0, viv_s44}); + 3'd4: viv_s33 <= (viv_s33 + {10'd0, viv_s44}); + default: begin end + endcase + end + end + end + end + end + always @( viv_s38 or viv_s29 or + viv_s30 or viv_s31 or + viv_s32 or viv_s33 ) begin + case ( viv_s38 ) + 3'd0: viv_s37 = viv_s29; + 3'd1: viv_s37 = viv_s30; + 3'd2: viv_s37 = viv_s31; + 3'd3: viv_s37 = viv_s32; + 3'd4: viv_s37 = viv_s33; + default: viv_s37 = 20'd0; + endcase + end + always @(posedge clk or negedge reset_n) begin + if(!reset_n) begin + viv_s41 <= 4'd0; + viv_s43 <= 23'd0; + viv_s47 <= 11'd0; + end + else if (viv_s45) begin + viv_s41 <= 4'd0; + viv_s43 <= {1'b0, viv_s25}; + viv_s47 <= viv_s27; + end + else if (!viv_s46) begin + if(viv_s42[22]) begin + viv_s43 <= {viv_s43[21:0],1'b0}; + end + else begin + viv_s43 <= {viv_s42[21:0],1'b1}; + end + viv_s41 <= viv_s41 + 4'd1; + end + end + assign viv_s42 = ( viv_s43 - {2'b0, viv_s47, 10'd0} ); + assign viv_s46 = (viv_s41 == 4'd10); + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + viv_s44 <= 10'd0; + end + else if (viv_s40) begin + viv_s44 <= viv_s43[9:0]; + end + end + assign viv_s48 = viv_s44[7:0]; + assign measure_complete = ( (viv_s49 == 6'b100100) && viv_s50 ); +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_exp_ctrl.v b/ispyocto/rtl/ispyocto/vsisp_isp_exp_ctrl.v new file mode 100644 index 0000000..716e711 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_isp_exp_ctrl.v
@@ -0,0 +1,223 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_isp_exp_ctrl + ( + val_buf_i, + current_x_block_i, + current_y_block_i, + x_counter_i, + y_counter_i, + exp_h_size_i, + exp_v_size_i, + sb_accu_val_o, + sel_sb_accu_o, + sel_rst_sb_accu_o, + rst_sb_accu_o, + sel_sb_accu_mux_o, + sel_divider_mux_o, + sel_divisor_mux_o, + sb_mean_accu_val_o, + sel_sb_mean_accu_o, + sel_rst_sb_mean_accu_o, + rst_sb_mean_accu_o, + sel_sb_mean_accu_mux_o, + denorm_start_o, + divider_start_o, + exp_mean_addr_o, + exp_mean_val_o + ); +input val_buf_i; +input [2:0] current_x_block_i; +input [2:0] current_y_block_i; +input [10:0] x_counter_i; +input [10:0] y_counter_i; +input [10:0] exp_h_size_i; +input [10:0] exp_v_size_i; +output sb_accu_val_o; +output [2:0] sel_sb_accu_o; +output [2:0] sel_rst_sb_accu_o; +output rst_sb_accu_o; +output [2:0] sel_sb_accu_mux_o; +output sel_divider_mux_o; +output sel_divisor_mux_o; +output sb_mean_accu_val_o; +output [2:0] sel_sb_mean_accu_o; +output [2:0] sel_rst_sb_mean_accu_o; +output rst_sb_mean_accu_o; +output [2:0] sel_sb_mean_accu_mux_o; +output denorm_start_o; +output divider_start_o; +output [5:0] exp_mean_addr_o; +output exp_mean_val_o; +reg [2:0] sel_rst_sb_accu_o; +reg [2:0] sel_rst_sb_mean_accu_o; +reg [2:0] sel_sb_mean_accu_mux_o; +wire viv_s0; +wire viv_s1; +wire viv_s2; +wire viv_s3; +wire viv_s4; + assign sb_accu_val_o = (val_buf_i && ((current_x_block_i >= 3'd0) && + (current_x_block_i <= 3'd4) && + (current_y_block_i >= 3'd0) && + (current_y_block_i <= 3'd4))); + assign sb_mean_accu_val_o = (( + ((viv_s0 == 1'b1) && + (current_y_block_i == 3'd0) && + (current_x_block_i < 3'd3) && + (x_counter_i == (exp_h_size_i-11'd1) ) && + (y_counter_i != (exp_v_size_i-11'd1)) ) || + ((viv_s0 == 1'b1) && + (current_y_block_i != 3'd0) && + (current_y_block_i < 3'd5) && + (x_counter_i == (exp_h_size_i-11'd1) ) && + (current_x_block_i < 3'd3) ) || + ((y_counter_i == (exp_v_size_i-11'd1)) && + (current_y_block_i == 3'd5) && + (x_counter_i == (exp_h_size_i-11'd1) ) && + (current_x_block_i < 3'd3) ) || + ((viv_s0 == 1'b0) && + (current_x_block_i > 3'd2) && + (current_x_block_i < 3'd5) && + (current_y_block_i < 3'd5) && + (x_counter_i == (exp_h_size_i-11'd1) )) ) && val_buf_i); + assign rst_sb_mean_accu_o = exp_mean_val_o; + assign viv_s0 = y_counter_i[0]; + assign divider_start_o = ((viv_s1 || viv_s2) && + val_buf_i); + assign rst_sb_accu_o = viv_s1; + assign sel_divisor_mux_o = viv_s1; + assign sel_divider_mux_o = viv_s2; + assign viv_s1 = ( + ((viv_s0 == 1'b1) && + (current_x_block_i == 3'd0) && + (current_y_block_i == 3'd0) && + (y_counter_i != (exp_v_size_i-11'd1) ) && + (x_counter_i == (exp_h_size_i-11'd1) )) || + ((viv_s0 == 1'b1) && + (current_x_block_i == 3'd0) && + (current_y_block_i != 3'd0) && + (x_counter_i == (exp_h_size_i-11'd1) )) || + ((viv_s0 == 1'b0) && + (current_x_block_i != 3'd0) && + (current_x_block_i < 3'd5) && + (current_y_block_i < 3'd5) && + (x_counter_i == (exp_h_size_i-11'd1) )) ); + assign viv_s2 = ( + ((viv_s0 == 1'b0) && + (current_y_block_i != 3'd0) && + (current_y_block_i < 3'd6) && + (y_counter_i == (exp_v_size_i-11'd2)) && + (x_counter_i == (exp_h_size_i-11'd1) ) && + (current_x_block_i == 3'd0) ) || + ((viv_s0 == 1'b1) && + (current_x_block_i != 3'd0) && + (current_x_block_i < 3'd5) && + (current_y_block_i != 3'd0) && + (current_y_block_i < 3'd6) && + (y_counter_i == (exp_v_size_i-11'd1)) && + (x_counter_i == (exp_h_size_i-11'd1) ))); + assign denorm_start_o = ((viv_s3 || viv_s4) && + val_buf_i); + assign viv_s3 = ( + ((viv_s0 == 1'b1) && + (current_x_block_i < 3'd2) && + (current_y_block_i == 3'd0) && + (x_counter_i == (exp_h_size_i-11'd1)) && + (y_counter_i != (exp_v_size_i-11'd1)) ) || + ((viv_s0 == 1'b1) && + (current_x_block_i < 3'd2) && + (x_counter_i == (exp_h_size_i-11'd1) ) && + (current_y_block_i != 3'd0) ) || + ((viv_s0 == 1'b0) && + (current_x_block_i > 3'd1) && + (current_x_block_i < 3'd5) && + (x_counter_i == (exp_h_size_i-11'd1) ) && + (current_y_block_i < 3'd5) )); + assign viv_s4 = ( + ((viv_s0 == 1'b0) && + (current_y_block_i != 3'd0) && + (current_x_block_i < 3'd2) && + (y_counter_i == (exp_v_size_i-11'd2)) && + (x_counter_i == (exp_h_size_i-11'd1))) || + ((viv_s0 == 1'b1) && + (current_y_block_i != 3'd0) && + (current_x_block_i > 3'd1) && + (current_x_block_i < 3'd5) && + (y_counter_i == (exp_v_size_i-11'd1)) && + (x_counter_i == (exp_h_size_i-11'd1)) )); + assign exp_mean_val_o = (( + ((viv_s0 == 1'b0) && + (current_x_block_i < 3'd3) && + (current_y_block_i != 3'd0) && + (current_y_block_i < 3'd6) && + (x_counter_i == (exp_h_size_i-11'd1)) && + (y_counter_i == (exp_v_size_i-11'd2)) ) || + ((viv_s0 == 1'b1) && + (current_x_block_i > 3'd2) && + (current_x_block_i < 3'd5) && + (current_y_block_i != 3'd0) && + (current_y_block_i < 3'd6) && + (x_counter_i == (exp_h_size_i-11'd1)) && + (y_counter_i == (exp_v_size_i-11'd1)) ) ) && val_buf_i); + assign exp_mean_addr_o = { (current_x_block_i < 3'd3) ? + (current_x_block_i + 3'd2) : + (current_x_block_i - 3'd3) ,(current_y_block_i-3'd1) }; + assign sel_sb_accu_mux_o = (current_x_block_i == 3'd0) ? 3'd4 : + (current_x_block_i - 3'd1) ; + always @( current_x_block_i ) begin + case (current_x_block_i) + 3'd0: sel_sb_mean_accu_mux_o = 3'd4; + 3'd1: sel_sb_mean_accu_mux_o = 3'd0; + 3'd2: sel_sb_mean_accu_mux_o = 3'd1; + 3'd3: sel_sb_mean_accu_mux_o = 3'd2; + 3'd4: sel_sb_mean_accu_mux_o = 3'd3; + default: sel_sb_mean_accu_mux_o = 3'd7; + endcase + end + assign sel_sb_accu_o = current_x_block_i; + assign sel_sb_mean_accu_o = (current_x_block_i > 3'd2) ? + (current_x_block_i - 3'd3) : + (current_x_block_i + 3'd2); + always @( current_x_block_i ) begin + case (current_x_block_i) + 3'd0: sel_rst_sb_mean_accu_o = 3'd2; + 3'd1: sel_rst_sb_mean_accu_o = 3'd3; + 3'd2: sel_rst_sb_mean_accu_o = 3'd4; + 3'd3: sel_rst_sb_mean_accu_o = 3'd0; + 3'd4: sel_rst_sb_mean_accu_o = 3'd1; + default: sel_rst_sb_mean_accu_o = 3'd7; + endcase + end + always @( current_x_block_i ) begin + case (current_x_block_i) + 3'd0: sel_rst_sb_accu_o = 3'd4; + 3'd1: sel_rst_sb_accu_o = 3'd0; + 3'd2: sel_rst_sb_accu_o = 3'd1; + 3'd3: sel_rst_sb_accu_o = 3'd2; + 3'd4: sel_rst_sb_accu_o = 3'd3; + default: sel_rst_sb_accu_o = 3'd7; + endcase + end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_exp_regs.v b/ispyocto/rtl/ispyocto/vsisp_isp_exp_regs.v new file mode 100644 index 0000000..fdee270 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_isp_exp_regs.v
@@ -0,0 +1,246 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_isp_exp_regs + ( + clk, + reset_n, + clk_cfg, + reset_cfg_n, + cfg_val_i, + cfg_addr_i, + cfg_rd_i, + cfg_wdata_i, + cfg_rdata_o, + exp_h_offset_o, + exp_v_offset_o, + exp_h_size_o, + exp_v_size_o, + exp_mean_data_i, + exp_mean_addr_i, + exp_mean_val_i, + exp_alt_mode_o, + exp_ena_o, + exp_ena_rst_i, + autostop_o + ); +`include "vsisp_isp.vh" + input clk; + input reset_n; + input clk_cfg; + input reset_cfg_n; + input cfg_val_i; + input [13: 2] cfg_addr_i; + input cfg_rd_i; + input [31: 0] cfg_wdata_i; + output [31: 0] cfg_rdata_o; + reg [31: 0] cfg_rdata_o; + output [12: 0] exp_h_offset_o; + output [12: 0] exp_v_offset_o; + output [10: 0] exp_h_size_o; + output [10: 0] exp_v_size_o; + input [ 7: 0] exp_mean_data_i; + input [ 5: 0] exp_mean_addr_i; + input exp_mean_val_i; + output exp_alt_mode_o; + output exp_ena_o; + input exp_ena_rst_i; + output autostop_o; + reg exp_alt_mode_o; + reg exp_ena_o; + reg autostop_o; + reg [12: 0] exp_h_offset_o; + reg [12: 0] exp_v_offset_o; + reg [10: 0] exp_h_size_o; + reg [10: 0] exp_v_size_o; + reg [ 7: 0] viv_s0; + reg [ 7: 0] viv_s1; + reg [ 7: 0] viv_s2; + reg [ 7: 0] viv_s3; + reg [ 7: 0] viv_s4; + reg [ 7: 0] viv_s5; + reg [ 7: 0] viv_s6; + reg [ 7: 0] viv_s7; + reg [ 7: 0] viv_s8; + reg [ 7: 0] viv_s9; + reg [ 7: 0] viv_s10; + reg [ 7: 0] viv_s11; + reg [ 7: 0] viv_s12; + reg [ 7: 0] viv_s13; + reg [ 7: 0] viv_s14; + reg [ 7: 0] viv_s15; + reg [ 7: 0] viv_s16; + reg [ 7: 0] viv_s17; + reg [ 7: 0] viv_s18; + reg [ 7: 0] viv_s19; + reg [ 7: 0] viv_s20; + reg [ 7: 0] viv_s21; + reg [ 7: 0] viv_s22; + reg [ 7: 0] viv_s23; + reg [ 7: 0] viv_s24; + always @( cfg_addr_i or exp_h_offset_o or exp_v_offset_o or + exp_h_size_o or exp_v_size_o or viv_s0 or + viv_s1 or viv_s2 or viv_s3 or + viv_s4 or viv_s5 or viv_s6 or + viv_s7 or viv_s8 or viv_s9 or + viv_s10 or viv_s11 or viv_s12 or + viv_s13 or viv_s14 or viv_s15 or + viv_s16 or viv_s17 or viv_s18 or + viv_s19 or viv_s20 or viv_s21 or + viv_s22 or viv_s23 or viv_s24 or + autostop_o or exp_ena_o or exp_alt_mode_o) begin + case (cfg_addr_i) + c_exp_conf[13:2] : cfg_rdata_o = { exp_alt_mode_o, 29'd0, autostop_o, exp_ena_o }; + c_exp_h_offset[13:2] : cfg_rdata_o = { 19'd0, exp_h_offset_o }; + c_exp_v_offset[13:2] : cfg_rdata_o = { 19'd0, exp_v_offset_o }; + c_exp_h_size[13:2] : cfg_rdata_o = { 21'd0, exp_h_size_o }; + c_exp_v_size[13:2] : cfg_rdata_o = { 21'd0, exp_v_size_o }; + c_exp_mean_00[13:2] : cfg_rdata_o = { 24'd0, viv_s0 }; + c_exp_mean_10[13:2] : cfg_rdata_o = { 24'd0, viv_s1 }; + c_exp_mean_20[13:2] : cfg_rdata_o = { 24'd0, viv_s2 }; + c_exp_mean_30[13:2] : cfg_rdata_o = { 24'd0, viv_s3 }; + c_exp_mean_40[13:2] : cfg_rdata_o = { 24'd0, viv_s4 }; + c_exp_mean_01[13:2] : cfg_rdata_o = { 24'd0, viv_s5 }; + c_exp_mean_11[13:2] : cfg_rdata_o = { 24'd0, viv_s6 }; + c_exp_mean_21[13:2] : cfg_rdata_o = { 24'd0, viv_s7 }; + c_exp_mean_31[13:2] : cfg_rdata_o = { 24'd0, viv_s8 }; + c_exp_mean_41[13:2] : cfg_rdata_o = { 24'd0, viv_s9 }; + c_exp_mean_02[13:2] : cfg_rdata_o = { 24'd0, viv_s10 }; + c_exp_mean_12[13:2] : cfg_rdata_o = { 24'd0, viv_s11 }; + c_exp_mean_22[13:2] : cfg_rdata_o = { 24'd0, viv_s12 }; + c_exp_mean_32[13:2] : cfg_rdata_o = { 24'd0, viv_s13 }; + c_exp_mean_42[13:2] : cfg_rdata_o = { 24'd0, viv_s14 }; + c_exp_mean_03[13:2] : cfg_rdata_o = { 24'd0, viv_s15 }; + c_exp_mean_13[13:2] : cfg_rdata_o = { 24'd0, viv_s16 }; + c_exp_mean_23[13:2] : cfg_rdata_o = { 24'd0, viv_s17 }; + c_exp_mean_33[13:2] : cfg_rdata_o = { 24'd0, viv_s18 }; + c_exp_mean_43[13:2] : cfg_rdata_o = { 24'd0, viv_s19 }; + c_exp_mean_04[13:2] : cfg_rdata_o = { 24'd0, viv_s20 }; + c_exp_mean_14[13:2] : cfg_rdata_o = { 24'd0, viv_s21 }; + c_exp_mean_24[13:2] : cfg_rdata_o = { 24'd0, viv_s22 }; + c_exp_mean_34[13:2] : cfg_rdata_o = { 24'd0, viv_s23 }; + c_exp_mean_44[13:2] : cfg_rdata_o = { 24'd0, viv_s24 }; + default : cfg_rdata_o = 32'd0; + endcase + end + always @(posedge clk_cfg or negedge reset_cfg_n) begin + if (~reset_cfg_n) begin + exp_ena_o <= 1'b0; + autostop_o <= 1'b0; + exp_alt_mode_o <= 1'b0; + exp_h_offset_o <= 13'd0; + exp_v_offset_o <= 13'd0; + exp_h_size_o <= 11'd0; + exp_v_size_o <= 11'd0; + end + else begin + if (exp_ena_rst_i) begin + exp_ena_o <= 1'b0; + end + if (cfg_val_i && ~cfg_rd_i) begin + case (cfg_addr_i) + c_exp_conf[13:2] : begin + exp_alt_mode_o <= cfg_wdata_i[31]; + exp_ena_o <= cfg_wdata_i[0: 0]; + autostop_o <= cfg_wdata_i[1: 1]; + end + c_exp_h_offset[13:2] : begin + exp_h_offset_o <= cfg_wdata_i[12: 0]; + end + c_exp_v_offset[13:2] : begin + exp_v_offset_o <= cfg_wdata_i[12: 0]; + end + c_exp_h_size[13:2] : begin + exp_h_size_o <= cfg_wdata_i[10: 0]; + end + c_exp_v_size[13:2] : begin + exp_v_size_o <= cfg_wdata_i[10: 0]; + end + default : begin + end + endcase + end + end + end + always @(posedge clk or negedge reset_n) begin + if (~reset_n) begin + viv_s0 <= 8'd0; + viv_s1 <= 8'd0; + viv_s2 <= 8'd0; + viv_s3 <= 8'd0; + viv_s4 <= 8'd0; + viv_s5 <= 8'd0; + viv_s6 <= 8'd0; + viv_s7 <= 8'd0; + viv_s8 <= 8'd0; + viv_s9 <= 8'd0; + viv_s10 <= 8'd0; + viv_s11 <= 8'd0; + viv_s12 <= 8'd0; + viv_s13 <= 8'd0; + viv_s14 <= 8'd0; + viv_s15 <= 8'd0; + viv_s16 <= 8'd0; + viv_s17 <= 8'd0; + viv_s18 <= 8'd0; + viv_s19 <= 8'd0; + viv_s20 <= 8'd0; + viv_s21 <= 8'd0; + viv_s22 <= 8'd0; + viv_s23 <= 8'd0; + viv_s24 <= 8'd0; + end + else begin + if (exp_mean_val_i) begin + case (exp_mean_addr_i) + 6'b000000 : viv_s0 <= exp_mean_data_i; + 6'b001000 : viv_s1 <= exp_mean_data_i; + 6'b010000 : viv_s2 <= exp_mean_data_i; + 6'b011000 : viv_s3 <= exp_mean_data_i; + 6'b100000 : viv_s4 <= exp_mean_data_i; + 6'b000001 : viv_s5 <= exp_mean_data_i; + 6'b001001 : viv_s6 <= exp_mean_data_i; + 6'b010001 : viv_s7 <= exp_mean_data_i; + 6'b011001 : viv_s8 <= exp_mean_data_i; + 6'b100001 : viv_s9 <= exp_mean_data_i; + 6'b000010 : viv_s10 <= exp_mean_data_i; + 6'b001010 : viv_s11 <= exp_mean_data_i; + 6'b010010 : viv_s12 <= exp_mean_data_i; + 6'b011010 : viv_s13 <= exp_mean_data_i; + 6'b100010 : viv_s14 <= exp_mean_data_i; + 6'b000011 : viv_s15 <= exp_mean_data_i; + 6'b001011 : viv_s16 <= exp_mean_data_i; + 6'b010011 : viv_s17 <= exp_mean_data_i; + 6'b011011 : viv_s18 <= exp_mean_data_i; + 6'b100011 : viv_s19 <= exp_mean_data_i; + 6'b000100 : viv_s20 <= exp_mean_data_i; + 6'b001100 : viv_s21 <= exp_mean_data_i; + 6'b010100 : viv_s22 <= exp_mean_data_i; + 6'b011100 : viv_s23 <= exp_mean_data_i; + 6'b100100 : viv_s24 <= exp_mean_data_i; + default : viv_s24 <= exp_mean_data_i; + endcase + end + end + end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_filt.v b/ispyocto/rtl/ispyocto/vsisp_isp_filt.v new file mode 100644 index 0000000..0b31624 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_isp_filt.v
@@ -0,0 +1,798 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_isp_filt + ( + clk, + reset_n, + clk_cfg, + reset_cfg_n, + soft_rst, + cfg_val, + cfg_addr, + cfg_rd, + cfg_wdata, + cfg_rdata, + in_data, + in_h_end, + in_v_end, + in_val, + in_ack, + regs_demosaic_th, + regs_dem_bypass, + regs_bayer_pat, + regs_cfg_upd, + regs_gen_cfg_upd, + filt_data, + filt_h_end, + filt_v_end, + filt_val, + filt_ack, + meas_val, + meas_h_end, + meas_v_end, + meas_data_t, + meas_data_m, + meas_data_b, + adr, + we_n, + cs_n, + wr_data, + rd_data); +`include "vsisp_isp.vh" +`include "vsisp_ram_sizes.vh" + parameter c_dw_rgb = 3*c_dw_si; + input clk; + input reset_n; + input clk_cfg; + input reset_cfg_n; + input soft_rst; + input cfg_val; + input [c_cfg_filt-1:2] cfg_addr; + input cfg_rd; + input [31:0] cfg_wdata; + output [31:0] cfg_rdata; + input [c_dw_si-1:0] in_data; + input in_h_end; + input in_v_end; + input in_val; + output in_ack; + input [7:0] regs_demosaic_th; + input regs_dem_bypass; + input [1:0] regs_bayer_pat; + input regs_cfg_upd; + input regs_gen_cfg_upd; + output [c_dw_rgb-1:0] filt_data; + output filt_h_end; + output filt_v_end; + output filt_val; + input filt_ack; + output meas_val; + output meas_h_end; + output meas_v_end; + output [c_dw_si-1:0] meas_data_t; + output [c_dw_si-1:0] meas_data_m; + output [c_dw_si-1:0] meas_data_b; + output [c_aw_dem_mem-1:0] adr; + output we_n; + output cs_n; + output [c_dw_dem_mem-1:0] wr_data; + input [c_dw_dem_mem-1:0] rd_data; + wire viv_s0; + wire [1:0] viv_s1; + wire [1:0] viv_s2; + wire viv_s3; + wire [3:0] viv_s4; + wire [3:0] viv_s5; + wire [5:0] viv_s6; + wire [5:0] viv_s7; + wire [5:0] viv_s8; + wire [5:0] viv_s9; + wire [5:0] viv_s10; + wire [5:0] viv_s11; + wire [9:0] viv_s12; + wire [9:0] viv_s13; + wire [9:0] viv_s14; + wire [9:0] viv_s15; + wire [2:0] viv_s16; + wire [7:0] viv_s17; + wire [7:0] viv_s18; + reg viv_s19; + reg viv_s20; + wire viv_s21; + wire viv_s22; + wire [1:0] viv_s23; + wire [12:0] viv_s24; + wire [12:0] viv_s25; + wire [4:0] viv_s26; + wire [4:0] viv_s27; + wire [3:0] viv_s28; + wire [3:0] viv_s29; + wire [8:0] viv_s30; + wire [8:0] viv_s31; + wire [8:0] viv_s32; + wire [8:0] viv_s33; + wire [8:0] viv_s34; + wire [8:0] viv_s35; + wire [c_dw_si+1:0] viv_s36; + wire [c_dw_si+1:0] viv_s37; + wire viv_s38; + wire viv_s39; + wire viv_s40; + wire viv_s41; + wire viv_s42; + wire [c_dw_si-1:0] viv_s43; + wire [c_dw_si+1:0] viv_s44; + wire viv_s45; + wire viv_s46; + wire viv_s47; + wire viv_s48; + wire viv_s49; + wire viv_s50; + wire viv_s51; + wire viv_s52; + wire viv_s53; + wire viv_s54; + wire viv_s55; + wire [c_dw_si-1:0] viv_s56; + wire [c_dw_si-1:0] viv_s57; + wire [c_dw_si-1:0] viv_s58; + wire [c_dw_si-1:0] viv_s59; + wire [c_dw_si-1:0] viv_s60; + wire [c_dw_si-1:0] viv_s61; + wire [c_dw_si-1:0] viv_s62; + wire [3:0] viv_s63; + wire [3:0] viv_s64; + wire [3:0] viv_s65; + wire viv_s66; + wire [4:0] viv_s67; + wire [7:0] viv_s68; + wire [7:0] viv_s69; + wire viv_s70; + wire viv_s71; + wire viv_s72; + wire viv_s73; + wire viv_s74; + wire viv_s75; + wire [c_dw_si-1:0] viv_s76; + wire [c_dw_si-1:0] viv_s77; + wire [c_dw_si-1:0] viv_s78; + wire [c_dw_si-1:0] viv_s79; + wire [c_dw_si-1:0] viv_s80; + wire [c_dw_si-1:0] viv_s81; + wire [c_dw_si-1:0] viv_s82; + wire [c_dw_si-1:0] viv_s83; + wire [c_dw_si-1:0] viv_s84; + wire [7:0] viv_s85; + wire [7:0] viv_s86; + wire [c_dw_si-1:0] viv_s87; + wire [c_dw_si-1:0] viv_s88; + wire [c_dw_si-1:0] viv_s89; + wire [7:0] viv_s90; + wire [7:0] viv_s91; + wire [c_dw_si-1:0] viv_s92; + wire [c_dw_si-1:0] viv_s93; + wire [c_dw_si-1:0] viv_s94; + wire [7:0] viv_s95; + wire [7:0] viv_s96; + wire [c_dw_si-1:0] viv_s97; + wire [c_dw_si-1:0] viv_s98; + wire [c_dw_si-1:0] viv_s99; + wire [7:0] viv_s100; + wire [7:0] viv_s101; + wire [c_dw_si-1:0] viv_s102; + wire [c_dw_si-1:0] viv_s103; + wire [c_dw_si-1:0] viv_s104; + wire [7:0] viv_s105; + wire [7:0] viv_s106; + wire viv_s107; + wire viv_s108; + wire viv_s109; + wire viv_s110; + wire viv_s111; + wire viv_s112; + wire viv_s113; + wire viv_s114; + wire viv_s115; + wire viv_s116; + wire viv_s117; + wire viv_s118; + wire viv_s119; + wire viv_s120; + wire viv_s121; + wire [c_dw_si:0] viv_s122; + wire [c_dw_si:0] viv_s123; + wire [c_dw_si-1:0] viv_s124; + wire [c_dw_si:0] viv_s125; + wire [c_dw_si:0] viv_s126; + wire [2*c_dw_si+1:0] viv_s127; + wire [2*c_dw_si+1:0] viv_s128; + wire [c_dw_si:0] viv_s129; + wire [c_dw_si:0] viv_s130; + wire [2:0] viv_s131; + wire viv_s132; + wire [2:0] viv_s133; + wire viv_s134; + wire viv_s135; + wire [1:0] viv_s136; + wire [1:0] viv_s137; + wire viv_s138; + wire viv_s139; + wire viv_s140; + wire viv_s141; + wire viv_s142; + wire viv_s143; + wire [1:0] viv_s144; + wire [1:0] viv_s145; + wire viv_s146; + wire viv_s147; + wire viv_s148; + wire viv_s149; + wire viv_s150; + wire viv_s151; + wire viv_s152; + wire viv_s153; + wire viv_s154; + wire viv_s155; + wire viv_s156; + wire viv_s157; + wire viv_s158; + wire viv_s159; + wire viv_s160; + wire viv_s161; + wire viv_s162; + wire [c_dw_si+2:0] viv_s163; + wire [c_dw_si+1:0] viv_s164; + wire [c_dw_si+2:0] viv_s165; + wire [c_dw_si+1:0] viv_s166; + wire viv_s167; + wire viv_s168; + wire viv_s169; + wire viv_s170; + wire [c_dw_si+1:0] viv_s171; + wire [2*c_dw_si+1:0] viv_s172; + wire [4*c_dw_si+12:0] viv_s173; + wire [4*c_dw_si+12:0] viv_s174; + wire viv_s175; + assign viv_s36 = {in_data, + in_h_end, + in_v_end}; + assign {viv_s43, + viv_s40, + viv_s41} = viv_s44; + assign viv_s127 = {viv_s129, viv_s130}; + assign viv_s5 = viv_s0 ? viv_s4 : 4'h8; + assign viv_s71 = viv_s55 ; + assign meas_val = viv_s54 & viv_s55; + assign meas_h_end = viv_s50; + assign meas_v_end = viv_s51; + assign meas_data_t = viv_s58; + assign meas_data_m = viv_s59; + assign meas_data_b = viv_s60; + always @ (posedge clk or negedge reset_n) begin + if (~reset_n) begin + viv_s19 <= 1'b0; + viv_s20 <= 1'b0; + end + else if (soft_rst) begin + viv_s19 <= 1'b0; + viv_s20 <= 1'b0; + end + else begin + if (regs_gen_cfg_upd) + viv_s19 <= 1'b1; + else if (viv_s148 && viv_s149 && viv_s146 && viv_s147) + viv_s19 <= 1'b0; + viv_s20 <= regs_cfg_upd || (viv_s19 && viv_s148 && viv_s149 && viv_s146 && viv_s147); + end + end + vsisp_isp_filt_regs u_isp_filt_regs + ( + .clk_cfg(clk_cfg), + .reset_cfg_n(reset_cfg_n), + .cfg_val(cfg_val), + .cfg_addr(cfg_addr), + .cfg_rd(cfg_rd), + .cfg_wdata(cfg_wdata), + .cfg_rdata(cfg_rdata), + .filt_enable(viv_s0), + .filt_lp_select(viv_s4), + .filt_chr_h_mode(viv_s1), + .filt_chr_v_mode(viv_s2), + .filt_mode(viv_s3), + .filt_fac_sh1(viv_s6), + .filt_fac_sh0(viv_s7), + .filt_fac_mid(viv_s8), + .filt_fac_bl0(viv_s9), + .filt_fac_bl1(viv_s10), + .filt_thres_bl0(viv_s12), + .filt_thres_bl1(viv_s13), + .filt_thres_sh0(viv_s14), + .filt_thres_sh1(viv_s15), + .lum_weight_gain(viv_s16), + .lum_weight_kink(viv_s17), + .lum_weight_min(viv_s18), + .cac_enable(viv_s21), + .cac_h_clip_mode(viv_s22), + .cac_v_clip_mode(viv_s23), + .cac_h_count_start(viv_s24), + .cac_v_count_start(viv_s25), + .cac_x_norm_factor(viv_s26), + .cac_y_norm_factor(viv_s27), + .cac_x_norm_shift(viv_s28), + .cac_y_norm_shift(viv_s29), + .cac_a_red(viv_s30), + .cac_b_red(viv_s31), + .cac_c_red(viv_s32), + .cac_a_blue(viv_s33), + .cac_b_blue(viv_s34), + .cac_c_blue(viv_s35)); + vsisp_isp_demosaic_dpsbe #(c_dw_si+2) u1_isp_demosaic_dpsbe + ( + .clk(clk), + .reset_n(reset_n), + .soft_rst(soft_rst), + .in_data(viv_s36), + .in_val(in_val), + .in_ack(in_ack), + .out_data(viv_s37), + .out_val(viv_s38), + .out_ack(viv_s39)); + vsisp_isp_dpsfe #(c_dw_si+2) u1_isp_dpsfe + ( + .clk(clk), + .reset_n(reset_n), + .soft_rst(soft_rst), + .in_data(viv_s37), + .in_val(viv_s38), + .in_ack(viv_s39), + .out_data(viv_s44), + .out_val(viv_s45), + .out_ack(viv_s42)); + vsisp_isp_line_mem_if u_isp_line_mem_if + ( + .clk(clk), + .reset_n(reset_n), + .soft_rst(soft_rst), + .in_val(viv_s45), + .in_h_end(viv_s40), + .in_v_end(viv_s41), + .in_data(viv_s43), + .in_ack(viv_s42), + .regs_bayer_pat(regs_bayer_pat), + .out_val(viv_s52), + .out_h_end(viv_s50), + .out_v_end(viv_s51), + .out_data_1t(viv_s56), + .out_data_m2(viv_s57), + .out_data_m3(viv_s58), + .out_data_m4(viv_s59), + .out_data_m5(viv_s60), + .out_data_m6(viv_s61), + .out_data_7b(viv_s62), + .out_ack(viv_s53), + .memif_h_end(viv_s48), + .memif_v_end(viv_s49), + .memif_val(viv_s46), + .memif_ack(viv_s47), + .adr(adr), + .we_n(we_n), + .cs_n(cs_n), + .wr_data(wr_data), + .rd_data(rd_data) + ); + vsisp_isp_cac_ctrl u_isp_cac_ctrl + ( + .clk(clk), + .reset_n(reset_n), + .soft_rst(soft_rst), + .memif_h_end(viv_s48), + .memif_v_end(viv_s49), + .memif_val(viv_s46), + .memif_ack(viv_s47), + .mem_h_end(viv_s50), + .mem_v_end(viv_s51), + .mem_val(viv_s52), + .mem_ack(viv_s53), + .cac_in_val(viv_s54), + .cac_in_ack(viv_s55), + .alom_stage1_en(viv_s107), + .alom_stage2_en(viv_s108), + .alom_stage3_en(viv_s109), + .alom_stage4_en(viv_s110), + .alom_stage5_en(viv_s111), + .alom_stage3_val(viv_s118), + .alom_stage5_val(viv_s120), + .regs_bayer_pat(regs_bayer_pat), + .cfg_upd(viv_s20), + .cac_enable(viv_s21), + .cac_h_clip_mode(viv_s22), + .cac_v_clip_mode(viv_s23), + .cac_h_count_start(viv_s24), + .cac_v_count_start(viv_s25), + .cac_x_norm_factor(viv_s26), + .cac_y_norm_factor(viv_s27), + .cac_x_norm_shift(viv_s28), + .cac_y_norm_shift(viv_s29), + .cac_a_red(viv_s30), + .cac_b_red(viv_s31), + .cac_c_red(viv_s32), + .cac_a_blue(viv_s33), + .cac_b_blue(viv_s34), + .cac_c_blue(viv_s35), + .cac_v_sel_1(viv_s63), + .cac_v_sel_2(viv_s64), + .cac_v_sel_3(viv_s65), + .cac_v_coef(viv_s67), + .cac_v_filt_disable(viv_s66), + .cac_h_red(viv_s68), + .cac_h_blue(viv_s69), + .cac_h_red_col(viv_s70)); + vsisp_isp_cac_ver u_isp_cac_ver + ( + .clk(clk), + .reset_n(reset_n), + .in_val(viv_s54), + .in_ack(viv_s55), + .in_h_end(viv_s50), + .in_v_end(viv_s51), + .mem_data_1t(viv_s56), + .mem_data_m2(viv_s57), + .mem_data_m3(viv_s58), + .mem_data_m4(viv_s59), + .mem_data_m5(viv_s60), + .mem_data_m6(viv_s61), + .mem_data_7b(viv_s62), + .cv_mask(viv_s136), + .regs_dem_bypass(regs_dem_bypass), + .cac_v_sel_1(viv_s63), + .cac_v_sel_2(viv_s64), + .cac_v_sel_3(viv_s65), + .cac_v_coef(viv_s67), + .cac_v_filt_disable(viv_s66), + .cac_v_data_out(viv_s81), + .out_h_end(viv_s74), + .out_v_end(viv_s75), + .out_val(viv_s72), + .out_ack(viv_s73)); + vsisp_isp_cac_delay u1_isp_cac_delay + ( + .clk(clk), + .reset_n(reset_n), + .cac_v_clk_en(viv_s71), + .mem_data_m2(viv_s57), + .mem_data_m3(viv_s58), + .mem_data_m4(viv_s59), + .mem_data_m5(viv_s60), + .mem_data_m6(viv_s61), + .dem_in_data_m2(viv_s76), + .dem_in_data_m3(viv_s77), + .dem_in_data_m4(viv_s78), + .dem_in_data_m5(viv_s79), + .dem_in_data_m6(viv_s80)); + vsisp_isp_cac_hor u_isp_cac_hor + ( + .clk(clk), + .reset_n(reset_n), + .soft_rst(soft_rst), + .in_val(viv_s72), + .in_ack(viv_s73), + .in_h_end(viv_s74), + .in_v_end(viv_s75), + .cac_v_data_out(viv_s81), + .red_sub(viv_s125), + .blue_sub(viv_s126), + .regs_dem_bypass(regs_dem_bypass), + .regs_bayer_pat(regs_bayer_pat), + .cac_h_red(viv_s68), + .cac_h_blue(viv_s69), + .cac_h_red_col(viv_s70), + .alom_stage1_en(viv_s107), + .alom_stage2_en(viv_s108), + .alom_stage3_en(viv_s109), + .alom_stage4_en(viv_s110), + .alom_stage5_en(viv_s111), + .alom_stage6_en(viv_s112), + .alom_stage7_en(viv_s113), + .alom_stage8_en(viv_s114), + .alom_stage0_val(viv_s115), + .alom_stage1_val(viv_s116), + .alom_stage2_val(viv_s117), + .alom_stage3_val(viv_s118), + .alom_stage4_val(viv_s119), + .alom_stage5_val(viv_s120), + .alom_stage6_val(viv_s121), + .proc_pattern_stg2(viv_s144), + .proc_pattern_stg3(viv_s145), + .out_cb(viv_s130), + .out_cr(viv_s129), + .out_h_end(viv_s148), + .out_v_end(viv_s149), + .out_val(viv_s146), + .out_ack(viv_s147)); + vsisp_isp_demosaic_buf_5lines u_isp_demosaic_buf_5lines + ( + .clk(clk), + .reset_n(reset_n), + .alom_stage0_val(viv_s115), + .alom_stage1_val(viv_s116), + .alom_stage2_val(viv_s117), + .alom_stage3_val(viv_s118), + .alom_stage4_val(viv_s119), + .in_data_t (viv_s76), + .in_data_m1(viv_s77), + .in_data_m2(viv_s78), + .in_data_m3(viv_s79), + .in_data_b (viv_s80), + .alom_stage1_en(viv_s107), + .alom_stage2_en(viv_s108), + .alom_stage3_en(viv_s109), + .alom_stage4_en(viv_s110), + .proc_pix_01(viv_s82), + .proc_pix_02(viv_s83), + .proc_pix_03(viv_s84), + .proc_pix_04(viv_s85), + .proc_pix_05(viv_s86), + .proc_pix_11(viv_s87), + .proc_pix_12(viv_s88), + .proc_pix_13(viv_s89), + .proc_pix_14(viv_s90), + .proc_pix_15(viv_s91), + .proc_pix_21(viv_s92), + .proc_pix_22(viv_s93), + .proc_pix_23(viv_s94), + .proc_pix_24(viv_s95), + .proc_pix_25(viv_s96), + .proc_pix_31(viv_s97), + .proc_pix_32(viv_s98), + .proc_pix_33(viv_s99), + .proc_pix_34(viv_s100), + .proc_pix_35(viv_s101), + .proc_pix_41(viv_s102), + .proc_pix_42(viv_s103), + .proc_pix_43(viv_s104), + .proc_pix_44(viv_s105), + .proc_pix_45(viv_s106)); + vsisp_isp_filt_txtdet u_isp_filt_txtdet + ( + .clk(clk), + .reset_n(reset_n), + .alom_dem_stage1_en(viv_s107), + .alom_dem_stage2_en(viv_s108), + .alom_dem_stage3_en(viv_s109), + .alom_dem_stage4_en(viv_s110), + .alom_dem_stage5_en(viv_s111), + .alom_dem_stage6_en(viv_s112), + .alom_dem_stage7_en(viv_s113), + .alom_dem_stage8_en(viv_s114), + .alom_stage1_val(viv_s116), + .alom_stage3_val(viv_s118), + .alom_stage4_val(viv_s119), + .pix_01(viv_s82[c_dw_si-1:c_dw_si-8]), + .pix_02(viv_s83[c_dw_si-1:c_dw_si-8]), + .pix_03(viv_s84[c_dw_si-1:c_dw_si-8]), + .pix_04(viv_s85), + .pix_05(viv_s86), + .pix_11(viv_s87[c_dw_si-1:c_dw_si-8]), + .pix_12(viv_s88[c_dw_si-1:c_dw_si-8]), + .pix_13(viv_s89[c_dw_si-1:c_dw_si-8]), + .pix_14(viv_s90), + .pix_15(viv_s91), + .pix_21(viv_s92[c_dw_si-1:c_dw_si-8]), + .pix_22(viv_s93[c_dw_si-1:c_dw_si-8]), + .pix_23(viv_s94[c_dw_si-1:c_dw_si-8]), + .pix_24(viv_s95), + .pix_25(viv_s96), + .pix_31(viv_s97[c_dw_si-1:c_dw_si-8]), + .pix_32(viv_s98[c_dw_si-1:c_dw_si-8]), + .pix_33(viv_s99[c_dw_si-1:c_dw_si-8]), + .pix_34(viv_s100), + .pix_35(viv_s101), + .pix_41(viv_s102[c_dw_si-1:c_dw_si-8]), + .pix_42(viv_s103[c_dw_si-1:c_dw_si-8]), + .pix_43(viv_s104[c_dw_si-1:c_dw_si-8]), + .pix_44(viv_s105), + .pix_45(viv_s106), + .proc_pattern_stg2(viv_s144), + .regs_demosaic_th(regs_demosaic_th), + .filt_thres_bl0(viv_s12), + .filt_thres_bl1(viv_s13), + .filt_thres_sh0(viv_s14), + .filt_thres_sh1(viv_s15), + .lum_weight_gain(viv_s16), + .lum_weight_kink(viv_s17), + .lum_weight_min(viv_s18), + .flag_h_1(viv_s138), + .flag_v_1(viv_s139), + .flag_h_2(viv_s140), + .flag_v_2(viv_s141), + .flag_h_3(viv_s142), + .flag_v_3(viv_s143), + .edge_dir(viv_s132), + .detail_level(viv_s131)); + vsisp_isp_demosaic5x u_isp_demosaic5x + ( + .clk(clk), + .reset_n(reset_n), + .alom_stage4_en(viv_s110), + .alom_stage5_en(viv_s111), + .regs_dem_bypass(regs_dem_bypass), + .cv_mask(viv_s136), + .proc_pix_01(viv_s82), + .proc_pix_02(viv_s83), + .proc_pix_03(viv_s84), + .proc_pix_11(viv_s87), + .proc_pix_12(viv_s88), + .proc_pix_13(viv_s89), + .proc_pix_21(viv_s92), + .proc_pix_22(viv_s93), + .proc_pix_23(viv_s94), + .proc_pix_31(viv_s97), + .proc_pix_32(viv_s98), + .proc_pix_33(viv_s99), + .proc_pix_41(viv_s102), + .proc_pix_42(viv_s103), + .proc_pix_43(viv_s104), + .proc_pattern_stg3(viv_s145), + .flag_h_1(viv_s138), + .flag_v_1(viv_s139), + .flag_h_2(viv_s140), + .flag_v_2(viv_s141), + .flag_h_3(viv_s142), + .flag_v_3(viv_s143), + .grn_line04(viv_s122), + .grn_line13(viv_s123), + .grn_line2(viv_s124), + .red_sub(viv_s125), + .blue_sub(viv_s126)); + assign viv_s173 = {viv_s131, + viv_s132, + viv_s163, + viv_s164, + viv_s127, + viv_s148, + viv_s149}; + assign {viv_s133, + viv_s134, + viv_s165, + viv_s166, + viv_s128, + viv_s152, + viv_s153} = viv_s174; + vsisp_isp_demosaic_dpsbe #(4*c_dw_si+13) u2_isp_demosaic_dpsbe + ( + .clk(clk), + .reset_n(reset_n), + .soft_rst(1'b0), + .in_data(viv_s173), + .in_val(viv_s146), + .in_ack(viv_s147), + .out_data(viv_s174), + .out_val(viv_s150), + .out_ack(viv_s151)); + vsisp_isp_filt_ctrl u_isp_filt_ctrl + ( + .clk(clk), + .reset_n(reset_n), + .flt_stage1_en(viv_s154), + .flt_stage2_en(viv_s155), + .flt_stage3_en(viv_s156), + .flt_stage1_val(viv_s160), + .flt_stage3_val(viv_s162), + .filt_enable(viv_s0), + .filt_chr_h_mode(viv_s1), + .filt_chr_v_mode(viv_s2), + .filt_mode(viv_s3), + .filt_fac_sh1(viv_s6), + .filt_fac_sh0(viv_s7), + .filt_fac_mid(viv_s8), + .filt_fac_bl0(viv_s9), + .filt_fac_bl1(viv_s10), + .detail_level(viv_s133), + .edge_dir(viv_s134), + .filt_fac_muxed(viv_s11), + .chr_h_bypass(viv_s135), + .cv_mask(viv_s136), + .ch_mask(viv_s137)); + vsisp_isp_filt_lp_core u_isp_filt_lp_core + ( + .clk(clk), + .reset_n(reset_n), + .alom_stage6_en(viv_s112), + .alom_stage7_en(viv_s113), + .alom_stage8_en(viv_s114), + .alom_stage5_val(viv_s120), + .alom_stage6_val(viv_s121), + .grn_line04(viv_s122), + .grn_line13(viv_s123), + .grn_line2(viv_s124), + .filt_lp_select(viv_s5), + .out_data13(viv_s163), + .out_data2(viv_s164)); + vsisp_isp_filt_hp_core u_isp_filt_hp_core + ( + .clk(clk), + .reset_n(reset_n), + .flt_stage1_en(viv_s154), + .flt_stage2_en(viv_s155), + .flt_stage3_en(viv_s156), + .flt_stage4_en(viv_s157), + .flt_stage5_en(viv_s158), + .flt_stage0_val(viv_s159), + .flt_stage1_val(viv_s160), + .flt_stage2_val(viv_s161), + .filt_fac_muxed(viv_s11), + .in_data13(viv_s165), + .in_data2(viv_s166), + .out_data(viv_s171)); + vsisp_isp_filt_chr_core u_isp_filt_chr_core + ( + .clk(clk), + .reset_n(reset_n), + .soft_rst(soft_rst), + .in_val(viv_s150), + .in_ack(viv_s175), + .in_h_end(viv_s152), + .in_v_end(viv_s153), + .crcb_v_filt(viv_s128), + .chr_h_bypass(viv_s135), + .ch_mask(viv_s137), + .flt_stage1_en(viv_s154), + .flt_stage2_en(viv_s155), + .flt_stage3_en(viv_s156), + .flt_stage4_en(viv_s157), + .flt_stage5_en(viv_s158), + .flt_stage0_val(viv_s159), + .flt_stage1_val(viv_s160), + .flt_stage2_val(viv_s161), + .flt_stage3_val(viv_s162), + .out_val(viv_s167), + .out_ack(viv_s168), + .out_h_end(viv_s169), + .out_v_end(viv_s170), + .out_data(viv_s172)); + vsisp_isp_filt_out_mux u_isp_filt_out_mux + ( + .clk(clk), + .reset_n(reset_n), + .soft_rst(soft_rst), + .filt_enable(viv_s0), + .hpfilt_in_ack(viv_s175), + .grn_line2(viv_s166[c_dw_si+1:2]), + .crcb_v_filt(viv_s128), + .in_h_end_dem(viv_s152), + .in_v_end_dem(viv_s153), + .in_val_dem(viv_s150), + .dem_out_ack(viv_s151), + .grn_filt(viv_s171), + .crcb_filt(viv_s172), + .hpfilt_h_end(viv_s169), + .hpfilt_v_end(viv_s170), + .hpfilt_val(viv_s167), + .hpfilt_ack(viv_s168), + .out_data(filt_data), + .out_h_end(filt_h_end), + .out_v_end(filt_v_end), + .out_val(filt_val), + .out_ack(filt_ack)); +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_filt_chr_buf.v b/ispyocto/rtl/ispyocto/vsisp_isp_filt_chr_buf.v new file mode 100644 index 0000000..0fb148e --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_isp_filt_chr_buf.v
@@ -0,0 +1,266 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_isp_filt_chr_buf + ( + clk, + reset_n, + soft_rst, + in_val, + in_ack, + in_h_end, + in_v_end, + in_data, + out_stage0, + out_stage1, + out_stage2, + out_stage3, + out_stage4, + out_stage5, + out_stage6, + flt_stage1_en, + flt_stage2_en, + flt_stage3_en, + flt_stage4_en, + flt_stage5_en, + flt_stage0_val, + flt_stage1_val, + flt_stage2_val, + flt_stage3_val, + out_h_end, + out_v_end, + out_val, + out_ack); + parameter c_dw_in = 10; + input clk; + input reset_n; + input soft_rst; + input in_val; + output in_ack; + input in_h_end; + input in_v_end; + input [c_dw_in-1:0] in_data; + output [c_dw_in-1:0] out_stage0; + output [c_dw_in-1:0] out_stage1; + output [c_dw_in-1:0] out_stage2; + output [c_dw_in-1:0] out_stage3; + output [c_dw_in-1:0] out_stage4; + output [c_dw_in-1:0] out_stage5; + output [c_dw_in-1:0] out_stage6; + output flt_stage1_en; + output flt_stage2_en; + output flt_stage3_en; + output flt_stage4_en; + output flt_stage5_en; + output flt_stage0_val; + output flt_stage1_val; + output flt_stage2_val; + output flt_stage3_val; + output out_h_end; + output out_v_end; + output out_val; + input out_ack; + parameter c_dw_buf = c_dw_in+2; + reg out_h_end; + reg out_v_end; + reg out_val; + reg [c_dw_in-1:0] out_stage0; + reg [c_dw_in-1:0] out_stage1; + reg [c_dw_in-1:0] out_stage2; + reg [c_dw_in-1:0] out_stage3; + reg [c_dw_in-1:0] out_stage4; + reg [c_dw_in-1:0] out_stage5; + reg [c_dw_in-1:0] out_stage6; + wire [c_dw_buf-1:0] viv_s0; + wire viv_s1; + reg viv_s2; + reg [c_dw_buf-1:0] viv_s3; + reg [c_dw_buf-1:0] viv_s4; + reg [c_dw_buf-1:0] viv_s5; + reg [c_dw_buf-1:0] viv_s6; + reg [c_dw_buf-1:0] viv_s7; + reg [c_dw_buf-1:0] viv_s8; + reg viv_s9; + reg viv_s10; + reg viv_s11; + reg viv_s12; + reg viv_s13; + reg viv_s14; + wire viv_s15; + wire viv_s16; + wire viv_s17; + wire viv_s18; + wire viv_s19; + wire viv_s20; + wire viv_s21; + wire viv_s22; + wire viv_s23; + wire viv_s24; + wire viv_s25; + wire viv_s26; + wire viv_s27; + wire viv_s28; + wire viv_s29; + wire viv_s30; + wire viv_s31; + wire viv_s32; + wire viv_s33; + wire viv_s34; + wire viv_s35; + wire viv_s36; + wire viv_s37; + wire viv_s38; + wire viv_s39; + wire viv_s40; + wire viv_s41; + wire viv_s42; + wire viv_s43; + wire viv_s44; + assign viv_s20 = (viv_s1 || viv_s35); + assign viv_s21 = viv_s20 && (viv_s9 || viv_s36); + assign viv_s22 = viv_s21 && (viv_s10 || viv_s37); + assign viv_s23 = viv_s22 && (viv_s11 || viv_s38); + assign viv_s25 = !viv_s9 || viv_s26 && viv_s20; + assign viv_s26 = !viv_s10 || viv_s27 && viv_s21; + assign viv_s27 = !viv_s11 || viv_s28 && viv_s22; + assign viv_s28 = !viv_s12 || viv_s31 && viv_s23; + assign viv_s29 = viv_s28; + assign viv_s30 = viv_s28; + assign viv_s31 = !out_val || out_ack; + assign viv_s32 = !viv_s12 || viv_s31; + assign viv_s33 = !viv_s11 || viv_s32; + assign viv_s34 = !viv_s10 || viv_s33; + assign in_ack = (!viv_s9 || viv_s34) && viv_s2; + assign viv_s24 = (!viv_s9 || viv_s34) && viv_s2 && viv_s1 ; + assign viv_s39 = viv_s6[c_dw_buf-2]; + assign viv_s35 = viv_s3[c_dw_buf-1]; + assign viv_s36 = viv_s4[c_dw_buf-1]; + assign viv_s37 = viv_s5[c_dw_buf-1]; + assign viv_s38 = viv_s6[c_dw_buf-1]; + assign viv_s1 = in_val && viv_s2; + assign viv_s0 = {in_h_end, in_v_end, in_data}; + assign viv_s40 = in_h_end && in_val && in_ack; + assign viv_s41 = viv_s38 && viv_s18 && viv_s31; + always @(posedge clk or negedge reset_n) begin + if (reset_n == 1'b0) begin + viv_s3 <= {c_dw_buf{1'b0}}; + viv_s4 <= {c_dw_buf{1'b0}}; + viv_s5 <= {c_dw_buf{1'b0}}; + viv_s6 <= {c_dw_buf{1'b0}}; + viv_s7 <= {c_dw_buf{1'b0}}; + viv_s8 <= {c_dw_buf{1'b0}}; + viv_s9 <= 1'b0; + viv_s10 <= 1'b0; + viv_s11 <= 1'b0; + viv_s12 <= 1'b0; + viv_s13 <= 1'b0; + viv_s14 <= 1'b0; + viv_s2 <= 1'b1; + end else begin + if (viv_s24) viv_s3 <= viv_s0; + if (viv_s26) viv_s4 <= viv_s3; + if (viv_s27) viv_s5 <= viv_s4; + if (viv_s28) viv_s6 <= viv_s5; + if (viv_s29) viv_s7 <= viv_s6; + if (viv_s30) viv_s8 <= viv_s7; + if (soft_rst) begin + viv_s9 <= 1'b0; + viv_s10 <= 1'b0; + viv_s11 <= 1'b0; + viv_s12 <= 1'b0; + viv_s13 <= 1'b0; + viv_s14 <= 1'b0; + viv_s2 <= 1'b1; + end else begin + if (viv_s25) viv_s9 <= viv_s1; + if (viv_s26) viv_s10 <= viv_s15; + if (viv_s27) viv_s11 <= viv_s16; + if (viv_s28) viv_s12 <= viv_s17; + if (viv_s29) viv_s13 <= viv_s18; + if (viv_s30) viv_s14 <= viv_s19; + if (viv_s40) viv_s2 <= 1'b0; + else if (viv_s41) viv_s2 <= 1'b1; + end + end + end + assign viv_s15 = viv_s9 && (viv_s1 || viv_s35); + assign viv_s16 = viv_s10 && (viv_s15 || viv_s36); + assign viv_s17 = viv_s11 && (viv_s16 || viv_s37); + assign viv_s18 = viv_s12 && (viv_s17 || viv_s38); + assign viv_s19 = viv_s13 && viv_s18; + always @(*) begin + if (viv_s1) out_stage0 = viv_s0[c_dw_in-1:0]; + else if (viv_s9) out_stage0 = viv_s3[c_dw_in-1:0]; + else if (viv_s10) out_stage0 = viv_s4[c_dw_in-1:0]; + else if (viv_s11) out_stage0 = viv_s5[c_dw_in-1:0]; + else out_stage0 = viv_s0[c_dw_in-1:0]; + if (viv_s9) out_stage1 = viv_s3[c_dw_in-1:0]; + else if (viv_s10) out_stage1 = viv_s4[c_dw_in-1:0]; + else if (viv_s11) out_stage1 = viv_s5[c_dw_in-1:0]; + else out_stage1 = viv_s3[c_dw_in-1:0]; + if (viv_s10) out_stage2 = viv_s4[c_dw_in-1:0]; + else if (viv_s11) out_stage2 = viv_s5[c_dw_in-1:0]; + else out_stage2 = viv_s4[c_dw_in-1:0]; + out_stage3 = viv_s5[c_dw_in-1:0]; + if (viv_s12) out_stage4 = viv_s6[c_dw_in-1:0]; + else if (viv_s11) out_stage4 = viv_s5[c_dw_in-1:0]; + else out_stage4 = viv_s6[c_dw_in-1:0]; + if (viv_s13) out_stage5 = viv_s7[c_dw_in-1:0]; + else if (viv_s12) out_stage5 = viv_s6[c_dw_in-1:0]; + else if (viv_s11) out_stage5 = viv_s5[c_dw_in-1:0]; + else out_stage5 = viv_s7[c_dw_in-1:0]; + if (viv_s14) out_stage6 = viv_s8[c_dw_in-1:0]; + else if (viv_s13) out_stage6 = viv_s7[c_dw_in-1:0]; + else if (viv_s12) out_stage6 = viv_s6[c_dw_in-1:0]; + else if (viv_s11) out_stage6 = viv_s5[c_dw_in-1:0]; + else out_stage6 = viv_s8[c_dw_in-1:0]; + end + assign viv_s42 = viv_s38 && viv_s18; + assign viv_s43 = viv_s39 && viv_s18; + assign viv_s44 = viv_s18; + assign flt_stage1_en = viv_s24; + assign flt_stage2_en = viv_s26; + assign flt_stage3_en = viv_s27; + assign flt_stage4_en = viv_s28; + assign flt_stage5_en = viv_s31; + assign flt_stage0_val = viv_s1; + assign flt_stage1_val = viv_s9; + assign flt_stage2_val = viv_s10; + assign flt_stage3_val = viv_s11; + always @(posedge clk or negedge reset_n) begin + if (reset_n == 1'b0) begin + out_h_end <= 0; + out_v_end <= 0; + out_val <= 0; + end else begin + if (viv_s31) begin + out_h_end <= viv_s42; + out_v_end <= viv_s43; + end + if (soft_rst) + out_val <= 1'b0; + else if (viv_s31) + out_val <= viv_s44; + end + end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_filt_chr_core.v b/ispyocto/rtl/ispyocto/vsisp_isp_filt_chr_core.v new file mode 100644 index 0000000..291870e --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_isp_filt_chr_core.v
@@ -0,0 +1,325 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_isp_filt_chr_core + ( + clk, + reset_n, + soft_rst, + in_val, + in_ack, + in_h_end, + in_v_end, + crcb_v_filt, + chr_h_bypass, + ch_mask, + flt_stage1_en, + flt_stage2_en, + flt_stage3_en, + flt_stage4_en, + flt_stage5_en, + flt_stage0_val, + flt_stage1_val, + flt_stage2_val, + flt_stage3_val, + out_val, + out_ack, + out_h_end, + out_v_end, + out_data + ); +`include "vsisp_isp.vh" + input clk; + input reset_n; + input soft_rst; + input in_val; + output in_ack; + input in_h_end; + input in_v_end; + input [2*c_dw_si+1:0] crcb_v_filt; + input chr_h_bypass; + input [1:0] ch_mask; + output flt_stage1_en; + output flt_stage2_en; + output flt_stage3_en; + output flt_stage4_en; + output flt_stage5_en; + output flt_stage0_val; + output flt_stage1_val; + output flt_stage2_val; + output flt_stage3_val; + output out_val; + input out_ack; + output out_h_end; + output out_v_end; + output [2*c_dw_si+1:0] out_data; + wire [2*c_dw_si+1:0] viv_s0; + wire [2*c_dw_si+1:0] viv_s1; + wire [2*c_dw_si+1:0] viv_s2; + wire [2*c_dw_si+1:0] viv_s3; + wire [2*c_dw_si+1:0] viv_s4; + wire [2*c_dw_si+1:0] viv_s5; + wire [2*c_dw_si+1:0] viv_s6; + wire [c_dw_si:0] viv_s7; + wire [c_dw_si:0] viv_s8; + wire [c_dw_si:0] viv_s9; + wire [c_dw_si:0] viv_s10; + wire [c_dw_si:0] viv_s11; + wire [c_dw_si:0] viv_s12; + wire [c_dw_si:0] viv_s13; + wire [c_dw_si:0] viv_s14; + wire [c_dw_si:0] viv_s15; + wire [c_dw_si:0] viv_s16; + wire [c_dw_si:0] viv_s17; + wire [c_dw_si:0] viv_s18; + wire [c_dw_si:0] viv_s19; + wire [c_dw_si:0] viv_s20; + wire flt_stage1_en; + wire flt_stage2_en; + wire flt_stage3_en; + wire flt_stage4_en; + wire flt_stage5_en; + wire flt_stage0_val; + wire flt_stage1_val; + wire flt_stage2_val; + wire flt_stage3_val; + wire viv_s21; + wire viv_s22; + wire viv_s23; + wire [c_dw_si+3:0] viv_s24; + wire [c_dw_si+3:0] viv_s25; + wire [c_dw_si+3:0] viv_s26; + wire [c_dw_si+4:0] viv_s27; + wire [c_dw_si+4:0] viv_s28; + wire [c_dw_si+2:0] viv_s29; + wire [c_dw_si+2:0] viv_s30; + wire [c_dw_si+2:0] viv_s31; + wire [c_dw_si+3:0] viv_s32; + wire [c_dw_si+3:0] viv_s33; + wire [c_dw_si+3:0] viv_s34; + wire [c_dw_si+3:0] viv_s35; + wire [c_dw_si+3:0] viv_s36; + wire [c_dw_si+4:0] viv_s37 ; + wire [c_dw_si+4:0] viv_s38; + wire [c_dw_si+4:0] viv_s39; + wire [c_dw_si+4:0] viv_s40; + wire [c_dw_si+4:0] viv_s41; + wire [c_dw_si+5:0] viv_s42; + wire [c_dw_si+5:0] viv_s43; + wire [c_dw_si+4:0] viv_s44; + wire [c_dw_si+4:0] viv_s45; + wire [c_dw_si+4:0] viv_s46; + wire [c_dw_si+5:0] viv_s47; + wire [c_dw_si+5:0] viv_s48; + wire [c_dw_si+5:0] viv_s49; + wire [c_dw_si+5:0] viv_s50; + wire [c_dw_si+5:0] viv_s51; + wire [c_dw_si+6:0] viv_s52; + wire [c_dw_si+6:0] viv_s53; + wire [c_dw_si+6:0] viv_s54; + wire [c_dw_si+6:0] viv_s55; + wire [c_dw_si+6:0] viv_s56; + wire [c_dw_si+7:0] viv_s57; + wire [c_dw_si+7:0] viv_s58; + wire [c_dw_si+8:0] viv_s59; + wire [c_dw_si:0] viv_s60; + wire [c_dw_si+3:0] viv_s61; + wire [c_dw_si+3:0] viv_s62; + wire [c_dw_si+3:0] viv_s63; + wire [c_dw_si+4:0] viv_s64; + wire [c_dw_si+4:0] viv_s65; + wire [c_dw_si+2:0] viv_s66; + wire [c_dw_si+2:0] viv_s67; + wire [c_dw_si+2:0] viv_s68; + wire [c_dw_si+3:0] viv_s69; + wire [c_dw_si+3:0] viv_s70; + wire [c_dw_si+3:0] viv_s71; + wire [c_dw_si+3:0] viv_s72; + wire [c_dw_si+3:0] viv_s73; + wire [c_dw_si+4:0] viv_s74 ; + wire [c_dw_si+4:0] viv_s75; + wire [c_dw_si+4:0] viv_s76; + wire [c_dw_si+4:0] viv_s77; + wire [c_dw_si+4:0] viv_s78; + wire [c_dw_si+5:0] viv_s79; + wire [c_dw_si+5:0] viv_s80; + wire [c_dw_si+4:0] viv_s81; + wire [c_dw_si+4:0] viv_s82; + wire [c_dw_si+4:0] viv_s83; + wire [c_dw_si+5:0] viv_s84; + wire [c_dw_si+5:0] viv_s85; + wire [c_dw_si+5:0] viv_s86; + wire [c_dw_si+5:0] viv_s87; + wire [c_dw_si+5:0] viv_s88; + wire [c_dw_si+6:0] viv_s89; + wire [c_dw_si+6:0] viv_s90; + wire [c_dw_si+6:0] viv_s91; + wire [c_dw_si+6:0] viv_s92; + wire [c_dw_si+6:0] viv_s93; + wire [c_dw_si+7:0] viv_s94; + wire [c_dw_si+7:0] viv_s95; + wire [c_dw_si+8:0] viv_s96; + wire [c_dw_si:0] viv_s97; + reg [2*c_dw_si+1:0] out_data; + reg [2*c_dw_si+1:0] viv_s98; + vsisp_isp_filt_chr_buf #(2*c_dw_si+2) u_isp_filt_chr_buf + ( + .clk(clk), + .reset_n(reset_n), + .soft_rst(soft_rst), + .in_val(in_val), + .in_ack(in_ack), + .in_h_end(in_h_end), + .in_v_end(in_v_end), + .in_data(crcb_v_filt), + .out_stage0(viv_s0), + .out_stage1(viv_s1), + .out_stage2(viv_s2), + .out_stage3(viv_s3), + .out_stage4(viv_s4), + .out_stage5(viv_s5), + .out_stage6(viv_s6), + .flt_stage1_en(flt_stage1_en), + .flt_stage2_en(flt_stage2_en), + .flt_stage3_en(flt_stage3_en), + .flt_stage4_en(flt_stage4_en), + .flt_stage5_en(flt_stage5_en), + .flt_stage0_val(flt_stage0_val), + .flt_stage1_val(flt_stage1_val), + .flt_stage2_val(flt_stage2_val), + .flt_stage3_val(flt_stage3_val), + .out_h_end(out_h_end), + .out_v_end(out_v_end), + .out_val(out_val), + .out_ack(out_ack)); + assign viv_s14 = viv_s0[2*c_dw_si+1:c_dw_si+1]; + assign viv_s15 = viv_s1[2*c_dw_si+1:c_dw_si+1]; + assign viv_s16 = viv_s2[2*c_dw_si+1:c_dw_si+1]; + assign viv_s17 = viv_s3[2*c_dw_si+1:c_dw_si+1]; + assign viv_s18 = viv_s4[2*c_dw_si+1:c_dw_si+1]; + assign viv_s19 = viv_s5[2*c_dw_si+1:c_dw_si+1]; + assign viv_s20 = viv_s6[2*c_dw_si+1:c_dw_si+1]; + assign viv_s7 = viv_s0[c_dw_si:0]; + assign viv_s8 = viv_s1[c_dw_si:0]; + assign viv_s9 = viv_s2[c_dw_si:0]; + assign viv_s10 = viv_s3[c_dw_si:0]; + assign viv_s11 = viv_s4[c_dw_si:0]; + assign viv_s12 = viv_s5[c_dw_si:0]; + assign viv_s13 = viv_s6[c_dw_si:0]; + assign viv_s21 = (ch_mask == 2'b00) ? 1'b1 : 1'b0; + assign viv_s22 = (ch_mask == 2'b01) ? 1'b1 : 1'b0; + assign viv_s23 = (ch_mask == 2'b10) ? 1'b1 : 1'b0; + assign viv_s24 = (viv_s23) ? {viv_s9, 3'b100} : {1'b0, viv_s7, 2'b10}; + assign viv_s25 = (viv_s23) ? {viv_s10, 3'b100} : {1'b0, viv_s10, 2'b10}; + assign viv_s26 = (viv_s23) ? {viv_s11, 3'b100} : {1'b0, viv_s13, 2'b10}; + assign viv_s29 = {viv_s8, 2'b10}; + assign viv_s30 = {viv_s9, 2'b10}; + assign viv_s31 = {viv_s11, 2'b10}; + assign viv_s34 = {1'b0, viv_s12, 2'b10}; + assign viv_s35 = viv_s32; + assign viv_s36 = viv_s33; + assign viv_s27 = {1'b0, viv_s24 ^ viv_s25 ^ viv_s26}; + assign viv_s28 = {(viv_s24 & viv_s25) | (viv_s24 & viv_s26) | (viv_s25 & viv_s26), 1'b0}; + assign viv_s32 = {1'b0, viv_s29 ^ viv_s30 ^ viv_s31}; + assign viv_s33 = {(viv_s29 & viv_s30) | (viv_s29 & viv_s31) | (viv_s30 & viv_s31), 1'b0}; + assign viv_s37 = {1'b0, viv_s34 ^ viv_s35 ^ viv_s36}; + assign viv_s38 = {(viv_s34 & viv_s35) | (viv_s34 & viv_s36) | (viv_s35 & viv_s36), 1'b0}; + assign viv_s39 = (viv_s22) ? {1'b0, viv_s10, 3'b100} : viv_s27; + assign viv_s40 = (viv_s22) ? {2'b0, viv_s10, 2'b10} : viv_s28; + assign viv_s41 = (viv_s22) ? {3'b0, viv_s9, 1'b1} : + (viv_s23) ? {c_dw_si+5{1'b0}} : {2'b0, viv_s37[c_dw_si+4:2]}; + assign viv_s44 = (viv_s22) ? {1'b0, viv_s9, 3'b100} : + (viv_s23) ? {2'b0, viv_s8, 2'b10} : viv_s37; + assign viv_s45 = (viv_s22) ? {1'b0, viv_s11, 3'b100} : + (viv_s23) ? {2'b0, viv_s12, 2'b10} : viv_s38; + assign viv_s46 = (viv_s22) ? {3'b00, viv_s11, 1'b1} : + (viv_s23) ? {c_dw_si+5{1'b0}} : {2'b0, viv_s38[c_dw_si+4:2]}; + assign viv_s42 = {1'b0, viv_s39 ^ viv_s40 ^ viv_s41}; + assign viv_s43 = {(viv_s39 & viv_s40) | (viv_s39 & viv_s41) | (viv_s40 & viv_s41), 1'b0}; + assign viv_s47 = {1'b0, viv_s44 ^ viv_s45 ^ viv_s46}; + assign viv_s48 = {(viv_s44 & viv_s45) | (viv_s44 & viv_s46) | (viv_s45 & viv_s46), 1'b0}; + assign viv_s49 = viv_s42; + assign viv_s50 = viv_s43; + assign viv_s51 = viv_s48; + assign viv_s52 = {1'b0, viv_s49 ^ viv_s50 ^ viv_s51}; + assign viv_s53 = {(viv_s49 & viv_s50) | (viv_s49 & viv_s51) | (viv_s50 & viv_s51), 1'b0}; + assign viv_s54 = (viv_s21) ? {3'b0, viv_s9, 3'b100} : viv_s53; + assign viv_s55 = (viv_s21) ? {2'b0, viv_s10, 4'b1000} : viv_s52; + assign viv_s56 = (viv_s21) ? {3'b0, viv_s11, 3'b100} : {1'b0,viv_s47}; + assign viv_s57 = {1'b0, viv_s54 ^ viv_s55 ^ viv_s56}; + assign viv_s58 = {(viv_s54 & viv_s55) | (viv_s54 & viv_s56) | (viv_s55 & viv_s56), 1'b0}; + assign viv_s59 = {1'b0,viv_s57} + viv_s58; + assign viv_s61 = (viv_s23) ? {viv_s16, 3'b100} : {1'b0, viv_s14, 2'b10}; + assign viv_s62 = (viv_s23) ? {viv_s17, 3'b100} : {1'b0, viv_s17, 2'b10}; + assign viv_s63 = (viv_s23) ? {viv_s18, 3'b100} : {1'b0, viv_s20, 2'b10}; + assign viv_s66 = {viv_s15, 2'b10}; + assign viv_s67 = {viv_s16, 2'b10}; + assign viv_s68 = {viv_s18, 2'b10}; + assign viv_s71 = {1'b0, viv_s19, 2'b10}; + assign viv_s72 = viv_s69; + assign viv_s73 = viv_s70; + assign viv_s64 = {1'b0, viv_s61 ^ viv_s62 ^ viv_s63}; + assign viv_s65 = {(viv_s61 & viv_s62) | (viv_s61 & viv_s63) | (viv_s62 & viv_s63), 1'b0}; + assign viv_s69 = {1'b0, viv_s66 ^ viv_s67 ^ viv_s68}; + assign viv_s70 = {(viv_s66 & viv_s67) | (viv_s66 & viv_s68) | (viv_s67 & viv_s68), 1'b0}; + assign viv_s74 = {1'b0, viv_s71 ^ viv_s72 ^ viv_s73}; + assign viv_s75 = {(viv_s71 & viv_s72) | (viv_s71 & viv_s73) | (viv_s72 & viv_s73), 1'b0}; + assign viv_s76 = (viv_s22) ? {1'b0, viv_s17, 3'b100} : viv_s64; + assign viv_s77 = (viv_s22) ? {2'b0, viv_s17, 2'b10} : viv_s65; + assign viv_s78 = (viv_s22) ? {3'b0, viv_s16, 1'b1} : + (viv_s23) ? {c_dw_si+5{1'b0}} : {2'b0, viv_s74[c_dw_si+4:2]}; + assign viv_s81 = (viv_s22) ? {1'b0, viv_s16, 3'b100} : + (viv_s23) ? {2'b0, viv_s15, 2'b10} : viv_s74; + assign viv_s82 = (viv_s22) ? {1'b0, viv_s18, 3'b100} : + (viv_s23) ? {2'b0, viv_s19, 2'b10} : viv_s75; + assign viv_s83 = (viv_s22) ? {3'b00, viv_s18, 1'b1} : + (viv_s23) ? {c_dw_si+5{1'b0}} : {2'b0, viv_s75[c_dw_si+4:2]}; + assign viv_s79 = {1'b0, viv_s76 ^ viv_s77 ^ viv_s78}; + assign viv_s80 = {(viv_s76 & viv_s77) | (viv_s76 & viv_s78) | (viv_s77 & viv_s78), 1'b0}; + assign viv_s84 = {1'b0, viv_s81 ^ viv_s82 ^ viv_s83}; + assign viv_s85 = {(viv_s81 & viv_s82) | (viv_s81 & viv_s83) | (viv_s82 & viv_s83), 1'b0}; + assign viv_s86 = viv_s79; + assign viv_s87 = viv_s80; + assign viv_s88 = viv_s85; + assign viv_s89 = {1'b0, viv_s86 ^ viv_s87 ^ viv_s88}; + assign viv_s90 = {(viv_s86 & viv_s87) | (viv_s86 & viv_s88) | (viv_s87 & viv_s88), 1'b0}; + assign viv_s91 = (viv_s21) ? {3'b0, viv_s16, 3'b100} : viv_s90; + assign viv_s92 = (viv_s21) ? {2'b0, viv_s17, 4'b1000} : viv_s89; + assign viv_s93 = (viv_s21) ? {3'b0, viv_s18, 3'b100} : {1'b0,viv_s84}; + assign viv_s94 = {1'b0, viv_s91 ^ viv_s92 ^ viv_s93}; + assign viv_s95 = {(viv_s91 & viv_s92) | (viv_s91 & viv_s93) | (viv_s92 & viv_s93), 1'b0}; + assign viv_s96 = {1'b0,viv_s94} + viv_s95; + assign viv_s60 = chr_h_bypass ? {~(viv_s10[c_dw_si]),viv_s10[c_dw_si-1:0]}: + {~(viv_s59[c_dw_si+5]),viv_s59[c_dw_si+4:5]}; + assign viv_s97 = chr_h_bypass ? {~(viv_s17[c_dw_si]),viv_s17[c_dw_si-1:0]}: + {~(viv_s96[c_dw_si+5]),viv_s96[c_dw_si+4:5]}; + always @(posedge clk or negedge reset_n) begin + if (reset_n == 1'b0) begin + viv_s98 <= {2*c_dw_si+2{1'b0}}; + out_data <= {2*c_dw_si+2{1'b0}}; + end else begin + if (flt_stage4_en) viv_s98 <= {viv_s97, viv_s60}; + if (flt_stage5_en) out_data <= viv_s98; + end + end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_filt_ctrl.v b/ispyocto/rtl/ispyocto/vsisp_isp_filt_ctrl.v new file mode 100644 index 0000000..db3e64b --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_isp_filt_ctrl.v
@@ -0,0 +1,168 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_isp_filt_ctrl + ( + clk, + reset_n, + flt_stage1_en, + flt_stage2_en, + flt_stage3_en, + flt_stage1_val, + flt_stage3_val, + filt_enable, + filt_chr_h_mode, + filt_chr_v_mode, + filt_mode, + filt_fac_sh1, + filt_fac_sh0, + filt_fac_mid, + filt_fac_bl0, + filt_fac_bl1, + detail_level, + edge_dir, + filt_fac_muxed, + chr_h_bypass, + cv_mask, + ch_mask); +`include "vsisp_isp.vh" + input clk; + input reset_n; + input flt_stage1_en; + input flt_stage2_en; + input flt_stage3_en; + input flt_stage1_val; + input flt_stage3_val; + input filt_enable; + input [1:0] filt_chr_h_mode; + input [1:0] filt_chr_v_mode; + input filt_mode; + input [5:0] filt_fac_sh1; + input [5:0] filt_fac_sh0; + input [5:0] filt_fac_mid; + input [5:0] filt_fac_bl0; + input [5:0] filt_fac_bl1; + input [2:0] detail_level; + input edge_dir; + output [5:0] filt_fac_muxed; + output chr_h_bypass; + output [1:0] cv_mask; + output [1:0] ch_mask; + reg [3:0] viv_s0; + reg [3:0] viv_s1; + reg [1:0] viv_s2; + reg viv_s3; + reg chr_h_bypass; + reg [5:0] viv_s4; + reg [5:0] filt_fac_muxed; + reg [1:0] cv_mask; + reg [1:0] ch_mask; + wire [2:0] viv_s5; + wire viv_s6; + wire viv_s7; + reg viv_s8; + wire viv_s9; + wire viv_s10; + wire viv_s11; + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + viv_s0 <= 4'b0; + viv_s1 <= 4'b0; + viv_s8 <= 1'b0; + end else begin + if (flt_stage1_en) viv_s0 <= {detail_level, edge_dir}; + if (flt_stage2_en) viv_s1 <= viv_s0; + if (flt_stage3_en) viv_s8 <= viv_s1[0]; + end + end + assign {viv_s5, viv_s6} = viv_s1; + assign viv_s7 = flt_stage1_val ? viv_s0[0] : viv_s6; + assign viv_s9 = flt_stage3_val ? viv_s8 : viv_s6; + always @(*) begin + if (~filt_mode) begin + viv_s4 = filt_fac_mid; + end else begin + case(viv_s5) + 3'b000 : viv_s4 = filt_fac_bl1; + 3'b001 : viv_s4 = filt_fac_bl0; + 3'b010 : viv_s4 = filt_fac_mid; + 3'b011 : viv_s4 = filt_fac_sh0; + default : viv_s4 = filt_fac_sh1; + endcase + end + end + assign viv_s11 = ~viv_s7 & ~viv_s6 & ~viv_s9; + assign viv_s10 = viv_s7 & viv_s6 & viv_s9; + always @(*) begin + if (filt_chr_h_mode == 2'b00) begin + viv_s3 = 1'b1; + viv_s2 = 2'b00; + end else if (filt_chr_h_mode == 2'b01) begin + viv_s2 = 2'b01; + viv_s3 = 1'b0; + end else if (filt_chr_h_mode == 2'b10) begin + viv_s3 = 1'b0; + case(viv_s5) + 3'b000 : begin + viv_s2 = 2'b11; + end + 3'b001 : begin + viv_s2 = 2'b10; + end + default : begin + if (viv_s11) viv_s2 = 2'b00; + else if (viv_s10) viv_s2 = 2'b10; + else viv_s2 = 2'b01; + end + endcase + end else begin + viv_s3 = 1'b0; + case(viv_s5) + 3'b000 : begin + viv_s2 = 2'b11; + end + 3'b001 : begin + viv_s2 = 2'b11; + end + default : begin + if (viv_s11) viv_s2 = 2'b00; + else if (viv_s10) viv_s2 = 2'b11; + else viv_s2 = 2'b10; + end + endcase + end + end + always @(posedge clk or negedge reset_n) begin + if (reset_n == 1'b0) begin + filt_fac_muxed <= {6'b0}; + chr_h_bypass <= {1'b0}; + ch_mask <= {2'b0}; + cv_mask <= {2'b0}; + end else begin + if (flt_stage3_en) filt_fac_muxed <= viv_s4; + if (flt_stage3_en) chr_h_bypass <= viv_s3; + if (flt_stage3_en) ch_mask <= viv_s2; + cv_mask <= (filt_enable) ? filt_chr_v_mode : {2'b0}; + end + end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_filt_hp_core.v b/ispyocto/rtl/ispyocto/vsisp_isp_filt_hp_core.v new file mode 100644 index 0000000..6ec7052 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_isp_filt_hp_core.v
@@ -0,0 +1,132 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_isp_filt_hp_core + ( + clk, + reset_n, + flt_stage1_en, + flt_stage2_en, + flt_stage3_en, + flt_stage4_en, + flt_stage5_en, + flt_stage0_val, + flt_stage1_val, + flt_stage2_val, + filt_fac_muxed, + in_data13, + in_data2, + out_data + ); +`include "vsisp_isp.vh" + input clk; + input reset_n; + input flt_stage1_en; + input flt_stage2_en; + input flt_stage3_en; + input flt_stage4_en; + input flt_stage5_en; + input flt_stage0_val; + input flt_stage1_val; + input flt_stage2_val; + input [5:0] filt_fac_muxed; + input [c_dw_si+2:0] in_data13; + input [c_dw_si+1:0] in_data2; + output [c_dw_si+1:0] out_data; + parameter c_dw_buf = 2*(c_dw_si+2)+1; + wire [c_dw_buf-1:0] viv_s0; + reg [c_dw_buf-1:0] viv_s1; + reg [c_dw_buf-1:0] viv_s2; + reg [c_dw_buf-1:0] viv_s3; + reg [c_dw_buf-1:0] viv_s4; + reg [c_dw_buf-1:0] viv_s5; + wire [c_dw_si+2:0] viv_s6; + wire [c_dw_si+2:0] viv_s7; + wire [c_dw_si+2:0] viv_s8; + wire [c_dw_si+1:0] viv_s9; + wire [c_dw_si+1:0] viv_s10; + wire [c_dw_si+1:0] viv_s11; + wire [c_dw_si+3:0] viv_s12; + wire [c_dw_si+7:0] viv_s13; + wire [c_dw_si+1:0] viv_s14; + reg [c_dw_si+1:0] viv_s15; + reg [c_dw_si+1:0] viv_s16; + reg signed [c_dw_si+2:0] viv_s17; + reg [c_dw_si+1:0] viv_s18; + reg [c_dw_si+1:0] out_data; + wire [c_dw_si+1:0] viv_s19; + wire signed [c_dw_si+2:0] viv_s20; + wire signed [c_dw_si+8:0] viv_s21; + wire [c_dw_si+6:0] viv_s22; + assign viv_s0 = {in_data13,in_data2}; + always @(posedge clk or negedge reset_n) begin + if (reset_n == 1'b0) begin + viv_s1 <= {c_dw_buf{1'b0}}; + viv_s2 <= {c_dw_buf{1'b0}}; + end else begin + if (flt_stage1_en) viv_s1 <= viv_s0; + if (flt_stage2_en) viv_s2 <= viv_s1; + end + end + always @(*) begin + if (flt_stage0_val) viv_s3 = viv_s0; + else if (flt_stage1_val) viv_s3 = viv_s1; + else viv_s3 = viv_s0; + viv_s4 = viv_s1; + if (flt_stage2_val) viv_s5 = viv_s2; + else if (flt_stage1_val) viv_s5 = viv_s1; + else viv_s5 = viv_s2; + end + assign viv_s6 = viv_s3[c_dw_buf-1:c_dw_si+2]; + assign viv_s7 = viv_s4[c_dw_buf-1:c_dw_si+2]; + assign viv_s8 = viv_s5[c_dw_buf-1:c_dw_si+2]; + assign viv_s9 = viv_s3[c_dw_si+1:0]; + assign viv_s10 = viv_s4[c_dw_si+1:0]; + assign viv_s11 = viv_s5[c_dw_si+1:0]; + assign viv_s12 = {1'b0, viv_s6} + viv_s8; + assign viv_s13 = {viv_s9 , 3'h7} + {viv_s10 , 3'h7} + + {viv_s11 , 3'h7} + {viv_s7, 3'h7} + + {viv_s12 , 2'h3} + {3'b0, viv_s12 , 1'b1}; + assign viv_s19 = viv_s13[c_dw_si+7:6]; + assign viv_s20 = $signed({1'b0, viv_s11}) - $signed({1'b0, viv_s15}); + assign viv_s21 = viv_s17 * $signed({1'b0, filt_fac_muxed}); + assign viv_s22 = viv_s21[c_dw_si+8:2] + viv_s16 + {1'b1, {c_dw_si{1'b0}} , 2'b10}; + assign viv_s14 = viv_s22[c_dw_si+6] ? {c_dw_si+2{1'b0}} : + (|viv_s22[c_dw_si+5:c_dw_si+4]) ? {c_dw_si+2{1'b1}} : + viv_s22[c_dw_si+3:2]; + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + viv_s15 <= {c_dw_si+2{1'b0}}; + viv_s16 <= {c_dw_si+2{1'b0}}; + viv_s17 <= {c_dw_si+3{1'b0}}; + viv_s18 <= {c_dw_si+2{1'b0}}; + out_data <= {c_dw_si+2{1'b0}}; + end else begin + if (flt_stage2_en) viv_s15 <= viv_s19; + if (flt_stage3_en) viv_s16 <= viv_s15; + if (flt_stage3_en) viv_s17 <= viv_s20; + if (flt_stage4_en) viv_s18 <= viv_s14; + if (flt_stage5_en) out_data <= viv_s18; + end + end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_filt_lp_core.v b/ispyocto/rtl/ispyocto/vsisp_isp_filt_lp_core.v new file mode 100644 index 0000000..da42a0c --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_isp_filt_lp_core.v
@@ -0,0 +1,291 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_isp_filt_lp_core + ( + clk, + reset_n, + alom_stage6_en, + alom_stage7_en, + alom_stage8_en, + alom_stage5_val, + alom_stage6_val, + grn_line04, + grn_line13, + grn_line2, + filt_lp_select, + out_data13, + out_data2 + ); +`include "vsisp_isp.vh" + input clk; + input reset_n; + input alom_stage6_en; + input alom_stage7_en; + input alom_stage8_en; + input alom_stage5_val; + input alom_stage6_val; + input [c_dw_si :0] grn_line04; + input [c_dw_si :0] grn_line13; + input [c_dw_si-1:0] grn_line2; + input [3:0] filt_lp_select; + output [c_dw_si+2:0] out_data13; + output [c_dw_si+1:0] out_data2; + parameter c_dw_buf = (3*c_dw_si)+2; + wire viv_s0; + wire viv_s1; + wire viv_s2; + wire viv_s3; + wire viv_s4; + reg viv_s5; + reg [3:0] viv_s6; + reg [c_dw_buf-1:0] viv_s7; + reg [c_dw_buf-1:0] viv_s8; + reg [c_dw_buf-1:0] viv_s9; + reg [c_dw_buf-1:0] viv_s10; + reg [c_dw_buf-1:0] viv_s11; + wire [c_dw_buf-1:0] viv_s12; + wire [c_dw_si:0] viv_s13; + wire [c_dw_si:0] viv_s14; + wire [c_dw_si:0] viv_s15; + wire [c_dw_si:0] viv_s16; + wire [c_dw_si:0] viv_s17; + wire [c_dw_si:0] viv_s18; + wire [c_dw_si-1:0] viv_s19; + wire [c_dw_si-1:0] viv_s20; + wire [c_dw_si-1:0] viv_s21; + wire [c_dw_si :0] viv_s22; + wire [c_dw_si+2:0] viv_s23; + wire [c_dw_si+2:0] viv_s24; + wire [c_dw_si-1:0] viv_s25; + wire [c_dw_si+1:0] viv_s26; + wire [c_dw_si+1:0] viv_s27; + wire [c_dw_si :0] viv_s28; + reg [c_dw_si+5:0] viv_s29; + reg [c_dw_si+3:0] viv_s30; + reg [c_dw_si+5:0] viv_s31; + reg [c_dw_si+3:0] viv_s32; + reg [c_dw_si+4:0] viv_s33; + reg [c_dw_si+3:0] viv_s34; + reg [c_dw_si+4:0] viv_s35; + reg [c_dw_si+2:0] viv_s36; + reg [c_dw_si+4:0] viv_s37; + reg [c_dw_si+2:0] viv_s38; + reg [c_dw_si+3:0] viv_s39; + reg [c_dw_si+2:0] viv_s40; + wire [c_dw_si+6:0] viv_s41; + wire [c_dw_si+5:0] viv_s42; + wire [c_dw_si+2:0] viv_s43; + wire [c_dw_si+1:0] viv_s44; + reg [c_dw_si+2:0] viv_s45; + reg [c_dw_si+1:0] viv_s46; + reg [c_dw_si+2:0] out_data13; + reg [c_dw_si+1:0] out_data2; + assign viv_s12 = {grn_line04, grn_line13, grn_line2}; + assign viv_s0 = alom_stage6_en; + assign viv_s1 = alom_stage7_en; + assign viv_s2 = alom_stage8_en; + assign viv_s3 = alom_stage5_val; + assign viv_s4 = alom_stage6_val; + always @(posedge clk or negedge reset_n) begin + if (reset_n == 1'b0) begin + viv_s7 <= {c_dw_buf{1'b0}}; + viv_s8 <= {c_dw_buf{1'b0}}; + viv_s6 <= 4'b0; + viv_s5 <= 1'b0; + end else begin + if (viv_s0) viv_s6 <= filt_lp_select; + if (viv_s0) viv_s7 <= viv_s12; + if (viv_s0) viv_s8 <= viv_s7; + if (viv_s0) viv_s5 <= viv_s4; + end + end + always @(*) begin + if (viv_s3) viv_s9 = viv_s12; + else if (viv_s4) viv_s9 = viv_s7; + else viv_s9 = viv_s12; + viv_s10 = viv_s7; + if (viv_s5) viv_s11 = viv_s8; + else if (viv_s4) viv_s11 = viv_s7; + else viv_s11 = viv_s8; + end + assign viv_s13 = viv_s9[3*c_dw_si+1:2*c_dw_si+1]; + assign viv_s14 = viv_s10[3*c_dw_si+1:2*c_dw_si+1]; + assign viv_s15 = viv_s11[3*c_dw_si+1:2*c_dw_si+1]; + assign viv_s16 = viv_s9[2*c_dw_si:c_dw_si]; + assign viv_s17 = viv_s10[2*c_dw_si:c_dw_si]; + assign viv_s18 = viv_s11[2*c_dw_si:c_dw_si]; + assign viv_s19 = viv_s9[c_dw_si-1:0]; + assign viv_s20 = viv_s10[c_dw_si-1:0]; + assign viv_s21 = viv_s11[c_dw_si-1:0]; + assign viv_s24 = {2'b0, viv_s14} + {viv_s20, 1'b0} + viv_s26; + assign viv_s23 = {2'b0, viv_s13} + viv_s15 + {viv_s28, 1'b0}; + assign viv_s22 = viv_s17; + assign viv_s28 = {1'b0, viv_s19} + viv_s21; + assign viv_s27 = {1'b0, viv_s17} + viv_s28; + assign viv_s26 = {1'b0, viv_s16} + viv_s18; + assign viv_s25 = viv_s20; + always @(*) begin + case(viv_s6[2:0]) + 3'b000 : viv_s29 = { viv_s24, 3'b0}; + 3'b001 : viv_s29 = { viv_s24, 3'b0}; + 3'b010 : viv_s29 = { viv_s24, 3'b0}; + 3'b111 : viv_s29 = {2'b0, viv_s24, 1'b0}; + default : viv_s29 = {1'b0, viv_s24, 2'b0}; + endcase + end + always @(*) begin + case(viv_s6[2:0]) + 3'b011 : viv_s30 = { viv_s24, 1'b0}; + 3'b100 : viv_s30 = { viv_s24, 1'b0}; + 3'b101 : viv_s30 = {1'b0, viv_s24 }; + 3'b111 : viv_s30 = {1'b0, viv_s24 }; + default : viv_s30 = 0; + endcase + end + always @(*) begin + case(viv_s6[2:0]) + 3'b000 : viv_s31 = {2'b0, viv_s22, 3'b0}; + 3'b001 : viv_s31 = {2'b0, viv_s22, 3'b0}; + 3'b010 : viv_s31 = {1'b0, viv_s22, 4'b0}; + 3'b011 : viv_s31 = {1'b0, viv_s22, 4'b0}; + 3'b100 : viv_s31 = {1'b0, viv_s22, 4'b0}; + default : viv_s31 = { viv_s22, 5'b0}; + endcase + end + always @(*) begin + case(viv_s6[2:0]) + 3'b000 : viv_s32 = 0; + 3'b001 : viv_s32 = {1'b0, viv_s22, 2'b0}; + 3'b010 : viv_s32 = 0; + 3'b011 : viv_s32 = {1'b0, viv_s22, 2'b0}; + 3'b100 : viv_s32 = { viv_s22, 3'b0}; + 3'b101 : viv_s32 = 0; + 3'b110 : viv_s32 = {1'b0, viv_s22, 2'b0}; + default : viv_s32 = { viv_s22, 3'b0}; + endcase + end + always @(*) begin + case(viv_s6[2:0]) + 3'b101 : viv_s33 = {1'b0, viv_s23, 1'b0}; + 3'b110 : viv_s33 = {1'b0, viv_s23, 1'b0}; + 3'b111 : viv_s33 = {2'b0, viv_s22, 2'b0}; + default : viv_s33 = { viv_s23, 2'b0}; + endcase + end + always @(*) begin + case(viv_s6[2:0]) + 3'b000 : viv_s34 = { viv_s23, 1'b0}; + 3'b001 : viv_s34 = {1'b0, viv_s23 }; + 3'b010 : viv_s34 = 0; + 3'b011 : viv_s34 = {1'b0, viv_s23 }; + 3'b100 : viv_s34 = 0; + 3'b101 : viv_s34 = {1'b0, viv_s23 }; + 3'b110 : viv_s34 = {1'b0, viv_s23 }; + default : viv_s34 = { viv_s23, 1'b0}; + endcase + end + always @(*) begin + case(viv_s6[2:0]) + 3'b000 : viv_s35 = { viv_s27, 3'b0}; + 3'b001 : viv_s35 = { viv_s27, 3'b0}; + 3'b010 : viv_s35 = { viv_s27, 3'b0}; + 3'b111 : viv_s35 = {2'b0, viv_s27, 1'b0}; + default : viv_s35 = {1'b0, viv_s27, 2'b0}; + endcase + end + always @(*) begin + case(viv_s6[2:0]) + 3'b011 : viv_s36 = { viv_s27, 1'b0}; + 3'b100 : viv_s36 = { viv_s27, 1'b0}; + 3'b101 : viv_s36 = {1'b0, viv_s27 }; + 3'b111 : viv_s36 = {1'b0, viv_s27 }; + default : viv_s36 = 0; + endcase + end + always @(*) begin + case(viv_s6[2:0]) + 3'b000 : viv_s37 = {2'b0, viv_s25, 3'b0}; + 3'b001 : viv_s37 = {2'b0, viv_s25, 3'b0}; + 3'b010 : viv_s37 = {1'b0, viv_s25, 4'b0}; + 3'b011 : viv_s37 = {1'b0, viv_s25, 4'b0}; + 3'b100 : viv_s37 = {1'b0, viv_s25, 4'b0}; + default : viv_s37 = { viv_s25, 5'b0}; + endcase + end + always @(*) begin + case(viv_s6[2:0]) + 3'b000 : viv_s38 = 0; + 3'b001 : viv_s38 = {1'b0, viv_s25, 2'b0}; + 3'b010 : viv_s38 = 0; + 3'b011 : viv_s38 = {1'b0, viv_s25, 2'b0}; + 3'b100 : viv_s38 = { viv_s25, 3'b0}; + 3'b101 : viv_s38 = 0; + 3'b110 : viv_s38 = {1'b0, viv_s25, 2'b0}; + default : viv_s38 = { viv_s25, 3'b0}; + endcase + end + always @(*) begin + case(viv_s6[2:0]) + 3'b101 : viv_s39 = {1'b0, viv_s26, 1'b0}; + 3'b110 : viv_s39 = {1'b0, viv_s26, 1'b0}; + 3'b111 : viv_s39 = {2'b0, viv_s25, 2'b0}; + default : viv_s39 = { viv_s26, 2'b0}; + endcase + end + always @(*) begin + case(viv_s6[2:0]) + 3'b000 : viv_s40 = { viv_s26, 1'b0}; + 3'b001 : viv_s40 = {1'b0, viv_s26 }; + 3'b010 : viv_s40 = 0; + 3'b011 : viv_s40 = {1'b0, viv_s26 }; + 3'b100 : viv_s40 = 0; + 3'b101 : viv_s40 = {1'b0, viv_s26 }; + 3'b110 : viv_s40 = {1'b0, viv_s26 }; + default : viv_s40 = { viv_s26, 1'b0}; + endcase + end + assign viv_s41 = {1'b0, viv_s29} + viv_s30 + viv_s31 + viv_s32 + viv_s33 + viv_s34; + assign viv_s42 = {1'b0, viv_s35} + viv_s36 + viv_s37 + viv_s38 + viv_s39 + viv_s40; + assign viv_s43 = viv_s6[3] ? {viv_s22, 2'b0} : + viv_s41[c_dw_si+6:4]; + assign viv_s44 = viv_s6[3] ? {viv_s25, 2'b0} : + viv_s42[c_dw_si+5:4]; + always @(posedge clk or negedge reset_n) begin + if (reset_n == 1'b0) begin + viv_s45 <= {c_dw_si+3{1'b0}}; + viv_s46 <= {c_dw_si+2{1'b0}}; + out_data13 <= {c_dw_si+3{1'b0}}; + out_data2 <= {c_dw_si+2{1'b0}}; + end else begin + if (viv_s1) begin + viv_s45 <= viv_s43; + viv_s46 <= viv_s44; + end + if (viv_s2) begin + out_data13 <= viv_s45; + out_data2 <= viv_s46; + end + end + end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_filt_out_mux.v b/ispyocto/rtl/ispyocto/vsisp_isp_filt_out_mux.v new file mode 100644 index 0000000..7b4c7ce --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_isp_filt_out_mux.v
@@ -0,0 +1,165 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_isp_filt_out_mux + ( + clk, + reset_n, + soft_rst, + filt_enable, + hpfilt_in_ack, + grn_line2, + crcb_v_filt, + in_h_end_dem, + in_v_end_dem, + in_val_dem, + dem_out_ack, + grn_filt, + crcb_filt, + hpfilt_h_end, + hpfilt_v_end, + hpfilt_val, + hpfilt_ack, + out_data, + out_h_end, + out_v_end, + out_val, + out_ack); +`include "vsisp_isp.vh" + input clk; + input reset_n; + input soft_rst; + input filt_enable; + input hpfilt_in_ack; + input [c_dw_si-1:0] grn_line2; + input [(2*c_dw_si)+1:0] crcb_v_filt; + input in_h_end_dem; + input in_v_end_dem; + input in_val_dem; + output dem_out_ack; + input [c_dw_si+1:0] grn_filt; + input [(2*c_dw_si)+1:0] crcb_filt; + input hpfilt_h_end; + input hpfilt_v_end; + input hpfilt_val; + output hpfilt_ack; + output [(3*c_dw_si)-1:0] out_data; + output out_h_end; + output out_v_end; + output out_val; + input out_ack; + wire viv_s0; + wire viv_s1; + wire viv_s2; + wire [c_dw_si:0] viv_s3; + wire [c_dw_si:0] viv_s4; + wire [c_dw_si+2:0] viv_s5; + wire [c_dw_si+3:0] viv_s6; + wire [c_dw_si+3:0] viv_s7; + wire [c_dw_si-1:0] viv_s8; + wire [c_dw_si-1:0] viv_s9; + wire [c_dw_si-1:0] viv_s10; + wire [(3*c_dw_si)-1:0] viv_s11; + reg viv_s12; + reg viv_s13; + reg viv_s14; + reg viv_s15; + reg [3*c_dw_si-1:0] viv_s16; + wire viv_s17; + wire viv_s18; + wire viv_s19; + wire [3*c_dw_si-1:0] viv_s20; + wire viv_s21; + reg [(3*c_dw_si)-1:0] out_data; + reg out_h_end; + reg out_v_end; + reg out_val; + assign viv_s4 = (filt_enable) ? crcb_filt[c_dw_si:0] : + {~crcb_v_filt[c_dw_si], crcb_v_filt[c_dw_si-1:0]}; + assign viv_s3 = (filt_enable) ? crcb_filt[(2*c_dw_si)+1 : c_dw_si+1] : + {~crcb_v_filt[(2*c_dw_si)+1], crcb_v_filt[2*c_dw_si: c_dw_si+1]}; + assign viv_s5 = (filt_enable) ? {1'b0, grn_filt} - {1'b1, {c_dw_si{1'b0}}} : + {3'b0, grn_line2}; + assign viv_s0 = (filt_enable) ? hpfilt_h_end : in_h_end_dem; + assign viv_s1 = (filt_enable) ? hpfilt_v_end : in_v_end_dem; + assign viv_s2 = (filt_enable) ? hpfilt_val : in_val_dem; + assign dem_out_ack = (filt_enable) ? hpfilt_in_ack : viv_s12; + assign hpfilt_ack = viv_s12; + assign viv_s6 = {viv_s3[c_dw_si], viv_s3[c_dw_si], viv_s3[c_dw_si], viv_s3} + + {viv_s5[c_dw_si+2], viv_s5}; + assign viv_s7 = {viv_s4[c_dw_si], viv_s4[c_dw_si], viv_s4[c_dw_si], viv_s4} + + {viv_s5[c_dw_si+2], viv_s5}; + assign viv_s8 = ( viv_s6[c_dw_si+3]) ? {c_dw_si{1'b0}} : + (|viv_s6[c_dw_si+2:c_dw_si]) ? {c_dw_si{1'b1}} : + viv_s6[c_dw_si-1:0]; + assign viv_s10 = ( viv_s7[c_dw_si+3]) ? {c_dw_si{1'b0}} : + (|viv_s7[c_dw_si+2:c_dw_si]) ? {c_dw_si{1'b1}} : + viv_s7[c_dw_si-1:0]; + assign viv_s9 = ( viv_s5[c_dw_si+2]) ? {c_dw_si{1'b0}} : + (|viv_s5[c_dw_si+1:c_dw_si]) ? {c_dw_si{1'b1}} : + viv_s5[c_dw_si-1:0]; + assign viv_s11 = {viv_s8, viv_s9, viv_s10}; + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + viv_s16 <= {(3*c_dw_si){1'b0}}; + viv_s14 <= 1'b0; + viv_s15 <= 1'b0; + viv_s12 <= 1'b0; + viv_s13 <= 1'b0; + end else begin + if (viv_s12) viv_s16 <= viv_s11; + if (viv_s12) viv_s14 <= viv_s0; + if (viv_s12) viv_s15 <= viv_s1; + if (soft_rst) begin + viv_s12 <= 1'b0; + viv_s13 <= 1'b0; + end else begin + viv_s12 <= ~viv_s17 | viv_s21; + if (viv_s12) viv_s13 <= viv_s2; + end + end + end + assign viv_s18 = viv_s12 ? viv_s0 : viv_s14; + assign viv_s19 = viv_s12 ? viv_s1 : viv_s15; + assign viv_s20 = viv_s12 ? viv_s11 : viv_s16; + assign viv_s17 = viv_s12 ? viv_s2 : viv_s13; + assign viv_s21 = ~out_val | out_ack; + always @(posedge clk or negedge reset_n) begin + if (reset_n == 1'b0) begin + out_data <= {(3*c_dw_si){1'b0}}; + out_h_end <= 0; + out_v_end <= 0; + out_val <= 0; + end else begin + if (viv_s21) begin + out_data <= viv_s20; + out_h_end <= viv_s18; + out_v_end <= viv_s19; + end + if (soft_rst) + out_val <= 1'b0; + else if (viv_s21) + out_val <= viv_s17; + end + end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_filt_regs.v b/ispyocto/rtl/ispyocto/vsisp_isp_filt_regs.v new file mode 100644 index 0000000..92f9042 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_isp_filt_regs.v
@@ -0,0 +1,292 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_isp_filt_regs + ( + clk_cfg, + reset_cfg_n, + cfg_val, + cfg_addr, + cfg_rd, + cfg_wdata, + cfg_rdata, + filt_enable, + filt_lp_select, + filt_chr_h_mode, + filt_chr_v_mode, + filt_mode, + filt_fac_sh1, + filt_fac_sh0, + filt_fac_mid, + filt_fac_bl0, + filt_fac_bl1, + filt_thres_bl0, + filt_thres_bl1, + filt_thres_sh0, + filt_thres_sh1, + lum_weight_gain, + lum_weight_kink, + lum_weight_min, + cac_enable, + cac_h_clip_mode, + cac_v_clip_mode, + cac_h_count_start, + cac_v_count_start, + cac_x_norm_factor, + cac_y_norm_factor, + cac_x_norm_shift, + cac_y_norm_shift, + cac_a_red, + cac_b_red, + cac_c_red, + cac_a_blue, + cac_b_blue, + cac_c_blue); +`include "vsisp_isp.vh" + parameter c_fa = c_cfg_filt-1 ; + input clk_cfg; + input reset_cfg_n; + input cfg_val; + input [c_fa:2] cfg_addr; + input cfg_rd; + input [31:0] cfg_wdata; + output [31:0] cfg_rdata; + output filt_enable; + output [3:0] filt_lp_select; + output [1:0] filt_chr_h_mode; + output [1:0] filt_chr_v_mode; + output filt_mode; + output [5:0] filt_fac_sh1; + output [5:0] filt_fac_sh0; + output [5:0] filt_fac_mid; + output [5:0] filt_fac_bl0; + output [5:0] filt_fac_bl1; + output [9:0] filt_thres_bl0; + output [9:0] filt_thres_bl1; + output [9:0] filt_thres_sh0; + output [9:0] filt_thres_sh1; + output [2:0] lum_weight_gain; + output [7:0] lum_weight_kink; + output [7:0] lum_weight_min; + output cac_enable; + output cac_h_clip_mode; + output [1:0] cac_v_clip_mode; + output [12:0] cac_h_count_start; + output [12:0] cac_v_count_start; + output [4:0] cac_x_norm_factor; + output [4:0] cac_y_norm_factor; + output [3:0] cac_x_norm_shift; + output [3:0] cac_y_norm_shift; + output [8:0] cac_a_red; + output [8:0] cac_b_red; + output [8:0] cac_c_red; + output [8:0] cac_a_blue; + output [8:0] cac_b_blue; + output [8:0] cac_c_blue; + reg filt_enable; + reg [3:0] filt_lp_select; + reg [1:0] filt_chr_h_mode; + reg [1:0] filt_chr_v_mode; + reg filt_mode; + reg [5:0] filt_fac_sh1; + reg [5:0] filt_fac_sh0; + reg [5:0] filt_fac_mid; + reg [5:0] filt_fac_bl0; + reg [5:0] filt_fac_bl1; + reg [9:0] filt_thres_bl0; + reg [9:0] filt_thres_bl1; + reg [9:0] filt_thres_sh0; + reg [9:0] filt_thres_sh1; + reg [2:0] lum_weight_gain; + reg [7:0] lum_weight_kink; + reg [7:0] lum_weight_min; + reg cac_enable; + reg cac_h_clip_mode; + reg [1:0] cac_v_clip_mode; + reg [12:0] cac_h_count_start; + reg [12:0] cac_v_count_start; + reg [4:0] cac_x_norm_factor; + reg [4:0] cac_y_norm_factor; + reg [3:0] cac_x_norm_shift; + reg [3:0] cac_y_norm_shift; + reg [8:0] cac_a_red; + reg [8:0] cac_b_red; + reg [8:0] cac_c_red; + reg [8:0] cac_a_blue; + reg [8:0] cac_b_blue; + reg [8:0] cac_c_blue; + reg [31:0] cfg_rdata; + always @(*) begin + if (cfg_val) begin + case (cfg_addr) + c_filt_mode[c_fa:2]: cfg_rdata = {20'b0, + filt_lp_select, + filt_chr_h_mode, + filt_chr_v_mode, + 2'b0, + filt_mode, + filt_enable}; + c_filt_fac_sh1[c_fa:2]: cfg_rdata = {26'b0, filt_fac_sh1}; + c_filt_fac_sh0[c_fa:2]: cfg_rdata = {26'b0, filt_fac_sh0}; + c_filt_fac_mid[c_fa:2]: cfg_rdata = {26'b0, filt_fac_mid}; + c_filt_fac_bl0[c_fa:2]: cfg_rdata = {26'b0, filt_fac_bl0}; + c_filt_fac_bl1[c_fa:2]: cfg_rdata = {26'b0, filt_fac_bl1}; + c_filt_thres_bl0[c_fa:2]: cfg_rdata = {22'b0, filt_thres_bl0}; + c_filt_thres_bl1[c_fa:2]: cfg_rdata = {22'b0, filt_thres_bl1}; + c_filt_thres_sh0[c_fa:2]: cfg_rdata = {22'b0, filt_thres_sh0}; + c_filt_thres_sh1[c_fa:2]: cfg_rdata = {22'b0, filt_thres_sh1}; + c_filt_lum_weigt[c_fa:2]: cfg_rdata = {13'b0, lum_weight_gain, + lum_weight_kink, + lum_weight_min}; + c_cac_ctrl[c_fa:2]: cfg_rdata = {28'b0, cac_h_clip_mode, + cac_v_clip_mode, + cac_enable}; + c_cac_count_start[c_fa:2]: cfg_rdata = {3'b0, cac_v_count_start, + 3'b0, cac_h_count_start}; + c_cac_a[c_fa:2]: cfg_rdata = {7'b0, cac_a_blue, + 7'b0, cac_a_red}; + c_cac_b[c_fa:2]: cfg_rdata = {7'b0, cac_b_blue, + 7'b0, cac_b_red}; + c_cac_c[c_fa:2]: cfg_rdata = {7'b0, cac_c_blue, + 7'b0, cac_c_red}; + c_cac_x_norm[c_fa:2]: cfg_rdata = {12'h0, cac_x_norm_shift, + 11'h0, cac_x_norm_factor}; + c_cac_y_norm[c_fa:2]: cfg_rdata = {12'h0, cac_y_norm_shift, + 11'h0, cac_y_norm_factor}; + default: cfg_rdata = 32'h0; + endcase + end else begin + cfg_rdata = 32'h0; + end + end + always @(posedge clk_cfg or negedge reset_cfg_n) begin + if (~reset_cfg_n) begin + filt_lp_select <= 4'b0100; + filt_chr_h_mode <= 2'b11; + filt_chr_v_mode <= 2'b11; + filt_mode <= 1'b1; + filt_enable <= 1'b0; + filt_fac_sh1 <= 6'h10; + filt_fac_sh0 <= 6'h0C; + filt_fac_mid <= 6'h0A; + filt_fac_bl0 <= 6'h06; + filt_fac_bl1 <= 6'h02; + filt_thres_sh1 <= 10'h02C; + filt_thres_sh0 <= 10'h01A; + filt_thres_bl0 <= 10'h00D; + filt_thres_bl1 <= 10'h005; + lum_weight_gain <= 3'h2; + lum_weight_kink <= 8'h20; + lum_weight_min <= 8'h40; + cac_enable <= 1'b0; + cac_h_clip_mode <= 1'b0; + cac_v_clip_mode <= 2'b0; + cac_h_count_start <= 13'h1000; + cac_v_count_start <= 13'h1000; + cac_x_norm_factor <= 5'h10; + cac_y_norm_factor <= 5'h10; + cac_x_norm_shift <= 4'h8; + cac_y_norm_shift <= 4'h8; + cac_a_red <= 9'h0; + cac_b_red <= 9'h0; + cac_c_red <= 9'h0; + cac_a_blue <= 9'h0; + cac_b_blue <= 9'h0; + cac_c_blue <= 9'h0; + end else begin + if (cfg_val && ~cfg_rd) begin + case (cfg_addr) + c_filt_mode[c_fa:2]: begin + filt_lp_select <= cfg_wdata[11:8]; + filt_chr_h_mode <= cfg_wdata[7:6]; + filt_chr_v_mode <= cfg_wdata[5:4]; + filt_mode <= cfg_wdata[1]; + filt_enable <= cfg_wdata[0]; + end + c_filt_thres_bl0[c_fa:2]: begin + filt_thres_bl0 <= cfg_wdata[9:0]; + end + c_filt_thres_bl1[c_fa:2]: begin + filt_thres_bl1 <= cfg_wdata[9:0]; + end + c_filt_thres_sh0[c_fa:2]: begin + filt_thres_sh0 <= cfg_wdata[9:0]; + end + c_filt_thres_sh1[c_fa:2]: begin + filt_thres_sh1 <= cfg_wdata[9:0]; + end + c_filt_lum_weigt[c_fa:2]: begin + lum_weight_gain <= cfg_wdata[18:16]; + lum_weight_kink <= cfg_wdata[15:8]; + lum_weight_min <= cfg_wdata[7:0]; + end + c_filt_fac_sh1[c_fa:2]: begin + filt_fac_sh1 <= cfg_wdata[5:0]; + end + c_filt_fac_sh0[c_fa:2]: begin + filt_fac_sh0 <= cfg_wdata[5:0]; + end + c_filt_fac_mid[c_fa:2]: begin + filt_fac_mid <= cfg_wdata[5:0]; + end + c_filt_fac_bl0[c_fa:2]: begin + filt_fac_bl0 <= cfg_wdata[5:0]; + end + c_filt_fac_bl1[c_fa:2]: begin + filt_fac_bl1 <= cfg_wdata[5:0]; + end + c_cac_ctrl[c_fa:2]: begin + cac_h_clip_mode <= cfg_wdata[3]; + cac_v_clip_mode <= cfg_wdata[2:1]; + cac_enable <= cfg_wdata[0]; + end + c_cac_count_start[c_fa:2]: begin + cac_v_count_start <= cfg_wdata[28:16]; + cac_h_count_start <= cfg_wdata[12:0]; + end + c_cac_a[c_fa:2]: begin + cac_a_blue <= cfg_wdata[24:16]; + cac_a_red <= cfg_wdata[8:0]; + end + c_cac_b[c_fa:2]: begin + cac_b_blue <= cfg_wdata[24:16]; + cac_b_red <= cfg_wdata[8:0]; + end + c_cac_c[c_fa:2]: begin + cac_c_blue <= cfg_wdata[24:16]; + cac_c_red <= cfg_wdata[8:0]; + end + c_cac_x_norm[c_fa:2]: begin + cac_x_norm_shift <= cfg_wdata[19:16]; + cac_x_norm_factor <= cfg_wdata[4:0]; + end + c_cac_y_norm[c_fa:2]: begin + cac_y_norm_shift <= cfg_wdata[19:16]; + cac_y_norm_factor <= cfg_wdata[4:0]; + end + default: begin end + endcase + end + end + end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_filt_txtdet.v b/ispyocto/rtl/ispyocto/vsisp_isp_filt_txtdet.v new file mode 100644 index 0000000..0c5be38 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_isp_filt_txtdet.v
@@ -0,0 +1,578 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_isp_filt_txtdet + ( + clk, + reset_n, + alom_dem_stage1_en, + alom_dem_stage2_en, + alom_dem_stage3_en, + alom_dem_stage4_en, + alom_dem_stage5_en, + alom_dem_stage6_en, + alom_dem_stage7_en, + alom_dem_stage8_en, + alom_stage1_val, + alom_stage3_val, + alom_stage4_val, + pix_01, + pix_02, + pix_03, + pix_04, + pix_05, + pix_11, + pix_12, + pix_13, + pix_14, + pix_15, + pix_21, + pix_22, + pix_23, + pix_24, + pix_25, + pix_31, + pix_32, + pix_33, + pix_34, + pix_35, + pix_41, + pix_42, + pix_43, + pix_44, + pix_45, + proc_pattern_stg2, + regs_demosaic_th, + filt_thres_bl0, + filt_thres_bl1, + filt_thres_sh0, + filt_thres_sh1, + lum_weight_gain, + lum_weight_kink, + lum_weight_min, + flag_h_1, + flag_v_1, + flag_h_2, + flag_v_2, + flag_h_3, + flag_v_3, + edge_dir, + detail_level); +`include "vsisp_isp.vh" + input clk; + input reset_n; + input alom_dem_stage1_en; + input alom_dem_stage2_en; + input alom_dem_stage3_en; + input alom_dem_stage4_en; + input alom_dem_stage5_en; + input alom_dem_stage6_en; + input alom_dem_stage7_en; + input alom_dem_stage8_en; + input alom_stage1_val; + input alom_stage3_val; + input alom_stage4_val; + input [7:0] pix_01; + input [7:0] pix_02; + input [7:0] pix_03; + input [7:0] pix_04; + input [7:0] pix_05; + input [7:0] pix_11; + input [7:0] pix_12; + input [7:0] pix_13; + input [7:0] pix_14; + input [7:0] pix_15; + input [7:0] pix_21; + input [7:0] pix_22; + input [7:0] pix_23; + input [7:0] pix_24; + input [7:0] pix_25; + input [7:0] pix_31; + input [7:0] pix_32; + input [7:0] pix_33; + input [7:0] pix_34; + input [7:0] pix_35; + input [7:0] pix_41; + input [7:0] pix_42; + input [7:0] pix_43; + input [7:0] pix_44; + input [7:0] pix_45; + input [1:0] proc_pattern_stg2; + input [7:0] regs_demosaic_th; + input [9:0] filt_thres_bl0; + input [9:0] filt_thres_bl1; + input [9:0] filt_thres_sh0; + input [9:0] filt_thres_sh1; + input [2:0] lum_weight_gain; + input [7:0] lum_weight_kink; + input [7:0] lum_weight_min; + output flag_h_1; + output flag_v_1; + output flag_h_2; + output flag_v_2; + output flag_h_3; + output flag_v_3; + output edge_dir; + output [2:0] detail_level; + reg [7:0] viv_s0; + reg [7:0] viv_s1; + reg [7:0] viv_s2; + reg [7:0] viv_s3; + reg [7:0] viv_s4; + reg [7:0] viv_s5; + reg [7:0] viv_s6; + reg [7:0] viv_s7; + reg [7:0] viv_s8; + reg [7:0] viv_s9; + wire [10:0] viv_s10; + wire [10:0] viv_s11; + wire viv_s12; + wire viv_s13; + reg flag_h_1; + reg flag_v_1; + reg [7:0] viv_s14; + reg [7:0] viv_s15; + reg [7:0] viv_s16; + reg [7:0] viv_s17; + reg [7:0] viv_s18; + reg [7:0] viv_s19; + reg [7:0] viv_s20; + reg [7:0] viv_s21; + reg [7:0] viv_s22; + reg [7:0] viv_s23; + reg [7:0] viv_s24; + reg [7:0] viv_s25; + reg [7:0] viv_s26; + reg [7:0] viv_s27; + reg [7:0] viv_s28; + reg [7:0] viv_s29; + reg [7:0] viv_s30; + reg [7:0] viv_s31; + reg [7:0] viv_s32; + reg [7:0] viv_s33; + wire [7:0] viv_s34; + wire [7:0] viv_s35; + wire [7:0] viv_s36; + wire [7:0] viv_s37; + wire [7:0] viv_s38; + wire [7:0] viv_s39; + wire [7:0] viv_s40; + wire [7:0] viv_s41; + wire [7:0] viv_s42; + wire [7:0] viv_s43; + reg [7:0] viv_s44; + reg [7:0] viv_s45; + reg [7:0] viv_s46; + reg [7:0] viv_s47; + reg [7:0] viv_s48; + reg [7:0] viv_s49; + reg [7:0] viv_s50; + reg [7:0] viv_s51; + reg [7:0] viv_s52; + reg [7:0] viv_s53; + wire [10:0] viv_s54; + wire [10:0] viv_s55; + wire viv_s56; + wire viv_s57; + reg flag_h_2; + reg flag_v_2; + reg [7:0] viv_s58; + reg [7:0] viv_s59; + reg [7:0] viv_s60; + reg [7:0] viv_s61; + reg [7:0] viv_s62; + reg [7:0] viv_s63; + reg [7:0] viv_s64; + reg [7:0] viv_s65; + reg [7:0] viv_s66; + reg [7:0] viv_s67; + wire [10:0] viv_s68; + wire [10:0] viv_s69; + wire viv_s70; + wire viv_s71; + reg flag_h_3; + reg flag_v_3; + wire [9:0] viv_s72; + reg [9:0] viv_s73; + reg [9:0] viv_s74; + reg [9:0] viv_s75; + wire [9:0] viv_s76; + wire [9:0] viv_s77; + reg [9:0] viv_s78; + wire [9:0] viv_s79; + wire [9:0] viv_s80; + wire [9:0] viv_s81; + wire [9:0] viv_s82; + wire [9:0] viv_s83; + wire [9:0] viv_s84; + wire [9:0] viv_s85; + reg [7:0] viv_s86; + reg [7:0] viv_s87; + reg [7:0] viv_s88; + reg [7:0] viv_s89; + wire [8:0] viv_s90; + wire [7:0] viv_s91; + reg [9:0] viv_s92; + wire [9:0] viv_s93; + reg [10:0] viv_s94; + wire [8:0] viv_s95; + reg [7:0] viv_s96; + wire [11:0] viv_s97; + reg [11:0] viv_s98; + reg [11:0] viv_s99; + reg [11:0] viv_s100; + wire [18:0] viv_s101; + reg [10:0] viv_s102; + wire [11:0] viv_s103; + wire [11:0] viv_s104; + wire [11:0] viv_s105; + wire [11:0] viv_s106; + reg [11:0] viv_s107; + reg [11:0] viv_s108; + reg [11:0] viv_s109; + reg [11:0] viv_s110; + reg [11:0] viv_s111; + reg [11:0] viv_s112; + reg viv_s113; + reg viv_s114; + reg viv_s115; + reg edge_dir; + reg [2:0] detail_level; + always @(*) begin + if ((proc_pattern_stg2 == c_r) || (proc_pattern_stg2 == c_b)) begin + viv_s14 = pix_11; + viv_s15 = pix_13; + viv_s16 = pix_22; + viv_s17 = pix_31; + viv_s18 = pix_33; + viv_s19 = pix_13; + viv_s20 = pix_15; + viv_s21 = pix_24; + viv_s22 = pix_33; + viv_s23 = pix_35; + viv_s24 = pix_02; + viv_s25 = pix_22; + viv_s26 = pix_13; + viv_s27 = pix_04; + viv_s28 = pix_24; + viv_s29 = pix_22; + viv_s30 = pix_42; + viv_s31 = pix_33; + viv_s32 = pix_24; + viv_s33 = pix_44; + end else begin + viv_s14 = pix_23; + viv_s15 = pix_21; + viv_s16 = pix_12; + viv_s17 = pix_32; + viv_s18 = 0; + viv_s19 = pix_25; + viv_s20 = pix_23; + viv_s21 = pix_14; + viv_s22 = pix_34; + viv_s23 = 0; + viv_s24 = pix_12; + viv_s25 = pix_03; + viv_s26 = pix_23; + viv_s27 = pix_14; + viv_s28 = 0; + viv_s29 = pix_32; + viv_s30 = pix_23; + viv_s31 = pix_43; + viv_s32 = pix_34; + viv_s33 = 0; + end + end + assign viv_s34 = f_abs_dif(viv_s14, viv_s19); + assign viv_s35 = f_abs_dif(viv_s15, viv_s20); + assign viv_s36 = f_abs_dif(viv_s16, viv_s21); + assign viv_s37 = f_abs_dif(viv_s17, viv_s22); + assign viv_s38 = f_abs_dif(viv_s18, viv_s23); + assign viv_s39 = f_abs_dif(viv_s24, viv_s29); + assign viv_s40 = f_abs_dif(viv_s25, viv_s30); + assign viv_s41 = f_abs_dif(viv_s26, viv_s31); + assign viv_s42 = f_abs_dif(viv_s27, viv_s32); + assign viv_s43 = f_abs_dif(viv_s28, viv_s33); + always @(*) begin + if ((proc_pattern_stg2 == c_r) || (proc_pattern_stg2 == c_b)) begin + viv_s0 = viv_s34 >> 1; + viv_s1 = viv_s35 >> 1; + viv_s2 = viv_s36; + viv_s3 = f_abs_dif(pix_02, pix_04); + viv_s4 = 0; + viv_s5 = 0; + viv_s6 = viv_s39; + viv_s7 = viv_s41; + viv_s8 = viv_s42; + viv_s9 = 0; + viv_s44 = viv_s34 >> 1; + viv_s45 = viv_s35 >> 1; + viv_s46 = viv_s36; + viv_s47 = viv_s37 >> 1; + viv_s48 = viv_s38 >> 1; + viv_s49 = viv_s39 >> 1; + viv_s50 = viv_s40 >> 1; + viv_s51 = viv_s41; + viv_s52 = viv_s42 >> 1; + viv_s53 = viv_s43 >> 1; + viv_s58 = viv_s36; + viv_s59 = viv_s37 >> 1; + viv_s60 = viv_s38 >> 1; + viv_s61 = f_abs_dif(pix_42, pix_44); + viv_s62 = 0; + viv_s63 = 0; + viv_s64 = viv_s40; + viv_s65 = viv_s41; + viv_s66 = viv_s43; + viv_s67 = 0; + end else begin + viv_s0 = viv_s34 >> 1; + viv_s1 = viv_s35 >> 1; + viv_s2 = viv_s36; + viv_s3 = f_abs_dif(pix_01, pix_03) >> 1; + viv_s4 = f_abs_dif(pix_03, pix_05) >> 1; + viv_s5 = 0; + viv_s6 = viv_s39; + viv_s7 = viv_s40; + viv_s8 = viv_s42; + viv_s9 = 0; + viv_s44 = viv_s34 >> 1; + viv_s45 = viv_s35 >> 1; + viv_s46 = viv_s36; + viv_s47 = viv_s37; + viv_s48 = viv_s38; + viv_s49 = viv_s39; + viv_s50 = viv_s40 >> 1; + viv_s51 = viv_s41 >> 1; + viv_s52 = viv_s42; + viv_s53 = 0; + viv_s58 = viv_s35 >> 1; + viv_s59 = viv_s34 >> 1; + viv_s60 = viv_s37; + viv_s61 = f_abs_dif(pix_41, pix_43) >> 1; + viv_s62 = f_abs_dif(pix_43, pix_45) >> 1; + viv_s63 = 0; + viv_s64 = viv_s39; + viv_s65 = viv_s41; + viv_s66 = viv_s42; + viv_s67 = 0; + end + end + assign viv_s11 = {3'b0, viv_s5} + viv_s6 + viv_s7 + viv_s8 + viv_s9; + assign viv_s55 = {3'b0, viv_s49} + viv_s50 + viv_s51 + viv_s52 + viv_s53; + assign viv_s69 = {3'b0, viv_s63} + viv_s64 + viv_s65 + viv_s66 + viv_s67; + assign viv_s10 = {3'b0, viv_s0} + viv_s1 + viv_s2 + viv_s3 + viv_s4; + assign viv_s54 = {3'b0, viv_s44} + viv_s45 + viv_s46 + viv_s47 + viv_s48; + assign viv_s68 = {3'b0, viv_s58} + viv_s59 + viv_s60 + viv_s61 + viv_s62; + assign {viv_s13, viv_s12} = f_compare(viv_s11, regs_demosaic_th, viv_s10); + assign {viv_s57, viv_s56} = f_compare(viv_s55, regs_demosaic_th, viv_s54); + assign {viv_s71, viv_s70} = f_compare(viv_s69, regs_demosaic_th, viv_s68); + function [7:0] f_abs_dif; + input [7:0] a, + b; + reg [8:0] viv_s116; + begin + viv_s116 = a - b; + f_abs_dif = viv_s116[8] ? + ~viv_s116[7:0] : + viv_s116[7:0]; + end + endfunction + function [1:0] f_compare; + input [10:0] a; + input [7:0] b; + input [10:0] c; + reg [11:0] viv_s117; + reg [11:0] viv_s118; + reg [11:0] viv_s119; + reg [11:0] viv_s120; + reg [12:0] viv_s121; + reg [12:0] viv_s122; + reg [12:0] viv_s123; + reg [12:0] viv_s124; + reg viv_s125; + begin + viv_s125 = ~(&b); + viv_s117 = {2'b0, a[9:0]}; + viv_s118 = {3'b0, b,1'b1}; + viv_s119 = {2'b0, c[9:0]}; + viv_s120 = ~(viv_s117 ^ viv_s118 ^ viv_s119); + viv_s121 = {( viv_s117 & viv_s118)|( viv_s117 & ~viv_s119)|(viv_s118 & ~viv_s119), 1'b0}; + viv_s122 = {(~viv_s117 & viv_s118)|(~viv_s117 & viv_s119)|(viv_s118 & viv_s119), 1'b0}; + viv_s123 = viv_s120 + viv_s121; + viv_s124 = viv_s120 + viv_s122; + f_compare = {(viv_s123[11] & viv_s125), (viv_s124[11] & viv_s125)}; + end + endfunction + function [10:0] f_abs_hv; + input [11:0] a; + reg [11:0] viv_s116; + begin + viv_s116 = a; + f_abs_hv = viv_s116[11] ? + ~viv_s116[10:0] : + viv_s116[10:0]; + end + endfunction + assign viv_s80 ={3'b0, pix_05[7:1]} + pix_15 + pix_25 + pix_35 + pix_45[7:1]; + always @(posedge clk or negedge reset_n) begin + if (reset_n == 1'b0) begin + viv_s75 <= 10'b0; + viv_s78 <= 10'b0; + viv_s74 <= 10'b0; + viv_s73 <= 10'b0; + end else begin + if (alom_dem_stage1_en) viv_s75 <= viv_s80; + if (alom_dem_stage2_en) viv_s78 <= viv_s75; + if (alom_dem_stage3_en) viv_s74 <= viv_s78; + if (alom_dem_stage4_en) viv_s73 <= viv_s74; + end + end + assign viv_s79 = alom_stage1_val ? viv_s75 : viv_s74; + assign viv_s77 = alom_stage3_val ? viv_s74 : viv_s75; + assign viv_s76 = alom_stage4_val ? viv_s73 : viv_s78; + assign viv_s81 = {3'b0, pix_01[7:1]} + pix_02 + pix_03 + pix_04 + pix_05[7:1]; + assign viv_s82 = {3'b0, pix_11[7:1]} + pix_12 + pix_13 + pix_14 + pix_15[7:1]; + assign viv_s83 = {3'b0, pix_21[7:1]} + pix_22 + pix_23 + pix_24 + pix_25[7:1]; + assign viv_s84 = {3'b0, pix_31[7:1]} + pix_32 + pix_33 + pix_34 + pix_35[7:1]; + assign viv_s85 = {3'b0, pix_41[7:1]} + pix_42 + pix_43 + pix_44 + pix_45[7:1]; + assign viv_s104 = (({2'b0, viv_s76} + viv_s77) - viv_s78) - viv_s79; + assign viv_s106 = (({2'b0, viv_s77} + viv_s78) - viv_s79) - viv_s80; + assign viv_s103 = (({2'b0, viv_s81} + viv_s82) - viv_s83) - viv_s84; + assign viv_s105 = (({2'b0, viv_s82} + viv_s83) - viv_s84) - viv_s85; + assign viv_s72 = {3'b0, viv_s76[9:3]} + viv_s77[9:2] + viv_s78[9:2] + viv_s79[9:2] + viv_s80[9:3]; + assign viv_s90 = {1'b0, viv_s89} - lum_weight_kink; + always @(*) begin + case(lum_weight_gain) + 3'h0 : viv_s92 = {10'b0}; + 3'h1 : viv_s92 = {10'b0}; + 3'h2 : viv_s92 = {1'b0,viv_s90[7:0],1'b0}; + 3'h3 : viv_s92 = {10'b0}; + 3'h4 : viv_s92 = {1'b0,viv_s90[7:0],1'b0}; + 3'h5 : viv_s92 = {10'b0}; + default: viv_s92 = {1'b0,viv_s90[7:0],1'b0}; + endcase + end + assign viv_s93 = viv_s92 + viv_s90[7:0]; + always @(*) begin + case(lum_weight_gain) + 3'h0 : viv_s94 = {3'b0,viv_s93[ 8:1]}; + 3'h1 : viv_s94 = {3'b0,viv_s93[ 7:0]}; + 3'h2 : viv_s94 = {2'b0,viv_s93[ 9:1]}; + 3'h3 : viv_s94 = {2'b0,viv_s93[ 7:0],1'b0}; + 3'h4 : viv_s94 = {1'b0,viv_s93[ 9:0]}; + 3'h5 : viv_s94 = {1'b0,viv_s93[ 7:0],2'b0}; + default: viv_s94 = { viv_s93[ 9:0],1'b0}; + endcase + end + assign viv_s91 = (viv_s90[8]) ? 8'h00 : + (|viv_s94[10:7]) ? 8'hFF : + {viv_s94[6:0],1'b0}; + assign viv_s95 = {1'b0, lum_weight_min} + viv_s91; + assign viv_s97 = viv_s112 + viv_s111; + always @(posedge clk or negedge reset_n) begin + if (reset_n == 1'b0) begin + viv_s86 <= 8'b0; + viv_s87 <= 8'b0; + viv_s88 <= 8'b0; + viv_s89 <= 8'b0; + viv_s113 <= 1'b0; + viv_s114 <= 1'b0; + viv_s115 <= 1'b0; + edge_dir <= 1'b0; + viv_s98 <= 12'b0; + viv_s99 <= 12'b0; + viv_s100 <= 12'b0; + viv_s96 <= 8'b0; + viv_s107 <= 12'b0; + viv_s108 <= 12'b0; + viv_s109 <= 12'b0; + viv_s110 <= 12'b0; + viv_s111 <= 12'b0; + viv_s112 <= 12'b0; + viv_s102 <= 11'b0; + end else begin + if (alom_dem_stage3_en) begin + viv_s86 <= viv_s72[9:2]; + viv_s107 <= viv_s103; + viv_s108 <= viv_s104; + viv_s109 <= viv_s105; + viv_s110 <= viv_s106; + end + if (alom_dem_stage4_en) begin + viv_s111 <= {1'b0, f_abs_hv(viv_s107)} + {1'b0, f_abs_hv(viv_s109)}; + viv_s112 <= {1'b0, f_abs_hv(viv_s108)} + {1'b0, f_abs_hv(viv_s110)}; + viv_s87 <= viv_s86; + end + if (alom_dem_stage5_en) begin + viv_s88 <= viv_s87; + viv_s98 <= viv_s97; + if( (viv_s112 < viv_s111)) + viv_s113 <= 1; + else + viv_s113 <= 0; + end + if (alom_dem_stage6_en) begin + viv_s89 <= viv_s88; + viv_s99 <= viv_s98; + viv_s114 <= viv_s113; + end + if (alom_dem_stage7_en) begin + viv_s100 <= viv_s99; + viv_s96 <= (viv_s95[8]) ? 8'hFF : viv_s95[7:0]; + viv_s115 <= viv_s114; + end + if (alom_dem_stage8_en) begin + edge_dir <= viv_s115; + viv_s102 <= {viv_s101[18] || viv_s101[17], viv_s101[16:7]}; + end + end + end + assign viv_s101 = viv_s100 * viv_s96[7:1]; + always@(*) begin + if (viv_s102 > {1'b0, filt_thres_sh1}) detail_level = 3'h4; + else if(viv_s102 > {1'b0, filt_thres_sh0}) detail_level = 3'h3; + else if(viv_s102 < {1'b0, filt_thres_bl1}) detail_level = 3'h0; + else if(viv_s102 < {1'b0, filt_thres_bl0}) detail_level = 3'h1; + else detail_level = 3'h2; + end + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + flag_h_1 <= 1'b0; + flag_h_2 <= 1'b0; + flag_h_3 <= 1'b0; + flag_v_1 <= 1'b0; + flag_v_2 <= 1'b0; + flag_v_3 <= 1'b0; + end else begin + if (alom_dem_stage3_en) begin + flag_v_1 <= viv_s13; + flag_v_2 <= viv_s57; + flag_v_3 <= viv_s71; + flag_h_1 <= viv_s12; + flag_h_2 <= viv_s56; + flag_h_3 <= viv_s70; + end + end + end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_gamma_channel_fix.v b/ispyocto/rtl/ispyocto/vsisp_isp_gamma_channel_fix.v new file mode 100644 index 0000000..bbd514a --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_isp_gamma_channel_fix.v
@@ -0,0 +1,297 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_isp_gamma_channel_fix ( + clk, + reset_n, + soft_rst, + enable, + equ_segm, + y0, + y1, + y2, + y3, + y4, + y5, + y6, + y7, + y8, + y9, + y10, + y11, + y12, + y13, + y14, + y15, + y16, + in_data, + in_h_end, + in_v_end, + in_val, + in_ack, + out_data, + out_h_end, + out_v_end, + out_val, + out_ack + ); +`include "vsisp_isp.vh" +input clk; +input reset_n; +input soft_rst; +input enable; +input equ_segm; +input [c_dw_do-1:0] y0; +input [c_dw_do-1:0] y1; +input [c_dw_do-1:0] y2; +input [c_dw_do-1:0] y3; +input [c_dw_do-1:0] y4; +input [c_dw_do-1:0] y5; +input [c_dw_do-1:0] y6; +input [c_dw_do-1:0] y7; +input [c_dw_do-1:0] y8; +input [c_dw_do-1:0] y9; +input [c_dw_do-1:0] y10; +input [c_dw_do-1:0] y11; +input [c_dw_do-1:0] y12; +input [c_dw_do-1:0] y13; +input [c_dw_do-1:0] y14; +input [c_dw_do-1:0] y15; +input [c_dw_do-1:0] y16; +input [c_dw_si-1:0] in_data; +input in_h_end; +input in_v_end; +input in_val; +output in_ack; +output [c_dw_do-1:0] out_data; +output out_h_end; +output out_v_end; +output out_val; +input out_ack; +reg [c_dw_do-1:0] out_data; +reg out_val; +reg out_h_end; +reg out_v_end; +reg [3:0] viv_s0; +reg [1:0] viv_s1; +reg [1:0] viv_s2; +reg [c_dw_do:0] viv_s3; +wire [c_dw_do:0] viv_s4; +wire [c_dw_do:0] viv_s5; +reg [c_dw_do:0] viv_s6; +reg [7:0] viv_s7; +wire [c_dw_si:0] viv_s8; +wire [c_dw_si-4:0] viv_s9; +reg [c_dw_si-4:0] viv_s10; +reg [c_dw_do-1:0] viv_s11; +reg [c_dw_do-1:0] viv_s12; +wire [c_dw_si+c_dw_do-3:0] viv_s13; +wire [c_dw_si+c_dw_do:0] viv_s14; +wire [c_dw_do+2:0] viv_s15; +wire [c_dw_do-1:0] viv_s16; +wire signed [c_dw_do:0] viv_s17; +wire signed [c_dw_si-3:0] viv_s18; +wire signed [c_dw_si+c_dw_do-3:0] viv_s19; +wire in_ack; +wire viv_s20; +reg viv_s21; +reg viv_s22; +reg viv_s23; +assign in_ack = (~viv_s21 & enable) | viv_s20; +assign viv_s20 = ~out_val | out_ack; +always @(*) + begin + if (equ_segm) viv_s0 = in_data[c_dw_si-1:c_dw_si-4]; + else if (in_data[c_dw_si-1:c_dw_si-3] == 3'd0) begin + if (in_data[c_dw_si-4:c_dw_si-6] == 3'd0) viv_s0=0; + else if (in_data[c_dw_si-4:c_dw_si-6] == 3'd1) viv_s0=1; + else if (in_data[c_dw_si-4:c_dw_si-6] == 3'd2) viv_s0=2; + else if (in_data[c_dw_si-4:c_dw_si-5] == 2'd1) viv_s0=3; + else if (in_data[c_dw_si-4:c_dw_si-5] == 2'd2) viv_s0=4; + else viv_s0=5; + end else if (in_data[c_dw_si-1] == 1'd0) begin + if (in_data[c_dw_si-2:c_dw_si-5] == 4'd4) viv_s0=6; + else if (in_data[c_dw_si-2:c_dw_si-4] == 3'd2) viv_s0=7; + else if (in_data[c_dw_si-2:c_dw_si-4] == 3'd3) viv_s0=8; + else if (in_data[c_dw_si-2:c_dw_si-4] == 3'd4) viv_s0=9; + else if (in_data[c_dw_si-2:c_dw_si-3] == 2'd2) viv_s0=10; + else viv_s0=11; + end else begin + case (in_data[c_dw_si-2:c_dw_si-3]) + 2'd0 : viv_s0=12; + 2'd1 : viv_s0=13; + 2'd2 : viv_s0=14; + default : viv_s0=15; + endcase + end + end +always @(viv_s0 or equ_segm) + begin + if (equ_segm) viv_s7 = {viv_s0,4'd0}; + else + case (viv_s0) + 4'd0 : viv_s7 = 8'd0; + 4'd1 : viv_s7 = 8'd4; + 4'd2 : viv_s7 = 8'd8; + 4'd3 : viv_s7 = 8'd12; + 4'd4 : viv_s7 = 8'd16; + 4'd5 : viv_s7 = 8'd24; + 4'd6 : viv_s7 = 8'd32; + 4'd7 : viv_s7 = 8'd40; + 4'd8 : viv_s7 = 8'd48; + 4'd9 : viv_s7 = 8'd64; + 4'd10: viv_s7 = 8'd80; + 4'd11: viv_s7 = 8'd96; + 4'd12: viv_s7 = 8'd128; + 4'd13: viv_s7 = 8'd160; + 4'd14: viv_s7 = 8'd192; + default: viv_s7 = 8'd224; + endcase +end +always @(viv_s0 or equ_segm) + begin + if (equ_segm) viv_s1 = 2'd2; + else + case(viv_s0) + 4'd0 : viv_s1 = 2'd0; + 4'd1 : viv_s1 = 2'd0; + 4'd2 : viv_s1 = 2'd0; + 4'd3 : viv_s1 = 2'd0; + 4'd4 : viv_s1 = 2'd1; + 4'd5 : viv_s1 = 2'd1; + 4'd6 : viv_s1 = 2'd1; + 4'd7 : viv_s1 = 2'd1; + 4'd8 : viv_s1 = 2'd2; + 4'd9 : viv_s1 = 2'd2; + 4'd10 : viv_s1 = 2'd2; + default: viv_s1 = 2'd3; + endcase +end +always @(viv_s0 or + y0 or y1 or y2 or y3 or y4 or y5 or y6 or y7 or y8 or + y9 or y10 or y11 or y12 or y13 or y14 or y15) + begin + case(viv_s0) + 4'd0 : viv_s11 = y0 ; + 4'd1 : viv_s11 = y1 ; + 4'd2 : viv_s11 = y2 ; + 4'd3 : viv_s11 = y3 ; + 4'd4 : viv_s11 = y4 ; + 4'd5 : viv_s11 = y5 ; + 4'd6 : viv_s11 = y6 ; + 4'd7 : viv_s11 = y7 ; + 4'd8 : viv_s11 = y8 ; + 4'd9 : viv_s11 = y9 ; + 4'd10 : viv_s11 = y10; + 4'd11 : viv_s11 = y11; + 4'd12 : viv_s11 = y12; + 4'd13 : viv_s11 = y13; + 4'd14 : viv_s11 = y14; + default: viv_s11 = y15; + endcase +end +assign viv_s4 = &y16[c_dw_do-1:c_dw_do-8] ? {1'b1,{c_dw_do{1'b0}}} : {1'b0,y16}; +always @(viv_s0 or y1 or y2 or y3 or y4 or y5 or y6 or y7 or y8 or + y9 or y10 or y11 or y12 or y13 or y14 or y15 or viv_s4) + begin + case(viv_s0) + 4'd0 : viv_s3 = {1'b0,y1} ; + 4'd1 : viv_s3 = {1'b0,y2} ; + 4'd2 : viv_s3 = {1'b0,y3} ; + 4'd3 : viv_s3 = {1'b0,y4} ; + 4'd4 : viv_s3 = {1'b0,y5} ; + 4'd5 : viv_s3 = {1'b0,y6} ; + 4'd6 : viv_s3 = {1'b0,y7} ; + 4'd7 : viv_s3 = {1'b0,y8} ; + 4'd8 : viv_s3 = {1'b0,y9} ; + 4'd9 : viv_s3 = {1'b0,y10}; + 4'd10 : viv_s3 = {1'b0,y11}; + 4'd11 : viv_s3 = {1'b0,y12}; + 4'd12 : viv_s3 = {1'b0,y13}; + 4'd13 : viv_s3 = {1'b0,y14}; + 4'd14 : viv_s3 = {1'b0,y15}; + default: viv_s3 = viv_s4; + endcase +end +assign viv_s5 = viv_s3 - {1'b0,viv_s11}; +assign viv_s8 = {1'b0,in_data} - {viv_s7,{c_dw_si-8{1'b0}}}; +assign viv_s9 = viv_s8[c_dw_si-4:0]; +assign viv_s17 = viv_s6; +assign viv_s18 = {1'b0, viv_s10}; +assign viv_s19 = viv_s17 * viv_s18; +assign viv_s13 = viv_s19; +assign viv_s14 = ({{3{viv_s13[c_dw_si+c_dw_do-3]}},viv_s13} >>(c_dw_si-8))>> viv_s2; +assign viv_s15 = viv_s14[c_dw_do+3:1] + {1'b0,viv_s12,1'b1}; +assign viv_s16 = viv_s15[c_dw_do:1]; +always @ (posedge clk or negedge reset_n) begin + if(~reset_n) begin + viv_s21 <= 1'b0; + viv_s10 <= {c_dw_si-3{1'b0}}; + viv_s6 <= {c_dw_do+1{1'b0}}; + viv_s2 <= 2'b0; + viv_s12 <= {c_dw_do{1'b0}}; + viv_s22 <= 1'b0; + viv_s23 <= 1'b0; + end else begin + if(soft_rst) begin + viv_s21 <= 1'b0; + viv_s22 <= 1'b0; + viv_s23 <= 1'b0; + end else if (in_ack) begin + viv_s10 <= viv_s9; + viv_s6 <= viv_s5; + viv_s2 <= viv_s1; + viv_s12 <= viv_s11; + viv_s21 <= in_val; + viv_s22 <= in_h_end; + viv_s23 <= in_v_end; + end + end +end +always @ (posedge clk or negedge reset_n) begin + if(~reset_n) begin + out_val <= 1'b0; + out_data <= {c_dw_do{1'b0}}; + out_h_end <= 1'b0; + out_v_end <= 1'b0; + end else begin + if(soft_rst) begin + out_val <= 1'b0; + out_h_end <= 1'b0; + out_v_end <= 1'b0; + end else if (viv_s20) begin + if(enable) begin + out_data <= (viv_s15[c_dw_do+1]) ? {c_dw_do{1'b1}} : viv_s16; + out_val <= viv_s21; + out_h_end <= viv_s22; + out_v_end <= viv_s23; + end else begin + out_data <= in_data[c_dw_si-1:c_dw_si-c_dw_do]; + out_val <= in_val; + out_h_end <= in_h_end; + out_v_end <= in_v_end; + end + end + end +end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_gamma_out.v b/ispyocto/rtl/ispyocto/vsisp_isp_gamma_out.v new file mode 100644 index 0000000..5ab068f --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_isp_gamma_out.v
@@ -0,0 +1,213 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_isp_gamma_out ( + clk, + reset_n, + soft_rst, + enable, + equ_segm, + y0, + y1, + y2, + y3, + y4, + y5, + y6, + y7, + y8, + y9, + y10, + y11, + y12, + y13, + y14, + y15, + y16, + in_data, + in_h_end, + in_v_end, + in_val, + in_ack, + out_data, + out_h_end, + out_v_end, + out_val, + out_ack + ); + `include "vsisp_isp.vh" + input clk; + input reset_n; + input soft_rst; + input enable; + input equ_segm; + input [c_dw_do-1:0] y0; + input [c_dw_do-1:0] y1; + input [c_dw_do-1:0] y2; + input [c_dw_do-1:0] y3; + input [c_dw_do-1:0] y4; + input [c_dw_do-1:0] y5; + input [c_dw_do-1:0] y6; + input [c_dw_do-1:0] y7; + input [c_dw_do-1:0] y8; + input [c_dw_do-1:0] y9; + input [c_dw_do-1:0] y10; + input [c_dw_do-1:0] y11; + input [c_dw_do-1:0] y12; + input [c_dw_do-1:0] y13; + input [c_dw_do-1:0] y14; + input [c_dw_do-1:0] y15; + input [c_dw_do-1:0] y16; + input [(3*c_dw_si)-1:0] in_data; + input in_h_end; + input in_v_end; + input in_val; + output in_ack; + output [(3*c_dw_do)-1:0] out_data; + output out_h_end; + output out_v_end; + output out_val; + input out_ack; + wire [c_dw_do-1:0] viv_s0; + wire viv_s1; + wire viv_s2; + wire viv_s3; + wire [c_dw_do-1:0] viv_s4; + wire [c_dw_do-1:0] viv_s5; + wire viv_s6; + wire viv_s7; + wire viv_s8; + wire viv_s9; + wire viv_s10; + wire viv_s11; + wire viv_s12; + wire viv_s13; + wire viv_s14; + vsisp_isp_gamma_channel_fix u_isp_gamma_r_channel_fix ( + .clk(clk), + .reset_n(reset_n), + .soft_rst(soft_rst), + .enable(enable), + .equ_segm(equ_segm), + .y0(y0), + .y1(y1), + .y2(y2), + .y3(y3), + .y4(y4), + .y5(y5), + .y6(y6), + .y7(y7), + .y8(y8), + .y9(y9), + .y10(y10), + .y11(y11), + .y12(y12), + .y13(y13), + .y14(y14), + .y15(y15), + .y16(y16), + .in_data(in_data[3*c_dw_si-1:2*c_dw_si]), + .in_h_end(in_h_end), + .in_v_end(in_v_end), + .in_val(in_val), + .in_ack(viv_s6), + .out_data(viv_s0), + .out_h_end(viv_s1), + .out_v_end(viv_s2), + .out_val(viv_s3), + .out_ack(out_ack) + ); + vsisp_isp_gamma_channel_fix u_isp_gamma_g_channel_fix ( + .clk(clk), + .reset_n(reset_n), + .soft_rst(soft_rst), + .enable(enable), + .equ_segm(equ_segm), + .y0(y0), + .y1(y1), + .y2(y2), + .y3(y3), + .y4(y4), + .y5(y5), + .y6(y6), + .y7(y7), + .y8(y8), + .y9(y9), + .y10(y10), + .y11(y11), + .y12(y12), + .y13(y13), + .y14(y14), + .y15(y15), + .y16(y16), + .in_data(in_data[2*c_dw_si-1:c_dw_si]), + .in_h_end(in_h_end), + .in_v_end(in_v_end), + .in_val(in_val), + .in_ack(viv_s7), + .out_data(viv_s4), + .out_h_end(viv_s8), + .out_v_end(viv_s9), + .out_val(viv_s10), + .out_ack(out_ack) + ); + vsisp_isp_gamma_channel_fix u_isp_gamma_b_channel_fix ( + .clk(clk), + .reset_n(reset_n), + .soft_rst(soft_rst), + .enable(enable), + .equ_segm(equ_segm), + .y0(y0), + .y1(y1), + .y2(y2), + .y3(y3), + .y4(y4), + .y5(y5), + .y6(y6), + .y7(y7), + .y8(y8), + .y9(y9), + .y10(y10), + .y11(y11), + .y12(y12), + .y13(y13), + .y14(y14), + .y15(y15), + .y16(y16), + .in_data(in_data[c_dw_si-1:0]), + .in_h_end(in_h_end), + .in_v_end(in_v_end), + .in_val(in_val), + .in_ack(viv_s11), + .out_data(viv_s5), + .out_h_end(viv_s12), + .out_v_end(viv_s13), + .out_val(viv_s14), + .out_ack(out_ack) + ); + assign out_data = {viv_s0,viv_s4,viv_s5}; + assign out_h_end = viv_s1; + assign out_v_end = viv_s2; + assign out_val = viv_s3; + assign in_ack = viv_s6; +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_inform.v b/ispyocto/rtl/ispyocto/vsisp_isp_inform.v new file mode 100644 index 0000000..eb4c717 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_isp_inform.v
@@ -0,0 +1,610 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_isp_inform + ( + clk, + reset_clk_n, + soft_rst, + s_data, + s_hsync, + s_vsync, + s_data_val, + s_data_ack, + out_bls_data, + out_bls_h_end, + out_bls_v_end, + out_bls_val, + inform_mux_data, + inform_mux_h_end, + inform_mux_v_end, + inform_mux_val, + inform_mux_ack, + regs_hsync_pol, + regs_vsync_pol, + regs_acq_h_offs, + regs_acq_v_offs, + regs_acq_h_size, + regs_acq_v_size, + regs_bayer_pat, + out_h_offs_shd, + out_v_offs_shd, + regs_input_pin_map, + regs_input_selection, + regs_field_selection, + regs_field_inv, + regs_isp_mode, + regs_inform_enable, + regs_cfg_upd, + regs_gen_cfg_upd, + bayer_pat_act, + bayer_pat_diff, + frame_in_irq, + inform_en_shd, + field, + in_size_err, + h_start_edge, + v_start_edge + ); +`include "vsisp_isp.vh" + input clk; + input reset_clk_n; + input soft_rst; + input [c_dw_si-1:0] s_data; + input s_hsync; + input s_vsync; + input s_data_val; + output s_data_ack; + output [c_dw_si-1:0] out_bls_data; + output out_bls_h_end; + output out_bls_v_end; + output out_bls_val; + output [c_dw_si-1:0] inform_mux_data; + output inform_mux_h_end; + output inform_mux_v_end; + output inform_mux_val; + input inform_mux_ack; + input regs_hsync_pol; + input regs_vsync_pol; + input [14:0] regs_acq_h_offs; + input [13:0] regs_acq_v_offs; + input [14:0] regs_acq_h_size; + input [13:0] regs_acq_v_size; + input [2:0] regs_input_pin_map; + input [2:0] regs_input_selection; + input [1:0] regs_field_selection; + input regs_field_inv; + input [2:0] regs_isp_mode; + input regs_inform_enable; + input [1:0] regs_bayer_pat; + input regs_cfg_upd; + input regs_gen_cfg_upd; + input [13:0] out_h_offs_shd; + input [13:0] out_v_offs_shd; + output [1:0] bayer_pat_act; + output [1:0] bayer_pat_diff; + output frame_in_irq; + output inform_en_shd; + output field; + output in_size_err; + output h_start_edge; + output v_start_edge; + reg frame_in_irq; + reg [c_dw_si-1:0] viv_s0; + reg [c_dw_si-1:0] viv_s1; + reg [15:0] viv_s2; + reg [14:0] viv_s3; + reg viv_s4; + reg viv_s5; + wire viv_s6; + reg viv_s7; + reg viv_s8; + reg viv_s9; + reg viv_s10; + reg viv_s11; + reg viv_s12; + reg inform_en_shd; + wire viv_s13; + reg viv_s14; + reg viv_s15; + wire in_size_err; + reg [1:0] viv_s16; + reg field; + wire viv_s17; + wire viv_s18; + reg viv_s19; + reg viv_s20; + reg viv_s21; + wire h_start_edge; + wire v_start_edge; + wire viv_s22; + wire [15:0] viv_s23; + wire [14:0] viv_s24; + reg [c_dw_si-1:0] out_bls_data; + reg out_bls_h_end; + reg out_bls_v_end; + reg out_bls_val; + wire viv_s25; + wire viv_s26; + reg viv_s27; + reg viv_s28; + reg viv_s29; + reg [c_dw_si-1:0] viv_s30; + wire viv_s31; + reg inform_mux_val; + reg [c_dw_si-1:0] inform_mux_data; + reg inform_mux_h_end; + reg inform_mux_v_end; + wire inform_mux_ack; + wire viv_s32; + wire viv_s33; + wire viv_s34; + wire viv_s35; + wire viv_s36; + wire [14:0] viv_s37; + wire viv_s38; + wire viv_s39; + wire s_data_ack; + reg [1:0] bayer_pat_act; + reg [1:0] bayer_pat_diff; + reg viv_s40; + wire viv_s41; + wire viv_s42; + wire viv_s43; + wire viv_s44; + reg [c_dw_si-1:0] viv_s45; + reg [c_dw_si-1:0] viv_s46; + reg viv_s47; + wire viv_s48; + wire viv_s49; + wire viv_s50; + wire viv_s51; + reg viv_s52; + wire viv_s53; + reg viv_s54; + wire viv_s55; + wire viv_s56; + wire viv_s57; + wire viv_s58; + reg viv_s59; + reg viv_s60; + reg [c_dw_si-1:0] viv_s61; + reg viv_s62; + wire viv_s63; + wire viv_s64; + wire viv_s65; + wire viv_s66; + wire viv_s67; + wire viv_s68; + assign viv_s13 = soft_rst | ~inform_en_shd; + assign viv_s55 = (regs_isp_mode[2:0] == 3'b001)| + (regs_isp_mode[2:0] == 3'b101)| + (regs_isp_mode[2:0] == 3'b110); + assign viv_s56 = (regs_isp_mode[2:0] == 3'b000)| + (regs_isp_mode[2:0] == 3'b100)| + (regs_isp_mode[2:0] == 3'b110); + assign viv_s57 = (regs_isp_mode[2:0] == 3'b100); + assign in_size_err = viv_s14 | viv_s15; + assign viv_s38 = ((v_start_edge || viv_s5) & viv_s4 & viv_s32); + assign viv_s37 = (~viv_s56) ? {regs_acq_h_size[14:1],1'b0} : + regs_acq_h_size; + assign viv_s23 = (regs_acq_h_offs + {1'b0,viv_s37}) - 1'b1; + assign viv_s24 = (regs_acq_v_offs + {1'b0,regs_acq_v_size}) - 1'b1; + assign viv_s32 = (viv_s2 == viv_s23); + assign viv_s33 = (viv_s3 == viv_s24); + always @(viv_s2 or viv_s3 or viv_s4 or viv_s5 or regs_acq_h_offs or + viv_s23 or viv_s24 or regs_acq_v_offs ) begin + if (viv_s4) begin + if ((viv_s2 >= {1'b0,regs_acq_h_offs}) & (viv_s2 <= viv_s23)) begin + viv_s7 = 1'b1; + end else begin + viv_s7 = 1'b0; + end + end else + viv_s7 = 1'b0; + if (viv_s5) begin + if ((viv_s3 >= {1'b0,regs_acq_v_offs}) & (viv_s3 <= viv_s24)) begin + viv_s8 = 1'b1; + end else begin + viv_s8 = 1'b0; + end + end else + viv_s8 = 1'b0; + end + assign viv_s6 = viv_s8 & viv_s7; + assign viv_s34 = (regs_field_selection[1]) ? + (viv_s36==1'b0) : + (regs_field_selection[0]) ? + (viv_s36==1'b1) : 1'b1; + assign viv_s17 = !inform_en_shd ? 1'b0 : + (viv_s55) ? ~viv_s9 : + viv_s42; + assign viv_s18 = !inform_en_shd ? 1'b0 : + (viv_s55) ? ~viv_s10 : + viv_s43; + assign viv_s35 = (viv_s55) ? viv_s11 : viv_s40; + assign viv_s36 = (regs_field_inv) ? ~viv_s35 : viv_s35; + assign viv_s42 = (regs_hsync_pol)? ~s_hsync : s_hsync; + assign viv_s43 = (regs_vsync_pol)? ~s_vsync : s_vsync; + assign viv_s51 = viv_s43; + assign viv_s53 = !viv_s51 & viv_s52; + assign viv_s50 = viv_s59 ? viv_s47 : viv_s6 & viv_s34 & viv_s47; + assign viv_s25 = viv_s59 ? viv_s54 : viv_s32; + assign viv_s26 = viv_s59 ? viv_s54 : viv_s33; + assign viv_s41 = (viv_s59) ? viv_s42 & viv_s43 & s_data_val : s_data_val; + assign viv_s58 = viv_s57 & !viv_s59; + always @(*) begin + case (regs_input_pin_map) + 3'b000 :viv_s45 = s_data[c_dw_si-1:0]; + 3'b001 :viv_s45 = {s_data[9:0],{(c_dw_si-10){1'b0}}}; + 3'b010 :viv_s45 = {s_data[7:0],{(c_dw_si- 8){1'b0}}}; + 3'b011 :viv_s45 = {s_data[9:2],{(c_dw_si- 8){1'b0}}}; + default:viv_s45 = s_data[c_dw_si-1:0]; + endcase + end + always @(posedge clk or negedge reset_clk_n) begin + if (!reset_clk_n) begin + viv_s59 <= 1'b0; + viv_s46 <= {c_dw_si{1'b0}}; + viv_s47 <= 1'b0; + end + else begin + if (viv_s13) begin + viv_s59 <= 1'b0; + viv_s46 <= {c_dw_si{1'b0}}; + viv_s47 <= 1'b0; + end else begin + viv_s59 <= viv_s57; + if (viv_s58) begin + viv_s47 <= 1'b0; + end + else if (viv_s44) begin + viv_s46 <= viv_s45; + viv_s47 <= viv_s41; + end + end + end + end + assign viv_s44 = viv_s48 | (~viv_s47); + assign s_data_ack = viv_s44; + always @(posedge clk or negedge reset_clk_n) begin + if(~reset_clk_n) begin + bayer_pat_act <= 2'b0; + bayer_pat_diff <= 2'b0; + end else begin + if (soft_rst) begin + bayer_pat_act <= 2'b0; + bayer_pat_diff <= 2'b0; + end else begin + bayer_pat_diff[1] <= out_v_offs_shd[0]; + bayer_pat_diff[0] <= out_h_offs_shd[0]; + bayer_pat_act[1] <= regs_bayer_pat[1] ^ out_v_offs_shd[0]; + bayer_pat_act[0] <= regs_bayer_pat[0] ^ out_h_offs_shd[0]; + end + end + end + always @(posedge clk or negedge reset_clk_n) begin + if(~reset_clk_n) begin + frame_in_irq <= 1'b0; + end else begin + if (soft_rst) begin + frame_in_irq <= 1'b0; + end else begin + if (inform_mux_h_end & inform_mux_v_end & inform_mux_val) + frame_in_irq <= 1'b1; + else + frame_in_irq <= 1'b0; + end + end + end + always @(*) begin + case (regs_input_selection) + 3'b000 : viv_s0 = viv_s46[c_dw_si-1:0]; + 3'b001 : viv_s0 = {viv_s46[c_dw_si-1:2],2'b00}; + 3'b010 : viv_s0 = {viv_s46[c_dw_si-1:2],viv_s46[c_dw_si-1:c_dw_si-2]}; + 3'b011 : viv_s0 = {viv_s46[c_dw_si-1:4],4'b00}; + default: viv_s0 = {viv_s46[c_dw_si-1:4],viv_s46[c_dw_si-1:c_dw_si-4]}; + endcase + end + always @(*) begin + case (regs_input_selection) + 3'b000 :viv_s1 = viv_s45[c_dw_si-1:0]; + 3'b001 :viv_s1 = {viv_s45[c_dw_si-1:2],2'b00}; + 3'b010 :viv_s1 = {viv_s45[c_dw_si-1:2],viv_s45[c_dw_si-1:c_dw_si-2]}; + 3'b011 :viv_s1 = {viv_s45[c_dw_si-1:4],4'b00}; + default:viv_s1 = {viv_s45[c_dw_si-1:4],viv_s45[c_dw_si-1:c_dw_si-4]}; + endcase + end + always @(posedge clk or negedge reset_clk_n) begin + if(~reset_clk_n) begin + viv_s19 <= 1'b0; + viv_s20 <= 1'b0; + viv_s21 <= 1'b0; + end else begin + viv_s19 <= viv_s17; + viv_s20 <= viv_s18; + viv_s21 <= inform_en_shd; + end + end + assign h_start_edge = viv_s17 & !viv_s19 & !viv_s22; + assign v_start_edge = viv_s18 & !viv_s20 & !viv_s22; + assign viv_s22 = inform_en_shd & ~viv_s21; + always @(posedge clk or negedge reset_clk_n) begin + if(~reset_clk_n) begin + viv_s2 <= 16'd0; + viv_s3 <= 15'd0; + viv_s4 <= 1'b0; + viv_s5 <= 1'b0; + inform_en_shd <= 1'b0; + end else begin + if(viv_s13) begin + viv_s2 <= 16'd0; + viv_s3 <= 15'd0; + viv_s4 <= 1'b0; + viv_s5 <= 1'b0; + inform_en_shd <= regs_inform_enable; + end else begin + if (v_start_edge) begin + viv_s3 <= 15'd0; + viv_s5 <= 1'b1; + end else if (viv_s32 & viv_s47 & viv_s48) begin + viv_s3 <= viv_s3 + 1'd1; + end + if (viv_s38 & viv_s47 & viv_s48) begin + if(viv_s33) begin + inform_en_shd <= regs_inform_enable; + viv_s5 <= 1'b0; + end + end + if (h_start_edge) begin + viv_s2 <= 16'd0; + end else if (viv_s47 & viv_s48 & viv_s4) begin + viv_s2 <= viv_s2 + 1; + end + if (h_start_edge & (v_start_edge | viv_s5)) begin + viv_s4 <= 1'b1; + end else if (viv_s32 & viv_s47 & viv_s48) begin + viv_s4 <= 1'b0; + end + end + end + end + assign viv_s39 = viv_s50 & viv_s25 & viv_s26; + always @(posedge clk or negedge reset_clk_n) begin + if(~reset_clk_n) begin + viv_s9 <= 1'b0; + viv_s10 <= 1'b0; + viv_s11 <= 1'b0; + viv_s12 <= 1'b0; + field <= 1'b0; + viv_s16 <= c_pre0; + end else begin + if(viv_s13) begin + viv_s9 <= 1'b0; + viv_s10 <= 1'b0; + viv_s11 <= 1'b0; + viv_s12 <= 1'b0; + field <= 1'b0; + viv_s16 <= c_pre0; + end else begin + if (viv_s39) begin + field <= viv_s36; + end + if (s_data_val & s_data_ack & viv_s55) begin + case (viv_s16) + c_pre1: begin + if(|viv_s1[c_dw_si-1:c_dw_si-8]) + viv_s16 <= c_pre0; + else + viv_s16 <= c_pre2; + end + c_pre2: begin + if(|viv_s1[c_dw_si-1:c_dw_si-8]) + viv_s16 <= c_pre0; + else + viv_s16 <= c_status; + end + c_status: begin + viv_s11 <= viv_s1[c_dw_si-2]; + viv_s10 <= viv_s1[c_dw_si-3]; + viv_s9 <= viv_s1[c_dw_si-4]; + viv_s16 <= c_pre0; + end + default: begin + if(&viv_s1[c_dw_si-1:c_dw_si-8]) + viv_s16 <= c_pre1; + end + endcase + end + if(v_start_edge) begin + viv_s12 <= ~viv_s17; + end + end + end + end + always @(posedge clk or negedge reset_clk_n) begin + if(~reset_clk_n) begin + viv_s52 <= 1'b0; + viv_s54 <= 1'b0; + end else begin + if(viv_s13) begin + viv_s52 <= 1'b0; + viv_s54 <= 1'b0; + end else begin + if (viv_s59) begin + viv_s52 <= viv_s51; + viv_s54 <= viv_s53; + end + end + end + end + always @(posedge clk or negedge reset_clk_n) begin + if(~reset_clk_n) begin + viv_s14 <= 1'b0; + viv_s15 <= 1'b0; + end else begin + if(soft_rst) begin + viv_s14 <= 1'b0; + viv_s15 <= 1'b0; + end else begin + viv_s14 <= 1'b0; + viv_s15 <= 1'b0; + if (!viv_s59) begin + if (h_start_edge & viv_s7) begin + viv_s14 <= 1'b1; + end + if (v_start_edge & viv_s8) begin + viv_s15 <= 1'b1; + end + if ((viv_s47 & viv_s48) | (inform_en_shd)) begin + if(~|viv_s37) + viv_s14 <= 1'b1; + if(~|regs_acq_v_size) + viv_s15 <= 1'b1; + end + end + end + end + end + always @(posedge clk or negedge reset_clk_n) begin + if (!reset_clk_n) begin + viv_s29 <= 1'b0; + viv_s30 <= {c_dw_si{1'b0}}; + viv_s27 <= 1'b0; + viv_s28 <= 1'b0; + end + else begin + if (viv_s13) begin + viv_s29 <= 1'b0; + viv_s30 <= {c_dw_si{1'b0}}; + viv_s27 <= 1'b0; + viv_s28 <= 1'b0; + end else begin + if (viv_s31) begin + viv_s29 <= viv_s50; + viv_s30 <= viv_s0; + viv_s27 <= viv_s25; + viv_s28 <= viv_s26; + end + end + end + end + assign viv_s31 = (viv_s49 | (~viv_s29)); + assign viv_s48 = (~viv_s6) ? 1'b1: viv_s31; + always @(posedge clk or negedge reset_clk_n) begin + if(~reset_clk_n) begin + out_bls_val <= 1'b0; + out_bls_data <= {c_dw_si{1'b0}}; + out_bls_h_end <= 1'b0; + out_bls_v_end <= 1'b0; + end else begin + if (soft_rst) begin + out_bls_val <= 1'b0; + end else begin + out_bls_val <= viv_s29 & viv_s49; + out_bls_data <= viv_s30; + out_bls_h_end <= viv_s27; + out_bls_v_end <= viv_s28; + end + end + end + always @(posedge clk or negedge reset_clk_n) begin + if (!reset_clk_n) begin + viv_s60 <= 1'b0; + viv_s61 <= {c_dw_si{1'b0}}; + viv_s62 <= 1'b0; + end + else begin + if (soft_rst) begin + viv_s60 <= 1'b0; + viv_s61 <= {c_dw_si{1'b0}}; + viv_s62 <= 1'b0; + end else begin + if (viv_s65) begin + viv_s60 <= viv_s29; + viv_s61 <= viv_s30; + viv_s62 <= viv_s28; + end + end + end + end + assign viv_s65 = viv_s64 | (~viv_s60); + assign viv_s66 = viv_s65; + assign viv_s67 = viv_s62 ? 1'b1 : + (viv_s28 & !viv_s29) ? 1'b1 : 1'b0; + assign viv_s68 = viv_s60 & + inform_mux_ack & + (viv_s29 | viv_s67); + assign viv_s63 = viv_s68; + assign viv_s64 = viv_s68; + always @(viv_s59 or viv_s63 or viv_s61 or viv_s67 or + viv_s29 or viv_s30 or viv_s27 or viv_s28) begin + if (!viv_s59) begin + inform_mux_data = viv_s30; + inform_mux_val = viv_s29; + inform_mux_h_end = viv_s27; + inform_mux_v_end = viv_s28; + end + else begin + inform_mux_data = viv_s61; + inform_mux_val = viv_s63; + inform_mux_h_end = viv_s67; + inform_mux_v_end = viv_s67; + end + end + assign viv_s49 = viv_s59 ? viv_s66 : inform_mux_ack; + reg[1:0] viv_s69; + always @(posedge clk or negedge reset_clk_n) begin + if(~reset_clk_n) + viv_s69 <= 2'b00; + else + viv_s69 <= {viv_s69[0],{inform_mux_h_end&inform_mux_v_end}}; + end + wire viv_s70 = viv_s69[1]&(~viv_s69[0]); + always @(posedge clk or negedge reset_clk_n) begin + if(~reset_clk_n) + viv_s40 <= 1'b0; + else if(viv_s70) + viv_s40 <= ~viv_s40; + else + viv_s40 <= viv_s40; + end +`ifdef FPGA_DEBUG_ISP + (* mark_debug = "true" *)reg [15:0] probing__inform_h_cnt/* synthesis syn_noprune=1 syn_preserve = 1 */; + (* mark_debug = "true" *)reg [14:0] probing__inform_v_cnt/* synthesis syn_noprune=1 syn_preserve = 1 */; + (* mark_debug = "true" *)reg probing__inform_mux_val/* synthesis syn_noprune=1 syn_preserve = 1 */; + (* mark_debug = "true" *)reg [c_dw_si-1:0] probing__inform_mux_data/* synthesis syn_noprune=1 syn_preserve = 1 */; + (* mark_debug = "true" *)reg probing__inform_mux_h_end/* synthesis syn_noprune=1 syn_preserve = 1 */; + (* mark_debug = "true" *)reg probing__inform_mux_v_end/* synthesis syn_noprune=1 syn_preserve = 1 */; + (* mark_debug = "true" *)reg probing__inform_mux_ack/* synthesis syn_noprune=1 syn_preserve = 1 */; +always@(posedge clk)begin + probing__inform_h_cnt <= viv_s2 ; + probing__inform_v_cnt <= viv_s3 ; + probing__inform_mux_val <= inform_mux_val ; + probing__inform_mux_data <= inform_mux_data ; + probing__inform_mux_h_end <= inform_mux_h_end; + probing__inform_mux_v_end <= inform_mux_v_end; + probing__inform_mux_ack <= inform_mux_ack ; +end +`endif +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_irq_handler.v b/ispyocto/rtl/ispyocto/vsisp_isp_irq_handler.v new file mode 100644 index 0000000..8876260 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_isp_irq_handler.v
@@ -0,0 +1,95 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_isp_irq_handler ( + clk, + reset_n, + soft_rst, + isp_err_status_set, + regs_err_clr, + isp_err_status, + irq_set, + regs_isp_ris, + regs_isp_mis, + regs_isp_imsc, + regs_isp_icr, + regs_isp_isr); +`include "vsisp_isp.vh" + input clk; + input reset_n; + input soft_rst; + input [c_isp_err_bw-1:0] isp_err_status_set; + input [c_isp_err_bw-1:0] regs_err_clr; + output [c_isp_err_bw-1:0] isp_err_status; + input [c_irq_bw-1:0] irq_set; + output [c_irq_bw-1:0] regs_isp_ris; + output [c_irq_bw-1:0] regs_isp_mis; + input [c_irq_bw-1:0] regs_isp_imsc; + input [c_irq_bw-1:0] regs_isp_icr; + input [c_irq_bw-1:0] regs_isp_isr; + reg [c_irq_bw-1:0] regs_isp_ris; + wire [c_irq_bw-1:0] viv_s0; + reg [c_isp_err_bw-1:0] isp_err_status; + assign viv_s0 = (regs_isp_ris | regs_isp_isr | irq_set) & + ~regs_isp_icr; + assign regs_isp_mis = regs_isp_ris & regs_isp_imsc; + always @(posedge clk or negedge reset_n) begin + if (reset_n == 1'b0) begin + regs_isp_ris <= 0; + end else begin + if (soft_rst == 1'b1) begin + regs_isp_ris <= 0; + end else begin + regs_isp_ris <= viv_s0; + end + end + end + always @(posedge clk or negedge reset_n) begin + if (reset_n == 1'b0) begin + isp_err_status <= 0; + end else begin + if (soft_rst == 1'b1) begin + isp_err_status <= 0; + end else begin + if (regs_err_clr[0]) begin + isp_err_status[0] <= 1'b0; + end + else if (isp_err_status_set[0]) begin + isp_err_status[0] <= 1'b1; + end + if (regs_err_clr[1]) begin + isp_err_status[1] <= 1'b0; + end + else if (isp_err_status_set[1]) begin + isp_err_status[1] <= 1'b1; + end + if (regs_err_clr[2]) begin + isp_err_status[2] <= 1'b0; + end + else if (isp_err_status_set[2]) begin + isp_err_status[2] <= 1'b1; + end + end + end + end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_isp_fifo_wrapper.v b/ispyocto/rtl/ispyocto/vsisp_isp_isp_fifo_wrapper.v new file mode 100644 index 0000000..ca79571 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_isp_isp_fifo_wrapper.v
@@ -0,0 +1,424 @@ +//**************************************************************************** +// +// Copyright 2023 Vivante Corp. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_isp_isp_fifo_wrapper(GC_CONTROL,cEn0_,mcReg_registerTimingControl,reset_,rwAddr0,rwclk0,wData0,wEn0_,rData0); + /*NAME: mmsx_isp_isp_fifo_wrapper_sw0x28x128 */ + input [15:0] GC_CONTROL; + input cEn0_; + input [31:0] mcReg_registerTimingControl; + input reset_; + input [7-1:0] rwAddr0; + input rwclk0; + input [28-1:0] wData0; + input wEn0_; + output [28-1:0] rData0; + wire [28-1:0] rData0; + `ifdef FPGA + reg [71:0] fpgaWData_0_0; + wire [71:0] fpgaRData_0_0; + always @(wData0[27:0]) + fpgaWData_0_0 = 72'd0 | wData0[27:0]; + wire [71:0] fpgaRData_0_0_0; + assign rData0[27:0] = fpgaRData_0_0_0[28-1:0]; + wire wEn0Stack_0_0_0_ = wEn0_; + `ifdef FPGA_ALTERA + FPGA_ALTERA_RF2P512W72B ram_0_0_0 ( + .address_a ({2'd0,rwAddr0}), + .address_b ({2'd0,rwAddr0}), + .clock_a (rwclk0), + .clock_b (rwclk0), + .data_a (72'b0), + .data_b (fpgaWData_0_0[71:0]), + .rden_a (~cEn0_ && (cEn0_|wEn0_)), + .rden_b (1'b0), + .wren_a (1'b0), + .wren_b (~(cEn0_|wEn0_)), + .q_a (fpgaRData_0_0_0[71:0]), + .q_b ()); + `else + FPGA_RF2P512W72B ram_0_0_0 ( + .DOA (fpgaRData_0_0_0[63:0]), + .DOPA (fpgaRData_0_0_0[71:64]), + .DOB (), + .DOPB (), + .ADDRA ({2'd0,rwAddr0}), + .DIA (64'd0), + .DIPA (8'd0), + .ENA (~cEn0_ && (cEn0_|wEn0_)), + .CLKA (rwclk0), + .SSRA (1'b0), + .WEA (2'd0), + .ADDRB ({2'd0,rwAddr0}), + .DIB (fpgaWData_0_0[63:0]), + .DIPB (fpgaWData_0_0[71:64]), + .ENB (~(cEn0_|wEn0_)), + .CLKB (rwclk0), + .SSRB (1'b0), + .WEB ({~(cEn0_|wEn0_),~(cEn0_|wEn0_)})); + `endif + `else + `ifdef OLD_MEM_MODEL + `else + `ifdef AQ_TSMC28HPM_RAM_MODEL + wire [7-1:0] BM_AA = {7{1'b0}}; + wire [7-1:0] BM_AB = {7{1'b0}}; + wire BM_CENA = 1'b0; + wire BM_CENB = 1'b0; + wire BM_BENA = 1'b0; + wire [28-1:0] BM_DB = {28{1'b0}}; + wire BM_EN = 1'b0; + wire [1-1:0] BM_WENB = {1{1'b1}}; + wire BIST = (BM_EN & BM_BENA); + wire enableClock = ~(cEn0_) | GC_CONTROL[4]; + `ifdef CG_IN_RAM + wire rwclk0En = rwclk0; + `else + wire rwclk0En; + vsisp_GC_CG_MOD GC_CG_RW(.enable(enableClock), .ck_in(rwclk0), .ck_out(rwclk0En), .test(GC_CONTROL[0])); + `endif + wire [28-1:0] ramRData0; + reg [28-1:0] ramWData0; + always @(wData0[27:0]) begin + ramWData0[28-1:0] = wData0[27:0]; + end + assign rData0[27:0] = ramRData0[28-1:0]; + RF1P128W28B2S ram0 ( + .Q(ramRData0), + .CLK(rwclk0En), + .WEB(wEn0_), + .CEB(cEn0_), + .BWEB({28{1'b0}}), + .A(rwAddr0), + .D(ramWData0), + .SLP(mcReg_registerTimingControl[0]), + .SD(mcReg_registerTimingControl[20]), + .AM(BM_AA), + .DM({BM_DB[27:0]}), + .BWEBM({28{1'b0}}), + .WEBM(BM_CENB), + .CEBM(BM_CENA), + .BIST(BIST), + .TURBO(1'b1), + .RTSEL(2'b01)); + `else + `ifdef AQ_SEC14LPP_RAM_MODEL + wire enableClock = ~(cEn0_) | GC_CONTROL[4]; + `ifdef CG_IN_RAM + wire rwclk0En = rwclk0; + `else + wire rwclk0En; + vsisp_GC_CG_MOD GC_CG_RW(.enable(enableClock), .ck_in(rwclk0), .ck_out(rwclk0En), .test(GC_CONTROL[0])); + `endif + wire [28-1:0] ramRData0; + reg [28-1:0] ramWData0; + always @(wData0[27:0]) begin + ramWData0[28-1:0] = wData0[27:0]; + end + assign rData0[27:0] = ramRData0[28-1:0]; + RF1P128W28B2M1BK0S0HD0WM ram0 ( + .Q(ramRData0), + .CLK(rwclk0En), + .CEN(cEn0_), + .GWEN(wEn0_), + .A(rwAddr0), + .D(ramWData0), + .STOV(1'b0), + .EMA(3'b010), + .EMAW(2'b01), + .EMAS(1'b0), + .RET1N(1'b1)); + `else + `ifdef AQ_TSMC7FF_RAM_MODEL + wire enableClock = ~(cEn0_) | GC_CONTROL[4]; + `ifdef CG_IN_RAM + wire rwclk0En = rwclk0; + `else + wire rwclk0En; + vsisp_GC_CG_MOD GC_CG_RW(.enable(enableClock), .ck_in(rwclk0), .ck_out(rwclk0En), .test(GC_CONTROL[0])); + `endif + wire [30-1:0] ramRData0; + reg [30-1:0] ramWData0; + always @(wData0[27:0]) begin + ramWData0[28-1:0] = wData0[27:0]; + end + assign rData0[27:0] = ramRData0[28-1:0]; + RF1P128W30B1MNSEG0S0HD0WM ram0 ( + .CLK(rwclk0En), + .Q(ramRData0), + .CEB(cEn0_), + .WEB(wEn0_), + .A(rwAddr0), + .D(ramWData0), + .SD(mcReg_registerTimingControl[20]), + .DSLP(mcReg_registerTimingControl[21]), + .DSLPLV(1'b0), + .PUDELAY_DSLP(), + .PUDELAY_SD(), + .RTSEL(2'b10), + .WTSEL(2'b01), + .DFTBYP(1'b0), + .SE(1'b0), + .SIC(1'b0), + .SID(2'b00), + .SOC(), + .SOD()); + `else + `ifdef AQ_TSMC12FFC_RAM_MODEL + wire enableClock = ~(cEn0_) | GC_CONTROL[4]; + `ifdef CG_IN_RAM + wire rwclk0En = rwclk0; + `else + wire rwclk0En; + vsisp_GC_CG_MOD GC_CG_RW(.enable(enableClock), .ck_in(rwclk0), .ck_out(rwclk0En), .test(GC_CONTROL[0])); + `endif + wire [30-1:0] ramRData0; + reg [30-1:0] ramWData0; + always @(wData0[27:0]) begin + ramWData0[28-1:0] = wData0[27:0]; + end + assign rData0[27:0] = ramRData0[28-1:0]; + RF1P128W30B1MSSEG0S0HD0WM ram0 ( + .CLK(rwclk0En), + .Q(ramRData0), + .CEB(cEn0_), + .WEB(wEn0_), + .A(rwAddr0), + .D(ramWData0), + .RTSEL(2'b01), + .WTSEL(2'b01)); + `else + wire enableClock = ~(cEn0_) | GC_CONTROL[4]; + `ifdef CG_IN_RAM + wire rwclk0En = rwclk0; + `else + wire rwclk0En; + vsisp_GC_CG_MOD GC_CG_RW(.enable(enableClock), .ck_in(rwclk0), .ck_out(rwclk0En), .test(GC_CONTROL[0])); + `endif + wire [28-1:0] ramRData0; + reg [28-1:0] ramWData0; + always @(wData0[27:0]) begin + ramWData0[28-1:0] = wData0[27:0]; + end + assign rData0[27:0] = ramRData0[28-1:0]; + vsisp_RAM1P128W28B_SS ram0 ( + .Q(ramRData0), + .CLK(rwclk0En), + .CEB(cEn0_), + .A(rwAddr0), + .WEB(wEn0_), + .BWEB({28{1'b0}}), + .D(ramWData0), + .CLKEN(enableClock), + .TESTEN(GC_CONTROL[0])); + `endif + `endif + `endif + `endif + `endif + `endif + `ifdef VIVANTE_CHECK_RAM_USAGE + `ifdef VIVANTE_SIM_END + reg [1-1:0] writeHappened; + reg readHappened; + initial begin + writeHappened = 1 'd0; + readHappened = 1'd0; + end + always @(posedge rwclk0) begin + readHappened <= (readHappened | (~cEn0_ & wEn0_)); + end + always @(posedge rwclk0) begin + if(~wEn0_ & ~cEn0_) begin + writeHappened <= 1'b1; + end + end + initial begin + @`VIVANTE_SIM_END; + if(&{readHappened,writeHappened}) begin + $display ("RAM USAGE: vsisp_isp_isp_fifo_wrapper at %m fully exercised."); + end else begin + $display ("RAM USAGE: vsisp_isp_isp_fifo_wrapper at %m not fully exercised."); + end + end + `endif + `endif + `ifdef ASSERT_ON_RAM + assert_never wrong_rwaddr0 (rwclk0, reset_, (~cEn0_ & (rwAddr0 > 128-1))); + assert_never_unknown #(0, 7, 0, "address is unknown") address_unknown0(rwclk0, reset_, ~cEn0_, rwAddr0); + assert_never_unknown #(0, 1, 0, "ram enable is unknown") ram_enable_unknown0(rwclk0, reset_, 1'b1, cEn0_); + assert_never_unknown #(0, 32, 0, "config signal is unknown") config_unknown_rw0(rwclk0, reset_, 1'b1, mcReg_registerTimingControl[32-1:0]); + assert_never_unknown #(0, 1, 0, "control signal is unknown") control_unknown_rw0(rwclk0, reset_, 1'b1, GC_CONTROL[4]); + `endif + `ifdef VIVANTE_CHECK_RAM_USAGE2 + `ifdef VIVANTE_RAM_MONITOR_END + parameter rAddr0Num = 8-1; + reg [rAddr0Num:0] rAddr0_r; + reg [31:0] rAddr0Cnt[0:rAddr0Num]; + parameter wAddr0Num = 8-1; + reg [wAddr0Num:0] wAddr0_r; + reg [31:0] wAddr0Cnt[0:wAddr0Num]; + parameter wData0Num = 29-1; + reg [wData0Num:0] wData0_r; + reg [31:0] wData0Cnt[0:wData0Num]; + parameter rData0Num = 29-1; + reg [rData0Num:0] rData0_r; + reg [31:0] rData0Cnt[0:rData0Num]; + initial + begin + #1; + @`VIVANTE_RAM_MONITOR_END + begin + integer i; + for(i=0;i<=rAddr0Num;i=i+1) + begin + $gethierachy(3, i, rAddr0Cnt[i]); + end + for(i=0;i<=wAddr0Num;i=i+1) + begin + $gethierachy(4, i, wAddr0Cnt[i]); + end + for(i=0;i<=wData0Num;i=i+1) + begin + $gethierachy(2, i, wData0Cnt[i]); + end + for(i=0;i<=rData0Num;i=i+1) + begin + $gethierachy(1, i, rData0Cnt[i]); + end + end + end + always @(posedge rwclk0 or negedge reset_) + begin + if(!reset_) + begin + rAddr0_r = 'b0; + rData0_r = 'b0; + end + else if(wEn0_&!cEn0_) + begin + rAddr0_r = rwAddr0; + rData0_r = rData0; + end + end + always @(posedge rwclk0 or negedge reset_) + begin + if(!reset_) + begin + integer i; + for(i=0;i<=rAddr0Num;i=i+1) + begin + rAddr0Cnt[i] = 'b0; + end + end + else if(wEn0_&!cEn0_) + begin + integer i; + for(i=0;i<=rAddr0Num;i=i+1) + begin + if(rAddr0_r[i]^rwAddr0[i]) + begin + rAddr0Cnt[i] = rAddr0Cnt[i] + 1; + end + end + end + end + always @(posedge rwclk0 or negedge reset_) + begin + if(!reset_) + begin + integer i; + for(i=0;i<=rData0Num;i=i+1) + begin + rData0Cnt[i] = 'b0; + end + end + else if(wEn0_&!cEn0_) + begin + integer i; + for(i=0;i<=rData0Num;i=i+1) + begin + if(rData0_r[i]^rData0[i]) + begin + rData0Cnt[i] = rData0Cnt[i] + 1; + end + end + end + end + always @(posedge rwclk0 or negedge reset_) + begin + if(!reset_) + begin + wAddr0_r = 'b0; + wData0_r = 'b0; + end + else if((!wEn0_)&(!cEn0_)) + begin + wAddr0_r = rwAddr0; + wData0_r = wData0; + end + end + always @(posedge rwclk0 or negedge reset_) + begin + if(!reset_) + begin + integer i; + for(i=0;i<=wAddr0Num;i=i+1) + begin + wAddr0Cnt[i] = 'b0; + end + end + else if((!wEn0_)&(!cEn0_)) + begin + integer i; + for(i=0;i<=wAddr0Num;i=i+1) + begin + if(wAddr0_r[i]^rwAddr0[i]) + begin + wAddr0Cnt[i] = wAddr0Cnt[i] + 1; + end + end + end + end + always @(posedge rwclk0 or negedge reset_) + begin + if(!reset_) + begin + integer i; + for(i=0;i<=wData0Num;i=i+1) + begin + wData0Cnt[i] = 'b0; + end + end + else if((!wEn0_)&(!cEn0_)) + begin + integer i; + for(i=0;i<=wData0Num;i=i+1) + begin + if(wData0_r[i]^wData0[i]) + begin + wData0Cnt[i] = wData0Cnt[i] + 1; + end + end + end + end + `endif + `endif +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_isp_ram_wrapper.v b/ispyocto/rtl/ispyocto/vsisp_isp_isp_ram_wrapper.v new file mode 100644 index 0000000..776b9ed --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_isp_isp_ram_wrapper.v
@@ -0,0 +1,602 @@ +//**************************************************************************** +// +// Copyright 2023 Vivante Corp. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_isp_isp_ram_wrapper(GC_CONTROL,cEn0_,mcReg_registerTimingControl,reset_,rwAddr0,rwclk0,wData0,wEn0_,rData0); + /*NAME: mmsx_isp_isp_ram_wrapper_sw0x168x320 */ + input [15:0] GC_CONTROL; + input cEn0_; + input [31:0] mcReg_registerTimingControl; + input reset_; + input [9-1:0] rwAddr0; + input rwclk0; + input [168-1:0] wData0; + input wEn0_; + output [168-1:0] rData0; + wire [168-1:0] rData0; + `ifdef FPGA + reg [71:0] fpgaWData_0_0; + wire [71:0] fpgaRData_0_0; + always @(wData0[71:0]) + fpgaWData_0_0 = 72'd0 | wData0[71:0]; + wire [71:0] fpgaRData_0_0_0; + assign rData0[71:0] = fpgaRData_0_0_0[72-1:0]; + wire wEn0Stack_0_0_0_ = wEn0_; + `ifdef FPGA_ALTERA + FPGA_ALTERA_RF2P512W72B ram_0_0_0 ( + .address_a ({rwAddr0}), + .address_b ({rwAddr0}), + .clock_a (rwclk0), + .clock_b (rwclk0), + .data_a (72'b0), + .data_b (fpgaWData_0_0[71:0]), + .rden_a (~cEn0_ && (cEn0_|wEn0_)), + .rden_b (1'b0), + .wren_a (1'b0), + .wren_b (~(cEn0_|wEn0_)), + .q_a (fpgaRData_0_0_0[71:0]), + .q_b ()); + `else + FPGA_RF2P512W72B ram_0_0_0 ( + .DOA (fpgaRData_0_0_0[63:0]), + .DOPA (fpgaRData_0_0_0[71:64]), + .DOB (), + .DOPB (), + .ADDRA ({rwAddr0}), + .DIA (64'd0), + .DIPA (8'd0), + .ENA (~cEn0_ && (cEn0_|wEn0_)), + .CLKA (rwclk0), + .SSRA (1'b0), + .WEA (2'd0), + .ADDRB ({rwAddr0}), + .DIB (fpgaWData_0_0[63:0]), + .DIPB (fpgaWData_0_0[71:64]), + .ENB (~(cEn0_|wEn0_)), + .CLKB (rwclk0), + .SSRB (1'b0), + .WEB ({~(cEn0_|wEn0_),~(cEn0_|wEn0_)})); + `endif + reg [71:0] fpgaWData_0_1; + wire [71:0] fpgaRData_0_1; + always @(wData0[143:72]) + fpgaWData_0_1 = 72'd0 | wData0[143:72]; + wire [71:0] fpgaRData_0_1_0; + assign rData0[143:72] = fpgaRData_0_1_0[72-1:0]; + wire wEn0Stack_0_1_0_ = wEn0_; + `ifdef FPGA_ALTERA + FPGA_ALTERA_RF2P512W72B ram_0_1_0 ( + .address_a ({rwAddr0}), + .address_b ({rwAddr0}), + .clock_a (rwclk0), + .clock_b (rwclk0), + .data_a (72'b0), + .data_b (fpgaWData_0_1[71:0]), + .rden_a (~cEn0_ && (cEn0_|wEn0_)), + .rden_b (1'b0), + .wren_a (1'b0), + .wren_b (~(cEn0_|wEn0_)), + .q_a (fpgaRData_0_1_0[71:0]), + .q_b ()); + `else + FPGA_RF2P512W72B ram_0_1_0 ( + .DOA (fpgaRData_0_1_0[63:0]), + .DOPA (fpgaRData_0_1_0[71:64]), + .DOB (), + .DOPB (), + .ADDRA ({rwAddr0}), + .DIA (64'd0), + .DIPA (8'd0), + .ENA (~cEn0_ && (cEn0_|wEn0_)), + .CLKA (rwclk0), + .SSRA (1'b0), + .WEA (2'd0), + .ADDRB ({rwAddr0}), + .DIB (fpgaWData_0_1[63:0]), + .DIPB (fpgaWData_0_1[71:64]), + .ENB (~(cEn0_|wEn0_)), + .CLKB (rwclk0), + .SSRB (1'b0), + .WEB ({~(cEn0_|wEn0_),~(cEn0_|wEn0_)})); + `endif + reg [71:0] fpgaWData_0_2; + wire [71:0] fpgaRData_0_2; + always @(wData0[167:144]) + fpgaWData_0_2 = 72'd0 | wData0[167:144]; + wire [71:0] fpgaRData_0_2_0; + assign rData0[167:144] = fpgaRData_0_2_0[24-1:0]; + wire wEn0Stack_0_2_0_ = wEn0_; + `ifdef FPGA_ALTERA + FPGA_ALTERA_RF2P512W72B ram_0_2_0 ( + .address_a ({rwAddr0}), + .address_b ({rwAddr0}), + .clock_a (rwclk0), + .clock_b (rwclk0), + .data_a (72'b0), + .data_b (fpgaWData_0_2[71:0]), + .rden_a (~cEn0_ && (cEn0_|wEn0_)), + .rden_b (1'b0), + .wren_a (1'b0), + .wren_b (~(cEn0_|wEn0_)), + .q_a (fpgaRData_0_2_0[71:0]), + .q_b ()); + `else + FPGA_RF2P512W72B ram_0_2_0 ( + .DOA (fpgaRData_0_2_0[63:0]), + .DOPA (fpgaRData_0_2_0[71:64]), + .DOB (), + .DOPB (), + .ADDRA ({rwAddr0}), + .DIA (64'd0), + .DIPA (8'd0), + .ENA (~cEn0_ && (cEn0_|wEn0_)), + .CLKA (rwclk0), + .SSRA (1'b0), + .WEA (2'd0), + .ADDRB ({rwAddr0}), + .DIB (fpgaWData_0_2[63:0]), + .DIPB (fpgaWData_0_2[71:64]), + .ENB (~(cEn0_|wEn0_)), + .CLKB (rwclk0), + .SSRB (1'b0), + .WEB ({~(cEn0_|wEn0_),~(cEn0_|wEn0_)})); + `endif + `else + `ifdef OLD_MEM_MODEL + `else + `ifdef AQ_TSMC28HPM_RAM_MODEL + wire [9-1:0] BM_AA = {9{1'b0}}; + wire [9-1:0] BM_AB = {9{1'b0}}; + wire BM_CENA = 1'b0; + wire BM_CENB = 1'b0; + wire BM_BENA = 1'b0; + wire [168-1:0] BM_DB = {168{1'b0}}; + wire BM_EN = 1'b0; + wire [1-1:0] BM_WENB = {1{1'b1}}; + wire BIST = (BM_EN & BM_BENA); + wire enableClock = ~(cEn0_) | GC_CONTROL[4]; + `ifdef CG_IN_RAM + wire rwclk0En = rwclk0; + `else + wire rwclk0En; + vsisp_GC_CG_MOD GC_CG_RW(.enable(enableClock), .ck_in(rwclk0), .ck_out(rwclk0En), .test(GC_CONTROL[0])); + `endif + wire [84-1:0] ramRData0; + reg [84-1:0] ramWData0; + always @(wData0[83:0]) begin + ramWData0[84-1:0] = wData0[83:0]; + end + assign rData0[83:0] = ramRData0[84-1:0]; + RF1P320W84B2S ram0 ( + .Q(ramRData0), + .CLK(rwclk0En), + .WEB(wEn0_), + .CEB(cEn0_), + .BWEB({84{1'b0}}), + .A(rwAddr0), + .D(ramWData0), + .SLP(mcReg_registerTimingControl[0]), + .SD(mcReg_registerTimingControl[20]), + .AM(BM_AA), + .DM({BM_DB[83:0]}), + .BWEBM({84{1'b0}}), + .WEBM(BM_CENB), + .CEBM(BM_CENA), + .BIST(BIST), + .TURBO(1'b1), + .RTSEL(2'b01)); + wire [84-1:0] ramRData1; + reg [84-1:0] ramWData1; + always @(wData0[167:84]) begin + ramWData1[84-1:0] = wData0[167:84]; + end + assign rData0[167:84] = ramRData1[84-1:0]; + RF1P320W84B2S ram1 ( + .Q(ramRData1), + .CLK(rwclk0En), + .WEB(wEn0_), + .CEB(cEn0_), + .BWEB({84{1'b0}}), + .A(rwAddr0), + .D(ramWData1), + .SLP(mcReg_registerTimingControl[0]), + .SD(mcReg_registerTimingControl[20]), + .AM(BM_AA), + .DM({BM_DB[167:84]}), + .BWEBM({84{1'b0}}), + .WEBM(BM_CENB), + .CEBM(BM_CENA), + .BIST(BIST), + .TURBO(1'b1), + .RTSEL(2'b01)); + `else + `ifdef AQ_SEC14LPP_RAM_MODEL + wire enableClock = ~(cEn0_) | GC_CONTROL[4]; + `ifdef CG_IN_RAM + wire rwclk0En = rwclk0; + `else + wire rwclk0En; + vsisp_GC_CG_MOD GC_CG_RW(.enable(enableClock), .ck_in(rwclk0), .ck_out(rwclk0En), .test(GC_CONTROL[0])); + `endif + wire [84-1:0] ramRData0; + reg [84-1:0] ramWData0; + always @(wData0[83:0]) begin + ramWData0[84-1:0] = wData0[83:0]; + end + assign rData0[83:0] = ramRData0[84-1:0]; + RF1P320W84B2M1BK0S0HD0WM ram0 ( + .Q(ramRData0), + .CLK(rwclk0En), + .CEN(cEn0_), + .GWEN(wEn0_), + .A(rwAddr0), + .D(ramWData0), + .STOV(1'b0), + .EMA(3'b010), + .EMAW(2'b01), + .EMAS(1'b0), + .RET1N(1'b1)); + wire [84-1:0] ramRData1; + reg [84-1:0] ramWData1; + always @(wData0[167:84]) begin + ramWData1[84-1:0] = wData0[167:84]; + end + assign rData0[167:84] = ramRData1[84-1:0]; + RF1P320W84B2M1BK0S0HD0WM ram1 ( + .Q(ramRData1), + .CLK(rwclk0En), + .CEN(cEn0_), + .GWEN(wEn0_), + .A(rwAddr0), + .D(ramWData1), + .STOV(1'b0), + .EMA(3'b010), + .EMAW(2'b01), + .EMAS(1'b0), + .RET1N(1'b1)); + `else + `ifdef AQ_TSMC7FF_RAM_MODEL + wire enableClock = ~(cEn0_) | GC_CONTROL[4]; + `ifdef CG_IN_RAM + wire rwclk0En = rwclk0; + `else + wire rwclk0En; + vsisp_GC_CG_MOD GC_CG_RW(.enable(enableClock), .ck_in(rwclk0), .ck_out(rwclk0En), .test(GC_CONTROL[0])); + `endif + wire [56-1:0] ramRData0; + reg [56-1:0] ramWData0; + always @(wData0[55:0]) begin + ramWData0[56-1:0] = wData0[55:0]; + end + assign rData0[55:0] = ramRData0[56-1:0]; + RF1P320W56B4MNSEG0S0HD0WM ram0 ( + .CLK(rwclk0En), + .Q(ramRData0), + .CEB(cEn0_), + .WEB(wEn0_), + .A(rwAddr0), + .D(ramWData0), + .SD(mcReg_registerTimingControl[20]), + .DSLP(mcReg_registerTimingControl[21]), + .DSLPLV(1'b0), + .PUDELAY_DSLP(), + .PUDELAY_SD(), + .RTSEL(2'b10), + .WTSEL(2'b01), + .DFTBYP(1'b0), + .SE(1'b0), + .SIC(1'b0), + .SID(2'b00), + .SOC(), + .SOD()); + wire [56-1:0] ramRData1; + reg [56-1:0] ramWData1; + always @(wData0[111:56]) begin + ramWData1[56-1:0] = wData0[111:56]; + end + assign rData0[111:56] = ramRData1[56-1:0]; + RF1P320W56B4MNSEG0S0HD0WM ram1 ( + .CLK(rwclk0En), + .Q(ramRData1), + .CEB(cEn0_), + .WEB(wEn0_), + .A(rwAddr0), + .D(ramWData1), + .SD(mcReg_registerTimingControl[20]), + .DSLP(mcReg_registerTimingControl[21]), + .DSLPLV(1'b0), + .PUDELAY_DSLP(), + .PUDELAY_SD(), + .RTSEL(2'b10), + .WTSEL(2'b01), + .DFTBYP(1'b0), + .SE(1'b0), + .SIC(1'b0), + .SID(2'b00), + .SOC(), + .SOD()); + wire [56-1:0] ramRData2; + reg [56-1:0] ramWData2; + always @(wData0[167:112]) begin + ramWData2[56-1:0] = wData0[167:112]; + end + assign rData0[167:112] = ramRData2[56-1:0]; + RF1P320W56B4MNSEG0S0HD0WM ram2 ( + .CLK(rwclk0En), + .Q(ramRData2), + .CEB(cEn0_), + .WEB(wEn0_), + .A(rwAddr0), + .D(ramWData2), + .SD(mcReg_registerTimingControl[20]), + .DSLP(mcReg_registerTimingControl[21]), + .DSLPLV(1'b0), + .PUDELAY_DSLP(), + .PUDELAY_SD(), + .RTSEL(2'b10), + .WTSEL(2'b01), + .DFTBYP(1'b0), + .SE(1'b0), + .SIC(1'b0), + .SID(2'b00), + .SOC(), + .SOD()); + `else + `ifdef AQ_TSMC12FFC_RAM_MODEL + wire enableClock = ~(cEn0_) | GC_CONTROL[4]; + `ifdef CG_IN_RAM + wire rwclk0En = rwclk0; + `else + wire rwclk0En; + vsisp_GC_CG_MOD GC_CG_RW(.enable(enableClock), .ck_in(rwclk0), .ck_out(rwclk0En), .test(GC_CONTROL[0])); + `endif + wire [168-1:0] ramRData0; + reg [168-1:0] ramWData0; + always @(wData0[167:0]) begin + ramWData0[168-1:0] = wData0[167:0]; + end + assign rData0[167:0] = ramRData0[168-1:0]; + RF1P320W168B1MNSEG0S0HD0WM ram0 ( + .CLK(rwclk0En), + .Q(ramRData0), + .CEB(cEn0_), + .WEB(wEn0_), + .A(rwAddr0), + .D(ramWData0), + .RTSEL(2'b01), + .WTSEL(2'b01)); + `else + wire enableClock = ~(cEn0_) | GC_CONTROL[4]; + `ifdef CG_IN_RAM + wire rwclk0En = rwclk0; + `else + wire rwclk0En; + vsisp_GC_CG_MOD GC_CG_RW(.enable(enableClock), .ck_in(rwclk0), .ck_out(rwclk0En), .test(GC_CONTROL[0])); + `endif + wire [168-1:0] ramRData0; + reg [168-1:0] ramWData0; + always @(wData0[167:0]) begin + ramWData0[168-1:0] = wData0[167:0]; + end + assign rData0[167:0] = ramRData0[168-1:0]; + vsisp_RAM1P320W168B_SS ram0 ( + .Q(ramRData0), + .CLK(rwclk0En), + .CEB(cEn0_), + .A(rwAddr0), + .WEB(wEn0_), + .BWEB({168{1'b0}}), + .D(ramWData0), + .CLKEN(enableClock), + .TESTEN(GC_CONTROL[0])); + `endif + `endif + `endif + `endif + `endif + `endif + `ifdef VIVANTE_CHECK_RAM_USAGE + `ifdef VIVANTE_SIM_END + reg [1-1:0] writeHappened; + reg readHappened; + initial begin + writeHappened = 1 'd0; + readHappened = 1'd0; + end + always @(posedge rwclk0) begin + readHappened <= (readHappened | (~cEn0_ & wEn0_)); + end + always @(posedge rwclk0) begin + if(~wEn0_ & ~cEn0_) begin + writeHappened <= 1'b1; + end + end + initial begin + @`VIVANTE_SIM_END; + if(&{readHappened,writeHappened}) begin + $display ("RAM USAGE: vsisp_isp_isp_ram_wrapper at %m fully exercised."); + end else begin + $display ("RAM USAGE: vsisp_isp_isp_ram_wrapper at %m not fully exercised."); + end + end + `endif + `endif + `ifdef ASSERT_ON_RAM + assert_never wrong_rwaddr0 (rwclk0, reset_, (~cEn0_ & (rwAddr0 > 320-1))); + assert_never_unknown #(0, 9, 0, "address is unknown") address_unknown0(rwclk0, reset_, ~cEn0_, rwAddr0); + assert_never_unknown #(0, 1, 0, "ram enable is unknown") ram_enable_unknown0(rwclk0, reset_, 1'b1, cEn0_); + assert_never_unknown #(0, 32, 0, "config signal is unknown") config_unknown_rw0(rwclk0, reset_, 1'b1, mcReg_registerTimingControl[32-1:0]); + assert_never_unknown #(0, 1, 0, "control signal is unknown") control_unknown_rw0(rwclk0, reset_, 1'b1, GC_CONTROL[4]); + `endif + `ifdef VIVANTE_CHECK_RAM_USAGE2 + `ifdef VIVANTE_RAM_MONITOR_END + parameter rAddr0Num = 8-1; + reg [rAddr0Num:0] rAddr0_r; + reg [31:0] rAddr0Cnt[0:rAddr0Num]; + parameter wAddr0Num = 8-1; + reg [wAddr0Num:0] wAddr0_r; + reg [31:0] wAddr0Cnt[0:wAddr0Num]; + parameter wData0Num = 29-1; + reg [wData0Num:0] wData0_r; + reg [31:0] wData0Cnt[0:wData0Num]; + parameter rData0Num = 29-1; + reg [rData0Num:0] rData0_r; + reg [31:0] rData0Cnt[0:rData0Num]; + initial + begin + #1; + @`VIVANTE_RAM_MONITOR_END + begin + integer i; + for(i=0;i<=rAddr0Num;i=i+1) + begin + $gethierachy(3, i, rAddr0Cnt[i]); + end + for(i=0;i<=wAddr0Num;i=i+1) + begin + $gethierachy(4, i, wAddr0Cnt[i]); + end + for(i=0;i<=wData0Num;i=i+1) + begin + $gethierachy(2, i, wData0Cnt[i]); + end + for(i=0;i<=rData0Num;i=i+1) + begin + $gethierachy(1, i, rData0Cnt[i]); + end + end + end + always @(posedge rwclk0 or negedge reset_) + begin + if(!reset_) + begin + rAddr0_r = 'b0; + rData0_r = 'b0; + end + else if(wEn0_&!cEn0_) + begin + rAddr0_r = rwAddr0; + rData0_r = rData0; + end + end + always @(posedge rwclk0 or negedge reset_) + begin + if(!reset_) + begin + integer i; + for(i=0;i<=rAddr0Num;i=i+1) + begin + rAddr0Cnt[i] = 'b0; + end + end + else if(wEn0_&!cEn0_) + begin + integer i; + for(i=0;i<=rAddr0Num;i=i+1) + begin + if(rAddr0_r[i]^rwAddr0[i]) + begin + rAddr0Cnt[i] = rAddr0Cnt[i] + 1; + end + end + end + end + always @(posedge rwclk0 or negedge reset_) + begin + if(!reset_) + begin + integer i; + for(i=0;i<=rData0Num;i=i+1) + begin + rData0Cnt[i] = 'b0; + end + end + else if(wEn0_&!cEn0_) + begin + integer i; + for(i=0;i<=rData0Num;i=i+1) + begin + if(rData0_r[i]^rData0[i]) + begin + rData0Cnt[i] = rData0Cnt[i] + 1; + end + end + end + end + always @(posedge rwclk0 or negedge reset_) + begin + if(!reset_) + begin + wAddr0_r = 'b0; + wData0_r = 'b0; + end + else if((!wEn0_)&(!cEn0_)) + begin + wAddr0_r = rwAddr0; + wData0_r = wData0; + end + end + always @(posedge rwclk0 or negedge reset_) + begin + if(!reset_) + begin + integer i; + for(i=0;i<=wAddr0Num;i=i+1) + begin + wAddr0Cnt[i] = 'b0; + end + end + else if((!wEn0_)&(!cEn0_)) + begin + integer i; + for(i=0;i<=wAddr0Num;i=i+1) + begin + if(wAddr0_r[i]^rwAddr0[i]) + begin + wAddr0Cnt[i] = wAddr0Cnt[i] + 1; + end + end + end + end + always @(posedge rwclk0 or negedge reset_) + begin + if(!reset_) + begin + integer i; + for(i=0;i<=wData0Num;i=i+1) + begin + wData0Cnt[i] = 'b0; + end + end + else if((!wEn0_)&(!cEn0_)) + begin + integer i; + for(i=0;i<=wData0Num;i=i+1) + begin + if(wData0_r[i]^wData0[i]) + begin + wData0Cnt[i] = wData0Cnt[i] + 1; + end + end + end + end + `endif + `endif +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_line_mem_if.v b/ispyocto/rtl/ispyocto/vsisp_isp_line_mem_if.v new file mode 100644 index 0000000..1a1cecf --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_isp_line_mem_if.v
@@ -0,0 +1,480 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_isp_line_mem_if + ( + clk, + reset_n, + soft_rst, + in_val, + in_h_end, + in_v_end, + in_data, + in_ack, + regs_bayer_pat, + out_val, + out_h_end, + out_v_end, + out_data_1t, + out_data_m2, + out_data_m3, + out_data_m4, + out_data_m5, + out_data_m6, + out_data_7b, + out_ack, + memif_h_end, + memif_v_end, + memif_val, + memif_ack, + adr, + we_n, + cs_n, + wr_data, + rd_data); +`include "vsisp_isp.vh" +`include "vsisp_ram_sizes.vh" + input clk; + input reset_n; + input soft_rst; + input in_val; + input in_h_end; + input in_v_end; + input [c_dw_si-1:0] in_data; + output in_ack; + input [1:0] regs_bayer_pat; + output out_val; + output out_h_end; + output out_v_end; + output [c_dw_si-1:0] out_data_1t; + output [c_dw_si-1:0] out_data_m2; + output [c_dw_si-1:0] out_data_m3; + output [c_dw_si-1:0] out_data_m4; + output [c_dw_si-1:0] out_data_m5; + output [c_dw_si-1:0] out_data_m6; + output [c_dw_si-1:0] out_data_7b; + input out_ack; + output memif_h_end; + output memif_v_end; + output memif_val; + output memif_ack; + output [c_aw_dem_mem-1:0] adr; + output we_n; + output cs_n; + output [c_dw_dem_mem-1:0] wr_data; + input [c_dw_dem_mem-1:0] rd_data; + reg viv_s0; + reg [1:0] viv_s1; + reg viv_s2; + reg viv_s3; + reg viv_s4; + reg [c_dw_dem_mem-1:0] viv_s5; + reg [c_dw_si-1:0] viv_s6; + reg [c_aw_dem_mem-1:0] viv_s7; + reg [c_aw_dem_mem-1:0] viv_s8; + reg [2:0] viv_s9; + reg [3:0] viv_s10; + reg [c_aw_dem_mem-1:0] viv_s11; + reg [(7*c_dw_si)-1:0] viv_s12; + reg out_h_end; + reg out_v_end; + reg viv_s13; + reg we_n; + wire cs_n; + reg [c_aw_dem_mem-1:0] adr; + reg memif_val; + wire memif_h_end; + wire memif_v_end; + wire [(7*c_dw_si)-1:0] viv_s14; + wire [c_dw_si-1:0] viv_s15; + wire [c_dw_si-1:0] viv_s16; + wire [c_dw_si-1:0] viv_s17; + wire [c_dw_si-1:0] viv_s18; + wire [c_dw_si-1:0] viv_s19; + wire [c_dw_si-1:0] viv_s20; + wire [c_dw_si-1:0] viv_s21; + wire [c_dw_si-1:0] viv_s22; + wire [c_dw_si-1:0] viv_s23; + wire [c_dw_si-1:0] viv_s24; + wire [c_dw_si-1:0] viv_s25; + wire [c_dw_si-1:0] viv_s26; + wire [c_dw_si-1:0] viv_s27; + wire [c_dw_si-1:0] viv_s28; + reg [c_dw_si-1:0] viv_s29; + reg [c_dw_si-1:0] viv_s30; + reg [c_dw_si-1:0] viv_s31; + reg [c_dw_si-1:0] viv_s32; + reg [c_dw_si-1:0] viv_s33; + reg [c_dw_si-1:0] viv_s34; + reg [c_dw_si-1:0] viv_s35; + reg [c_dw_si-1:0] viv_s36; + reg [c_dw_si-1:0] viv_s37; + reg [c_dw_si-1:0] viv_s38; + reg [c_dw_si-1:0] viv_s39; + reg [c_dw_si-1:0] viv_s40; + wire [c_dw_si-1:0] viv_s41; + wire [c_dw_si-1:0] viv_s42; + wire [c_dw_si-1:0] viv_s43; + reg in_ack; + reg [c_dw_dem_mem-1:0] wr_data; + reg viv_s44; + wire viv_s45; + wire viv_s46; + wire viv_s47; + wire viv_s48; + wire viv_s49; + wire viv_s50; + wire viv_s51; + wire memif_ack; + assign viv_s45 = viv_s10 < c_line_delay; + assign viv_s46 = viv_s10 == c_line_delay; + assign viv_s47 = viv_s10 == c_line_delay; + assign viv_s48 = viv_s10 > c_line_delay; + assign viv_s49 = viv_s7 == viv_s11; + assign viv_s50 = (viv_s45 || viv_s47) ? in_h_end : + viv_s49 && (viv_s9 == c_odd_wr); + always @(posedge clk or negedge reset_n) begin + if (reset_n == 1'b0) begin + viv_s0 <= 1'b0; + viv_s1 <= 2'd0; + end else begin + if (soft_rst || (memif_v_end && memif_h_end && memif_val)) begin + viv_s0 <= 0; + end else if (in_val && in_ack) begin + viv_s0 <= 1; + end + if (~viv_s0) + viv_s1 <= regs_bayer_pat; + end + end + always @(posedge clk or negedge reset_n) begin + if (reset_n == 1'b0) begin + viv_s2 <= 0; + viv_s3 <= 0; + end else begin + if (~viv_s44 && ~viv_s0) begin + viv_s2 <= ~viv_s1[1]; + viv_s3 <= viv_s1[1] == viv_s1[0]; + end else if (viv_s44) begin + if (viv_s50) begin + if (memif_v_end) begin + viv_s2 <= ~viv_s1[1]; + viv_s3 <= viv_s1[1] == viv_s1[0]; + end else begin + viv_s2 <= ~viv_s2 ; + viv_s3 <= ~viv_s2 == viv_s1[0]; + end + end else begin + viv_s3 <= ~viv_s3; + end + end + end + end + always @(posedge clk or negedge reset_n) begin + if (reset_n == 1'b0) begin + viv_s9 <= c_reset; + viv_s10 <= 0; + viv_s4 <= 1; + end else begin + if (soft_rst) begin + viv_s9 <= c_reset; + end else begin + case (viv_s9) + c_rd_p0 : + viv_s9 <= c_rd_p1; + c_rd_p1 : + if (viv_s44) begin + viv_s9 <= c_odd_wr; + end else begin + viv_s9 <= c_even; + end + c_even : + if (viv_s44) begin + viv_s9 <= c_odd_wr; + end + c_odd_wr : begin + if (viv_s44) begin + if (viv_s50) begin + if (memif_v_end) begin + viv_s9 <= c_even; + viv_s4 <= 1; + viv_s10 <= 0; + end else begin + viv_s9 <= c_rd_p0; + viv_s4 <= 0; + if (in_v_end || ~viv_s46) + viv_s10 <= viv_s10 +1; + end + end else begin + viv_s9 <= c_even; + end + end + end + default : begin + viv_s9 <= c_even; + viv_s4 <= 1'b1; + viv_s10 <= 0; + end + endcase + end + end + end + always @(posedge clk or negedge reset_n) begin + if (reset_n == 1'b0) begin + viv_s7 <= {c_aw_dem_mem{1'b0}}; + viv_s8 <= {c_aw_dem_mem{1'b0}}; + viv_s6 <= {c_dw_si{1'b0}}; + viv_s5 <= {c_dw_dem_mem{1'b0}}; + viv_s11 <= {c_aw_dem_mem{1'b0}}; + end else begin + if (~soft_rst) begin + case (viv_s9) + c_rd_p0 : + viv_s7 <= {{c_aw_dem_mem-1{1'b0}},1'b1}; + c_rd_p1 : begin + viv_s5 <= rd_data; + if (viv_s44) begin + viv_s6 <= viv_s30; + end + end + c_even : + if (viv_s44) begin + viv_s6 <= viv_s30; + end + c_odd_wr : + if (viv_s44) begin + if (viv_s50) begin + viv_s5 <= {c_dw_dem_mem{1'b0}}; + viv_s8 <= {c_aw_dem_mem{1'b0}}; + viv_s7 <= {c_aw_dem_mem{1'b0}}; + if (memif_v_end) + viv_s11 <= {c_aw_dem_mem{1'b0}}; + else if (in_v_end) + viv_s11 <= viv_s7; + end else begin + viv_s8 <= viv_s8 + 1'b1; + viv_s7 <= viv_s7 + 1'b1; + if (viv_s10 == 4'h0) + viv_s5 <= {c_dw_dem_mem{1'b0}}; + else + viv_s5 <= rd_data; + end + end + default : begin + viv_s7 <= {c_aw_dem_mem{1'b0}}; + viv_s8 <= {c_aw_dem_mem{1'b0}}; + end + endcase + end + end + end + assign cs_n = (viv_s9 == c_reset); + always @(*) begin + case (viv_s9) + c_reset : begin + adr = {c_aw_dem_mem{1'b0}}; + we_n = 1'b1; + end + c_odd_wr : + if (viv_s10 < c_last_line) begin + adr = (viv_s44) ? viv_s8 : viv_s7; + we_n = ~viv_s44; + end else begin + adr = viv_s7; + we_n = 1'b1; + end + default : begin + adr = viv_s7; + we_n = 1'b1; + end + endcase + end + always @(viv_s9 or viv_s51 or viv_s45 or viv_s47) begin + case (viv_s9) + c_rd_p0 : + in_ack = 1'b0; + c_rd_p1 , + c_even , + c_odd_wr : + if (viv_s45) + in_ack = 1'b1; + else if (viv_s47) + in_ack = viv_s51; + else + in_ack = 1'b0; + default : + in_ack = 1'b1; + endcase + end + always @(*) begin + case (viv_s9) + c_reset, + c_rd_p0 : begin + memif_val = 1'b0; + viv_s44 = 1'b1; + end + default : + if (viv_s45) begin + memif_val = 1'b0; + viv_s44 = in_val; + end else if (viv_s47) begin + memif_val = in_val; + viv_s44 = in_val && memif_ack; + end else begin + memif_val = 1'b1; + viv_s44 = memif_ack; + end + endcase + end + assign memif_h_end = (viv_s9 == c_odd_wr) && ( + (viv_s47 && in_h_end ) || + (viv_s48 && viv_s49) ); + assign memif_v_end = viv_s10 == c_last_line; + assign viv_s15 = viv_s5[(14*c_dw_si)-1 :13*c_dw_si]; + assign viv_s16 = viv_s5[(13*c_dw_si)-1 :12*c_dw_si]; + assign viv_s17 = viv_s5[(12*c_dw_si)-1 :11*c_dw_si]; + assign viv_s18 = viv_s5[(10*c_dw_si)-1 : 9*c_dw_si]; + assign viv_s19 = viv_s5[( 8*c_dw_si)-1 : 7*c_dw_si]; + assign viv_s20 = viv_s5[( 6*c_dw_si)-1 : 5*c_dw_si]; + assign viv_s21 = viv_s5[( 4*c_dw_si)-1 : 3*c_dw_si]; + assign viv_s22 = viv_s5[( 2*c_dw_si)-1 : 1*c_dw_si]; + assign viv_s23 = viv_s5[(11*c_dw_si)-1 :10*c_dw_si]; + assign viv_s24 = viv_s5[( 9*c_dw_si)-1 : 8*c_dw_si]; + assign viv_s25 = viv_s5[( 7*c_dw_si)-1 : 6*c_dw_si]; + assign viv_s26 = viv_s5[( 5*c_dw_si)-1 : 4*c_dw_si]; + assign viv_s27 = viv_s5[( 3*c_dw_si)-1 : 2*c_dw_si]; + assign viv_s28 = viv_s5[( 1*c_dw_si)-1 : 0 ]; + assign viv_s42 = viv_s23; + assign viv_s41 = viv_s17; + assign viv_s43 = viv_s16; + always @(*) begin + wr_data[(14*c_dw_si)-1 : 13*c_dw_si] = viv_s43; + wr_data[(12*c_dw_si)-1 : 10*c_dw_si] = {viv_s18, viv_s24}; + wr_data[( 8*c_dw_si)-1 : 6*c_dw_si] = {viv_s20, viv_s26}; + wr_data[( 4*c_dw_si)-1 : 2*c_dw_si] = {viv_s22, viv_s28}; + wr_data[( 2*c_dw_si)-1 : 0] = {viv_s6, viv_s29}; + if (viv_s3) + wr_data[(13*c_dw_si)-1 :12*c_dw_si] = viv_s42; + else + wr_data[(13*c_dw_si)-1 :12*c_dw_si] = viv_s41; + if (viv_s10 > 4'h1) + wr_data[(10*c_dw_si)-1 : 8*c_dw_si] = {viv_s19, viv_s25}; + else + wr_data[(10*c_dw_si)-1 : 8*c_dw_si] = {viv_s6, viv_s29}; + if (viv_s10 > 4'h1) + wr_data[(6*c_dw_si)-1 : 4*c_dw_si] = {viv_s21, viv_s27}; + else + wr_data[(6*c_dw_si)-1 : 4*c_dw_si] = {viv_s6, viv_s29}; + end + always @(*) begin + if (viv_s4) begin + viv_s38 = {c_dw_si{1'b0}}; + viv_s37 = {c_dw_si{1'b0}}; + viv_s36 = {c_dw_si{1'b0}}; + viv_s35 = {c_dw_si{1'b0}}; + viv_s34 = {c_dw_si{1'b0}}; + viv_s33 = {c_dw_si{1'b0}}; + viv_s32 = {c_dw_si{1'b0}}; + viv_s31 = {c_dw_si{1'b0}}; + end else begin + case (viv_s9) + c_rd_p1 : begin + viv_s38 = rd_data[(14*c_dw_si)-1 :13*c_dw_si]; + viv_s37 = rd_data[(13*c_dw_si)-1 :12*c_dw_si]; + viv_s36 = rd_data[(12*c_dw_si)-1 :11*c_dw_si]; + viv_s35 = rd_data[(10*c_dw_si)-1 : 9*c_dw_si]; + viv_s34 = rd_data[( 8*c_dw_si)-1 : 7*c_dw_si]; + viv_s33 = rd_data[( 6*c_dw_si)-1 : 5*c_dw_si]; + viv_s32 = rd_data[( 4*c_dw_si)-1 : 3*c_dw_si]; + viv_s31 = rd_data[( 2*c_dw_si)-1 : 1*c_dw_si]; + end + c_even : begin + viv_s38 = viv_s15; + viv_s37 = viv_s16; + viv_s36 = viv_s17; + viv_s35 = viv_s18; + viv_s34 = viv_s19; + viv_s33 = viv_s20; + viv_s32 = viv_s21; + viv_s31 = viv_s22; + end + default : begin + viv_s38 = viv_s15; + viv_s37 = viv_s16; + viv_s36 = viv_s23; + viv_s35 = viv_s24; + viv_s34 = viv_s25; + viv_s33 = viv_s26; + viv_s32 = viv_s27; + viv_s31 = viv_s28; + end + endcase + end + end + always @(*) begin + if (viv_s48) begin + viv_s30 = viv_s32; + viv_s29 = viv_s27; + end else begin + viv_s30 = in_data; + viv_s29 = in_data; + end + end + always @(*) begin + if (viv_s3) begin + viv_s40 = viv_s38; + viv_s39 = viv_s30; + end else begin + viv_s40 = viv_s37; + viv_s39 = viv_s31; + end + end + assign viv_s51 = out_ack || (~viv_s13); + assign memif_ack = viv_s51; + assign out_val = viv_s13; + assign viv_s14 = {viv_s40, viv_s36, viv_s35, viv_s34, viv_s33, viv_s32, viv_s39}; + always @(posedge clk or negedge reset_n) begin + if (reset_n == 1'b0) begin + viv_s13 <= 1'b0; + out_h_end <= 1'b0; + out_v_end <= 1'b0; + viv_s12 <= {7*c_dw_si{1'b0}}; + end else if (soft_rst) begin + viv_s13 <= 1'b0; + out_h_end <= 1'b0; + out_v_end <= 1'b0; + end else if (viv_s51) begin + viv_s13 <= memif_val; + out_h_end <= memif_h_end; + out_v_end <= memif_v_end; + viv_s12 <= viv_s14; + end + end + assign {out_data_7b, + out_data_m6, + out_data_m5, + out_data_m4, + out_data_m3, + out_data_m2, + out_data_1t} = viv_s12; +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_miv1_mp_sramy_wrapper.v b/ispyocto/rtl/ispyocto/vsisp_isp_miv1_mp_sramy_wrapper.v new file mode 100644 index 0000000..928614e --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_isp_miv1_mp_sramy_wrapper.v
@@ -0,0 +1,424 @@ +//**************************************************************************** +// +// Copyright 2023 Vivante Corp. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_isp_miv1_mp_sramy_wrapper(GC_CONTROL,cEn0_,mcReg_registerTimingControl,reset_,rwAddr0,rwclk0,wData0,wEn0_,rData0); + /*NAME: mmsx_isp_miv1_mp_sramy_wrapper_sw0x66x80 */ + input [15:0] GC_CONTROL; + input cEn0_; + input [31:0] mcReg_registerTimingControl; + input reset_; + input [7-1:0] rwAddr0; + input rwclk0; + input [66-1:0] wData0; + input wEn0_; + output [66-1:0] rData0; + wire [66-1:0] rData0; + `ifdef FPGA + reg [71:0] fpgaWData_0_0; + wire [71:0] fpgaRData_0_0; + always @(wData0[65:0]) + fpgaWData_0_0 = 72'd0 | wData0[65:0]; + wire [71:0] fpgaRData_0_0_0; + assign rData0[65:0] = fpgaRData_0_0_0[66-1:0]; + wire wEn0Stack_0_0_0_ = wEn0_; + `ifdef FPGA_ALTERA + FPGA_ALTERA_RF2P512W72B ram_0_0_0 ( + .address_a ({2'd0,rwAddr0}), + .address_b ({2'd0,rwAddr0}), + .clock_a (rwclk0), + .clock_b (rwclk0), + .data_a (72'b0), + .data_b (fpgaWData_0_0[71:0]), + .rden_a (~cEn0_ && (cEn0_|wEn0_)), + .rden_b (1'b0), + .wren_a (1'b0), + .wren_b (~(cEn0_|wEn0_)), + .q_a (fpgaRData_0_0_0[71:0]), + .q_b ()); + `else + FPGA_RF2P512W72B ram_0_0_0 ( + .DOA (fpgaRData_0_0_0[63:0]), + .DOPA (fpgaRData_0_0_0[71:64]), + .DOB (), + .DOPB (), + .ADDRA ({2'd0,rwAddr0}), + .DIA (64'd0), + .DIPA (8'd0), + .ENA (~cEn0_ && (cEn0_|wEn0_)), + .CLKA (rwclk0), + .SSRA (1'b0), + .WEA (2'd0), + .ADDRB ({2'd0,rwAddr0}), + .DIB (fpgaWData_0_0[63:0]), + .DIPB (fpgaWData_0_0[71:64]), + .ENB (~(cEn0_|wEn0_)), + .CLKB (rwclk0), + .SSRB (1'b0), + .WEB ({~(cEn0_|wEn0_),~(cEn0_|wEn0_)})); + `endif + `else + `ifdef OLD_MEM_MODEL + `else + `ifdef AQ_TSMC28HPM_RAM_MODEL + wire [7-1:0] BM_AA = {7{1'b0}}; + wire [7-1:0] BM_AB = {7{1'b0}}; + wire BM_CENA = 1'b0; + wire BM_CENB = 1'b0; + wire BM_BENA = 1'b0; + wire [66-1:0] BM_DB = {66{1'b0}}; + wire BM_EN = 1'b0; + wire [1-1:0] BM_WENB = {1{1'b1}}; + wire BIST = (BM_EN & BM_BENA); + wire enableClock = ~(cEn0_) | GC_CONTROL[4]; + `ifdef CG_IN_RAM + wire rwclk0En = rwclk0; + `else + wire rwclk0En; + vsisp_GC_CG_MOD GC_CG_RW(.enable(enableClock), .ck_in(rwclk0), .ck_out(rwclk0En), .test(GC_CONTROL[0])); + `endif + wire [66-1:0] ramRData0; + reg [66-1:0] ramWData0; + always @(wData0[65:0]) begin + ramWData0[66-1:0] = wData0[65:0]; + end + assign rData0[65:0] = ramRData0[66-1:0]; + RF1P80W66B4S ram0 ( + .Q(ramRData0), + .CLK(rwclk0En), + .WEB(wEn0_), + .CEB(cEn0_), + .BWEB({66{1'b0}}), + .A(rwAddr0), + .D(ramWData0), + .SLP(mcReg_registerTimingControl[0]), + .SD(mcReg_registerTimingControl[20]), + .AM(BM_AA), + .DM({BM_DB[65:0]}), + .BWEBM({66{1'b0}}), + .WEBM(BM_CENB), + .CEBM(BM_CENA), + .BIST(BIST), + .TURBO(1'b1), + .RTSEL(2'b01)); + `else + `ifdef AQ_SEC14LPP_RAM_MODEL + wire enableClock = ~(cEn0_) | GC_CONTROL[4]; + `ifdef CG_IN_RAM + wire rwclk0En = rwclk0; + `else + wire rwclk0En; + vsisp_GC_CG_MOD GC_CG_RW(.enable(enableClock), .ck_in(rwclk0), .ck_out(rwclk0En), .test(GC_CONTROL[0])); + `endif + wire [66-1:0] ramRData0; + reg [66-1:0] ramWData0; + always @(wData0[65:0]) begin + ramWData0[66-1:0] = wData0[65:0]; + end + assign rData0[65:0] = ramRData0[66-1:0]; + RF1P80W66B2M1BK0S0HD0WM ram0 ( + .Q(ramRData0), + .CLK(rwclk0En), + .CEN(cEn0_), + .GWEN(wEn0_), + .A(rwAddr0), + .D(ramWData0), + .STOV(1'b0), + .EMA(3'b010), + .EMAW(2'b01), + .EMAS(1'b0), + .RET1N(1'b1)); + `else + `ifdef AQ_TSMC7FF_RAM_MODEL + wire enableClock = ~(cEn0_) | GC_CONTROL[4]; + `ifdef CG_IN_RAM + wire rwclk0En = rwclk0; + `else + wire rwclk0En; + vsisp_GC_CG_MOD GC_CG_RW(.enable(enableClock), .ck_in(rwclk0), .ck_out(rwclk0En), .test(GC_CONTROL[0])); + `endif + wire [66-1:0] ramRData0; + reg [66-1:0] ramWData0; + always @(wData0[65:0]) begin + ramWData0[66-1:0] = wData0[65:0]; + end + assign rData0[65:0] = ramRData0[66-1:0]; + RF1P128W66B1MNSEG0S0HD0WM ram0 ( + .CLK(rwclk0En), + .Q(ramRData0), + .CEB(cEn0_), + .WEB(wEn0_), + .A(rwAddr0), + .D(ramWData0), + .SD(mcReg_registerTimingControl[20]), + .DSLP(mcReg_registerTimingControl[21]), + .DSLPLV(1'b0), + .PUDELAY_DSLP(), + .PUDELAY_SD(), + .RTSEL(2'b10), + .WTSEL(2'b01), + .DFTBYP(1'b0), + .SE(1'b0), + .SIC(1'b0), + .SID(2'b00), + .SOC(), + .SOD()); + `else + `ifdef AQ_TSMC12FFC_RAM_MODEL + wire enableClock = ~(cEn0_) | GC_CONTROL[4]; + `ifdef CG_IN_RAM + wire rwclk0En = rwclk0; + `else + wire rwclk0En; + vsisp_GC_CG_MOD GC_CG_RW(.enable(enableClock), .ck_in(rwclk0), .ck_out(rwclk0En), .test(GC_CONTROL[0])); + `endif + wire [66-1:0] ramRData0; + reg [66-1:0] ramWData0; + always @(wData0[65:0]) begin + ramWData0[66-1:0] = wData0[65:0]; + end + assign rData0[65:0] = ramRData0[66-1:0]; + RF1P80W66B1MNSEG0S0HD0WM ram0 ( + .CLK(rwclk0En), + .Q(ramRData0), + .CEB(cEn0_), + .WEB(wEn0_), + .A(rwAddr0), + .D(ramWData0), + .RTSEL(2'b01), + .WTSEL(2'b01)); + `else + wire enableClock = ~(cEn0_) | GC_CONTROL[4]; + `ifdef CG_IN_RAM + wire rwclk0En = rwclk0; + `else + wire rwclk0En; + vsisp_GC_CG_MOD GC_CG_RW(.enable(enableClock), .ck_in(rwclk0), .ck_out(rwclk0En), .test(GC_CONTROL[0])); + `endif + wire [66-1:0] ramRData0; + reg [66-1:0] ramWData0; + always @(wData0[65:0]) begin + ramWData0[66-1:0] = wData0[65:0]; + end + assign rData0[65:0] = ramRData0[66-1:0]; + vsisp_RAM1P80W66B_SS ram0 ( + .Q(ramRData0), + .CLK(rwclk0En), + .CEB(cEn0_), + .A(rwAddr0), + .WEB(wEn0_), + .BWEB({66{1'b0}}), + .D(ramWData0), + .CLKEN(enableClock), + .TESTEN(GC_CONTROL[0])); + `endif + `endif + `endif + `endif + `endif + `endif + `ifdef VIVANTE_CHECK_RAM_USAGE + `ifdef VIVANTE_SIM_END + reg [1-1:0] writeHappened; + reg readHappened; + initial begin + writeHappened = 1 'd0; + readHappened = 1'd0; + end + always @(posedge rwclk0) begin + readHappened <= (readHappened | (~cEn0_ & wEn0_)); + end + always @(posedge rwclk0) begin + if(~wEn0_ & ~cEn0_) begin + writeHappened <= 1'b1; + end + end + initial begin + @`VIVANTE_SIM_END; + if(&{readHappened,writeHappened}) begin + $display ("RAM USAGE: vsisp_isp_miv1_mp_sramy_wrapper at %m fully exercised."); + end else begin + $display ("RAM USAGE: vsisp_isp_miv1_mp_sramy_wrapper at %m not fully exercised."); + end + end + `endif + `endif + `ifdef ASSERT_ON_RAM + assert_never wrong_rwaddr0 (rwclk0, reset_, (~cEn0_ & (rwAddr0 > 80-1))); + assert_never_unknown #(0, 7, 0, "address is unknown") address_unknown0(rwclk0, reset_, ~cEn0_, rwAddr0); + assert_never_unknown #(0, 1, 0, "ram enable is unknown") ram_enable_unknown0(rwclk0, reset_, 1'b1, cEn0_); + assert_never_unknown #(0, 32, 0, "config signal is unknown") config_unknown_rw0(rwclk0, reset_, 1'b1, mcReg_registerTimingControl[32-1:0]); + assert_never_unknown #(0, 1, 0, "control signal is unknown") control_unknown_rw0(rwclk0, reset_, 1'b1, GC_CONTROL[4]); + `endif + `ifdef VIVANTE_CHECK_RAM_USAGE2 + `ifdef VIVANTE_RAM_MONITOR_END + parameter rAddr0Num = 8-1; + reg [rAddr0Num:0] rAddr0_r; + reg [31:0] rAddr0Cnt[0:rAddr0Num]; + parameter wAddr0Num = 8-1; + reg [wAddr0Num:0] wAddr0_r; + reg [31:0] wAddr0Cnt[0:wAddr0Num]; + parameter wData0Num = 29-1; + reg [wData0Num:0] wData0_r; + reg [31:0] wData0Cnt[0:wData0Num]; + parameter rData0Num = 29-1; + reg [rData0Num:0] rData0_r; + reg [31:0] rData0Cnt[0:rData0Num]; + initial + begin + #1; + @`VIVANTE_RAM_MONITOR_END + begin + integer i; + for(i=0;i<=rAddr0Num;i=i+1) + begin + $gethierachy(3, i, rAddr0Cnt[i]); + end + for(i=0;i<=wAddr0Num;i=i+1) + begin + $gethierachy(4, i, wAddr0Cnt[i]); + end + for(i=0;i<=wData0Num;i=i+1) + begin + $gethierachy(2, i, wData0Cnt[i]); + end + for(i=0;i<=rData0Num;i=i+1) + begin + $gethierachy(1, i, rData0Cnt[i]); + end + end + end + always @(posedge rwclk0 or negedge reset_) + begin + if(!reset_) + begin + rAddr0_r = 'b0; + rData0_r = 'b0; + end + else if(wEn0_&!cEn0_) + begin + rAddr0_r = rwAddr0; + rData0_r = rData0; + end + end + always @(posedge rwclk0 or negedge reset_) + begin + if(!reset_) + begin + integer i; + for(i=0;i<=rAddr0Num;i=i+1) + begin + rAddr0Cnt[i] = 'b0; + end + end + else if(wEn0_&!cEn0_) + begin + integer i; + for(i=0;i<=rAddr0Num;i=i+1) + begin + if(rAddr0_r[i]^rwAddr0[i]) + begin + rAddr0Cnt[i] = rAddr0Cnt[i] + 1; + end + end + end + end + always @(posedge rwclk0 or negedge reset_) + begin + if(!reset_) + begin + integer i; + for(i=0;i<=rData0Num;i=i+1) + begin + rData0Cnt[i] = 'b0; + end + end + else if(wEn0_&!cEn0_) + begin + integer i; + for(i=0;i<=rData0Num;i=i+1) + begin + if(rData0_r[i]^rData0[i]) + begin + rData0Cnt[i] = rData0Cnt[i] + 1; + end + end + end + end + always @(posedge rwclk0 or negedge reset_) + begin + if(!reset_) + begin + wAddr0_r = 'b0; + wData0_r = 'b0; + end + else if((!wEn0_)&(!cEn0_)) + begin + wAddr0_r = rwAddr0; + wData0_r = wData0; + end + end + always @(posedge rwclk0 or negedge reset_) + begin + if(!reset_) + begin + integer i; + for(i=0;i<=wAddr0Num;i=i+1) + begin + wAddr0Cnt[i] = 'b0; + end + end + else if((!wEn0_)&(!cEn0_)) + begin + integer i; + for(i=0;i<=wAddr0Num;i=i+1) + begin + if(wAddr0_r[i]^rwAddr0[i]) + begin + wAddr0Cnt[i] = wAddr0Cnt[i] + 1; + end + end + end + end + always @(posedge rwclk0 or negedge reset_) + begin + if(!reset_) + begin + integer i; + for(i=0;i<=wData0Num;i=i+1) + begin + wData0Cnt[i] = 'b0; + end + end + else if((!wEn0_)&(!cEn0_)) + begin + integer i; + for(i=0;i<=wData0Num;i=i+1) + begin + if(wData0_r[i]^wData0[i]) + begin + wData0Cnt[i] = wData0Cnt[i] + 1; + end + end + end + end + `endif + `endif +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_outform.v b/ispyocto/rtl/ispyocto/vsisp_isp_outform.v new file mode 100644 index 0000000..3f728ba --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_isp_outform.v
@@ -0,0 +1,276 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_isp_outform + ( + clk, + reset_clk_n, + soft_rst, + in_data, + in_h_end, + in_v_end, + in_val, + in_ack, + outform_data, + outform_h_end, + outform_v_end, + outform_val, + outform_ack, + regs_out_h_offs, + regs_out_v_offs, + regs_out_h_size, + regs_out_v_size, + regs_isp_mode, + regs_cfg_upd, + regs_gen_cfg_upd, + isp_on_shd, + h_offs_shd, + v_offs_shd, + h_size_shd, + v_size_shd, + v_start_pos, + size_err + ); + parameter c_data_width = 10; +`include "vsisp_isp.vh" + input clk; + input reset_clk_n; + input soft_rst; + input [c_data_width-1:0] in_data; + input in_h_end; + input in_v_end; + input in_val; + output in_ack; + output [c_data_width-1:0] outform_data; + output outform_h_end; + output outform_v_end; + output outform_val; + input outform_ack; + input [13:0] regs_out_h_offs; + input [13:0] regs_out_v_offs; + input [14:0] regs_out_h_size; + input [13:0] regs_out_v_size; + input [2:0] regs_isp_mode; + input regs_cfg_upd; + input regs_gen_cfg_upd; + input isp_on_shd; + output [13:0] h_offs_shd; + output [13:0] v_offs_shd; + output [14:0] h_size_shd; + output [13:0] v_size_shd; + output size_err; + output v_start_pos; + reg [c_data_width-1:0] outform_data; + reg outform_h_end; + reg outform_v_end; + reg outform_val; + reg [13:0] h_offs_shd; + reg [13:0] v_offs_shd; + reg [14:0] h_size_shd; + reg [13:0] v_size_shd; + reg [15:0] viv_s0; + reg [14:0] viv_s1; + reg viv_s2; + reg viv_s3; + wire size_err; + reg viv_s4; + reg viv_s5; + reg viv_s6; + reg viv_s7; + reg viv_s8; + wire in_ack; + wire [14:0] viv_s9; + wire [14:0] viv_s10; + wire viv_s11; + wire viv_s12; + wire viv_s13; + wire viv_s14; + wire viv_s15; + wire viv_s16; + wire viv_s17; + wire viv_s18; + wire viv_s19; + wire viv_s20; + wire viv_s21; + wire v_start_pos; + assign size_err = viv_s4 | viv_s5; + assign viv_s17 = in_h_end & ~viv_s11; + assign viv_s18 = in_h_end & in_v_end & ~viv_s12; + assign viv_s19 = (regs_isp_mode[2:0] == 3'b011)| + (regs_isp_mode[2:0] == 3'b101); + assign viv_s20 = (regs_isp_mode[2:0] == 3'b001)| + (regs_isp_mode[2:0] == 3'b010); + assign viv_s21 = (regs_isp_mode[2:0] == 3'b100); + assign viv_s9 = (viv_s19) ? {h_offs_shd} : (viv_s20) ? {h_offs_shd[12:1],2'b00} :h_offs_shd; + assign viv_s10 = (viv_s19) ? {1'b0,h_size_shd[13:1],1'b0} : (viv_s20) ? {h_size_shd[13:1],2'b00} :h_size_shd; + assign viv_s11 = (viv_s0 == {1'b0, viv_s9}); + assign viv_s12 = (viv_s1 == {1'b0, v_offs_shd}); + assign viv_s13 = (viv_s0 == ((viv_s10 + viv_s9) - 1'd1)); + assign viv_s14 = (viv_s1 == (({1'b0, v_size_shd} + v_offs_shd) - 1'd1)); + assign viv_s15 = (viv_s11 | viv_s2) & (viv_s12 | viv_s3) | viv_s21; + assign viv_s16 = in_val & viv_s15; + assign v_start_pos = viv_s11 & viv_s12 & in_val & in_ack; + always @ (posedge clk or negedge reset_clk_n) begin + if(~reset_clk_n) begin + viv_s0 <= 16'd0; + viv_s1 <= 15'd0; + h_offs_shd <= 14'd0; + v_offs_shd <= 14'd0; + h_size_shd <= 15'd0; + v_size_shd <= 14'd0; + viv_s2 <= 1'b0; + viv_s3 <= 1'b0; + viv_s4 <= 1'b0; + viv_s5 <= 1'b0; + viv_s8 <= 1'b0; + viv_s6 <= 1'b0; + viv_s7 <= 1'b0; + end else begin + if (soft_rst) begin + viv_s0 <= 16'd0; + viv_s1 <= 15'd0; + viv_s2 <= 1'b0; + viv_s3 <= 1'b0; + viv_s4 <= 1'b0; + viv_s5 <= 1'b0; + viv_s8 <= 1'b0; + viv_s6 <= 1'b0; + viv_s7 <= 1'b0; + end else begin + if (isp_on_shd & ~viv_s21) begin + if (~|h_size_shd) begin + viv_s4 <= 1'b1; + end else if (~|v_size_shd) begin + viv_s5 <= 1'b1; + end + end + if(in_ack & in_val &~viv_s21) begin + if (in_h_end & isp_on_shd & + ((viv_s2 & ~viv_s13) || ~(viv_s11 | viv_s6))) begin + viv_s4 <= 1'b1; + viv_s2 <= 1'b0; + end + else if (in_h_end & in_v_end & isp_on_shd & + ((viv_s3 & ~viv_s14) || ~(viv_s12 | viv_s7))) begin + viv_s5 <= 1'b1; + viv_s3 <= 1'b0; + end + end else begin + viv_s5 <= 1'b0; + viv_s4 <= 1'b0; + end + if (viv_s11) viv_s6 <= 1'b1; + if (viv_s12) viv_s7 <= 1'b1; + if (regs_gen_cfg_upd) begin + viv_s8 <= 1'b1; + end + if (in_ack & in_val & ~viv_s21) begin + if (in_h_end) begin + viv_s0 <= 16'd0; + if(in_v_end) begin + viv_s1 <= 15'd0; + end else begin + viv_s1 <= viv_s1 + 1'd1; + end + end else begin + viv_s0 <= viv_s0 + 1'd1; + end + if (viv_s2 & viv_s13) begin + viv_s2 <= 1'b0; + end else begin + if (viv_s11 & ~viv_s13) begin + viv_s2 <= 1'b1; + end + end + if (viv_s17) viv_s6 <= 1'b0; + if ((viv_s3 & viv_s14) & + (viv_s2 & viv_s13)) begin + viv_s3 <= 1'b0; + end else begin + if (viv_s12 &~viv_s14) begin + viv_s3 <= 1'b1; + end + end + if (viv_s18) viv_s7 <= 1'b0; + end + if (in_val & in_ack & viv_s13 & viv_s14 & viv_s15) begin + if (viv_s8) begin + viv_s8 <= regs_gen_cfg_upd; + h_offs_shd <= regs_out_h_offs; + v_offs_shd <= regs_out_v_offs; + h_size_shd <= regs_out_h_size; + v_size_shd <= regs_out_v_size; + end + end + if (regs_cfg_upd) begin + h_offs_shd <= regs_out_h_offs; + v_offs_shd <= regs_out_v_offs; + h_size_shd <= regs_out_h_size; + v_size_shd <= regs_out_v_size; + end + end + end + end + always @(posedge clk or negedge reset_clk_n) begin + if (!reset_clk_n) begin + outform_data <= {c_data_width{1'b0}}; + outform_val <= 1'b0; + outform_h_end <= 1'b0; + outform_v_end <= 1'b0; + end + else begin + if (soft_rst) begin + outform_data <= {c_data_width{1'b0}}; + outform_val <= 1'b0; + outform_h_end <= 1'b0; + outform_v_end <= 1'b0; + end else begin + if (in_ack) begin + outform_data <= in_data; + outform_h_end <= viv_s21 ? in_h_end : viv_s13; + outform_v_end <= viv_s21 ? in_v_end : viv_s14; + outform_val <= viv_s16; + end + end + end + end + assign in_ack = ~outform_val | outform_ack; +`ifdef FPGA_DEBUG_ISP + (* mark_debug = "true" *)reg [15:0] probing__outform_h_cnt/* synthesis syn_noprune=1 syn_preserve = 1 */; + (* mark_debug = "true" *)reg [14:0] probing__outform_v_cnt/* synthesis syn_noprune=1 syn_preserve = 1 */; + (* mark_debug = "true" *)reg probing__outform_val/* synthesis syn_noprune=1 syn_preserve = 1 */; + (* mark_debug = "true" *)reg [c_dw_si-1:0] probing__outform_data/* synthesis syn_noprune=1 syn_preserve = 1 */; + (* mark_debug = "true" *)reg probing__outform_h_end/* synthesis syn_noprune=1 syn_preserve = 1 */; + (* mark_debug = "true" *)reg probing__outform_v_end/* synthesis syn_noprune=1 syn_preserve = 1 */; + (* mark_debug = "true" *)reg probing__outform_ack/* synthesis syn_noprune=1 syn_preserve = 1 */; +always@(posedge clk)begin + probing__outform_h_cnt <= viv_s0 ; + probing__outform_v_cnt <= viv_s1 ; + probing__outform_val <= outform_val ; + probing__outform_data <= outform_data ; + probing__outform_h_end <= outform_h_end; + probing__outform_v_end <= outform_v_end; + probing__outform_ack <= outform_ack ; +end +`endif +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_pseudo_random_gen.v b/ispyocto/rtl/ispyocto/vsisp_isp_pseudo_random_gen.v new file mode 100644 index 0000000..e7fbc8c --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_isp_pseudo_random_gen.v
@@ -0,0 +1,43 @@ +//**************************************************************************** +// +// Copyright 2023 Vivante Corp. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_isp_pseudo_random_gen +( + input wire clk, + input wire ce, + input wire rst_n, + input wire random_seed_en, + input wire [31:0] seed, + output reg [31:0] q +); +wire viv_s0 = q[31]^q[29]^q[28]^ q[27]^ q[23]^q[20]^ q[19]^q[17]^ q[15]^q[14]^q[12]^ q[11]^q[9]^ q[4]^ q[3]^q[2]; +always @(posedge clk or negedge rst_n) +begin + if (!rst_n) + q <= 32'h0; + else + if(random_seed_en) + q <= seed; + else + if (ce) + q <= {q[30:0], viv_s0}; +end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_regs.v b/ispyocto/rtl/ispyocto/vsisp_isp_regs.v new file mode 100644 index 0000000..addd12d --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_isp_regs.v
@@ -0,0 +1,1038 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_isp_regs + (clk_cfg, + reset_cfg_n, + cfg_addr, + cfg_wdata, + cfg_rdata, + cfg_rd, + cfg_val, + cfg_ack, + regs_gen_cfg_upd, + regs_cfg_upd, + regs_isp_mode, + regs_isp_enable, + regs_disable_isp_clk, + regs_awb_enable, + regs_statistic_3a_sel, + regs_inform_enable, + regs_input_selection, + regs_input_pin_map, + regs_field_inv, + regs_field_selection, + regs_ccir_seq, + regs_conv_422, + regs_bayer_pat, + regs_vsync_pol, + regs_hsync_pol, + regs_sample_edge, + regs_acq_h_offs, + regs_acq_v_offs, + regs_acq_h_size, + regs_acq_v_size, + regs_out_h_offs, + regs_out_v_offs, + regs_out_h_size, + regs_out_v_size, + out_h_offs_shd, + out_v_offs_shd, + out_h_size_shd, + out_v_size_shd, + regs_dgain_enable, + regs_dgain_r, + regs_dgain_gr, + regs_dgain_gb, + regs_dgain_b, + regs_demosaic_bypass, + regs_demosaic_th, + regs_gamma_out_enable, + regs_equ_segm, + regs_gamma_out_y0, + regs_gamma_out_y1, + regs_gamma_out_y2, + regs_gamma_out_y3, + regs_gamma_out_y4, + regs_gamma_out_y5, + regs_gamma_out_y6, + regs_gamma_out_y7, + regs_gamma_out_y8, + regs_gamma_out_y9, + regs_gamma_out_y10, + regs_gamma_out_y11, + regs_gamma_out_y12, + regs_gamma_out_y13, + regs_gamma_out_y14, + regs_gamma_out_y15, + regs_gamma_out_y16, + regs_awb_meas_mode, + regs_awb_max_en, + regs_awb_mode, + regs_awb_h_offs, + regs_awb_v_offs, + regs_awb_h_size, + regs_awb_v_size, + regs_awb_frames, + regs_awb_ref_cb__max_b, + regs_awb_ref_cr__max_r, + regs_awb_max_y, + regs_awb_min_y__max_g, + regs_awb_min_c, + regs_awb_max_csum, + awb_white_cnt, + awb_mean_y__g, + awb_mean_cb__b, + awb_mean_cr__r, + regs_cc_coeff0, + regs_cc_coeff1, + regs_cc_coeff2, + regs_cc_coeff3, + regs_cc_coeff4, + regs_cc_coeff5, + regs_cc_coeff6, + regs_cc_coeff7, + regs_cc_coeff8, + regs_csm_y_range, + regs_csm_c_range, + format_conv_ctrl, + regs_ct_coeff0, + regs_ct_coeff1, + regs_ct_coeff2, + regs_ct_coeff3, + regs_ct_coeff4, + regs_ct_coeff5, + regs_ct_coeff6, + regs_ct_coeff7, + regs_ct_coeff8, + regs_ct_offset_r, + regs_ct_offset_g, + regs_ct_offset_b, + regs_isp_ris, + regs_isp_mis, + regs_isp_imsc, + regs_isp_isr, + regs_isp_icr, + regs_err_clr, + isp_err_status, + cfg_filt_rdata, + cfg_bls_rdata, + cfg_exp_rdata, + tpg_en, + img_num, + frm_num, + cfa_pat, + color_depth, + def_sync, + max_sync, + tpg_resolution, + vtotal_in, + htotal_in, + v_act_in, + h_act_in, + fp_v_in, + fp_h_in, + bp_v_in, + bp_h_in, + vs_w_in, + hs_w_in, + line_gap_in, + pix_gap_in, + pix_gap_std_in, + random_seed_in, + clk, + rst_clk_n, + frame_end_dgain + ); +`include "vsisp_isp.vh" + input clk_cfg; + input reset_cfg_n; + input [31:0] cfg_addr; + input [31:0] cfg_wdata; + output [31:0] cfg_rdata; + input cfg_rd; + input cfg_val; + output cfg_ack; +output tpg_en; +output [2:0] img_num; +output [15:0] frm_num; +output [1:0] cfa_pat; +output [1:0] color_depth; +output def_sync; +output max_sync; +output [1:0] tpg_resolution; +output [13:0] vtotal_in; +output [13:0] htotal_in; +output [13:0] v_act_in; +output [13:0] h_act_in; +output [13:0] fp_v_in; +output [13:0] fp_h_in; +output [13:0] bp_v_in; +output [13:0] bp_h_in; +output [13:0] vs_w_in; +output [13:0] hs_w_in; +output [13:0] line_gap_in; +output [13:0] pix_gap_in; +output [13:0] pix_gap_std_in; +output [31:0] random_seed_in; +input clk; +input rst_clk_n; +input frame_end_dgain; + output regs_gen_cfg_upd; + output regs_cfg_upd; + output [2:0] regs_isp_mode; + output regs_isp_enable; + output regs_disable_isp_clk; + output regs_awb_enable; + output regs_statistic_3a_sel; + output regs_inform_enable; + output [2:0] regs_input_selection; + output [2:0] regs_input_pin_map; + output regs_field_inv; + output [1:0] regs_field_selection; + output [1:0] regs_ccir_seq; + output [1:0] regs_conv_422; + output [1:0] regs_bayer_pat; + output regs_vsync_pol; + output regs_hsync_pol; + output regs_sample_edge; + output [14:0] regs_acq_h_offs; + output [13:0] regs_acq_v_offs; + output [14:0] regs_acq_h_size; + output [13:0] regs_acq_v_size; + output [13:0] regs_out_h_offs; + output [13:0] regs_out_v_offs; + output [14:0] regs_out_h_size; + output [13:0] regs_out_v_size; + input [13:0] out_h_offs_shd; + input [13:0] out_v_offs_shd; + input [14:0] out_h_size_shd; + input [13:0] out_v_size_shd; + output regs_dgain_enable; + output [ 15:0] regs_dgain_r; + output [ 15:0] regs_dgain_gr; + output [ 15:0] regs_dgain_gb; + output [ 15:0] regs_dgain_b; + output regs_demosaic_bypass; + output [7:0] regs_demosaic_th; + output regs_gamma_out_enable; + output regs_equ_segm; + output [c_dw_do-1:0] regs_gamma_out_y0; + output [c_dw_do-1:0] regs_gamma_out_y1; + output [c_dw_do-1:0] regs_gamma_out_y2; + output [c_dw_do-1:0] regs_gamma_out_y3; + output [c_dw_do-1:0] regs_gamma_out_y4; + output [c_dw_do-1:0] regs_gamma_out_y5; + output [c_dw_do-1:0] regs_gamma_out_y6; + output [c_dw_do-1:0] regs_gamma_out_y7; + output [c_dw_do-1:0] regs_gamma_out_y8; + output [c_dw_do-1:0] regs_gamma_out_y9; + output [c_dw_do-1:0] regs_gamma_out_y10; + output [c_dw_do-1:0] regs_gamma_out_y11; + output [c_dw_do-1:0] regs_gamma_out_y12; + output [c_dw_do-1:0] regs_gamma_out_y13; + output [c_dw_do-1:0] regs_gamma_out_y14; + output [c_dw_do-1:0] regs_gamma_out_y15; + output [c_dw_do-1:0] regs_gamma_out_y16; + output regs_awb_meas_mode; + output regs_awb_max_en; + output [1:0] regs_awb_mode; + output [12:0] regs_awb_h_offs; + output [12:0] regs_awb_v_offs; + output [13:0] regs_awb_h_size; + output [13:0] regs_awb_v_size; + output [ 2:0] regs_awb_frames; + output [ 7:0] regs_awb_ref_cb__max_b; + output [ 7:0] regs_awb_ref_cr__max_r; + output [ 7:0] regs_awb_max_y; + output [ 7:0] regs_awb_min_y__max_g; + output [ 7:0] regs_awb_min_c; + output [ 7:0] regs_awb_max_csum; + input [c_white_cnt-1:0] awb_white_cnt; + input [ 7:0] awb_mean_y__g; + input [ 7:0] awb_mean_cb__b; + input [ 7:0] awb_mean_cr__r; + output [ 8:0] regs_cc_coeff0; + output [ 8:0] regs_cc_coeff1; + output [ 8:0] regs_cc_coeff2; + output [ 8:0] regs_cc_coeff3; + output [ 8:0] regs_cc_coeff4; + output [ 8:0] regs_cc_coeff5; + output [ 8:0] regs_cc_coeff6; + output [ 8:0] regs_cc_coeff7; + output [ 8:0] regs_cc_coeff8; + output regs_csm_y_range; + output regs_csm_c_range; + output format_conv_ctrl; + output [10:0] regs_ct_coeff0; + output [10:0] regs_ct_coeff1; + output [10:0] regs_ct_coeff2; + output [10:0] regs_ct_coeff3; + output [10:0] regs_ct_coeff4; + output [10:0] regs_ct_coeff5; + output [10:0] regs_ct_coeff6; + output [10:0] regs_ct_coeff7; + output [10:0] regs_ct_coeff8; + output [c_dw_si-1:0] regs_ct_offset_r; + output [c_dw_si-1:0] regs_ct_offset_g; + output [c_dw_si-1:0] regs_ct_offset_b; + input [c_irq_bw-1:0] regs_isp_ris; + input [c_irq_bw-1:0] regs_isp_mis; + output [c_irq_bw-1:0] regs_isp_imsc; + output [c_irq_bw-1:0] regs_isp_isr; + output [c_irq_bw-1:0] regs_isp_icr; + output [c_isp_err_bw-1:0] regs_err_clr; + input [c_isp_err_bw-1:0] isp_err_status; + input [31:0] cfg_filt_rdata; + input [31:0] cfg_bls_rdata; + input [31:0] cfg_exp_rdata; +reg tpg_en; +reg [2:0] img_num; +reg [15:0] frm_num; +reg [1:0] cfa_pat; +reg [1:0] color_depth; +reg def_sync; +reg max_sync; +reg [1:0] tpg_resolution; +reg [13:0] vtotal_in; +reg [13:0] htotal_in; +reg [13:0] v_act_in; +reg [13:0] h_act_in; +reg [13:0] fp_v_in; +reg [13:0] fp_h_in; +reg [13:0] bp_v_in; +reg [13:0] bp_h_in; +reg [13:0] vs_w_in; +reg [13:0] hs_w_in; +reg [13:0] line_gap_in; +reg [13:0] pix_gap_in; +reg [13:0] pix_gap_std_in; +reg [31:0] random_seed_in; + reg cfg_ack; + reg [31:0] cfg_rdata; + reg regs_gen_cfg_upd; + reg regs_cfg_upd; + reg viv_s0; + reg [2:0] regs_isp_mode; + reg regs_isp_enable; + reg regs_disable_isp_clk; + reg regs_awb_enable; + reg regs_statistic_3a_sel; + reg regs_inform_enable; + reg [2:0] regs_input_selection; + reg [2:0] regs_input_pin_map; + reg regs_field_inv; + reg [1:0] regs_field_selection; + reg [1:0] regs_ccir_seq; + reg [1:0] regs_conv_422; + reg [1:0] regs_bayer_pat; + reg regs_vsync_pol; + reg regs_hsync_pol; + reg regs_sample_edge; + reg [14:0] regs_acq_h_offs; + reg [13:0] regs_acq_v_offs; + reg [14:0] regs_acq_h_size; + reg [13:0] regs_acq_v_size; + reg [5:0] viv_s1; + reg [13:0] regs_out_h_offs; + reg [13:0] regs_out_v_offs; + reg [14:0] regs_out_h_size; + reg [13:0] regs_out_v_size; + reg regs_dgain_enable; + reg [ 15:0] regs_dgain_r; + reg [ 15:0] regs_dgain_gr; + reg [ 15:0] regs_dgain_gb; + reg [ 15:0] regs_dgain_b; + reg [ 15:0] viv_s2; + reg [ 15:0] viv_s3; + reg [ 15:0] viv_s4; + reg [ 15:0] viv_s5; + reg regs_demosaic_bypass; + reg [7:0] regs_demosaic_th; + reg regs_gamma_out_enable; + reg regs_equ_segm; + reg [c_dw_do-1:0] regs_gamma_out_y0; + reg [c_dw_do-1:0] regs_gamma_out_y1; + reg [c_dw_do-1:0] regs_gamma_out_y2; + reg [c_dw_do-1:0] regs_gamma_out_y3; + reg [c_dw_do-1:0] regs_gamma_out_y4; + reg [c_dw_do-1:0] regs_gamma_out_y5; + reg [c_dw_do-1:0] regs_gamma_out_y6; + reg [c_dw_do-1:0] regs_gamma_out_y7; + reg [c_dw_do-1:0] regs_gamma_out_y8; + reg [c_dw_do-1:0] regs_gamma_out_y9; + reg [c_dw_do-1:0] regs_gamma_out_y10; + reg [c_dw_do-1:0] regs_gamma_out_y11; + reg [c_dw_do-1:0] regs_gamma_out_y12; + reg [c_dw_do-1:0] regs_gamma_out_y13; + reg [c_dw_do-1:0] regs_gamma_out_y14; + reg [c_dw_do-1:0] regs_gamma_out_y15; + reg [c_dw_do-1:0] regs_gamma_out_y16; + reg regs_awb_max_en; + reg regs_awb_meas_mode; + reg [1:0] regs_awb_mode; + reg [12:0] regs_awb_h_offs; + reg [12:0] regs_awb_v_offs; + reg [13:0] regs_awb_h_size; + reg [13:0] regs_awb_v_size; + reg [ 2:0] regs_awb_frames; + reg [ 7:0] regs_awb_ref_cb__max_b; + reg [ 7:0] regs_awb_ref_cr__max_r; + reg [ 7:0] regs_awb_max_y; + reg [ 7:0] regs_awb_min_y__max_g; + reg [ 7:0] regs_awb_min_c; + reg [ 7:0] regs_awb_max_csum; + reg [ 8:0] regs_cc_coeff0; + reg [ 8:0] regs_cc_coeff1; + reg [ 8:0] regs_cc_coeff2; + reg [ 8:0] regs_cc_coeff3; + reg [ 8:0] regs_cc_coeff4; + reg [ 8:0] regs_cc_coeff5; + reg [ 8:0] regs_cc_coeff6; + reg [ 8:0] regs_cc_coeff7; + reg [ 8:0] regs_cc_coeff8; + reg regs_csm_y_range; + reg regs_csm_c_range; + reg format_conv_ctrl; + reg [10:0] regs_ct_coeff0; + reg [10:0] regs_ct_coeff1; + reg [10:0] regs_ct_coeff2; + reg [10:0] regs_ct_coeff3; + reg [10:0] regs_ct_coeff4; + reg [10:0] regs_ct_coeff5; + reg [10:0] regs_ct_coeff6; + reg [10:0] regs_ct_coeff7; + reg [10:0] regs_ct_coeff8; + reg [c_dw_si-1:0] regs_ct_offset_r; + reg [c_dw_si-1:0] regs_ct_offset_g; + reg [c_dw_si-1:0] regs_ct_offset_b; + reg [c_irq_bw-1:0] regs_isp_imsc; + reg [c_irq_bw-1:0] regs_isp_isr; + reg [c_irq_bw-1:0] regs_isp_icr; + reg [c_isp_err_bw-1:0] regs_err_clr; + wire [11:0] viv_s6; + wire viv_s7; + wire viv_s8; + wire viv_s9; + wire viv_s10; + assign viv_s7 = ((viv_s6 >= (c_filt_base_adr+ 12'h004)) & + (viv_s6 <= (c_filt_base_adr + 12'h02C))); + assign viv_s8 = ((viv_s6 >= c_bls_base_adr) & + (viv_s6 <= (c_bls_base_adr + 12'h010))); + assign viv_s9 = ((viv_s6 >= c_cac_base_adr) & + (viv_s6 <= (c_cac_base_adr + 12'h018))); + assign viv_s10 = ((viv_s6 >= c_exp_base_adr) & + (viv_s6 <= (c_exp_base_adr + 12'h074))); + parameter c_gamma_reset_y0 = 14'h0000 >>(c_dw_do+4-10) ; + parameter c_gamma_reset_y1 = 14'h0490 >>(c_dw_do+4-10) ; + parameter c_gamma_reset_y2 = 14'h0890 >>(c_dw_do+4-10) ; + parameter c_gamma_reset_y3 = 14'h0B70 >>(c_dw_do+4-10) ; + parameter c_gamma_reset_y4 = 14'h0DF0 >>(c_dw_do+4-10) ; + parameter c_gamma_reset_y5 = 14'h11F0 >>(c_dw_do+4-10) ; + parameter c_gamma_reset_y6 = 14'h1540 >>(c_dw_do+4-10) ; + parameter c_gamma_reset_y7 = 14'h1830 >>(c_dw_do+4-10) ; + parameter c_gamma_reset_y8 = 14'h1AD0 >>(c_dw_do+4-10) ; + parameter c_gamma_reset_y9 = 14'h1F60 >>(c_dw_do+4-10) ; + parameter c_gamma_reset_y10 = 14'h2350 >>(c_dw_do+4-10) ; + parameter c_gamma_reset_y11 = 14'h26F0 >>(c_dw_do+4-10) ; + parameter c_gamma_reset_y12 = 14'h2D30 >>(c_dw_do+4-10) ; + parameter c_gamma_reset_y13 = 14'h32A0 >>(c_dw_do+4-10) ; + parameter c_gamma_reset_y14 = 14'h3780 >>(c_dw_do+4-10) ; + parameter c_gamma_reset_y15 = 14'h3BF0 >>(c_dw_do+4-10) ; + assign viv_s6 = cfg_addr[11:0]; + always @(posedge clk_cfg or negedge reset_cfg_n) begin + if (~reset_cfg_n) begin + regs_isp_imsc <= {c_irq_bw{1'b0}}; + regs_isp_isr <= {c_irq_bw{1'b0}}; + regs_isp_icr <= {c_irq_bw{1'b0}}; + regs_err_clr <= {c_isp_err_bw{1'b0}}; + regs_gen_cfg_upd <= 0; + regs_cfg_upd <= 0; + viv_s0 <= 0; + regs_gamma_out_enable <= 0; + regs_inform_enable <= 0; + regs_isp_mode <= 0; + regs_isp_enable <= 0; + regs_disable_isp_clk <= 1; + regs_statistic_3a_sel <= 0; + regs_awb_enable <= 0; + regs_demosaic_bypass <= 0; + regs_demosaic_th <= 4; + regs_input_selection <= 0; + regs_input_pin_map <= 0; + regs_field_inv <= 0; + regs_field_selection <= 0; + regs_ccir_seq <= 0; + regs_conv_422 <= 0; + regs_bayer_pat <= 0; + regs_vsync_pol <= 0; + regs_hsync_pol <= 0; + regs_sample_edge <= 0; + regs_acq_h_offs <= 0; + regs_acq_v_offs <= 0; + regs_acq_h_size <= 15'h1000; + regs_acq_v_size <= 14'hC00; + regs_equ_segm <= 1'b0; + regs_gamma_out_y0 <= c_gamma_reset_y0 [c_dw_do-1:0] ; + regs_gamma_out_y1 <= c_gamma_reset_y1 [c_dw_do-1:0] ; + regs_gamma_out_y2 <= c_gamma_reset_y2 [c_dw_do-1:0] ; + regs_gamma_out_y3 <= c_gamma_reset_y3 [c_dw_do-1:0] ; + regs_gamma_out_y4 <= c_gamma_reset_y4 [c_dw_do-1:0] ; + regs_gamma_out_y5 <= c_gamma_reset_y5 [c_dw_do-1:0] ; + regs_gamma_out_y6 <= c_gamma_reset_y6 [c_dw_do-1:0] ; + regs_gamma_out_y7 <= c_gamma_reset_y7 [c_dw_do-1:0] ; + regs_gamma_out_y8 <= c_gamma_reset_y8 [c_dw_do-1:0] ; + regs_gamma_out_y9 <= c_gamma_reset_y9 [c_dw_do-1:0] ; + regs_gamma_out_y10 <= c_gamma_reset_y10[c_dw_do-1:0] ; + regs_gamma_out_y11 <= c_gamma_reset_y11[c_dw_do-1:0] ; + regs_gamma_out_y12 <= c_gamma_reset_y12[c_dw_do-1:0] ; + regs_gamma_out_y13 <= c_gamma_reset_y13[c_dw_do-1:0] ; + regs_gamma_out_y14 <= c_gamma_reset_y14[c_dw_do-1:0] ; + regs_gamma_out_y15 <= c_gamma_reset_y15[c_dw_do-1:0] ; + regs_gamma_out_y16 <= {c_dw_do{1'b1}}; + regs_awb_meas_mode <= 0; + regs_awb_max_en <= 0; + regs_awb_mode <= 0; + regs_awb_h_offs <= 0; + regs_awb_v_offs <= 0; + regs_awb_h_size <= 0; + regs_awb_v_size <= 0; + regs_awb_frames <= 0; + regs_awb_ref_cb__max_b <= 8'd128; + regs_awb_ref_cr__max_r <= 8'd128; + regs_awb_max_y <= 8'hE9; + regs_awb_min_y__max_g <= 8'hc0; + regs_awb_min_c <= 8'h10; + regs_awb_max_csum <= 8'h10; + regs_cc_coeff0 <= 9'h021; + regs_cc_coeff1 <= 9'h040; + regs_cc_coeff2 <= 9'h00d; + regs_cc_coeff3 <= 9'h1ed; + regs_cc_coeff4 <= 9'h1db; + regs_cc_coeff5 <= 9'h038; + regs_cc_coeff6 <= 9'h038; + regs_cc_coeff7 <= 9'h1d1; + regs_cc_coeff8 <= 9'h1f7; + regs_csm_y_range <= 0; + regs_csm_c_range <= 0; + format_conv_ctrl <= 0; + regs_ct_coeff0 <= 11'h080; + regs_ct_coeff1 <= 11'h0; + regs_ct_coeff2 <= 11'h0; + regs_ct_coeff3 <= 11'h0; + regs_ct_coeff4 <= 11'h080; + regs_ct_coeff5 <= 11'h0; + regs_ct_coeff6 <= 11'h0; + regs_ct_coeff7 <= 11'h0; + regs_ct_coeff8 <= 11'h080; + regs_ct_offset_r <= {c_dw_si{1'b0}}; + regs_ct_offset_g <= {c_dw_si{1'b0}}; + regs_ct_offset_b <= {c_dw_si{1'b0}}; + regs_out_h_offs <= 14'h0; + regs_out_v_offs <= 14'h0; + regs_out_h_size <= 15'h280; + regs_out_v_size <= 14'h1e0; + tpg_en <= 1'h0; + img_num <= 3'h0; + frm_num <= 16'h0; + cfa_pat <= 2'h0; + color_depth <= 2'h0; + def_sync <= 1'h0; + max_sync <= 1'h0; + tpg_resolution <= 2'h0; + vtotal_in <= 14'h0; + htotal_in <= 14'h0; + v_act_in <= 14'h0; + h_act_in <= 14'h0; + fp_v_in <= 14'h0; + fp_h_in <= 14'h0; + bp_v_in <= 14'h0; + bp_h_in <= 14'h0; + vs_w_in <= 14'h0; + hs_w_in <= 14'h0; + line_gap_in <= 14'h0; + pix_gap_in <= 14'h0; + pix_gap_std_in <= 14'h0; + random_seed_in <= 32'h0; + viv_s1 <= 6'h0; + viv_s2 <= 16'h100; + viv_s3 <= 16'h100; + viv_s4 <= 16'h100; + viv_s5 <= 16'h100; + regs_dgain_enable <= 1'b0; + end else begin + regs_gen_cfg_upd <= viv_s0; + regs_cfg_upd <= 1'b0; + regs_isp_isr <= {c_irq_bw{1'b0}}; + regs_isp_icr <= {c_irq_bw{1'b0}}; + regs_err_clr <= {c_isp_err_bw{1'b0}}; + if(~cfg_ack) begin + if (cfg_val) begin + if (~cfg_rd) begin + case (viv_s6[11:0]) + c_ctrl:begin + regs_disable_isp_clk <= cfg_wdata[31]; + regs_statistic_3a_sel <= cfg_wdata[21]; + regs_csm_c_range <= cfg_wdata[14]; + regs_csm_y_range <= cfg_wdata[13]; + regs_dgain_enable <= cfg_wdata[12]; + regs_gamma_out_enable <= cfg_wdata[11]; + regs_gen_cfg_upd <= cfg_wdata[10]; + regs_cfg_upd <= cfg_wdata[9]; + viv_s0 <= cfg_wdata[8]; + regs_awb_enable <= cfg_wdata[6]; + regs_inform_enable <= cfg_wdata[4]; + regs_isp_mode <= cfg_wdata[3:1]; + regs_isp_enable <= cfg_wdata[0]; + end + c_acq_prop:begin + regs_input_pin_map <= cfg_wdata[19:17]; + regs_input_selection <= cfg_wdata[14:12]; + regs_field_inv <= cfg_wdata[11]; + regs_field_selection <= cfg_wdata[10:9]; + regs_ccir_seq <= cfg_wdata[8:7]; + regs_conv_422 <= cfg_wdata[6:5]; + regs_bayer_pat <= cfg_wdata[4:3]; + regs_vsync_pol <= cfg_wdata[2]; + regs_hsync_pol <= cfg_wdata[1]; + regs_sample_edge <= cfg_wdata[0]; + end + c_acq_h_offs:begin + regs_acq_h_offs <= cfg_wdata[14:0]; + end + c_acq_v_offs:begin + regs_acq_v_offs <= cfg_wdata[13:0]; + end + c_acq_h_size:begin + regs_acq_h_size <= cfg_wdata[14:0]; + end + c_acq_v_size:begin + regs_acq_v_size <= cfg_wdata[13:0]; + end + c_tpg_global : begin + tpg_en <= cfg_wdata[0]; + img_num <= cfg_wdata[3:1]; + cfa_pat <= cfg_wdata[5:4]; + color_depth <= cfg_wdata[7:6]; + def_sync <= cfg_wdata[8]; + max_sync <= cfg_wdata[9]; + tpg_resolution <= cfg_wdata[11:10]; + end + c_tpg_total : begin + vtotal_in <= cfg_wdata[13:0]; + htotal_in <= cfg_wdata[27:14]; + end + c_tpg_act : begin + v_act_in <= cfg_wdata[13:0]; + h_act_in <= cfg_wdata[27:14]; + end + c_tpg_fp : begin + fp_v_in <= cfg_wdata[13:0]; + fp_h_in <= cfg_wdata[27:14]; + end + c_tpg_bp : begin + bp_v_in <= cfg_wdata[13:0]; + bp_h_in <= cfg_wdata[27:14]; + end + c_tpg_w : begin + vs_w_in <= cfg_wdata[13:0]; + hs_w_in <= cfg_wdata[27:14]; + end + c_tpg_gap : begin + line_gap_in <= cfg_wdata[13:0]; + pix_gap_in <= cfg_wdata[27:14]; + end + c_tpg_gap_std : begin + pix_gap_std_in <= cfg_wdata[13:0]; + end + c_tpg_seed : random_seed_in <= cfg_wdata[31:0]; + c_tpg_frm_num : frm_num <= cfg_wdata[15:0]; + c_frame_rate_ctrl: begin + viv_s1 <= cfg_wdata[5:0]; + end + c_out_h_offs:begin + regs_out_h_offs <= cfg_wdata[13:0]; + end + c_out_v_offs:begin + regs_out_v_offs <= cfg_wdata[13:0]; + end + c_out_h_size:begin + regs_out_h_size <= cfg_wdata[14:0]; + end + c_out_v_size:begin + regs_out_v_size <= cfg_wdata[13:0]; + end + c_dgain_0:begin + viv_s2 <= cfg_wdata[31:16]; + viv_s5 <= cfg_wdata[15:0]; + end + c_dgain_1:begin + viv_s3 <= cfg_wdata[31:16]; + viv_s4 <= cfg_wdata[15:0]; + end + c_demosaic:begin + regs_demosaic_bypass <= cfg_wdata[10]; + regs_demosaic_th <= cfg_wdata[7:0]; + end + c_gamma_out_mod:begin + regs_equ_segm <= cfg_wdata[0]; + end + c_gamma_out_y0: regs_gamma_out_y0 <= {cfg_wdata[c_dw_do-1:0]}; + c_gamma_out_y1: regs_gamma_out_y1 <= {cfg_wdata[c_dw_do-1:0]}; + c_gamma_out_y2: regs_gamma_out_y2 <= {cfg_wdata[c_dw_do-1:0]}; + c_gamma_out_y3: regs_gamma_out_y3 <= {cfg_wdata[c_dw_do-1:0]}; + c_gamma_out_y4: regs_gamma_out_y4 <= {cfg_wdata[c_dw_do-1:0]}; + c_gamma_out_y5: regs_gamma_out_y5 <= {cfg_wdata[c_dw_do-1:0]}; + c_gamma_out_y6: regs_gamma_out_y6 <= {cfg_wdata[c_dw_do-1:0]}; + c_gamma_out_y7: regs_gamma_out_y7 <= {cfg_wdata[c_dw_do-1:0]}; + c_gamma_out_y8: regs_gamma_out_y8 <= {cfg_wdata[c_dw_do-1:0]}; + c_gamma_out_y9: regs_gamma_out_y9 <= {cfg_wdata[c_dw_do-1:0]}; + c_gamma_out_y10: regs_gamma_out_y10<= {cfg_wdata[c_dw_do-1:0]}; + c_gamma_out_y11: regs_gamma_out_y11<= {cfg_wdata[c_dw_do-1:0]}; + c_gamma_out_y12: regs_gamma_out_y12<= {cfg_wdata[c_dw_do-1:0]}; + c_gamma_out_y13: regs_gamma_out_y13<= {cfg_wdata[c_dw_do-1:0]}; + c_gamma_out_y14: regs_gamma_out_y14<= {cfg_wdata[c_dw_do-1:0]}; + c_gamma_out_y15: regs_gamma_out_y15<= {cfg_wdata[c_dw_do-1:0]}; + c_gamma_out_y16: regs_gamma_out_y16<= {cfg_wdata[c_dw_do-1:0]}; + c_awb_prop:begin + regs_awb_meas_mode <= cfg_wdata[31]; + regs_awb_max_en <= cfg_wdata[2]; + regs_awb_mode <= cfg_wdata[1:0]; + end + c_awb_h_offs_old:begin + regs_awb_h_offs <= cfg_wdata[12:0]; + end + c_awb_v_offs_old:begin + regs_awb_v_offs <= cfg_wdata[12:0]; + end + c_awb_h_size_old:begin + regs_awb_h_size <= cfg_wdata[13:0]; + end + c_awb_v_size_old:begin + regs_awb_v_size <= cfg_wdata[13:0]; + end + c_awb_frames:begin + regs_awb_frames <= cfg_wdata[2:0]; + end + c_awb_ref:begin + regs_awb_ref_cr__max_r <= cfg_wdata[15:8]; + regs_awb_ref_cb__max_b <= cfg_wdata[7:0]; + end + c_awb_thres:begin + regs_awb_max_y <= cfg_wdata[31:24]; + regs_awb_min_y__max_g <= cfg_wdata[23:16]; + regs_awb_max_csum <= cfg_wdata[15:8]; + regs_awb_min_c <= cfg_wdata[7:0]; + end + c_cc_coeff_0: regs_cc_coeff0 <= cfg_wdata[8:0]; + c_cc_coeff_1: regs_cc_coeff1 <= cfg_wdata[8:0]; + c_cc_coeff_2: regs_cc_coeff2 <= cfg_wdata[8:0]; + c_cc_coeff_3: regs_cc_coeff3 <= cfg_wdata[8:0]; + c_cc_coeff_4: regs_cc_coeff4 <= cfg_wdata[8:0]; + c_cc_coeff_5: regs_cc_coeff5 <= cfg_wdata[8:0]; + c_cc_coeff_6: regs_cc_coeff6 <= cfg_wdata[8:0]; + c_cc_coeff_7: regs_cc_coeff7 <= cfg_wdata[8:0]; + c_cc_coeff_8: regs_cc_coeff8 <= cfg_wdata[8:0]; + c_format_conv_ctrl:begin + format_conv_ctrl <= cfg_wdata[0]; + end + c_ct_coeff_0: regs_ct_coeff0 <= cfg_wdata[10:0]; + c_ct_coeff_1: regs_ct_coeff1 <= cfg_wdata[10:0]; + c_ct_coeff_2: regs_ct_coeff2 <= cfg_wdata[10:0]; + c_ct_coeff_3: regs_ct_coeff3 <= cfg_wdata[10:0]; + c_ct_coeff_4: regs_ct_coeff4 <= cfg_wdata[10:0]; + c_ct_coeff_5: regs_ct_coeff5 <= cfg_wdata[10:0]; + c_ct_coeff_6: regs_ct_coeff6 <= cfg_wdata[10:0]; + c_ct_coeff_7: regs_ct_coeff7 <= cfg_wdata[10:0]; + c_ct_coeff_8: regs_ct_coeff8 <= cfg_wdata[10:0]; + c_ct_offset_r:regs_ct_offset_r <= cfg_wdata[c_dw_si-1:0]; + c_ct_offset_g:regs_ct_offset_g <= cfg_wdata[c_dw_si-1:0]; + c_ct_offset_b:regs_ct_offset_b <= cfg_wdata[c_dw_si-1:0]; + c_imsc:begin + regs_isp_imsc <= cfg_wdata[c_irq_bw-1:0]; + end + c_icr:begin + regs_isp_icr <= cfg_wdata[c_irq_bw-1:0]; + end + c_isr:begin + regs_isp_isr <= cfg_wdata[c_irq_bw-1:0]; + end + c_isp_err_clear:begin + regs_err_clr <= {cfg_wdata[c_isp_err_bw-1:0]}; + end + default: begin end + endcase + end + end + end + end + end + always @(*) begin + cfg_rdata = 32'd0; + if (cfg_val & cfg_rd) begin + case (viv_s6[11:0]) + c_ctrl:begin + cfg_rdata = {regs_disable_isp_clk, + 9'd0, + regs_statistic_3a_sel, + 6'd0, + regs_csm_c_range, + regs_csm_y_range, + regs_dgain_enable, + regs_gamma_out_enable, + 1'b0, + 1'b0, + viv_s0, + 1'b0, + regs_awb_enable, + 1'b0, + regs_inform_enable, + regs_isp_mode, + regs_isp_enable}; + end + c_acq_prop:begin + cfg_rdata = {12'd0, + regs_input_pin_map, + 2'd0, + regs_input_selection, + regs_field_inv, + regs_field_selection, + regs_ccir_seq, + regs_conv_422, + regs_bayer_pat, + regs_vsync_pol, + regs_hsync_pol, + regs_sample_edge}; + end + c_acq_h_offs:begin + cfg_rdata = {17'd0, regs_acq_h_offs}; + end + c_acq_v_offs:begin + cfg_rdata = {18'd0,regs_acq_v_offs}; + end + c_acq_h_size:begin + cfg_rdata = {17'd0,regs_acq_h_size}; + end + c_acq_v_size:begin + cfg_rdata = {18'd0,regs_acq_v_size}; + end + c_cc_coeff_0: cfg_rdata = {23'd0,regs_cc_coeff0}; + c_cc_coeff_1: cfg_rdata = {23'd0,regs_cc_coeff1}; + c_cc_coeff_2: cfg_rdata = {23'd0,regs_cc_coeff2}; + c_cc_coeff_3: cfg_rdata = {23'd0,regs_cc_coeff3}; + c_cc_coeff_4: cfg_rdata = {23'd0,regs_cc_coeff4}; + c_cc_coeff_5: cfg_rdata = {23'd0,regs_cc_coeff5}; + c_cc_coeff_6: cfg_rdata = {23'd0,regs_cc_coeff6}; + c_cc_coeff_7: cfg_rdata = {23'd0,regs_cc_coeff7}; + c_cc_coeff_8: cfg_rdata = {23'd0,regs_cc_coeff8}; + c_format_conv_ctrl: cfg_rdata = {31'd0,format_conv_ctrl}; + c_ct_coeff_0: cfg_rdata = {21'd0,regs_ct_coeff0}; + c_ct_coeff_1: cfg_rdata = {21'd0,regs_ct_coeff1}; + c_ct_coeff_2: cfg_rdata = {21'd0,regs_ct_coeff2}; + c_ct_coeff_3: cfg_rdata = {21'd0,regs_ct_coeff3}; + c_ct_coeff_4: cfg_rdata = {21'd0,regs_ct_coeff4}; + c_ct_coeff_5: cfg_rdata = {21'd0,regs_ct_coeff5}; + c_ct_coeff_6: cfg_rdata = {21'd0,regs_ct_coeff6}; + c_ct_coeff_7: cfg_rdata = {21'd0,regs_ct_coeff7}; + c_ct_coeff_8: cfg_rdata = {21'd0,regs_ct_coeff8}; + c_ct_offset_r:cfg_rdata = {{32-c_dw_si{1'b0}},regs_ct_offset_r}; + c_ct_offset_g:cfg_rdata = {{32-c_dw_si{1'b0}},regs_ct_offset_g}; + c_ct_offset_b:cfg_rdata = {{32-c_dw_si{1'b0}},regs_ct_offset_b}; + c_out_h_offs:begin + cfg_rdata = {18'd0,regs_out_h_offs}; + end + c_out_v_offs:begin + cfg_rdata = {18'd0,regs_out_v_offs}; + end + c_out_h_size:begin + cfg_rdata = {17'd0,regs_out_h_size}; + end + c_out_v_size:begin + cfg_rdata = {18'd0,regs_out_v_size}; + end + c_demosaic:begin + cfg_rdata = {21'd0, + regs_demosaic_bypass,2'b0, + regs_demosaic_th}; + end + c_out_h_offs_shd: cfg_rdata = {18'd0,out_h_offs_shd}; + c_out_v_offs_shd: cfg_rdata = {18'd0,out_v_offs_shd}; + c_out_h_size_shd: cfg_rdata = {17'd0,out_h_size_shd}; + c_out_v_size_shd: cfg_rdata = {18'd0,out_v_size_shd}; + c_dgain_0:begin + cfg_rdata = {viv_s2,viv_s5}; + end + c_dgain_1:begin + cfg_rdata = {viv_s3,viv_s4}; + end + c_dgain_0_shd: begin + cfg_rdata = {regs_dgain_r,regs_dgain_b}; + end + c_dgain_1_shd: begin + cfg_rdata = {regs_dgain_gr,regs_dgain_gb}; + end + c_imsc:begin + cfg_rdata = {{(32-c_irq_bw){1'b0}},regs_isp_imsc}; + end + c_ris:begin + cfg_rdata = {{(32-c_irq_bw){1'b0}},regs_isp_ris}; + end + c_mis:begin + cfg_rdata = {{(32-c_irq_bw){1'b0}},regs_isp_mis}; + end + c_gamma_out_mod:begin + cfg_rdata = {31'd0, regs_equ_segm}; + end + c_gamma_out_y0: cfg_rdata = {{32-c_dw_do{1'b0}},regs_gamma_out_y0 }; + c_gamma_out_y1: cfg_rdata = {{32-c_dw_do{1'b0}},regs_gamma_out_y1 }; + c_gamma_out_y2: cfg_rdata = {{32-c_dw_do{1'b0}},regs_gamma_out_y2 }; + c_gamma_out_y3: cfg_rdata = {{32-c_dw_do{1'b0}},regs_gamma_out_y3 }; + c_gamma_out_y4: cfg_rdata = {{32-c_dw_do{1'b0}},regs_gamma_out_y4 }; + c_gamma_out_y5: cfg_rdata = {{32-c_dw_do{1'b0}},regs_gamma_out_y5 }; + c_gamma_out_y6: cfg_rdata = {{32-c_dw_do{1'b0}},regs_gamma_out_y6 }; + c_gamma_out_y7: cfg_rdata = {{32-c_dw_do{1'b0}},regs_gamma_out_y7 }; + c_gamma_out_y8: cfg_rdata = {{32-c_dw_do{1'b0}},regs_gamma_out_y8 }; + c_gamma_out_y9: cfg_rdata = {{32-c_dw_do{1'b0}},regs_gamma_out_y9 }; + c_gamma_out_y10: cfg_rdata = {{32-c_dw_do{1'b0}},regs_gamma_out_y10}; + c_gamma_out_y11: cfg_rdata = {{32-c_dw_do{1'b0}},regs_gamma_out_y11}; + c_gamma_out_y12: cfg_rdata = {{32-c_dw_do{1'b0}},regs_gamma_out_y12}; + c_gamma_out_y13: cfg_rdata = {{32-c_dw_do{1'b0}},regs_gamma_out_y13}; + c_gamma_out_y14: cfg_rdata = {{32-c_dw_do{1'b0}},regs_gamma_out_y14}; + c_gamma_out_y15: cfg_rdata = {{32-c_dw_do{1'b0}},regs_gamma_out_y15}; + c_gamma_out_y16: cfg_rdata = {{32-c_dw_do{1'b0}},regs_gamma_out_y16}; + c_awb_prop:begin + cfg_rdata = {regs_awb_meas_mode, + 28'd0, + regs_awb_max_en, + regs_awb_mode }; + end + c_awb_h_offs_old:begin + cfg_rdata = {19'd0,regs_awb_h_offs }; + end + c_awb_v_offs_old:begin + cfg_rdata = {19'd0,regs_awb_v_offs }; + end + c_awb_h_size_old:begin + cfg_rdata = {18'd0,regs_awb_h_size }; + end + c_awb_v_size_old:begin + cfg_rdata = {18'd0,regs_awb_v_size }; + end + c_awb_frames:begin + cfg_rdata = {29'd0,regs_awb_frames }; + end + c_awb_ref:begin + cfg_rdata = {16'd0, + regs_awb_ref_cr__max_r, + regs_awb_ref_cb__max_b}; + end + c_awb_thres:begin + cfg_rdata = {regs_awb_max_y, + regs_awb_min_y__max_g, + regs_awb_max_csum, + regs_awb_min_c}; + end + c_awb_white_cnt:begin + cfg_rdata = {{32-c_white_cnt{1'b0}},awb_white_cnt}; + end + c_awb_mean:begin + cfg_rdata = {8'd0, + awb_mean_y__g, + awb_mean_cb__b, + awb_mean_cr__r}; + end + c_isp_err:begin + cfg_rdata = {{32-c_isp_err_bw{1'b0}},isp_err_status}; + end + c_tpg_global : begin + cfg_rdata = {20'h0,tpg_resolution,max_sync,def_sync,color_depth,cfa_pat,img_num,tpg_en}; + end + c_tpg_total : begin cfg_rdata = {4'h0,htotal_in,vtotal_in}; + end + c_tpg_act : begin cfg_rdata = {4'h0,h_act_in,v_act_in}; + end + c_tpg_fp : begin cfg_rdata = {4'h0,fp_h_in,fp_v_in}; + end + c_tpg_bp : begin cfg_rdata = {4'h0,bp_h_in,bp_v_in}; + end + c_tpg_w : begin cfg_rdata = {4'h0,hs_w_in,vs_w_in}; + end + c_tpg_gap : begin cfg_rdata = {4'h0,pix_gap_in,line_gap_in}; + end + c_tpg_gap_std : begin cfg_rdata = {18'h0,pix_gap_std_in}; + end + c_tpg_seed : cfg_rdata = random_seed_in; + c_tpg_frm_num : cfg_rdata = {16'h0,frm_num}; + default: begin + if (viv_s7 || viv_s9) + cfg_rdata = cfg_filt_rdata; + else if (viv_s8) + cfg_rdata = cfg_bls_rdata; + else if(viv_s10) + cfg_rdata = cfg_exp_rdata; + else + cfg_rdata = 32'd0; + end + endcase + end + end +reg viv_s11; +always @(posedge clk or negedge rst_clk_n) begin +if(~rst_clk_n) + viv_s11<= 1'b0; +else if(regs_gen_cfg_upd) + viv_s11<= 1'b1; +else if(frame_end_dgain) + viv_s11<= 1'b0; +end +wire viv_s12=viv_s11&&frame_end_dgain; +always @(posedge clk or negedge rst_clk_n) begin + if(~rst_clk_n)begin + regs_dgain_r <=16'h100; + regs_dgain_gr<=16'h100; + regs_dgain_gb<=16'h100; + regs_dgain_b <=16'h100; + end + else if(regs_cfg_upd||viv_s12)begin + regs_dgain_r <=viv_s2 ; + regs_dgain_gr<=viv_s3; + regs_dgain_gb<=viv_s4; + regs_dgain_b <=viv_s5 ; + end +end + always @(posedge clk_cfg or negedge reset_cfg_n) begin + if(~reset_cfg_n) begin + cfg_ack <= 1'b0; + end + else begin + if(cfg_ack) begin + cfg_ack <= 1'b0; + end + else begin + if(cfg_val) begin + cfg_ack <= 1'b1; + end + end + end + end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_rgb_yuv_sel.v b/ispyocto/rtl/ispyocto/vsisp_isp_rgb_yuv_sel.v new file mode 100644 index 0000000..563c72e --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_isp_rgb_yuv_sel.v
@@ -0,0 +1,108 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_isp_rgb_yuv_sel + ( + if_sel, + yuv_dma_sel, + s2_val, + s2_data, + s2_h_end, + s2_v_end, + s2_ack, + s1_val, + s1_data, + s1_h_end, + s1_v_end, + s1_ack, + s0_val, + s0_data, + s0_h_end, + s0_v_end, + s0_ack, + out_val, + out_data, + out_h_end, + out_v_end, + out_ack + ); +`include "vsisp_isp.vh" + input if_sel; + input yuv_dma_sel; + input s2_val; + input [2*c_dw_do-1:0] s2_data; + input s2_h_end; + input s2_v_end; + output s2_ack; + input s1_val; + input [2*c_dw_do-1:0] s1_data; + input s1_h_end; + input s1_v_end; + output s1_ack; + input s0_val; + input [2*c_dw_do-1:0] s0_data; + input s0_h_end; + input s0_v_end; + output s0_ack; + output out_val; + output [2*c_dw_do-1:0] out_data; + output out_h_end; + output out_v_end; + input out_ack; + reg out_val; + reg [2*c_dw_do-1:0] out_data; + reg out_h_end; + reg out_v_end; + reg s0_ack; + reg s1_ack; + reg s2_ack; + always @(*) begin + if (yuv_dma_sel) begin + out_val = s2_val; + out_h_end = s2_h_end; + out_v_end = s2_v_end; + out_data = s2_data; + s2_ack = out_ack; + s1_ack = 1'b1; + s0_ack = 1'b1; + end + else if (if_sel) begin + out_val = s1_val; + out_h_end = s1_h_end; + out_v_end = s1_v_end; + out_data = s1_data; + s2_ack = 1'b1; + s1_ack = out_ack; + s0_ack = 1'b1; + end + else begin + out_val = s0_val; + out_h_end = s0_h_end; + out_v_end = s0_v_end; + out_data = s0_data; + s2_ack = 1'b1; + s1_ack = 1'b1; + s0_ack = out_ack; + end + end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_srsz_c_wrapper.v b/ispyocto/rtl/ispyocto/vsisp_isp_srsz_c_wrapper.v new file mode 100644 index 0000000..65a29df --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_isp_srsz_c_wrapper.v
@@ -0,0 +1,424 @@ +//**************************************************************************** +// +// Copyright 2023 Vivante Corp. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_isp_srsz_c_wrapper(GC_CONTROL,cEn0_,mcReg_registerTimingControl,reset_,rwAddr0,rwclk0,wData0,wEn0_,rData0); + /*NAME: mmsx_isp_srsz_c_wrapper_sw0x32x320 */ + input [15:0] GC_CONTROL; + input cEn0_; + input [31:0] mcReg_registerTimingControl; + input reset_; + input [9-1:0] rwAddr0; + input rwclk0; + input [32-1:0] wData0; + input wEn0_; + output [32-1:0] rData0; + wire [32-1:0] rData0; + `ifdef FPGA + reg [71:0] fpgaWData_0_0; + wire [71:0] fpgaRData_0_0; + always @(wData0[31:0]) + fpgaWData_0_0 = 72'd0 | wData0[31:0]; + wire [71:0] fpgaRData_0_0_0; + assign rData0[31:0] = fpgaRData_0_0_0[32-1:0]; + wire wEn0Stack_0_0_0_ = wEn0_; + `ifdef FPGA_ALTERA + FPGA_ALTERA_RF2P512W72B ram_0_0_0 ( + .address_a ({rwAddr0}), + .address_b ({rwAddr0}), + .clock_a (rwclk0), + .clock_b (rwclk0), + .data_a (72'b0), + .data_b (fpgaWData_0_0[71:0]), + .rden_a (~cEn0_ && (cEn0_|wEn0_)), + .rden_b (1'b0), + .wren_a (1'b0), + .wren_b (~(cEn0_|wEn0_)), + .q_a (fpgaRData_0_0_0[71:0]), + .q_b ()); + `else + FPGA_RF2P512W72B ram_0_0_0 ( + .DOA (fpgaRData_0_0_0[63:0]), + .DOPA (fpgaRData_0_0_0[71:64]), + .DOB (), + .DOPB (), + .ADDRA ({rwAddr0}), + .DIA (64'd0), + .DIPA (8'd0), + .ENA (~cEn0_ && (cEn0_|wEn0_)), + .CLKA (rwclk0), + .SSRA (1'b0), + .WEA (2'd0), + .ADDRB ({rwAddr0}), + .DIB (fpgaWData_0_0[63:0]), + .DIPB (fpgaWData_0_0[71:64]), + .ENB (~(cEn0_|wEn0_)), + .CLKB (rwclk0), + .SSRB (1'b0), + .WEB ({~(cEn0_|wEn0_),~(cEn0_|wEn0_)})); + `endif + `else + `ifdef OLD_MEM_MODEL + `else + `ifdef AQ_TSMC28HPM_RAM_MODEL + wire [9-1:0] BM_AA = {9{1'b0}}; + wire [9-1:0] BM_AB = {9{1'b0}}; + wire BM_CENA = 1'b0; + wire BM_CENB = 1'b0; + wire BM_BENA = 1'b0; + wire [32-1:0] BM_DB = {32{1'b0}}; + wire BM_EN = 1'b0; + wire [1-1:0] BM_WENB = {1{1'b1}}; + wire BIST = (BM_EN & BM_BENA); + wire enableClock = ~(cEn0_) | GC_CONTROL[4]; + `ifdef CG_IN_RAM + wire rwclk0En = rwclk0; + `else + wire rwclk0En; + vsisp_GC_CG_MOD GC_CG_RW(.enable(enableClock), .ck_in(rwclk0), .ck_out(rwclk0En), .test(GC_CONTROL[0])); + `endif + wire [32-1:0] ramRData0; + reg [32-1:0] ramWData0; + always @(wData0[31:0]) begin + ramWData0[32-1:0] = wData0[31:0]; + end + assign rData0[31:0] = ramRData0[32-1:0]; + RF1P320W32B2S ram0 ( + .Q(ramRData0), + .CLK(rwclk0En), + .WEB(wEn0_), + .CEB(cEn0_), + .BWEB({32{1'b0}}), + .A(rwAddr0), + .D(ramWData0), + .SLP(mcReg_registerTimingControl[0]), + .SD(mcReg_registerTimingControl[20]), + .AM(BM_AA), + .DM({BM_DB[31:0]}), + .BWEBM({32{1'b0}}), + .WEBM(BM_CENB), + .CEBM(BM_CENA), + .BIST(BIST), + .TURBO(1'b1), + .RTSEL(2'b01)); + `else + `ifdef AQ_SEC14LPP_RAM_MODEL + wire enableClock = ~(cEn0_) | GC_CONTROL[4]; + `ifdef CG_IN_RAM + wire rwclk0En = rwclk0; + `else + wire rwclk0En; + vsisp_GC_CG_MOD GC_CG_RW(.enable(enableClock), .ck_in(rwclk0), .ck_out(rwclk0En), .test(GC_CONTROL[0])); + `endif + wire [32-1:0] ramRData0; + reg [32-1:0] ramWData0; + always @(wData0[31:0]) begin + ramWData0[32-1:0] = wData0[31:0]; + end + assign rData0[31:0] = ramRData0[32-1:0]; + RF1P320W32B2M1BK0S0HD0WM ram0 ( + .Q(ramRData0), + .CLK(rwclk0En), + .CEN(cEn0_), + .GWEN(wEn0_), + .A(rwAddr0), + .D(ramWData0), + .STOV(1'b0), + .EMA(3'b010), + .EMAW(2'b01), + .EMAS(1'b0), + .RET1N(1'b1)); + `else + `ifdef AQ_TSMC7FF_RAM_MODEL + wire enableClock = ~(cEn0_) | GC_CONTROL[4]; + `ifdef CG_IN_RAM + wire rwclk0En = rwclk0; + `else + wire rwclk0En; + vsisp_GC_CG_MOD GC_CG_RW(.enable(enableClock), .ck_in(rwclk0), .ck_out(rwclk0En), .test(GC_CONTROL[0])); + `endif + wire [32-1:0] ramRData0; + reg [32-1:0] ramWData0; + always @(wData0[31:0]) begin + ramWData0[32-1:0] = wData0[31:0]; + end + assign rData0[31:0] = ramRData0[32-1:0]; + RF1P384W32B4MNSEG0S0HD0WM ram0 ( + .CLK(rwclk0En), + .Q(ramRData0), + .CEB(cEn0_), + .WEB(wEn0_), + .A(rwAddr0), + .D(ramWData0), + .SD(mcReg_registerTimingControl[20]), + .DSLP(mcReg_registerTimingControl[21]), + .DSLPLV(1'b0), + .PUDELAY_DSLP(), + .PUDELAY_SD(), + .RTSEL(2'b10), + .WTSEL(2'b01), + .DFTBYP(1'b0), + .SE(1'b0), + .SIC(1'b0), + .SID(2'b00), + .SOC(), + .SOD()); + `else + `ifdef AQ_TSMC12FFC_RAM_MODEL + wire enableClock = ~(cEn0_) | GC_CONTROL[4]; + `ifdef CG_IN_RAM + wire rwclk0En = rwclk0; + `else + wire rwclk0En; + vsisp_GC_CG_MOD GC_CG_RW(.enable(enableClock), .ck_in(rwclk0), .ck_out(rwclk0En), .test(GC_CONTROL[0])); + `endif + wire [32-1:0] ramRData0; + reg [32-1:0] ramWData0; + always @(wData0[31:0]) begin + ramWData0[32-1:0] = wData0[31:0]; + end + assign rData0[31:0] = ramRData0[32-1:0]; + RF1P416W32B4MSSEG0S0HD0WM ram0 ( + .CLK(rwclk0En), + .Q(ramRData0), + .CEB(cEn0_), + .WEB(wEn0_), + .A(rwAddr0), + .D(ramWData0), + .RTSEL(2'b01), + .WTSEL(2'b01)); + `else + wire enableClock = ~(cEn0_) | GC_CONTROL[4]; + `ifdef CG_IN_RAM + wire rwclk0En = rwclk0; + `else + wire rwclk0En; + vsisp_GC_CG_MOD GC_CG_RW(.enable(enableClock), .ck_in(rwclk0), .ck_out(rwclk0En), .test(GC_CONTROL[0])); + `endif + wire [32-1:0] ramRData0; + reg [32-1:0] ramWData0; + always @(wData0[31:0]) begin + ramWData0[32-1:0] = wData0[31:0]; + end + assign rData0[31:0] = ramRData0[32-1:0]; + vsisp_RAM1P320W32B_SS ram0 ( + .Q(ramRData0), + .CLK(rwclk0En), + .CEB(cEn0_), + .A(rwAddr0), + .WEB(wEn0_), + .BWEB({32{1'b0}}), + .D(ramWData0), + .CLKEN(enableClock), + .TESTEN(GC_CONTROL[0])); + `endif + `endif + `endif + `endif + `endif + `endif + `ifdef VIVANTE_CHECK_RAM_USAGE + `ifdef VIVANTE_SIM_END + reg [1-1:0] writeHappened; + reg readHappened; + initial begin + writeHappened = 1 'd0; + readHappened = 1'd0; + end + always @(posedge rwclk0) begin + readHappened <= (readHappened | (~cEn0_ & wEn0_)); + end + always @(posedge rwclk0) begin + if(~wEn0_ & ~cEn0_) begin + writeHappened <= 1'b1; + end + end + initial begin + @`VIVANTE_SIM_END; + if(&{readHappened,writeHappened}) begin + $display ("RAM USAGE: vsisp_isp_srsz_c_wrapper at %m fully exercised."); + end else begin + $display ("RAM USAGE: vsisp_isp_srsz_c_wrapper at %m not fully exercised."); + end + end + `endif + `endif + `ifdef ASSERT_ON_RAM + assert_never wrong_rwaddr0 (rwclk0, reset_, (~cEn0_ & (rwAddr0 > 320-1))); + assert_never_unknown #(0, 9, 0, "address is unknown") address_unknown0(rwclk0, reset_, ~cEn0_, rwAddr0); + assert_never_unknown #(0, 1, 0, "ram enable is unknown") ram_enable_unknown0(rwclk0, reset_, 1'b1, cEn0_); + assert_never_unknown #(0, 32, 0, "config signal is unknown") config_unknown_rw0(rwclk0, reset_, 1'b1, mcReg_registerTimingControl[32-1:0]); + assert_never_unknown #(0, 1, 0, "control signal is unknown") control_unknown_rw0(rwclk0, reset_, 1'b1, GC_CONTROL[4]); + `endif + `ifdef VIVANTE_CHECK_RAM_USAGE2 + `ifdef VIVANTE_RAM_MONITOR_END + parameter rAddr0Num = 8-1; + reg [rAddr0Num:0] rAddr0_r; + reg [31:0] rAddr0Cnt[0:rAddr0Num]; + parameter wAddr0Num = 8-1; + reg [wAddr0Num:0] wAddr0_r; + reg [31:0] wAddr0Cnt[0:wAddr0Num]; + parameter wData0Num = 29-1; + reg [wData0Num:0] wData0_r; + reg [31:0] wData0Cnt[0:wData0Num]; + parameter rData0Num = 29-1; + reg [rData0Num:0] rData0_r; + reg [31:0] rData0Cnt[0:rData0Num]; + initial + begin + #1; + @`VIVANTE_RAM_MONITOR_END + begin + integer i; + for(i=0;i<=rAddr0Num;i=i+1) + begin + $gethierachy(3, i, rAddr0Cnt[i]); + end + for(i=0;i<=wAddr0Num;i=i+1) + begin + $gethierachy(4, i, wAddr0Cnt[i]); + end + for(i=0;i<=wData0Num;i=i+1) + begin + $gethierachy(2, i, wData0Cnt[i]); + end + for(i=0;i<=rData0Num;i=i+1) + begin + $gethierachy(1, i, rData0Cnt[i]); + end + end + end + always @(posedge rwclk0 or negedge reset_) + begin + if(!reset_) + begin + rAddr0_r = 'b0; + rData0_r = 'b0; + end + else if(wEn0_&!cEn0_) + begin + rAddr0_r = rwAddr0; + rData0_r = rData0; + end + end + always @(posedge rwclk0 or negedge reset_) + begin + if(!reset_) + begin + integer i; + for(i=0;i<=rAddr0Num;i=i+1) + begin + rAddr0Cnt[i] = 'b0; + end + end + else if(wEn0_&!cEn0_) + begin + integer i; + for(i=0;i<=rAddr0Num;i=i+1) + begin + if(rAddr0_r[i]^rwAddr0[i]) + begin + rAddr0Cnt[i] = rAddr0Cnt[i] + 1; + end + end + end + end + always @(posedge rwclk0 or negedge reset_) + begin + if(!reset_) + begin + integer i; + for(i=0;i<=rData0Num;i=i+1) + begin + rData0Cnt[i] = 'b0; + end + end + else if(wEn0_&!cEn0_) + begin + integer i; + for(i=0;i<=rData0Num;i=i+1) + begin + if(rData0_r[i]^rData0[i]) + begin + rData0Cnt[i] = rData0Cnt[i] + 1; + end + end + end + end + always @(posedge rwclk0 or negedge reset_) + begin + if(!reset_) + begin + wAddr0_r = 'b0; + wData0_r = 'b0; + end + else if((!wEn0_)&(!cEn0_)) + begin + wAddr0_r = rwAddr0; + wData0_r = wData0; + end + end + always @(posedge rwclk0 or negedge reset_) + begin + if(!reset_) + begin + integer i; + for(i=0;i<=wAddr0Num;i=i+1) + begin + wAddr0Cnt[i] = 'b0; + end + end + else if((!wEn0_)&(!cEn0_)) + begin + integer i; + for(i=0;i<=wAddr0Num;i=i+1) + begin + if(wAddr0_r[i]^rwAddr0[i]) + begin + wAddr0Cnt[i] = wAddr0Cnt[i] + 1; + end + end + end + end + always @(posedge rwclk0 or negedge reset_) + begin + if(!reset_) + begin + integer i; + for(i=0;i<=wData0Num;i=i+1) + begin + wData0Cnt[i] = 'b0; + end + end + else if((!wEn0_)&(!cEn0_)) + begin + integer i; + for(i=0;i<=wData0Num;i=i+1) + begin + if(wData0_r[i]^wData0[i]) + begin + wData0Cnt[i] = wData0Cnt[i] + 1; + end + end + end + end + `endif + `endif +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_srsz_y_wrapper.v b/ispyocto/rtl/ispyocto/vsisp_isp_srsz_y_wrapper.v new file mode 100644 index 0000000..8b804a9 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_isp_srsz_y_wrapper.v
@@ -0,0 +1,424 @@ +//**************************************************************************** +// +// Copyright 2023 Vivante Corp. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_isp_srsz_y_wrapper(GC_CONTROL,cEn0_,mcReg_registerTimingControl,reset_,rwAddr0,rwclk0,wData0,wEn0_,rData0); + /*NAME: mmsx_isp_srsz_y_wrapper_sw0x32x320 */ + input [15:0] GC_CONTROL; + input cEn0_; + input [31:0] mcReg_registerTimingControl; + input reset_; + input [9-1:0] rwAddr0; + input rwclk0; + input [32-1:0] wData0; + input wEn0_; + output [32-1:0] rData0; + wire [32-1:0] rData0; + `ifdef FPGA + reg [71:0] fpgaWData_0_0; + wire [71:0] fpgaRData_0_0; + always @(wData0[31:0]) + fpgaWData_0_0 = 72'd0 | wData0[31:0]; + wire [71:0] fpgaRData_0_0_0; + assign rData0[31:0] = fpgaRData_0_0_0[32-1:0]; + wire wEn0Stack_0_0_0_ = wEn0_; + `ifdef FPGA_ALTERA + FPGA_ALTERA_RF2P512W72B ram_0_0_0 ( + .address_a ({rwAddr0}), + .address_b ({rwAddr0}), + .clock_a (rwclk0), + .clock_b (rwclk0), + .data_a (72'b0), + .data_b (fpgaWData_0_0[71:0]), + .rden_a (~cEn0_ && (cEn0_|wEn0_)), + .rden_b (1'b0), + .wren_a (1'b0), + .wren_b (~(cEn0_|wEn0_)), + .q_a (fpgaRData_0_0_0[71:0]), + .q_b ()); + `else + FPGA_RF2P512W72B ram_0_0_0 ( + .DOA (fpgaRData_0_0_0[63:0]), + .DOPA (fpgaRData_0_0_0[71:64]), + .DOB (), + .DOPB (), + .ADDRA ({rwAddr0}), + .DIA (64'd0), + .DIPA (8'd0), + .ENA (~cEn0_ && (cEn0_|wEn0_)), + .CLKA (rwclk0), + .SSRA (1'b0), + .WEA (2'd0), + .ADDRB ({rwAddr0}), + .DIB (fpgaWData_0_0[63:0]), + .DIPB (fpgaWData_0_0[71:64]), + .ENB (~(cEn0_|wEn0_)), + .CLKB (rwclk0), + .SSRB (1'b0), + .WEB ({~(cEn0_|wEn0_),~(cEn0_|wEn0_)})); + `endif + `else + `ifdef OLD_MEM_MODEL + `else + `ifdef AQ_TSMC28HPM_RAM_MODEL + wire [9-1:0] BM_AA = {9{1'b0}}; + wire [9-1:0] BM_AB = {9{1'b0}}; + wire BM_CENA = 1'b0; + wire BM_CENB = 1'b0; + wire BM_BENA = 1'b0; + wire [32-1:0] BM_DB = {32{1'b0}}; + wire BM_EN = 1'b0; + wire [1-1:0] BM_WENB = {1{1'b1}}; + wire BIST = (BM_EN & BM_BENA); + wire enableClock = ~(cEn0_) | GC_CONTROL[4]; + `ifdef CG_IN_RAM + wire rwclk0En = rwclk0; + `else + wire rwclk0En; + vsisp_GC_CG_MOD GC_CG_RW(.enable(enableClock), .ck_in(rwclk0), .ck_out(rwclk0En), .test(GC_CONTROL[0])); + `endif + wire [32-1:0] ramRData0; + reg [32-1:0] ramWData0; + always @(wData0[31:0]) begin + ramWData0[32-1:0] = wData0[31:0]; + end + assign rData0[31:0] = ramRData0[32-1:0]; + RF1P320W32B2S ram0 ( + .Q(ramRData0), + .CLK(rwclk0En), + .WEB(wEn0_), + .CEB(cEn0_), + .BWEB({32{1'b0}}), + .A(rwAddr0), + .D(ramWData0), + .SLP(mcReg_registerTimingControl[0]), + .SD(mcReg_registerTimingControl[20]), + .AM(BM_AA), + .DM({BM_DB[31:0]}), + .BWEBM({32{1'b0}}), + .WEBM(BM_CENB), + .CEBM(BM_CENA), + .BIST(BIST), + .TURBO(1'b1), + .RTSEL(2'b01)); + `else + `ifdef AQ_SEC14LPP_RAM_MODEL + wire enableClock = ~(cEn0_) | GC_CONTROL[4]; + `ifdef CG_IN_RAM + wire rwclk0En = rwclk0; + `else + wire rwclk0En; + vsisp_GC_CG_MOD GC_CG_RW(.enable(enableClock), .ck_in(rwclk0), .ck_out(rwclk0En), .test(GC_CONTROL[0])); + `endif + wire [32-1:0] ramRData0; + reg [32-1:0] ramWData0; + always @(wData0[31:0]) begin + ramWData0[32-1:0] = wData0[31:0]; + end + assign rData0[31:0] = ramRData0[32-1:0]; + RF1P320W32B2M1BK0S0HD0WM ram0 ( + .Q(ramRData0), + .CLK(rwclk0En), + .CEN(cEn0_), + .GWEN(wEn0_), + .A(rwAddr0), + .D(ramWData0), + .STOV(1'b0), + .EMA(3'b010), + .EMAW(2'b01), + .EMAS(1'b0), + .RET1N(1'b1)); + `else + `ifdef AQ_TSMC7FF_RAM_MODEL + wire enableClock = ~(cEn0_) | GC_CONTROL[4]; + `ifdef CG_IN_RAM + wire rwclk0En = rwclk0; + `else + wire rwclk0En; + vsisp_GC_CG_MOD GC_CG_RW(.enable(enableClock), .ck_in(rwclk0), .ck_out(rwclk0En), .test(GC_CONTROL[0])); + `endif + wire [32-1:0] ramRData0; + reg [32-1:0] ramWData0; + always @(wData0[31:0]) begin + ramWData0[32-1:0] = wData0[31:0]; + end + assign rData0[31:0] = ramRData0[32-1:0]; + RF1P384W32B4MNSEG0S0HD0WM ram0 ( + .CLK(rwclk0En), + .Q(ramRData0), + .CEB(cEn0_), + .WEB(wEn0_), + .A(rwAddr0), + .D(ramWData0), + .SD(mcReg_registerTimingControl[20]), + .DSLP(mcReg_registerTimingControl[21]), + .DSLPLV(1'b0), + .PUDELAY_DSLP(), + .PUDELAY_SD(), + .RTSEL(2'b10), + .WTSEL(2'b01), + .DFTBYP(1'b0), + .SE(1'b0), + .SIC(1'b0), + .SID(2'b00), + .SOC(), + .SOD()); + `else + `ifdef AQ_TSMC12FFC_RAM_MODEL + wire enableClock = ~(cEn0_) | GC_CONTROL[4]; + `ifdef CG_IN_RAM + wire rwclk0En = rwclk0; + `else + wire rwclk0En; + vsisp_GC_CG_MOD GC_CG_RW(.enable(enableClock), .ck_in(rwclk0), .ck_out(rwclk0En), .test(GC_CONTROL[0])); + `endif + wire [32-1:0] ramRData0; + reg [32-1:0] ramWData0; + always @(wData0[31:0]) begin + ramWData0[32-1:0] = wData0[31:0]; + end + assign rData0[31:0] = ramRData0[32-1:0]; + RF1P416W32B4MSSEG0S0HD0WM ram0 ( + .CLK(rwclk0En), + .Q(ramRData0), + .CEB(cEn0_), + .WEB(wEn0_), + .A(rwAddr0), + .D(ramWData0), + .RTSEL(2'b01), + .WTSEL(2'b01)); + `else + wire enableClock = ~(cEn0_) | GC_CONTROL[4]; + `ifdef CG_IN_RAM + wire rwclk0En = rwclk0; + `else + wire rwclk0En; + vsisp_GC_CG_MOD GC_CG_RW(.enable(enableClock), .ck_in(rwclk0), .ck_out(rwclk0En), .test(GC_CONTROL[0])); + `endif + wire [32-1:0] ramRData0; + reg [32-1:0] ramWData0; + always @(wData0[31:0]) begin + ramWData0[32-1:0] = wData0[31:0]; + end + assign rData0[31:0] = ramRData0[32-1:0]; + vsisp_RAM1P320W32B_SS ram0 ( + .Q(ramRData0), + .CLK(rwclk0En), + .CEB(cEn0_), + .A(rwAddr0), + .WEB(wEn0_), + .BWEB({32{1'b0}}), + .D(ramWData0), + .CLKEN(enableClock), + .TESTEN(GC_CONTROL[0])); + `endif + `endif + `endif + `endif + `endif + `endif + `ifdef VIVANTE_CHECK_RAM_USAGE + `ifdef VIVANTE_SIM_END + reg [1-1:0] writeHappened; + reg readHappened; + initial begin + writeHappened = 1 'd0; + readHappened = 1'd0; + end + always @(posedge rwclk0) begin + readHappened <= (readHappened | (~cEn0_ & wEn0_)); + end + always @(posedge rwclk0) begin + if(~wEn0_ & ~cEn0_) begin + writeHappened <= 1'b1; + end + end + initial begin + @`VIVANTE_SIM_END; + if(&{readHappened,writeHappened}) begin + $display ("RAM USAGE: vsisp_isp_srsz_y_wrapper at %m fully exercised."); + end else begin + $display ("RAM USAGE: vsisp_isp_srsz_y_wrapper at %m not fully exercised."); + end + end + `endif + `endif + `ifdef ASSERT_ON_RAM + assert_never wrong_rwaddr0 (rwclk0, reset_, (~cEn0_ & (rwAddr0 > 320-1))); + assert_never_unknown #(0, 9, 0, "address is unknown") address_unknown0(rwclk0, reset_, ~cEn0_, rwAddr0); + assert_never_unknown #(0, 1, 0, "ram enable is unknown") ram_enable_unknown0(rwclk0, reset_, 1'b1, cEn0_); + assert_never_unknown #(0, 32, 0, "config signal is unknown") config_unknown_rw0(rwclk0, reset_, 1'b1, mcReg_registerTimingControl[32-1:0]); + assert_never_unknown #(0, 1, 0, "control signal is unknown") control_unknown_rw0(rwclk0, reset_, 1'b1, GC_CONTROL[4]); + `endif + `ifdef VIVANTE_CHECK_RAM_USAGE2 + `ifdef VIVANTE_RAM_MONITOR_END + parameter rAddr0Num = 8-1; + reg [rAddr0Num:0] rAddr0_r; + reg [31:0] rAddr0Cnt[0:rAddr0Num]; + parameter wAddr0Num = 8-1; + reg [wAddr0Num:0] wAddr0_r; + reg [31:0] wAddr0Cnt[0:wAddr0Num]; + parameter wData0Num = 29-1; + reg [wData0Num:0] wData0_r; + reg [31:0] wData0Cnt[0:wData0Num]; + parameter rData0Num = 29-1; + reg [rData0Num:0] rData0_r; + reg [31:0] rData0Cnt[0:rData0Num]; + initial + begin + #1; + @`VIVANTE_RAM_MONITOR_END + begin + integer i; + for(i=0;i<=rAddr0Num;i=i+1) + begin + $gethierachy(3, i, rAddr0Cnt[i]); + end + for(i=0;i<=wAddr0Num;i=i+1) + begin + $gethierachy(4, i, wAddr0Cnt[i]); + end + for(i=0;i<=wData0Num;i=i+1) + begin + $gethierachy(2, i, wData0Cnt[i]); + end + for(i=0;i<=rData0Num;i=i+1) + begin + $gethierachy(1, i, rData0Cnt[i]); + end + end + end + always @(posedge rwclk0 or negedge reset_) + begin + if(!reset_) + begin + rAddr0_r = 'b0; + rData0_r = 'b0; + end + else if(wEn0_&!cEn0_) + begin + rAddr0_r = rwAddr0; + rData0_r = rData0; + end + end + always @(posedge rwclk0 or negedge reset_) + begin + if(!reset_) + begin + integer i; + for(i=0;i<=rAddr0Num;i=i+1) + begin + rAddr0Cnt[i] = 'b0; + end + end + else if(wEn0_&!cEn0_) + begin + integer i; + for(i=0;i<=rAddr0Num;i=i+1) + begin + if(rAddr0_r[i]^rwAddr0[i]) + begin + rAddr0Cnt[i] = rAddr0Cnt[i] + 1; + end + end + end + end + always @(posedge rwclk0 or negedge reset_) + begin + if(!reset_) + begin + integer i; + for(i=0;i<=rData0Num;i=i+1) + begin + rData0Cnt[i] = 'b0; + end + end + else if(wEn0_&!cEn0_) + begin + integer i; + for(i=0;i<=rData0Num;i=i+1) + begin + if(rData0_r[i]^rData0[i]) + begin + rData0Cnt[i] = rData0Cnt[i] + 1; + end + end + end + end + always @(posedge rwclk0 or negedge reset_) + begin + if(!reset_) + begin + wAddr0_r = 'b0; + wData0_r = 'b0; + end + else if((!wEn0_)&(!cEn0_)) + begin + wAddr0_r = rwAddr0; + wData0_r = wData0; + end + end + always @(posedge rwclk0 or negedge reset_) + begin + if(!reset_) + begin + integer i; + for(i=0;i<=wAddr0Num;i=i+1) + begin + wAddr0Cnt[i] = 'b0; + end + end + else if((!wEn0_)&(!cEn0_)) + begin + integer i; + for(i=0;i<=wAddr0Num;i=i+1) + begin + if(wAddr0_r[i]^rwAddr0[i]) + begin + wAddr0Cnt[i] = wAddr0Cnt[i] + 1; + end + end + end + end + always @(posedge rwclk0 or negedge reset_) + begin + if(!reset_) + begin + integer i; + for(i=0;i<=wData0Num;i=i+1) + begin + wData0Cnt[i] = 'b0; + end + end + else if((!wEn0_)&(!cEn0_)) + begin + integer i; + for(i=0;i<=wData0Num;i=i+1) + begin + if(wData0_r[i]^wData0[i]) + begin + wData0Cnt[i] = wData0Cnt[i] + 1; + end + end + end + end + `endif + `endif +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_tpg_cfg.v b/ispyocto/rtl/ispyocto/vsisp_isp_tpg_cfg.v new file mode 100644 index 0000000..d598154 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_isp_tpg_cfg.v
@@ -0,0 +1,685 @@ +//**************************************************************************** +// +// Copyright 2023 Vivante Corp. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_isp_tpg_cfg +( + input wire clk, + input wire rst_n, + input wire tpg_en, + input wire [2:0] img_num, + input wire [1:0] cfa_pat, + input wire [1:0] color_depth, + input wire def_sync, + input wire max_sync, + input wire [1:0] tpg_resolution, + input wire [15:0] frame_num, + input wire [13:0] vtotal_in, + input wire [13:0] htotal_in, + input wire [13:0] v_act_in, + input wire [13:0] h_act_in, + input wire [13:0] fp_v_in, + input wire [13:0] fp_h_in, + input wire [13:0] bp_v_in, + input wire [13:0] bp_h_in, + input wire [13:0] vs_w_in, + input wire [13:0] hs_w_in, + input wire [13:0] line_gap_in, + input wire [13:0] pix_gap_in, + input wire [13:0] pix_gap_std_in, + input wire [31:0] random_seed_in, + output reg [ 15:0] cfa_out, + output reg vs_out, + output reg hs_out, + output reg vde_out, + output reg hde_out +); +wire [31:0] viv_s0; +wire [13:0] viv_s1; +wire [13:0] viv_s2; +wire viv_s3; +wire viv_s4; +wire viv_s5; +wire viv_s6; +wire viv_s7; +wire viv_s8; +reg [13:0] viv_s9; +reg [13:0] viv_s10; +reg [13:0] viv_s11; +reg [13:0] viv_s12; +reg [13:0] viv_s13; +reg [13:0] viv_s14; +reg [13:0] viv_s15; +reg [13:0] viv_s16; +reg [13:0] viv_s17; +reg [13:0] viv_s18; +reg [13:0] viv_s19; +reg [13:0] viv_s20; +reg [13:0] viv_s21; +reg [13:0] viv_s22; +reg [13:0] viv_s23; +reg [7:0] viv_s24; +reg [7:0] viv_s25; +reg [7:0] viv_s26; +reg [13:0] viv_s27; +reg viv_s28; +reg viv_s29; +reg viv_s30; +reg viv_s31; +reg viv_s32; +reg viv_s33; +reg [7:0] viv_s34; +reg viv_s35; +reg viv_s36; +reg viv_s37; +reg viv_s38; +reg viv_s39; +reg viv_s40; +reg viv_s41; +reg viv_s42; +reg viv_s43; +vsisp_isp_pseudo_random_gen u_random_gen +( + .q (viv_s0[31:0]), + .clk (clk), + .rst_n (rst_n), + .random_seed_en(viv_s8), + .ce (viv_s6), + .seed (random_seed_in[31:0]) +); +always @(*) +begin + case(tpg_resolution[1:0]) + 2'b00: begin + viv_s9[13:0] = 14'd1968; + viv_s10[13:0] = 14'd2844; + viv_s11[13:0] = 14'd1080; + viv_s12[13:0] = 14'd1920; + viv_s17[13:0] = 14'd2; + viv_s18[13:0] = 14'd308; + viv_s19[13:0] = 14'd360; + viv_s20[13:0] = 14'd640; + viv_s21[13:0] = 14'd240; + viv_s13[13:0] = 14'd5; + viv_s14[13:0] = 14'd308; + viv_s15[13:0] = 14'd881; + viv_s16[13:0] = 14'd308; + end + 2'b01: begin + viv_s9[13:0] = 14'd1968; + viv_s10[13:0] = 14'd2844; + viv_s11[13:0] = 14'd720; + viv_s12[13:0] = 14'd1280; + viv_s17[13:0] = 14'd2; + viv_s18[13:0] = 14'd521; + viv_s19[13:0] = 14'd240; + viv_s20[13:0] = 14'd426; + viv_s21[13:0] = 14'd160; + viv_s13[13:0] = 14'd5; + viv_s14[13:0] = 14'd521; + viv_s15[13:0] = 14'd1241; + viv_s16[13:0] = 14'd521; + end + 2'b10: begin + viv_s9[13:0] = 14'd3048; + viv_s10[13:0] = 14'd4764; + viv_s11[13:0] = 14'd2160; + viv_s12[13:0] = 14'd3840; + viv_s17[13:0] = 14'd2; + viv_s18[13:0] = 14'd308; + viv_s19[13:0] = 14'd720; + viv_s20[13:0] = 14'd1280; + viv_s21[13:0] = 14'd480; + viv_s13[13:0] = 14'd5; + viv_s14[13:0] = 14'd308; + viv_s15[13:0] = 14'd881; + viv_s16[13:0] = 14'd308; + end + 2'b11: begin + viv_s9[13:0] = vtotal_in[13:0]; + viv_s10[13:0] = htotal_in[13:0]; + viv_s11[13:0] = v_act_in[13:0]; + viv_s12[13:0] = h_act_in[13:0]; + viv_s17[13:0] = vs_w_in[13:0]; + viv_s18[13:0] = hs_w_in[13:0]; + viv_s19[13:0] = line_gap_in[13:0]; + viv_s20[13:0] = pix_gap_in[13:0]; + viv_s21[13:0] = pix_gap_std_in[13:0]; + viv_s13[13:0] = fp_v_in[13:0]; + viv_s14[13:0] = fp_h_in[13:0]; + viv_s15[13:0] = bp_v_in[13:0]; + viv_s16[13:0] = bp_h_in[13:0]; + end + default:begin + viv_s9[13:0] = 14'h0; + viv_s10[11:0] = 12'h0; + viv_s11[13:0] = 14'h0; + viv_s12[13:0] = 14'h0; + viv_s13[13:0] = 14'h0; + viv_s14[13:0] = 14'h0; + viv_s15[13:0] = 14'h0; + viv_s16[13:0] = 14'h0; + viv_s17[13:0] = 14'h0; + viv_s18[13:0] = 14'h0; + viv_s19[13:0] = 14'h0; + viv_s20[13:0] = 14'h0; + viv_s21[13:0] = 14'h0; + end + endcase +end +assign viv_s1[13:0] = viv_s13[13:0] + viv_s17[13:0] + viv_s15[13:0]; +assign viv_s2[13:0] = viv_s14[13:0] + viv_s18[13:0] + viv_s16[13:0]; +always @(posedge clk or negedge rst_n) +begin + if(!rst_n) + viv_s43 <= 1'b0; + else + viv_s43 <= tpg_en; +end +assign viv_s8 = tpg_en && (~viv_s43); +always @(posedge clk or negedge rst_n) +begin + if(!rst_n) + viv_s22[13:0] <= 14'b0; + else + if(tpg_en) + begin + if(viv_s3) + viv_s22[13:0] <= 14'b0; + else + viv_s22[13:0] <= viv_s22[13:0]+1'b1; + end +end +assign viv_s3 = (viv_s22[13:0] == (viv_s10[13:0]-1'b1)) && tpg_en; +always @(posedge clk or negedge rst_n) +begin + if(!rst_n) + viv_s23[13:0] <= 14'b0; + else + if(tpg_en) + begin + if(viv_s3) + begin + if(viv_s4) + viv_s23[13:0] <= 14'b0; + else + viv_s23[13:0] <= viv_s23[13:0] + 1'b1; + end + end +end +assign viv_s4 = (viv_s23[13:0] == (viv_s9[13:0]-1'b1)) && viv_s3; +always @(posedge clk or negedge rst_n) +begin + if(!rst_n) + begin + viv_s24 <= 8'b0; + viv_s25 <= 8'b0; + viv_s26 <= 8'b0; + end + else + if(!viv_s6) + begin + viv_s24 <= 8'b0; + viv_s25 <= 8'b0; + viv_s26 <= 8'b0; + end + else + case(img_num) + 3'd0: begin + if(viv_s23<(viv_s1+viv_s19)) + begin + if(viv_s22<(viv_s2+viv_s20)) + begin + viv_s24 <= 8'hfc; + viv_s25 <= 8'h0; + viv_s26 <= 8'h0; + end + else + if(viv_s22<(viv_s2+{viv_s20,1'b0})) + begin + viv_s24 <= 8'h0; + viv_s25 <= 8'hfc; + viv_s26 <= 8'h0; + end + else + begin + viv_s24 <= 8'h0; + viv_s25 <= 8'h0; + viv_s26 <= 8'hfc; + end + end + else + if(viv_s23<(viv_s1+{viv_s19,1'b0})) + begin + if(viv_s22<(viv_s2+viv_s20)) + begin + viv_s24 <= 8'h0; + viv_s25 <= 8'hfc; + viv_s26 <= 8'h0; + end + else + if(viv_s22<(viv_s2+{viv_s20,1'b0})) + begin + viv_s24 <= 8'h0; + viv_s25 <= 8'h0; + viv_s26 <= 8'hfc; + end + else + begin + viv_s24 <= 8'hfc; + viv_s25 <= 8'h0; + viv_s26 <= 8'h0; + end + end + else + begin + if(viv_s22<(viv_s2+viv_s20)) + begin + viv_s24 <= 8'h0; + viv_s25 <= 8'h0; + viv_s26 <= 8'hfc; + end + else + if(viv_s22<(viv_s2+{viv_s20,1'b0})) + begin + viv_s24 <= 8'hfc; + viv_s25 <= 8'h0; + viv_s26 <= 8'h0; + end + else + begin + viv_s24 <= 8'h0; + viv_s25 <= 8'hfc; + viv_s26 <= 8'h0; + end + end + end + 3'd1: begin + if(viv_s22<(viv_s2+viv_s21)) + begin + viv_s24 <= 8'hfc; + viv_s25 <= 8'hfc; + viv_s26 <= 8'hfc; + end + else + if(viv_s22<(viv_s2+{viv_s21,1'b0})) + begin + viv_s24 <= 8'hfc; + viv_s25 <= 8'hfc; + viv_s26 <= 8'h0; + end + else + if(viv_s22<(viv_s2+{viv_s21,1'b0})+viv_s21) + begin + viv_s24 <= 8'h0; + viv_s25 <= 8'hfc; + viv_s26 <= 8'hfc; + end + else + if(viv_s22<(viv_s2+{viv_s21,2'b0})) + begin + viv_s24 <= 8'h0; + viv_s25 <= 8'hfc; + viv_s26 <= 8'h0; + end + else + if(viv_s22<(viv_s2+{viv_s21,2'b0})+viv_s21) + begin + viv_s24 <= 8'hfc; + viv_s25 <= 8'h0; + viv_s26 <= 8'hfc; + end + else + if(viv_s22<(viv_s2+{viv_s21,2'b0})+{viv_s21,1'b0}) + begin + viv_s24 <= 8'hfc; + viv_s25 <= 8'h0; + viv_s26 <= 8'h0; + end + else + if(viv_s22<(viv_s2+{viv_s21,2'b0})+{viv_s21,1'b0}+viv_s21) + begin + viv_s24 <= 8'h0; + viv_s25 <= 8'h0; + viv_s26 <= 8'hfc; + end + else + begin + viv_s24 <= 8'h0; + viv_s25 <= 8'h0; + viv_s26 <= 8'h0; + end + end + 3'd2: begin + if(viv_s22<(viv_s2+viv_s21)) + begin + viv_s24 <= 8'hfc; + viv_s25 <= 8'hfc; + viv_s26 <= 8'hfc; + end + else + if(viv_s22<(viv_s2+{viv_s21,1'b0})) + begin + viv_s24 <= 8'hd8; + viv_s25 <= 8'hd8; + viv_s26 <= 8'hd8; + end + else + if(viv_s22<(viv_s2+{viv_s21,1'b0})+viv_s21) + begin + viv_s24 <= 8'hb4; + viv_s25 <= 8'hb4; + viv_s26 <= 8'hb4; + end + else + if(viv_s22<(viv_s2+{viv_s21,2'b0})) + begin + viv_s24 <= 8'h90; + viv_s25 <= 8'h90; + viv_s26 <= 8'h90; + end + else + if(viv_s22<(viv_s2+{viv_s21,2'b0})+viv_s21) + begin + viv_s24 <= 8'h6c; + viv_s25 <= 8'h6c; + viv_s26 <= 8'h6c; + end + else + if(viv_s22<(viv_s2+{viv_s21,2'b0})+{viv_s21,1'b0}) + begin + viv_s24 <= 8'h48; + viv_s25 <= 8'h48; + viv_s26 <= 8'h48; + end + else + if(viv_s22<(viv_s2+{viv_s21,2'b0})+{viv_s21,1'b0}+viv_s21) + begin + viv_s24 <= 8'h24; + viv_s25 <= 8'h24; + viv_s26 <= 8'h24; + end + else + begin + viv_s24 <= 8'h0; + viv_s25 <= 8'h0; + viv_s26 <= 8'h0; + end + end + 3'd3: begin + if(((viv_s22==(viv_s2+viv_s21))|(viv_s22==(viv_s2+viv_s21+1'b1))) | + ((viv_s22==(viv_s2+{viv_s21,1'b0}))|(viv_s22==(viv_s2+{viv_s21,1'b0}+1'b1))) | + ((viv_s22==(viv_s2+{viv_s21,1'b0}+viv_s21))|(viv_s22==(viv_s2+{viv_s21,1'b0}+viv_s21+1'b1))) | + ((viv_s22==(viv_s2+{viv_s21,2'b0}))|(viv_s22==(viv_s2+{viv_s21,2'b0}+1'b1))) | + ((viv_s22==(viv_s2+{viv_s21,2'b0}+viv_s21))|(viv_s22==(viv_s2+{viv_s21,2'b0}+viv_s21+1'b1))) | + ((viv_s22==(viv_s2+{viv_s21,2'b0}+{viv_s21,1'b0}))|(viv_s22==(viv_s2+{viv_s21,2'b0}+{viv_s21,1'b0}+1'b1))) | + ((viv_s22==(viv_s2+{viv_s21,2'b0}+{viv_s21,1'b0}+viv_s21))|(viv_s22==(viv_s2+{viv_s21,2'b0}+{viv_s21,1'b0}+viv_s21+1'b1)))) + begin + viv_s24 <= 8'hfc; + viv_s25 <= 8'hfc; + viv_s26 <= 8'hfc; + end + else + if(((viv_s23==(viv_s1+viv_s21))|(viv_s23==(viv_s1+viv_s21+1'b1))) | + ((viv_s23==(viv_s1+{viv_s21,1'b0}))|(viv_s23==(viv_s1+{viv_s21,1'b0}+1'b1))) | + ((viv_s23==(viv_s1+{viv_s21,1'b0}+viv_s21))|(viv_s23==(viv_s1+{viv_s21,1'b0}+viv_s21+1'b1))) | + ((viv_s23==(viv_s1+{viv_s21,2'b0}))|(viv_s23==(viv_s1+{viv_s21,2'b0}+1'b1))) | + ((viv_s23==(viv_s1+{viv_s21,2'b0}+viv_s21))|(viv_s23==(viv_s1+{viv_s21,2'b0}+viv_s21+1'b1))) | + ((viv_s23==(viv_s1+{viv_s21,2'b0}+{viv_s21,1'b0}))|(viv_s23==(viv_s1+{viv_s21,2'b0}+{viv_s21,1'b0}+1'b1))) | + ((viv_s23==(viv_s1+{viv_s21,2'b0}+{viv_s21,1'b0}+viv_s21))|(viv_s23==(viv_s1+{viv_s21,2'b0}+{viv_s21,1'b0}+viv_s21+1'b1))) ) + begin + viv_s24 <= 8'hfc; + viv_s25 <= 8'hfc; + viv_s26 <= 8'hfc; + end + else + begin + viv_s24 <= 8'h0; + viv_s25 <= 8'h0; + viv_s26 <= 8'h0; + end + end + 3'd4: begin + viv_s24 <= viv_s0[27:20]; + viv_s25 <= viv_s0[17:10]; + viv_s26 <= viv_s0[ 7: 0]; + end + default:begin + viv_s24 <= 8'b0; + viv_s25 <= 8'b0; + viv_s26 <= 8'b0; + end + endcase +end +always @(posedge clk or negedge rst_n) +begin + if(!rst_n) + begin + viv_s28 <= 1'b1; + viv_s29 <= 1'b0; + end else + begin + if(viv_s22==viv_s14) + viv_s28 <= 1'b0; + else if(viv_s22==(viv_s14+viv_s18)) + viv_s28 <= 1'b1; + else if(viv_s22==viv_s2-1'b1) + viv_s29 <= 1'b1; + else if(viv_s22==viv_s27) + viv_s29 <= 1'b0; + end +end +always @(posedge clk or negedge rst_n) +begin + if(!rst_n) + viv_s27 <= 14'b0; + else + viv_s27 <= (viv_s2+viv_s12-1'b1); +end +always @(posedge clk or negedge rst_n) +begin + if(!rst_n) + begin + viv_s30 <= 1'b1; + viv_s31 <= 1'b0; + end + else + begin + if((viv_s23==viv_s13)&(viv_s22==viv_s14)) + viv_s30 <= 1'b0; + else + if((viv_s23==(viv_s13+viv_s17))&(viv_s22==viv_s14)) + viv_s30 <= 1'b1; + else + if((viv_s23==viv_s1)&(viv_s22==viv_s2-1'b1)) + viv_s31 <= 1'b1; + else + if((viv_s23==(viv_s1+viv_s11-1'b1))&(viv_s22==viv_s27)) + viv_s31 <= 1'b0; + end +end +assign viv_s5 = ((viv_s22>=viv_s2-1'b1) & (viv_s22<=viv_s27)) & + ((viv_s23>=viv_s1) & (viv_s23<=(viv_s1+viv_s11-1'b1))); +assign viv_s6 = viv_s31&viv_s29; +assign viv_s7 = viv_s41&viv_s37; +always @(posedge clk or negedge rst_n) +begin + if(!rst_n) + viv_s32 <= 1'b0; + else + if(!vde_out) + viv_s32 <= 1'b0; + else + if((!viv_s36)&hs_out) + viv_s32 <= ~viv_s32; +end +always @(posedge clk or negedge rst_n) +begin + if(!rst_n) + viv_s33 <= 1'b0; + else + if(!viv_s7) + viv_s33 <= 1'b0; + else + viv_s33 <= ~viv_s33; +end +always @(posedge clk or negedge rst_n) +begin + if(!rst_n) + viv_s34 <= 8'b0; + else + case(cfa_pat) + 2'd0: begin + case({viv_s32,viv_s33}) + 2'b00: viv_s34 <= viv_s24; + 2'b01: viv_s34 <= viv_s25; + 2'b10: viv_s34 <= viv_s25; + 2'b11: viv_s34 <= viv_s26; + default:viv_s34 <= 8'b0; + endcase + end + 2'd1: begin + case({viv_s32,viv_s33}) + 2'b00: viv_s34 <= viv_s25; + 2'b01: viv_s34 <= viv_s24; + 2'b10: viv_s34 <= viv_s26; + 2'b11: viv_s34 <= viv_s25; + default:viv_s34 <= 8'b0; + endcase + end + 2'd2: begin + case({viv_s32,viv_s33}) + 2'b00: viv_s34 <= viv_s25; + 2'b01: viv_s34 <= viv_s26; + 2'b10: viv_s34 <= viv_s24; + 2'b11: viv_s34 <= viv_s25; + default:viv_s34 <= 8'b0; + endcase + end + 2'd3: begin + case({viv_s32,viv_s33}) + 2'b00: viv_s34 <= viv_s26; + 2'b01: viv_s34 <= viv_s25; + 2'b10: viv_s34 <= viv_s25; + 2'b11: viv_s34 <= viv_s24; + default:viv_s34 <= 8'b0; + endcase + end + default:begin + case({viv_s32,viv_s33}) + 2'b00: viv_s34 <= 8'b0; + 2'b01: viv_s34 <= 8'b0; + 2'b10: viv_s34 <= 8'b0; + 2'b11: viv_s34 <= 8'b0; + default:viv_s34 <= 8'b0; + endcase + end + endcase +end +always @(posedge clk or negedge rst_n) +begin + if(!rst_n) + cfa_out <= 16'b0; + else + cfa_out <= {viv_s34,8'b0}; +end +wire viv_s44; +wire viv_s45; +wire viv_s46; +wire viv_s47; +wire viv_s48; +wire viv_s49; +reg [15:0] viv_s50; +always @(posedge clk or negedge rst_n) +begin + if(!rst_n) + viv_s50[15:0] <= 16'b0; + else + if(viv_s8) + viv_s50[15:0] <= 16'b0; + else + if(viv_s4) + viv_s50[15:0] <= viv_s50[15:0] + 1'b1; +end +assign viv_s44 = (viv_s50[15:0] == (frame_num[15:0]-1'b1)) && viv_s4; +assign viv_s45 = (frame_num[15:0] == 1'b0) ? 1'b1 : (viv_s50[15:0] < frame_num[15:0]); +assign viv_s46 = viv_s29 && viv_s45; +assign viv_s47 = viv_s28 && viv_s45; +assign viv_s48 = viv_s31 && viv_s45; +assign viv_s49 = viv_s30 && viv_s45; +always @(posedge clk or negedge rst_n) +begin + if(!rst_n) + viv_s35 <= 1'b1; + else + if(max_sync) + viv_s35 <= viv_s46; + else + viv_s35 <= viv_s47; +end +always @(posedge clk or negedge rst_n) +begin + if(!rst_n) + begin + viv_s37 <= 1'b0; + viv_s38 <= 1'b0; + hde_out <= 1'b0; + viv_s36 <= 1'b1; + hs_out <= 1'b1; + end + else + begin + viv_s37 <= viv_s46; + viv_s38 <= viv_s37; + hde_out <= viv_s38; + viv_s36 <= viv_s35; + hs_out <= viv_s36; + end +end +always @(posedge clk or negedge rst_n) +begin + if(!rst_n) + viv_s39 <= 1'b1; + else + if(max_sync) + viv_s39 <= viv_s48; + else + viv_s39 <= viv_s49; +end +always @(posedge clk or negedge rst_n) +begin + if(!rst_n) + begin + viv_s41 <= 1'b0; + viv_s42 <= 1'b0; + vde_out <= 1'b0; + viv_s40 <= 1'b1; + vs_out <= 1'b1; + end + else + begin + viv_s41 <= viv_s48; + viv_s42 <= viv_s41; + vde_out <= viv_s42; + viv_s40 <= viv_s39; + vs_out <= viv_s40; + end +end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_m4_clock_gating.v b/ispyocto/rtl/ispyocto/vsisp_m4_clock_gating.v new file mode 100644 index 0000000..35aed52 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_m4_clock_gating.v
@@ -0,0 +1,45 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_m4_clock_gating + ( + per_clk_i, + pdft_scan_mode_i, + gating_en_i, + clk_o); + input per_clk_i; + input pdft_scan_mode_i; + input gating_en_i; + output clk_o; + wire clk_o; + `ifdef FPGA + assign clk_o = per_clk_i; + `else + vsisp_GC_CG_MOD u_gc_cg_md + ( + .enable(gating_en_i), + .ck_in(per_clk_i), + .ck_out(clk_o), + .test(pdft_scan_mode_i)); + `endif +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_marvin_ctrl.v b/ispyocto/rtl/ispyocto/vsisp_marvin_ctrl.v new file mode 100644 index 0000000..9f8da94 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_marvin_ctrl.v
@@ -0,0 +1,311 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_marvin_ctrl + ( + clk, + reset_n, + ctrl_reset_clk_n, + m_hclk, + reset_m_hclk_n, + soft_rst_marvin, + paddr, + pwdata, + prdata, + pval, + prd, + pack, + cfg_addr, + cfg_wdata, + cfg_rd, + cfg_rdata_isp, + cfg_val_isp, + cfg_ack_isp, + cfg_rdata_mrsz, + cfg_val_mrsz, + cfg_ack_mrsz, + cfg_rdata_srsz, + cfg_val_srsz, + cfg_ack_srsz, + clk_isp, + clk_mrsz, + clk_srsz, + clk_mi, + clk_cfg_isp, + clk_cfg_mrsz, + clk_cfg_srsz, + soft_rst_isp, + soft_rst_yc, + soft_rst_mrsz, + soft_rst_srsz, + soft_rst_mi, + mi_clk_en_mhclk, + soft_rst_mi_mhclk, + isp_clk_en, + test_mode + ); + parameter c_marvin_id = 32'h00453017; +`include "vsisp_marvin_ctrl.vh" + input clk; + input reset_n; + input ctrl_reset_clk_n; + input m_hclk; + input reset_m_hclk_n; + output soft_rst_marvin; + input [c_paddr_word-1:0] paddr; + input [c_pwdata_word-1:0] pwdata; + output [c_prdata_word-1:0] prdata; + input pval; + input prd; + output pack; + output [c_cfg_addr_word-1:0] cfg_addr; + output [c_cfg_wdata_word-1:0] cfg_wdata; + output cfg_rd; + input [c_cfg_rdata32_word-1:0] cfg_rdata_isp; + output cfg_val_isp; + input cfg_ack_isp; + input [c_cfg_rdata32_word-1:0] cfg_rdata_mrsz; + output cfg_val_mrsz; + input cfg_ack_mrsz; + input [c_cfg_rdata32_word-1:0] cfg_rdata_srsz; + output cfg_val_srsz; + input cfg_ack_srsz; + output clk_isp; + output clk_mrsz; + output clk_srsz; + output clk_mi; + output mi_clk_en_mhclk; + output soft_rst_mi_mhclk; + output isp_clk_en; + output clk_cfg_isp; + output clk_cfg_mrsz; + output clk_cfg_srsz; + output soft_rst_isp; + output soft_rst_yc; + output soft_rst_mrsz; + output soft_rst_srsz; + output soft_rst_mi; + input test_mode; + reg [c_cfg_wdata_word-1:0] cfg_wdata; + reg cfg_rd; + reg [c_cfg_addr_word-1:0] cfg_addr; + wire viv_s0; + wire viv_s1; + wire viv_s2; + wire viv_s3; + wire [c_prdata_word-1:0] viv_s4; + wire viv_s5; + wire viv_s6; + wire viv_s7; + wire [c_prdata_word-1:0] viv_s8; + wire [c_iccl_word-1:0] viv_s9; + wire [c_ircl_word-1:0] viv_s10; + wire viv_s11; + wire viv_s12; + wire viv_s13; + wire viv_s14; + reg viv_s15; + reg viv_s16; + reg viv_s17; + reg viv_s18; + reg viv_s19; + reg viv_s20; + wire viv_s21; + wire viv_s22; + wire mi_clk_en_mhclk; + wire soft_rst_mi_mhclk; + vsisp_marvin_ctrl_pvci #( + .c_marvin_id(c_marvin_id) + ) u_marvin_ctrl_pvci + ( + .clk (clk), + .reset_n (ctrl_reset_clk_n), + .pval (pval), + .prd (prd), + .paddr (paddr), + .pwdata (pwdata), + .vi_iccl (viv_s9), + .pack_ctrl_off (viv_s6), + .prdata_ctrl_off (viv_s4), + .vi_ccl_out (viv_s5) + ); + vsisp_marvin_ctrl_pvcidis u_marvin_ctrl_pvcidis + ( + .clk (viv_s3), + .reset_n (ctrl_reset_clk_n), + .pval (pval), + .prd (prd), + .paddr (paddr), + .pwdata (pwdata), + .cfg_rdata_isp (cfg_rdata_isp), + .cfg_rdata_mrsz (cfg_rdata_mrsz), + .cfg_rdata_srsz (cfg_rdata_srsz), + .cfg_ack_isp (cfg_ack_isp), + .cfg_ack_mrsz (cfg_ack_mrsz), + .cfg_ack_srsz (cfg_ack_srsz), + .vi_iccl_out (viv_s9), + .vi_ircl_out (viv_s10), + .pack_ctrl_on (viv_s7), + .prdata_ctrl_on (viv_s8), + .cfg_val_mrsz (cfg_val_mrsz), + .cfg_val_srsz (cfg_val_srsz), + .cfg_val_isp (cfg_val_isp) + ); + vsisp_m4_clock_gating u_clock_gating_clk + ( + .per_clk_i(clk), + .pdft_scan_mode_i(test_mode), + .gating_en_i(!viv_s5), + .clk_o(viv_s3) + ); + vsisp_m4_clock_gating u_clock_gating_isp + ( + .per_clk_i(clk), + .pdft_scan_mode_i(test_mode), + .gating_en_i(viv_s9[0] & !viv_s5), + .clk_o(clk_isp) + ); + assign isp_clk_en = (viv_s9[0] & !viv_s5); + vsisp_m4_clock_gating u_clock_gating_mrsz + ( + .per_clk_i(clk), + .pdft_scan_mode_i(test_mode), + .gating_en_i(viv_s9[3] & !viv_s5), + .clk_o(clk_mrsz) + ); + vsisp_m4_clock_gating u_clock_gating_srsz + ( + .per_clk_i(clk), + .pdft_scan_mode_i(test_mode), + .gating_en_i(viv_s9[4] & !viv_s5), + .clk_o(clk_srsz) + ); + vsisp_m4_clock_gating u_clock_gating_mi + ( + .per_clk_i(clk), + .pdft_scan_mode_i(test_mode), + .gating_en_i(viv_s9[6] & !viv_s5), + .clk_o(clk_mi) + ); + vsisp_m4_clock_gating u_cfg_clock_gating_isp + ( + .per_clk_i(clk), + .pdft_scan_mode_i(test_mode), + .gating_en_i(viv_s0 & !viv_s5), + .clk_o(clk_cfg_isp) + ); + vsisp_m4_clock_gating u_cfg_clock_gating_mrsz + ( + .per_clk_i(clk), + .pdft_scan_mode_i(test_mode), + .gating_en_i(viv_s1 & !viv_s5), + .clk_o(clk_cfg_mrsz) + ); + vsisp_m4_clock_gating u_cfg_clock_gating_srsz + ( + .per_clk_i(clk), + .pdft_scan_mode_i(test_mode), + .gating_en_i(viv_s2 & !viv_s5), + .clk_o(clk_cfg_srsz) + ); + assign viv_s11 = viv_s9[0]; + assign viv_s12 = viv_s9[3]; + assign viv_s13 = viv_s9[4]; + assign viv_s0 = ((c_isp_start_addr <= paddr[11:8] < c_isp_end_addr) && pval && + viv_s11) ? 1'b1 : 1'b0; + assign viv_s1 = ((paddr[11:8] == c_mrsz_addr) && pval && + viv_s12) ? 1'b1 : 1'b0; + assign viv_s2 = ((paddr[13:7] == c_srsz_addr) && pval && + viv_s13) ? 1'b1 : 1'b0; + always @(posedge clk or negedge ctrl_reset_clk_n) begin + if (!ctrl_reset_clk_n) begin + cfg_wdata <= {c_cfg_wdata_word{1'b0}}; + cfg_rd <= 1'b0; + cfg_addr <= {c_paddr_word{1'b0}}; + end + else begin + cfg_wdata <= pwdata[c_cfg_wdata_word-1:0]; + cfg_rd <= prd; + cfg_addr <= paddr[c_paddr_word-1:0]; + end + end +vsisp_AQSync u_aqsync_soft_rst_mi( + .bitSync (viv_s21), + .clk (m_hclk), + .bitIn (viv_s10[6]), + .reset_ (reset_m_hclk_n) + ); +reg viv_s23; + always @(posedge clk or negedge ctrl_reset_clk_n) begin + if(~ctrl_reset_clk_n) + viv_s23 <= 1'b0; + else + viv_s23 <= viv_s9[6] & !viv_s5; + end + vsisp_AQSync u_aqsync_iccl_mi_en( + .bitSync (viv_s22), + .clk (m_hclk), + .bitIn (viv_s23), + .reset_ (reset_m_hclk_n) + ); + assign mi_clk_en_mhclk = viv_s22; + assign soft_rst_mi_mhclk = viv_s21; + assign pack = (viv_s6 || viv_s7) ? 1'b1 : 1'b0; + assign prdata = (viv_s6) ? viv_s4 : viv_s8; + assign soft_rst_isp = viv_s10[0]; + assign soft_rst_yc = viv_s10[2]; + assign soft_rst_mrsz = viv_s10[3]; + assign soft_rst_srsz = viv_s10[4]; + assign soft_rst_mi = viv_s10[6]; + assign soft_rst_marvin = viv_s20; + always @(posedge clk or negedge ctrl_reset_clk_n) begin + if (!ctrl_reset_clk_n) begin + viv_s15 <= 1'b0; + viv_s16 <= 1'b0; + viv_s17 <= 1'b0; + viv_s18 <= 1'b0; + viv_s19 <= 1'b0; + end + else begin + viv_s15 <= viv_s14; + viv_s16 <= viv_s15; + viv_s17 <= viv_s16; + viv_s18 <= viv_s17; + viv_s19 <= viv_s18; + end + end + vsisp_AQSync u_aqsync_soft_rst_marvin( + .bitSync (viv_s14), + .clk (clk), + .bitIn (viv_s10[7]), + .reset_ (ctrl_reset_clk_n) + ); + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + viv_s20 <= 1'b0; + end + else begin + viv_s20 <= viv_s19; + end + end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_marvin_ctrl_pvci.v b/ispyocto/rtl/ispyocto/vsisp_marvin_ctrl_pvci.v new file mode 100644 index 0000000..34b8627 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_marvin_ctrl_pvci.v
@@ -0,0 +1,272 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_marvin_ctrl_pvci + ( + clk, + reset_n, + pval, + prd, + paddr, + pwdata, + vi_iccl, + pack_ctrl_off, + prdata_ctrl_off, + vi_ccl_out); + parameter c_marvin_id = 32'h00453017; +`include "vsisp_marvin_ctrl.vh" +`include "vsisp_marvin_id.vh" + input clk; + input reset_n; + input [c_paddr_word-1:0] paddr; + input [c_pwdata_word-1:0] pwdata; + input pval; + input prd; + input [c_iccl_word-1:0] vi_iccl; + output [c_prdata_word-1:0] prdata_ctrl_off; + output pack_ctrl_off; + output vi_ccl_out; + reg [c_prdata_word-1:0] prdata_ctrl_off; + reg vi_ccl_out; + reg pack_ctrl_off; + wire viv_s0; + wire viv_s1; + wire viv_s2; + assign viv_s0 = !prd && pval; + assign viv_s1 = prd && pval; + assign viv_s2 = vi_ccl_out || !vi_iccl[0]; + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + vi_ccl_out <= 1'b0; + pack_ctrl_off <= 1'b0; + prdata_ctrl_off <= {c_prdata_word{1'b0}}; + end + else begin + if (pack_ctrl_off) begin + pack_ctrl_off <= 1'b0; + end + else begin + if (paddr[12:8] == c_ctrl_addr) begin + if (viv_s0) begin + case (paddr[7:0]) + c_vi_ccl_addr : begin + pack_ctrl_off <= 1'b1; + vi_ccl_out <= pwdata[2]; + end + c_isp_id_custom_id_addr : begin + pack_ctrl_off <= 1'b1; + end + c_isp_id_product_id_addr : begin + pack_ctrl_off <= 1'b1; + end + c_isp_id_chip_id_addr : begin + pack_ctrl_off <= 1'b1; + end + c_isp_id_eco_id_addr : begin + pack_ctrl_off <= 1'b1; + end + c_isp_id_chip_revision_addr : begin + pack_ctrl_off <= 1'b1; + end + c_isp_id_patch_revision_addr : begin + pack_ctrl_off <= 1'b1; + end + c_isp_id_chip_date_addr : begin + pack_ctrl_off <= 1'b1; + end + c_isp_id_chip_time_addr : begin + pack_ctrl_off <= 1'b1; + end + c_vi_id_rsv0_addr : begin + pack_ctrl_off <= 1'b1; + end + c_vi_id_rsv1_addr : begin + pack_ctrl_off <= 1'b1; + end + c_vi_id_rsv2_addr : begin + pack_ctrl_off <= 1'b1; + end + c_vi_id_rsv3_addr : begin + pack_ctrl_off <= 1'b1; + end + c_vi_id_rsv4_addr : begin + pack_ctrl_off <= 1'b1; + end + c_vi_id_rsv5_addr : begin + pack_ctrl_off <= 1'b1; + end + c_vi_id_rsv6_addr : begin + pack_ctrl_off <= 1'b1; + end + c_vi_id_rsv7_addr : begin + pack_ctrl_off <= 1'b1; + end + c_vi_iccl_addr : begin + if (vi_ccl_out) begin + pack_ctrl_off <= 1'b1; + end + end + c_vi_ircl_addr : begin + if (vi_ccl_out) begin + pack_ctrl_off <= 1'b1; + end + end + default: begin + pack_ctrl_off <= 1'b1; + end + endcase + end + else begin + if (viv_s1) begin + case (paddr[7:0]) + c_vi_ccl_addr : begin + pack_ctrl_off <= 1'b1; + prdata_ctrl_off <= {29'b0,vi_ccl_out, + vi_ccl_out,1'b0}; + end + c_isp_id_custom_id_addr : begin + pack_ctrl_off <= 1'b1; + prdata_ctrl_off <= c_isp_id_custom_id; + end + c_isp_id_product_id_addr : begin + pack_ctrl_off <= 1'b1; + prdata_ctrl_off <= c_isp_id_product_id; + end + c_isp_id_chip_id_addr : begin + pack_ctrl_off <= 1'b1; + prdata_ctrl_off <= c_isp_id_chip_id; + end + c_isp_id_eco_id_addr : begin + pack_ctrl_off <= 1'b1; + prdata_ctrl_off <= c_isp_id_eco_id; + end + c_isp_id_chip_revision_addr : begin + pack_ctrl_off <= 1'b1; + prdata_ctrl_off <= c_isp_id_chip_revision; + end + c_isp_id_patch_revision_addr : begin + pack_ctrl_off <= 1'b1; + prdata_ctrl_off <= c_isp_id_patch_revision; + end + c_isp_id_chip_date_addr : begin + pack_ctrl_off <= 1'b1; + prdata_ctrl_off <= c_isp_id_chip_date; + end + c_isp_id_chip_time_addr : begin + pack_ctrl_off <= 1'b1; + prdata_ctrl_off <= c_isp_id_chip_time; + end + c_vi_id_rsv0_addr : begin + pack_ctrl_off <= 1'b1; + prdata_ctrl_off <= c_marvin_id_rsv0; + end + c_vi_id_rsv1_addr : begin + pack_ctrl_off <= 1'b1; + prdata_ctrl_off <= c_marvin_id_rsv1; + end + c_vi_id_rsv2_addr : begin + pack_ctrl_off <= 1'b1; + prdata_ctrl_off <= c_marvin_id_rsv2; + end + c_vi_id_rsv3_addr : begin + pack_ctrl_off <= 1'b1; + prdata_ctrl_off <= c_marvin_id_rsv3; + end + c_vi_id_rsv4_addr : begin + pack_ctrl_off <= 1'b1; + prdata_ctrl_off <= c_marvin_id_rsv4; + end + c_vi_id_rsv5_addr : begin + pack_ctrl_off <= 1'b1; + prdata_ctrl_off <= c_marvin_id_rsv5; + end + c_vi_id_rsv6_addr : begin + pack_ctrl_off <= 1'b1; + prdata_ctrl_off <= c_marvin_id_rsv6; + end + c_vi_id_rsv7_addr : begin + pack_ctrl_off <= 1'b1; + prdata_ctrl_off <= c_marvin_id_rsv7; + end + c_vi_iccl_addr : begin + if (vi_ccl_out) begin + pack_ctrl_off <= 1'b1; + prdata_ctrl_off <= {32'hDEADDEAD}; + end + end + c_vi_ircl_addr : begin + if (vi_ccl_out) begin + pack_ctrl_off <= 1'b1; + prdata_ctrl_off <= {32'hDEADDEAD}; + end + end + default: begin + pack_ctrl_off <= 1'b1; + if (vi_ccl_out) begin + prdata_ctrl_off <= {32'hDEADDEAD}; + end else begin + prdata_ctrl_off <= 32'b0; + end + end + endcase + end + end + end + else if ((c_isp_start_addr <= paddr[12:8]) && (paddr[12:8] < c_isp_end_addr)) begin + if (pval) begin + if (viv_s2) begin + pack_ctrl_off <= 1'b1; + prdata_ctrl_off <= {32'hDEADDEAD}; + end + end + end + else if (paddr[12:8] == c_mrsz_addr) begin + if (pval) begin + if (vi_ccl_out || !vi_iccl[3]) begin + pack_ctrl_off <= 1'b1; + prdata_ctrl_off <= {32'hDEADDEAD}; + end + end + end + else if (paddr[12:7] == c_srsz_addr) begin + if (pval) begin + if (vi_ccl_out || !vi_iccl[4]) begin + pack_ctrl_off <= 1'b1; + prdata_ctrl_off <= {32'hDEADDEAD}; + end + end + end + else begin + if (pval) begin + if (vi_ccl_out) begin + prdata_ctrl_off <= {32'hDEADDEAD}; + end else begin + prdata_ctrl_off <= 32'b0; + end + pack_ctrl_off <= 1'b1; + end + end + end + end + end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_marvin_ctrl_pvcidis.v b/ispyocto/rtl/ispyocto/vsisp_marvin_ctrl_pvcidis.v new file mode 100644 index 0000000..b9b91ce --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_marvin_ctrl_pvcidis.v
@@ -0,0 +1,312 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_marvin_ctrl_pvcidis + ( + clk, + reset_n, + pval, + prd, + paddr, + pwdata, + cfg_ack_isp, + cfg_ack_mrsz, + cfg_ack_srsz, + cfg_rdata_isp, + cfg_rdata_mrsz, + cfg_rdata_srsz, + vi_iccl_out, + vi_ircl_out, + pack_ctrl_on, + prdata_ctrl_on, + cfg_val_mrsz, + cfg_val_srsz, + cfg_val_isp + ); +`include "vsisp_marvin_ctrl.vh" +`include "vsisp_marvin_id.vh" + input clk; + input reset_n; + input pval; + input prd; + input [c_paddr_word-1:0] paddr; + input [c_pwdata_word-1:0] pwdata; + input cfg_ack_isp; + input cfg_ack_mrsz; + input cfg_ack_srsz; + input [c_prdata_word-1:0] cfg_rdata_isp; + input [c_prdata_word-1:0] cfg_rdata_mrsz; + input [c_prdata_word-1:0] cfg_rdata_srsz; + output [c_iccl_word-1:0] vi_iccl_out; + output [c_ircl_word-1:0] vi_ircl_out; + output pack_ctrl_on; + output [c_prdata_word-1:0] prdata_ctrl_on; + output cfg_val_mrsz; + output cfg_val_srsz; + output cfg_val_isp; + reg [c_prdata_word-1:0] prdata_ctrl_on; + reg [c_iccl_word-1:0] vi_iccl_out; + reg [c_ircl_word-1:0] vi_ircl_out; + reg pack_ctrl_on; + reg cfg_val_mrsz; + reg cfg_val_srsz; + reg cfg_val_isp; + wire viv_s0; + wire viv_s1; + assign viv_s0 = !prd && pval; + assign viv_s1 = prd && pval; + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + vi_iccl_out <= 13'h1f7b; + vi_ircl_out <= {c_ircl_word{1'b0}}; + pack_ctrl_on <= 1'b0; + prdata_ctrl_on <= 32'h00000000; + cfg_val_mrsz <= 1'b0; + cfg_val_srsz <= 1'b0; + cfg_val_isp <= 1'b0; + end + else begin + if (cfg_val_isp) begin + if (cfg_ack_isp) begin + cfg_val_isp <= 1'b0; + end + end + if (cfg_val_mrsz) begin + if (cfg_ack_mrsz) begin + cfg_val_mrsz <= 1'b0; + end + end + if (cfg_val_srsz) begin + if (cfg_ack_srsz) begin + cfg_val_srsz <= 1'b0; + end + end + if (pack_ctrl_on) begin + pack_ctrl_on <= 1'b0; + end + else begin + if (paddr[12:8] == c_ctrl_addr) begin + if (viv_s0) begin + case (paddr[7:0]) + c_vi_iccl_addr : begin + pack_ctrl_on <= 1'b1; + vi_iccl_out <= pwdata[c_iccl_word-1:0]; + end + c_vi_ircl_addr : begin + pack_ctrl_on <= 1'b1; + vi_ircl_out <= pwdata[c_ircl_word-1:0]; + end + c_vi_ccl_addr : begin + end + c_isp_id_custom_id_addr : begin + end + c_isp_id_product_id_addr : begin + end + c_isp_id_chip_id_addr : begin + end + c_isp_id_eco_id_addr : begin + end + c_isp_id_chip_revision_addr : begin + end + c_isp_id_patch_revision_addr : begin + end + c_isp_id_chip_date_addr : begin + end + c_isp_id_chip_time_addr : begin + end + default: begin + pack_ctrl_on <= 1'b1; + end + endcase + end + else begin + if (viv_s1) begin + case (paddr[7:0]) + c_vi_iccl_addr : begin + pack_ctrl_on <= 1'b1; + prdata_ctrl_on <= {25'b0, + vi_iccl_out[6], + 1'b0, + vi_iccl_out[4], + vi_iccl_out[3], + 2'b0, + vi_iccl_out[0]}; + end + c_vi_ircl_addr : begin + pack_ctrl_on <= 1'b1; + prdata_ctrl_on <= {24'b0,vi_ircl_out[7:6],1'b0,vi_ircl_out[4:2],1'b0,vi_ircl_out[0]}; + end + c_vi_ccl_addr : begin + prdata_ctrl_on <= 32'h00000000; + end + c_isp_id_custom_id_addr : begin + pack_ctrl_on <= 1'b1; + prdata_ctrl_on <= c_isp_id_custom_id; + end + c_isp_id_product_id_addr : begin + pack_ctrl_on <= 1'b1; + prdata_ctrl_on <= c_isp_id_product_id; + end + c_isp_id_chip_id_addr : begin + pack_ctrl_on <= 1'b1; + prdata_ctrl_on <= c_isp_id_chip_id; + end + c_isp_id_eco_id_addr : begin + pack_ctrl_on <= 1'b1; + prdata_ctrl_on <= c_isp_id_eco_id; + end + c_isp_id_chip_revision_addr : begin + pack_ctrl_on <= 1'b1; + prdata_ctrl_on <= c_isp_id_chip_revision; + end + c_isp_id_patch_revision_addr : begin + pack_ctrl_on <= 1'b1; + prdata_ctrl_on <= c_isp_id_patch_revision; + end + c_isp_id_chip_date_addr : begin + pack_ctrl_on <= 1'b1; + prdata_ctrl_on <= c_isp_id_chip_date; + end + c_isp_id_chip_time_addr : begin + pack_ctrl_on <= 1'b1; + prdata_ctrl_on <= c_isp_id_chip_time; + end + c_vi_id_rsv0_addr : begin + pack_ctrl_on <= 1'b1; + prdata_ctrl_on <= c_marvin_id_rsv0; + end + c_vi_id_rsv1_addr : begin + pack_ctrl_on <= 1'b1; + prdata_ctrl_on <= c_marvin_id_rsv1; + end + c_vi_id_rsv2_addr : begin + pack_ctrl_on <= 1'b1; + prdata_ctrl_on <= c_marvin_id_rsv2; + end + c_vi_id_rsv3_addr : begin + pack_ctrl_on <= 1'b1; + prdata_ctrl_on <= c_marvin_id_rsv3; + end + c_vi_id_rsv4_addr : begin + pack_ctrl_on <= 1'b1; + prdata_ctrl_on <= c_marvin_id_rsv4; + end + c_vi_id_rsv5_addr : begin + pack_ctrl_on <= 1'b1; + prdata_ctrl_on <= c_marvin_id_rsv5; + end + c_vi_id_rsv6_addr : begin + pack_ctrl_on <= 1'b1; + prdata_ctrl_on <= c_marvin_id_rsv6; + end + c_vi_id_rsv7_addr : begin + pack_ctrl_on <= 1'b1; + prdata_ctrl_on <= c_marvin_id_rsv7; + end + default: begin + prdata_ctrl_on <= 32'h00000000; + pack_ctrl_on <= 1'b1; + end + endcase + end + end + end + else if ((c_isp_start_addr <= paddr[12:8]) && (paddr[12:8] < c_isp_end_addr)) begin + if (vi_iccl_out[0]) begin + if (viv_s0) begin + pack_ctrl_on <= 1'b1; + if (!cfg_ack_isp) begin + cfg_val_isp <= 1'b1; + pack_ctrl_on <= 1'b0; + end + end + else begin + if (viv_s1) begin + if (cfg_ack_isp) begin + pack_ctrl_on <= 1'b1; + prdata_ctrl_on <= cfg_rdata_isp; + end + else begin + pack_ctrl_on <= 1'b0; + cfg_val_isp <= 1'b1; + end + end + end + end + end + else if (paddr[12:8] == c_mrsz_addr) begin + if (vi_iccl_out[3]) begin + if (viv_s0) begin + pack_ctrl_on <= 1'b1; + if (!cfg_ack_mrsz) begin + cfg_val_mrsz <= 1'b1; + pack_ctrl_on <= 1'b0; + end + end + else begin + if (viv_s1) begin + if (cfg_ack_mrsz) begin + pack_ctrl_on <= 1'b1; + prdata_ctrl_on <= cfg_rdata_mrsz; + end + else begin + pack_ctrl_on <= 1'b0; + cfg_val_mrsz <= 1'b1; + end + end + end + end + end + else if (paddr[12:7] == c_srsz_addr) begin + if (vi_iccl_out[4]) begin + if (viv_s0) begin + pack_ctrl_on <= 1'b1; + if (!cfg_ack_srsz) begin + cfg_val_srsz <= 1'b1; + pack_ctrl_on <= 1'b0; + end + end + else begin + if (viv_s1) begin + if (cfg_ack_srsz) begin + pack_ctrl_on <= 1'b1; + prdata_ctrl_on <= cfg_rdata_srsz; + end + else begin + pack_ctrl_on <= 1'b0; + cfg_val_srsz <= 1'b1; + end + end + end + end + end + else begin + if (pval) begin + prdata_ctrl_on <= 32'h00000000; + pack_ctrl_on <= 1'b1; + end + end + end + end + end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_marvin_ctrl_reset_gen.v b/ispyocto/rtl/ispyocto/vsisp_marvin_ctrl_reset_gen.v new file mode 100644 index 0000000..3386f46 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_marvin_ctrl_reset_gen.v
@@ -0,0 +1,57 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_marvin_ctrl_reset_gen ( + reset_n, + clk, + soft_rst_i, + reset_out_n, + test_mode + ); + input reset_n; + input clk; + input soft_rst_i; + output reset_out_n; + input test_mode; + reg viv_s0; + reg viv_s1; + reg viv_s2; + reg viv_s3; + wire viv_s4; + assign viv_s4 = (test_mode) ? reset_n : (reset_n & !soft_rst_i); + always @(posedge clk or negedge viv_s4) begin + if (!viv_s4)begin + viv_s0 <= 1'b0; + viv_s1 <= 1'b0; + viv_s2 <= 1'b0; + viv_s3 <= 1'b0; + end + else begin + viv_s0 <= 1'b1; + viv_s1 <= viv_s0; + viv_s2 <= viv_s1; + viv_s3 <= viv_s2; + end + end + assign reset_out_n = (test_mode) ? reset_n : viv_s3; +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_marvin_dpsfe.v b/ispyocto/rtl/ispyocto/vsisp_marvin_dpsfe.v new file mode 100644 index 0000000..5497b93 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_marvin_dpsfe.v
@@ -0,0 +1,67 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_marvin_dpsfe +( clk, + reset_n, + soft_rst, + dpsfe_data_i, + dpsfe_val_i, + dpsfe_ack_o, + dpsfe_data_o, + dpsfe_val_o, + dpsfe_ack_i +); + parameter c_dpsfe_data_width = 11; + input clk; + input reset_n; + input soft_rst; + input [c_dpsfe_data_width-1:0] dpsfe_data_i; + input dpsfe_val_i; + output dpsfe_ack_o; + output [c_dpsfe_data_width-1:0] dpsfe_data_o; + output dpsfe_val_o; + input dpsfe_ack_i; + reg [c_dpsfe_data_width-1:0] dpsfe_data_o; + reg viv_s0; + wire viv_s1; + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + dpsfe_data_o <= {c_dpsfe_data_width{1'b0}}; + viv_s0 <= 1'b0; + end + else begin + if (soft_rst) begin + dpsfe_data_o <= {c_dpsfe_data_width{1'b0}}; + viv_s0 <= 1'b0; + end + else if (viv_s1) begin + viv_s0 <= dpsfe_val_i; + dpsfe_data_o <= dpsfe_data_i; + end + end + end + assign viv_s1 = dpsfe_ack_i | (~viv_s0); + assign dpsfe_ack_o = viv_s1; + assign dpsfe_val_o = viv_s0; +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_marvin_dpsfifo.v b/ispyocto/rtl/ispyocto/vsisp_marvin_dpsfifo.v new file mode 100644 index 0000000..4e519e2 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_marvin_dpsfifo.v
@@ -0,0 +1,66 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_marvin_dpsfifo +( clk, + reset_n, + soft_rst, + fifo_data_i, + fifo_val_i, + fifo_ack_o, + fifo_data_o, + fifo_val_o, + fifo_ack_i +); + parameter c_fifo_data_width = 11; + input clk; + input reset_n; + input soft_rst; + input [c_fifo_data_width-1:0] fifo_data_i; + input fifo_val_i; + output fifo_ack_o; + output [c_fifo_data_width-1:0] fifo_data_o; + output fifo_val_o; + input fifo_ack_i; + reg [c_fifo_data_width-1:0] viv_s0; + reg viv_s1; + wire viv_s2; + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + viv_s0 <= {c_fifo_data_width{1'b0}}; + viv_s1 <= 1'b0; + end + else if (soft_rst) begin + viv_s1 <= 1'b0; + end + else begin + viv_s1 <= (~fifo_ack_i && fifo_val_i) || (~fifo_ack_i && viv_s1) || (viv_s1 && fifo_val_i); + if (fifo_val_i && viv_s2) + viv_s0 <= fifo_data_i; + end + end + assign fifo_data_o = viv_s1 ? viv_s0 : fifo_data_i; + assign fifo_val_o = fifo_val_i || viv_s1; + assign viv_s2 = fifo_ack_i || ~viv_s1; + assign fifo_ack_o = viv_s2; +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_marvin_irq_handler.v b/ispyocto/rtl/ispyocto/vsisp_marvin_irq_handler.v new file mode 100644 index 0000000..6b7bd17 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_marvin_irq_handler.v
@@ -0,0 +1,211 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_marvin_irq_handler ( + clk, + reset_n, + jpeg_clk, + reset_jpeg_clk_n, + isp_hist_end_int, + isp_exp_end_int, + isp_fl_cap_int, + isp_afm_fin_int, + isp_afm_lum_of_int, + isp_afm_sum_of_int, + isp_sh_off_int, + isp_sh_on_int, + isp_fl_off_int, + isp_fl_on_int, + isp_h_start_int, + isp_v_start_int, + isp_frame_in_int, + isp_awb_done_int, + isp_vsm_done_int, + isp_size_err_int, + isp_frame_int, + isp_dataloss_int, + isp_off_int, + mi_mp_frame_end_int, + mi_bp_frame_end_int, + mi_sp_frame_end_int, + mi_mblk_line_int, + mi_fill_mp_y_int, + mi_wrap_mp_y_int, + mi_wrap_mp_cb_int, + mi_wrap_mp_cr_int, + mi_fill_bp_r_int, + mi_wrap_bp_r_int, + mi_wrap_bp_gr_int, + mi_wrap_bp_gb_int, + mi_wrap_bp_b_int, + mi_wrap_sp_y_int, + mi_wrap_sp_cb_int, + mi_wrap_sp_cr_int, + mi_dma_ready_int, + mi_mp_handshk_int, + mi_mp_handshk_sw_int, + jpeg_err_int, + jpeg_stat_int, + mi_irq, + isp_irq, + jpeg_stat_irq, + jpeg_err_irq + ); + input clk; + input reset_n; + input jpeg_clk; + input reset_jpeg_clk_n; + input isp_hist_end_int; + input isp_exp_end_int; + input isp_fl_cap_int; + input isp_afm_fin_int; + input isp_afm_lum_of_int; + input isp_afm_sum_of_int; + input isp_sh_off_int; + input isp_sh_on_int; + input isp_fl_off_int; + input isp_fl_on_int; + input isp_v_start_int; + input isp_h_start_int; + input isp_frame_in_int; + input isp_awb_done_int; + input isp_vsm_done_int; + input isp_size_err_int; + input isp_frame_int; + input isp_dataloss_int; + input isp_off_int; + input mi_mp_frame_end_int; + input mi_bp_frame_end_int; + input mi_sp_frame_end_int; + input mi_mblk_line_int; + input mi_fill_mp_y_int; + input mi_wrap_mp_y_int; + input mi_wrap_mp_cb_int; + input mi_wrap_mp_cr_int; + input mi_fill_bp_r_int; + input mi_wrap_bp_r_int; + input mi_wrap_bp_gr_int; + input mi_wrap_bp_gb_int; + input mi_wrap_bp_b_int; + input mi_wrap_sp_y_int; + input mi_wrap_sp_cb_int; + input mi_wrap_sp_cr_int; + input mi_dma_ready_int; + input mi_mp_handshk_int; + input mi_mp_handshk_sw_int; + input [10:0] jpeg_err_int; + input [1:0] jpeg_stat_int; + output isp_irq; + output mi_irq; + output jpeg_stat_irq; + output jpeg_err_irq; + reg mi_irq; + reg isp_irq; + reg jpeg_err_irq; + reg viv_s0; + reg viv_s1; + reg jpeg_stat_irq; + reg viv_s2; + reg viv_s3; + always @(posedge clk or negedge reset_n) begin + if(!reset_n)begin + isp_irq <= 1'b0; + mi_irq <= 1'b0; + end + else begin + isp_irq <= isp_hist_end_int || + isp_exp_end_int || + isp_fl_cap_int || + isp_afm_fin_int || + isp_afm_lum_of_int || + isp_afm_sum_of_int || + isp_sh_off_int || + isp_sh_on_int || + isp_fl_off_int || + isp_fl_on_int || + isp_h_start_int || + isp_v_start_int || + isp_size_err_int || + isp_frame_int || + isp_frame_in_int || + isp_dataloss_int || + isp_awb_done_int || + isp_vsm_done_int || + isp_off_int; + mi_irq <= mi_mp_frame_end_int || + mi_sp_frame_end_int || + mi_bp_frame_end_int || + mi_mblk_line_int || + mi_fill_mp_y_int || + mi_fill_bp_r_int || + mi_wrap_mp_y_int || + mi_wrap_mp_cb_int || + mi_wrap_mp_cr_int || + mi_wrap_bp_r_int || + mi_wrap_bp_gr_int || + mi_wrap_bp_gb_int || + mi_wrap_bp_b_int || + mi_wrap_sp_y_int || + mi_wrap_sp_cb_int || + mi_wrap_sp_cr_int || + mi_dma_ready_int || + mi_mp_handshk_int || + mi_mp_handshk_sw_int; + end + end + always @(posedge jpeg_clk or negedge reset_jpeg_clk_n) begin + if(!reset_jpeg_clk_n)begin + viv_s0 <= 1'b0; + viv_s2 <= 1'b0; + end + else begin + viv_s0 <= jpeg_err_int[0] || + jpeg_err_int[1] || + jpeg_err_int[2] || + jpeg_err_int[3] || + jpeg_err_int[4] || + jpeg_err_int[5] || + jpeg_err_int[6] || + jpeg_err_int[7] || + jpeg_err_int[8] || + jpeg_err_int[9] || + jpeg_err_int[10]; + viv_s2 <= jpeg_stat_int[0] || + jpeg_stat_int[1]; + end + end + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + viv_s1 <= 1'b0; + jpeg_err_irq <= 1'b0; + viv_s3 <= 1'b0; + jpeg_stat_irq <= 1'b0; + end + else begin + viv_s1 <= viv_s0; + jpeg_err_irq <= viv_s1; + viv_s3 <= viv_s2; + jpeg_stat_irq <= viv_s3; + end + end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_marvin_mi.v b/ispyocto/rtl/ispyocto/vsisp_marvin_mi.v new file mode 100644 index 0000000..ce15949 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_marvin_mi.v
@@ -0,0 +1,1742 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_marvin_mi + ( + clk, + reset_n, + soft_rst, + m_hclk, + reset_m_hclk_n, + m_hclk_cfg, + reset_m_hclk_cfg_n, + soft_rst_m_hclk, + jpeg_clk, + reset_jpeg_clk_n, + test_mode, + mp_lsb_alignment_out, + mp_output_format_out, + mp_little_endian_out, + cfg_mi_val, + cfg_mi_addr, + cfg_mi_rd, + cfg_mi_wdata, + cfg_mi_rdata, + cfg_mi_ack, + in_mp_y_val, + in_mp_y_data, + in_mp_y_h_end, + in_mp_y_v_end, + in_mp_y_cfg_upd, + in_mp_y_ack, + in_mp_cb_val, + in_mp_cb_data, + in_mp_cb_h_end, + in_mp_cb_v_end, + in_mp_cb_cfg_upd, + in_mp_cb_ack, + in_mp_cr_val, + in_mp_cr_data, + in_mp_cr_h_end, + in_mp_cr_v_end, + in_mp_cr_cfg_upd, + in_mp_cr_ack, + in_sp_y_val, + in_sp_y_data, + in_sp_y_h_end, + in_sp_y_v_end, + in_sp_y_cfg_upd, + in_sp_y_ack, + in_sp_cb_val, + in_sp_cb_data, + in_sp_cb_h_end, + in_sp_cb_v_end, + in_sp_cb_cfg_upd, + in_sp_cb_ack, + in_sp_cr_val, + in_sp_cr_data, + in_sp_cr_h_end, + in_sp_cr_v_end, + in_sp_cr_cfg_upd, + in_sp_cr_ack, + in_jpeg_val, + in_jpeg_data, + in_jpeg_end, + in_jpeg_byte_no, + in_jpeg_ack, + in_dp_data, + in_dp_end, + in_dp_val, + in_dp_ack, + in_bp_val, + in_bp_data, + in_bp_h_end, + in_bp_v_end, + in_bp_cfg_upd, + in_bp_ack, + in_bp_frame_end, + bayer_pat, + vci_out_m1_cmdval, + vci_out_m1_plen, + vci_out_m1_eop, + vci_out_m1_address, + vci_out_m1_wdata, + vci_out_m1_be, + vci_out_m1_cmd, + vci_out_m1_const, + vci_out_m1_contig, + vci_out_m1_wrap, + vci_out_m1_cmdack, + vci_out_m1_rspval, + vci_out_m1_reop, + vci_out_m1_rspack, + vci_out_m2_cmdval, + vci_out_m2_plen, + vci_out_m2_eop, + vci_out_m2_address, + vci_out_m2_wdata, + vci_out_m2_be, + vci_out_m2_cmd, + vci_out_m2_const, + vci_out_m2_contig, + vci_out_m2_wrap, + vci_out_m2_cmdack, + vci_out_m2_rspval, + vci_out_m2_reop, + vci_out_m2_rspack, + vci_out_m3_cmdval, + vci_out_m3_plen, + vci_out_m3_eop, + vci_out_m3_address, + vci_out_m3_wdata, + vci_out_m3_be, + vci_out_m3_cmd, + vci_out_m3_const, + vci_out_m3_contig, + vci_out_m3_wrap, + vci_out_m3_cmdack, + vci_out_m3_rspval, + vci_out_m3_reop, + vci_out_m3_rspack, + out_y_val, + out_y_data, + out_y_h_end, + out_y_v_end, + out_y_cfg_update, + out_y_ack, + out_c_val, + out_c_data, + out_c_h_end, + out_c_v_end, + out_c_cfg_update, + out_c_ack, + vci_in_cmdval, + vci_in_plen, + vci_in_eop, + vci_in_address, + vci_in_be, + vci_in_cmd, + vci_in_const, + vci_in_contig, + vci_in_wrap, + vci_in_cmdack, + vci_in_rspval, + vci_in_reop, + vci_in_rdata, + vci_in_rspack, + mi_mp_frame_end_int, + mi_sp_frame_end_int, + mi_mblk_line_int, + mi_fill_mp_y_int, + mi_wrap_mp_y_int, + mi_wrap_mp_cb_int, + mi_wrap_mp_cr_int, + mi_wrap_sp_y_int, + mi_wrap_sp_cb_int, + mi_wrap_sp_cr_int, + mi_dma_ready_int, + mi_mp_handshk_int, + mi_mp_handshk_sw_int, + mi_bp_frame_end_int, + mi_fill_bp_r_int, + mi_wrap_bp_r_int, + mi_wrap_bp_gr_int, + mi_wrap_bp_gb_int, + mi_wrap_bp_b_int, + rot_en, + ram_cs_n, + ram_we_n, + ram_addr, + ram_wdata, + ram_rdata, + mp_y_fifo_sram_DIN, + mp_y_fifo_sram_DOUT, + mp_y_fifo_sram_ADDR, + mp_y_fifo_sram_CEN, + mp_y_fifo_sram_WEN, + mp_cb_fifo_sram_DIN, + mp_cb_fifo_sram_DOUT, + mp_cb_fifo_sram_ADDR, + mp_cb_fifo_sram_CEN, + mp_cb_fifo_sram_WEN, + mp_cr_fifo_sram_DIN, + mp_cr_fifo_sram_DOUT, + mp_cr_fifo_sram_ADDR, + mp_cr_fifo_sram_CEN, + mp_cr_fifo_sram_WEN, + bp_ec_fifo_sram_DIN, + bp_ec_fifo_sram_DOUT, + bp_ec_fifo_sram_ADDR, + bp_ec_fifo_sram_CEN, + bp_ec_fifo_sram_WEN, + bp_oc_fifo_sram_DIN, + bp_oc_fifo_sram_DOUT, + bp_oc_fifo_sram_ADDR, + bp_oc_fifo_sram_CEN, + bp_oc_fifo_sram_WEN, + last_pixel_m1_req, + last_pixel_m1_ack, + last_pixel_m2_req, + last_pixel_m2_ack, + last_pixel_m3_req, + last_pixel_m3_ack, + dma_bayer_format, + data_mode_en, + isp_0_ack, + bresp_in, + isp_0_ready, + isp_0_attr + ); +`include "vsisp_marvin_mi.vh" +`include "vsisp_isp.vh" +`include "vsisp_ram_sizes.vh" +input isp_0_ack; +input data_mode_en; +input bresp_in; +output isp_0_ready; +output [1:0] isp_0_attr; + parameter c_rot_line_length = 1280; + parameter c_rot_ram_aw = 14; + parameter c_ram_dw = 32; + input clk; + input reset_n; + input soft_rst; + input m_hclk; + input reset_m_hclk_n; + input m_hclk_cfg; + input reset_m_hclk_cfg_n; + input soft_rst_m_hclk; + input jpeg_clk; + input reset_jpeg_clk_n; + input test_mode; + output mp_lsb_alignment_out; + output[3:0] mp_output_format_out; + output mp_little_endian_out; + input cfg_mi_val; + input [8:2] cfg_mi_addr; + input cfg_mi_rd; + input [31:0] cfg_mi_wdata; + output [31:0] cfg_mi_rdata; + output cfg_mi_ack; + input in_mp_y_val; + input [7:0] in_mp_y_data; + input in_mp_y_h_end; + input in_mp_y_v_end; + input in_mp_y_cfg_upd; + output in_mp_y_ack; + input in_mp_cb_val; + input [7:0] in_mp_cb_data; + input in_mp_cb_h_end; + input in_mp_cb_v_end; + input in_mp_cb_cfg_upd; + output in_mp_cb_ack; + input in_mp_cr_val; + input [7:0] in_mp_cr_data; + input in_mp_cr_h_end; + input in_mp_cr_v_end; + input in_mp_cr_cfg_upd; + output in_mp_cr_ack; + input in_sp_y_val; + input [7:0] in_sp_y_data; + input in_sp_y_h_end; + input in_sp_y_v_end; + input in_sp_y_cfg_upd; + output in_sp_y_ack; + input in_sp_cb_val; + input [7:0] in_sp_cb_data; + input in_sp_cb_h_end; + input in_sp_cb_v_end; + input in_sp_cb_cfg_upd; + output in_sp_cb_ack; + input in_sp_cr_val; + input [7:0] in_sp_cr_data; + input in_sp_cr_h_end; + input in_sp_cr_v_end; + input in_sp_cr_cfg_upd; + output in_sp_cr_ack; + input in_jpeg_val; + input [63:0] in_jpeg_data; + input in_jpeg_end; + input [2:0] in_jpeg_byte_no; + output in_jpeg_ack; + input [31:0] in_dp_data; + input in_dp_end; + input in_dp_val; + output in_dp_ack; + input in_bp_val; + input [15:0] in_bp_data; + input in_bp_h_end; + input in_bp_v_end; + input in_bp_cfg_upd; + output in_bp_ack; + input in_bp_frame_end; + input [1:0] bayer_pat; + output vci_out_m1_cmdval; + output [8:0] vci_out_m1_plen; + output vci_out_m1_eop; + output [c_mi_data_addr+3:3] vci_out_m1_address; + output [63:0] vci_out_m1_wdata; + output [7:0] vci_out_m1_be; + output [1:0] vci_out_m1_cmd; + output vci_out_m1_const; + output vci_out_m1_contig; + output vci_out_m1_wrap; + input vci_out_m1_cmdack; + input vci_out_m1_rspval; + input vci_out_m1_reop; + output vci_out_m1_rspack; + output vci_out_m2_cmdval; + output [8:0] vci_out_m2_plen; + output vci_out_m2_eop; + output [c_mi_data_addr+3:3] vci_out_m2_address; + output [63:0] vci_out_m2_wdata; + output [7:0] vci_out_m2_be; + output [1:0] vci_out_m2_cmd; + output vci_out_m2_const; + output vci_out_m2_contig; + output vci_out_m2_wrap; + input vci_out_m2_cmdack; + input vci_out_m2_rspval; + input vci_out_m2_reop; + output vci_out_m2_rspack; + output vci_out_m3_cmdval; + output [8:0] vci_out_m3_plen; + output vci_out_m3_eop; + output [c_mi_data_addr+3:3] vci_out_m3_address; + output [63:0] vci_out_m3_wdata; + output [7:0] vci_out_m3_be; + output [1:0] vci_out_m3_cmd; + output vci_out_m3_const; + output vci_out_m3_contig; + output vci_out_m3_wrap; + input vci_out_m3_cmdack; + input vci_out_m3_rspval; + input vci_out_m3_reop; + output vci_out_m3_rspack; + output out_y_val; + output [7:0] out_y_data; + output out_y_h_end; + output out_y_v_end; + output out_y_cfg_update; + input out_y_ack; + output out_c_val; + output [7:0] out_c_data; + output out_c_h_end; + output out_c_v_end; + output out_c_cfg_update; + input out_c_ack; + output vci_in_cmdval; + output [8:0] vci_in_plen; + output vci_in_eop; + output [c_mi_data_addr+3:3] vci_in_address; + output [7:0] vci_in_be; + output [1:0] vci_in_cmd; + output vci_in_const; + output vci_in_contig; + output vci_in_wrap; + input vci_in_cmdack; + input vci_in_rspval; + input vci_in_reop; + input [63:0] vci_in_rdata; + output vci_in_rspack; + output mi_mp_frame_end_int; + output mi_sp_frame_end_int; + output mi_mblk_line_int; + output mi_fill_mp_y_int; + output mi_wrap_mp_y_int; + output mi_wrap_mp_cb_int; + output mi_wrap_mp_cr_int; + output mi_wrap_sp_y_int; + output mi_wrap_sp_cb_int; + output mi_wrap_sp_cr_int; + output mi_dma_ready_int; + output mi_mp_handshk_int; + output mi_mp_handshk_sw_int; + output mi_bp_frame_end_int; + output mi_fill_bp_r_int; + output mi_wrap_bp_r_int; + output mi_wrap_bp_gr_int; + output mi_wrap_bp_gb_int; + output mi_wrap_bp_b_int; + output rot_en; + output ram_cs_n; + output ram_we_n; + output [c_rot_ram_aw-1:0] ram_addr; + output [c_ram_dw-1:0] ram_wdata; + input [c_ram_dw-1:0] ram_rdata; + output last_pixel_m1_req; + input last_pixel_m1_ack; + output last_pixel_m2_req; + input last_pixel_m2_ack; + output last_pixel_m3_req; + input last_pixel_m3_ack; + wire viv_s0; + input [65:0] mp_y_fifo_sram_DIN; + output [65:0] mp_y_fifo_sram_DOUT; + output [ c_mi_mp_y_aw -1:0] mp_y_fifo_sram_ADDR; + output mp_y_fifo_sram_CEN; + output mp_y_fifo_sram_WEN; + input [65:0] mp_cb_fifo_sram_DIN; + output [65:0] mp_cb_fifo_sram_DOUT; + output [ c_mi_mp_c_aw -1:0] mp_cb_fifo_sram_ADDR; + output mp_cb_fifo_sram_CEN; + output mp_cb_fifo_sram_WEN; + input [65:0] mp_cr_fifo_sram_DIN; + output [65:0] mp_cr_fifo_sram_DOUT; + output [ c_mi_mp_c_aw -1:0] mp_cr_fifo_sram_ADDR; + output mp_cr_fifo_sram_CEN; + output mp_cr_fifo_sram_WEN; + output [3:0] dma_bayer_format; + input [65:0] bp_ec_fifo_sram_DIN; + output [65:0] bp_ec_fifo_sram_DOUT; + output [8:0] bp_ec_fifo_sram_ADDR; + output bp_ec_fifo_sram_CEN; + output bp_ec_fifo_sram_WEN; + input [65:0] bp_oc_fifo_sram_DIN; + output [65:0] bp_oc_fifo_sram_DOUT; + output [8:0] bp_oc_fifo_sram_ADDR; + output bp_oc_fifo_sram_CEN; + output bp_oc_fifo_sram_WEN; + wire [31:0] viv_s1; + wire [31:0] viv_s2; + wire [31:0] viv_s3; + wire viv_s4; + wire viv_s5; + wire [14:0] viv_s6; + wire [c_mi_data_addr:0] viv_s7; + wire [c_mi_data_addr:0] viv_s8; + wire [2:0] viv_s9; + wire [2:0] viv_s10; + wire [2:0] viv_s11; + wire viv_s12; + wire viv_s13; + wire viv_s14; + wire [1:0] viv_s15; + wire viv_s16; + wire viv_s17; + wire viv_s18; + wire [1:0] viv_s19; + wire [1:0] viv_s20; + wire [1:0] viv_s21; + wire [2:0] viv_s22; + wire viv_s23; + wire viv_s24; + wire viv_s25; + wire viv_s26; + wire [14:0] viv_s27; + wire [14:0] viv_s28; + wire viv_s29; + wire viv_s30; + wire viv_s31; + wire viv_s32; + wire [1:0] viv_s33; + wire viv_s34; + wire viv_s35; + wire viv_s36; + wire viv_s37; + wire viv_s38; + wire viv_s39; + wire viv_s40; + wire viv_s41; + wire viv_s42; + wire viv_s43; + wire viv_s44; + wire viv_s45; + wire viv_s46; + wire [1:0] viv_s47; + wire [1:0] viv_s48; + wire [1:0] viv_s49; + wire [1:0] viv_s50; + wire [2:0] viv_s51; + wire viv_s52; + wire viv_s53; + wire [c_mi_data_addr+3:3] viv_s54; + wire [c_mi_data_addr:3] viv_s55; + wire [c_mi_data_addr:3] viv_s56; + wire [c_mi_data_addr+3:3] viv_s57; + wire [c_mi_data_addr+3:3] viv_s58; + wire [c_mi_data_addr:3] viv_s59; + wire [c_mi_data_addr:3] viv_s60; + wire [c_mi_data_addr:3] viv_s61; + wire [c_mi_data_addr:3] viv_s62; + wire [c_mi_data_addr:3] viv_s63; + wire [c_mi_data_addr+3:3] viv_s64; + wire [c_mi_data_addr-1:3] viv_s65; + wire [c_mi_data_addr-1:3] viv_s66; + wire [c_mi_data_addr+3:3] viv_s67; + wire [c_mi_data_addr+3:3] viv_s68; + wire [c_mi_data_addr-1:3] viv_s69; + wire [c_mi_data_addr-1:3] viv_s70; + wire [c_mi_data_addr-1:3] viv_s71; + wire [c_mi_data_addr+3:3] viv_s72; + wire [c_mi_data_addr-1:3] viv_s73; + wire [c_mi_data_addr-1:3] viv_s74; + wire [c_mi_data_addr+3:3] viv_s75; + wire [c_mi_data_addr+3:3] viv_s76; + wire [c_mi_data_addr-1:3] viv_s77; + wire [c_mi_data_addr-1:3] viv_s78; + wire [c_mi_data_addr-1:3] viv_s79; + wire [c_mi_data_addr+3:3] viv_s80; + wire [c_mi_data_addr:3] viv_s81; + wire [c_mi_data_addr:3] viv_s82; + wire [c_mi_data_addr+3:3] viv_s83; + wire [c_mi_data_addr+3:3] viv_s84; + wire [c_mi_data_addr:3] viv_s85; + wire [c_mi_data_addr:3] viv_s86; + wire [c_mi_data_addr:3] viv_s87; + wire [14:0] viv_s88; + wire [14:0] viv_s89; + wire [c_mi_data_addr:0] viv_s90; + wire [c_mi_data_addr+3:3] viv_s91; + wire [c_mi_data_addr-1:3] viv_s92; + wire [c_mi_data_addr-1:3] viv_s93; + wire [c_mi_data_addr+3:3] viv_s94; + wire [c_mi_data_addr+3:3] viv_s95; + wire [c_mi_data_addr-1:3] viv_s96; + wire [c_mi_data_addr-1:3] viv_s97; + wire [c_mi_data_addr-1:3] viv_s98; + wire [c_mi_data_addr+3:3] viv_s99; + wire [c_mi_data_addr-1:3] viv_s100; + wire [c_mi_data_addr-1:3] viv_s101; + wire [c_mi_data_addr+3:3] viv_s102; + wire [c_mi_data_addr+3:3] viv_s103; + wire [c_mi_data_addr-1:3] viv_s104; + wire [c_mi_data_addr-1:3] viv_s105; + wire [c_mi_data_addr-1:3] viv_s106; + wire [1:0] viv_s107; + wire [1:0] viv_s108; + wire viv_s109; + wire [1:0] viv_s110; + wire [1:0] viv_s111; + wire [1:0] viv_s112; + wire [1:0] viv_s113; + wire [1:0] viv_s114; + wire viv_s115; + wire viv_s116; + wire viv_s117; + wire [31:0] viv_s118; + wire [14:0] viv_s119; + wire [14:0] viv_s120; + wire [c_bufsize-1:0] viv_s121; + wire [31:0] viv_s122; + wire [31:0] viv_s123; + wire [14:0] viv_s124; + wire [14:0] viv_s125; + wire [c_bufsize-1:0] viv_s126; + wire [5:0] viv_s127; + wire [14:0] viv_s128; + wire [14:0] viv_s129; + wire viv_s130; + wire [7:0] viv_s131; + wire viv_s132; + wire viv_s133; + wire viv_s134; + wire viv_s135; + wire viv_s136; + wire [7:0] viv_s137; + wire viv_s138; + wire viv_s139; + wire viv_s140; + wire viv_s141; + wire viv_s142; + wire [7:0] viv_s143; + wire viv_s144; + wire viv_s145; + wire viv_s146; + wire viv_s147; + wire viv_s148; + wire [7:0] viv_s149; + wire viv_s150; + wire viv_s151; + wire viv_s152; + wire viv_s153; + wire viv_s154; + wire [7:0] viv_s155; + wire viv_s156; + wire viv_s157; + wire viv_s158; + wire viv_s159; + wire viv_s160; + wire [7:0] viv_s161; + wire viv_s162; + wire viv_s163; + wire viv_s164; + wire viv_s165; + wire viv_s166; + wire [7:0] viv_s167; + wire viv_s168; + wire viv_s169; + wire viv_s170; + wire viv_s171; + wire viv_s172; + wire [7:0] viv_s173; + wire viv_s174; + wire viv_s175; + wire viv_s176; + wire viv_s177; + wire viv_s178; + wire [7:0] viv_s179; + wire viv_s180; + wire viv_s181; + wire viv_s182; + wire viv_s183; + wire viv_s184; + wire viv_s185; + wire viv_s186; + wire [1:0] viv_s187; + wire viv_s188; + wire viv_s189; + wire [c_mi_data_addr-1:0] viv_s190; + wire viv_s191; + wire viv_s192; + wire [c_mi_data_addr-1:0] viv_s193; + wire viv_s194; + wire viv_s195; + wire [c_mi_data_addr-1:0] viv_s196; + wire viv_s197; + wire [63:0] viv_s198; + wire viv_s199; + wire viv_s200; + wire viv_s201; + wire viv_s202; + wire viv_s203; + wire [63:0] viv_s204; + wire viv_s205; + wire viv_s206; + wire viv_s207; + wire viv_s208; + wire viv_s209; + wire [63:0] viv_s210; + wire viv_s211; + wire viv_s212; + wire viv_s213; + wire viv_s214; + wire viv_s215; + wire [63:0] viv_s216; + wire viv_s217; + wire viv_s218; + wire viv_s219; + wire viv_s220; + wire [63:0] viv_s221; + wire viv_s222; + wire viv_s223; + wire viv_s224; + wire viv_s225; + wire [63:0] viv_s226; + wire viv_s227; + wire viv_s228; + wire viv_s229; + wire viv_s230; + wire viv_s231; + wire [1:0] viv_s232; + wire [63:0] viv_s233; + wire viv_s234; + wire viv_s235; + wire viv_s236; + wire [1:0] viv_s237; + wire [63:0] viv_s238; + wire viv_s239; + wire viv_s240; + wire viv_s241; + wire [c_addr_width:0] viv_s242; + reg [c_fifo_depth_bw-1:0] viv_s243; + wire viv_s244; + wire [c_addr_width:0] viv_s245; + reg [c_fifo_depth_bw-1:0] viv_s246; + wire viv_s247; + wire [c_addr_width:0] viv_s248; + reg [c_fifo_depth_bw-1:0] viv_s249; + wire viv_s250; + wire [c_addr_width:0] viv_s251; + reg [c_fifo_depth_bw-1:0] viv_s252; + wire viv_s253; + wire [c_addr_width:0] viv_s254; + reg [c_fifo_depth_bw-1:0] viv_s255; + wire viv_s256; + wire [c_addr_width:0] viv_s257; + reg [c_fifo_depth_bw-1:0] viv_s258; + wire viv_s259; + wire viv_s260; + wire viv_s261; + wire viv_s262; + wire viv_s263; + wire [1:0] viv_s264; + wire viv_s265; + reg viv_s266; + reg viv_s267; + wire viv_s268; + reg viv_s269; + reg viv_s270; + wire viv_s271; + reg viv_s272; + reg viv_s273; + wire viv_s274; + wire viv_s275; + wire viv_s276; + wire viv_s277; + wire viv_s278; + wire viv_s279; + wire viv_s280; + wire viv_s281; + wire viv_s282; + wire viv_s283; + wire viv_s284; + wire viv_s285; + wire viv_s286; + reg [31:0] viv_s287; + reg viv_s288; + reg viv_s289; + reg viv_s290; + wire viv_s291; + wire [10:0] viv_s292; + wire viv_s293; + wire viv_s294; + wire [10:0] viv_s295; + wire viv_s296; + wire viv_s297; + wire viv_s298; + reg viv_s299; + reg viv_s300; + reg viv_s301; + wire viv_s302; + wire viv_s303; + reg viv_s304; + reg viv_s305; + reg viv_s306; + reg viv_s307; + reg viv_s308; + wire viv_s309; + wire [1:0] viv_s310; +wire viv_s311; +wire viv_s312; +wire [1:0] viv_s313; +wire [7:0] viv_s314; +wire [7:0] viv_s315; +wire [7:0] viv_s316; +wire [1:0] viv_s317; +wire viv_s318; +wire viv_s319; +wire [7:0] viv_s320; +wire [c_mi_data_addr:0] viv_s321; +wire [c_mi_data_addr:0] viv_s322; +wire [c_mi_data_addr:0] viv_s323; +reg [31:0] viv_s324; +reg [31:0] viv_s325; +reg [31:0] viv_s326; +wire viv_s327; + always @ (*) begin + if (in_dp_val) begin + viv_s288 = in_dp_end; + viv_s287 = in_dp_data; + end + else begin + viv_s288 = 1'b0; + viv_s287 = 32'b0; + end + end +wire [c_mi_data_addr:3] viv_s328; +wire [c_mi_data_addr:3] viv_s329; +wire [14:0] viv_s330; +wire [14:0] viv_s331; +wire [14:0] viv_s332; +wire viv_s333; +wire viv_s334; +wire [3:0] viv_s335; +wire [1:0] viv_s336; +wire [1:0] viv_s337; +wire [1:0] viv_s338; +wire [2:0] viv_s339; +wire viv_s340; +wire viv_s341; +wire [3:0] viv_s342; +wire [1:0] viv_s343; +wire [1:0] viv_s344; +wire [1:0] viv_s345; +wire [c_mi_data_addr:3] viv_s346; +wire [c_mi_data_addr:3] viv_s347; +wire [c_mi_data_addr:3] viv_s348; +wire [c_mi_data_addr+3:3] viv_s349; +wire [c_mi_data_addr+3:3] viv_s350; +wire [c_mi_data_addr:3] viv_s351; +wire [c_mi_data_addr:3] viv_s352; +wire [c_mi_data_addr+3:3] viv_s353; +wire [c_mi_data_addr+3:3] viv_s354; +wire [c_mi_data_addr:3] viv_s355; +wire [c_mi_data_addr:3] viv_s356; +wire [c_mi_data_addr+3:3] viv_s357; +wire [c_mi_data_addr+3:3] viv_s358; +wire [c_mi_data_addr:3] viv_s359; +wire [c_mi_data_addr:3] viv_s360; +wire [c_mi_data_addr+3:3] viv_s361; +wire [c_mi_data_addr+3:3] viv_s362; +wire [c_mi_data_addr:3] viv_s363; +wire [c_mi_data_addr:3] viv_s364; +wire viv_s365; +wire viv_s366; +wire viv_s367; +wire viv_s368; +wire viv_s369; +wire viv_s370; +wire viv_s371 = ~in_bp_ack; + vsisp_marvin_mi_regs u_marvin_mi_regs + (.mp_lsb_alignment_out (mp_lsb_alignment_out), + .mp_little_endian_out (mp_little_endian_out), + .mp_y_pic_width_out (viv_s1), + .mp_y_pic_height_out (viv_s2), + .mp_y_pic_size_out (viv_s3), + .sw_mi_fifo_depth_ctrl_out(viv_s310), + .mp_output_format_out (mp_output_format_out), + .mp_y_llength_out (viv_s6), + .mp_slice_offset_y_out (viv_s7), + .mp_slice_offset_c_out (viv_s8), + .mp_byte_swap_out (viv_s9), + .sp_byte_swap_out (viv_s10), + .dma_byte_swap_out (viv_s11), + .bp_wr_path_enable_in (viv_s340), + .bp_wr_path_enable_out (viv_s341), + .bp_auto_update (viv_s334), + .bp_wr_raw_bit_in (viv_s342), + .bp_wr_aligned_in (viv_s343), + .bp_wr_write_format_in (viv_s344), + .bp_wr_write_format_out (viv_s345), + .bp_wr_burst_len (viv_s338), + .bp_wr_byte_swap (viv_s339), + .bp_wr_size (viv_s328), + .bp_wr_size_init (viv_s329), + .bp_wr_llength (viv_s330), + .bp_wr_pic_width (viv_s331), + .bp_wr_pic_height (viv_s332), + .bp_wr_offs_cnt_init (viv_s348), + .bp_wr_irq_offs_init (viv_s347), + .bp_wr_irq_offs (viv_s346), + .bp_r_base_ad (viv_s349), + .bp_r_base_ad_init (viv_s350), + .bp_r_offs_cnt (viv_s351), + .bp_r_offs_cnt_start (viv_s352), + .bp_gr_base_ad (viv_s353), + .bp_gr_base_ad_init (viv_s354), + .bp_gr_offs_cnt (viv_s355), + .bp_gr_offs_cnt_start (viv_s356), + .bp_gb_base_ad (viv_s357), + .bp_gb_base_ad_init (viv_s358), + .bp_gb_offs_cnt (viv_s359), + .bp_gb_offs_cnt_start (viv_s360), + .bp_b_base_ad (viv_s361), + .bp_b_base_ad_init (viv_s362), + .bp_b_offs_cnt (viv_s363), + .bp_b_offs_cnt_start (viv_s364), + .stat_bp_frame_end(viv_s365), + .stat_fill_bp_r(viv_s366), + .stat_wrap_bp_r(viv_s367), + .stat_wrap_bp_gr(viv_s368), + .stat_wrap_bp_gb(viv_s369), + .stat_wrap_bp_b(viv_s370), + .mi_bp_frame_end_int(mi_bp_frame_end_int), + .mi_fill_bp_r_int(mi_fill_bp_r_int), + .mi_wrap_bp_r_int(mi_wrap_bp_r_int), + .mi_wrap_bp_gr_int(mi_wrap_bp_gr_int), + .mi_wrap_bp_gb_int(mi_wrap_bp_gb_int), + .mi_wrap_bp_b_int(mi_wrap_bp_b_int), + .clk (clk ), + .reset_n (reset_n), + .jpeg_clk (jpeg_clk), + .reset_jpeg_clk_n (reset_jpeg_clk_n), + .m_hclk (m_hclk), + .reset_m_hclk_n (reset_m_hclk_n), + .m_hclk_cfg (m_hclk_cfg), + .reset_m_hclk_cfg_n (reset_m_hclk_cfg_n), + .cfg_mi_val (cfg_mi_val), + .cfg_mi_addr (cfg_mi_addr), + .cfg_mi_rd (cfg_mi_rd), + .cfg_mi_wdata (cfg_mi_wdata), + .cfg_mi_rdata (cfg_mi_rdata), + .cfg_mi_ack (cfg_mi_ack), + .mi_mp_frame_end_int (mi_mp_frame_end_int), + .mi_sp_frame_end_int (mi_sp_frame_end_int), + .mi_mblk_line_int (mi_mblk_line_int), + .mi_fill_mp_y_int (mi_fill_mp_y_int), + .mi_wrap_mp_y_int (mi_wrap_mp_y_int), + .mi_wrap_mp_cb_int (mi_wrap_mp_cb_int), + .mi_wrap_mp_cr_int (mi_wrap_mp_cr_int), + .mi_wrap_sp_y_int (mi_wrap_sp_y_int), + .mi_wrap_sp_cb_int (mi_wrap_sp_cb_int), + .mi_wrap_sp_cr_int (mi_wrap_sp_cr_int), + .mi_dma_ready_int (mi_dma_ready_int), + .mi_mp_handshk_int (mi_mp_handshk_int), + .mi_mp_handshk_sw_int (mi_mp_handshk_sw_int), + .soft_upd_in (viv_s26), + .mp_enable_in (viv_s12), + .sp_enable_in (viv_s13), + .jpeg_enable_in (viv_s14), + .dp_enable_in (viv_s15), + .raw_enable_in (viv_s16), + .h_flip_in (viv_s17), + .rot_in (viv_s18), + .mp_write_format_in (viv_s19), + .sp_write_format_in (viv_s20), + .sp_input_format_in (viv_s21), + .cfg_y_full (viv_s23), + .cfg_crcb_full (viv_s24), + .cfg_422noncosited (viv_s25), + .sp_output_format_in (viv_s22), + .sp_y_pic_width_in (viv_s27), + .sp_y_pic_height_in (viv_s28), + .stat_mp_enable_in (viv_s184), + .stat_sp_enable_in (viv_s185), + .stat_jpeg_enable_in (viv_s186), + .stat_dp_enable_in (viv_s187), + .stat_raw_enable_in (viv_s188), + .stat_byte_cnt_raw_val (viv_s189), + .stat_byte_cnt_raw (viv_s190), + .stat_byte_cnt_raw_ack (viv_s191), + .stat_byte_cnt_jpeg_val (viv_s192), + .stat_byte_cnt_jpeg (viv_s193), + .stat_byte_cnt_jpeg_ack (viv_s194), + .stat_byte_cnt_dp_val (viv_s195), + .stat_byte_cnt_dp (viv_s196), + .stat_byte_cnt_dp_ack (viv_s197), + .soft_upd_out (viv_s52), + .skip (viv_s53), + .mp_enable_out (viv_s29), + .sp_enable_out (viv_s30), + .jpeg_enable_out (viv_s31), + .raw_enable_out (viv_s32), + .dp_enable_out (viv_s33), + .h_flip_out (viv_s34), + .v_flip_out (viv_s35), + .rot_out (viv_s36), + .mp_write_format_out (viv_s49), + .sp_write_format_out (viv_s50), + .sp_output_format_out (viv_s51), + .byte_swap (viv_s37), + .init_base_en (viv_s38), + .init_offset_en (viv_s39), + .mp_pingpong_en (viv_s40), + .sp_pingpong_en (viv_s41), + .mp_auto_update (viv_s42), + .sp_auto_update (viv_s43), + .burst_len_lum (viv_s47), + .burst_len_chrom (viv_s48), + .stat_mp_enable_out (viv_s260), + .stat_sp_enable_out (viv_s261), + .stat_jpeg_enable_out (viv_s262), + .stat_raw_enable_out (viv_s263), + .stat_dp_enable_out (viv_s264), + .mp_y_base_ad (viv_s54), + .mp_y_size (viv_s55), + .mp_y_offs_cnt (viv_s56), + .mp_y_base_ad_init (viv_s57), + .mp_y_base_ad_init2 (viv_s58), + .mp_y_size_init (viv_s59), + .mp_y_offs_cnt_init (viv_s60), + .mp_y_offs_cnt_start (viv_s61), + .mp_y_irq_offs_init (viv_s62), + .mp_y_irq_offs (viv_s63), + .mp_cb_base_ad (viv_s64), + .mp_cb_size (viv_s65), + .mp_cb_offs_cnt (viv_s66), + .mp_cb_base_ad_init (viv_s67), + .mp_cb_base_ad_init2 (viv_s68), + .mp_cb_size_init (viv_s69), + .mp_cb_offs_cnt_init (viv_s70), + .mp_cb_offs_cnt_start (viv_s71), + .mp_cr_base_ad (viv_s72), + .mp_cr_size (viv_s73), + .mp_cr_offs_cnt (viv_s74), + .mp_cr_base_ad_init (viv_s75), + .mp_cr_base_ad_init2 (viv_s76), + .mp_cr_size_init (viv_s77), + .mp_cr_offs_cnt_init (viv_s78), + .mp_cr_offs_cnt_start (viv_s79), + .sp_y_base_ad (viv_s80), + .sp_y_size (viv_s81), + .sp_y_offs_cnt (viv_s82), + .sp_y_base_ad_init (viv_s83), + .sp_y_base_ad_init2 (viv_s84), + .sp_y_size_init (viv_s85), + .sp_y_offs_cnt_init (viv_s86), + .sp_y_offs_cnt_start (viv_s87), + .sp_y_pic_width (viv_s88), + .sp_y_llength (viv_s89), + .sp_y_pic_size (viv_s90), + .sp_cb_base_ad (viv_s91), + .sp_cb_size (viv_s92), + .sp_cb_offs_cnt (viv_s93), + .sp_cb_base_ad_init (viv_s94), + .sp_cb_base_ad_init2 (viv_s95), + .sp_cb_size_init (viv_s96), + .sp_cb_offs_cnt_init (viv_s97), + .sp_cb_offs_cnt_start (viv_s98), + .sp_cr_base_ad (viv_s99), + .sp_cr_size (viv_s100), + .sp_cr_offs_cnt (viv_s101), + .sp_cr_base_ad_init (viv_s102), + .sp_cr_base_ad_init2 (viv_s103), + .sp_cr_size_init (viv_s104), + .sp_cr_offs_cnt_init (viv_s105), + .sp_cr_offs_cnt_start (viv_s106), + .dma_read_format_in (viv_s107), + .dma_rgb_format_in (viv_s108), + .dma_start (viv_s109), + .stat_dma_active (viv_s275), + .dma_burst_len_lum (viv_s110), + .dma_burst_len_chrom (viv_s111), + .dma_read_format_out (viv_s112), + .dma_rgb_format_out (viv_s113), + .dma_inout_format (viv_s114), + .dma_byte_swap (viv_s115), + .dma_continuous_en (viv_s116), + .dma_bayer_format (dma_bayer_format), + .dma_frame_end_disable (viv_s117), + .dma_y_pic_start_ad (viv_s118), + .dma_y_pic_width (viv_s119), + .dma_y_llength (viv_s120), + .dma_y_pic_size (viv_s121), + .dma_cb_pic_start_ad (viv_s122), + .dma_cr_pic_start_ad (viv_s123), + .dma_y_pic_width_in(viv_s124), + .dma_y_llength_in(viv_s125), + .dma_y_pic_size_in(viv_s126), + .dma_y_raw_fmt_in(viv_s127), + .dma_y_raw_lval(viv_s128), + .dma_y_raw_lval_in(viv_s129), + .stat_mp_y_full (viv_s203 ), + .stat_mp_cb_full (viv_s209), + .stat_mp_cr_full (viv_s215), + .stat_sp_y_full (viv_s220), + .stat_sp_cb_full (viv_s225), + .stat_sp_cr_full (viv_s230), + .stat_bp_ecl_full (bp_ecl_fifo_sram_buf_full), + .stat_bp_ocl_full (bp_ocl_fifo_sram_buf_full), + .stat_bp_in_full (viv_s371), + .stat_mp_frame_end (viv_s276), + .stat_sp_frame_end (viv_s277), + .stat_mblk_line (viv_s278), + .stat_fill_mp_y (viv_s279), + .stat_wrap_mp_y (viv_s280), + .stat_wrap_mp_cb (viv_s281), + .stat_wrap_mp_cr (viv_s282), + .stat_wrap_sp_y (viv_s283), + .stat_wrap_sp_cb (viv_s284), + .stat_wrap_sp_cr (viv_s285), + .stat_dma_ready (viv_s286), + .last_pixel_sig_en (viv_s0), + .nv21_main (viv_s44), + .nv21_self (viv_s45), + .nv21_dma_read (viv_s46), + .handshake_en (viv_s312), + .starage_format (viv_s313), + .data_format (viv_s317), + .slice_size (viv_s314), + .slice_buf_size (viv_s315), + .ack_count (viv_s316), + .mp_interrupt (viv_s311), + .handshake_mode_0 (viv_s319), + .slice_cnt_int (viv_s320), + .sw_addr_mp_y (viv_s324), + .sw_addr_mp_cb (viv_s325), + .sw_addr_mp_cr (viv_s326), + .sw_interrupt (viv_s327)); + assign rot_en = viv_s17 | viv_s18; +assign viv_s274 = 1'b1; +assign viv_s265 = 1'b1; + vsisp_marvin_mi_in u_marvin_mi_in + ( + .mp_y_llength (viv_s6), + .mp_y_pic_width (viv_s1), + .mp_y_pic_height (viv_s2), + .mp_y_pic_size (viv_s3), + .mp_line_sens (viv_s318), + .slice_size (viv_s314), + .data_format (viv_s317), + .mp_slice_offset_y (viv_s7), + .mp_slice_offset_c (viv_s8), + .handshake_en (viv_s312), + .stat_skip_active (viv_s241), + .clk (jpeg_clk), + .reset_n (reset_jpeg_clk_n), + .soft_rst (viv_s291), + .in_mp_y_val (in_mp_y_val), + .in_mp_y_data (in_mp_y_data), + .in_mp_y_h_end (in_mp_y_h_end), + .in_mp_y_v_end (in_mp_y_v_end), + .in_mp_y_cfg_upd (in_mp_y_cfg_upd), + .in_mp_y_ack (in_mp_y_ack), + .in_mp_cb_val (in_mp_cb_val), + .in_mp_cb_data (in_mp_cb_data), + .in_mp_cb_h_end (in_mp_cb_h_end), + .in_mp_cb_v_end (in_mp_cb_v_end), + .in_mp_cb_cfg_upd (in_mp_cb_cfg_upd), + .in_mp_cb_ack (in_mp_cb_ack), + .in_mp_cr_val (in_mp_cr_val), + .in_mp_cr_data (in_mp_cr_data), + .in_mp_cr_h_end (in_mp_cr_h_end), + .in_mp_cr_v_end (in_mp_cr_v_end), + .in_mp_cr_cfg_upd (in_mp_cr_cfg_upd), + .in_mp_cr_ack (in_mp_cr_ack), + .in_dp_data (viv_s287), + .in_dp_val (in_dp_val), + .in_dp_ack (in_dp_ack), + .in_dp_end (viv_s288), + .in_sp_y_val (in_sp_y_val ), + .in_sp_y_data (in_sp_y_data ), + .in_sp_y_h_end (in_sp_y_h_end ), + .in_sp_y_v_end (in_sp_y_v_end ), + .in_sp_y_cfg_upd (in_sp_y_cfg_upd ), + .in_sp_y_ack (in_sp_y_ack ), + .in_sp_cb_val (in_sp_cb_val ), + .in_sp_cb_data (in_sp_cb_data ), + .in_sp_cb_h_end (in_sp_cb_h_end ), + .in_sp_cb_v_end (in_sp_cb_v_end ), + .in_sp_cb_cfg_upd (in_sp_cb_cfg_upd), + .in_sp_cb_ack (in_sp_cb_ack ), + .in_sp_cr_val (in_sp_cr_val ), + .in_sp_cr_data (in_sp_cr_data ), + .in_sp_cr_h_end (in_sp_cr_h_end ), + .in_sp_cr_v_end (in_sp_cr_v_end ), + .in_sp_cr_cfg_upd (in_sp_cr_cfg_upd), + .in_sp_cr_ack (in_sp_cr_ack ), + .in_jpeg_val (in_jpeg_val), + .in_jpeg_data (in_jpeg_data), + .in_jpeg_end (in_jpeg_end), + .in_jpeg_byte_no (in_jpeg_byte_no), + .in_jpeg_ack (in_jpeg_ack), + .mp_y_fifo_data (viv_s198), + .mp_y_fifo_h_end (viv_s199), + .mp_y_fifo_v_end (viv_s200), + .mp_y_fifo_write64 (viv_s201), + .mp_y_fifo_full (viv_s202), + .mp_cb_fifo_data (viv_s204), + .mp_cb_fifo_h_end (viv_s205), + .mp_cb_fifo_v_end (viv_s206), + .mp_cb_fifo_write64 (viv_s207), + .mp_cb_fifo_full (viv_s208), + .mp_cr_fifo_data (viv_s210), + .mp_cr_fifo_h_end (viv_s211), + .mp_cr_fifo_v_end (viv_s212), + .mp_cr_fifo_write64 (viv_s213), + .mp_cr_fifo_full (viv_s214), + .sp_y_fifo_data (viv_s216), + .sp_y_fifo_h_end (viv_s217), + .sp_y_fifo_v_end (viv_s218), + .sp_y_fifo_write64 (viv_s219), + .sp_y_fifo_full (viv_s220), + .sp_cb_fifo_data (viv_s221), + .sp_cb_fifo_h_end (viv_s222), + .sp_cb_fifo_v_end (viv_s223), + .sp_cb_fifo_write64 (viv_s224), + .sp_cb_fifo_full (viv_s225), + .sp_cr_fifo_data (viv_s226), + .sp_cr_fifo_h_end (viv_s227), + .sp_cr_fifo_v_end (viv_s228), + .sp_cr_fifo_write64 (viv_s229), + .sp_cr_fifo_full (viv_s230), + .mp_auto_update (viv_s42), + .sp_auto_update (viv_s43), + .mp_nv21 (viv_s44), + .sp_nv21 (viv_s45), + .soft_upd (viv_s26), + .mp_enable (viv_s12), + .sp_enable (viv_s13), + .jpeg_enable (viv_s14), + .dp_enable (viv_s15), + .raw_enable (viv_s16), + .mp_write_format (viv_s19), + .sp_write_format (viv_s20), + .sp_output_format (viv_s22), + .sp_line_sens (viv_s265), + .sp_col_sens (viv_s274), + .stat_mp_enable_in (viv_s184), + .stat_sp_enable_in (viv_s185), + .stat_jpeg_enable_in (viv_s186), + .stat_dp_enable_in (viv_s187), + .stat_raw_enable_in (viv_s188), + .stat_byte_cnt_raw_val (viv_s189), + .stat_byte_cnt_raw (viv_s190), + .stat_byte_cnt_raw_ack (viv_s191), + .stat_byte_cnt_jpeg_val (viv_s192), + .stat_byte_cnt_jpeg (viv_s193), + .stat_byte_cnt_jpeg_ack (viv_s194), + .stat_byte_cnt_dp_val (viv_s195), + .stat_byte_cnt_dp (viv_s196), + .stat_byte_cnt_dp_ack (viv_s197), + .cfg_in_update_mp (viv_s268), + .cfg_in_update_sp (viv_s271), + .cfg_out_update_mp (viv_s302), + .cfg_out_update_sp (viv_s309) + ); + always @(posedge m_hclk or negedge reset_m_hclk_n) begin + if (~reset_m_hclk_n) begin + viv_s269 <= 1'b0; + viv_s270 <= 1'b0; + viv_s272 <= 1'b0; + viv_s273 <= 1'b0; + end + else begin + viv_s269 <= viv_s268; + viv_s270 <= viv_s269; + viv_s272 <= viv_s271; + viv_s273 <= viv_s272; + end + end + always @(posedge jpeg_clk or negedge reset_jpeg_clk_n) begin + if (~reset_jpeg_clk_n) begin + viv_s299 <= 1'b0; + viv_s300 <= 1'b0; + viv_s301 <= 1'b0; + end + else begin + viv_s299 <= viv_s298; + viv_s300 <= viv_s299; + viv_s301 <= viv_s300; + end + end + always @(posedge clk or negedge reset_n) begin + if (~reset_n) begin + viv_s306 <= 1'b0; + viv_s307 <= 1'b0; + viv_s308 <= 1'b0; + end + else begin + viv_s306 <= viv_s303; + viv_s307 <= viv_s306; + viv_s308 <= viv_s307; + end + end + assign viv_s302 = viv_s300 && ~viv_s301; + assign viv_s309 = viv_s307 && ~viv_s308; + vsisp_marvin_mi_fifo #(.c_fifo_depth(c_fifo_depth)) u_marvin_mi_fifo + ( + .sw_mi_fifo_depth_ctrl (viv_s310), + .clk (jpeg_clk), + .reset_n (reset_jpeg_clk_n), + .soft_rst (viv_s291), + .m_hclk (m_hclk), + .reset_m_hclk_n (reset_m_hclk_n), + .soft_rst_m_hclk (soft_rst_m_hclk), + .test_mode (test_mode), + .sp_rot_in (viv_s18), + .mp_y_fifo_data_in (viv_s198), + .mp_y_fifo_h_end_in (viv_s199), + .mp_y_fifo_v_end_in (viv_s200), + .mp_y_fifo_write64 (viv_s201), + .mp_y_fifo_full (viv_s202), + .mp_y_fifo_sram_buf_full (viv_s203 ), + .mp_cb_fifo_data_in (viv_s204), + .mp_cb_fifo_h_end_in (viv_s205), + .mp_cb_fifo_v_end_in (viv_s206), + .mp_cb_fifo_write64 (viv_s207), + .mp_cb_fifo_full (viv_s208), + .mp_cb_fifo_sram_buf_full(viv_s209 ), + .mp_cr_fifo_data_in (viv_s210), + .mp_cr_fifo_h_end_in (viv_s211), + .mp_cr_fifo_v_end_in (viv_s212), + .mp_cr_fifo_write64 (viv_s213), + .mp_cr_fifo_full (viv_s214), + .mp_cr_fifo_sram_buf_full(viv_s215 ), + .sp_y_fifo_data_in (viv_s216), + .sp_y_fifo_h_end_in (viv_s217), + .sp_y_fifo_v_end_in (viv_s218), + .sp_y_fifo_write64 (viv_s219), + .sp_y_fifo_full (viv_s220), + .sp_cb_fifo_data_in (viv_s221), + .sp_cb_fifo_h_end_in (viv_s222), + .sp_cb_fifo_v_end_in (viv_s223), + .sp_cb_fifo_write64 (viv_s224), + .sp_cb_fifo_full (viv_s225), + .sp_cr_fifo_data_in (viv_s226), + .sp_cr_fifo_h_end_in (viv_s227), + .sp_cr_fifo_v_end_in (viv_s228), + .sp_cr_fifo_write64 (viv_s229), + .sp_cr_fifo_full (viv_s230), + .mp_fifo_read64 (viv_s231), + .mp_fifo_select (viv_s232), + .mp_fifo_data_out (viv_s233), + .mp_fifo_h_end_out (viv_s234), + .mp_fifo_v_end_out (viv_s235), + .sp_fifo_read64 (viv_s236), + .sp_fifo_select (viv_s237), + .sp_fifo_data_out (viv_s238), + .sp_fifo_h_end_out (viv_s239), + .sp_fifo_v_end_out (viv_s240), + .mp_y_fifo_fill_level (viv_s242), + .mp_y_fifo_flush (viv_s244), + .mp_cb_fifo_fill_level (viv_s245), + .mp_cb_fifo_flush (viv_s247), + .mp_cr_fifo_fill_level (viv_s248), + .mp_cr_fifo_flush (viv_s250), + .sp_y_fifo_fill_level (viv_s251), + .sp_y_fifo_flush (viv_s253), + .sp_cb_fifo_fill_level (viv_s254), + .sp_cb_fifo_flush (viv_s256), + .sp_cr_fifo_fill_level (viv_s257), + .sp_cr_fifo_flush (viv_s259), + .mp_y_fifo_sram_DIN (mp_y_fifo_sram_DIN ), + .mp_y_fifo_sram_DOUT (mp_y_fifo_sram_DOUT ), + .mp_y_fifo_sram_ADDR (mp_y_fifo_sram_ADDR ), + .mp_y_fifo_sram_CEN (mp_y_fifo_sram_CEN ), + .mp_y_fifo_sram_WEN (mp_y_fifo_sram_WEN ), + .mp_cb_fifo_sram_DIN (mp_cb_fifo_sram_DIN ), + .mp_cb_fifo_sram_DOUT (mp_cb_fifo_sram_DOUT ), + .mp_cb_fifo_sram_ADDR (mp_cb_fifo_sram_ADDR ), + .mp_cb_fifo_sram_CEN (mp_cb_fifo_sram_CEN ), + .mp_cb_fifo_sram_WEN (mp_cb_fifo_sram_WEN ), + .mp_cr_fifo_sram_DIN (mp_cr_fifo_sram_DIN ), + .mp_cr_fifo_sram_DOUT (mp_cr_fifo_sram_DOUT ), + .mp_cr_fifo_sram_ADDR (mp_cr_fifo_sram_ADDR ), + .mp_cr_fifo_sram_CEN (mp_cr_fifo_sram_CEN ), + .mp_cr_fifo_sram_WEN (mp_cr_fifo_sram_WEN )); + always @ (viv_s245 or viv_s248 or viv_s242 or + viv_s254 or viv_s257 or viv_s251) begin + viv_s243 = 6'h0; + viv_s243[c_addr_width:0] = viv_s242; + viv_s246 = 6'h0; + viv_s246[c_addr_width:0] = viv_s245; + viv_s249 = 6'h0; + viv_s249[c_addr_width:0] = viv_s248; + viv_s252 = 6'h0; + viv_s252[c_addr_width:0] = viv_s251; + viv_s255 = 6'h0; + viv_s255[c_addr_width:0] = viv_s254; + viv_s258 = 6'h0; + viv_s258[c_addr_width:0] = viv_s257; + end + vsisp_marvin_mi_out u_marvin_mi_out + ( + .mp_line_sens (viv_s318), + .mp_output_format (mp_output_format_out), + .mp_y_llength (viv_s6), + .mp_slice_offset_y (viv_s7), + .mp_slice_offset_c (viv_s8), + .mp_byte_swap (viv_s9), + .sp_byte_swap (viv_s10), + .stat_skip_active (viv_s241), + .m_hclk (m_hclk), + .reset_m_hclk_n (reset_m_hclk_n), + .soft_rst_m_hclk (soft_rst_m_hclk), + .mp_fifo_read64 (viv_s231), + .mp_fifo_select (viv_s232), + .mp_fifo_data (viv_s233), + .mp_fifo_h_end (viv_s234), + .mp_fifo_v_end (viv_s235), + .sp_fifo_read64 (viv_s236), + .sp_fifo_select (viv_s237), + .sp_fifo_data (viv_s238), + .sp_fifo_h_end (viv_s239), + .sp_fifo_v_end (viv_s240), + .mp_y_fifo_fill_level (viv_s243), + .mp_y_fifo_flush (viv_s244), + .mp_cb_fifo_fill_level (viv_s246), + .mp_cb_fifo_flush (viv_s247), + .mp_cr_fifo_fill_level (viv_s249), + .mp_cr_fifo_flush (viv_s250), + .sp_y_fifo_fill_level (viv_s252), + .sp_y_fifo_flush (viv_s253), + .sp_cb_fifo_fill_level (viv_s255), + .sp_cb_fifo_flush (viv_s256), + .sp_cr_fifo_fill_level (viv_s258), + .sp_cr_fifo_flush (viv_s259), + .soft_upd (viv_s52), + .skip (viv_s53), + .mp_enable (viv_s29), + .sp_enable (viv_s30), + .jpeg_enable (viv_s31), + .raw_enable (viv_s32), + .dp_enable (viv_s33), + .h_flip (viv_s34), + .v_flip (viv_s35), + .rot (viv_s36), + .mp_write_format (viv_s49), + .sp_write_format (viv_s50), + .sp_output_format (viv_s51), + .byte_swap (viv_s37), + .init_base_en (viv_s38), + .init_offset_en (viv_s39), + .mp_pingpong_en (viv_s40), + .sp_pingpong_en (viv_s41), + .burst_len_lum (viv_s47), + .burst_len_chrom (viv_s48), + .stat_mp_enable_out (viv_s260), + .stat_sp_enable_out (viv_s261), + .stat_jpeg_enable_out (viv_s262), + .stat_raw_enable_out (viv_s263), + .stat_dp_enable_out (viv_s264), + .mp_y_base_ad (viv_s54), + .mp_y_size (viv_s55), + .mp_y_offs_cnt (viv_s56), + .mp_y_base_ad_init (viv_s57), + .mp_y_base_ad_init2 (viv_s58), + .mp_y_size_init (viv_s59), + .mp_y_offs_cnt_init (viv_s60), + .mp_y_offs_cnt_start (viv_s61), + .mp_y_irq_offs_init (viv_s62), + .mp_y_irq_offs (viv_s63), + .mp_cb_base_ad (viv_s64), + .mp_cb_size (viv_s65), + .mp_cb_offs_cnt (viv_s66), + .mp_cb_base_ad_init (viv_s67), + .mp_cb_base_ad_init2 (viv_s68), + .mp_cb_size_init (viv_s69), + .mp_cb_offs_cnt_init (viv_s70), + .mp_cb_offs_cnt_start (viv_s71), + .mp_cr_base_ad (viv_s72), + .mp_cr_size (viv_s73), + .mp_cr_offs_cnt (viv_s74), + .mp_cr_base_ad_init (viv_s75), + .mp_cr_base_ad_init2 (viv_s76), + .mp_cr_size_init (viv_s77), + .mp_cr_offs_cnt_init (viv_s78), + .mp_cr_offs_cnt_start (viv_s79), + .sp_y_base_ad (viv_s80), + .sp_y_size (viv_s81), + .sp_y_offs_cnt (viv_s82), + .sp_y_base_ad_init (viv_s83), + .sp_y_base_ad_init2 (viv_s84), + .sp_y_size_init (viv_s85), + .sp_y_offs_cnt_init (viv_s86), + .sp_y_offs_cnt_start (viv_s87), + .sp_y_pic_width (viv_s88), + .sp_y_llength (viv_s89), + .sp_y_pic_size (viv_s90), + .sp_cb_base_ad (viv_s91), + .sp_cb_size (viv_s92), + .sp_cb_offs_cnt (viv_s93), + .sp_cb_base_ad_init (viv_s94), + .sp_cb_base_ad_init2 (viv_s95), + .sp_cb_size_init (viv_s96), + .sp_cb_offs_cnt_init (viv_s97), + .sp_cb_offs_cnt_start (viv_s98), + .sp_cr_base_ad (viv_s99), + .sp_cr_size (viv_s100), + .sp_cr_offs_cnt (viv_s101), + .sp_cr_base_ad_init (viv_s102), + .sp_cr_base_ad_init2 (viv_s103), + .sp_cr_size_init (viv_s104), + .sp_cr_offs_cnt_init (viv_s105), + .sp_cr_offs_cnt_start (viv_s106), + .stat_mp_frame_end (viv_s276), + .stat_sp_frame_end (viv_s277), + .stat_mblk_line (viv_s278), + .stat_fill_mp_y (viv_s279), + .stat_wrap_mp_y (viv_s280), + .stat_wrap_mp_cb (viv_s281), + .stat_wrap_mp_cr (viv_s282), + .stat_wrap_sp_y (viv_s283), + .stat_wrap_sp_cb (viv_s284), + .stat_wrap_sp_cr (viv_s285), + .cfg_in_update_mp (viv_s270), + .cfg_in_update_sp (viv_s273), + .cfg_out_update_mp (viv_s298), + .cfg_out_update_sp (viv_s303), + .vci_out_m1_cmdval (vci_out_m1_cmdval), + .vci_out_m1_plen (vci_out_m1_plen), + .vci_out_m1_eop (vci_out_m1_eop), + .vci_out_m1_address (vci_out_m1_address), + .vci_out_m1_wdata (vci_out_m1_wdata), + .vci_out_m1_be (vci_out_m1_be), + .vci_out_m1_cmd (vci_out_m1_cmd), + .vci_out_m1_const (vci_out_m1_const), + .vci_out_m1_contig (vci_out_m1_contig), + .vci_out_m1_wrap (vci_out_m1_wrap), + .vci_out_m1_cmdack (vci_out_m1_cmdack), + .vci_out_m1_rspval (vci_out_m1_rspval), + .vci_out_m1_reop (vci_out_m1_reop), + .vci_out_m1_rspack (vci_out_m1_rspack), + .vci_out_m2_cmdval (vci_out_m2_cmdval), + .vci_out_m2_plen (vci_out_m2_plen), + .vci_out_m2_eop (vci_out_m2_eop), + .vci_out_m2_address (vci_out_m2_address), + .vci_out_m2_wdata (vci_out_m2_wdata), + .vci_out_m2_be (vci_out_m2_be), + .vci_out_m2_cmd (vci_out_m2_cmd), + .vci_out_m2_const (vci_out_m2_const), + .vci_out_m2_contig (vci_out_m2_contig), + .vci_out_m2_wrap (vci_out_m2_wrap), + .vci_out_m2_cmdack (vci_out_m2_cmdack), + .vci_out_m2_rspval (vci_out_m2_rspval), + .vci_out_m2_reop (vci_out_m2_reop), + .vci_out_m2_rspack (vci_out_m2_rspack), + .last_pixel_sig_en (viv_s0), + .last_pixel_m1_req (last_pixel_m1_req), + .last_pixel_m1_ack (last_pixel_m1_ack), + .last_pixel_m2_req (last_pixel_m2_req), + .last_pixel_m2_ack (last_pixel_m2_ack), + .handshake_en(viv_s312), + .starage_format(viv_s313), + .data_format(viv_s317), + .slice_size(viv_s314), + .slice_buf_size(viv_s315), + .ack_count(viv_s316), + .mp_interrupt(viv_s311), + .isp_0_ack (isp_0_ack), + .bresp_in (bresp_in), + .isp_0_ready (isp_0_ready), + .isp_0_attr (isp_0_attr), + .handshake_mode_0 (viv_s319), + .slice_cnt_int (viv_s320), + .sw_addr_mp_y (viv_s321), + .sw_addr_mp_cb (viv_s322), + .sw_addr_mp_cr (viv_s323), + .sw_interrupt (viv_s327)); + always @(posedge m_hclk or negedge reset_m_hclk_n) + begin + if (~reset_m_hclk_n) + begin + viv_s324[31:0] <= 32'h0; + viv_s325[31:0] <= 32'h0; + viv_s326[31:0] <= 32'h0; + end + else + begin + viv_s324[31:0] <= {1'b0,viv_s321[c_mi_data_addr:0]}; + viv_s325[31:0] <= {1'b0,viv_s322[c_mi_data_addr:0]}; + viv_s326[31:0] <= {1'b0,viv_s323[c_mi_data_addr:0]}; + end + end + assign viv_s275 = 1'b0; + assign viv_s286 = 1'b0; + assign vci_in_cmdval = 1'b0; + assign vci_in_plen = 9'b0; + assign vci_in_eop = 1'b0; + assign vci_in_address = 31'b0; + assign vci_in_be = 8'b0; + assign vci_in_cmd = 2'b0; + assign vci_in_const = 1'b0; + assign vci_in_contig = 1'b0; + assign vci_in_wrap = 1'b0; + assign vci_in_rspack = 1'b1; + assign out_y_val = 1'b0; + assign out_y_data = 8'b0; + assign out_y_h_end = 1'b0; + assign out_y_v_end = 1'b0; + assign out_y_cfg_update = 1'b0; + assign out_c_val = 1'b0; + assign out_c_data = 8'b0; + assign out_c_h_end = 1'b0; + assign out_c_v_end = 1'b0; + assign out_c_cfg_update = 1'b0; +wire viv_s372; + vsisp_marvin_mi_bp u_marvin_mi_bp( + .clk(jpeg_clk), + .reset_n(reset_jpeg_clk_n), + .soft_reset(viv_s291), + .m_hclk(m_hclk), + .reset_m_hclk_n(reset_m_hclk_n), + .soft_reset_m_hclk(soft_rst_m_hclk), + .test_mode(test_mode), + .in_bp_val(in_bp_val), + .in_bp_data(in_bp_data), + .in_bp_h_end(in_bp_h_end), + .in_bp_v_end(in_bp_v_end), + .in_bp_ack(in_bp_ack), + .in_bp_frame_end(in_bp_frame_end), + .vci_out_cmdval(vci_out_m3_cmdval), + .vci_out_plen(vci_out_m3_plen), + .vci_out_eop(vci_out_m3_eop), + .vci_out_address(vci_out_m3_address), + .vci_out_wdata(vci_out_m3_wdata), + .vci_out_be(vci_out_m3_be), + .vci_out_cmd(vci_out_m3_cmd), + .vci_out_const(vci_out_m3_const), + .vci_out_contig(vci_out_m3_contig), + .vci_out_wrap(vci_out_m3_wrap), + .vci_out_cmdack(vci_out_m3_cmdack), + .vci_out_rspval(vci_out_m3_rspval), + .vci_out_reop(vci_out_m3_reop), + .vci_out_rspack(vci_out_m3_rspack), + .last_pixel_sig_en(viv_s0), + .last_pixel_req(last_pixel_m3_req), + .last_pixel_ack(last_pixel_m3_ack), + .stat_mp_frame_end(viv_s365), + .stat_mblk_line(viv_s372), + .stat_fill_mp_r(viv_s366), + .stat_wrap_mp_r(viv_s367), + .stat_wrap_mp_gr(viv_s368), + .stat_wrap_mp_gb(viv_s369), + .stat_wrap_mp_b(viv_s370), + .bp_wr_size(viv_s328), + .bp_wr_size_init(viv_s329), + .bp_wr_llength(viv_s330), + .bp_wr_pic_width(viv_s331), + .bp_wr_pic_height(viv_s332), + .bp_r_irq_offs(viv_s346), + .bp_r_irq_offs_init(viv_s347), + .bp_r_base_ad(viv_s349), + .bp_r_offs_cnt(viv_s351), + .bp_r_base_ad_init(viv_s350), + .bp_r_offs_cnt_init(viv_s348), + .bp_r_offs_cnt_start(viv_s352), + .bp_gr_base_ad(viv_s353), + .bp_gr_offs_cnt(viv_s355), + .bp_gr_base_ad_init(viv_s354), + .bp_gr_offs_cnt_init(viv_s348), + .bp_gr_offs_cnt_start(viv_s356), + .bp_gb_base_ad(viv_s357), + .bp_gb_offs_cnt(viv_s359), + .bp_gb_base_ad_init(viv_s358), + .bp_gb_offs_cnt_init(viv_s348), + .bp_gb_offs_cnt_start(viv_s360), + .bp_b_base_ad(viv_s361), + .bp_b_offs_cnt(viv_s363), + .bp_b_base_ad_init(viv_s362), + .bp_b_offs_cnt_init(viv_s348), + .bp_b_offs_cnt_start(viv_s364), + .bp_y_fifo_sram_DIN(bp_ec_fifo_sram_DIN), + .bp_y_fifo_sram_DOUT(bp_ec_fifo_sram_DOUT), + .bp_y_fifo_sram_ADDR(bp_ec_fifo_sram_ADDR), + .bp_y_fifo_sram_CEN(bp_ec_fifo_sram_CEN), + .bp_y_fifo_sram_WEN(bp_ec_fifo_sram_WEN), + .bp_cb_fifo_sram_DIN(bp_oc_fifo_sram_DIN), + .bp_cb_fifo_sram_DOUT(bp_oc_fifo_sram_DOUT), + .bp_cb_fifo_sram_ADDR(bp_oc_fifo_sram_ADDR), + .bp_cb_fifo_sram_CEN(bp_oc_fifo_sram_CEN), + .bp_cb_fifo_sram_WEN(bp_oc_fifo_sram_WEN), + .bp_ecl_fifo_sram_buf_full(bp_ecl_fifo_sram_buf_full), + .bp_ocl_fifo_sram_buf_full(bp_ocl_fifo_sram_buf_full), + .bp_ecl_fifo_full(bp_ecl_fifo_full), + .bp_ocl_fifo_full(bp_ocl_fifo_full), + .path_enable_in (viv_s340), + .path_enable_out (viv_s341), + .auto_update (viv_s334), + .rformat (viv_s342), + .ralignen (viv_s343), + .write_format_in (viv_s344), + .write_format_out (viv_s345), + .burst_len (viv_s338), + .soft_upd_in(viv_s26), + .soft_upd_out(viv_s52), + .skip(viv_s53), + .byte_swap(viv_s37), + .mp_byte_swap(viv_s339), + .init_base_en(viv_s38), + .init_offset_en(viv_s39), + .bayer_pat(bayer_pat), + .data_mode_en(data_mode_en) +); + always @(posedge jpeg_clk or negedge reset_jpeg_clk_n) begin + if (~reset_jpeg_clk_n) begin + viv_s289 <= 1'b0; + viv_s290 <= 1'b0; + end + else begin + viv_s289 <= soft_rst; + viv_s290 <= viv_s289; + end + end + assign viv_s291 = viv_s290; +`ifdef FPGAa +`endif +`ifdef FPGA_DEBUG_ISP +(* mark_debug = "true" *) reg viv_s373;/* synthesis syn_noprune=1 syn_preserve = 1 */ +(* mark_debug = "true" *) reg viv_s374;/* synthesis syn_noprune=1 syn_preserve = 1 */ +(* mark_debug = "true" *) reg viv_s375;/* synthesis syn_noprune=1 syn_preserve = 1 */ +(* mark_debug = "true" *) reg viv_s376;/* synthesis syn_noprune=1 syn_preserve = 1 */ +(* mark_debug = "true" *) reg viv_s377;/* synthesis syn_noprune=1 syn_preserve = 1 */ +(* mark_debug = "true" *) reg viv_s378;/* synthesis syn_noprune=1 syn_preserve = 1 */ +(* mark_debug = "true" *) reg viv_s379;/* synthesis syn_noprune=1 syn_preserve = 1 */ +(* mark_debug = "true" *) reg viv_s380;/* synthesis syn_noprune=1 syn_preserve = 1 */ +(* mark_debug = "true" *) reg viv_s381;/* synthesis syn_noprune=1 syn_preserve = 1 */ +(* mark_debug = "true" *) reg viv_s382;/* synthesis syn_noprune=1 syn_preserve = 1 */ +(* mark_debug = "true" *) reg viv_s383;/* synthesis syn_noprune=1 syn_preserve = 1 */ +(* mark_debug = "true" *) reg viv_s384;/* synthesis syn_noprune=1 syn_preserve = 1 */ +(* mark_debug = "true" *) reg viv_s385;/* synthesis syn_noprune=1 syn_preserve = 1 */ +(* mark_debug = "true" *) reg viv_s386;/* synthesis syn_noprune=1 syn_preserve = 1 */ +(* mark_debug = "true" *) reg viv_s387;/* synthesis syn_noprune=1 syn_preserve = 1 */ +(* mark_debug = "true" *) reg viv_s388;/* synthesis syn_noprune=1 syn_preserve = 1 */ +(* mark_debug = "true" *) reg viv_s389;/* synthesis syn_noprune=1 syn_preserve = 1 */ +(* mark_debug = "true" *) reg viv_s390;/* synthesis syn_noprune=1 syn_preserve = 1 */ +(* mark_debug = "true" *) reg viv_s391;/* synthesis syn_noprune=1 syn_preserve = 1 */ +(* mark_debug = "true" *) reg viv_s392;/* synthesis syn_noprune=1 syn_preserve = 1 */ +(* mark_debug = "true" *) reg viv_s393;/* synthesis syn_noprune=1 syn_preserve = 1 */ +(* mark_debug = "true" *) reg viv_s394;/* synthesis syn_noprune=1 syn_preserve = 1 */ +(* mark_debug = "true" *) reg viv_s395;/* synthesis syn_noprune=1 syn_preserve = 1 */ +(* mark_debug = "true" *) reg viv_s396;/* synthesis syn_noprune=1 syn_preserve = 1 */ +(* mark_debug = "true" *) reg viv_s397;/* synthesis syn_noprune=1 syn_preserve = 1 */ +(* mark_debug = "true" *) reg viv_s398;/* synthesis syn_noprune=1 syn_preserve = 1 */ +(* mark_debug = "true" *) reg viv_s399;/* synthesis syn_noprune=1 syn_preserve = 1 */ +(* mark_debug = "true" *) reg viv_s400;/* synthesis syn_noprune=1 syn_preserve = 1 */ +(* mark_debug = "true" *) reg viv_s401;/* synthesis syn_noprune=1 syn_preserve = 1 */ +(* mark_debug = "true" *) reg viv_s402;/* synthesis syn_noprune=1 syn_preserve = 1 */ +(* mark_debug = "true" *) reg viv_s403;/* synthesis syn_noprune=1 syn_preserve = 1 */ +(* mark_debug = "true" *) reg viv_s404;/* synthesis syn_noprune=1 syn_preserve = 1 */ +always @(posedge m_hclk)begin + viv_s373 <= cfg_mi_val; + viv_s374 <= cfg_mi_addr; + viv_s375 <= cfg_mi_rd; + viv_s376 <= cfg_mi_wdata; + viv_s377 <= cfg_mi_rdata; + viv_s378 <= cfg_mi_ack; +end +always @(posedge clk)begin + viv_s379 <= in_mp_y_val; + viv_s380 <= in_mp_y_data; + viv_s381 <= in_mp_y_h_end; + viv_s382 <= in_mp_y_v_end; + viv_s383 <= in_mp_y_cfg_upd; + viv_s384 <= in_mp_y_ack; + viv_s385 <= in_mp_cb_val; + viv_s386 <= in_mp_cb_data; + viv_s387 <= in_mp_cb_h_end; + viv_s388 <= in_mp_cb_v_end; + viv_s389 <= in_mp_cb_cfg_upd; + viv_s390 <= in_mp_cb_ack; + viv_s391 <= in_mp_cr_val; + viv_s392 <= in_mp_cr_data; + viv_s393 <= in_mp_cr_h_end; + viv_s394 <= in_mp_cr_v_end; + viv_s395 <= in_mp_cr_cfg_upd; + viv_s396 <= in_mp_cr_ack; + viv_s397 <= in_bp_val; + viv_s398 <= in_bp_data; + viv_s399 <= in_bp_h_end; + viv_s400 <= in_bp_v_end; + viv_s401 <= in_bp_cfg_upd; + viv_s402 <= in_bp_ack; + viv_s403 <= in_bp_frame_end; + viv_s404 <= bayer_pat; +end +`endif +`ifdef FPGAa + `undef FPGA_DEBUG_ISP +`endif +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_marvin_mi_2to3.v b/ispyocto/rtl/ispyocto/vsisp_marvin_mi_2to3.v new file mode 100644 index 0000000..458fe32 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_marvin_mi_2to3.v
@@ -0,0 +1,206 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_marvin_mi_2to3 ( + clk, + reset_n, + soft_rst, + in_y_val, + in_y_data, + in_y_h_end, + in_y_v_end, + in_y_cfg_upd, + in_y_ack, + in_c_val, + in_c_data, + in_c_h_end, + in_c_v_end, + in_c_cfg_upd, + in_c_ack, + out_y_val, + out_y_data, + out_y_h_end, + out_y_v_end, + out_y_cfg_update, + out_y_ack, + out_cb_val, + out_cb_data, + out_cb_h_end, + out_cb_v_end, + out_cb_cfg_update, + out_cb_ack, + out_cr_val, + out_cr_data, + out_cr_h_end, + out_cr_v_end, + out_cr_cfg_update, + out_cr_ack +); +input clk; +input reset_n; +input soft_rst; +input in_y_val; +input [7:0] in_y_data; +input in_y_h_end; +input in_y_v_end; +input in_y_cfg_upd; +output in_y_ack; +wire in_y_ack; +input in_c_val; +input [7:0] in_c_data; +input in_c_h_end; +input in_c_v_end; +input in_c_cfg_upd; +output in_c_ack; +wire in_c_ack; +output out_y_val; +output [7:0] out_y_data; +output out_y_h_end; +output out_y_v_end; +output out_y_cfg_update; +input out_y_ack; +wire out_y_val; +wire [7:0] out_y_data; +wire out_y_h_end; +wire out_y_v_end; +wire out_y_cfg_update; +output out_cb_val; +output [7:0] out_cb_data; +output out_cb_h_end; +output out_cb_v_end; +output out_cb_cfg_update; +input out_cb_ack; +wire out_cb_val; +reg [7:0] out_cb_data; +wire out_cb_h_end; +wire out_cb_v_end; +wire out_cb_cfg_update; +output out_cr_val; +output [7:0] out_cr_data; +output out_cr_h_end; +output out_cr_v_end; +output out_cr_cfg_update; +input out_cr_ack; +wire out_cr_val; +reg [7:0] out_cr_data; +wire out_cr_h_end; +wire out_cr_v_end; +wire out_cr_cfg_update; +wire [10:0] viv_s0; +wire [10:0] viv_s1; +wire viv_s2; +wire [7:0] viv_s3; +wire viv_s4; +wire viv_s5; +wire viv_s6; +wire viv_s7; +wire [15:0] viv_s8; +wire [15:0] viv_s9; +wire [7:0] viv_s10; +wire [7:0] viv_s11; +wire viv_s12; +assign viv_s8 = {in_y_data, in_c_data}; +assign viv_s10 = viv_s8[15:8]; +assign viv_s11 = viv_s8[7 :0]; +assign out_y_data = viv_s10; +assign out_y_val = in_y_val; +assign out_y_h_end = in_y_h_end; +assign out_y_v_end = in_y_v_end; +assign out_y_cfg_update = in_y_cfg_upd; +assign in_y_ack = out_y_ack; +assign viv_s0 = {in_c_cfg_upd, in_c_v_end, in_c_h_end, viv_s11}; +vsisp_marvin_mi_dpsbe #(11) u_c_buf( + .clk ( clk ), + .reset_n ( reset_n ), + .soft_rst ( soft_rst ), + .dpsbe_data_i ( viv_s0 ), + .dpsbe_val_i ( in_c_val ), + .dpsbe_ack_o ( in_c_ack ), + .dpsbe_data_o ( viv_s1 ), + .dpsbe_val_o ( viv_s2 ), + .dpsbe_ack_i ( viv_s7 ) +); +assign viv_s3 = viv_s1[7:0]; +assign viv_s4 = viv_s1[8]; +assign viv_s5 = viv_s1[9]; +assign viv_s6 = viv_s1[10]; +reg viv_s13; +reg viv_s14; +reg viv_s15; +reg viv_s16; +wire viv_s17; +wire viv_s18; +wire viv_s19; +reg viv_s20; +wire viv_s21; +assign viv_s21 = out_cb_ack & out_cr_ack & viv_s19; +assign viv_s18 = viv_s21; +assign out_cb_val = viv_s21; +assign out_cb_h_end = viv_s13; +assign out_cb_v_end = viv_s14; +assign out_cb_cfg_update = viv_s15; +assign out_cr_val = viv_s21; +assign out_cr_h_end = viv_s13; +assign out_cr_v_end = viv_s14; +assign out_cr_cfg_update = viv_s15; +always @(posedge clk or negedge reset_n) begin + if (~reset_n) begin + out_cb_data <= {8{1'b0}}; + out_cr_data <= {8{1'b0}}; + viv_s13 <= 1'b0; + viv_s14 <= 1'b0; + viv_s15 <= 1'b0; + viv_s16 <= 1'b0; + viv_s20 <= 1'b0; + end + else if (soft_rst) begin + out_cb_data <= {8{1'b0}}; + out_cr_data <= {8{1'b0}}; + viv_s13 <= 1'b0; + viv_s14 <= 1'b0; + viv_s15 <= 1'b0; + viv_s16 <= 1'b0; + viv_s20 <= 1'b0; + end + else begin + if (viv_s2 & viv_s7) begin + viv_s20 <= (viv_s4) ? 1'b0 : ~viv_s20; + end + if (viv_s17) begin + viv_s16 <= viv_s2 & viv_s20; + if (viv_s20) begin + out_cr_data <= viv_s3; + end + else begin + out_cb_data <= viv_s3; + end + viv_s15 <= viv_s6; + viv_s13 <= viv_s4; + viv_s14 <= viv_s5; + end + end +end +assign viv_s17 = viv_s18 | (~viv_s16); +assign viv_s7 = viv_s17; +assign viv_s19 = viv_s16; +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_marvin_mi_bp.v b/ispyocto/rtl/ispyocto/vsisp_marvin_mi_bp.v new file mode 100644 index 0000000..e294d44 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_marvin_mi_bp.v
@@ -0,0 +1,570 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_marvin_mi_bp( +clk, +reset_n, +soft_reset, +m_hclk, +reset_m_hclk_n, +soft_reset_m_hclk, +test_mode, +in_bp_val, +in_bp_data, +in_bp_h_end, +in_bp_v_end, +in_bp_ack, +in_bp_frame_end, +vci_out_cmdval, +vci_out_plen, +vci_out_eop, +vci_out_address, +vci_out_wdata, +vci_out_be, +vci_out_cmd, +vci_out_const, +vci_out_contig, +vci_out_wrap, +vci_out_cmdack, +vci_out_rspval, +vci_out_reop, +vci_out_rspack, +last_pixel_sig_en, +last_pixel_req, +last_pixel_ack, +stat_mp_frame_end, +stat_mblk_line, +stat_fill_mp_r, +stat_wrap_mp_r, +stat_wrap_mp_gr, +stat_wrap_mp_gb, +stat_wrap_mp_b, +bp_wr_size, +bp_wr_size_init, +bp_wr_llength, +bp_wr_pic_width, +bp_wr_pic_height, +bp_r_irq_offs, +bp_r_irq_offs_init, +bp_r_base_ad, +bp_r_offs_cnt, +bp_r_base_ad_init, +bp_r_offs_cnt_init, +bp_r_offs_cnt_start, +bp_gr_base_ad, +bp_gr_offs_cnt, +bp_gr_base_ad_init, +bp_gr_offs_cnt_init, +bp_gr_offs_cnt_start, +bp_gb_base_ad, +bp_gb_offs_cnt, +bp_gb_base_ad_init, +bp_gb_offs_cnt_init, +bp_gb_offs_cnt_start, +bp_b_base_ad, +bp_b_offs_cnt, +bp_b_base_ad_init, +bp_b_offs_cnt_init, +bp_b_offs_cnt_start, +bp_y_fifo_sram_DIN, +bp_y_fifo_sram_DOUT, +bp_y_fifo_sram_ADDR, +bp_y_fifo_sram_CEN, +bp_y_fifo_sram_WEN, +bp_cb_fifo_sram_DIN, +bp_cb_fifo_sram_DOUT, +bp_cb_fifo_sram_ADDR, +bp_cb_fifo_sram_CEN, +bp_cb_fifo_sram_WEN, +bp_ecl_fifo_sram_buf_full, +bp_ocl_fifo_sram_buf_full, +bp_ecl_fifo_full, +bp_ocl_fifo_full, +soft_upd_in, +soft_upd_out, +skip, +path_enable_in, +path_enable_out, +auto_update, +byte_swap, +mp_byte_swap, +init_base_en, +init_offset_en, +burst_len, +write_format_in, +write_format_out, +rformat, +ralignen, +bayer_pat, +data_mode_en +); +`include "vsisp_marvin_mi.vh" +input clk; +input reset_n; +input soft_reset; +input m_hclk; +input reset_m_hclk_n; +input soft_reset_m_hclk; +input test_mode; +input in_bp_val; +input [15:0] in_bp_data; +input in_bp_h_end; +input in_bp_v_end; +output in_bp_ack; +input in_bp_frame_end; +output vci_out_cmdval; +output [8:0] vci_out_plen; +output vci_out_eop; +output [c_mi_data_addr+3:3] vci_out_address; +output [63:0] vci_out_wdata; +output [7:0] vci_out_be; +output [1:0] vci_out_cmd; +output vci_out_const; +output vci_out_contig; +output vci_out_wrap; +input vci_out_cmdack; +input vci_out_rspval; +input vci_out_reop; +output vci_out_rspack; +output last_pixel_req; +input last_pixel_ack; +input last_pixel_sig_en; +output stat_mp_frame_end; +output stat_mblk_line; +output stat_fill_mp_r; +output stat_wrap_mp_r; +output stat_wrap_mp_gr; +output stat_wrap_mp_gb; +output stat_wrap_mp_b; +output [c_mi_data_addr:3] bp_wr_size; +input [c_mi_data_addr:3] bp_wr_size_init; +input [14:0] bp_wr_llength; +input [14:0] bp_wr_pic_width; +input [14:0] bp_wr_pic_height; +output [c_mi_data_addr:3] bp_r_irq_offs; +input [c_mi_data_addr:3] bp_r_irq_offs_init; +output [c_mi_data_addr:3] bp_r_offs_cnt; +output [c_mi_data_addr+3:3] bp_r_base_ad; +input [c_mi_data_addr+3:3] bp_r_base_ad_init; +input [c_mi_data_addr:3] bp_r_offs_cnt_init; +output [c_mi_data_addr:3] bp_r_offs_cnt_start; +output [c_mi_data_addr+3:3] bp_gr_base_ad; +output [c_mi_data_addr:3] bp_gr_offs_cnt; +input [c_mi_data_addr+3:3] bp_gr_base_ad_init; +input [c_mi_data_addr:3] bp_gr_offs_cnt_init; +output [c_mi_data_addr:3] bp_gr_offs_cnt_start; +output [c_mi_data_addr+3:3] bp_gb_base_ad; +output [c_mi_data_addr:3] bp_gb_offs_cnt; +input [c_mi_data_addr+3:3] bp_gb_base_ad_init; +input [c_mi_data_addr:3] bp_gb_offs_cnt_init; +output [c_mi_data_addr:3] bp_gb_offs_cnt_start; +output [c_mi_data_addr+3:3] bp_b_base_ad; +output [c_mi_data_addr:3] bp_b_offs_cnt; +input [c_mi_data_addr+3:3] bp_b_base_ad_init; +input [c_mi_data_addr:3] bp_b_offs_cnt_init; +output [c_mi_data_addr:3] bp_b_offs_cnt_start; +input [65:0] bp_y_fifo_sram_DIN; +output [65:0] bp_y_fifo_sram_DOUT; +output [8:0] bp_y_fifo_sram_ADDR; +output bp_y_fifo_sram_CEN; +output bp_y_fifo_sram_WEN; +input [65:0] bp_cb_fifo_sram_DIN; +output [65:0] bp_cb_fifo_sram_DOUT; +output [8:0] bp_cb_fifo_sram_ADDR; +output bp_cb_fifo_sram_CEN; +output bp_cb_fifo_sram_WEN; +output bp_ecl_fifo_sram_buf_full; +output bp_ocl_fifo_sram_buf_full; +output bp_ecl_fifo_full; +output bp_ocl_fifo_full; +input path_enable_in; +input path_enable_out; +input auto_update; +input soft_upd_in; +input soft_upd_out; +input skip; +input byte_swap; +input [2:0] mp_byte_swap; +input init_base_en; +input init_offset_en; +input [1:0] burst_len; +input [1:0] write_format_in; +input [1:0] write_format_out; +input [3:0] rformat; +input [1:0] ralignen; +input [1:0] bayer_pat; +input data_mode_en; +assign bp_ecl_fifo_full=1'b0; +assign bp_ocl_fifo_full=1'b0; +wire viv_s0; +wire viv_s1=1'b0; +wire viv_s2 = (write_format_in == 2'b00 || write_format_in == 2'b01) & viv_s0; +wire [1:0] viv_s3 = write_format_out==2'b00 ? 2'b01: write_format_out; +wire [3:0] viv_s4 = viv_s3==2'b01 ? 4'b0010: 4'b0000; +wire [15:0] viv_s5, viv_s6; +wire [127:0] viv_s7, viv_s8; +wire viv_s9; +wire viv_s10; +wire viv_s11; +vsisp_dreg_en_1d #(1,1'd0) stat_path_enable_in_Reg (.clk(clk), .reset_n(reset_n), .soft_reset(1'b0), .out(viv_s0), .in(path_enable_in), .en(soft_upd_in|cfg_in_update_mp)); +vsisp_mi_bayer_split u_mi_bayer_split( + .clk(clk), + .reset_n(reset_n), + .soft_reset(soft_reset), + .in_data(in_bp_data&{16{viv_s2}}), + .in_hend(in_bp_h_end&viv_s2), + .in_vend(in_bp_v_end&viv_s2), + .in_val(in_bp_val&viv_s2), + .in_ack(in_bp_ack_plnr), + .out_data0(viv_s5), + .out_hend0(out_hend_ecl), + .out_vend0(out_vend_ecl), + .out_val0(out_val_ecl), + .out_ack0(viv_s2&viv_s9), + .out_data1(viv_s6), + .out_hend1(out_hend_ocl), + .out_vend1(out_vend_ocl), + .out_val1(out_val_ocl), + .out_ack1(out_ack_ocl) +); +wire [15:0] viv_s12 = viv_s2? viv_s5: in_bp_data; +wire viv_s13 = viv_s2? out_val_ecl: in_bp_val; +wire viv_s14 = viv_s2? out_hend_ecl: in_bp_h_end; +wire viv_s15 = viv_s2? out_vend_ecl: in_bp_v_end; +wire in_bp_ack = viv_s2? in_bp_ack_plnr: viv_s9; + vsisp_mi_dp_raw u_mi_dp_raw_ecl ( + .clk(clk), + .reset_n(reset_n), + .soft_rst(soft_reset), + .rformat(rformat), + .ralignen(ralignen), + .rpadpseud(viv_s1), + .in_raw(viv_s12), + .in_h_end(viv_s14), + .in_v_end(viv_s15), + .in_ack(viv_s9), + .in_val(viv_s13), + .out_duo(out_duo_dp_ecl), + .out_h_end(out_hend_dp_ecl), + .out_v_end(out_vend_dp_ecl), + .out_fifo_full(~out_ack_dp_ecl), + .out_val(out_val_dp_ecl), + .out_raw(viv_s7), + .out_cfg_upd(out_cfg_upd_ecl), + .cfg_in_update(cfg_in_update_mp), + .cfg_out_update(cfg_out_update_mp), + .auto_update(auto_update), + .path_enable(viv_s0) +); +wire [63:0] viv_s16, viv_s17; + vsisp_mi_dp_outstage u_mi_dp_outstage_ecl( + .clk(clk), + .reset_n(reset_n), + .soft_reset(soft_reset), + .in_val(out_val_dp_ecl), + .in_data(viv_s7), + .in_hend(out_hend_dp_ecl), + .in_vend(out_vend_dp_ecl), + .in_ack(out_ack_dp_ecl), + .in_duo(out_duo_dp_ecl), + .out_val(mp_ecl_fifo_write64), + .out_data(viv_s16), + .out_hend(mp_ecl_fifo_h_end), + .out_vend(mp_ecl_fifo_v_end), + .out_ack(~mp_ecl_fifo_full) + ); + vsisp_mi_dp_raw u_mi_dp_raw_ocl ( + .clk(clk), + .reset_n(reset_n), + .soft_rst(soft_reset), + .rformat(rformat), + .ralignen(ralignen), + .rpadpseud(viv_s1), + .in_raw(viv_s6), + .in_h_end(out_hend_ocl), + .in_v_end(out_vend_ocl), + .in_ack(out_ack_ocl), + .in_val(out_val_ocl), + .out_duo(out_duo_dp_ocl), + .out_h_end(out_hend_dp_ocl), + .out_v_end(out_vend_dp_ocl), + .out_fifo_full(~out_ack_dp_ocl), + .out_val(out_val_dp_ocl), + .out_raw(viv_s8), + .out_cfg_upd(out_cfg_upd_ocl), + .cfg_in_update(), + .cfg_out_update(1'b0), + .auto_update(1'b0), + .path_enable(viv_s0) +); + vsisp_mi_dp_outstage u_mi_dp_outstage_ocl( + .clk(clk), + .reset_n(reset_n), + .soft_reset(soft_reset), + .in_val(out_val_dp_ocl), + .in_data(viv_s8), + .in_hend(out_hend_dp_ocl), + .in_vend(out_vend_dp_ocl), + .in_ack(out_ack_dp_ocl), + .in_duo(out_duo_dp_ocl), + .out_val(mp_ocl_fifo_write64), + .out_data(viv_s17), + .out_hend(mp_ocl_fifo_h_end), + .out_vend(mp_ocl_fifo_v_end), + .out_ack(~mp_ocl_fifo_full) + ); +wire viv_s18=1'b0; +wire [1:0] viv_s19=2'b00; +wire [1:0] viv_s20; +wire [63:0] viv_s21; +wire [c_fifo_depth_bw-1:0] viv_s22, viv_s23; + vsisp_marvin_mi_fifo_bp #(.c_fifo_depth(c_fifo_depth)) u_marvin_mi_fifo + ( + .sw_mi_fifo_depth_ctrl (viv_s19), + .clk (clk), + .reset_n (reset_n), + .soft_rst (soft_reset), + .m_hclk (m_hclk), + .reset_m_hclk_n (reset_m_hclk_n), + .soft_rst_m_hclk (soft_reset_m_hclk), + .test_mode (test_mode), + .sp_rot_in (viv_s18), + .wr_resume (viv_s10), + .plnr_wrt (viv_s2), + .mp_y_fifo_data_in (viv_s16), + .mp_y_fifo_h_end_in (mp_ecl_fifo_h_end), + .mp_y_fifo_v_end_in (mp_ecl_fifo_v_end), + .mp_y_fifo_write64 (mp_ecl_fifo_write64), + .mp_y_fifo_full (mp_ecl_fifo_full), + .mp_y_fifo_sram_buf_full (bp_ecl_fifo_sram_buf_full ), + .mp_cb_fifo_data_in (viv_s17), + .mp_cb_fifo_h_end_in (mp_ocl_fifo_h_end), + .mp_cb_fifo_v_end_in (mp_ocl_fifo_v_end), + .mp_cb_fifo_write64 (mp_ocl_fifo_write64), + .mp_cb_fifo_full (mp_ocl_fifo_full), + .mp_cb_fifo_sram_buf_full(bp_ocl_fifo_sram_buf_full ), + .mp_cr_fifo_data_in (64'h0), + .mp_cr_fifo_h_end_in (1'h0), + .mp_cr_fifo_v_end_in (1'h0), + .mp_cr_fifo_write64 (1'h0), + .mp_cr_fifo_full (), + .mp_cr_fifo_sram_buf_full(), + .sp_y_fifo_data_in (64'h0), + .sp_y_fifo_h_end_in (1'h0), + .sp_y_fifo_v_end_in (1'h0), + .sp_y_fifo_write64 (1'h0), + .sp_y_fifo_full (), + .sp_cb_fifo_data_in (64'h0), + .sp_cb_fifo_h_end_in (1'h0), + .sp_cb_fifo_v_end_in (1'h0), + .sp_cb_fifo_write64 (1'h0), + .sp_cb_fifo_full (), + .sp_cr_fifo_data_in (64'h0), + .sp_cr_fifo_h_end_in (1'h0), + .sp_cr_fifo_v_end_in (1'h0), + .sp_cr_fifo_write64 (1'h0), + .sp_cr_fifo_full (), + .mp_fifo_read64 (mp_fifo_read64), + .mp_fifo_select (viv_s20), + .mp_fifo_data_out (viv_s21), + .mp_fifo_h_end_out (mp_fifo_h_end_out), + .mp_fifo_v_end_out (mp_fifo_v_end_out), + .sp_fifo_read64 (1'h0), + .sp_fifo_select (2'h0), + .sp_fifo_data_out (), + .sp_fifo_h_end_out (), + .sp_fifo_v_end_out (), + .mp_y_fifo_fill_level (viv_s22), + .mp_y_fifo_flush (mp_y_fifo_flush), + .mp_cb_fifo_fill_level (viv_s23), + .mp_cb_fifo_flush (mp_cb_fifo_flush), + .mp_cr_fifo_fill_level (), + .mp_cr_fifo_flush (), + .sp_y_fifo_fill_level (), + .sp_y_fifo_flush (), + .sp_cb_fifo_fill_level (), + .sp_cb_fifo_flush (), + .sp_cr_fifo_fill_level (), + .sp_cr_fifo_flush (), + .mp_y_fifo_sram_DIN (bp_y_fifo_sram_DIN ), + .mp_y_fifo_sram_DOUT (bp_y_fifo_sram_DOUT ), + .mp_y_fifo_sram_ADDR (bp_y_fifo_sram_ADDR ), + .mp_y_fifo_sram_CEN (bp_y_fifo_sram_CEN ), + .mp_y_fifo_sram_WEN (bp_y_fifo_sram_WEN ), + .mp_cb_fifo_sram_DIN (bp_cb_fifo_sram_DIN ), + .mp_cb_fifo_sram_DOUT (bp_cb_fifo_sram_DOUT ), + .mp_cb_fifo_sram_ADDR (bp_cb_fifo_sram_ADDR ), + .mp_cb_fifo_sram_CEN (bp_cb_fifo_sram_CEN ), + .mp_cb_fifo_sram_WEN (bp_cb_fifo_sram_WEN ), + .mp_cr_fifo_sram_DIN (66'h0), + .mp_cr_fifo_sram_DOUT (), + .mp_cr_fifo_sram_ADDR (), + .mp_cr_fifo_sram_CEN (), + .mp_cr_fifo_sram_WEN ()); +wire viv_s24; +vsisp_dreg_en_2d #(1,1'd0) data_mode_en_Reg (.clk(m_hclk), .reset_n(reset_m_hclk_n), .soft_reset(soft_reset_m_hclk), .out(viv_s24), .in(data_mode_en), .en(1'b1)); +wire viv_s25= ~viv_s24 & (viv_s3==2'b10 ? bp_wr_llength != bp_wr_pic_width : bp_wr_llength != (bp_wr_pic_width>>1'b1)); +wire viv_s26; +wire viv_s27; +wire viv_s28; +wire [1:0] viv_s29; +vsisp_marvin_mi_out_bp u_marvin_mi_out_bp + ( + .m_hclk(m_hclk), + .reset_m_hclk_n(reset_m_hclk_n), + .soft_rst_m_hclk(soft_reset_m_hclk), + .mp_fifo_read64(mp_fifo_read64), + .mp_fifo_select(viv_s20), + .mp_fifo_data(viv_s21), + .mp_fifo_h_end(mp_fifo_h_end_out), + .mp_fifo_v_end(mp_fifo_v_end_out), + .mp_y_fifo_fill_level(viv_s22), + .mp_y_fifo_flush(mp_y_fifo_flush), + .mp_cb_fifo_fill_level(viv_s23), + .mp_cb_fifo_flush(mp_cb_fifo_flush), + .mp_cr_fifo_fill_level({c_fifo_depth_bw{1'b0}}), + .mp_cr_fifo_flush(1'b0), + .soft_upd(soft_upd_out), + .skip(skip), + .mp_enable(path_enable_out), + .jpeg_enable(1'b0), + .raw_enable(1'b0), + .dp_enable(1'b0), + .mp_write_format(viv_s3), + .byte_swap(1'b0), + .init_base_en(init_base_en), + .init_offset_en(init_offset_en), + .mp_pingpong_en(1'b0), + .burst_len_lum(burst_len), + .burst_len_chrom(burst_len), + .stat_mp_enable_out(), + .stat_jpeg_enable_out(), + .stat_raw_enable_out(), + .stat_dp_enable_out(), + .plnr_wrt(viv_s2), + .val_1st_pxl(viv_s28), + .bayer_pat(viv_s29), + .line_tgl_en(viv_s11), + .mp_r_base_ad(bp_r_base_ad), + .mp_r_size(bp_wr_size), + .mp_r_offs_cnt(bp_r_offs_cnt), + .mp_r_base_ad_init(bp_r_base_ad_init), + .mp_r_base_ad_init2({c_mi_data_addr+1{1'b0}}), + .mp_r_size_init(bp_wr_size_init), + .mp_r_offs_cnt_init(bp_r_offs_cnt_init), + .mp_r_offs_cnt_start(bp_r_offs_cnt_start), + .mp_r_irq_offs_init(bp_r_irq_offs_init), + .mp_r_irq_offs(bp_r_irq_offs), + .mp_gr_base_ad(bp_gr_base_ad), + .mp_gr_size(), + .mp_gr_offs_cnt(bp_gr_offs_cnt), + .mp_gr_base_ad_init(bp_gr_base_ad_init), + .mp_gr_base_ad_init2({c_mi_data_addr+1{1'b0}}), + .mp_gr_size_init(bp_wr_size_init), + .mp_gr_offs_cnt_init(bp_gr_offs_cnt_init), + .mp_gr_offs_cnt_start(bp_gr_offs_cnt_start), + .mp_gb_base_ad(bp_gb_base_ad), + .mp_gb_size(), + .mp_gb_offs_cnt(bp_gb_offs_cnt), + .mp_gb_base_ad_init(bp_gb_base_ad_init), + .mp_gb_base_ad_init2({c_mi_data_addr+1{1'b0}}), + .mp_gb_size_init(bp_wr_size_init), + .mp_gb_offs_cnt_init(bp_gb_offs_cnt_init), + .mp_gb_offs_cnt_start(bp_gb_offs_cnt_start), + .mp_b_base_ad(bp_b_base_ad), + .mp_b_size(), + .mp_b_offs_cnt(bp_b_offs_cnt), + .mp_b_base_ad_init(bp_b_base_ad_init), + .mp_b_base_ad_init2({c_mi_data_addr+1{1'b0}}), + .mp_b_size_init(bp_wr_size_init), + .mp_b_offs_cnt_init(bp_b_offs_cnt_init), + .mp_b_offs_cnt_start(bp_b_offs_cnt_start), + .mp_addr_cur_y( {c_mi_data_addr+1{1'b0}}), + .mp_addr_cur_cb({c_mi_data_addr+1{1'b0}}), + .mp_addr_cur_cr({c_mi_data_addr+1{1'b0}}), + .handshake_en(1'b0), + .stat_mp_frame_end(frame_end_int_out), + .stat_mblk_line(stat_mblk_line), + .stat_fill_mp_r(stat_fill_mp_r), + .stat_wrap_mp_r(stat_wrap_mp_r), + .stat_wrap_mp_gr(stat_wrap_mp_gr), + .stat_wrap_mp_gb(stat_wrap_mp_gb), + .stat_wrap_mp_b(stat_wrap_mp_b), + .cfg_in_update_mp(cfg_in_update_mp), + .cfg_out_update_mp(cfg_out_update_mp), + .vci_out_m1_cmdval(vci_out_cmdval), + .vci_out_m1_plen(vci_out_plen), + .vci_out_m1_eop(vci_out_eop), + .vci_out_m1_address(vci_out_address), + .vci_out_m1_wdata(vci_out_wdata), + .vci_out_m1_be(vci_out_be), + .vci_out_m1_cmd(vci_out_cmd), + .vci_out_m1_const(vci_out_const), + .vci_out_m1_contig(vci_out_contig), + .vci_out_m1_wrap(vci_out_wrap), + .vci_out_m1_cmdack(vci_out_cmdack), + .vci_out_m1_rspval(vci_out_rspval), + .vci_out_m1_reop(vci_out_reop), + .vci_out_m1_rspack(vci_out_rspack), + .last_pixel_sig_en(last_pixel_sig_en), + .last_pixel_m1_req(last_pixel_req), + .last_pixel_m1_ack(last_pixel_ack), + .mp_byte_swap(mp_byte_swap), + .mp_output_format(viv_s4), + .mp_y_llength(bp_wr_llength), + .cfg_upd_double(viv_s26), + .stat_skip_active(viv_s27), + .data_mode_en(viv_s24), + .mp_line_sens(viv_s25) + ); +wire viv_s30; +wire viv_s31; +vsisp_dreg_en_1d #(1,1'b0) frame_end_ptr_reg (.clk(clk), .reset_n(reset_n), .soft_reset(soft_reset), .out(viv_s31), .in(in_bp_frame_end), .en(1'b1)); +vsisp_dreg_en_1d #(1,1'b0) frame_end_tgl_reg (.clk(clk), .reset_n(reset_n), .soft_reset(soft_reset), .out(viv_s30), .in(~viv_s30), .en(in_bp_frame_end & ~viv_s31)); +vsisp_dreg_en_1d #(1,1'b0) frame_end_tgl_reg0 (.clk(m_hclk), .reset_n(reset_m_hclk_n), .soft_reset(soft_reset_m_hclk), .out(frame_end_tgl_d0), .in(viv_s30), .en(1'b1)); +vsisp_dreg_en_1d #(1,1'b0) frame_end_tgl_reg1 (.clk(m_hclk), .reset_n(reset_m_hclk_n), .soft_reset(soft_reset_m_hclk), .out(frame_end_tgl_d1), .in(frame_end_tgl_d0), .en(1'b1)); +vsisp_dreg_en_1d #(1,1'b0) frame_end_tgl_reg2 (.clk(m_hclk), .reset_n(reset_m_hclk_n), .soft_reset(soft_reset_m_hclk), .out(frame_end_tgl_d2), .in(frame_end_tgl_d1), .en(1'b1)); +wire viv_s32 = frame_end_tgl_d2 ^ frame_end_tgl_d1; +wire viv_s33; +wire viv_s34 = ~stat_mp_frame_end & (viv_s32 | viv_s33); +vsisp_dreg_en_1d #(1,1'b0) frame_end_active_locked_reg (.clk(m_hclk), .reset_n(reset_m_hclk_n), .soft_reset(soft_reset_m_hclk), .out(viv_s33), .in(viv_s34), .en(1'b1)); +wire viv_s35; +wire viv_s36 = ~stat_mp_frame_end & (frame_end_int_out | viv_s35) ; +vsisp_dreg_en_1d #(1,1'b0) frame_end_int_out_locked_reg (.clk(m_hclk), .reset_n(reset_m_hclk_n), .soft_reset(soft_reset_m_hclk), .out(viv_s35), .in(viv_s36), .en(1'b1)); +assign stat_mp_frame_end = viv_s33 & viv_s35; +wire viv_s37, viv_s38; +wire viv_s39 = in_bp_val & path_enable_in; +wire viv_s40 = (viv_s39 & in_bp_ack) & viv_s37 ? ~viv_s28: viv_s28; +assign viv_s38 = (viv_s39 & in_bp_ack) & viv_s37 ? 1'b0: + (viv_s39 & in_bp_ack) & in_bp_v_end & in_bp_h_end ? 1'b1: viv_s37; +wire [1:0] viv_s41 = (viv_s39 & in_bp_ack) & viv_s37 ? bayer_pat: viv_s29; +vsisp_dreg_en_1d #(1,1'b0) u_val_1st_pxl (.clk(clk), .reset_n(reset_n), .soft_reset(soft_reset), .out(viv_s28), .in(viv_s40), .en(1'b1)); +vsisp_dreg_en_1d #(1,1'b1) u_tgl_en (.clk(clk), .reset_n(reset_n), .soft_reset(soft_reset), .out(viv_s37), .in(viv_s38), .en(1'b1)); +vsisp_dreg_en_1d #(2,2'b0) u_bayer_pat (.clk(clk), .reset_n(reset_n), .soft_reset(soft_reset), .out(viv_s29), .in(bayer_pat), .en(1'b1)); +wire viv_s42; +vsisp_dreg_en_1d #(1,1'b0) wr_resume_tgl_reg (.clk(m_hclk), .reset_n(reset_m_hclk_n), .soft_reset(soft_reset_m_hclk), .out(viv_s42), .in(~viv_s42), .en(viv_s11)); +vsisp_dreg_en_1d #(1,1'b0) wr_resume_tgl_reg0 (.clk(clk), .reset_n(reset_n), .soft_reset(soft_reset), .out(wr_resume_tgl_d0), .in(viv_s42), .en(1'b1)); +vsisp_dreg_en_1d #(1,1'b0) wr_resume_tgl_reg1 (.clk(clk), .reset_n(reset_n), .soft_reset(soft_reset), .out(wr_resume_tgl_d1), .in(wr_resume_tgl_d0), .en(1'b1)); +vsisp_dreg_en_1d #(1,1'b0) wr_resume_tgl_reg2 (.clk(clk), .reset_n(reset_n), .soft_reset(soft_reset), .out(wr_resume_tgl_d2), .in(wr_resume_tgl_d1), .en(1'b1)); +assign viv_s10 = wr_resume_tgl_d2 ^ wr_resume_tgl_d1; +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_marvin_mi_dpsbe.v b/ispyocto/rtl/ispyocto/vsisp_marvin_mi_dpsbe.v new file mode 100644 index 0000000..0a7c294 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_marvin_mi_dpsbe.v
@@ -0,0 +1,74 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_marvin_mi_dpsbe +( clk, + reset_n, + soft_rst, + dpsbe_data_i, + dpsbe_val_i, + dpsbe_ack_o, + dpsbe_data_o, + dpsbe_val_o, + dpsbe_ack_i +); + parameter c_dpsbe_data_width = 8; + input clk; + input reset_n; + input soft_rst; + input [c_dpsbe_data_width-1:0] dpsbe_data_i; + input dpsbe_val_i; + output dpsbe_ack_o; + output [c_dpsbe_data_width-1:0] dpsbe_data_o; + output dpsbe_val_o; + input dpsbe_ack_i; + reg [c_dpsbe_data_width-1:0] viv_s0; + reg viv_s1; + reg viv_s2; + wire viv_s3; + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + viv_s0 <= {c_dpsbe_data_width{1'b0}}; + viv_s1 <= 1'b0; + viv_s2 <= 1'b0; + end + else if (soft_rst) begin + viv_s0 <= {c_dpsbe_data_width{1'b0}}; + viv_s1 <= 1'b0; + viv_s2 <= 1'b0; + end + else begin + viv_s2 <= dpsbe_ack_i | (!viv_s3); + if (viv_s2) begin + viv_s1 <= dpsbe_val_i; + end + if (viv_s2) begin + viv_s0 <= dpsbe_data_i; + end + end + end + assign dpsbe_data_o = viv_s2 ? dpsbe_data_i : viv_s0; + assign viv_s3 = viv_s2 ? dpsbe_val_i : viv_s1; + assign dpsbe_val_o = viv_s3; + assign dpsbe_ack_o = viv_s2; +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_marvin_mi_fifo.v b/ispyocto/rtl/ispyocto/vsisp_marvin_mi_fifo.v new file mode 100644 index 0000000..4c2d548 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_marvin_mi_fifo.v
@@ -0,0 +1,505 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_marvin_mi_fifo + ( + clk, + reset_n, + soft_rst, + m_hclk, + reset_m_hclk_n, + soft_rst_m_hclk, + test_mode, + sp_rot_in, + sw_mi_fifo_depth_ctrl, + mp_y_fifo_data_in, + mp_y_fifo_h_end_in, + mp_y_fifo_v_end_in, + mp_y_fifo_write64, + mp_y_fifo_full, + mp_y_fifo_sram_buf_full, + mp_cb_fifo_data_in, + mp_cb_fifo_h_end_in, + mp_cb_fifo_v_end_in, + mp_cb_fifo_write64, + mp_cb_fifo_full, + mp_cb_fifo_sram_buf_full, + mp_cr_fifo_data_in, + mp_cr_fifo_h_end_in, + mp_cr_fifo_v_end_in, + mp_cr_fifo_write64, + mp_cr_fifo_full, + mp_cr_fifo_sram_buf_full, + sp_y_fifo_data_in, + sp_y_fifo_h_end_in, + sp_y_fifo_v_end_in, + sp_y_fifo_write64, + sp_y_fifo_full, + sp_cb_fifo_data_in, + sp_cb_fifo_h_end_in, + sp_cb_fifo_v_end_in, + sp_cb_fifo_write64, + sp_cb_fifo_full, + sp_cr_fifo_data_in, + sp_cr_fifo_h_end_in, + sp_cr_fifo_v_end_in, + sp_cr_fifo_write64, + sp_cr_fifo_full, + mp_fifo_read64, + mp_fifo_select, + mp_fifo_data_out, + mp_fifo_h_end_out, + mp_fifo_v_end_out, + sp_fifo_read64, + sp_fifo_select, + sp_fifo_data_out, + sp_fifo_h_end_out, + sp_fifo_v_end_out, + mp_y_fifo_fill_level, + mp_y_fifo_flush, + mp_cb_fifo_fill_level, + mp_cb_fifo_flush, + mp_cr_fifo_fill_level, + mp_cr_fifo_flush, + sp_y_fifo_fill_level, + sp_y_fifo_flush, + sp_cb_fifo_fill_level, + sp_cb_fifo_flush, + sp_cr_fifo_fill_level, + sp_cr_fifo_flush, + mp_y_fifo_sram_DIN, + mp_y_fifo_sram_DOUT, + mp_y_fifo_sram_ADDR, + mp_y_fifo_sram_CEN, + mp_y_fifo_sram_WEN, + mp_cb_fifo_sram_DIN, + mp_cb_fifo_sram_DOUT, + mp_cb_fifo_sram_ADDR, + mp_cb_fifo_sram_CEN, + mp_cb_fifo_sram_WEN, + mp_cr_fifo_sram_DIN, + mp_cr_fifo_sram_DOUT, + mp_cr_fifo_sram_ADDR, + mp_cr_fifo_sram_CEN, + mp_cr_fifo_sram_WEN + ); + `include "vsisp_isp.vh" + `include "vsisp_ram_sizes.vh" + parameter c_fifo_depth = 8; + parameter c_addr_width = (c_fifo_depth <= 1) ? 0 : + (c_fifo_depth <= 2) ? 1 : + (c_fifo_depth <= 4) ? 2 : + (c_fifo_depth <= 8) ? 3 : + (c_fifo_depth <= 16) ? 4 : + (c_fifo_depth <= 32) ? 5 : + (c_fifo_depth <= 64) ? 6 : + (c_fifo_depth <= 128) ? 7 : 8; + input clk; + input reset_n; + input soft_rst; + input m_hclk; + input reset_m_hclk_n; + input soft_rst_m_hclk; + input test_mode; + input sp_rot_in; + input [1:0] sw_mi_fifo_depth_ctrl; + input [63:0] mp_y_fifo_data_in; + input mp_y_fifo_h_end_in; + input mp_y_fifo_v_end_in; + input mp_y_fifo_write64; + output mp_y_fifo_full; + output mp_y_fifo_sram_buf_full; + input [63:0] mp_cb_fifo_data_in; + input mp_cb_fifo_h_end_in; + input mp_cb_fifo_v_end_in; + input mp_cb_fifo_write64; + output mp_cb_fifo_full; + output mp_cb_fifo_sram_buf_full; + input [63:0] mp_cr_fifo_data_in; + input mp_cr_fifo_h_end_in; + input mp_cr_fifo_v_end_in; + input mp_cr_fifo_write64; + output mp_cr_fifo_full; + output mp_cr_fifo_sram_buf_full; + input [63:0] sp_y_fifo_data_in; + input sp_y_fifo_h_end_in; + input sp_y_fifo_v_end_in; + input sp_y_fifo_write64; + output sp_y_fifo_full; + input [63:0] sp_cb_fifo_data_in; + input sp_cb_fifo_h_end_in; + input sp_cb_fifo_v_end_in; + input sp_cb_fifo_write64; + output sp_cb_fifo_full; + input [63:0] sp_cr_fifo_data_in; + input sp_cr_fifo_h_end_in; + input sp_cr_fifo_v_end_in; + input sp_cr_fifo_write64; + output sp_cr_fifo_full; + input mp_fifo_read64; + input [1:0] mp_fifo_select; + output [63:0] mp_fifo_data_out; + output mp_fifo_h_end_out; + output mp_fifo_v_end_out; + reg [63:0] mp_fifo_data_out; + reg mp_fifo_h_end_out; + reg mp_fifo_v_end_out; + input sp_fifo_read64; + input [1:0] sp_fifo_select; + output [63:0] sp_fifo_data_out; + output sp_fifo_h_end_out; + output sp_fifo_v_end_out; + reg [63:0] sp_fifo_data_out; + reg sp_fifo_h_end_out; + reg sp_fifo_v_end_out; + output [c_addr_width:0] mp_y_fifo_fill_level; + output mp_y_fifo_flush; + reg viv_s0; + wire [63:0] viv_s1; + wire viv_s2; + wire viv_s3; + output [c_addr_width:0] mp_cb_fifo_fill_level; + output mp_cb_fifo_flush; + reg viv_s4; + wire [63:0] viv_s5; + wire viv_s6; + wire viv_s7; + output [c_addr_width:0] mp_cr_fifo_fill_level; + output mp_cr_fifo_flush; + reg viv_s8; + wire [63:0] viv_s9; + wire viv_s10; + wire viv_s11; + output [c_addr_width:0] sp_y_fifo_fill_level; + output sp_y_fifo_flush; + reg viv_s12; + wire [63:0] viv_s13; + wire viv_s14; + wire viv_s15; + output [c_addr_width:0] sp_cb_fifo_fill_level; + output sp_cb_fifo_flush; + reg viv_s16; + wire [63:0] viv_s17; + wire viv_s18; + wire viv_s19; + output [c_addr_width:0] sp_cr_fifo_fill_level; + output sp_cr_fifo_flush; + reg viv_s20; + wire [63:0] viv_s21; + wire viv_s22; + wire viv_s23; + input [65:0] mp_y_fifo_sram_DIN; + output [65:0] mp_y_fifo_sram_DOUT; + output [ c_mi_mp_y_aw -1:0]mp_y_fifo_sram_ADDR; + output mp_y_fifo_sram_CEN; + output mp_y_fifo_sram_WEN; + input [65:0] mp_cb_fifo_sram_DIN; + output [65:0] mp_cb_fifo_sram_DOUT; + output [ c_mi_mp_c_aw -1:0]mp_cb_fifo_sram_ADDR; + output mp_cb_fifo_sram_CEN; + output mp_cb_fifo_sram_WEN; + input [65:0] mp_cr_fifo_sram_DIN; + output [65:0] mp_cr_fifo_sram_DOUT; + output [ c_mi_mp_c_aw -1:0]mp_cr_fifo_sram_ADDR; + output mp_cr_fifo_sram_CEN; + output mp_cr_fifo_sram_WEN; + wire viv_s24; + wire viv_s25; + wire viv_s26; + wire viv_s27; + wire viv_s28; + wire viv_s29; + wire viv_s30; + wire viv_s31; + wire [65:0] viv_s32; + wire [65:0] viv_s33; + wire [65:0] viv_s34; + wire [65:0] viv_s35; + wire [65:0] viv_s36; + wire [65:0] viv_s37; + wire viv_s38, viv_s39; + wire viv_s40, viv_s41; + wire viv_s42, viv_s43; + wire viv_s44, viv_s45; + wire viv_s46, viv_s47; + wire viv_s48, viv_s49; + wire viv_s50; + wire [63:0] viv_s51; + wire viv_s52; + wire viv_s53; + wire viv_s54; + wire [63:0] viv_s55; + wire viv_s56; + wire viv_s57; + wire viv_s58; + wire [63:0] viv_s59; + wire viv_s60; + wire viv_s61; + wire viv_s62, viv_s63, viv_s64; + vsisp_sync_fifo_reset_gen_wr u_sync_fifo_dma_rst_wr + ( + .wr_clk (clk), + .reset_n (reset_n ), + .soft_reset(soft_rst), + .test_mode (test_mode), + .wr_reset_n(viv_s24) + ); + vsisp_sync_fifo_reset_gen_rd u_sync_fifo_dma_rst_rd + ( + .rd_clk (m_hclk), + .reset_n (reset_m_hclk_n), + .soft_reset(soft_rst), + .test_mode (test_mode), + .rd_reset_n(viv_s25) + ); + assign viv_s38 = mp_y_fifo_write64; + assign viv_s32 = {mp_y_fifo_data_in, mp_y_fifo_h_end_in, mp_y_fifo_v_end_in}; + assign viv_s40 = viv_s41 && !viv_s62; + assign mp_y_sramfifo_err = viv_s38 && !viv_s39; + assign mp_y_fifo_full = !viv_s39; + vsisp_mi_fifo_ram #( + .FIFO_DATA_WIDTH ( 64+2 ), + .FIFO_DEPTH ( 80 ), + .SRAM_ADDRWIDTH ( 7 ), + .FIFO_SRAM_REGS ( 3 ), + .FIFO_DESCRIPTION ( "mi_sync_sram_y")) u_marvin_mi_mp_y_sramfifo( + .clk (clk ), + .resetn (viv_s24 ), + .fifo_synch_reset (viv_s24 ), + .sw_fifo_depth_ctrl (sw_mi_fifo_depth_ctrl ), + .fifo_write_e_lz (viv_s38 ), + .fifo_write_data (viv_s32 ), + .fifo_read_e_lz (viv_s40 ), + .fifo_read_data (viv_s35 ), + .fifo_validread_am (), + .fifo_validwrite_vz (viv_s39), + .fifo_validread_vz (viv_s41 ), + .fifo_sram_buf_full (mp_y_fifo_sram_buf_full ), + .fifo_sram_DIN (mp_y_fifo_sram_DIN ), + .fifo_sram_DOUT (mp_y_fifo_sram_DOUT ), + .fifo_sram_ADDR (mp_y_fifo_sram_ADDR ), + .fifo_sram_CEN (mp_y_fifo_sram_CEN ), + .fifo_sram_WEN (mp_y_fifo_sram_WEN )); + assign viv_s50 = viv_s40; + assign viv_s51 = viv_s35[65:2]; + assign viv_s52= viv_s35[1]; + assign viv_s53= viv_s35[0]; + vsisp_mi_fifo_core #(c_fifo_depth) u_marvin_mi_mp_y_fifo + ( + .wr_clk (clk), + .wr_reset_n (viv_s24), + .rd_clk (m_hclk), + .rd_reset_n (viv_s25), + .rotation (1'b0), + .wr_en (viv_s50), + .wdata (viv_s51), + .wr_h_end (viv_s52), + .wr_v_end (viv_s53), + .fifo_full (viv_s62), + .rd_en (viv_s0), + .rdata (viv_s1), + .rd_h_end (viv_s2), + .rd_v_end (viv_s3), + .fifo_empty (viv_s26), + .fifo_fill_level (mp_y_fifo_fill_level), + .fifo_flush (mp_y_fifo_flush) + ); + assign mp_cb_fifo_sram_buf_full = 1'b0; + assign mp_cb_fifo_sram_DOUT = 66'h0; + assign mp_cb_fifo_sram_ADDR = 6'h0; + assign mp_cb_fifo_sram_CEN = 1'b1; + assign mp_cb_fifo_sram_WEN = 1'b1; + vsisp_mi_fifo_core #(c_fifo_depth) u_marvin_mi_mp_cb_fifo + ( + .wr_clk (clk), + .wr_reset_n (viv_s24), + .rd_clk (m_hclk), + .rd_reset_n (viv_s25), + .rotation (1'b0), + .wr_en (mp_cb_fifo_write64), + .wdata (mp_cb_fifo_data_in), + .wr_h_end (mp_cb_fifo_h_end_in), + .wr_v_end (mp_cb_fifo_v_end_in), + .fifo_full (mp_cb_fifo_full), + .rd_en (viv_s4), + .rdata (viv_s5), + .rd_h_end (viv_s6), + .rd_v_end (viv_s7), + .fifo_empty (viv_s27), + .fifo_fill_level (mp_cb_fifo_fill_level), + .fifo_flush (mp_cb_fifo_flush) + ); + assign mp_cr_fifo_sram_buf_full = 1'b0; + assign mp_cr_fifo_sram_DOUT = 66'h0; + assign mp_cr_fifo_sram_ADDR = 6'b0; + assign mp_cr_fifo_sram_CEN = 1'b1; + assign mp_cr_fifo_sram_WEN = 1'b1; + vsisp_mi_fifo_core #(c_fifo_depth) u_marvin_mi_mp_cr_fifo + ( + .wr_clk (clk), + .wr_reset_n (viv_s24), + .rd_clk (m_hclk), + .rd_reset_n (viv_s25), + .rotation (1'b0), + .wr_en (mp_cr_fifo_write64), + .wdata (mp_cr_fifo_data_in), + .wr_h_end (mp_cr_fifo_h_end_in), + .wr_v_end (mp_cr_fifo_v_end_in), + .fifo_full (mp_cr_fifo_full), + .rd_en (viv_s8), + .rdata (viv_s9), + .rd_h_end (viv_s10), + .rd_v_end (viv_s11), + .fifo_empty (viv_s28), + .fifo_fill_level (mp_cr_fifo_fill_level), + .fifo_flush (mp_cr_fifo_flush) + ); + always @(mp_fifo_read64 or mp_fifo_select or viv_s5 or + viv_s6 or viv_s7 or + viv_s9 or viv_s10 or + viv_s11 or viv_s1 or + viv_s2 or viv_s3) begin + viv_s0 = 1'b0; + viv_s4 = 1'b0; + viv_s8 = 1'b0; + case (mp_fifo_select) + 2'd0: begin + viv_s0 = mp_fifo_read64; + mp_fifo_data_out = viv_s1; + mp_fifo_h_end_out = viv_s2; + mp_fifo_v_end_out = viv_s3; + end + 2'd1: begin + viv_s4 = mp_fifo_read64; + mp_fifo_data_out = viv_s5; + mp_fifo_h_end_out = viv_s6; + mp_fifo_v_end_out = viv_s7; + end + 2'd2: begin + viv_s8 = mp_fifo_read64; + mp_fifo_data_out = viv_s9; + mp_fifo_h_end_out = viv_s10; + mp_fifo_v_end_out = viv_s11; + end + default: begin + mp_fifo_data_out = 64'h0; + mp_fifo_h_end_out = 1'b0; + mp_fifo_v_end_out = 1'b0; + end + endcase + end + vsisp_mi_fifo_core #(c_fifo_depth) u_marvin_mi_sp_y_fifo + ( + .wr_clk (clk), + .wr_reset_n (viv_s24), + .rd_clk (m_hclk), + .rd_reset_n (viv_s25), + .rotation (sp_rot_in), + .wr_en (sp_y_fifo_write64), + .wdata (sp_y_fifo_data_in), + .wr_h_end (sp_y_fifo_h_end_in), + .wr_v_end (sp_y_fifo_v_end_in), + .fifo_full (sp_y_fifo_full), + .rd_en (viv_s12), + .rdata (viv_s13 ), + .rd_h_end (viv_s14), + .rd_v_end (viv_s15), + .fifo_empty (viv_s29), + .fifo_fill_level (sp_y_fifo_fill_level), + .fifo_flush (sp_y_fifo_flush) + ); + vsisp_mi_fifo_core #(c_fifo_depth) u_marvin_mi_sp_cb_fifo + ( + .wr_clk (clk), + .wr_reset_n (viv_s24), + .rd_clk (m_hclk), + .rd_reset_n (viv_s25), + .rotation (sp_rot_in), + .wr_en (sp_cb_fifo_write64), + .wdata (sp_cb_fifo_data_in), + .wr_h_end (sp_cb_fifo_h_end_in), + .wr_v_end (sp_cb_fifo_v_end_in), + .fifo_full (sp_cb_fifo_full), + .rd_en (viv_s16), + .rdata (viv_s17), + .rd_h_end (viv_s18), + .rd_v_end (viv_s19), + .fifo_empty (viv_s30), + .fifo_fill_level (sp_cb_fifo_fill_level), + .fifo_flush (sp_cb_fifo_flush) + ); + vsisp_mi_fifo_core #(c_fifo_depth) u_marvin_mi_sp_cr_fifo + ( + .wr_clk (clk), + .wr_reset_n (viv_s24), + .rd_clk (m_hclk), + .rd_reset_n (viv_s25), + .rotation (sp_rot_in), + .wr_en (sp_cr_fifo_write64), + .wdata (sp_cr_fifo_data_in), + .wr_h_end (sp_cr_fifo_h_end_in), + .wr_v_end (sp_cr_fifo_v_end_in), + .fifo_full (sp_cr_fifo_full), + .rd_en (viv_s20), + .rdata (viv_s21), + .rd_h_end (viv_s22), + .rd_v_end (viv_s23), + .fifo_empty (viv_s31), + .fifo_fill_level (sp_cr_fifo_fill_level), + .fifo_flush (sp_cr_fifo_flush) + ); + always @(sp_fifo_read64 or sp_fifo_select or viv_s17 or + viv_s18 or viv_s19 or + viv_s21 or viv_s22 or + viv_s23 or viv_s13 or + viv_s14 or viv_s15) begin + viv_s12 = 1'b0; + viv_s16 = 1'b0; + viv_s20 = 1'b0; + case (sp_fifo_select) + 2'd0: begin + viv_s12 = sp_fifo_read64; + sp_fifo_data_out = viv_s13; + sp_fifo_h_end_out = viv_s14; + sp_fifo_v_end_out = viv_s15; + end + 2'd1: begin + viv_s16 = sp_fifo_read64; + sp_fifo_data_out = viv_s17; + sp_fifo_h_end_out = viv_s18; + sp_fifo_v_end_out = viv_s19; + end + 2'd2: begin + viv_s20 = sp_fifo_read64; + sp_fifo_data_out = viv_s21; + sp_fifo_h_end_out = viv_s22; + sp_fifo_v_end_out = viv_s23; + end + default: begin + sp_fifo_data_out = 64'h0; + sp_fifo_h_end_out = 1'b0; + sp_fifo_v_end_out = 1'b0; + end + endcase + end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_marvin_mi_fifo_bp.v b/ispyocto/rtl/ispyocto/vsisp_marvin_mi_fifo_bp.v new file mode 100644 index 0000000..e77ec0e --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_marvin_mi_fifo_bp.v
@@ -0,0 +1,497 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_marvin_mi_fifo_bp + ( + clk, + reset_n, + soft_rst, + m_hclk, + reset_m_hclk_n, + soft_rst_m_hclk, + test_mode, + sp_rot_in, + sw_mi_fifo_depth_ctrl, + wr_resume, + plnr_wrt, + mp_y_fifo_data_in, + mp_y_fifo_h_end_in, + mp_y_fifo_v_end_in, + mp_y_fifo_write64, + mp_y_fifo_full, + mp_y_fifo_sram_buf_full, + mp_cb_fifo_data_in, + mp_cb_fifo_h_end_in, + mp_cb_fifo_v_end_in, + mp_cb_fifo_write64, + mp_cb_fifo_full, + mp_cb_fifo_sram_buf_full, + mp_cr_fifo_data_in, + mp_cr_fifo_h_end_in, + mp_cr_fifo_v_end_in, + mp_cr_fifo_write64, + mp_cr_fifo_full, + mp_cr_fifo_sram_buf_full, + sp_y_fifo_data_in, + sp_y_fifo_h_end_in, + sp_y_fifo_v_end_in, + sp_y_fifo_write64, + sp_y_fifo_full, + sp_cb_fifo_data_in, + sp_cb_fifo_h_end_in, + sp_cb_fifo_v_end_in, + sp_cb_fifo_write64, + sp_cb_fifo_full, + sp_cr_fifo_data_in, + sp_cr_fifo_h_end_in, + sp_cr_fifo_v_end_in, + sp_cr_fifo_write64, + sp_cr_fifo_full, + mp_fifo_read64, + mp_fifo_select, + mp_fifo_data_out, + mp_fifo_h_end_out, + mp_fifo_v_end_out, + sp_fifo_read64, + sp_fifo_select, + sp_fifo_data_out, + sp_fifo_h_end_out, + sp_fifo_v_end_out, + mp_y_fifo_fill_level, + mp_y_fifo_flush, + mp_cb_fifo_fill_level, + mp_cb_fifo_flush, + mp_cr_fifo_fill_level, + mp_cr_fifo_flush, + sp_y_fifo_fill_level, + sp_y_fifo_flush, + sp_cb_fifo_fill_level, + sp_cb_fifo_flush, + sp_cr_fifo_fill_level, + sp_cr_fifo_flush, + mp_y_fifo_sram_DIN, + mp_y_fifo_sram_DOUT, + mp_y_fifo_sram_ADDR, + mp_y_fifo_sram_CEN, + mp_y_fifo_sram_WEN, + mp_cb_fifo_sram_DIN, + mp_cb_fifo_sram_DOUT, + mp_cb_fifo_sram_ADDR, + mp_cb_fifo_sram_CEN, + mp_cb_fifo_sram_WEN, + mp_cr_fifo_sram_DIN, + mp_cr_fifo_sram_DOUT, + mp_cr_fifo_sram_ADDR, + mp_cr_fifo_sram_CEN, + mp_cr_fifo_sram_WEN + ); + parameter c_fifo_depth = 8; + parameter c_addr_width = (c_fifo_depth <= 1) ? 0 : + (c_fifo_depth <= 2) ? 1 : + (c_fifo_depth <= 4) ? 2 : + (c_fifo_depth <= 8) ? 3 : + (c_fifo_depth <= 16) ? 4 : + (c_fifo_depth <= 32) ? 5 : + (c_fifo_depth <= 64) ? 6 : + (c_fifo_depth <= 128) ? 7 : 8; + input clk; + input reset_n; + input soft_rst; + input m_hclk; + input reset_m_hclk_n; + input soft_rst_m_hclk; + input test_mode; + input sp_rot_in; + input [1:0] sw_mi_fifo_depth_ctrl; + input wr_resume; + input plnr_wrt; + input [63:0] mp_y_fifo_data_in; + input mp_y_fifo_h_end_in; + input mp_y_fifo_v_end_in; + input mp_y_fifo_write64; + output mp_y_fifo_full; + output mp_y_fifo_sram_buf_full; + input [63:0] mp_cb_fifo_data_in; + input mp_cb_fifo_h_end_in; + input mp_cb_fifo_v_end_in; + input mp_cb_fifo_write64; + output mp_cb_fifo_full; + output mp_cb_fifo_sram_buf_full; + input [63:0] mp_cr_fifo_data_in; + input mp_cr_fifo_h_end_in; + input mp_cr_fifo_v_end_in; + input mp_cr_fifo_write64; + output mp_cr_fifo_full; + output mp_cr_fifo_sram_buf_full; + input [63:0] sp_y_fifo_data_in; + input sp_y_fifo_h_end_in; + input sp_y_fifo_v_end_in; + input sp_y_fifo_write64; + output sp_y_fifo_full; + input [63:0] sp_cb_fifo_data_in; + input sp_cb_fifo_h_end_in; + input sp_cb_fifo_v_end_in; + input sp_cb_fifo_write64; + output sp_cb_fifo_full; + input [63:0] sp_cr_fifo_data_in; + input sp_cr_fifo_h_end_in; + input sp_cr_fifo_v_end_in; + input sp_cr_fifo_write64; + output sp_cr_fifo_full; + input mp_fifo_read64; + input [1:0] mp_fifo_select; + output [63:0] mp_fifo_data_out; + output mp_fifo_h_end_out; + output mp_fifo_v_end_out; + reg [63:0] mp_fifo_data_out; + reg mp_fifo_h_end_out; + reg mp_fifo_v_end_out; + input sp_fifo_read64; + input [1:0] sp_fifo_select; + output [63:0] sp_fifo_data_out; + output sp_fifo_h_end_out; + output sp_fifo_v_end_out; + reg [63:0] sp_fifo_data_out; + reg sp_fifo_h_end_out; + reg sp_fifo_v_end_out; + output [c_addr_width:0] mp_y_fifo_fill_level; + output mp_y_fifo_flush; + reg viv_s0; + wire [63:0] viv_s1; + wire viv_s2; + wire viv_s3; + output [c_addr_width:0] mp_cb_fifo_fill_level; + output mp_cb_fifo_flush; + reg viv_s4; + wire [63:0] viv_s5; + wire viv_s6; + wire viv_s7; + output [c_addr_width:0] mp_cr_fifo_fill_level; + output mp_cr_fifo_flush; + reg viv_s8; + wire [63:0] viv_s9; + wire viv_s10; + wire viv_s11; + output [c_addr_width:0] sp_y_fifo_fill_level; + output sp_y_fifo_flush; + reg viv_s12; + wire [63:0] viv_s13; + wire viv_s14; + wire viv_s15; + output [c_addr_width:0] sp_cb_fifo_fill_level; + output sp_cb_fifo_flush; + reg viv_s16; + wire [63:0] viv_s17; + wire viv_s18; + wire viv_s19; + output [c_addr_width:0] sp_cr_fifo_fill_level; + output sp_cr_fifo_flush; + reg viv_s20; + wire [63:0] viv_s21; + wire viv_s22; + wire viv_s23; + input [65:0] mp_y_fifo_sram_DIN; + output [65:0] mp_y_fifo_sram_DOUT; + output [ 8:0] mp_y_fifo_sram_ADDR; + output mp_y_fifo_sram_CEN; + output mp_y_fifo_sram_WEN; + input [65:0] mp_cb_fifo_sram_DIN; + output [65:0] mp_cb_fifo_sram_DOUT; + output [ 8:0] mp_cb_fifo_sram_ADDR; + output mp_cb_fifo_sram_CEN; + output mp_cb_fifo_sram_WEN; + input [65:0] mp_cr_fifo_sram_DIN; + output [65:0] mp_cr_fifo_sram_DOUT; + output [ 8:0] mp_cr_fifo_sram_ADDR; + output mp_cr_fifo_sram_CEN; + output mp_cr_fifo_sram_WEN; + wire viv_s24; + wire viv_s25; + wire viv_s26; + wire viv_s27; + wire viv_s28; + wire viv_s29; + wire viv_s30; + wire viv_s31; + wire [65:0] viv_s32; + wire [65:0] viv_s33; + wire [65:0] viv_s34; + wire [65:0] viv_s35; + wire [65:0] viv_s36; + wire [65:0] viv_s37; + wire viv_s38, viv_s39; + wire viv_s40, viv_s41; + wire viv_s42, viv_s43; + wire viv_s44, viv_s45; + wire viv_s46, viv_s47; + wire viv_s48, viv_s49; + wire viv_s50; + wire [63:0] viv_s51; + wire viv_s52; + wire viv_s53; + wire viv_s54; + wire [63:0] viv_s55; + wire viv_s56; + wire viv_s57; + wire viv_s58; + wire [63:0] viv_s59; + wire viv_s60; + wire viv_s61; + wire viv_s62, viv_s63, viv_s64; + vsisp_sync_fifo_reset_gen_wr u_sync_fifo_dma_rst_wr + ( + .wr_clk (clk), + .reset_n (reset_n ), + .soft_reset(soft_rst), + .test_mode (test_mode), + .wr_reset_n(viv_s24) + ); + vsisp_sync_fifo_reset_gen_rd u_sync_fifo_dma_rst_rd + ( + .rd_clk (m_hclk), + .reset_n (reset_m_hclk_n), + .soft_reset(soft_rst), + .test_mode (test_mode), + .rd_reset_n(viv_s25) + ); + assign viv_s38 = mp_y_fifo_write64; + assign viv_s32 = {mp_y_fifo_data_in, mp_y_fifo_h_end_in, mp_y_fifo_v_end_in}; + assign viv_s40 = viv_s41 && !viv_s62; + assign mp_y_sramfifo_err = viv_s38 && !viv_s39; + assign mp_y_fifo_full = !viv_s39; + vsisp_mi_fifo_ram #( + .FIFO_DATA_WIDTH ( 64+2 ), + .FIFO_DEPTH ( 294 ), + .SRAM_ADDRWIDTH ( 9 ), + .FIFO_SRAM_REGS ( 3 ), + .FIFO_DESCRIPTION ( "mi_sync_sram_y")) u_marvin_mi_mp_y_sramfifo( + .clk (clk ), + .resetn (viv_s24 ), + .fifo_synch_reset (viv_s24 ), + .sw_fifo_depth_ctrl (sw_mi_fifo_depth_ctrl ), + .fifo_write_e_lz (viv_s38 ), + .fifo_write_data (viv_s32 ), + .fifo_read_e_lz (viv_s40 ), + .fifo_read_data (viv_s35 ), + .fifo_validread_am (), + .fifo_validwrite_vz (viv_s39), + .fifo_validread_vz (viv_s41 ), + .fifo_sram_buf_full (mp_y_fifo_sram_buf_full ), + .fifo_sram_DIN (mp_y_fifo_sram_DIN ), + .fifo_sram_DOUT (mp_y_fifo_sram_DOUT ), + .fifo_sram_ADDR (mp_y_fifo_sram_ADDR ), + .fifo_sram_CEN (mp_y_fifo_sram_CEN ), + .fifo_sram_WEN (mp_y_fifo_sram_WEN )); + assign viv_s50 = viv_s40; + assign viv_s51 = viv_s35[65:2]; + assign viv_s52= viv_s35[1]; + assign viv_s53= viv_s35[0]; + vsisp_mi_fifo_core #(c_fifo_depth) u_marvin_mi_mp_y_fifo + ( + .wr_clk (clk), + .wr_reset_n (viv_s24), + .rd_clk (m_hclk), + .rd_reset_n (viv_s25), + .rotation (1'b0), + .wr_en (viv_s50), + .wdata (viv_s51), + .wr_h_end (viv_s52), + .wr_v_end (viv_s53), + .fifo_full (mp_y_fifo2_full_inst), + .rd_en (viv_s0), + .rdata (viv_s1), + .rd_h_end (viv_s2), + .rd_v_end (viv_s3), + .fifo_empty (viv_s26), + .fifo_fill_level (mp_y_fifo_fill_level), + .fifo_flush (mp_y_fifo_flush) + ); + assign viv_s42 = mp_cb_fifo_write64; + assign viv_s33 = {mp_cb_fifo_data_in, mp_cb_fifo_h_end_in, mp_cb_fifo_v_end_in}; + assign viv_s44 = viv_s45 && !viv_s63; + assign mp_cb_sramfifo_err = viv_s42 && !viv_s43; + assign mp_cb_fifo_full = !viv_s43; + vsisp_mi_fifo_ram #( + .FIFO_DATA_WIDTH ( 64+2 ), + .FIFO_DEPTH ( 294 ), + .SRAM_ADDRWIDTH ( 9 ), + .FIFO_SRAM_REGS ( 3 ), + .FIFO_DESCRIPTION ( "mi_sync_sram_y")) u_marvin_mi_mp_cb_sramfifo( + .clk (clk ), + .resetn (viv_s24 ), + .fifo_synch_reset (viv_s24 ), + .sw_fifo_depth_ctrl (sw_mi_fifo_depth_ctrl ), + .fifo_write_e_lz (viv_s42 ), + .fifo_write_data (viv_s33 ), + .fifo_read_e_lz (viv_s44 ), + .fifo_read_data (viv_s36 ), + .fifo_validread_am (), + .fifo_validwrite_vz (viv_s43), + .fifo_validread_vz (viv_s45), + .fifo_sram_buf_full (mp_cb_fifo_sram_buf_full ), + .fifo_sram_DIN (mp_cb_fifo_sram_DIN ), + .fifo_sram_DOUT (mp_cb_fifo_sram_DOUT ), + .fifo_sram_ADDR (mp_cb_fifo_sram_ADDR ), + .fifo_sram_CEN (mp_cb_fifo_sram_CEN ), + .fifo_sram_WEN (mp_cb_fifo_sram_WEN )); + assign viv_s54 = viv_s44; + assign viv_s55 = viv_s36[65:2]; + assign viv_s56= viv_s36[1]; + assign viv_s57= viv_s36[0]; + vsisp_mi_fifo_core #(c_fifo_depth) u_marvin_mi_mp_cb_fifo + ( + .wr_clk (clk), + .wr_reset_n (viv_s24), + .rd_clk (m_hclk), + .rd_reset_n (viv_s25), + .rotation (1'b0), + .wr_en (viv_s54), + .wdata (viv_s55), + .wr_h_end (viv_s56), + .wr_v_end (viv_s57), + .fifo_full (mp_cb_fifo2_full_inst), + .rd_en (viv_s4), + .rdata (viv_s5), + .rd_h_end (viv_s6), + .rd_v_end (viv_s7), + .fifo_empty (viv_s27), + .fifo_fill_level (mp_cb_fifo_fill_level), + .fifo_flush (mp_cb_fifo_flush) + ); + assign viv_s46 = mp_cr_fifo_write64; + assign viv_s34 = {mp_cr_fifo_data_in, mp_cr_fifo_h_end_in, mp_cr_fifo_v_end_in}; + assign viv_s48 = viv_s49 && !viv_s64; + assign mp_cr_sramfifo_err = viv_s46 && !viv_s47; + assign mp_cr_fifo_full = !viv_s47; + vsisp_mi_fifo_ram #( + .FIFO_DATA_WIDTH ( 64+2 ), + .FIFO_DEPTH ( 294 ), + .SRAM_ADDRWIDTH ( 9 ), + .FIFO_SRAM_REGS ( 3 ), + .FIFO_DESCRIPTION ( "mi_sync_sram_y")) u_marvin_mi_mp_cr_sramfifo( + .clk (clk ), + .resetn (viv_s24 ), + .fifo_synch_reset (viv_s24 ), + .sw_fifo_depth_ctrl (sw_mi_fifo_depth_ctrl ), + .fifo_write_e_lz (viv_s46 ), + .fifo_write_data (viv_s34 ), + .fifo_read_e_lz (viv_s48 ), + .fifo_read_data (viv_s37 ), + .fifo_validread_am (), + .fifo_validwrite_vz (viv_s47), + .fifo_validread_vz (viv_s49), + .fifo_sram_buf_full (mp_cr_fifo_sram_buf_full ), + .fifo_sram_DIN (mp_cr_fifo_sram_DIN ), + .fifo_sram_DOUT (mp_cr_fifo_sram_DOUT ), + .fifo_sram_ADDR (mp_cr_fifo_sram_ADDR ), + .fifo_sram_CEN (mp_cr_fifo_sram_CEN ), + .fifo_sram_WEN (mp_cr_fifo_sram_WEN )); + assign viv_s58 = viv_s48; + assign viv_s59 = viv_s37[65:2]; + assign viv_s60= viv_s37[1]; + assign viv_s61= viv_s37[0]; + vsisp_mi_fifo_core #(c_fifo_depth) u_marvin_mi_mp_cr_fifo + ( + .wr_clk (clk), + .wr_reset_n (viv_s24), + .rd_clk (m_hclk), + .rd_reset_n (viv_s25), + .rotation (1'b0), + .wr_en (viv_s58), + .wdata (viv_s59), + .wr_h_end (viv_s60), + .wr_v_end (viv_s61), + .fifo_full (viv_s64), + .rd_en (viv_s8), + .rdata (viv_s9), + .rd_h_end (viv_s10), + .rd_v_end (viv_s11), + .fifo_empty (viv_s28), + .fifo_fill_level (mp_cr_fifo_fill_level), + .fifo_flush (mp_cr_fifo_flush) + ); + always @(mp_fifo_read64 or mp_fifo_select or viv_s5 or + viv_s6 or viv_s7 or + viv_s9 or viv_s10 or + viv_s11 or viv_s1 or + viv_s2 or viv_s3) begin + viv_s0 = 1'b0; + viv_s4 = 1'b0; + viv_s8 = 1'b0; + case (mp_fifo_select) + 2'd0: begin + viv_s0 = mp_fifo_read64; + mp_fifo_data_out = viv_s1; + mp_fifo_h_end_out = viv_s2; + mp_fifo_v_end_out = viv_s3; + end + 2'd1: begin + viv_s4 = mp_fifo_read64; + mp_fifo_data_out = viv_s5; + mp_fifo_h_end_out = viv_s6; + mp_fifo_v_end_out = viv_s7; + end + 2'd2: begin + viv_s8 = mp_fifo_read64; + mp_fifo_data_out = viv_s9; + mp_fifo_h_end_out = viv_s10; + mp_fifo_v_end_out = viv_s11; + end + default: begin + mp_fifo_data_out = 64'h0; + mp_fifo_h_end_out = 1'b0; + mp_fifo_v_end_out = 1'b0; + end + endcase + end + assign sp_y_fifo_full = 1'b0; + assign sp_cb_fifo_full = 1'b0; + assign sp_cr_fifo_full = 1'b0; + always @(posedge clk or negedge reset_n) begin + if (~reset_n) begin + sp_fifo_data_out <= 64'b0; + sp_fifo_h_end_out <= 1'b0; + sp_fifo_v_end_out <= 1'b0; + end + else begin + sp_fifo_data_out <= 64'b0; + sp_fifo_h_end_out <= 1'b0; + sp_fifo_v_end_out <= 1'b0; + end + end + assign sp_y_fifo_fill_level = {(c_addr_width+1){1'b0}}; + assign sp_y_fifo_flush = 1'b0; + assign sp_cb_fifo_fill_level = {(c_addr_width+1){1'b0}}; + assign sp_cb_fifo_flush = 1'b0; + assign sp_cr_fifo_fill_level = {(c_addr_width+1){1'b0}}; + assign sp_cr_fifo_flush = 1'b0; +wire viv_s65, viv_s66; + wire viv_s67 = viv_s50 & viv_s52; + assign viv_s62 = mp_y_fifo2_full_inst | viv_s65; +wire viv_s68 = viv_s54 & viv_s56; +assign viv_s63 = mp_cb_fifo2_full_inst | viv_s66; +wire viv_s69 = plnr_wrt & (viv_s67 | (viv_s65 & ~wr_resume)); +vsisp_dreg_en_1d #(1,1'b0) mp_y_wr_stall_Reg (.clk(clk), .reset_n(reset_n), .soft_reset(soft_rst), .out(viv_s65), .in(viv_s69), .en(1'b1)); +wire viv_s70 = plnr_wrt & (viv_s68 | (viv_s66 & ~wr_resume)); +vsisp_dreg_en_1d #(1,1'b0) mp_cb_wr_stall_Reg (.clk(clk), .reset_n(reset_n), .soft_reset(soft_rst), .out(viv_s66), .in(viv_s70), .en(1'b1)); +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_marvin_mi_handshake.v b/ispyocto/rtl/ispyocto/vsisp_marvin_mi_handshake.v new file mode 100644 index 0000000..86bb6f2 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_marvin_mi_handshake.v
@@ -0,0 +1,743 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_marvin_mi_handshake( +isp_0_clock , +isp_0_rst_n , +soft_upd , +mp_line_sens , +data_format , +starage_format , +slice_size , +buf_size , +mp_fifo_h_end , +mp_fifo_v_end , +mp_fifo_read64 , +stat_skip_active, +mp_fifo_select , +isp_0_ack , +bresp_in , +isp_0_ready , +isp_0_attr , +mp_y_base_ad , +mp_cb_base_ad , +mp_cr_base_ad , +address , +mp_addr_cur_y , +mp_addr_cur_cb , +mp_addr_cur_cr , +ack_count , +mp_y_llength , +mp_slice_offset_y, +mp_slice_offset_c, +mp_interrupt, +handshake_en , +handshake_mode_0, +slice_cnt_int , +sw_addr_mp_y , +sw_addr_mp_cb , +sw_addr_mp_cr , +sw_interrupt_out); +`include "vsisp_marvin_mi.vh" +input isp_0_clock ; +input isp_0_rst_n ; +input soft_upd ; +input mp_line_sens ; +input [1:0] data_format ; +input [1:0] starage_format ; +input [7:0] slice_size ; +input [7:0] buf_size ; +input mp_fifo_h_end ; +input mp_fifo_v_end ; +input mp_fifo_read64 ; +input stat_skip_active; +input [1:0] mp_fifo_select ; +input isp_0_ack ; +input bresp_in ; +output isp_0_ready ; +output [1:0] isp_0_attr ; +input [c_mi_data_addr:0] mp_y_base_ad ; +input [c_mi_data_addr:0] mp_cb_base_ad ; +input [c_mi_data_addr:0] mp_cr_base_ad ; +output [c_mi_data_addr:0] address ; +output [c_mi_data_addr:0] mp_addr_cur_y ; +output [c_mi_data_addr:0] mp_addr_cur_cb ; +output [c_mi_data_addr:0] mp_addr_cur_cr ; +input [7:0] ack_count ; +input [14:0] mp_y_llength ; +input [c_mi_data_addr:0] mp_slice_offset_y; +input [c_mi_data_addr:0] mp_slice_offset_c; +output mp_interrupt; +input handshake_en ; +input handshake_mode_0; +input [7:0] slice_cnt_int ; +output [c_mi_data_addr:0] sw_addr_mp_y ; +output [c_mi_data_addr:0] sw_addr_mp_cb ; +output [c_mi_data_addr:0] sw_addr_mp_cr ; +output sw_interrupt_out; +reg [1:0] isp_0_attr ; +reg [c_mi_data_addr:0] address ; +reg [c_mi_data_addr:0] mp_addr_cur_y ; +reg [c_mi_data_addr:0] mp_addr_cur_cb ; +reg [c_mi_data_addr:0] mp_addr_cur_cr ; +reg [c_mi_data_addr:0] sw_addr_mp_y ; +reg [c_mi_data_addr:0] sw_addr_mp_cb ; +reg [c_mi_data_addr:0] sw_addr_mp_cr ; +reg viv_s0; +reg viv_s1; +reg viv_s2; +reg viv_s3; +reg viv_s4; +reg viv_s5; +reg viv_s6; +reg [7:0] viv_s7; +reg [7:0] viv_s8; +reg [7:0] viv_s9; +reg [7:0] viv_s10; +reg [1:0] viv_s11; +reg viv_s12; +reg viv_s13; +reg viv_s14; +reg [7:0] viv_s15; +reg [7:0] viv_s16; +reg [7:0] viv_s17; +reg [7:0] viv_s18; +reg [7:0] viv_s19; +reg [7:0] viv_s20; +reg viv_s21; +reg viv_s22; +reg viv_s23; +reg viv_s24; +reg viv_s25; +reg [14:0] viv_s26; +reg [14:0] viv_s27; +reg [c_mi_data_addr:0] viv_s28; +reg [c_mi_data_addr:0] viv_s29; +reg [c_mi_data_addr:0] viv_s30; +reg [c_mi_data_addr:0] viv_s31; +reg [c_mi_data_addr:0] viv_s32; +reg [c_mi_data_addr:0] viv_s33; +wire [c_mi_data_addr:0] viv_s34; +wire [c_mi_data_addr:0] viv_s35; +wire [c_mi_data_addr:0] viv_s36; +wire [c_mi_data_addr:0] viv_s37; +wire [c_mi_data_addr:0] viv_s38; +wire [c_mi_data_addr:0] viv_s39; +reg viv_s40; +reg [7:0] viv_s41; +reg viv_s42; +wire viv_s43; +wire viv_s44; +wire viv_s45; +wire [c_mi_data_addr:0] viv_s46; +wire [c_mi_data_addr:0] viv_s47; +wire [c_mi_data_addr:0] viv_s48; +wire viv_s49; +wire viv_s50; +wire viv_s51; +wire [c_mi_data_addr:0] viv_s52; +wire viv_s53; +always @(*) +begin + viv_s1 = 1'b0; + viv_s2 = 1'b0; + viv_s3 = 1'b0; + viv_s4 = 1'b0; + viv_s5 = 1'b0; + viv_s6 = 1'b0; + if(mp_fifo_read64) + begin + case(mp_fifo_select) + 2'b00: begin + viv_s1 = mp_fifo_h_end; + viv_s4 = mp_fifo_v_end && mp_fifo_h_end; + end + 2'b01: begin + viv_s2 = mp_fifo_h_end; + viv_s5 = mp_fifo_v_end && mp_fifo_h_end; + end + 2'b10: begin + viv_s3 = mp_fifo_h_end; + viv_s6 = mp_fifo_v_end && mp_fifo_h_end; + end + endcase + end +end +always @(*) +begin + viv_s7[7:0] = 8'h0; + viv_s8[7:0] = 8'h0; + viv_s9[7:0] = 8'h0; + if(data_format[1:0] == 2'b00) + viv_s7[7:0] = slice_size[7:0]; + else + if((data_format[1:0] == 2'b01) || (data_format[1:0] == 2'b10)) + begin + viv_s7[7:0] = slice_size[7:0]; + viv_s8[7:0] = slice_size[7:0]; + viv_s9[7:0] = slice_size[7:0]; + end + else + begin + if(data_format[1:0] == 2'b11) + begin + viv_s7[7:0] = slice_size[7:0]; + viv_s8[7:0] = {1'b0,slice_size[7:1]}; + viv_s9[7:0] = {1'b0,slice_size[7:1]}; + end + end +end +always @(posedge isp_0_clock or negedge isp_0_rst_n) +begin + if (~isp_0_rst_n) + begin + viv_s13 <= 1'b0; + viv_s14 <= 1'b0; + end + else + begin + viv_s13 <= isp_0_ack; + viv_s14 <= viv_s13; + end +end +always @(posedge isp_0_clock or negedge isp_0_rst_n) +begin + if (~isp_0_rst_n) + viv_s15[7:0] <= 8'h0; + else + begin + if(viv_s43 || viv_s4 || soft_upd) + viv_s15[7:0] <= 8'h0; + else + begin + if(~stat_skip_active) + begin + if(viv_s1) + viv_s15[7:0] <= viv_s15[7:0] + 1; + end + end + end +end +assign viv_s43 =((viv_s15[7:0] == viv_s7[7:0]) && viv_s1) || viv_s4; +always @(posedge isp_0_clock or negedge isp_0_rst_n) +begin + if (~isp_0_rst_n) + viv_s21 <= 1'b0; + else + begin + if(soft_upd || viv_s14) + viv_s21 <= 1'b0; + else + begin + if(viv_s43) + viv_s21 <= 1'b1; + end + end +end +always @(posedge isp_0_clock or negedge isp_0_rst_n) +begin + if (~isp_0_rst_n) + viv_s16[7:0] <= 8'h0; + else + begin + if(viv_s44 || viv_s5 || soft_upd) + viv_s16[7:0] <= 8'h0; + else + begin + if(~stat_skip_active) + begin + if(viv_s2) + viv_s16[7:0] <= viv_s16[7:0] + 1; + end + end + end +end +assign viv_s44 =((viv_s16[7:0] == viv_s8[7:0]) && viv_s2) || viv_s5; +always @(posedge isp_0_clock or negedge isp_0_rst_n) +begin + if (~isp_0_rst_n) + viv_s23 <= 1'b0; + else + begin + if(soft_upd || viv_s14) + viv_s23 <= 1'b0; + else + begin + if(viv_s44) + viv_s23 <= 1'b1; + end + end +end +always @(posedge isp_0_clock or negedge isp_0_rst_n) +begin + if (~isp_0_rst_n) + viv_s17[7:0] <= 8'h0; + else + begin + if(viv_s45 || viv_s6 || soft_upd) + viv_s17[7:0] <= 8'h0; + else + begin + if(~stat_skip_active) + begin + if(viv_s3) + viv_s17[7:0] <= viv_s17[7:0] + 1; + end + end + end +end +assign viv_s45 =((viv_s17[7:0] == viv_s9[7:0]) && viv_s3) || viv_s6; +always @(posedge isp_0_clock or negedge isp_0_rst_n) +begin + if (~isp_0_rst_n) + viv_s22 <= 1'b0; + else + begin + if(soft_upd || viv_s14) + viv_s22 <= 1'b0; + else + begin + if(viv_s45) + viv_s22 <= 1'b1; + end + end +end +always @(*) +begin + viv_s12 = 1'b0; + case(starage_format) + 2'b00: viv_s12 = viv_s22; + 2'b01: viv_s12 = viv_s23; + 2'b10: viv_s12 = viv_s21; + endcase +end +assign isp_0_ready = viv_s0; +always @(posedge isp_0_clock or negedge isp_0_rst_n) +begin + if (~isp_0_rst_n) + viv_s0 <= 1'b0; + else + begin + if(soft_upd || viv_s14 || mp_interrupt) + viv_s0 <= 1'b0; + else + begin + if((viv_s12) && (bresp_in || stat_skip_active)) + viv_s0 <= 1'b1; + end + end +end +always @(*) +begin + viv_s24 = 1'b0; + case(starage_format[1:0]) + 2'b00: viv_s24 = viv_s6; + 2'b01: viv_s24 = viv_s5; + 2'b10: viv_s24 = viv_s4; + endcase +end +always @(posedge isp_0_clock or negedge isp_0_rst_n) +begin + if (~isp_0_rst_n) + viv_s25 <= 1'b0; + else + begin + if((viv_s14 && viv_s0) || soft_upd || mp_interrupt) + viv_s25 <= 1'b0; + else + begin + if(viv_s24) + viv_s25 <= 1'b1; + end + end +end +always @(posedge isp_0_clock or negedge isp_0_rst_n) +begin + if (~isp_0_rst_n) + isp_0_attr[1:0] <= 2'b00; + else + begin + if(soft_upd) + isp_0_attr[1:0] <= 2'b01; + else + begin + if(viv_s25) + begin + if((isp_0_attr[1:0] == 2'b01) || (isp_0_attr[1:0] == 2'b11)) + isp_0_attr[1:0] <= 2'b11; + else + isp_0_attr[1:0] <= 2'b10; + end + else + begin + if(isp_0_attr[1:0] == 2'b00) + isp_0_attr[1:0] <= 2'b00; + else + begin + if(viv_s14 && viv_s0) + isp_0_attr[1:0] <= 2'b00; + else + isp_0_attr[1:0] <= 2'b01; + end + end + end + end +end +always @(posedge isp_0_clock or negedge isp_0_rst_n) +begin + if (~isp_0_rst_n) + viv_s10[7:0] <= 8'h0; + else + begin + if(soft_upd || viv_s14 || mp_interrupt) + viv_s10[7:0] <= 8'h0; + else + begin + if(isp_0_ready) + viv_s10[7:0] <= viv_s10[7:0] + 1; + end + end +end +assign mp_interrupt = (viv_s10[7:0] == ack_count[7:0] - 1); +always @(posedge isp_0_clock or negedge isp_0_rst_n) +begin + if (~isp_0_rst_n) + viv_s18[7:0] <= 8'h0; + else + begin + if(viv_s49 || viv_s4 || soft_upd) + viv_s18[7:0] <= 8'h0; + else + begin + if(~stat_skip_active) + begin + if ((mp_fifo_select[1:0] == 2'b00) & viv_s43) + viv_s18[7:0] <= viv_s18[7:0] + 1; + end + end + end +end +assign viv_s49 = (viv_s18[7:0] == buf_size[7:0]) && ((mp_fifo_select[1:0] == 2'b00) & viv_s43); +always @(posedge isp_0_clock or negedge isp_0_rst_n) +begin + if (~isp_0_rst_n) + viv_s19[7:0] <= 8'h0; + else + begin + if(viv_s50 || viv_s5 || soft_upd) + viv_s19[7:0] <= 8'h0; + else + begin + if(~stat_skip_active) + begin + if ((mp_fifo_select[1:0] == 2'b01) & viv_s44) + viv_s19[7:0] <= viv_s19[7:0] + 1; + end + end + end +end +assign viv_s50 = (viv_s19[7:0] == buf_size[7:0]) && ((mp_fifo_select[1:0] == 2'b01) & viv_s44); +always @(posedge isp_0_clock or negedge isp_0_rst_n) +begin + if (~isp_0_rst_n) + viv_s20[7:0] <= 8'h0; + else + begin + if(viv_s51 || viv_s6 || soft_upd) + viv_s20[7:0] <= 8'h0; + else + begin + if(~stat_skip_active) + begin + if ((mp_fifo_select[1:0] == 2'b10) & viv_s45) + viv_s20[7:0] <= viv_s20[7:0] + 1; + end + end + end +end +assign viv_s51 = (viv_s20[7:0] == buf_size[7:0]) && ((mp_fifo_select[1:0] == 2'b10) & viv_s45); +always @(posedge isp_0_clock or negedge isp_0_rst_n) +begin + if (~isp_0_rst_n) + viv_s26[14:0] <= 15'h0; + else + begin + if (starage_format[1:0] == 2'b10) + viv_s26[14:0] <= {mp_y_llength[13:0],1'b0}; + else + viv_s26[14:0] <= mp_y_llength[14:0]; + end +end +always @(posedge isp_0_clock or negedge isp_0_rst_n) +begin + if (~isp_0_rst_n) + viv_s27[14:0] <= 15'h0; + else + begin + case(data_format[1:0]) + 2'b01: begin + if(starage_format == 2'b01) + viv_s27[14:0] <= {mp_y_llength[13:0], 1'b0}; + else + begin + if(starage_format == 2'b00) + viv_s27[14:0] <= mp_y_llength[14:0]; + end + end + 2'b10: begin + if(starage_format == 2'b01) + viv_s27[14:0] <= mp_y_llength[14:0]; + else + begin + if(starage_format == 2'b00) + viv_s27[14:0] <= {1'b0, mp_y_llength[14:1]}; + end + end + 2'b11: begin + if(starage_format == 2'b01) + viv_s27[14:0] <= mp_y_llength[14:0]; + else + begin + if(starage_format == 2'b00) + viv_s27[14:0] <= {1'b0, mp_y_llength[14:1]}; + end + end + default:viv_s27[14:0] <= 15'h0; + endcase + end +end +assign viv_s37[c_mi_data_addr:0] = viv_s28[c_mi_data_addr:0] + mp_slice_offset_y[c_mi_data_addr:0]; +assign viv_s34[c_mi_data_addr:0] = viv_s31[c_mi_data_addr:0] + {17'h0,viv_s26[14:3]}; +always @(posedge isp_0_clock or negedge isp_0_rst_n) +begin + if (~isp_0_rst_n) + begin + mp_addr_cur_y[c_mi_data_addr:0] <= {c_mi_data_addr+1{1'b0}}; + viv_s28[c_mi_data_addr:0] <= {c_mi_data_addr+1{1'b0}}; + viv_s31[c_mi_data_addr:0] <= {c_mi_data_addr+1{1'b0}}; + end + else + begin + if(viv_s49 || viv_s4 || soft_upd) + begin + mp_addr_cur_y[c_mi_data_addr:0] <= {c_mi_data_addr+1{1'b0}}; + viv_s28[c_mi_data_addr:0] <= {c_mi_data_addr+1{1'b0}}; + viv_s31[c_mi_data_addr:0] <= {c_mi_data_addr+1{1'b0}}; + end + else + begin + if(~stat_skip_active) + begin + if ((mp_fifo_select[1:0] == 2'b00) & mp_fifo_read64) + begin + if(viv_s43) + begin + viv_s28[c_mi_data_addr:0] <= viv_s37[c_mi_data_addr:0]; + mp_addr_cur_y[c_mi_data_addr:0] <= viv_s37[c_mi_data_addr:0]; + viv_s31[c_mi_data_addr:0] <= viv_s37[c_mi_data_addr:0]; + end + else + begin + if (viv_s1) + begin + viv_s31[c_mi_data_addr:0] <= viv_s34[c_mi_data_addr:0]; + if(mp_line_sens) + mp_addr_cur_y[c_mi_data_addr:0] <= viv_s34[c_mi_data_addr:0]; + else + mp_addr_cur_y[c_mi_data_addr:0] <= mp_addr_cur_y[c_mi_data_addr:0] + 1; + end + else + begin + mp_addr_cur_y[c_mi_data_addr:0] <= mp_addr_cur_y[c_mi_data_addr:0] + 1; + end + end + end + end + end + end +end +assign viv_s38[c_mi_data_addr:0] = viv_s29[c_mi_data_addr:0] + mp_slice_offset_c[c_mi_data_addr:0]; +assign viv_s35[c_mi_data_addr:0] = viv_s32[c_mi_data_addr:0] + {17'h0,viv_s27[14:3]}; +always @(posedge isp_0_clock or negedge isp_0_rst_n) +begin + if (~isp_0_rst_n) + begin + mp_addr_cur_cb[c_mi_data_addr:0] <= {c_mi_data_addr+1{1'b0}}; + viv_s29[c_mi_data_addr:0] <= {c_mi_data_addr+1{1'b0}}; + viv_s32[c_mi_data_addr:0] <= {c_mi_data_addr+1{1'b0}}; + end + else + begin + if(viv_s50 || viv_s5 || soft_upd) + begin + mp_addr_cur_cb[c_mi_data_addr:0] <= {c_mi_data_addr+1{1'b0}}; + viv_s29[c_mi_data_addr:0] <= {c_mi_data_addr+1{1'b0}}; + viv_s32[c_mi_data_addr:0] <= {c_mi_data_addr+1{1'b0}}; + end + else + begin + if(~stat_skip_active) + begin + if ((mp_fifo_select[1:0] == 2'b01) & mp_fifo_read64) + begin + if(viv_s44) + begin + viv_s29[c_mi_data_addr:0] <= viv_s38[c_mi_data_addr:0]; + mp_addr_cur_cb[c_mi_data_addr:0] <= viv_s38[c_mi_data_addr:0]; + viv_s32[c_mi_data_addr:0] <= viv_s38[c_mi_data_addr:0]; + end + else + begin + if (viv_s2) + begin + viv_s32[c_mi_data_addr:0] <= viv_s35[c_mi_data_addr:0]; + if(mp_line_sens) + mp_addr_cur_cb[c_mi_data_addr:0] <= viv_s35[c_mi_data_addr:0]; + else + mp_addr_cur_cb[c_mi_data_addr:0] <= mp_addr_cur_cb[c_mi_data_addr:0] + 1; + end + else + begin + mp_addr_cur_cb[c_mi_data_addr:0] <= mp_addr_cur_cb[c_mi_data_addr:0] + 1; + end + end + end + end + end + end +end +assign viv_s39[c_mi_data_addr:0] = viv_s30[c_mi_data_addr:0] + mp_slice_offset_c[c_mi_data_addr:0]; +assign viv_s36[c_mi_data_addr:0] = viv_s33[c_mi_data_addr:0] + {17'h0,viv_s27[14:3]}; +always @(posedge isp_0_clock or negedge isp_0_rst_n) +begin + if (~isp_0_rst_n) + begin + mp_addr_cur_cr[c_mi_data_addr:0] <= {c_mi_data_addr+1{1'b0}}; + viv_s30[c_mi_data_addr:0] <= {c_mi_data_addr+1{1'b0}}; + viv_s33[c_mi_data_addr:0] <= {c_mi_data_addr+1{1'b0}}; + end + else + begin + if(viv_s51 || viv_s6 || soft_upd) + begin + mp_addr_cur_cr[c_mi_data_addr:0] <= {c_mi_data_addr+1{1'b0}}; + viv_s30[c_mi_data_addr:0] <= {c_mi_data_addr+1{1'b0}}; + viv_s33[c_mi_data_addr:0] <= {c_mi_data_addr+1{1'b0}}; + end + else + begin + if(~stat_skip_active) + begin + if ((mp_fifo_select[1:0] == 2'b10) & mp_fifo_read64) + begin + if(viv_s45) + begin + viv_s30[c_mi_data_addr:0] <= viv_s39[c_mi_data_addr:0]; + mp_addr_cur_cr[c_mi_data_addr:0] <= viv_s39[c_mi_data_addr:0]; + viv_s33[c_mi_data_addr:0] <= viv_s39[c_mi_data_addr:0]; + end + else + begin + if (viv_s3) + begin + viv_s33[c_mi_data_addr:0] <= viv_s36[c_mi_data_addr:0]; + if(mp_line_sens) + mp_addr_cur_cr[c_mi_data_addr:0] <= viv_s36[c_mi_data_addr:0]; + else + mp_addr_cur_cr[c_mi_data_addr:0] <= mp_addr_cur_cr[c_mi_data_addr:0] + 1; + end + else + begin + mp_addr_cur_cr[c_mi_data_addr:0] <= mp_addr_cur_cr[c_mi_data_addr:0] + 1; + end + end + end + end + end + end +end +assign viv_s46[c_mi_data_addr:0] = mp_y_base_ad[c_mi_data_addr:0] + mp_addr_cur_y[c_mi_data_addr:0]; +assign viv_s47[c_mi_data_addr:0] = mp_cb_base_ad[c_mi_data_addr:0] + mp_addr_cur_cb[c_mi_data_addr:0]; +assign viv_s48[c_mi_data_addr:0] = mp_cr_base_ad[c_mi_data_addr:0] + mp_addr_cur_cr[c_mi_data_addr:0]; +assign viv_s52[c_mi_data_addr:0] = ((mp_fifo_select[1:0] == 2'd0) ? viv_s46[c_mi_data_addr:0] : {c_mi_data_addr+1{1'b0}}) | + ((mp_fifo_select[1:0] == 2'd1) ? viv_s47[c_mi_data_addr:0] : {c_mi_data_addr+1{1'b0}}) | + ((mp_fifo_select[1:0] == 2'd2) ? viv_s48[c_mi_data_addr:0] : {c_mi_data_addr+1{1'b0}}); +always @(posedge isp_0_clock or negedge isp_0_rst_n) +begin + if (~isp_0_rst_n) + address[c_mi_data_addr:0] <= {c_mi_data_addr+1{1'b0}}; + else + begin + if (mp_fifo_read64) + address[c_mi_data_addr:0] <= viv_s52[c_mi_data_addr:0]; + end +end +always @(*) +begin + viv_s42 = 1'b0; + case(starage_format) + 2'b00: viv_s42 = viv_s45; + 2'b01: viv_s42 = viv_s44; + 2'b10: viv_s42 = viv_s43; + endcase +end +always @(posedge isp_0_clock or negedge isp_0_rst_n) +begin + if (~isp_0_rst_n) + viv_s41[7:0] <= 8'h0; + else + if(viv_s53) + viv_s41[7:0] <= 8'h0; + else + if(viv_s42) + viv_s41[7:0] <= viv_s41[7:0] + 1; +end +assign viv_s53 = ((viv_s41[7:0] == slice_cnt_int[7:0]) && viv_s42) || viv_s4; +always @(posedge isp_0_clock or negedge isp_0_rst_n) +begin + if (~isp_0_rst_n) + begin + sw_addr_mp_y[c_mi_data_addr:0] <= {c_mi_data_addr+1{1'b0}}; + sw_addr_mp_cb[c_mi_data_addr:0] <= {c_mi_data_addr+1{1'b0}}; + sw_addr_mp_cr[c_mi_data_addr:0] <= {c_mi_data_addr+1{1'b0}}; + end + else + if(viv_s53) + begin + sw_addr_mp_y[c_mi_data_addr:0] <= viv_s46[c_mi_data_addr:0]; + sw_addr_mp_cb[c_mi_data_addr:0] <= viv_s47[c_mi_data_addr:0]; + sw_addr_mp_cr[c_mi_data_addr:0] <= viv_s48[c_mi_data_addr:0]; + end +end +always @(posedge isp_0_clock or negedge isp_0_rst_n) +begin + if (~isp_0_rst_n) + viv_s40 <= 1'b0; + else + if(viv_s53) + viv_s40 <= 1'b1; + else + viv_s40 <= 1'b0; +end +assign sw_interrupt_out = viv_s40 && handshake_mode_0 && handshake_en; +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_marvin_mi_in.v b/ispyocto/rtl/ispyocto/vsisp_marvin_mi_in.v new file mode 100644 index 0000000..a3de7b6 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_marvin_mi_in.v
@@ -0,0 +1,694 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_marvin_mi_in + ( + clk, + reset_n, + soft_rst, + in_mp_y_val, + in_mp_y_data, + in_mp_y_h_end, + in_mp_y_v_end, + in_mp_y_cfg_upd, + in_mp_y_ack, + in_mp_cb_val, + in_mp_cb_data, + in_mp_cb_h_end, + in_mp_cb_v_end, + in_mp_cb_cfg_upd, + in_mp_cb_ack, + in_mp_cr_val, + in_mp_cr_data, + in_mp_cr_h_end, + in_mp_cr_v_end, + in_mp_cr_cfg_upd, + in_mp_cr_ack, + in_jpeg_val, + in_jpeg_data, + in_jpeg_end, + in_jpeg_byte_no, + in_jpeg_ack, + in_dp_data, + in_dp_end, + in_dp_val, + in_dp_ack, + in_sp_y_val, + in_sp_y_data, + in_sp_y_h_end, + in_sp_y_v_end, + in_sp_y_cfg_upd, + in_sp_y_ack, + in_sp_cb_val, + in_sp_cb_data, + in_sp_cb_h_end, + in_sp_cb_v_end, + in_sp_cb_cfg_upd, + in_sp_cb_ack, + in_sp_cr_val, + in_sp_cr_data, + in_sp_cr_h_end, + in_sp_cr_v_end, + in_sp_cr_cfg_upd, + in_sp_cr_ack, + mp_y_fifo_data, + mp_y_fifo_h_end, + mp_y_fifo_v_end, + mp_y_fifo_write64, + mp_y_fifo_full, + mp_cb_fifo_data, + mp_cb_fifo_h_end, + mp_cb_fifo_v_end, + mp_cb_fifo_write64, + mp_cb_fifo_full, + mp_cr_fifo_data, + mp_cr_fifo_h_end, + mp_cr_fifo_v_end, + mp_cr_fifo_write64, + mp_cr_fifo_full, + sp_y_fifo_data, + sp_y_fifo_h_end, + sp_y_fifo_v_end, + sp_y_fifo_write64, + sp_y_fifo_full, + sp_cb_fifo_data, + sp_cb_fifo_h_end, + sp_cb_fifo_v_end, + sp_cb_fifo_write64, + sp_cb_fifo_full, + sp_cr_fifo_data, + sp_cr_fifo_h_end, + sp_cr_fifo_v_end, + sp_cr_fifo_write64, + sp_cr_fifo_full, + mp_auto_update, + sp_auto_update, + mp_nv21, + sp_nv21, + soft_upd, + mp_enable, + sp_enable, + jpeg_enable, + dp_enable, + raw_enable, + mp_write_format, + sp_write_format, + sp_output_format, + sp_line_sens, + sp_col_sens, + stat_mp_enable_in, + stat_sp_enable_in, + stat_jpeg_enable_in, + stat_dp_enable_in, + stat_raw_enable_in, + stat_byte_cnt_raw_val, + stat_byte_cnt_raw, + stat_byte_cnt_raw_ack, + stat_byte_cnt_jpeg_val, + stat_byte_cnt_jpeg, + stat_byte_cnt_jpeg_ack, + stat_byte_cnt_dp_val, + stat_byte_cnt_dp, + stat_byte_cnt_dp_ack, + cfg_in_update_mp, + cfg_in_update_sp, + cfg_out_update_mp, + cfg_out_update_sp, + mp_line_sens, + mp_y_pic_width, + mp_y_pic_height, + mp_y_llength, + mp_y_pic_size, + slice_size, + data_format, + mp_slice_offset_y, + mp_slice_offset_c, + stat_skip_active, + handshake_en + ); +`include "vsisp_marvin_mi.vh" + input [31:0] mp_y_pic_width; + input [31:0] mp_y_pic_height; + input [14:0] mp_y_llength; + input [31:0] mp_y_pic_size; + input [7:0] slice_size; + input [1:0] data_format; + input [c_mi_data_addr:0] mp_slice_offset_y; + input [c_mi_data_addr:0] mp_slice_offset_c; + input stat_skip_active; + input handshake_en; + output mp_line_sens; + input clk; + input reset_n; + input soft_rst; + input in_mp_y_val; + input [7:0] in_mp_y_data; + input in_mp_y_h_end; + input in_mp_y_v_end; + input in_mp_y_cfg_upd; + output in_mp_y_ack; + input in_mp_cb_val; + input [7:0] in_mp_cb_data; + input in_mp_cb_h_end; + input in_mp_cb_v_end; + input in_mp_cb_cfg_upd; + output in_mp_cb_ack; + input in_mp_cr_val; + input [7:0] in_mp_cr_data; + input in_mp_cr_h_end; + input in_mp_cr_v_end; + input in_mp_cr_cfg_upd; + output in_mp_cr_ack; + input in_sp_y_val; + input [7:0] in_sp_y_data; + input in_sp_y_h_end; + input in_sp_y_v_end; + input in_sp_y_cfg_upd; + output in_sp_y_ack; + input in_sp_cb_val; + input [7:0] in_sp_cb_data; + input in_sp_cb_h_end; + input in_sp_cb_v_end; + input in_sp_cb_cfg_upd; + output in_sp_cb_ack; + input in_sp_cr_val; + input [7:0] in_sp_cr_data; + input in_sp_cr_h_end; + input in_sp_cr_v_end; + input in_sp_cr_cfg_upd; + output in_sp_cr_ack; + input in_jpeg_val; + input [63:0] in_jpeg_data; + input in_jpeg_end; + input [2:0] in_jpeg_byte_no; + output in_jpeg_ack; + input [31:0] in_dp_data; + input in_dp_end; + input in_dp_val; + output in_dp_ack; + output [63:0] mp_y_fifo_data; + output mp_y_fifo_h_end; + output mp_y_fifo_v_end; + output mp_y_fifo_write64; + input mp_y_fifo_full; + output [63:0] mp_cb_fifo_data; + output mp_cb_fifo_h_end; + output mp_cb_fifo_v_end; + output mp_cb_fifo_write64; + input mp_cb_fifo_full; + output [63:0] mp_cr_fifo_data; + output mp_cr_fifo_h_end; + output mp_cr_fifo_v_end; + output mp_cr_fifo_write64; + input mp_cr_fifo_full; + output [63:0] sp_y_fifo_data; + output sp_y_fifo_h_end; + output sp_y_fifo_v_end; + output sp_y_fifo_write64; + input sp_y_fifo_full; + output [63:0] sp_cb_fifo_data; + output sp_cb_fifo_h_end; + output sp_cb_fifo_v_end; + output sp_cb_fifo_write64; + input sp_cb_fifo_full; + output [63:0] sp_cr_fifo_data; + output sp_cr_fifo_h_end; + output sp_cr_fifo_v_end; + output sp_cr_fifo_write64; + input sp_cr_fifo_full; + input mp_auto_update; + input sp_auto_update; + input mp_nv21; + input sp_nv21; + input soft_upd; + input mp_enable; + input sp_enable; + input jpeg_enable; + input [1:0] dp_enable; + input raw_enable; + input [1:0] mp_write_format; + input [1:0] sp_write_format; + input [2:0] sp_output_format; + input sp_line_sens; + input sp_col_sens; + output stat_mp_enable_in; + output stat_sp_enable_in; + output stat_jpeg_enable_in; + output [1:0] stat_dp_enable_in; + output stat_raw_enable_in; + output stat_byte_cnt_raw_val; + output [c_mi_data_addr-1:0] stat_byte_cnt_raw; + input stat_byte_cnt_raw_ack; + output stat_byte_cnt_jpeg_val; + output [c_mi_data_addr-1:0] stat_byte_cnt_jpeg; + input stat_byte_cnt_jpeg_ack; + output stat_byte_cnt_dp_val; + output [c_mi_data_addr-1:0] stat_byte_cnt_dp; + input stat_byte_cnt_dp_ack; + reg stat_mp_enable_in; + reg stat_sp_enable_in; + reg stat_jpeg_enable_in; + reg [1:0] stat_dp_enable_in; + reg stat_raw_enable_in; + reg stat_byte_cnt_raw_val; + reg [c_mi_data_addr-1:0] stat_byte_cnt_raw; + reg stat_byte_cnt_jpeg_val; + reg [c_mi_data_addr-1:0] stat_byte_cnt_jpeg; + reg stat_byte_cnt_dp_val; + reg [c_mi_data_addr-1:0] stat_byte_cnt_dp; + output cfg_in_update_mp; + output cfg_in_update_sp; + input cfg_out_update_mp; + input cfg_out_update_sp; + wire [3:0] viv_s0; + wire [3:0] viv_s1; + wire mp_line_sens; + wire viv_s2; + reg viv_s3; + reg viv_s4; + reg viv_s5; + reg viv_s6; + reg viv_s7; + reg viv_s8; + reg [7:0] viv_s9; + reg [7:0] viv_s10; + reg [7:0] viv_s11; + reg [7:0] viv_s12; + reg [7:0] viv_s13; + reg [7:0] viv_s14; + wire viv_s15; + wire viv_s16; + wire viv_s17; + wire viv_s18; + wire viv_s19; + wire viv_s20; + wire viv_s21; + wire viv_s22; + wire viv_s23; + wire [63:0] viv_s24; + wire viv_s25; + wire viv_s26; + wire in_jpeg_ack; + wire viv_s27; + wire viv_s28; + wire viv_s29; + wire viv_s30; + wire viv_s31; + wire viv_s32; + wire viv_s33; + assign viv_s27 = in_mp_y_h_end; + assign viv_s28 = in_mp_cb_h_end; + assign viv_s29 = in_mp_cr_h_end; +assign viv_s15 = handshake_en && ((mp_slice_offset_y == {23'h0,viv_s12[7:0]}) ? 1'h0 : viv_s18); +assign viv_s16 = handshake_en && ((mp_slice_offset_c == {23'h0,viv_s13[7:0]}) ? 1'h0 : viv_s19); +assign viv_s17 = handshake_en && ((mp_slice_offset_c == {23'h0,viv_s14[7:0]}) ? 1'h0 : viv_s20); +always @(*) +begin + viv_s12[7:0] = 8'h0; + viv_s13[7:0] = 8'h0; + viv_s14[7:0] = 8'h0; + if(data_format[1:0] == 2'b00) + viv_s12[7:0] = slice_size[7:0]; + else + if((data_format[1:0] == 2'b01) || (data_format[1:0] == 2'b10)) + begin + viv_s12[7:0] = slice_size[7:0]; + viv_s13[7:0] = slice_size[7:0]; + viv_s14[7:0] = slice_size[7:0]; + end + else + begin + if(data_format[1:0] == 2'b11) + begin + viv_s12[7:0] = slice_size[7:0]; + viv_s13[7:0] = {1'b0,slice_size[7:1]}; + viv_s14[7:0] = {1'b0,slice_size[7:1]}; + end + end +end +always @(posedge clk or negedge reset_n) +begin + if (~reset_n) + viv_s9[7:0] <= 8'h0; + else + begin + if(viv_s18 || in_mp_y_v_end || soft_upd) + viv_s9[7:0] <= 8'h0; + else + begin + if(~stat_skip_active) + begin + if(in_mp_y_h_end) + viv_s9[7:0] <= viv_s9[7:0] + 1; + end + end + end +end +assign viv_s18 =((viv_s9[7:0] == viv_s12[7:0]) && in_mp_y_h_end); +always @(posedge clk or negedge reset_n) +begin + if (~reset_n) + viv_s10[7:0] <= 8'h0; + else + begin + if(viv_s19 || in_mp_cb_v_end || soft_upd) + viv_s10[7:0] <= 8'h0; + else + begin + if(~stat_skip_active) + begin + if(in_mp_cb_h_end) + viv_s10[7:0] <= viv_s10[7:0] + 1; + end + end + end +end +assign viv_s19 =((viv_s10[7:0] == viv_s13[7:0]) && in_mp_cb_h_end); +always @(posedge clk or negedge reset_n) +begin + if (~reset_n) + viv_s11[7:0] <= 8'h0; + else + begin + if(viv_s20 || in_mp_cr_v_end || soft_upd) + viv_s11[7:0] <= 8'h0; + else + begin + if(~stat_skip_active) + begin + if(in_mp_cr_h_end) + viv_s11[7:0] <= viv_s11[7:0] + 1; + end + end + end +end +assign viv_s20 =((viv_s11[7:0] == viv_s14[7:0]) && in_mp_cr_h_end); + vsisp_marvin_mi_dpsbe #(65) u_marvin_mi_dpsbe + ( + .clk (clk), + .reset_n (reset_n), + .soft_rst (soft_rst), + .dpsbe_data_i ({in_jpeg_end, + in_jpeg_data}), + .dpsbe_val_i (in_jpeg_val), + .dpsbe_ack_o (in_jpeg_ack), + .dpsbe_data_o ({viv_s25, + viv_s24}), + .dpsbe_val_o (viv_s23), + .dpsbe_ack_i (viv_s26) + ); + vsisp_marvin_mi_in_distrib u_marvin_mi_mp_distrib + ( + .slice_offset_sens_y(viv_s15), + .slice_offset_sens_cb(viv_s16), + .slice_offset_sens_cr(viv_s17), + .clk (clk), + .reset_n (reset_n), + .soft_rst (soft_rst), + .in_y_val (in_mp_y_val), + .in_y_data (in_mp_y_data), + .in_y_h_end (viv_s27), + .in_y_v_end (in_mp_y_v_end), + .in_y_cfg_upd (in_mp_y_cfg_upd), + .in_y_ack (in_mp_y_ack), + .in_cb_val (in_mp_cb_val), + .in_cb_data (in_mp_cb_data), + .in_cb_h_end (viv_s28), + .in_cb_v_end (in_mp_cb_v_end), + .in_cb_cfg_upd (in_mp_cb_cfg_upd), + .in_cb_ack (in_mp_cb_ack), + .in_cr_val (in_mp_cr_val), + .in_cr_data (in_mp_cr_data), + .in_cr_h_end (viv_s29), + .in_cr_v_end (in_mp_cr_v_end), + .in_cr_cfg_upd (in_mp_cr_cfg_upd), + .in_cr_ack (in_mp_cr_ack), + .in_jpeg_val (viv_s23), + .in_jpeg_data (viv_s24), + .in_jpeg_end (viv_s25), + .in_jpeg_ack (viv_s26), + .in_dp_data (in_dp_data), + .in_dp_val (in_dp_val), + .in_dp_ack (viv_s21), + .in_dp_end (in_dp_end), + .out_y_fifo_data (mp_y_fifo_data), + .out_y_fifo_h_end (mp_y_fifo_h_end), + .out_y_fifo_v_end (mp_y_fifo_v_end), + .out_y_fifo_write64 (mp_y_fifo_write64), + .out_y_fifo_full (mp_y_fifo_full), + .out_cb_fifo_data (mp_cb_fifo_data), + .out_cb_fifo_h_end (mp_cb_fifo_h_end), + .out_cb_fifo_v_end (mp_cb_fifo_v_end), + .out_cb_fifo_write64 (mp_cb_fifo_write64), + .out_cb_fifo_full (mp_cb_fifo_full), + .out_cr_fifo_data (mp_cr_fifo_data), + .out_cr_fifo_h_end (mp_cr_fifo_h_end), + .out_cr_fifo_v_end (mp_cr_fifo_v_end), + .out_cr_fifo_write64 (mp_cr_fifo_write64), + .out_cr_fifo_full (mp_cr_fifo_full), + .path_sel (viv_s0), + .nv21 (mp_nv21), + .line_sens (mp_line_sens), + .col_sens (viv_s2), + .auto_update (mp_auto_update), + .cfg_in_update (cfg_in_update_mp), + .cfg_out_update (cfg_out_update_mp) + ); + assign mp_line_sens = mp_y_pic_width != mp_y_llength; + assign viv_s2 = 1'b0; + assign viv_s0 = + (stat_raw_enable_in & ((mp_write_format==2'b01) | (mp_write_format==2'b10))) ? 4'b1_111 : + (stat_raw_enable_in & (mp_write_format==2'b00)) ? 4'b1_110 : + (stat_dp_enable_in[0] ) ? 4'b0_001 : + (stat_jpeg_enable_in ) ? 4'b1_011 : + (stat_mp_enable_in & (mp_write_format == 2'b10)) ? 4'b1_010 : + (stat_mp_enable_in & (mp_write_format == 2'b01)) ? 4'b1_001 : + (stat_mp_enable_in & (mp_write_format == 2'b00)) ? 4'b1_000 : + (stat_mp_enable_in & (mp_write_format == 2'b11)) ? 4'b1_110 : + 4'b0_000; + assign viv_s30 = in_sp_y_h_end && (in_sp_y_v_end || sp_line_sens); + assign viv_s31 = in_sp_cb_h_end && (in_sp_cb_v_end || sp_line_sens); + assign viv_s32 = in_sp_cr_h_end && (in_sp_cr_v_end || sp_line_sens); + vsisp_marvin_mi_in_distrib u_marvin_mi_sp_distrib + ( + .slice_offset_sens_y (1'b0), + .slice_offset_sens_cb(1'b0), + .slice_offset_sens_cr(1'b0), + .clk (clk), + .reset_n (reset_n), + .soft_rst (soft_rst), + .in_y_val (in_sp_y_val), + .in_y_data (in_sp_y_data), + .in_y_h_end (viv_s30), + .in_y_v_end (in_sp_y_v_end), + .in_y_cfg_upd (in_sp_y_cfg_upd), + .in_y_ack (in_sp_y_ack), + .in_cb_val (in_sp_cb_val), + .in_cb_data (in_sp_cb_data), + .in_cb_h_end (viv_s31), + .in_cb_v_end (in_sp_cb_v_end), + .in_cb_cfg_upd (in_sp_cb_cfg_upd), + .in_cb_ack (in_sp_cb_ack), + .in_cr_val (in_sp_cr_val), + .in_cr_data (in_sp_cr_data), + .in_cr_h_end (viv_s32), + .in_cr_v_end (in_sp_cr_v_end), + .in_cr_cfg_upd (in_sp_cr_cfg_upd), + .in_cr_ack (in_sp_cr_ack), + .in_jpeg_val (1'b0), + .in_jpeg_data (64'b0), + .in_jpeg_end (1'b0), + .in_jpeg_ack (viv_s33), + .in_dp_data (in_dp_data), + .in_dp_val (in_dp_val), + .in_dp_ack (viv_s22), + .in_dp_end (in_dp_end), + .out_y_fifo_data (sp_y_fifo_data), + .out_y_fifo_h_end (sp_y_fifo_h_end), + .out_y_fifo_v_end (sp_y_fifo_v_end), + .out_y_fifo_write64 (sp_y_fifo_write64), + .out_y_fifo_full (sp_y_fifo_full), + .out_cb_fifo_data (sp_cb_fifo_data), + .out_cb_fifo_h_end (sp_cb_fifo_h_end), + .out_cb_fifo_v_end (sp_cb_fifo_v_end), + .out_cb_fifo_write64 (sp_cb_fifo_write64), + .out_cb_fifo_full (sp_cb_fifo_full), + .out_cr_fifo_data (sp_cr_fifo_data), + .out_cr_fifo_h_end (sp_cr_fifo_h_end), + .out_cr_fifo_v_end (sp_cr_fifo_v_end), + .out_cr_fifo_write64 (sp_cr_fifo_write64), + .out_cr_fifo_full (sp_cr_fifo_full), + .path_sel (viv_s1), + .nv21 (sp_nv21), + .line_sens (sp_line_sens), + .col_sens (sp_col_sens), + .auto_update (sp_auto_update), + .cfg_in_update (cfg_in_update_sp), + .cfg_out_update (cfg_out_update_sp) + ); + assign viv_s1 = + (stat_sp_enable_in & (sp_output_format==3'b100)) ? 4'b1_101 : + (stat_sp_enable_in & ((sp_output_format==3'b110) | (sp_output_format==3'b101))) ? 4'b1_100 : + (stat_dp_enable_in[1] ) ? 4'b0_001 : + (stat_sp_enable_in & (sp_write_format == 2'b10)) ? 4'b1_010 : + (stat_sp_enable_in & (sp_write_format == 2'b01)) ? 4'b1_001 : + (stat_sp_enable_in & (sp_write_format == 2'b00)) ? 4'b1_000 : + (sp_output_format == 3'b100) ? 4'b0_101 : + 4'b0_000; + assign in_dp_ack = (stat_dp_enable_in[0]) ? viv_s21 : + (stat_dp_enable_in[1]) ? viv_s22 : 1'b1; + always @(posedge clk or negedge reset_n) begin + if (~reset_n) begin + stat_mp_enable_in <= 1'b0; + stat_sp_enable_in <= 1'b0; + stat_jpeg_enable_in <= 1'b0; + stat_dp_enable_in <= 2'b0; + stat_raw_enable_in <= 1'b0; + end + else begin + if (cfg_in_update_mp | soft_upd) begin + stat_mp_enable_in <= mp_enable; + stat_raw_enable_in <= raw_enable; + end + if (cfg_in_update_sp | soft_upd) begin + stat_sp_enable_in <= sp_enable; + end + if (soft_upd) begin + stat_jpeg_enable_in <= jpeg_enable; + stat_dp_enable_in <= dp_enable; + end + end + end + always @(posedge clk or negedge reset_n) begin + if (~reset_n) begin + viv_s3 <= 1'b0; + viv_s4 <= 1'b0; + end + else begin + viv_s3 <= stat_byte_cnt_raw_ack; + viv_s4 <= viv_s3; + end + end + always @(posedge clk or negedge reset_n) begin + if (~reset_n) begin + stat_byte_cnt_raw_val <= 1'b0; + stat_byte_cnt_raw <= {c_mi_data_addr{1'b0}}; + end + else if (soft_rst) begin + stat_byte_cnt_raw_val <= 1'b0; + stat_byte_cnt_raw <= {c_mi_data_addr{1'b0}}; + end + else begin + if (stat_byte_cnt_raw_val) begin + if (viv_s4) begin + stat_byte_cnt_raw_val <= 1'b0; + stat_byte_cnt_raw <= {c_mi_data_addr{1'b0}}; + end + end + else if (stat_raw_enable_in & in_mp_y_val & in_mp_y_ack) begin + if (in_mp_y_h_end & in_mp_y_v_end) begin + stat_byte_cnt_raw_val <= 1'b1; + stat_byte_cnt_raw <= stat_byte_cnt_raw + + ((mp_write_format[1] == 1'b1) ? 28'd2 : 28'd1); + end + else begin + stat_byte_cnt_raw <= stat_byte_cnt_raw + + ((mp_write_format[1] == 1'b1) ? 28'd2 : 28'd1); + end + end + end + end + always @(posedge clk or negedge reset_n) begin + if (~reset_n) begin + viv_s5 <= 1'b0; + viv_s6 <= 1'b0; + end + else begin + viv_s5 <= stat_byte_cnt_jpeg_ack; + viv_s6 <= viv_s5; + end + end + always @(posedge clk or negedge reset_n) begin + if (reset_n == 1'b0) begin + stat_byte_cnt_jpeg_val <= 1'b0; + stat_byte_cnt_jpeg <= {c_mi_data_addr{1'b0}}; + end + else if (soft_rst) begin + stat_byte_cnt_jpeg_val <= 1'b0; + stat_byte_cnt_jpeg <= {c_mi_data_addr{1'b0}}; + end + else begin + if (stat_byte_cnt_jpeg_val) begin + if (viv_s6) begin + stat_byte_cnt_jpeg_val <= 1'b0; + stat_byte_cnt_jpeg <= {c_mi_data_addr{1'b0}}; + end + end + else if (stat_jpeg_enable_in & in_jpeg_val & in_jpeg_ack) begin + if (in_jpeg_end) begin + stat_byte_cnt_jpeg_val <= 1'b1; + stat_byte_cnt_jpeg <= stat_byte_cnt_jpeg + + {25'h0, in_jpeg_byte_no} + 28'd1; + end + else begin + stat_byte_cnt_jpeg <= stat_byte_cnt_jpeg + + ((in_jpeg_byte_no[2]) ? 28'd8 : 28'd4); + end + end + end + end + always @(posedge clk or negedge reset_n) begin + if (~reset_n) begin + viv_s7 <= 1'b0; + viv_s8 <= 1'b0; + end + else begin + viv_s7 <= stat_byte_cnt_dp_ack; + viv_s8 <= viv_s7; + end + end + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + stat_byte_cnt_dp_val <= 1'b0; + stat_byte_cnt_dp <= {c_mi_data_addr{1'b0}}; + end + else if (soft_rst) begin + stat_byte_cnt_dp_val <= 1'b0; + stat_byte_cnt_dp <= {c_mi_data_addr{1'b0}}; + end + else begin + if (stat_byte_cnt_dp_val) begin + if (viv_s8) begin + stat_byte_cnt_dp_val <= 1'b0; + stat_byte_cnt_dp <= {c_mi_data_addr{1'b0}}; + end + end + else if (|stat_dp_enable_in & in_dp_val & in_dp_ack) begin + stat_byte_cnt_dp <= stat_byte_cnt_dp + 28'd1; + if (in_dp_end) begin + stat_byte_cnt_dp_val <= 1'b1; + end + end + end + end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_marvin_mi_in_distrib.v b/ispyocto/rtl/ispyocto/vsisp_marvin_mi_in_distrib.v new file mode 100644 index 0000000..b46c7c2 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_marvin_mi_in_distrib.v
@@ -0,0 +1,1753 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_marvin_mi_in_distrib + ( + clk, + reset_n, + soft_rst, + in_y_val, + in_y_data, + in_y_h_end, + in_y_v_end, + in_y_cfg_upd, + in_y_ack, + in_cb_val, + in_cb_data, + in_cb_h_end, + in_cb_v_end, + in_cb_cfg_upd, + in_cb_ack, + in_cr_val, + in_cr_data, + in_cr_h_end, + in_cr_v_end, + in_cr_cfg_upd, + in_cr_ack, + in_jpeg_val, + in_jpeg_data, + in_jpeg_end, + in_jpeg_ack, + in_dp_data, + in_dp_end, + in_dp_val, + in_dp_ack, + out_y_fifo_data, + out_y_fifo_h_end, + out_y_fifo_v_end, + out_y_fifo_write64, + out_y_fifo_full, + out_cb_fifo_data, + out_cb_fifo_h_end, + out_cb_fifo_v_end, + out_cb_fifo_write64, + out_cb_fifo_full, + out_cr_fifo_data, + out_cr_fifo_h_end, + out_cr_fifo_v_end, + out_cr_fifo_write64, + out_cr_fifo_full, + path_sel, + nv21, + line_sens, + col_sens, + auto_update, + cfg_in_update, + cfg_out_update, + slice_offset_sens_y, + slice_offset_sens_cb, + slice_offset_sens_cr + ); + input slice_offset_sens_y; + input slice_offset_sens_cb; + input slice_offset_sens_cr; + input clk; + input reset_n; + input soft_rst; + input in_y_val; + input [7:0] in_y_data; + input in_y_h_end; + input in_y_v_end; + input in_y_cfg_upd; + output in_y_ack; + input in_cb_val; + input [7:0] in_cb_data; + input in_cb_h_end; + input in_cb_v_end; + input in_cb_cfg_upd; + output in_cb_ack; + input in_cr_val; + input [7:0] in_cr_data; + input in_cr_h_end; + input in_cr_v_end; + input in_cr_cfg_upd; + output in_cr_ack; + input in_jpeg_val; + input [63:0] in_jpeg_data; + input in_jpeg_end; + output in_jpeg_ack; + input [31:0] in_dp_data; + input in_dp_end; + input in_dp_val; + output in_dp_ack; + output [63:0] out_y_fifo_data; + output out_y_fifo_h_end; + output out_y_fifo_v_end; + output out_y_fifo_write64; + input out_y_fifo_full; + reg [63:0] out_y_fifo_data; + reg out_y_fifo_h_end; + reg out_y_fifo_v_end; + reg out_y_fifo_write64; + output [63:0] out_cb_fifo_data; + output out_cb_fifo_h_end; + output out_cb_fifo_v_end; + output out_cb_fifo_write64; + input out_cb_fifo_full; + reg [63:0] out_cb_fifo_data; + reg out_cb_fifo_h_end; + reg out_cb_fifo_v_end; + reg out_cb_fifo_write64; + output [63:0] out_cr_fifo_data; + output out_cr_fifo_h_end; + output out_cr_fifo_v_end; + output out_cr_fifo_write64; + input out_cr_fifo_full; + reg [63:0] out_cr_fifo_data; + reg out_cr_fifo_h_end; + reg out_cr_fifo_v_end; + reg out_cr_fifo_write64; + input [3:0] path_sel; + input nv21; + input line_sens; + input col_sens; + input auto_update; + output cfg_in_update; + input cfg_out_update; + reg cfg_in_update; + wire [10:0] viv_s0; + wire viv_s1; + wire [10:0] viv_s2; + wire [7:0] viv_s3; + wire viv_s4; + wire viv_s5; + wire viv_s6; + wire viv_s7; + wire viv_s8; + wire [10:0] viv_s9; + wire [7:0] viv_s10; + wire viv_s11; + wire viv_s12; + wire viv_s13; + wire viv_s14; + wire viv_s15; + wire viv_s16; + wire [10:0] viv_s17; + wire [7:0] viv_s18; + wire viv_s19; + wire viv_s20; + wire viv_s21; + wire viv_s22; + wire viv_s23; + wire viv_s24; + wire [10:0] viv_s25; + wire [7:0] viv_s26; + wire viv_s27; + wire viv_s28; + wire viv_s29; + wire viv_s30; + wire viv_s31; + wire viv_s32; + wire [10:0] viv_s33; + wire [7:0] viv_s34; + wire viv_s35; + wire viv_s36; + wire viv_s37; + wire viv_s38; + wire viv_s39; + wire viv_s40; + wire [10:0] viv_s41; + wire [7:0] viv_s42; + wire viv_s43; + wire viv_s44; + wire viv_s45; + wire viv_s46; + wire viv_s47; + wire viv_s48; + wire [10:0] viv_s49; + wire [7:0] viv_s50; + wire viv_s51; + wire viv_s52; + wire viv_s53; + wire viv_s54; + wire viv_s55; + wire viv_s56; + wire [10:0] viv_s57; + wire [7:0] viv_s58; + wire viv_s59; + wire viv_s60; + wire viv_s61; + wire viv_s62; + wire viv_s63; + wire [10:0] viv_s64; + wire viv_s65; + wire [10:0] viv_s66; + wire [7:0] viv_s67; + wire viv_s68; + wire viv_s69; + wire viv_s70; + wire viv_s71; + wire viv_s72; + wire [10:0] viv_s73; + wire [7:0] viv_s74; + wire viv_s75; + wire viv_s76; + wire viv_s77; + wire viv_s78; + wire viv_s79; + wire viv_s80; + wire [10:0] viv_s81; + wire [7:0] viv_s82; + wire viv_s83; + wire viv_s84; + wire viv_s85; + wire viv_s86; + wire viv_s87; + wire viv_s88; + wire [10:0] viv_s89; + wire [7:0] viv_s90; + wire viv_s91; + wire viv_s92; + wire viv_s93; + wire viv_s94; + wire viv_s95; + wire viv_s96; + wire [10:0] viv_s97; + wire [7:0] viv_s98; + wire viv_s99; + wire viv_s100; + wire viv_s101; + wire viv_s102; + wire viv_s103; + wire viv_s104; + wire [10:0] viv_s105; + wire [7:0] viv_s106; + wire viv_s107; + wire viv_s108; + wire viv_s109; + wire viv_s110; + wire viv_s111; + wire viv_s112; + wire [10:0] viv_s113; + wire [7:0] viv_s114; + wire viv_s115; + wire viv_s116; + wire viv_s117; + wire viv_s118; + wire viv_s119; + wire viv_s120; + wire [10:0] viv_s121; + wire [7:0] viv_s122; + wire viv_s123; + wire viv_s124; + wire viv_s125; + wire viv_s126; + wire viv_s127; + wire [10:0] viv_s128; + wire viv_s129; + wire [10:0] viv_s130; + wire [7:0] viv_s131; + wire viv_s132; + wire viv_s133; + wire viv_s134; + wire viv_s135; + wire viv_s136; + wire [10:0] viv_s137; + wire [7:0] viv_s138; + wire viv_s139; + wire viv_s140; + wire viv_s141; + wire viv_s142; + wire viv_s143; + wire viv_s144; + wire [10:0] viv_s145; + wire [7:0] viv_s146; + wire viv_s147; + wire viv_s148; + wire viv_s149; + wire viv_s150; + wire viv_s151; + wire viv_s152; + wire [10:0] viv_s153; + wire [7:0] viv_s154; + wire viv_s155; + wire viv_s156; + wire viv_s157; + wire viv_s158; + wire viv_s159; + wire viv_s160; + wire [10:0] viv_s161; + wire [7:0] viv_s162; + wire viv_s163; + wire viv_s164; + wire viv_s165; + wire viv_s166; + wire viv_s167; + wire viv_s168; + wire [10:0] viv_s169; + wire [7:0] viv_s170; + wire viv_s171; + wire viv_s172; + wire viv_s173; + wire viv_s174; + wire viv_s175; + wire viv_s176; + wire [10:0] viv_s177; + wire [7:0] viv_s178; + wire viv_s179; + wire viv_s180; + wire viv_s181; + wire viv_s182; + wire viv_s183; + wire viv_s184; + wire [10:0] viv_s185; + wire [7:0] viv_s186; + wire viv_s187; + wire viv_s188; + wire viv_s189; + wire viv_s190; + wire viv_s191; + wire viv_s192; + wire viv_s193; + wire [31:0] viv_s194; + wire [32:0] viv_s195; + wire viv_s196; + wire viv_s197; + wire viv_s198; + wire [31:0] viv_s199; + wire [32:0] viv_s200; + wire viv_s201; + reg [1:0] viv_s202; + reg viv_s203; + reg viv_s204; + wire viv_s205; + reg in_jpeg_ack; + reg viv_s206; + reg viv_s207; + reg viv_s208; + reg viv_s209; + reg viv_s210; + reg viv_s211; + reg viv_s212; + reg viv_s213; + reg [7:0] viv_s214; + reg viv_s215; + reg viv_s216; + reg viv_s217; + reg viv_s218; + reg viv_s219; + reg viv_s220; + reg viv_s221; + reg viv_s222; + reg [7:0] viv_s223; + reg viv_s224; + reg viv_s225; + reg viv_s226; + reg viv_s227; + reg viv_s228; + reg viv_s229; + reg viv_s230; + reg viv_s231; + reg [7:0] viv_s232; + reg viv_s233; + reg viv_s234; + reg viv_s235; + reg viv_s236; + reg viv_s237; + reg viv_s238; + reg viv_s239; + reg viv_s240; + assign viv_s0 = {in_y_cfg_upd, in_y_v_end, in_y_h_end, in_y_data}; + vsisp_marvin_mi_dpsbe #(11) u_y_buf7 + ( + .clk (clk), + .reset_n (reset_n), + .soft_rst (soft_rst), + .dpsbe_data_i (viv_s0), + .dpsbe_val_i (in_y_val), + .dpsbe_ack_o (in_y_ack), + .dpsbe_data_o (viv_s57), + .dpsbe_val_o (viv_s56), + .dpsbe_ack_i (viv_s63) + ); + assign viv_s58 = viv_s57[7:0]; + assign viv_s59 = viv_s57[8]; + assign viv_s60 = viv_s57[9]; + assign viv_s61 = viv_s57[10]; + assign viv_s63 = viv_s62 | viv_s214[7]; + vsisp_marvin_mi_dpsbe #(11) u_y_buf6 + ( + .clk (clk), + .reset_n (reset_n), + .soft_rst (soft_rst), + .dpsbe_data_i (viv_s57), + .dpsbe_val_i (viv_s56), + .dpsbe_ack_o (viv_s62), + .dpsbe_data_o (viv_s49), + .dpsbe_val_o (viv_s48), + .dpsbe_ack_i (viv_s55) + ); + assign viv_s50 = viv_s49[7:0]; + assign viv_s51 = viv_s49[8]; + assign viv_s52 = viv_s49[9]; + assign viv_s53 = viv_s49[10]; + assign viv_s55 = viv_s54 | viv_s214[6]; + vsisp_marvin_mi_dpsbe #(11) u_y_buf5 + ( + .clk (clk), + .reset_n (reset_n), + .soft_rst (soft_rst), + .dpsbe_data_i (viv_s49), + .dpsbe_val_i (viv_s48), + .dpsbe_ack_o (viv_s54), + .dpsbe_data_o (viv_s41), + .dpsbe_val_o (viv_s40), + .dpsbe_ack_i (viv_s47) + ); + assign viv_s42 = viv_s41[7:0]; + assign viv_s43 = viv_s41[8]; + assign viv_s44 = viv_s41[9]; + assign viv_s45 = viv_s41[10]; + assign viv_s47 = viv_s46 | viv_s214[5]; + vsisp_marvin_mi_dpsbe #(11) u_y_buf4 + ( + .clk (clk), + .reset_n (reset_n), + .soft_rst (soft_rst), + .dpsbe_data_i (viv_s41), + .dpsbe_val_i (viv_s40), + .dpsbe_ack_o (viv_s46), + .dpsbe_data_o (viv_s33), + .dpsbe_val_o (viv_s32), + .dpsbe_ack_i (viv_s39) + ); + assign viv_s34 = viv_s33[7:0]; + assign viv_s35 = viv_s33[8]; + assign viv_s36 = viv_s33[9]; + assign viv_s37 = viv_s33[10]; + assign viv_s39 = viv_s38 | viv_s214[4]; + vsisp_marvin_mi_dpsbe #(11) u_y_buf3 + ( + .clk (clk), + .reset_n (reset_n), + .soft_rst (soft_rst), + .dpsbe_data_i (viv_s33), + .dpsbe_val_i (viv_s32), + .dpsbe_ack_o (viv_s38), + .dpsbe_data_o (viv_s25), + .dpsbe_val_o (viv_s24), + .dpsbe_ack_i (viv_s31) + ); + assign viv_s26 = viv_s25[7:0]; + assign viv_s27 = viv_s25[8]; + assign viv_s28 = viv_s25[9]; + assign viv_s29 = viv_s25[10]; + assign viv_s31 = viv_s30 | viv_s214[3]; + vsisp_marvin_mi_dpsbe #(11) u_y_buf2 + ( + .clk (clk), + .reset_n (reset_n), + .soft_rst (soft_rst), + .dpsbe_data_i (viv_s25), + .dpsbe_val_i (viv_s24), + .dpsbe_ack_o (viv_s30), + .dpsbe_data_o (viv_s17), + .dpsbe_val_o (viv_s16), + .dpsbe_ack_i (viv_s23) + ); + assign viv_s18 = viv_s17[7:0]; + assign viv_s19 = viv_s17[8]; + assign viv_s20 = viv_s17[9]; + assign viv_s21 = viv_s17[10]; + assign viv_s23 = viv_s22 | viv_s214[2]; + vsisp_marvin_mi_dpsbe #(11) u_y_buf1 + ( + .clk (clk), + .reset_n (reset_n), + .soft_rst (soft_rst), + .dpsbe_data_i (viv_s17), + .dpsbe_val_i (viv_s16), + .dpsbe_ack_o (viv_s22), + .dpsbe_data_o (viv_s9), + .dpsbe_val_o (viv_s8), + .dpsbe_ack_i (viv_s15) + ); + assign viv_s10 = viv_s9[7:0]; + assign viv_s11 = viv_s9[8]; + assign viv_s12 = viv_s9[9]; + assign viv_s13 = viv_s9[10]; + assign viv_s15 = viv_s14 | viv_s214[1]; + vsisp_marvin_mi_dpsbe #(11) u_y_buf0 + ( + .clk (clk), + .reset_n (reset_n), + .soft_rst (soft_rst), + .dpsbe_data_i (viv_s9), + .dpsbe_val_i (viv_s8), + .dpsbe_ack_o (viv_s14), + .dpsbe_data_o (viv_s2), + .dpsbe_val_o (viv_s1), + .dpsbe_ack_i (viv_s7) + ); + assign viv_s3 = viv_s2[7:0]; + assign viv_s4 = viv_s2[8]; + assign viv_s5 = viv_s2[9]; + assign viv_s6 = viv_s2[10]; + assign viv_s7 = viv_s214[0]; + assign viv_s64 = {in_cb_cfg_upd, in_cb_v_end, in_cb_h_end, in_cb_data}; + vsisp_marvin_mi_dpsbe #(11) u_cb_buf7 + ( + .clk (clk), + .reset_n (reset_n), + .soft_rst (soft_rst), + .dpsbe_data_i (viv_s64), + .dpsbe_val_i (in_cb_val), + .dpsbe_ack_o (in_cb_ack), + .dpsbe_data_o (viv_s121), + .dpsbe_val_o (viv_s120), + .dpsbe_ack_i (viv_s127) + ); + assign viv_s122 = viv_s121[7:0]; + assign viv_s123 = viv_s121[8]; + assign viv_s124 = viv_s121[9]; + assign viv_s125 = viv_s121[10]; + assign viv_s127 = viv_s126 | viv_s223[7]; + vsisp_marvin_mi_dpsbe #(11) u_cb_buf6 + ( + .clk (clk), + .reset_n (reset_n), + .soft_rst (soft_rst), + .dpsbe_data_i (viv_s121), + .dpsbe_val_i (viv_s120), + .dpsbe_ack_o (viv_s126), + .dpsbe_data_o (viv_s113), + .dpsbe_val_o (viv_s112), + .dpsbe_ack_i (viv_s119) + ); + assign viv_s114 = viv_s113[7:0]; + assign viv_s115 = viv_s113[8]; + assign viv_s116 = viv_s113[9]; + assign viv_s117 = viv_s113[10]; + assign viv_s119 = viv_s118 | viv_s223[6]; + vsisp_marvin_mi_dpsbe #(11) u_cb_buf5 + ( + .clk (clk), + .reset_n (reset_n), + .soft_rst (soft_rst), + .dpsbe_data_i (viv_s113), + .dpsbe_val_i (viv_s112), + .dpsbe_ack_o (viv_s118), + .dpsbe_data_o (viv_s105), + .dpsbe_val_o (viv_s104), + .dpsbe_ack_i (viv_s111) + ); + assign viv_s106 = viv_s105[7:0]; + assign viv_s107 = viv_s105[8]; + assign viv_s108 = viv_s105[9]; + assign viv_s109 = viv_s105[10]; + assign viv_s111 = viv_s110 | viv_s223[5]; + vsisp_marvin_mi_dpsbe #(11) u_cb_buf4 + ( + .clk (clk), + .reset_n (reset_n), + .soft_rst (soft_rst), + .dpsbe_data_i (viv_s105), + .dpsbe_val_i (viv_s104), + .dpsbe_ack_o (viv_s110), + .dpsbe_data_o (viv_s97), + .dpsbe_val_o (viv_s96), + .dpsbe_ack_i (viv_s103) + ); + assign viv_s98 = viv_s97[7:0]; + assign viv_s99 = viv_s97[8]; + assign viv_s100 = viv_s97[9]; + assign viv_s101 = viv_s97[10]; + assign viv_s103 = viv_s102 | viv_s223[4]; + vsisp_marvin_mi_dpsbe #(11) u_cb_buf3 + ( + .clk (clk), + .reset_n (reset_n), + .soft_rst (soft_rst), + .dpsbe_data_i (viv_s97), + .dpsbe_val_i (viv_s96), + .dpsbe_ack_o (viv_s102), + .dpsbe_data_o (viv_s89), + .dpsbe_val_o (viv_s88), + .dpsbe_ack_i (viv_s95) + ); + assign viv_s90 = viv_s89[7:0]; + assign viv_s91 = viv_s89[8]; + assign viv_s92 = viv_s89[9]; + assign viv_s93 = viv_s89[10]; + assign viv_s95 = viv_s94 | viv_s223[3]; + vsisp_marvin_mi_dpsbe #(11) u_cb_buf2 + ( + .clk (clk), + .reset_n (reset_n), + .soft_rst (soft_rst), + .dpsbe_data_i (viv_s89), + .dpsbe_val_i (viv_s88), + .dpsbe_ack_o (viv_s94), + .dpsbe_data_o (viv_s81), + .dpsbe_val_o (viv_s80), + .dpsbe_ack_i (viv_s87) + ); + assign viv_s82 = viv_s81[7:0]; + assign viv_s83 = viv_s81[8]; + assign viv_s84 = viv_s81[9]; + assign viv_s85 = viv_s81[10]; + assign viv_s87 = viv_s86 | viv_s223[2]; + vsisp_marvin_mi_dpsbe #(11) u_cb_buf1 + ( + .clk (clk), + .reset_n (reset_n), + .soft_rst (soft_rst), + .dpsbe_data_i (viv_s81), + .dpsbe_val_i (viv_s80), + .dpsbe_ack_o (viv_s86), + .dpsbe_data_o (viv_s73), + .dpsbe_val_o (viv_s72), + .dpsbe_ack_i (viv_s79) + ); + assign viv_s74 = viv_s73[7:0]; + assign viv_s75 = viv_s73[8]; + assign viv_s76 = viv_s73[9]; + assign viv_s77 = viv_s73[10]; + assign viv_s79 = viv_s78 | viv_s223[1]; + vsisp_marvin_mi_dpsbe #(11) u_cb_buf0 + ( + .clk (clk), + .reset_n (reset_n), + .soft_rst (soft_rst), + .dpsbe_data_i (viv_s73), + .dpsbe_val_i (viv_s72), + .dpsbe_ack_o (viv_s78), + .dpsbe_data_o (viv_s66), + .dpsbe_val_o (viv_s65), + .dpsbe_ack_i (viv_s71) + ); + assign viv_s67 = viv_s66[7:0]; + assign viv_s68 = viv_s66[8]; + assign viv_s69 = viv_s66[9]; + assign viv_s70 = viv_s66[10]; + assign viv_s71 = viv_s223[0]; + assign viv_s128 = {in_cr_cfg_upd, in_cr_v_end, in_cr_h_end, in_cr_data}; + vsisp_marvin_mi_dpsbe #(11) u_cr_buf7 + ( + .clk (clk), + .reset_n (reset_n), + .soft_rst (soft_rst), + .dpsbe_data_i (viv_s128), + .dpsbe_val_i (in_cr_val), + .dpsbe_ack_o (in_cr_ack), + .dpsbe_data_o (viv_s185), + .dpsbe_val_o (viv_s184), + .dpsbe_ack_i (viv_s191) + ); + assign viv_s186 = viv_s185[7:0]; + assign viv_s187 = viv_s185[8]; + assign viv_s188 = viv_s185[9]; + assign viv_s189 = viv_s185[10]; + assign viv_s191 = viv_s190 | viv_s232[7]; + vsisp_marvin_mi_dpsbe #(11) u_cr_buf6 + ( + .clk (clk), + .reset_n (reset_n), + .soft_rst (soft_rst), + .dpsbe_data_i (viv_s185), + .dpsbe_val_i (viv_s184), + .dpsbe_ack_o (viv_s190), + .dpsbe_data_o (viv_s177), + .dpsbe_val_o (viv_s176), + .dpsbe_ack_i (viv_s183) + ); + assign viv_s178 = viv_s177[7:0]; + assign viv_s179 = viv_s177[8]; + assign viv_s180 = viv_s177[9]; + assign viv_s181 = viv_s177[10]; + assign viv_s183 = viv_s182 | viv_s232[6]; + vsisp_marvin_mi_dpsbe #(11) u_cr_buf5 + ( + .clk (clk), + .reset_n (reset_n), + .soft_rst (soft_rst), + .dpsbe_data_i (viv_s177), + .dpsbe_val_i (viv_s176), + .dpsbe_ack_o (viv_s182), + .dpsbe_data_o (viv_s169), + .dpsbe_val_o (viv_s168), + .dpsbe_ack_i (viv_s175) + ); + assign viv_s170 = viv_s169[7:0]; + assign viv_s171 = viv_s169[8]; + assign viv_s172 = viv_s169[9]; + assign viv_s173 = viv_s169[10]; + assign viv_s175 = viv_s174 | viv_s232[5]; + vsisp_marvin_mi_dpsbe #(11) u_cr_buf4 + ( + .clk (clk), + .reset_n (reset_n), + .soft_rst (soft_rst), + .dpsbe_data_i (viv_s169), + .dpsbe_val_i (viv_s168), + .dpsbe_ack_o (viv_s174), + .dpsbe_data_o (viv_s161), + .dpsbe_val_o (viv_s160), + .dpsbe_ack_i (viv_s167) + ); + assign viv_s162 = viv_s161[7:0]; + assign viv_s163 = viv_s161[8]; + assign viv_s164 = viv_s161[9]; + assign viv_s165 = viv_s161[10]; + assign viv_s167 = viv_s166 | viv_s232[4]; + vsisp_marvin_mi_dpsbe #(11) u_cr_buf3 + ( + .clk (clk), + .reset_n (reset_n), + .soft_rst (soft_rst), + .dpsbe_data_i (viv_s161), + .dpsbe_val_i (viv_s160), + .dpsbe_ack_o (viv_s166), + .dpsbe_data_o (viv_s153), + .dpsbe_val_o (viv_s152), + .dpsbe_ack_i (viv_s159) + ); + assign viv_s154 = viv_s153[7:0]; + assign viv_s155 = viv_s153[8]; + assign viv_s156 = viv_s153[9]; + assign viv_s157 = viv_s153[10]; + assign viv_s159 = viv_s158 | viv_s232[3]; + vsisp_marvin_mi_dpsbe #(11) u_cr_buf2 + ( + .clk (clk), + .reset_n (reset_n), + .soft_rst (soft_rst), + .dpsbe_data_i (viv_s153), + .dpsbe_val_i (viv_s152), + .dpsbe_ack_o (viv_s158), + .dpsbe_data_o (viv_s145), + .dpsbe_val_o (viv_s144), + .dpsbe_ack_i (viv_s151) + ); + assign viv_s146 = viv_s145[7:0]; + assign viv_s147 = viv_s145[8]; + assign viv_s148 = viv_s145[9]; + assign viv_s149 = viv_s145[10]; + assign viv_s151 = viv_s150 | viv_s232[2]; + vsisp_marvin_mi_dpsbe #(11) u_cr_buf1 + ( + .clk (clk), + .reset_n (reset_n), + .soft_rst (soft_rst), + .dpsbe_data_i (viv_s145), + .dpsbe_val_i (viv_s144), + .dpsbe_ack_o (viv_s150), + .dpsbe_data_o (viv_s137), + .dpsbe_val_o (viv_s136 ), + .dpsbe_ack_i (viv_s143) + ); + assign viv_s138 = viv_s137[7:0]; + assign viv_s139 = viv_s137[8]; + assign viv_s140 = viv_s137[9]; + assign viv_s141 = viv_s137[10]; + assign viv_s143 = viv_s142 | viv_s232[1]; + vsisp_marvin_mi_dpsbe #(11) u_cr_buf0 + ( + .clk (clk), + .reset_n (reset_n), + .soft_rst (soft_rst), + .dpsbe_data_i (viv_s137), + .dpsbe_val_i (viv_s136), + .dpsbe_ack_o (viv_s142), + .dpsbe_data_o (viv_s130), + .dpsbe_val_o (viv_s129), + .dpsbe_ack_i (viv_s135) + ); + assign viv_s131 = viv_s130[7:0]; + assign viv_s132 = viv_s130[8]; + assign viv_s133 = viv_s130[9]; + assign viv_s134 = viv_s130[10]; + assign viv_s135 = viv_s232[0]; + vsisp_marvin_mi_dpsbe #(33) u_dp_buf1 + ( + .clk (clk), + .reset_n (reset_n), + .soft_rst (soft_rst), + .dpsbe_data_i ({in_dp_end, in_dp_data}), + .dpsbe_val_i (in_dp_val), + .dpsbe_ack_o (in_dp_ack), + .dpsbe_data_o (viv_s200), + .dpsbe_val_o (viv_s197), + .dpsbe_ack_i (viv_s205) + ); + assign viv_s199 = viv_s200[31:0]; + assign viv_s201 = viv_s200[32]; + assign viv_s205 = viv_s198 | viv_s202[1]; + vsisp_marvin_mi_dpsbe #(33) u_dp_buf0 + ( + .clk (clk), + .reset_n (reset_n), + .soft_rst (soft_rst), + .dpsbe_data_i (viv_s200), + .dpsbe_val_i (viv_s197), + .dpsbe_ack_o (viv_s198), + .dpsbe_data_o (viv_s195), + .dpsbe_val_o (viv_s192), + .dpsbe_ack_i (viv_s193) + ); + assign viv_s194 = viv_s195[31:0]; + assign viv_s196 = viv_s195[32]; + assign viv_s193 = viv_s202[0]; + always @ (*) begin + out_y_fifo_data = 64'h0; + out_y_fifo_h_end = 1'b0; + out_y_fifo_v_end = 1'b0; + viv_s238 = 1'b0; + out_cb_fifo_data = 64'h0; + out_cb_fifo_h_end = 1'b0; + out_cb_fifo_v_end = 1'b0; + viv_s239 = 1'b0; + out_cr_fifo_data = 64'h0; + out_cr_fifo_h_end = 1'b0; + out_cr_fifo_v_end = 1'b0; + viv_s240 = 1'b0; + out_y_fifo_write64 = 1'b0; + out_cb_fifo_write64 = 1'b0; + out_cr_fifo_write64 = 1'b0; + viv_s206 = 1'b0; + viv_s207 = 1'b0; + viv_s208 = 1'b0; + viv_s209 = 1'b0; + viv_s210 = 1'b0; + viv_s211 = 1'b0; + viv_s212 = 1'b0; + viv_s213 = 1'b0; + viv_s215 = 1'b0; + viv_s216 = 1'b0; + viv_s217 = 1'b0; + viv_s218 = 1'b0; + viv_s219 = 1'b0; + viv_s220 = 1'b0; + viv_s221 = 1'b0; + viv_s222 = 1'b0; + viv_s224 = 1'b0; + viv_s225 = 1'b0; + viv_s226 = 1'b0; + viv_s227 = 1'b0; + viv_s228 = 1'b0; + viv_s229 = 1'b0; + viv_s230 = 1'b0; + viv_s231 = 1'b0; + viv_s204 = 1'b0; + viv_s203 = 1'b0; + viv_s214 = 8'b0000; + viv_s223 = 8'b0000; + viv_s232 = 8'b0000; + viv_s202 = 2'b0; + in_jpeg_ack = 1'b0; + case (path_sel) + 4'b1_110: begin + viv_s213 = viv_s1 & viv_s4 & (viv_s5 | line_sens | slice_offset_sens_y); + viv_s212 = viv_s1 & viv_s8 & + ~viv_s14 & + viv_s11 & (viv_s12 | line_sens | slice_offset_sens_y); + viv_s211 = viv_s1 & viv_s8 & viv_s16 & + ~viv_s14 & ~viv_s22 & + viv_s19 & (viv_s20 | line_sens | slice_offset_sens_y); + viv_s210 = viv_s1 & viv_s8 & viv_s16 & viv_s24 & + ~viv_s14 & ~viv_s22 & ~viv_s30 & + viv_s27 & (viv_s28 | line_sens | slice_offset_sens_y); + viv_s209 = viv_s1 & viv_s8 & viv_s16 & viv_s24 & + viv_s32 & + ~viv_s14 & ~viv_s22 & ~viv_s30 & ~viv_s38 & + viv_s35 & (viv_s36 | line_sens | slice_offset_sens_y); + viv_s208 = viv_s1 & viv_s8 & viv_s16 & viv_s24 & + viv_s32 & viv_s40 & + ~viv_s14 & ~viv_s22 & ~viv_s30 & ~viv_s38 & + ~viv_s46 & + viv_s43 & (viv_s44 | line_sens | slice_offset_sens_y); + viv_s207 = viv_s1 & viv_s8 & viv_s16 & viv_s24 & + viv_s32 & viv_s40 & viv_s48 & + ~viv_s14 & ~viv_s22 & ~viv_s30 & ~viv_s38 & + ~viv_s46 & ~viv_s54 & + viv_s51 & (viv_s52 | line_sens | slice_offset_sens_y); + viv_s206 = viv_s1 & viv_s8 & viv_s16 & viv_s24 & + viv_s32 & viv_s40 & viv_s48 & viv_s56 & + ~viv_s14 & ~viv_s22 & ~viv_s30 & ~viv_s38 & + ~viv_s46 & ~viv_s54 & ~viv_s62; + if (viv_s213 & ~out_y_fifo_full) begin + out_y_fifo_data = {8'h00, 8'h00, 8'h00, 8'h00, + 8'h00, 8'h00, 8'h00, viv_s3}; + out_y_fifo_h_end = viv_s4; + out_y_fifo_v_end = viv_s5; + viv_s238 = viv_s6; + out_y_fifo_write64 = 1'b1; + viv_s214 = 8'b00000001; + end + else if (viv_s212 & ~out_y_fifo_full) begin + out_y_fifo_data = {8'h00, 8'h00, 8'h00, 8'h00, + 8'h00, 8'h00, viv_s10, viv_s3}; + out_y_fifo_h_end = viv_s11; + out_y_fifo_v_end = viv_s12; + viv_s238 = viv_s13; + out_y_fifo_write64 = 1'b1; + viv_s214 = 8'b00000011; + end + else if (viv_s211 & ~out_y_fifo_full) begin + out_y_fifo_data = {8'h00, 8'h00, 8'h00, 8'h00, + 8'h00, viv_s18, viv_s10, viv_s3}; + out_y_fifo_h_end = viv_s19; + out_y_fifo_v_end = viv_s20; + viv_s238 = viv_s21; + out_y_fifo_write64 = 1'b1; + viv_s214 = 8'b00000111; + end + else if (viv_s210 & ~out_y_fifo_full) begin + out_y_fifo_data = {8'h00, 8'h00, 8'h00, 8'h00, + viv_s26, viv_s18, viv_s10, viv_s3}; + out_y_fifo_h_end = viv_s27; + out_y_fifo_v_end = viv_s28; + viv_s238 = viv_s29; + out_y_fifo_write64 = 1'b1; + viv_s214 = 8'b00001111; + end + else if (viv_s209 & ~out_y_fifo_full) begin + out_y_fifo_data = {8'h00, 8'h00, 8'h00, viv_s34, + viv_s26, viv_s18, viv_s10, viv_s3}; + out_y_fifo_h_end = viv_s35; + out_y_fifo_v_end = viv_s36; + viv_s238 = viv_s37; + out_y_fifo_write64 = 1'b1; + viv_s214 = 8'b00011111; + end + else if (viv_s208 & ~out_y_fifo_full) begin + out_y_fifo_data = {8'h00, 8'h00, viv_s42, viv_s34, + viv_s26, viv_s18, viv_s10, viv_s3}; + out_y_fifo_h_end = viv_s43; + out_y_fifo_v_end = viv_s44; + viv_s238 = viv_s45; + out_y_fifo_write64 = 1'b1; + viv_s214 = 8'b00111111; + end + else if (viv_s207 & ~out_y_fifo_full) begin + out_y_fifo_data = {8'h00, viv_s50, viv_s42, viv_s34, + viv_s26, viv_s18, viv_s10, viv_s3}; + out_y_fifo_h_end = viv_s51; + out_y_fifo_v_end = viv_s52; + viv_s238 = viv_s53; + out_y_fifo_write64 = 1'b1; + viv_s214 = 8'b01111111; + end + else if (viv_s206 & ~out_y_fifo_full) begin + out_y_fifo_data = {viv_s58, viv_s50, viv_s42, viv_s34, + viv_s26, viv_s18, viv_s10, viv_s3}; + out_y_fifo_h_end = viv_s59; + out_y_fifo_v_end = viv_s60; + viv_s238 = viv_s61; + out_y_fifo_write64 = 1'b1; + viv_s214 = 8'b11111111; + end + viv_s223 = 8'b00000001; + viv_s232 = 8'b00000001; + end + 4'b1_101: begin + viv_s206 = viv_s1 & viv_s65 & viv_s8 & viv_s72 & + viv_s16 & viv_s80 & viv_s24 & viv_s88 & + ~viv_s14 & ~viv_s78 & ~viv_s22 & ~viv_s86 & + ~viv_s30 & ~viv_s94; + if (viv_s206 & ~out_y_fifo_full) begin + out_y_fifo_data = {viv_s26, viv_s90, viv_s18, viv_s82, + viv_s10, viv_s74, viv_s3, viv_s67}; + out_y_fifo_h_end = viv_s27; + out_y_fifo_v_end = viv_s28; + viv_s238 = viv_s29; + out_y_fifo_write64 = 1'b1; + viv_s214 = 8'b1111; + viv_s223 = 8'b1111; + end + end + 4'b1_100: begin + viv_s208 = viv_s1 & viv_s65 & viv_s129 & + viv_s8 & viv_s72 & viv_s136 & + ~viv_s14 & ~viv_s78 & ~viv_s142; + if (viv_s208 & ~out_y_fifo_full) begin + out_y_fifo_data = {8'h00, viv_s10, viv_s74, viv_s138, + 8'h00, viv_s3, viv_s67, viv_s131}; + out_y_fifo_h_end = viv_s11; + out_y_fifo_v_end = viv_s12; + viv_s238 = viv_s13; + out_y_fifo_write64 = 1'b1; + viv_s214 = 8'b0011; + viv_s223 = 8'b0011; + viv_s232 = 8'b0011; + end + end + 4'b1_011: begin + out_y_fifo_data = in_jpeg_data; + out_y_fifo_h_end = in_jpeg_end; + out_y_fifo_v_end = in_jpeg_end; + out_y_fifo_write64 = in_jpeg_val && ~viv_s233; + in_jpeg_ack = ~out_y_fifo_full && ~viv_s233; + end + 4'b0_001: begin + viv_s203 = viv_s192 & viv_s196; + viv_s204 = viv_s197 & viv_s192 & ~viv_s198; + if (viv_s203 & ~out_y_fifo_full) begin + out_y_fifo_data = {32'b0,viv_s194}; + out_y_fifo_h_end = viv_s196; + out_y_fifo_v_end = viv_s196; + out_y_fifo_write64 = 1'b1; + viv_s202 = 2'b01; + end + else if (viv_s204 & ~out_y_fifo_full) begin + out_y_fifo_data = {viv_s199,viv_s194}; + out_y_fifo_h_end = viv_s201; + out_y_fifo_v_end = viv_s201; + out_y_fifo_write64 = 1'b1; + viv_s202 = 2'b11; + end + end + 4'b1_111, 4'b1_010: begin + viv_s212 = viv_s1 & viv_s65 & + viv_s4 & + (viv_s5 | line_sens | slice_offset_sens_y); + viv_s210 = viv_s1 & viv_s65 & viv_s8 & viv_s129 & + ~viv_s14 & + viv_s11 & (viv_s12 | line_sens | slice_offset_sens_y); + viv_s208 = viv_s1 & viv_s65 & viv_s8 & viv_s129 & + viv_s16 & viv_s72 & + ~viv_s22 & ~viv_s14 & ~viv_s78 & + viv_s19 & (viv_s20 | line_sens | slice_offset_sens_y); + viv_s206 = viv_s1 & viv_s65 & viv_s8 & viv_s129 & + viv_s16 & viv_s72 & viv_s24 & viv_s136 & + ~viv_s30 & ~viv_s22 & ~viv_s14 & ~viv_s78 & ~viv_s142; + if (viv_s212 & ~out_y_fifo_full) begin + out_y_fifo_data = {8'h00, 8'h00, 8'h00, 8'h00, + 8'h00, 8'h00, viv_s67, viv_s3}; + out_y_fifo_h_end = viv_s4; + out_y_fifo_v_end = viv_s5; + viv_s238 = viv_s6; + out_y_fifo_write64 = 1'b1; + viv_s214 = 8'b0001; + viv_s223 = 8'b0001; + end + else if (viv_s210 & ~out_y_fifo_full) begin + out_y_fifo_data = {8'h00, 8'h00, 8'h00, 8'h00, + viv_s131, viv_s10, viv_s67, viv_s3}; + out_y_fifo_h_end = viv_s11; + out_y_fifo_v_end = viv_s12; + viv_s238 = viv_s13; + out_y_fifo_write64 = 1'b1; + viv_s214 = 8'b0011; + viv_s223 = 8'b0001; + viv_s232 = 8'b0001; + end + else if (viv_s208 & ~out_y_fifo_full) begin + out_y_fifo_data = {8'h00, 8'h00, viv_s74, viv_s18, + viv_s131, viv_s10, viv_s67, viv_s3}; + out_y_fifo_h_end = viv_s19; + out_y_fifo_v_end = viv_s20; + viv_s238 = viv_s21; + out_y_fifo_write64 = 1'b1; + viv_s214 = 8'b0111; + viv_s223 = 8'b0011; + viv_s232 = 8'b0001; + end + else if (viv_s206 & ~out_y_fifo_full) begin + out_y_fifo_data = {viv_s138, viv_s26, viv_s74, viv_s18, + viv_s131, viv_s10, viv_s67, viv_s3}; + out_y_fifo_h_end = viv_s27; + out_y_fifo_v_end = viv_s28; + viv_s238 = viv_s29; + out_y_fifo_write64 = 1'b1; + viv_s214 = 8'b1111; + viv_s223 = 8'b0011; + viv_s232 = 8'b0011; + end + end + 4'b1_001: begin + viv_s213 = viv_s1 & + viv_s4 & (viv_s5 | line_sens | slice_offset_sens_y); + viv_s212 = viv_s1 & viv_s8 & + ~viv_s14 & + viv_s11 & (viv_s12 | line_sens | slice_offset_sens_y); + viv_s211 = viv_s1 & viv_s8 & viv_s16 & + ~viv_s14 & ~viv_s22 & + viv_s19 & (viv_s20 | line_sens | slice_offset_sens_y); + viv_s210 = viv_s1 & viv_s8 & viv_s16 & viv_s24 & + ~viv_s14 & ~viv_s22 & ~viv_s30 & + viv_s27 & (viv_s28 | line_sens | slice_offset_sens_y); + viv_s209 = viv_s1 & viv_s8 & viv_s16 & viv_s24 & viv_s32 & + ~viv_s14 & ~viv_s22 & ~viv_s30 & ~viv_s38 & + viv_s35 & (viv_s36 | line_sens | slice_offset_sens_y); + viv_s208 = viv_s1 & viv_s8 & viv_s16 & viv_s24 & viv_s32 & + viv_s40 & + ~viv_s14 & ~viv_s22 & ~viv_s30 & ~viv_s38 & + ~viv_s46 & + viv_s43 & (viv_s44 | line_sens | slice_offset_sens_y); + viv_s207 = viv_s1 & viv_s8 & viv_s16 & viv_s24 & + viv_s32 & viv_s40 & viv_s48 & + ~viv_s14 & ~viv_s22 & ~viv_s30 & ~viv_s38 & + ~viv_s46 & ~viv_s54 & + viv_s51 & (viv_s52 | line_sens | slice_offset_sens_y); + viv_s206 = viv_s1 & viv_s8 & viv_s16 & viv_s24 & + viv_s32 & viv_s40 & viv_s48 & viv_s56 & + ~viv_s14 & ~viv_s22 & ~viv_s30 & ~viv_s38 & + ~viv_s46 & ~viv_s54 & ~viv_s62; + if (viv_s213 & ~out_y_fifo_full) begin + out_y_fifo_data = {8'h00, 8'h00, 8'h00, 8'h00, + 8'h00, 8'h00, 8'h00, viv_s3}; + out_y_fifo_h_end = viv_s4; + out_y_fifo_v_end = viv_s5; + viv_s238 = viv_s6; + out_y_fifo_write64 = 1'b1; + viv_s214 = 8'b0001; + end + else if (viv_s212 & ~out_y_fifo_full) begin + out_y_fifo_data = {8'h00, 8'h00, 8'h00, 8'h00, + 8'h00, 8'h00, viv_s10, viv_s3}; + out_y_fifo_h_end = viv_s11; + out_y_fifo_v_end = viv_s12; + viv_s238 = viv_s13; + out_y_fifo_write64 = 1'b1; + viv_s214 = 8'b0011; + end + else if (viv_s211 & ~out_y_fifo_full) begin + out_y_fifo_data = {8'h00, 8'h00, 8'h00, 8'h00, + 8'h00, viv_s18, viv_s10, viv_s3}; + out_y_fifo_h_end = viv_s19; + out_y_fifo_v_end = viv_s20; + viv_s238 = viv_s21; + out_y_fifo_write64 = 1'b1; + viv_s214 = 8'b0111; + end + else if (viv_s210 & ~out_y_fifo_full) begin + out_y_fifo_data = {8'h00, 8'h00, 8'h00, 8'h00, + viv_s26, viv_s18, viv_s10, viv_s3}; + out_y_fifo_h_end = viv_s27; + out_y_fifo_v_end = viv_s28; + viv_s238 = viv_s29; + out_y_fifo_write64 = 1'b1; + viv_s214 = 8'b1111; + end + else if (viv_s209 & ~out_y_fifo_full) begin + out_y_fifo_data = {8'h00, 8'h00, 8'h00, viv_s34, + viv_s26, viv_s18, viv_s10, viv_s3}; + out_y_fifo_h_end = viv_s35; + out_y_fifo_v_end = viv_s36; + viv_s238 = viv_s37; + out_y_fifo_write64 = 1'b1; + viv_s214 = 8'b11111; + end + else if (viv_s208 & ~out_y_fifo_full) begin + out_y_fifo_data = {8'h00, 8'h00, viv_s42, viv_s34, + viv_s26, viv_s18, viv_s10, viv_s3}; + out_y_fifo_h_end = viv_s43; + out_y_fifo_v_end = viv_s44; + viv_s238 = viv_s45; + out_y_fifo_write64 = 1'b1; + viv_s214 = 8'b111111; + end + else if (viv_s207 & ~out_y_fifo_full) begin + out_y_fifo_data = {8'h00, viv_s50, viv_s42, viv_s34, + viv_s26, viv_s18, viv_s10, viv_s3}; + out_y_fifo_h_end = viv_s51; + out_y_fifo_v_end = viv_s52; + viv_s238 = viv_s53; + out_y_fifo_write64 = 1'b1; + viv_s214 = 8'b1111111; + end + else if (viv_s206 & ~out_y_fifo_full) begin + out_y_fifo_data = {viv_s58, viv_s50, viv_s42, viv_s34, + viv_s26, viv_s18, viv_s10, viv_s3}; + out_y_fifo_h_end = viv_s59 | viv_s51 | viv_s43 | viv_s35 | + viv_s27 | viv_s19 | viv_s11 | viv_s4; + out_y_fifo_v_end = viv_s5; + viv_s238 = viv_s61; + out_y_fifo_write64 = 1'b1; + viv_s214 = 8'b11111111; + end + viv_s221 = viv_s65 & viv_s129 & + viv_s68 & (viv_s69 | line_sens | slice_offset_sens_cb); + viv_s219 = viv_s65 & viv_s129 & viv_s72 & viv_s136 & + ~viv_s78 & ~viv_s142 & + viv_s75 & (viv_s76 | line_sens | slice_offset_sens_cb); + viv_s217 = viv_s65 & viv_s129 & viv_s72 & viv_s136 & + viv_s80 & viv_s144 & + ~viv_s78 & ~viv_s142 & ~viv_s86 & ~viv_s150 & + viv_s83 & (viv_s84 | line_sens | slice_offset_sens_cb); + viv_s215 = viv_s65 & viv_s129 & viv_s72 & viv_s136 & + viv_s80 & viv_s144 & viv_s88 & viv_s152 & + ~viv_s78 & ~viv_s142 & ~viv_s86 & ~viv_s150 & + ~viv_s94 & ~viv_s158; + if (viv_s221 & ~out_cb_fifo_full) begin + if (nv21) begin + out_cb_fifo_data = {8'h00, 8'h00, 8'h00, 8'h00, + 8'h00, 8'h00, viv_s67, viv_s131}; + end + else begin + out_cb_fifo_data = {8'h00, 8'h00, 8'h00, 8'h00, + 8'h00, 8'h00, viv_s131, viv_s67}; + end + out_cb_fifo_h_end = viv_s68; + out_cb_fifo_v_end = viv_s69; + viv_s239 = viv_s70; + out_cb_fifo_write64 = 1'b1; + viv_s223 = 8'b0001; + viv_s232 = 8'b0001; + end + else if (viv_s219 & ~out_cb_fifo_full) begin + if (nv21) begin + out_cb_fifo_data = {8'h00, 8'h00, 8'h00, 8'h00, + viv_s74, viv_s138, viv_s67, viv_s131}; + end + else begin + out_cb_fifo_data = {8'h00, 8'h00, 8'h00, 8'h00, + viv_s138, viv_s74, viv_s131, viv_s67}; + end + out_cb_fifo_h_end = viv_s139 | viv_s75 | viv_s132 | viv_s68; + out_cb_fifo_v_end = viv_s69; + viv_s239 = viv_s77; + out_cb_fifo_write64 = 1'b1; + viv_s223 = 8'b0011; + viv_s232 = 8'b0011; + end + else if (viv_s217 & ~out_cb_fifo_full) begin + if (nv21) begin + out_cb_fifo_data = {8'h00, 8'h00, viv_s82, viv_s146, + viv_s74, viv_s138, viv_s67, viv_s131}; + end + else begin + out_cb_fifo_data = {8'h00, 8'h00, viv_s146, viv_s82, + viv_s138, viv_s74, viv_s131, viv_s67}; + end + out_cb_fifo_h_end = viv_s147 | viv_s83 | viv_s139 | viv_s75 | + viv_s132 | viv_s68; + out_cb_fifo_v_end = viv_s69; + viv_s239 = viv_s85; + out_cb_fifo_write64 = 1'b1; + viv_s223 = 8'b0111; + viv_s232 = 8'b0111; + end + else if (viv_s215 & ~out_cb_fifo_full) begin + if (nv21) begin + out_cb_fifo_data = {viv_s90, viv_s154, viv_s82, viv_s146, + viv_s74, viv_s138, viv_s67, viv_s131}; + end + else begin + out_cb_fifo_data = {viv_s154, viv_s90, viv_s146, viv_s82, + viv_s138, viv_s74, viv_s131, viv_s67}; + end + out_cb_fifo_h_end = viv_s155 | viv_s91 | viv_s147 | viv_s83 | + viv_s139 | viv_s75 | viv_s132 | viv_s68; + out_cb_fifo_v_end = viv_s69; + viv_s239 = viv_s93; + out_cb_fifo_write64 = 1'b1; + viv_s223 = 8'b1111; + viv_s232 = 8'b1111; + end + end + 4'b1_000: begin + viv_s213 = viv_s1 & + (viv_s4 | viv_s5) & + (viv_s4 | col_sens) & + (viv_s5 | line_sens | slice_offset_sens_y); + viv_s212 = viv_s1 & viv_s8 & + ~viv_s14 & + (viv_s11 | viv_s12) & + (viv_s11 | col_sens) & + (viv_s12 | line_sens | slice_offset_sens_y); + viv_s211 = viv_s1 & viv_s8 & viv_s16 & + ~viv_s14 & ~viv_s22 & + (viv_s19 | viv_s20) & + (viv_s19 | col_sens) & + (viv_s20 | line_sens | slice_offset_sens_y); + viv_s210 = viv_s1 & viv_s8 & viv_s16 & viv_s24 & + ~viv_s14 & ~viv_s22 & ~viv_s30 & + (viv_s27 | viv_s28) & + (viv_s27 | col_sens) & + (viv_s28 | line_sens | slice_offset_sens_y); + viv_s209 = viv_s1 & viv_s8 & viv_s16 & viv_s24 & + viv_s32 & + ~viv_s14 & ~viv_s22 & ~viv_s30 & ~viv_s38 & + (viv_s35 | viv_s36) & + (viv_s35 | col_sens) & + (viv_s36 | line_sens | slice_offset_sens_y); + viv_s208 = viv_s1 & viv_s8 & viv_s16 & viv_s24 & + viv_s32 & viv_s40 & + ~viv_s14 & ~viv_s22 & ~viv_s30 & ~viv_s38 & + ~viv_s46 & + (viv_s43 | viv_s44) & + (viv_s43 | col_sens) & + (viv_s44 | line_sens | slice_offset_sens_y); + viv_s207 = viv_s1 & viv_s8 & viv_s16 & viv_s24 & + viv_s32 & viv_s40 & viv_s48 & + ~viv_s14 & ~viv_s22 & ~viv_s30 & ~viv_s38 & + ~viv_s46 & ~viv_s54 & + (viv_s51 | viv_s52) & + (viv_s51 | col_sens) & + (viv_s52 | line_sens | slice_offset_sens_y); + viv_s206 = viv_s1 & viv_s8 & viv_s16 & viv_s24 & + viv_s32 & viv_s40 & viv_s48 & viv_s56 & + ~viv_s14 & ~viv_s22 & ~viv_s30 & ~viv_s38 & + ~viv_s46 & ~viv_s54 & ~viv_s62; + if (viv_s213 & ~out_y_fifo_full) begin + out_y_fifo_data = {8'b00, 8'h00, 8'h00, 8'h00, + 8'h00, 8'h00, 8'h00, viv_s3}; + out_y_fifo_h_end = viv_s4; + out_y_fifo_v_end = viv_s5; + viv_s238 = viv_s6; + out_y_fifo_write64 = 1'b1; + viv_s214 = 8'b0001; + end + else if (viv_s212 & ~out_y_fifo_full) begin + out_y_fifo_data = {8'b00, 8'h00, 8'h00, 8'h00, + 8'h00, 8'h00, viv_s10, viv_s3}; + out_y_fifo_h_end = viv_s11; + out_y_fifo_v_end = viv_s12; + viv_s238 = viv_s13; + out_y_fifo_write64 = 1'b1; + viv_s214 = 8'b0011; + end + else if (viv_s211 & ~out_y_fifo_full) begin + out_y_fifo_data = {8'b00, 8'h00, 8'h00, 8'h00, + 8'h00, viv_s18, viv_s10, viv_s3}; + out_y_fifo_h_end = viv_s19; + out_y_fifo_v_end = viv_s20; + viv_s238 = viv_s21; + out_y_fifo_write64 = 1'b1; + viv_s214 = 8'b0111; + end + else if (viv_s210 & ~out_y_fifo_full) begin + out_y_fifo_data = {8'b00, 8'h00, 8'h00, 8'h00, + viv_s26, viv_s18, viv_s10, viv_s3}; + out_y_fifo_h_end = viv_s27; + out_y_fifo_v_end = viv_s28; + viv_s238 = viv_s29; + out_y_fifo_write64 = 1'b1; + viv_s214 = 8'b1111; + end + else if (viv_s209 & ~out_y_fifo_full) begin + out_y_fifo_data = {8'b00, 8'h00, 8'h00, viv_s34, + viv_s26, viv_s18, viv_s10, viv_s3}; + out_y_fifo_h_end = viv_s35; + out_y_fifo_v_end = viv_s36; + viv_s238 = viv_s37; + out_y_fifo_write64 = 1'b1; + viv_s214 = 8'b11111; + end + else if (viv_s208 & ~out_y_fifo_full) begin + out_y_fifo_data = {8'b00, 8'h00, viv_s42, viv_s34, + viv_s26, viv_s18, viv_s10, viv_s3}; + out_y_fifo_h_end = viv_s43; + out_y_fifo_v_end = viv_s44; + viv_s238 = viv_s45; + out_y_fifo_write64 = 1'b1; + viv_s214 = 8'b111111; + end + else if (viv_s207 & ~out_y_fifo_full) begin + out_y_fifo_data = {8'b00, viv_s50, viv_s42, viv_s34, + viv_s26, viv_s18, viv_s10, viv_s3}; + out_y_fifo_h_end = viv_s51; + out_y_fifo_v_end = viv_s52; + viv_s238 = viv_s53; + out_y_fifo_write64 = 1'b1; + viv_s214 = 8'b1111111; + end + else if (viv_s206 & ~out_y_fifo_full) begin + out_y_fifo_data = {viv_s58, viv_s50, viv_s42, viv_s34, + viv_s26, viv_s18, viv_s10, viv_s3}; + out_y_fifo_h_end = viv_s59 | viv_s51 | viv_s43 | viv_s35 | + viv_s27 | viv_s19 | viv_s11 | viv_s4; + out_y_fifo_v_end = (viv_s59 | col_sens) & viv_s60; + viv_s238 = viv_s61; + out_y_fifo_write64 = 1'b1; + viv_s214 = 8'b11111111; + end + viv_s222 = viv_s65 & + (viv_s68 | viv_s69) & + (viv_s68 | col_sens) & + (viv_s69 | line_sens | slice_offset_sens_cb); + viv_s221 = viv_s65 & viv_s72 & + ~viv_s78 & + (viv_s75 | viv_s76) & + (viv_s75 | col_sens) & + (viv_s76 | line_sens | slice_offset_sens_cb); + viv_s220 = viv_s65 & viv_s72 & viv_s80 & + ~viv_s78 & ~viv_s86 & + (viv_s83 | viv_s84) & + (viv_s83 | col_sens) & + (viv_s84 | line_sens | slice_offset_sens_cb); + viv_s219 = viv_s65 & viv_s72 & viv_s80 & viv_s88 & + ~viv_s78 & ~viv_s86 & ~viv_s94 & + (viv_s91 | viv_s92) & + (viv_s91 | col_sens) & + (viv_s92 | line_sens | slice_offset_sens_cb); + viv_s218 = viv_s65 & viv_s72 & viv_s80 & viv_s88 & + viv_s96 & + ~viv_s78 & ~viv_s86 & ~viv_s94 & ~viv_s102 & + (viv_s99 | viv_s100) & + (viv_s99 | col_sens) & + (viv_s100 | line_sens | slice_offset_sens_cb); + viv_s217 = viv_s65 & viv_s72 & viv_s80 & viv_s88 & + viv_s96 & viv_s104 & + ~viv_s78 & ~viv_s86 & ~viv_s94 & ~viv_s102 & + ~viv_s110 & + (viv_s107 | viv_s108) & + (viv_s107 | col_sens) & + (viv_s108 | line_sens | slice_offset_sens_cb); + viv_s216 = viv_s65 & viv_s72 & viv_s80 & viv_s88 & + viv_s96 & viv_s104 & viv_s112 & + ~viv_s78 & ~viv_s86 & ~viv_s94 & ~viv_s102 & + ~viv_s110 & ~viv_s118 & + (viv_s115 | viv_s116) & + (viv_s115 | col_sens) & + (viv_s116 | line_sens | slice_offset_sens_cb); + viv_s215 = viv_s65 & viv_s72 & viv_s80 & viv_s88 & + viv_s96 & viv_s104 & viv_s112 & viv_s120 & + ~viv_s78 & ~viv_s86 & ~viv_s94 & ~viv_s102 & + ~viv_s110 & ~viv_s118 & ~viv_s126; + if (viv_s222 & ~out_cb_fifo_full) begin + out_cb_fifo_data = {8'h00, 8'h00, 8'h00, 8'h00, + 8'h00, 8'h00, 8'h00, viv_s67}; + out_cb_fifo_h_end = viv_s68; + out_cb_fifo_v_end = viv_s69; + viv_s239 = viv_s70; + out_cb_fifo_write64 = 1'b1; + viv_s223 = 8'b0001; + end + else if (viv_s221 & ~out_cb_fifo_full) begin + out_cb_fifo_data = {8'h00, 8'h00, 8'h00, 8'h00, + 8'h00, 8'h00, viv_s74, viv_s67}; + out_cb_fifo_h_end = viv_s75; + out_cb_fifo_v_end = viv_s76; + viv_s239 = viv_s77; + out_cb_fifo_write64 = 1'b1; + viv_s223 = 8'b0011; + end + else if (viv_s220 & ~out_cb_fifo_full) begin + out_cb_fifo_data = {8'h00, 8'h00, 8'h00, 8'h00, + 8'h00, viv_s82, viv_s74, viv_s67}; + out_cb_fifo_h_end = viv_s83; + out_cb_fifo_v_end = viv_s84; + viv_s239 = viv_s85; + out_cb_fifo_write64 = 1'b1; + viv_s223 = 8'b0111; + end + else if (viv_s219 & ~out_cb_fifo_full) begin + out_cb_fifo_data = {8'h00, 8'h00, 8'h00, 8'h00, + viv_s90, viv_s82, viv_s74, viv_s67}; + out_cb_fifo_h_end = viv_s91; + out_cb_fifo_v_end = viv_s92; + viv_s239 = viv_s93; + out_cb_fifo_write64 = 1'b1; + viv_s223 = 8'b1111; + end + else if (viv_s218 & ~out_cb_fifo_full) begin + out_cb_fifo_data = {8'h00, 8'h00, 8'h00, viv_s98, + viv_s90, viv_s82, viv_s74, viv_s67}; + out_cb_fifo_h_end = viv_s99; + out_cb_fifo_v_end = viv_s100; + viv_s239 = viv_s101; + out_cb_fifo_write64 = 1'b1; + viv_s223 = 8'b11111; + end + else if (viv_s217 & ~out_cb_fifo_full) begin + out_cb_fifo_data = {8'h00, 8'h00, viv_s106, viv_s98, + viv_s90, viv_s82, viv_s74, viv_s67}; + out_cb_fifo_h_end = viv_s107; + out_cb_fifo_v_end = viv_s108; + viv_s239 = viv_s109; + out_cb_fifo_write64 = 1'b1; + viv_s223 = 8'b111111; + end + else if (viv_s216 & ~out_cb_fifo_full) begin + out_cb_fifo_data = {8'h00, viv_s114, viv_s106, viv_s98, + viv_s90, viv_s82, viv_s74, viv_s67}; + out_cb_fifo_h_end = viv_s115; + out_cb_fifo_v_end = viv_s116; + viv_s239 = viv_s117; + out_cb_fifo_write64 = 1'b1; + viv_s223 = 8'b1111111; + end + else if (viv_s215 & ~out_cb_fifo_full) begin + out_cb_fifo_data = {viv_s122, viv_s114, viv_s106, viv_s98, + viv_s90, viv_s82, viv_s74, viv_s67}; + out_cb_fifo_h_end = viv_s123 | viv_s115 | viv_s107 | viv_s99 | + viv_s91 | viv_s83 | viv_s75 | viv_s68 ; + out_cb_fifo_v_end = (viv_s123 | col_sens) & viv_s124; + viv_s239 = viv_s125; + out_cb_fifo_write64 = 1'b1; + viv_s223 = 8'b11111111; + end + viv_s231 = viv_s129 & + (viv_s132 | viv_s133) & + (viv_s132 | col_sens) & + (viv_s133 | line_sens | slice_offset_sens_cr); + viv_s230 = viv_s129 & viv_s136 & + ~viv_s142 & + (viv_s139 | viv_s140) & + (viv_s139 | col_sens) & + (viv_s140 | line_sens | slice_offset_sens_cr); + viv_s229 = viv_s129 & viv_s136 & viv_s144 & + ~viv_s142 & ~viv_s150 & + (viv_s147 | viv_s148) & + (viv_s147 | col_sens) & + (viv_s148 | line_sens | slice_offset_sens_cr); + viv_s228 = viv_s129 & viv_s136 & viv_s144 & viv_s152 & + ~viv_s142 & ~viv_s150 & ~viv_s158 & + (viv_s155 | viv_s156) & + (viv_s155 | col_sens) & + (viv_s156 | line_sens | slice_offset_sens_cr); + viv_s227 = viv_s129 & viv_s136 & viv_s144 & viv_s152 & + viv_s160 & + ~viv_s142 & ~viv_s150 & ~viv_s158 & ~viv_s166 & + (viv_s163 | viv_s164) & + (viv_s163 | col_sens) & + (viv_s164 | line_sens | slice_offset_sens_cr); + viv_s226 = viv_s129 & viv_s136 & viv_s144 & viv_s152 & + viv_s160 & viv_s168 & + ~viv_s142 & ~viv_s150 & ~viv_s158 & ~viv_s166 & + ~viv_s174 & + (viv_s171 | viv_s172) & + (viv_s171 | col_sens) & + (viv_s172 | line_sens | slice_offset_sens_cr); + viv_s225 = viv_s129 & viv_s136 & viv_s144 & viv_s152 & + viv_s160 & viv_s168 & viv_s176 & + ~viv_s142 & ~viv_s150 & ~viv_s158 & ~viv_s166 & + ~viv_s174 & ~viv_s182 & + (viv_s179 | viv_s180) & + (viv_s179 | col_sens) & + (viv_s180 | line_sens | slice_offset_sens_cr); + viv_s224 = viv_s129 & viv_s136 & viv_s144 & viv_s152 & + viv_s160 & viv_s168 & viv_s176 & viv_s184 & + ~viv_s142 & ~viv_s150 & ~viv_s158 & ~viv_s166 & + ~viv_s174 & ~viv_s182 & ~viv_s190; + if (viv_s231 & ~out_cr_fifo_full) begin + out_cr_fifo_data = {8'h00, 8'h00, 8'h00, 8'h00, + 8'h00, 8'h00, 8'h00, viv_s131}; + out_cr_fifo_h_end = viv_s132; + out_cr_fifo_v_end = viv_s133; + viv_s240 = viv_s134; + out_cr_fifo_write64 = 1'b1; + viv_s232 = 8'b0001; + end + else if (viv_s230 & ~out_cr_fifo_full) begin + out_cr_fifo_data = {8'h00, 8'h00, 8'h00, 8'h00, + 8'h00, 8'h00, viv_s138, viv_s131}; + out_cr_fifo_h_end = viv_s139; + out_cr_fifo_v_end = viv_s140; + viv_s240 = viv_s141; + out_cr_fifo_write64 = 1'b1; + viv_s232 = 8'b0011; + end + else if (viv_s229 & ~out_cr_fifo_full) begin + out_cr_fifo_data = {8'h00, 8'h00, 8'h00, 8'h00, + 8'h00, viv_s146, viv_s138, viv_s131}; + out_cr_fifo_h_end = viv_s147; + out_cr_fifo_v_end = viv_s148; + viv_s240 = viv_s149; + out_cr_fifo_write64 = 1'b1; + viv_s232 = 8'b0111; + end + else if (viv_s228 & ~out_cr_fifo_full) begin + out_cr_fifo_data = {8'h00, 8'h00, 8'h00, 8'h00, + viv_s154, viv_s146, viv_s138, viv_s131}; + out_cr_fifo_h_end = viv_s155; + out_cr_fifo_v_end = viv_s156; + viv_s240 = viv_s157; + out_cr_fifo_write64 = 1'b1; + viv_s232 = 8'b1111; + end + else if (viv_s227 & ~out_cr_fifo_full) begin + out_cr_fifo_data = {8'h00, 8'h00, 8'h00, viv_s162, + viv_s154, viv_s146, viv_s138, viv_s131}; + out_cr_fifo_h_end = viv_s163; + out_cr_fifo_v_end = viv_s164; + viv_s240 = viv_s165; + out_cr_fifo_write64 = 1'b1; + viv_s232 = 8'b11111; + end + else if (viv_s226 & ~out_cr_fifo_full) begin + out_cr_fifo_data = {8'h00, 8'h00, viv_s170, viv_s162, + viv_s154, viv_s146, viv_s138, viv_s131}; + out_cr_fifo_h_end = viv_s171; + out_cr_fifo_v_end = viv_s172; + viv_s240 = viv_s173; + out_cr_fifo_write64 = 1'b1; + viv_s232 = 8'b111111; + end + else if (viv_s225 & ~out_cr_fifo_full) begin + out_cr_fifo_data = {8'h00, viv_s178, viv_s170, viv_s162, + viv_s154, viv_s146, viv_s138, viv_s131}; + out_cr_fifo_h_end = viv_s179; + out_cr_fifo_v_end = viv_s180; + viv_s240 = viv_s181; + out_cr_fifo_write64 = 1'b1; + viv_s232 = 8'b1111111; + end + else if (viv_s224 & ~out_cr_fifo_full) begin + out_cr_fifo_data = {viv_s186, viv_s178, viv_s170, viv_s162, + viv_s154, viv_s146, viv_s138, viv_s131}; + out_cr_fifo_h_end = viv_s187 | viv_s179 | viv_s171 | viv_s163 | + viv_s155 | viv_s147 | viv_s139 | viv_s132; + out_cr_fifo_v_end = (viv_s187 | col_sens) & viv_s188; + viv_s240 = viv_s189; + out_cr_fifo_write64 = 1'b1; + viv_s232 = 8'b11111111; + end + end + 4'b0_101: begin + out_y_fifo_h_end = viv_s1 & viv_s4; + out_y_fifo_v_end = viv_s1 & viv_s5; + viv_s238 = viv_s1 & viv_s6; + out_cb_fifo_h_end = viv_s65 & viv_s68; + out_cb_fifo_v_end = viv_s65 & viv_s69; + viv_s239 = viv_s65 & viv_s70; + out_cr_fifo_h_end = out_cb_fifo_h_end; + out_cr_fifo_v_end = out_cb_fifo_v_end; + viv_s240 = viv_s239; + viv_s214 = 8'b0001; + viv_s223 = 8'b0001; + viv_s232 = 8'b0001; + end + default: begin + out_y_fifo_h_end = viv_s1 & viv_s4; + out_y_fifo_v_end = viv_s1 & viv_s5; + viv_s238 = viv_s1 & viv_s6; + out_cb_fifo_h_end = viv_s65 & viv_s68; + out_cb_fifo_v_end = viv_s65 & viv_s69; + viv_s239 = viv_s65 & viv_s70; + out_cr_fifo_h_end = viv_s129 & viv_s132; + out_cr_fifo_v_end = viv_s129 & viv_s133; + viv_s240 = viv_s129 & viv_s134; + viv_s214 = 8'b0001; + viv_s223 = 8'b0001; + viv_s232 = 8'b0001; + end + endcase + end + always @(posedge clk or negedge reset_n) begin + if (~reset_n) begin + cfg_in_update <= 1'b0; + end + else if (soft_rst) begin + cfg_in_update <= 1'b0; + end + else begin + if ((path_sel == 4'b1_000) || (path_sel[3] == 1'b0)) begin + cfg_in_update <= viv_s235 & viv_s236 & viv_s237; + end + else if (path_sel == 4'b1_001) begin + cfg_in_update <= viv_s235 & viv_s236; + end + else if (path_sel == 4'b1_011) begin + cfg_in_update <= viv_s234; + end + else begin + cfg_in_update <= viv_s235; + end + end + end + always @(posedge clk or negedge reset_n) begin + if (~reset_n) begin + viv_s234 <= 1'b0; + viv_s233 <= 1'b0; + end + else if (soft_rst) begin + viv_s234 <= 1'b0; + viv_s233 <= 1'b0; + end + else begin + if (in_jpeg_ack & out_y_fifo_v_end & auto_update) begin + viv_s234 <= 1'b1; + viv_s233 <= 1'b1; + end + else if (cfg_out_update) begin + viv_s234 <= 1'b0; + viv_s233 <= 1'b0; + end + end + end + always @(posedge clk or negedge reset_n) begin + if (~reset_n) begin + viv_s235 <= 1'b0; + end + else if (soft_rst) begin + viv_s235 <= 1'b0; + end + else begin + if (|viv_s214 & out_y_fifo_h_end & out_y_fifo_v_end & + (viv_s238 || auto_update) ) begin + viv_s235 <= 1'b1; + end + else if (cfg_out_update) begin + viv_s235 <= 1'b0; + end + end + end + always @(posedge clk or negedge reset_n) begin + if (~reset_n) begin + viv_s236 <= 1'b0; + end + else if (soft_rst) begin + viv_s236 <= 1'b0; + end + else begin + if (|viv_s223 & out_cb_fifo_h_end & out_cb_fifo_v_end & + (viv_s239 || auto_update) ) begin + viv_s236 <= 1'b1; + end + else if (cfg_out_update) begin + viv_s236 <= 1'b0; + end + end + end + always @(posedge clk or negedge reset_n) begin + if (~reset_n) begin + viv_s237 <= 1'b0; + end + else if (soft_rst) begin + viv_s237 <= 1'b0; + end + else begin + if (|viv_s232 & out_cr_fifo_h_end & out_cr_fifo_v_end & + (viv_s240 || auto_update) ) begin + viv_s237 <= 1'b1; + end + else if (cfg_out_update) begin + viv_s237 <= 1'b0; + end + end + end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_marvin_mi_out.v b/ispyocto/rtl/ispyocto/vsisp_marvin_mi_out.v new file mode 100644 index 0000000..91e26c3 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_marvin_mi_out.v
@@ -0,0 +1,611 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_marvin_mi_out + ( + m_hclk, + reset_m_hclk_n, + soft_rst_m_hclk, + mp_fifo_read64, + mp_fifo_select, + mp_fifo_data, + mp_fifo_h_end, + mp_fifo_v_end, + sp_fifo_read64, + sp_fifo_select, + sp_fifo_data, + sp_fifo_h_end, + sp_fifo_v_end, + mp_y_fifo_fill_level, + mp_y_fifo_flush, + mp_cb_fifo_fill_level, + mp_cb_fifo_flush, + mp_cr_fifo_fill_level, + mp_cr_fifo_flush, + sp_y_fifo_fill_level, + sp_y_fifo_flush, + sp_cb_fifo_fill_level, + sp_cb_fifo_flush, + sp_cr_fifo_fill_level, + sp_cr_fifo_flush, + soft_upd, + skip, + mp_enable, + sp_enable, + jpeg_enable, + raw_enable, + dp_enable, + h_flip, + v_flip, + rot, + mp_write_format, + sp_write_format, + sp_output_format, + byte_swap, + init_base_en, + init_offset_en, + mp_pingpong_en, + sp_pingpong_en, + burst_len_lum, + burst_len_chrom, + stat_mp_enable_out, + stat_sp_enable_out, + stat_jpeg_enable_out, + stat_raw_enable_out, + stat_dp_enable_out, + mp_y_base_ad, + mp_y_size, + mp_y_offs_cnt, + mp_y_base_ad_init, + mp_y_base_ad_init2, + mp_y_size_init, + mp_y_offs_cnt_init, + mp_y_offs_cnt_start, + mp_y_irq_offs_init, + mp_y_irq_offs, + mp_cb_base_ad, + mp_cb_size, + mp_cb_offs_cnt, + mp_cb_base_ad_init, + mp_cb_base_ad_init2, + mp_cb_size_init, + mp_cb_offs_cnt_init, + mp_cb_offs_cnt_start, + mp_cr_base_ad, + mp_cr_size, + mp_cr_offs_cnt, + mp_cr_base_ad_init, + mp_cr_base_ad_init2, + mp_cr_size_init, + mp_cr_offs_cnt_init, + mp_cr_offs_cnt_start, + sp_y_base_ad, + sp_y_size, + sp_y_offs_cnt, + sp_y_base_ad_init, + sp_y_base_ad_init2, + sp_y_size_init, + sp_y_offs_cnt_init, + sp_y_offs_cnt_start, + sp_y_pic_width, + sp_y_llength, + sp_y_pic_size, + sp_cb_base_ad, + sp_cb_size, + sp_cb_offs_cnt, + sp_cb_base_ad_init, + sp_cb_base_ad_init2, + sp_cb_size_init, + sp_cb_offs_cnt_init, + sp_cb_offs_cnt_start, + sp_cr_base_ad, + sp_cr_size, + sp_cr_offs_cnt, + sp_cr_base_ad_init, + sp_cr_base_ad_init2, + sp_cr_size_init, + sp_cr_offs_cnt_init, + sp_cr_offs_cnt_start, + stat_mp_frame_end, + stat_sp_frame_end, + stat_mblk_line, + stat_fill_mp_y, + stat_wrap_mp_y, + stat_wrap_mp_cb, + stat_wrap_mp_cr, + stat_wrap_sp_y, + stat_wrap_sp_cb, + stat_wrap_sp_cr, + cfg_in_update_mp, + cfg_in_update_sp, + cfg_out_update_mp, + cfg_out_update_sp, + vci_out_m1_cmdval, + vci_out_m1_plen, + vci_out_m1_eop, + vci_out_m1_address, + vci_out_m1_wdata, + vci_out_m1_be, + vci_out_m1_cmd, + vci_out_m1_const, + vci_out_m1_contig, + vci_out_m1_wrap, + vci_out_m1_cmdack, + vci_out_m1_rspval, + vci_out_m1_reop, + vci_out_m1_rspack, + vci_out_m2_cmdval, + vci_out_m2_plen, + vci_out_m2_eop, + vci_out_m2_address, + vci_out_m2_wdata, + vci_out_m2_be, + vci_out_m2_cmd, + vci_out_m2_const, + vci_out_m2_contig, + vci_out_m2_wrap, + vci_out_m2_cmdack, + vci_out_m2_rspval, + vci_out_m2_reop, + vci_out_m2_rspack, + last_pixel_sig_en, + last_pixel_m1_req, + last_pixel_m1_ack, + last_pixel_m2_req, + last_pixel_m2_ack, + mp_y_llength, + mp_output_format, + mp_slice_offset_y, + mp_slice_offset_c, + mp_byte_swap, + sp_byte_swap, + handshake_en, + starage_format, + data_format, + slice_size, + slice_buf_size, + ack_count, + mp_interrupt, + isp_0_ack, + bresp_in, + isp_0_ready, + isp_0_attr, + stat_skip_active, + mp_line_sens, + handshake_mode_0, + slice_cnt_int , + sw_addr_mp_y , + sw_addr_mp_cb , + sw_addr_mp_cr , + sw_interrupt ); +`include "vsisp_marvin_mi.vh" +input mp_line_sens; +output stat_skip_active; +input [3:0] mp_output_format; +input [14:0] mp_y_llength; +input [c_mi_data_addr:0] mp_slice_offset_y; +input [c_mi_data_addr:0] mp_slice_offset_c; +input [2:0] mp_byte_swap; +input [2:0] sp_byte_swap; +input handshake_en; +input [1:0] starage_format; +input [1:0] data_format; +input [7:0] slice_size; +input [7:0] slice_buf_size; +input [7:0] ack_count; +output mp_interrupt; +input isp_0_ack; +input bresp_in; +output isp_0_ready; +output [1:0] isp_0_attr; +input handshake_mode_0; +input [7:0] slice_cnt_int; +output [c_mi_data_addr:0] sw_addr_mp_y; +output [c_mi_data_addr:0] sw_addr_mp_cb; +output [c_mi_data_addr:0] sw_addr_mp_cr; +output sw_interrupt; + input m_hclk; + input reset_m_hclk_n; + input soft_rst_m_hclk; + output mp_fifo_read64; + output [1:0] mp_fifo_select; + input [63:0] mp_fifo_data; + input mp_fifo_h_end; + input mp_fifo_v_end; + output sp_fifo_read64; + output [1:0] sp_fifo_select; + input [63:0] sp_fifo_data; + input sp_fifo_h_end; + input sp_fifo_v_end; + input [c_fifo_depth_bw-1:0] mp_y_fifo_fill_level; + input mp_y_fifo_flush; + input [c_fifo_depth_bw-1:0] mp_cb_fifo_fill_level; + input mp_cb_fifo_flush; + input [c_fifo_depth_bw-1:0] mp_cr_fifo_fill_level; + input mp_cr_fifo_flush; + input [c_fifo_depth_bw-1:0] sp_y_fifo_fill_level; + input sp_y_fifo_flush; + input [c_fifo_depth_bw-1:0] sp_cb_fifo_fill_level; + input sp_cb_fifo_flush; + input [c_fifo_depth_bw-1:0] sp_cr_fifo_fill_level; + input sp_cr_fifo_flush; + input soft_upd; + input skip; + input mp_enable; + input sp_enable; + input jpeg_enable; + input raw_enable; + input [1:0] dp_enable; + input h_flip; + input v_flip; + input rot; + input [1:0] mp_write_format; + input [1:0] sp_write_format; + input [2:0] sp_output_format; + input byte_swap; + input init_base_en; + input init_offset_en; + input mp_pingpong_en; + input sp_pingpong_en; + input [1:0] burst_len_lum; + input [1:0] burst_len_chrom; + output stat_mp_enable_out; + output stat_sp_enable_out; + output stat_jpeg_enable_out; + output stat_raw_enable_out; + output [1:0] stat_dp_enable_out; + input [c_mi_data_addr+3:3] mp_y_base_ad_init; + input [c_mi_data_addr+3:3] mp_y_base_ad_init2; + input [c_mi_data_addr:3] mp_y_size_init; + input [c_mi_data_addr:3] mp_y_offs_cnt_init; + input [c_mi_data_addr:3] mp_y_irq_offs_init; + output [c_mi_data_addr+3:3] mp_y_base_ad; + output [c_mi_data_addr:3] mp_y_size; + output [c_mi_data_addr:3] mp_y_offs_cnt; + output [c_mi_data_addr:3] mp_y_offs_cnt_start; + output [c_mi_data_addr:3] mp_y_irq_offs; + input [c_mi_data_addr+3:3] mp_cb_base_ad_init; + input [c_mi_data_addr+3:3] mp_cb_base_ad_init2; + input [c_mi_data_addr-1:3] mp_cb_size_init; + input [c_mi_data_addr-1:3] mp_cb_offs_cnt_init; + output [c_mi_data_addr+3:3] mp_cb_base_ad; + output [c_mi_data_addr-1:3] mp_cb_size; + output [c_mi_data_addr-1:3] mp_cb_offs_cnt; + output [c_mi_data_addr-1:3] mp_cb_offs_cnt_start; + input [c_mi_data_addr+3:3] mp_cr_base_ad_init; + input [c_mi_data_addr+3:3] mp_cr_base_ad_init2; + input [c_mi_data_addr-1:3] mp_cr_size_init; + input [c_mi_data_addr-1:3] mp_cr_offs_cnt_init; + output [c_mi_data_addr+3:3] mp_cr_base_ad; + output [c_mi_data_addr-1:3] mp_cr_size; + output [c_mi_data_addr-1:3] mp_cr_offs_cnt; + output [c_mi_data_addr-1:3] mp_cr_offs_cnt_start; + input [c_mi_data_addr+3:3] sp_y_base_ad_init; + input [c_mi_data_addr+3:3] sp_y_base_ad_init2; + input [c_mi_data_addr:3] sp_y_size_init; + input [c_mi_data_addr:3] sp_y_offs_cnt_init; + input [14:0] sp_y_pic_width; + input [14:0] sp_y_llength; + input [c_mi_data_addr:0] sp_y_pic_size; + output [c_mi_data_addr+3:3] sp_y_base_ad; + output [c_mi_data_addr:3] sp_y_size; + output [c_mi_data_addr:3] sp_y_offs_cnt; + output [c_mi_data_addr:3] sp_y_offs_cnt_start; + input [c_mi_data_addr+3:3] sp_cb_base_ad_init; + input [c_mi_data_addr+3:3] sp_cb_base_ad_init2; + input [c_mi_data_addr-1:3] sp_cb_size_init; + input [c_mi_data_addr-1:3] sp_cb_offs_cnt_init; + output [c_mi_data_addr+3:3] sp_cb_base_ad; + output [c_mi_data_addr-1:3] sp_cb_size; + output [c_mi_data_addr-1:3] sp_cb_offs_cnt; + output [c_mi_data_addr-1:3] sp_cb_offs_cnt_start; + output [c_mi_data_addr+3:3] sp_cr_base_ad; + output [c_mi_data_addr-1:3] sp_cr_size; + output [c_mi_data_addr-1:3] sp_cr_offs_cnt; + input [c_mi_data_addr+3:3] sp_cr_base_ad_init; + input [c_mi_data_addr+3:3] sp_cr_base_ad_init2; + input [c_mi_data_addr-1:3] sp_cr_size_init; + input [c_mi_data_addr-1:3] sp_cr_offs_cnt_init; + output [c_mi_data_addr-1:3] sp_cr_offs_cnt_start; + output stat_mp_frame_end; + output stat_sp_frame_end; + output stat_mblk_line; + output stat_fill_mp_y; + output stat_wrap_mp_y; + output stat_wrap_mp_cb; + output stat_wrap_mp_cr; + output stat_wrap_sp_y; + output stat_wrap_sp_cb; + output stat_wrap_sp_cr; + input cfg_in_update_mp; + input cfg_in_update_sp; + output cfg_out_update_mp; + output cfg_out_update_sp; + output vci_out_m1_cmdval; + output [8:0] vci_out_m1_plen; + output vci_out_m1_eop; + output [c_mi_data_addr+3:3] vci_out_m1_address; + output [63:0] vci_out_m1_wdata; + output [7:0] vci_out_m1_be; + output [1:0] vci_out_m1_cmd; + output vci_out_m1_const; + output vci_out_m1_contig; + output vci_out_m1_wrap; + input vci_out_m1_cmdack; + input vci_out_m1_rspval; + input vci_out_m1_reop; + output vci_out_m1_rspack; + output vci_out_m2_cmdval; + output [8:0] vci_out_m2_plen; + output vci_out_m2_eop; + output [c_mi_data_addr+3:3] vci_out_m2_address; + output [63:0] vci_out_m2_wdata; + output [7:0] vci_out_m2_be; + output [1:0] vci_out_m2_cmd; + output vci_out_m2_const; + output vci_out_m2_contig; + output vci_out_m2_wrap; + input vci_out_m2_cmdack; + input vci_out_m2_rspval; + input vci_out_m2_reop; + output vci_out_m2_rspack; + output last_pixel_m1_req; + input last_pixel_m1_ack; + input last_pixel_sig_en; + output last_pixel_m2_req; + input last_pixel_m2_ack; + wire [c_mi_data_addr+3:3] viv_s0; + wire [c_mi_data_addr:0] viv_s1; + wire viv_s2; + wire viv_s3; + wire [1:0] viv_s4; + wire stat_skip_active; + wire viv_s5; + wire [c_mi_data_addr:0] viv_s6; + wire [c_mi_data_addr:0] viv_s7; + wire [c_mi_data_addr:0] viv_s8; + wire [c_mi_data_addr:0] sw_addr_mp_y; + wire [c_mi_data_addr:0] sw_addr_mp_cb; + wire [c_mi_data_addr:0] sw_addr_mp_cr; + wire sw_interrupt; + vsisp_marvin_mi_out_mp #(c_bursts_supported, c_burst_len_bw, c_fifo_depth_bw) u_marvin_mi_out_mp + ( + .mp_line_sens (mp_line_sens), + .mp_output_format (mp_output_format), + .mp_y_llength (mp_y_llength), + .mp_byte_swap (mp_byte_swap), + .m_hclk (m_hclk), + .reset_m_hclk_n (reset_m_hclk_n), + .soft_rst_m_hclk (soft_rst_m_hclk), + .mp_fifo_read64 (mp_fifo_read64), + .mp_fifo_select (mp_fifo_select), + .mp_fifo_data (mp_fifo_data), + .mp_fifo_h_end (mp_fifo_h_end), + .mp_fifo_v_end (mp_fifo_v_end), + .mp_y_fifo_fill_level (mp_y_fifo_fill_level), + .mp_y_fifo_flush (mp_y_fifo_flush), + .mp_cb_fifo_fill_level (mp_cb_fifo_fill_level), + .mp_cb_fifo_flush (mp_cb_fifo_flush), + .mp_cr_fifo_fill_level (mp_cr_fifo_fill_level), + .mp_cr_fifo_flush (mp_cr_fifo_flush), + .soft_upd (soft_upd), + .skip (skip), + .mp_enable (mp_enable), + .jpeg_enable (jpeg_enable), + .raw_enable (raw_enable), + .dp_enable (dp_enable[0]), + .mp_write_format (mp_write_format), + .byte_swap (byte_swap), + .init_base_en (init_base_en), + .init_offset_en (init_offset_en), + .mp_pingpong_en (mp_pingpong_en), + .burst_len_lum (burst_len_lum), + .burst_len_chrom (burst_len_chrom), + .stat_mp_enable_out (stat_mp_enable_out), + .stat_jpeg_enable_out (stat_jpeg_enable_out), + .stat_raw_enable_out (stat_raw_enable_out), + .stat_dp_enable_out (stat_dp_enable_out[0]), + .mp_y_base_ad (mp_y_base_ad), + .mp_y_size (mp_y_size), + .mp_y_offs_cnt (mp_y_offs_cnt), + .mp_y_base_ad_init (mp_y_base_ad_init), + .mp_y_base_ad_init2 (mp_y_base_ad_init2), + .mp_y_size_init (mp_y_size_init), + .mp_y_offs_cnt_init (mp_y_offs_cnt_init), + .mp_y_offs_cnt_start (mp_y_offs_cnt_start), + .mp_y_irq_offs_init (mp_y_irq_offs_init), + .mp_y_irq_offs (mp_y_irq_offs), + .mp_cb_base_ad (mp_cb_base_ad), + .mp_cb_size (mp_cb_size), + .mp_cb_offs_cnt (mp_cb_offs_cnt), + .mp_cb_base_ad_init (mp_cb_base_ad_init), + .mp_cb_base_ad_init2 (mp_cb_base_ad_init2), + .mp_cb_size_init (mp_cb_size_init), + .mp_cb_offs_cnt_init (mp_cb_offs_cnt_init), + .mp_cb_offs_cnt_start (mp_cb_offs_cnt_start), + .mp_cr_base_ad (mp_cr_base_ad), + .mp_cr_size (mp_cr_size), + .mp_cr_offs_cnt (mp_cr_offs_cnt), + .mp_cr_base_ad_init (mp_cr_base_ad_init), + .mp_cr_base_ad_init2 (mp_cr_base_ad_init2), + .mp_cr_size_init (mp_cr_size_init), + .mp_cr_offs_cnt_init (mp_cr_offs_cnt_init), + .mp_cr_offs_cnt_start (mp_cr_offs_cnt_start), + .mp_addr_cur_y (viv_s6 ), + .mp_addr_cur_cb (viv_s7 ), + .mp_addr_cur_cr (viv_s8 ), + .handshake_en (handshake_en ), + .stat_mp_frame_end (stat_mp_frame_end), + .stat_mblk_line (stat_mblk_line), + .stat_fill_mp_y (stat_fill_mp_y), + .stat_wrap_mp_y (stat_wrap_mp_y), + .stat_wrap_mp_cb (stat_wrap_mp_cb), + .stat_wrap_mp_cr (stat_wrap_mp_cr), + .cfg_in_update_mp (cfg_in_update_mp), + .cfg_out_update_mp (cfg_out_update_mp), + .vci_out_m1_cmdval (vci_out_m1_cmdval), + .vci_out_m1_plen (vci_out_m1_plen), + .vci_out_m1_eop (vci_out_m1_eop), + .vci_out_m1_address (viv_s0), + .vci_out_m1_wdata (vci_out_m1_wdata), + .vci_out_m1_be (vci_out_m1_be), + .vci_out_m1_cmd (vci_out_m1_cmd), + .vci_out_m1_const (vci_out_m1_const), + .vci_out_m1_contig (vci_out_m1_contig), + .vci_out_m1_wrap (vci_out_m1_wrap), + .vci_out_m1_cmdack (vci_out_m1_cmdack), + .vci_out_m1_rspval (vci_out_m1_rspval), + .vci_out_m1_reop (vci_out_m1_reop), + .vci_out_m1_rspack (vci_out_m1_rspack), + .last_pixel_sig_en (last_pixel_sig_en), + .last_pixel_m1_req (last_pixel_m1_req), + .last_pixel_m1_ack (last_pixel_m1_ack), + .cfg_upd_double (viv_s5), + .stat_skip_active (stat_skip_active) + ); + vsisp_marvin_mi_out_sp #(c_bursts_supported, c_burst_len_bw, c_fifo_depth_bw) u_marvin_mi_out_sp + ( + .sp_byte_swap (sp_byte_swap), + .m_hclk (m_hclk), + .reset_m_hclk_n (reset_m_hclk_n), + .soft_rst_m_hclk (soft_rst_m_hclk), + .sp_fifo_read64 (sp_fifo_read64), + .sp_fifo_select (sp_fifo_select), + .sp_fifo_data (sp_fifo_data), + .sp_fifo_h_end (sp_fifo_h_end), + .sp_fifo_v_end (sp_fifo_v_end), + .sp_y_fifo_fill_level (sp_y_fifo_fill_level), + .sp_y_fifo_flush (sp_y_fifo_flush), + .sp_cb_fifo_fill_level (sp_cb_fifo_fill_level), + .sp_cb_fifo_flush (sp_cb_fifo_flush), + .sp_cr_fifo_fill_level (sp_cr_fifo_fill_level), + .sp_cr_fifo_flush (sp_cr_fifo_flush), + .soft_upd (soft_upd), + .sp_enable (sp_enable), + .dp_enable (dp_enable[1]), + .h_flip (h_flip), + .v_flip (v_flip), + .rot (rot), + .sp_write_format (sp_write_format), + .sp_output_format (sp_output_format), + .byte_swap (byte_swap), + .init_base_en (init_base_en), + .init_offset_en (init_offset_en), + .sp_pingpong_en (sp_pingpong_en), + .burst_len_lum (burst_len_lum), + .burst_len_chrom (burst_len_chrom), + .stat_sp_enable_out (stat_sp_enable_out), + .stat_dp_enable_out (stat_dp_enable_out[1]), + .sp_y_base_ad (sp_y_base_ad), + .sp_y_size (sp_y_size), + .sp_y_offs_cnt (sp_y_offs_cnt), + .sp_y_base_ad_init (sp_y_base_ad_init), + .sp_y_base_ad_init2 (sp_y_base_ad_init2), + .sp_y_size_init (sp_y_size_init), + .sp_y_offs_cnt_init (sp_y_offs_cnt_init), + .sp_y_offs_cnt_start (sp_y_offs_cnt_start), + .sp_y_pic_width (sp_y_pic_width), + .sp_y_llength (sp_y_llength), + .sp_y_pic_size (sp_y_pic_size), + .sp_cb_base_ad (sp_cb_base_ad), + .sp_cb_size (sp_cb_size), + .sp_cb_offs_cnt (sp_cb_offs_cnt), + .sp_cb_base_ad_init (sp_cb_base_ad_init), + .sp_cb_base_ad_init2 (sp_cb_base_ad_init2), + .sp_cb_size_init (sp_cb_size_init), + .sp_cb_offs_cnt_init (sp_cb_offs_cnt_init), + .sp_cb_offs_cnt_start (sp_cb_offs_cnt_start), + .sp_cr_base_ad (sp_cr_base_ad), + .sp_cr_size (sp_cr_size), + .sp_cr_offs_cnt (sp_cr_offs_cnt), + .sp_cr_base_ad_init (sp_cr_base_ad_init), + .sp_cr_base_ad_init2 (sp_cr_base_ad_init2), + .sp_cr_size_init (sp_cr_size_init), + .sp_cr_offs_cnt_init (sp_cr_offs_cnt_init), + .sp_cr_offs_cnt_start (sp_cr_offs_cnt_start), + .stat_sp_frame_end (stat_sp_frame_end), + .stat_wrap_sp_y (stat_wrap_sp_y), + .stat_wrap_sp_cb (stat_wrap_sp_cb), + .stat_wrap_sp_cr (stat_wrap_sp_cr), + .cfg_in_update_sp (cfg_in_update_sp), + .cfg_out_update_sp (cfg_out_update_sp), + .vci_out_m2_cmdval (vci_out_m2_cmdval), + .vci_out_m2_plen (vci_out_m2_plen), + .vci_out_m2_eop (vci_out_m2_eop), + .vci_out_m2_address (vci_out_m2_address), + .vci_out_m2_wdata (vci_out_m2_wdata), + .vci_out_m2_be (vci_out_m2_be), + .vci_out_m2_cmd (vci_out_m2_cmd), + .vci_out_m2_const (vci_out_m2_const), + .vci_out_m2_contig (vci_out_m2_contig), + .vci_out_m2_wrap (vci_out_m2_wrap), + .vci_out_m2_cmdack (vci_out_m2_cmdack), + .vci_out_m2_rspval (vci_out_m2_rspval), + .vci_out_m2_reop (vci_out_m2_reop), + .vci_out_m2_rspack (vci_out_m2_rspack), + .last_pixel_sig_en (last_pixel_sig_en), + .last_pixel_m2_req (last_pixel_m2_req), + .last_pixel_m2_ack (last_pixel_m2_ack) + ); +vsisp_marvin_mi_handshake u_marvin_mi_handshake( + .isp_0_clock (m_hclk), + .isp_0_rst_n (reset_m_hclk_n), + .soft_upd (soft_upd), + .data_format (data_format), + .starage_format (starage_format), + .slice_size (slice_size), + .buf_size (slice_buf_size), + .mp_fifo_h_end (mp_fifo_h_end), + .mp_fifo_v_end (mp_fifo_v_end), + .mp_fifo_read64 (mp_fifo_read64), + .stat_skip_active (stat_skip_active), + .mp_fifo_select (mp_fifo_select), + .isp_0_ack (isp_0_ack), + .bresp_in (bresp_in), + .mp_y_base_ad (mp_y_base_ad), + .mp_cb_base_ad (mp_cb_base_ad), + .mp_cr_base_ad (mp_cr_base_ad), + .mp_addr_cur_y (viv_s6 ), + .mp_addr_cur_cb (viv_s7 ), + .mp_addr_cur_cr (viv_s8 ), + .ack_count (ack_count), + .mp_slice_offset_y (mp_slice_offset_y), + .mp_slice_offset_c (mp_slice_offset_c), + .mp_y_llength (mp_y_llength), + .mp_line_sens (mp_line_sens), + .isp_0_ready (viv_s2), + .address (viv_s1), + .isp_0_attr (viv_s4), + .mp_interrupt (viv_s3), + .handshake_en (handshake_en), + .handshake_mode_0 (handshake_mode_0), + .slice_cnt_int (slice_cnt_int), + .sw_addr_mp_y (sw_addr_mp_y), + .sw_addr_mp_cb (sw_addr_mp_cb), + .sw_addr_mp_cr (sw_addr_mp_cr), + .sw_interrupt_out (sw_interrupt)); +assign vci_out_m1_address[c_mi_data_addr+3:3] = handshake_en ? viv_s1 : viv_s0; +assign isp_0_attr[1:0] = handshake_en ? viv_s4 : 2'h0; +assign isp_0_ready = handshake_en && viv_s2; +assign mp_interrupt = handshake_en && viv_s3; +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_marvin_mi_out_addrgen_mp.v b/ispyocto/rtl/ispyocto/vsisp_marvin_mi_out_addrgen_mp.v new file mode 100644 index 0000000..dda2139 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_marvin_mi_out_addrgen_mp.v
@@ -0,0 +1,686 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_marvin_mi_out_addrgen_mp + ( + m_hclk, + reset_m_hclk_n, + soft_rst_m_hclk, + mp_fifo_h_end, + mp_fifo_v_end, + soft_upd, + mp_write_format, + mp_output_format, + mp_y_llength, + init_base_en, + init_offset_en, + mp_pingpong_en, + mp_y_base_ad, + mp_y_size, + mp_y_offs_cnt, + mp_y_base_ad_init, + mp_y_base_ad_init2, + mp_y_size_init, + mp_y_offs_cnt_init, + mp_y_offs_cnt_start, + mp_y_irq_offs_init, + mp_y_irq_offs, + mp_cb_base_ad, + mp_cb_size, + mp_cb_offs_cnt, + mp_cb_base_ad_init, + mp_cb_base_ad_init2, + mp_cb_size_init, + mp_cb_offs_cnt_init, + mp_cb_offs_cnt_start, + mp_cr_base_ad, + mp_cr_size, + mp_cr_offs_cnt, + mp_cr_base_ad_init, + mp_cr_base_ad_init2, + mp_cr_size_init, + mp_cr_offs_cnt_init, + mp_cr_offs_cnt_start, + vci_out_m1_rspval, + vci_out_m1_reop, + stat_mblk_line, + stat_fill_mp_y, + stat_wrap_mp_y, + stat_wrap_mp_cb, + stat_wrap_mp_cr, + mp_fifo_read64, + mp_fifo_select, + cfg_out_update_mp, + stat_skip_active, + mp_y_cur_ptr, + mp_cb_cur_ptr, + mp_cr_cur_ptr, + mp_line_sens, + cfg_upd_double + ); +`include "vsisp_marvin_mi.vh" + input mp_line_sens; + output cfg_upd_double; + input m_hclk; + input reset_m_hclk_n; + input soft_rst_m_hclk; + input mp_fifo_h_end; + input mp_fifo_v_end; + input soft_upd; + input [1:0] mp_write_format; + input [3:0] mp_output_format; + input [14:0] mp_y_llength; + input init_base_en; + input init_offset_en; + input mp_pingpong_en; + input [c_mi_data_addr+3:3] mp_y_base_ad_init; + input [c_mi_data_addr+3:3] mp_y_base_ad_init2; + input [c_mi_data_addr:3] mp_y_size_init; + input [c_mi_data_addr:3] mp_y_offs_cnt_init; + input [c_mi_data_addr:3] mp_y_irq_offs_init; + output [c_mi_data_addr+3:3] mp_y_base_ad; + output [c_mi_data_addr:3] mp_y_size; + output [c_mi_data_addr:3] mp_y_offs_cnt; + output [c_mi_data_addr:3] mp_y_offs_cnt_start; + output [c_mi_data_addr:3] mp_y_irq_offs; + input [c_mi_data_addr+3:3] mp_cb_base_ad_init; + input [c_mi_data_addr+3:3] mp_cb_base_ad_init2; + input [c_mi_data_addr-1:3] mp_cb_size_init; + input [c_mi_data_addr-1:3] mp_cb_offs_cnt_init; + output [c_mi_data_addr+3:3] mp_cb_base_ad; + output [c_mi_data_addr-1:3] mp_cb_size; + output [c_mi_data_addr-1:3] mp_cb_offs_cnt; + output [c_mi_data_addr-1:3] mp_cb_offs_cnt_start; + input [c_mi_data_addr+3:3] mp_cr_base_ad_init; + input [c_mi_data_addr+3:3] mp_cr_base_ad_init2; + input [c_mi_data_addr-1:3] mp_cr_size_init; + input [c_mi_data_addr-1:3] mp_cr_offs_cnt_init; + output [c_mi_data_addr+3:3] mp_cr_base_ad; + output [c_mi_data_addr-1:3] mp_cr_size; + output [c_mi_data_addr-1:3] mp_cr_offs_cnt; + output [c_mi_data_addr-1:3] mp_cr_offs_cnt_start; + input vci_out_m1_rspval; + input vci_out_m1_reop; + output stat_mblk_line; + output stat_fill_mp_y; + output stat_wrap_mp_y; + output stat_wrap_mp_cb; + output stat_wrap_mp_cr; + input mp_fifo_read64; + input [1:0] mp_fifo_select; + input cfg_out_update_mp; + input stat_skip_active; + output [c_mi_data_addr:3] mp_y_cur_ptr; + output [c_mi_data_addr-1:3] mp_cb_cur_ptr; + output [c_mi_data_addr-1:3] mp_cr_cur_ptr; + wire viv_s0; + wire cfg_upd_double; + wire [c_mi_data_addr:3] viv_s1; + wire [c_mi_data_addr-1:3] viv_s2; + wire [c_mi_data_addr-1:3] viv_s3; + reg [c_mi_data_addr:3] viv_s4; + reg [c_mi_data_addr-1:3] viv_s5; + reg [c_mi_data_addr-1:3] viv_s6; + reg [c_mi_data_addr:3] viv_s7; + reg [c_mi_data_addr-1:3] viv_s8; + reg [c_mi_data_addr-1:3] viv_s9; + reg [c_mi_data_addr:3] viv_s10; + reg [c_mi_data_addr-1:3] viv_s11; + reg [c_mi_data_addr-1:3] viv_s12; + reg [c_mi_data_addr:3] viv_s13; + reg [c_mi_data_addr-1:3] viv_s14; + reg [c_mi_data_addr-1:3] viv_s15; + reg [3:0] viv_s16; + reg [2:0] viv_s17; + reg [2:0] viv_s18; + reg [3:0] viv_s19; + reg [2:0] viv_s20; + reg [2:0] viv_s21; + reg viv_s22; + reg viv_s23; + reg viv_s24; + reg [14:0] viv_s25; + reg [14:0] viv_s26; + wire [c_mi_data_addr:3] viv_s27; + wire [c_mi_data_addr:3] viv_s28; + wire [c_mi_data_addr:3] viv_s29; + reg [c_mi_data_addr:3] viv_s30; + reg [c_mi_data_addr:3] viv_s31; + reg [c_mi_data_addr:3] viv_s32; + reg [c_mi_data_addr:3] viv_s33; + reg [c_mi_data_addr:3] viv_s34; + reg [c_mi_data_addr:3] viv_s35; + reg [c_mi_data_addr+3:3] mp_y_base_ad; + reg [c_mi_data_addr:3] mp_y_size; + reg [c_mi_data_addr:3] mp_y_offs_cnt_start; + reg [c_mi_data_addr:3] mp_y_irq_offs; + reg [c_mi_data_addr+3:3] mp_cb_base_ad; + reg [c_mi_data_addr-1:3] mp_cb_size; + reg [c_mi_data_addr-1:3] mp_cb_offs_cnt_start; + reg [c_mi_data_addr+3:3] mp_cr_base_ad; + reg [c_mi_data_addr-1:3] mp_cr_size; + reg [c_mi_data_addr-1:3] mp_cr_offs_cnt_start; + reg stat_mblk_line; + reg stat_wrap_mp_y; + reg stat_wrap_mp_cb; + reg stat_wrap_mp_cr; + reg [c_mi_data_addr:3] mp_y_cur_ptr; + reg [c_mi_data_addr-1:3] mp_cb_cur_ptr; + reg [c_mi_data_addr-1:3] mp_cr_cur_ptr; + reg viv_s36; + reg viv_s37; + reg viv_s38; + assign stat_fill_mp_y = ((mp_fifo_select == 2'd0) & mp_fifo_read64) && + (mp_y_cur_ptr == mp_y_irq_offs); + assign viv_s1 = mp_y_cur_ptr + 22'd1; + assign viv_s2 = mp_cb_cur_ptr + 21'd1; + assign viv_s3 = mp_cr_cur_ptr + 21'd1; + reg [14:0] viv_s39; + always @(posedge m_hclk or negedge reset_m_hclk_n) + begin + if (~reset_m_hclk_n) begin + viv_s25 <= 15'h0; + end else + begin + if(((mp_output_format == 4'b0010) && (mp_write_format == 2'b10)) || (mp_output_format == 4'b0100) || (mp_output_format == 4'b0111))begin + viv_s25 <= {mp_y_llength[13:0],1'b0}; + end + else if(mp_output_format == 4'b0110) begin + viv_s25 <= {mp_y_llength[11:0],3'b0}; + end + else begin + viv_s25 <= mp_y_llength; + end + end + end + always @(posedge m_hclk or negedge reset_m_hclk_n) + begin + if (~reset_m_hclk_n) begin + viv_s26 <= 15'h0; + end else + begin + if ((mp_output_format == 4'b0011) && (mp_write_format == 2'b01)) begin + viv_s26 <= {mp_y_llength[13:0], 1'b0}; + end + else if ((mp_output_format == 4'b0011) && (mp_write_format == 2'b00)) begin + viv_s26 <= mp_y_llength; + end + else if ((mp_output_format == 4'b0010) && (mp_write_format == 2'b01)) begin + viv_s26 <= mp_y_llength; + end + else if ((mp_output_format == 4'b0010) && (mp_write_format == 2'b00)) begin + viv_s26 <= {1'b0, mp_y_llength[14:1]}; + end + else if ((mp_output_format == 4'b0001) && (mp_write_format == 2'b01)) begin + viv_s26 <= mp_y_llength; + end + else if ((mp_output_format == 4'b0001) && (mp_write_format == 2'b00)) begin + viv_s26 <= {1'b0, mp_y_llength[14:1]}; + end + else begin + viv_s26 <= 15'h0; + end + end + end + assign viv_s27 = {1'b0,viv_s30 } + {{(c_mi_data_addr+1-14){1'b0}},viv_s25[14:3]}; + assign viv_s28 = {1'b0,viv_s31} + {{(c_mi_data_addr-14){1'b0}},viv_s26[14:3]}; + assign viv_s29 = {1'b0,viv_s32} + {{(c_mi_data_addr-14){1'b0}},viv_s26[14:3]}; +always @(*) +begin + viv_s4 = mp_y_cur_ptr; + viv_s7 = viv_s10; + viv_s13 = mp_y_offs_cnt_start; + viv_s33 = viv_s30; + stat_wrap_mp_y = 1'b0; + if (cfg_upd_double | soft_upd) + begin + if (init_offset_en) + begin + viv_s7 = mp_y_offs_cnt_init; + end + viv_s33 = viv_s7; + viv_s4 = viv_s7; + end + else + begin + if ((mp_fifo_select == 2'd0) & mp_fifo_read64) + begin + if (mp_fifo_h_end & mp_fifo_v_end & stat_skip_active) + begin + if (init_offset_en) + begin + viv_s7 = mp_y_offs_cnt_init; + end + else + begin + viv_s7 = viv_s10; + end + viv_s33 = viv_s7; + viv_s4 = viv_s7; + end + else + begin + if (mp_fifo_h_end & mp_fifo_v_end) + begin + if (viv_s27>= mp_y_size) + begin + viv_s4 = {c_mi_data_addr-2{1'b0}}; + viv_s33 = {c_mi_data_addr-2{1'b0}}; + stat_wrap_mp_y = 1'b1; + end + else + begin + viv_s33 = viv_s27; + if(mp_line_sens) + begin + viv_s4 = viv_s33; + end + else + begin + viv_s4 = viv_s1; + end + end + viv_s7 = viv_s4; + viv_s13 = viv_s10; + end + else + begin + if (viv_s1 >= mp_y_size || (viv_s27>= mp_y_size && mp_fifo_h_end)) + begin + viv_s33 = {c_mi_data_addr-2{1'b0}}; + viv_s4 = {c_mi_data_addr-2{1'b0}}; + stat_wrap_mp_y = 1'b1; + end + else + begin + if(mp_fifo_h_end) + begin + viv_s33 = viv_s27; + if(mp_line_sens) + begin + viv_s4 = viv_s33; + end + else + begin + viv_s4 = viv_s1; + end + end + else + viv_s4 = viv_s1; + end + end + end + end + else + begin + viv_s4 = mp_y_cur_ptr; + viv_s7 = viv_s10; + viv_s13 = mp_y_offs_cnt_start; + stat_wrap_mp_y = 1'b0; + end + end + end + always @(*) begin + viv_s5 = mp_cb_cur_ptr; + viv_s8 = viv_s11; + viv_s14 = mp_cb_offs_cnt_start; + viv_s34 = viv_s31; + stat_wrap_mp_cb = 1'b0; + if (cfg_upd_double | soft_upd) begin + if (init_offset_en) begin + viv_s8 = mp_cb_offs_cnt_init; + end + viv_s34 = viv_s8; + viv_s5 = viv_s8; + end + else if ((mp_fifo_select == 2'd1) & mp_fifo_read64) begin + if (mp_fifo_h_end & mp_fifo_v_end & stat_skip_active) begin + if (init_offset_en) begin + viv_s8 = mp_cb_offs_cnt_init; + end + else begin + viv_s8 = viv_s11; + end + viv_s34 = viv_s8; + viv_s5 = viv_s8; + end + else if (mp_fifo_h_end & mp_fifo_v_end) begin + if (viv_s28 >= mp_cb_size) begin + viv_s34 = {c_mi_data_addr-2{1'b0}}; + viv_s5 = {c_bufsize-2{1'b0}}; + stat_wrap_mp_cb = 1'b1; + end + else begin + viv_s34 = viv_s28; + if(mp_line_sens) begin + viv_s5 = viv_s34; + end + else begin + viv_s5 = viv_s2; + end + end + viv_s8 = viv_s5; + viv_s14 = viv_s11; + end + else if (viv_s2 >= mp_cb_size || (viv_s28>= mp_cb_size && mp_fifo_h_end)) begin + viv_s34 = {c_mi_data_addr-2{1'b0}}; + viv_s5 = {c_mi_data_addr-2{1'b0}}; + stat_wrap_mp_cb = 1'b1; + end + else begin + if(mp_fifo_h_end) + begin + viv_s34 = viv_s28; + if(mp_line_sens) begin + viv_s5 = viv_s34; + end + else begin + viv_s5 = viv_s2; + end + end + else + viv_s5 = viv_s2; + end + end + else begin + viv_s5 = mp_cb_cur_ptr; + viv_s8 = viv_s11; + viv_s14 = mp_cb_offs_cnt_start; + stat_wrap_mp_cb = 1'b0; + end + end + always @(*) begin + viv_s6 = mp_cr_cur_ptr; + viv_s9 = viv_s12; + viv_s15 = mp_cr_offs_cnt_start; + viv_s35 = viv_s32; + stat_wrap_mp_cr = 1'b0; + if (cfg_upd_double | soft_upd) begin + if (init_offset_en) begin + viv_s9 = mp_cr_offs_cnt_init; + end + viv_s35 = viv_s9; + viv_s6 = viv_s9; + end + else if ((mp_fifo_select == 2'd2) & mp_fifo_read64) begin + if (mp_fifo_h_end & mp_fifo_v_end & stat_skip_active) begin + if (init_offset_en) begin + viv_s9 = mp_cr_offs_cnt_init; + end + else begin + viv_s9 = viv_s12; + end + viv_s35 = viv_s9; + viv_s6 = viv_s9; + end + else if (mp_fifo_h_end & mp_fifo_v_end) begin + if (viv_s29 >= mp_cr_size) begin + viv_s35 = {c_mi_data_addr-2{1'b0}}; + viv_s6 = {c_mi_data_addr-2{1'b0}}; + stat_wrap_mp_cr = 1'b1; + end + else begin + viv_s35 = viv_s29; + if(mp_line_sens) begin + viv_s6 = viv_s35; + end + else begin + viv_s6 = viv_s3; + end + end + viv_s9 = viv_s6; + viv_s15 = viv_s12; + end + else if (viv_s3 >= mp_cr_size || (viv_s29>= mp_cr_size && mp_fifo_h_end)) begin + viv_s35 = {c_mi_data_addr-2{1'b0}}; + viv_s6 = {c_mi_data_addr-2{1'b0}}; + stat_wrap_mp_cr = 1'b1; + end + else begin + if(mp_fifo_h_end) + begin + viv_s35 = viv_s29; + if(mp_line_sens) begin + viv_s6 = viv_s35; + end + else begin + viv_s6 = viv_s3; + end + end + else + viv_s6 = viv_s3; + end + end + else begin + viv_s6 = mp_cr_cur_ptr; + viv_s9 = viv_s12; + viv_s15 = mp_cr_offs_cnt_start; + stat_wrap_mp_cr = 1'b0; + end + end + always @(posedge m_hclk or negedge reset_m_hclk_n) begin + if (~reset_m_hclk_n) begin + mp_y_cur_ptr <= {c_mi_data_addr-2{1'b0}}; + mp_cb_cur_ptr <= {c_mi_data_addr-3{1'b0}}; + mp_cr_cur_ptr <= {c_mi_data_addr-3{1'b0}}; + viv_s10 <= {c_mi_data_addr-2{1'b0}}; + viv_s11 <= {c_mi_data_addr-3{1'b0}}; + viv_s12 <= {c_mi_data_addr-3{1'b0}}; + mp_y_offs_cnt_start <= {c_mi_data_addr-2{1'b0}}; + mp_cb_offs_cnt_start <= {c_mi_data_addr-3{1'b0}}; + mp_cr_offs_cnt_start <= {c_mi_data_addr-3{1'b0}}; + viv_s30 <= {c_mi_data_addr-3{1'b0}}; + viv_s31 <= {c_mi_data_addr-3{1'b0}}; + viv_s32 <= {c_mi_data_addr-3{1'b0}}; + end + else if (soft_rst_m_hclk) begin + mp_y_cur_ptr <= {c_mi_data_addr-2{1'b0}}; + mp_cb_cur_ptr <= {c_mi_data_addr-3{1'b0}}; + mp_cr_cur_ptr <= {c_mi_data_addr-3{1'b0}}; + viv_s10 <= {c_mi_data_addr-2{1'b0}}; + viv_s11 <= {c_mi_data_addr-3{1'b0}}; + viv_s12 <= {c_mi_data_addr-3{1'b0}}; + mp_y_offs_cnt_start <= {c_mi_data_addr-2{1'b0}}; + mp_cb_offs_cnt_start <= {c_mi_data_addr-3{1'b0}}; + mp_cr_offs_cnt_start <= {c_mi_data_addr-3{1'b0}}; + viv_s30 <= {c_mi_data_addr-3{1'b0}}; + viv_s31 <= {c_mi_data_addr-3{1'b0}}; + viv_s32 <= {c_mi_data_addr-3{1'b0}}; + end + else begin + mp_y_cur_ptr <= viv_s4; + mp_cb_cur_ptr <= viv_s5; + mp_cr_cur_ptr <= viv_s6; + viv_s10 <= viv_s7; + viv_s11 <= viv_s8; + viv_s12 <= viv_s9; + mp_y_offs_cnt_start <= viv_s13; + mp_cb_offs_cnt_start <= viv_s14; + mp_cr_offs_cnt_start <= viv_s15; + viv_s30 <= viv_s33; + viv_s31 <= viv_s34; + viv_s32 <= viv_s35; + end + end + assign mp_y_offs_cnt = viv_s10; + assign mp_cb_offs_cnt = viv_s11; + assign mp_cr_offs_cnt = viv_s12; + assign viv_s0 = cfg_out_update_mp && ~viv_s37; + assign cfg_upd_double = (cfg_out_update_mp && ~viv_s37) || viv_s38; + always @(posedge m_hclk or negedge reset_m_hclk_n) begin + if (~reset_m_hclk_n) begin + mp_y_base_ad <= {c_mi_data_addr+1{1'b0}}; + mp_y_size <= {c_mi_data_addr-2{1'b0}}; + mp_cb_base_ad <= {c_mi_data_addr+1{1'b0}}; + mp_cb_size <= {c_mi_data_addr-3{1'b0}}; + mp_cr_base_ad <= {c_mi_data_addr+1{1'b0}}; + mp_cr_size <= {c_mi_data_addr-3{1'b0}}; + mp_y_irq_offs <= {c_mi_data_addr-2{1'b0}}; + viv_s36 <= 1'b0; + viv_s37 <= 1'b0; + viv_s38 <= 1'b0; + end + else if (soft_rst_m_hclk) begin + mp_y_base_ad <= mp_y_base_ad_init; + mp_y_size <= mp_y_size_init; + mp_y_irq_offs <= mp_y_irq_offs_init; + mp_cb_base_ad <= mp_cb_base_ad_init; + mp_cb_size <= mp_cb_size_init; + mp_cr_base_ad <= mp_cr_base_ad_init; + mp_cr_size <= mp_cr_size_init; + viv_s36 <= 1'b0; + end + else begin + viv_s37 <= cfg_out_update_mp; + viv_s38 <= viv_s0; + if (soft_upd | cfg_upd_double) begin + mp_y_irq_offs <= mp_y_irq_offs_init; + end + if (soft_upd) begin + viv_s36 <= 1'b0; + end + else if (viv_s0 & init_base_en) begin + viv_s36 <= ~viv_s36; + end + if ((soft_upd | viv_s0 ) & init_base_en) begin + if (soft_upd) begin + mp_y_base_ad <= mp_y_base_ad_init; + mp_cb_base_ad <= mp_cb_base_ad_init; + mp_cr_base_ad <= mp_cr_base_ad_init; + end + else begin + if (mp_pingpong_en && ~viv_s36) begin + mp_y_base_ad <= mp_y_base_ad_init2; + mp_cb_base_ad <= mp_cb_base_ad_init2; + mp_cr_base_ad <= mp_cr_base_ad_init2; + end + else begin + mp_y_base_ad <= mp_y_base_ad_init; + mp_cb_base_ad <= mp_cb_base_ad_init; + mp_cr_base_ad <= mp_cr_base_ad_init; + end + end + mp_y_size <= mp_y_size_init; + mp_cb_size <= mp_cb_size_init; + mp_cr_size <= mp_cr_size_init; + end + end + end + always @(*) begin + if (soft_upd | cfg_upd_double) begin + viv_s16 = 4'd15; + viv_s17 = 3'd7; + viv_s18 = 3'd7; + end + else begin + viv_s16 = viv_s19; + viv_s17 = viv_s20; + viv_s18 = viv_s21; + if (mp_fifo_read64 & mp_fifo_h_end & ~stat_skip_active) begin + case (mp_fifo_select) + 2'd0: begin + if (viv_s19 > 4'd0) begin + viv_s16 = viv_s19 - 4'd1; + end + else begin + viv_s16 = 4'd15; + end + end + 2'd1: begin + if (viv_s20 > 3'd0) begin + viv_s17 = viv_s20 - 3'd1; + end + else begin + viv_s17 = 3'd7; + end + end + default: begin + if (viv_s21 > 3'd0) begin + viv_s18 = viv_s21 - 3'd1; + end + else begin + viv_s18 = 3'd7; + end + end + endcase + end + end + end + always @(posedge m_hclk or negedge reset_m_hclk_n) begin + if (~reset_m_hclk_n) begin + viv_s19 <= 4'd15; + viv_s20 <= 3'd7; + viv_s21 <= 3'd7; + end + else if (soft_rst_m_hclk) begin + viv_s19 <= 4'd15; + viv_s20 <= 3'd7; + viv_s21 <= 3'd7; + end + else begin + viv_s19 <= viv_s16; + viv_s20 <= viv_s17; + viv_s21 <= viv_s18; + end + end + always @(posedge m_hclk or negedge reset_m_hclk_n) begin + if (~reset_m_hclk_n) begin + viv_s22 <= 1'b0; + viv_s23 <= 1'b0; + viv_s24 <= 1'b0; + stat_mblk_line <= 1'b0; + end + else if (soft_rst_m_hclk) begin + viv_s22 <= 1'b0; + viv_s23 <= 1'b0; + viv_s24 <= 1'b0; + stat_mblk_line <= 1'b0; + end + else begin + if (soft_upd | cfg_upd_double | stat_mblk_line) begin + viv_s22 <= 1'b0; + viv_s23 <= 1'b0; + viv_s24 <= 1'b0; + stat_mblk_line <= 1'b0; + end + else if (mp_fifo_read64 & mp_fifo_h_end & ~stat_skip_active) begin + if ((mp_fifo_select == 2'd0) && (viv_s16 == 4'd0)) begin + viv_s22 <= 1'b1; + end + else if ((mp_fifo_select == 2'd1) && + (viv_s17 == 3'd0)) begin + viv_s23 <= 1'b1; + end + else if ((mp_fifo_select == 2'd2) && + (viv_s18 == 3'd0)) begin + viv_s24 <= 1'b1; + end + end + if (viv_s22 & viv_s23 & + (viv_s24 | (mp_write_format == 2'b01)) & + vci_out_m1_rspval & vci_out_m1_reop & ~stat_skip_active) begin + stat_mblk_line <= 1'b1; + end + end + end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_marvin_mi_out_addrgen_sp.v b/ispyocto/rtl/ispyocto/vsisp_marvin_mi_out_addrgen_sp.v new file mode 100644 index 0000000..9d07a7f --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_marvin_mi_out_addrgen_sp.v
@@ -0,0 +1,759 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_marvin_mi_out_addrgen_sp + ( + m_hclk, + reset_m_hclk_n, + soft_rst_m_hclk, + sp_fifo_h_end, + sp_fifo_v_end, + soft_upd, + h_flip, + v_flip, + rot, + sp_write_format, + sp_output_format, + init_base_en, + init_offset_en, + sp_pingpong_en, + sp_y_base_ad, + sp_y_size, + sp_y_offs_cnt, + sp_y_base_ad_init, + sp_y_base_ad_init2, + sp_y_size_init, + sp_y_offs_cnt_init, + sp_y_offs_cnt_start, + sp_y_pic_width, + sp_y_llength, + sp_y_pic_size, + sp_cb_base_ad, + sp_cb_size, + sp_cb_offs_cnt, + sp_cb_base_ad_init, + sp_cb_base_ad_init2, + sp_cb_size_init, + sp_cb_offs_cnt_init, + sp_cb_offs_cnt_start, + sp_cr_base_ad, + sp_cr_size, + sp_cr_offs_cnt, + sp_cr_base_ad_init, + sp_cr_base_ad_init2, + sp_cr_size_init, + sp_cr_offs_cnt_init, + sp_cr_offs_cnt_start, + stat_wrap_sp_y, + stat_wrap_sp_cb, + stat_wrap_sp_cr, + sp_fifo_read64, + sp_fifo_select, + cfg_out_update_sp, + sp_y_cur_ptr, + sp_cb_cur_ptr, + sp_cr_cur_ptr + ); +`include "vsisp_marvin_mi.vh" + input m_hclk; + input reset_m_hclk_n; + input soft_rst_m_hclk; + input sp_fifo_h_end; + input sp_fifo_v_end; + input soft_upd; + input h_flip; + input v_flip; + input rot; + input [1:0] sp_write_format; + input [2:0] sp_output_format; + input init_base_en; + input init_offset_en; + input sp_pingpong_en; + output [31:3] sp_y_base_ad; + output [c_bufsize:3] sp_y_size; + output [c_bufsize:3] sp_y_offs_cnt; + input [31:3] sp_y_base_ad_init; + input [31:3] sp_y_base_ad_init2; + input [c_bufsize:3] sp_y_size_init; + input [c_bufsize:3] sp_y_offs_cnt_init; + output [c_bufsize:3] sp_y_offs_cnt_start; + input [14:0] sp_y_pic_width; + input [14:0] sp_y_llength; + input [c_bufsize:0] sp_y_pic_size; + reg [31:3] sp_y_base_ad; + reg [c_bufsize:3] sp_y_size; + reg [c_bufsize:3] sp_y_offs_cnt_start; + output [31:3] sp_cb_base_ad; + output [c_bufsize-1:3] sp_cb_size; + output [c_bufsize-1:3] sp_cb_offs_cnt; + input [31:3] sp_cb_base_ad_init; + input [31:3] sp_cb_base_ad_init2; + input [c_bufsize-1:3] sp_cb_size_init; + input [c_bufsize-1:3] sp_cb_offs_cnt_init; + output [c_bufsize-1:3] sp_cb_offs_cnt_start; + reg [31:3] sp_cb_base_ad; + reg [c_bufsize-1:3] sp_cb_size; + reg [c_bufsize-1:3] sp_cb_offs_cnt_start; + output [31:3] sp_cr_base_ad; + output [c_bufsize-1:3] sp_cr_size; + output [c_bufsize-1:3] sp_cr_offs_cnt; + input [31:3] sp_cr_base_ad_init; + input [31:3] sp_cr_base_ad_init2; + input [c_bufsize-1:3] sp_cr_size_init; + input [c_bufsize-1:3] sp_cr_offs_cnt_init; + output [c_bufsize-1:3] sp_cr_offs_cnt_start; + reg [31:3] sp_cr_base_ad; + reg [c_bufsize-1:3] sp_cr_size; + reg [c_bufsize-1:3] sp_cr_offs_cnt_start; + output stat_wrap_sp_y; + output stat_wrap_sp_cb; + output stat_wrap_sp_cr; + reg stat_wrap_sp_y; + reg stat_wrap_sp_cb; + reg stat_wrap_sp_cr; + input sp_fifo_read64; + input [1:0] sp_fifo_select; + input cfg_out_update_sp; + output [c_bufsize:3] sp_y_cur_ptr; + output [c_bufsize-1:3] sp_cb_cur_ptr; + output [c_bufsize-1:3] sp_cr_cur_ptr; + reg [c_bufsize:3] sp_y_cur_ptr; + reg [c_bufsize-1:3] sp_cb_cur_ptr; + reg [c_bufsize-1:3] sp_cr_cur_ptr; + reg viv_s0; + reg viv_s1; + reg viv_s2; + wire viv_s3; + wire viv_s4; + reg [14:0] viv_s5; + reg [14:0] viv_s6; + reg [c_bufsize:0] viv_s7; + reg [14:0] viv_s8; + reg [14:0] viv_s9; + reg [c_bufsize:0] viv_s10; + reg [c_bufsize:0] viv_s11; + reg [c_bufsize:0] viv_s12; + wire [c_bufsize:0] viv_s13; + wire [c_bufsize:0] viv_s14; + wire [c_bufsize+1:3] viv_s15; + wire [c_bufsize:3] viv_s16; + wire [c_bufsize:3] viv_s17; + reg [c_bufsize+1:3] viv_s18; + reg [c_bufsize:3] viv_s19; + reg [c_bufsize:3] viv_s20; + reg viv_s21; + reg [c_bufsize+1:3] viv_s22; + reg [c_bufsize:3] viv_s23; + reg [c_bufsize:3] viv_s24; + reg viv_s25; + wire [c_bufsize+1:3] viv_s26; + wire [c_bufsize:3] viv_s27; + wire [c_bufsize:3] viv_s28; + wire [c_bufsize:3] viv_s29; + wire [c_bufsize:3] viv_s30; + wire [c_bufsize:3] viv_s31; + wire [c_bufsize:3] viv_s32; + wire [c_bufsize:3] viv_s33; + wire [c_bufsize:3] viv_s34; + wire [c_bufsize:3] viv_s35; + wire [c_bufsize:3] viv_s36; + wire [c_bufsize:3] viv_s37; + wire [c_bufsize:3] viv_s38; + wire [c_bufsize-1:3] viv_s39; + wire [c_bufsize-1:3] viv_s40; + wire [c_bufsize:3] viv_s41; + wire [c_bufsize:3] viv_s42; + wire [c_bufsize:3] viv_s43; + wire [c_bufsize:3] viv_s44; + wire [c_bufsize:3] viv_s45; + wire [c_bufsize:3] viv_s46; + reg [c_bufsize+1:3] viv_s47; + reg [c_bufsize+1:3] viv_s48; + reg [c_bufsize+1:3] viv_s49; + reg [c_bufsize+1:3] viv_s50; + reg [c_bufsize:3] viv_s51; + reg [c_bufsize:3] viv_s52; + reg [c_bufsize:3] viv_s53; + reg [c_bufsize:3] viv_s54; + reg [c_bufsize:3] viv_s55; + reg [c_bufsize:3] viv_s56; + reg [c_bufsize:3] viv_s57; + reg [c_bufsize:3] viv_s58; + reg [c_bufsize:3] viv_s59; + reg [c_bufsize-1:3] viv_s60; + reg [c_bufsize-1:3] viv_s61; + reg [c_bufsize:3] viv_s62; + reg [c_bufsize-1:3] viv_s63; + reg [c_bufsize-1:3] viv_s64; + reg [c_bufsize:3] viv_s65; + reg [c_bufsize-1:3] viv_s66; + reg [c_bufsize-1:3] viv_s67; + reg [c_bufsize:3] viv_s68; + reg [c_bufsize-1:3] viv_s69; + reg [c_bufsize-1:3] viv_s70; + wire viv_s71; + wire viv_s72; + assign viv_s72 = (sp_y_pic_width != sp_y_llength) | + (h_flip | v_flip | rot); + always @(posedge m_hclk or negedge reset_m_hclk_n) begin + if (~reset_m_hclk_n) begin + viv_s5 <= 15'h0; + viv_s6 <= 15'h0; + viv_s7 <= {(c_bufsize+1){1'b0}}; + viv_s8 <= 15'h0; + viv_s9 <= 15'h0; + viv_s10 <= {(c_bufsize+1){1'b0}}; + end else begin + if ((sp_output_format == 3'b100) || (sp_write_format == 2'b10))begin + viv_s5 <= {sp_y_pic_width[13:0] , 1'b0} - 12'd2; + viv_s6 <= {sp_y_llength[13:0] , 1'b0}; + viv_s7 <= {sp_y_pic_size[c_bufsize-1:0] , 1'b0}; + end + else if (sp_output_format[2]) begin + viv_s5 <= {sp_y_pic_width[12:0] , 2'b00} - 12'd4; + viv_s6 <= {sp_y_llength[12:0] , 2'b00}; + viv_s7 <= {sp_y_pic_size[c_bufsize-2:0] , 2'b00}; + end + else begin + viv_s5 <= sp_y_pic_width - 15'd1; + viv_s6 <= sp_y_llength; + viv_s7 <= sp_y_pic_size; + end + if ((sp_output_format == 3'b011) && (sp_write_format == 2'b01)) begin + viv_s8 <= {sp_y_pic_width[13:0], 1'b0}; + viv_s9 <= {sp_y_llength[13:0], 1'b0}; + viv_s10 <= {sp_y_pic_size[c_bufsize-1:0], 1'b0}; + end + else if ((sp_output_format == 3'b011) && (sp_write_format == 2'b00)) begin + viv_s8 <= sp_y_pic_width - 15'd1; + viv_s9 <= sp_y_llength; + viv_s10 <= sp_y_pic_size; + end + else if ((sp_output_format == 3'b010) && (sp_write_format == 2'b01)) begin + viv_s8 <= sp_y_pic_width - 15'd1; + viv_s9 <= sp_y_llength; + viv_s10 <= sp_y_pic_size; + end + else if ((sp_output_format == 3'b010) && (sp_write_format == 2'b00)) begin + viv_s8 <= {1'b0, sp_y_pic_width[14:1]}; + viv_s9 <= {1'b0, sp_y_llength[14:1]}; + viv_s10 <= {1'b0, sp_y_pic_size[c_bufsize:1]}; + end + else if ((sp_output_format == 3'b001) && (sp_write_format == 2'b01)) begin + viv_s8 <= sp_y_pic_width - 15'd1; + viv_s9 <= sp_y_llength; + viv_s10 <= {1'b0, sp_y_pic_size[c_bufsize:1]}; + end + else if ((sp_output_format == 3'b001) && (sp_write_format == 2'b00)) begin + viv_s8 <= {1'b0, sp_y_pic_width[14:1]}; + viv_s9 <= {1'b0, sp_y_llength[14:1]}; + viv_s10 <= {2'b00, sp_y_pic_size[c_bufsize:2]}; + end + else begin + viv_s8 <= 15'h0; + viv_s9 <= 15'h0; + viv_s10 <= {(c_bufsize+1){1'b0}}; + end + end + end + assign viv_s13 = viv_s7 - {{c_bufsize-14{1'b0}}, viv_s6}; + assign viv_s14 = viv_s10 - {{c_bufsize-14{1'b0}}, viv_s9}; + always @(posedge m_hclk or negedge reset_m_hclk_n) begin + if (~reset_m_hclk_n) begin + viv_s11 <= {c_bufsize+1{1'b0}}; + viv_s12 <= {c_bufsize+1{1'b0}}; + end else begin + case({rot, h_flip, v_flip}) + 3'b000, 3'b010, 3'b100: begin + viv_s11 <= {c_bufsize+1{1'b0}}; + viv_s12 <= {c_bufsize+1{1'b0}}; + end + 3'b001, 3'b011, 3'b101: begin + viv_s11 <= viv_s13; + viv_s12 <= viv_s14; + end + 3'b110: begin + if (sp_output_format == 3'b011) begin + viv_s11 <= viv_s13 + + {{c_bufsize-14{1'b0}}, viv_s5[14:2], 2'b0}; + viv_s12 <= viv_s14 + + {{c_bufsize-14{1'b0}}, viv_s8[14:2], 2'b0}; + end + else begin + viv_s11 <= viv_s13 + + {{c_bufsize-14{1'b0}}, viv_s5[14:4], 4'b0}; + viv_s12 <= viv_s14 + + {{c_bufsize-14{1'b0}}, viv_s8[14:4], 4'b0}; + end + end + default: begin + if (sp_output_format == 3'b011) begin + viv_s11 <= {{c_bufsize-14{1'b0}}, viv_s5[14:2], 2'b0}; + viv_s12 <= {{c_bufsize-14{1'b0}}, viv_s8[14:2], 2'b0}; + end + else begin + viv_s11 <= {{c_bufsize-14{1'b0}}, viv_s5[14:4], 4'b0}; + viv_s12 <= {{c_bufsize-14{1'b0}}, viv_s8[14:4], 4'b0}; + end + end + endcase + end + end + assign viv_s71 = ({rot, h_flip} == 2'b11) ? ~v_flip : v_flip; + always @(*) begin + if (~viv_s71) begin + viv_s18 = {1'b0,viv_s59 } + {{(c_bufsize+1-14){1'b0}},viv_s6[14:3]}; + viv_s19 = {1'b0,viv_s60} + {{(c_bufsize-14){1'b0}},viv_s9[14:3]}; + viv_s20 = {1'b0,viv_s61} + {{(c_bufsize-14){1'b0}},viv_s9[14:3]}; + viv_s21 = 1'b0; + end + else begin + viv_s18 = {1'b0,viv_s59 } - {{(c_bufsize+1-14){1'b0}},viv_s6[14:3]}; + viv_s19 = {1'b0,viv_s60} - {{(c_bufsize-14){1'b0}},viv_s9[14:3]}; + viv_s20 = {1'b0,viv_s61} - {{(c_bufsize-14){1'b0}},viv_s9[14:3]}; + viv_s21 = 1'b1; + end + end + always @(h_flip or viv_s63 or viv_s64 or + sp_output_format or viv_s62) begin + if (sp_output_format == 3'b011) begin + if (~h_flip) begin + viv_s22 = {1'b0,viv_s62 } + 27'd1; + viv_s23 = {1'b0,viv_s63} + 27'd1; + viv_s24 = {1'b0,viv_s64} + 27'd1; + viv_s25 = 1'b0; + end + else begin + viv_s22 = {1'b0,viv_s62 } - 27'd1; + viv_s23 = {1'b0,viv_s63} - 27'd1; + viv_s24 = {1'b0,viv_s64} - 27'd1; + viv_s25 = 1'b1; + end + end + else begin + if (~h_flip) begin + viv_s22 = {1'b0,viv_s62 } + 27'd2; + viv_s23 = {1'b0,viv_s63} + 27'd4; + viv_s24 = {1'b0,viv_s64} + 27'd4; + viv_s25 = 1'b0; + end + else begin + viv_s22 = {1'b0,viv_s62 } - 27'd2; + viv_s23 = {1'b0,viv_s63} - 27'd4; + viv_s24 = {1'b0,viv_s64} - 27'd4; + viv_s25 = 1'b1; + end + end + end + assign viv_s26 = {1'b0,viv_s65} +{1'b0, viv_s7[c_bufsize:3] }; + assign viv_s27 = {1'b0,viv_s66}+{1'b0, viv_s10[c_bufsize-1:3]}; + assign viv_s28 = {1'b0,viv_s67}+{1'b0, viv_s10[c_bufsize-1:3]}; + assign viv_s29 = (viv_s26 >= {1'b0, sp_y_size}) ? viv_s26 - {1'b0, sp_y_size} : viv_s26; + assign viv_s30 = (viv_s27 >= {1'b0, sp_cb_size}) ? viv_s27 - {1'b0, sp_cb_size}: viv_s27; + assign viv_s31 = (viv_s28 >= {1'b0, sp_cr_size}) ? viv_s28 - {1'b0, sp_cr_size}: viv_s28; + assign viv_s35 = viv_s29 + viv_s11[c_bufsize:3]; + assign viv_s36 = viv_s30 + viv_s12[c_bufsize:3]; + assign viv_s37 = viv_s31 + viv_s12[c_bufsize:3]; + assign viv_s32 = (viv_s35 >= sp_y_size ) ? + viv_s35 - sp_y_size : viv_s35; + assign viv_s33 = (viv_s36 >= {1'b0, sp_cb_size}) ? + viv_s36 - {1'b0, sp_cb_size} : viv_s36; + assign viv_s34 = (viv_s37 >= {1'b0, sp_cr_size}) ? + viv_s37 - {1'b0, sp_cr_size} : viv_s37; + assign viv_s38 = init_offset_en ? sp_y_offs_cnt_init : viv_s65; + assign viv_s39 = init_offset_en ? sp_cb_offs_cnt_init : viv_s66; + assign viv_s40 = init_offset_en ? sp_cr_offs_cnt_init : viv_s67; + assign viv_s44 = viv_s38 + viv_s11[c_bufsize:3]; + assign viv_s45 = {1'b0, viv_s39} + viv_s12[c_bufsize:3]; + assign viv_s46 = {1'b0, viv_s40} + viv_s12[c_bufsize:3]; + assign viv_s41 = (viv_s44 >= sp_y_size ) ? + viv_s44 - sp_y_size : viv_s44; + assign viv_s42 = (viv_s45 >= {1'b0, sp_cb_size}) ? + viv_s45 - {1'b0, sp_cb_size} : viv_s45; + assign viv_s43 = (viv_s46 >= {1'b0, sp_cr_size}) ? + viv_s46 - {1'b0, sp_cr_size} : viv_s46; + assign viv_s15 = {1'b0, sp_y_cur_ptr} + 27'd1; + assign viv_s16 = {1'b0, sp_cb_cur_ptr} + 27'd1; + assign viv_s17 = {1'b0, sp_cr_cur_ptr} + 27'd1; + always @(*) begin + viv_s47 = {1'b0, sp_y_cur_ptr}; + viv_s48 = {1'b0, viv_s59}; + viv_s49 = {1'b0, viv_s62}; + viv_s50 = {1'b0, viv_s65}; + viv_s68 = sp_y_offs_cnt_start; + stat_wrap_sp_y = 1'b0; + if (viv_s4 | soft_upd) begin + if (init_offset_en) begin + viv_s50 = {1'b0, sp_y_offs_cnt_init}; + end + viv_s47 = {1'b0, viv_s41}; + viv_s48 = {1'b0, viv_s41}; + viv_s49 = {1'b0, viv_s41}; + viv_s68 = sp_y_offs_cnt_start; + end + else if ((sp_fifo_select == 2'd0) & sp_fifo_read64) begin + if (sp_fifo_h_end & sp_fifo_v_end & viv_s72) begin + if (viv_s26 >= {1'b0, sp_y_size}) begin + viv_s50 = viv_s26 - {1'b0, sp_y_size}; + stat_wrap_sp_y = 1'b1; + end + else begin + viv_s50 = viv_s26; + end + viv_s47 = {1'b0, viv_s32}; + viv_s48 = {1'b0, viv_s32}; + viv_s49 = {1'b0, viv_s32}; + viv_s68 = viv_s65; + end + else if (sp_fifo_h_end & sp_fifo_v_end) begin + if (viv_s15 >= {1'b0, sp_y_size}) begin + viv_s47 = {(c_bufsize-1){1'b0}}; + viv_s50 = {(c_bufsize-1){1'b0}}; + stat_wrap_sp_y = 1'b1; + end + else begin + viv_s47 = viv_s15; + viv_s50 = viv_s15; + end + viv_s68 = viv_s65; + end + else if (sp_fifo_h_end & viv_s72 & viv_s18[c_bufsize+1] & viv_s21) begin + viv_s48 = viv_s18 + {1'b0, sp_y_size}; + viv_s47 = viv_s18 + {1'b0, sp_y_size}; + stat_wrap_sp_y = 1'b1; + end + else if (sp_fifo_h_end & viv_s72 & + (viv_s18 >= {1'b0, sp_y_size})) begin + viv_s48 = viv_s18 - {1'b0, sp_y_size}; + viv_s47 = viv_s18 - {1'b0, sp_y_size}; + stat_wrap_sp_y = 1'b1; + end + else if (sp_fifo_h_end & viv_s72) begin + viv_s48 = viv_s18; + viv_s47 = viv_s18; + end + else if (rot & sp_fifo_v_end & viv_s22[c_bufsize+1] & viv_s25) begin + viv_s49 = viv_s22 + {1'b0, sp_y_size}; + viv_s48 = viv_s22 + {1'b0, sp_y_size}; + viv_s47 = viv_s22 + {1'b0, sp_y_size}; + stat_wrap_sp_y = 1'b1; + end + else if (rot & sp_fifo_v_end & (viv_s22 >= {1'b0, sp_y_size})) begin + viv_s49 = viv_s22 - {1'b0, sp_y_size}; + viv_s48 = viv_s22 - {1'b0, sp_y_size}; + viv_s47 = viv_s22 - {1'b0, sp_y_size}; + stat_wrap_sp_y = 1'b1; + end + else if (rot & sp_fifo_v_end) begin + viv_s49 = viv_s22; + viv_s48 = viv_s22; + viv_s47 = viv_s22; + end + else if (viv_s15 >= {1'b0, sp_y_size}) begin + viv_s47 = {(c_bufsize-1){1'b0}}; + stat_wrap_sp_y = 1'b1; + end + else begin + viv_s47 = viv_s15; + end + end + end + always @(*) begin + viv_s51 = {1'b0, sp_cb_cur_ptr}; + viv_s52 = {1'b0, viv_s60}; + viv_s53 = {1'b0, viv_s63}; + viv_s54 = {1'b0, viv_s66}; + viv_s69 = sp_cb_offs_cnt_start; + stat_wrap_sp_cb = 1'b0; + if (viv_s4 | soft_upd) begin + if (init_offset_en) begin + viv_s54 = {1'b0, sp_cb_offs_cnt_init}; + end + viv_s51 = viv_s42; + viv_s52 = viv_s42; + viv_s53 = viv_s42; + viv_s69 = sp_cb_offs_cnt_start; + end + else if ((sp_fifo_select == 2'd1) & sp_fifo_read64) begin + if (sp_fifo_h_end & sp_fifo_v_end & viv_s72) begin + if (viv_s27 >= {1'b0, sp_cb_size}) begin + viv_s54 = viv_s27 - {1'b0, sp_cb_size}; + stat_wrap_sp_cb = 1'b1; + end + else begin + viv_s54 = viv_s27; + end + viv_s51 = viv_s33; + viv_s52 = viv_s33; + viv_s53 = viv_s33; + viv_s69 = viv_s66; + end + else if (sp_fifo_h_end & sp_fifo_v_end) begin + if (viv_s16 >= {1'b0, sp_cb_size}) begin + viv_s51 = {(c_bufsize-2){1'b0}}; + viv_s54 = {(c_bufsize-2){1'b0}}; + stat_wrap_sp_cb = 1'b1; + end + else begin + viv_s51 = viv_s16; + viv_s54 = viv_s16; + end + viv_s69 = viv_s66; + end + else if (sp_fifo_h_end & viv_s72 & viv_s19[c_bufsize] & viv_s21) begin + viv_s52 = viv_s19 + {1'b0, sp_cb_size}; + viv_s51 = viv_s19 + {1'b0, sp_cb_size}; + stat_wrap_sp_cb = 1'b1; + end + else if (sp_fifo_h_end & viv_s72 & + (viv_s19 >= {1'b0, sp_cb_size})) begin + viv_s52 = viv_s19 - {1'b0, sp_cb_size}; + viv_s51 = viv_s19 - {1'b0, sp_cb_size}; + stat_wrap_sp_cb = 1'b1; + end + else if (sp_fifo_h_end & viv_s72) begin + viv_s52 = viv_s19; + viv_s51 = viv_s19; + end + else if (rot & sp_fifo_v_end & viv_s23[c_bufsize] & viv_s25) begin + viv_s53 = viv_s23 + {1'b0, sp_cb_size}; + viv_s52 = viv_s23 + {1'b0, sp_cb_size}; + viv_s51 = viv_s23 + {1'b0, sp_cb_size}; + stat_wrap_sp_cb = 1'b1; + end + else if (rot & sp_fifo_v_end & (viv_s23 >= {1'b0, sp_cb_size})) begin + viv_s53 = viv_s23 - {1'b0, sp_cb_size}; + viv_s52 = viv_s23 - {1'b0, sp_cb_size}; + viv_s51 = viv_s23 - {1'b0, sp_cb_size}; + stat_wrap_sp_cb = 1'b1; + end + else if (rot & sp_fifo_v_end) begin + viv_s53 = viv_s23; + viv_s52 = viv_s23; + viv_s51 = viv_s23; + end + else if (viv_s16 >= {1'b0, sp_cb_size}) begin + viv_s51 = {(c_bufsize-2){1'b0}}; + stat_wrap_sp_cb = 1'b1; + end + else begin + viv_s51 = viv_s16; + end + end + end + always @(*) begin + viv_s55 = {1'b0, sp_cr_cur_ptr}; + viv_s56 = {1'b0, viv_s61}; + viv_s57 = {1'b0, viv_s64}; + viv_s58 = {1'b0, viv_s67}; + viv_s70 = sp_cr_offs_cnt_start; + stat_wrap_sp_cr = 1'b0; + if (viv_s4 | soft_upd) begin + if (init_offset_en) begin + viv_s58 = {1'b0, sp_cr_offs_cnt_init}; + end + viv_s55 = viv_s43; + viv_s56 = viv_s43; + viv_s57 = viv_s43; + viv_s70 = sp_cr_offs_cnt_start; + end + else if ((sp_fifo_select == 2'd2) & sp_fifo_read64) begin + if (sp_fifo_h_end & sp_fifo_v_end & viv_s72) begin + if (viv_s28 >= {1'b0, sp_cr_size}) begin + viv_s58 = viv_s28 - {1'b0, sp_cr_size}; + stat_wrap_sp_cr = 1'b1; + end + else begin + viv_s58 = viv_s28; + end + viv_s55 = viv_s34; + viv_s56 = viv_s34; + viv_s57 = viv_s34; + viv_s70 = viv_s67; + end + else if (sp_fifo_h_end & sp_fifo_v_end) begin + if (viv_s17 >= {1'b0, sp_cr_size}) begin + viv_s55 = {(c_bufsize-2){1'b0}}; + viv_s58 = {(c_bufsize-2){1'b0}}; + stat_wrap_sp_cr = 1'b1; + end + else begin + viv_s55 = viv_s17; + viv_s58 = viv_s17; + end + viv_s70 = viv_s67; + end + else if (sp_fifo_h_end & viv_s72 & viv_s20[c_bufsize] & viv_s21) begin + viv_s56 = viv_s20 + {1'b0, sp_cr_size}; + viv_s55 = viv_s20 + {1'b0, sp_cr_size}; + stat_wrap_sp_cr = 1'b1; + end + else if (sp_fifo_h_end & viv_s72 & + (viv_s20 >= {1'b0, sp_cr_size})) begin + viv_s56 = viv_s20 - {1'b0, sp_cr_size}; + viv_s55 = viv_s20 - {1'b0, sp_cr_size}; + stat_wrap_sp_cr = 1'b1; + end + else if (sp_fifo_h_end & viv_s72) begin + viv_s56 = viv_s20; + viv_s55 = viv_s20; + end + else if (rot & sp_fifo_v_end & viv_s24[c_bufsize] & viv_s25) begin + viv_s57 = viv_s24 + {1'b0, sp_cr_size}; + viv_s56 = viv_s24 + {1'b0, sp_cr_size}; + viv_s55 = viv_s24 + {1'b0, sp_cr_size}; + stat_wrap_sp_cr = 1'b1; + end + else if (rot & sp_fifo_v_end & (viv_s24 >= {1'b0, sp_cr_size})) begin + viv_s57 = viv_s24 - {1'b0, sp_cr_size}; + viv_s56 = viv_s24 - {1'b0, sp_cr_size}; + viv_s55 = viv_s24 - {1'b0, sp_cr_size}; + stat_wrap_sp_cr = 1'b1; + end + else if (rot & sp_fifo_v_end) begin + viv_s57 = viv_s24; + viv_s56 = viv_s24; + viv_s55 = viv_s24; + end + else if (viv_s17 >= {1'b0, sp_cr_size}) begin + viv_s55 = {(c_bufsize-2){1'b0}}; + stat_wrap_sp_cr = 1'b1; + end + else begin + viv_s55 = viv_s17; + end + end + end + always @(posedge m_hclk or negedge reset_m_hclk_n) begin + if (~reset_m_hclk_n) begin + sp_y_cur_ptr <= {c_bufsize-2{1'b0}}; + sp_cb_cur_ptr <= {c_bufsize-3{1'b0}}; + sp_cr_cur_ptr <= {c_bufsize-3{1'b0}}; + viv_s59 <= {c_bufsize-2{1'b0}}; + viv_s60 <= {c_bufsize-3{1'b0}}; + viv_s61 <= {c_bufsize-3{1'b0}}; + viv_s62 <= {c_bufsize-2{1'b0}}; + viv_s63 <= {c_bufsize-3{1'b0}}; + viv_s64 <= {c_bufsize-3{1'b0}}; + viv_s65 <= {c_bufsize-2{1'b0}}; + viv_s66 <= {c_bufsize-3{1'b0}}; + viv_s67 <= {c_bufsize-3{1'b0}}; + sp_y_offs_cnt_start <= {c_bufsize-2{1'b0}}; + sp_cb_offs_cnt_start <= {c_bufsize-3{1'b0}}; + sp_cr_offs_cnt_start <= {c_bufsize-3{1'b0}}; + end + else if (soft_rst_m_hclk) begin + sp_y_cur_ptr <= {c_bufsize-2{1'b0}}; + sp_cb_cur_ptr <= {c_bufsize-3{1'b0}}; + sp_cr_cur_ptr <= {c_bufsize-3{1'b0}}; + viv_s59 <= {c_bufsize-2{1'b0}}; + viv_s60 <= {c_bufsize-3{1'b0}}; + viv_s61 <= {c_bufsize-3{1'b0}}; + viv_s62 <= {c_bufsize-2{1'b0}}; + viv_s63 <= {c_bufsize-3{1'b0}}; + viv_s64 <= {c_bufsize-3{1'b0}}; + viv_s65 <= {c_bufsize-2{1'b0}}; + viv_s66 <= {c_bufsize-3{1'b0}}; + viv_s67 <= {c_bufsize-3{1'b0}}; + sp_y_offs_cnt_start <= {c_bufsize-2{1'b0}}; + sp_cb_offs_cnt_start <= {c_bufsize-3{1'b0}}; + sp_cr_offs_cnt_start <= {c_bufsize-3{1'b0}}; + end + else begin + sp_y_cur_ptr <= viv_s47[c_bufsize:3]; + sp_cb_cur_ptr <= viv_s51[c_bufsize-1:3]; + sp_cr_cur_ptr <= viv_s55[c_bufsize-1:3]; + viv_s59 <= viv_s48[c_bufsize:3]; + viv_s60 <= viv_s52[c_bufsize-1:3]; + viv_s61 <= viv_s56[c_bufsize-1:3]; + viv_s62 <= viv_s49[c_bufsize:3]; + viv_s63 <= viv_s53[c_bufsize-1:3]; + viv_s64 <= viv_s57[c_bufsize-1:3]; + viv_s65 <= viv_s50[c_bufsize:3]; + viv_s66 <= viv_s54[c_bufsize-1:3]; + viv_s67 <= viv_s58[c_bufsize-1:3]; + sp_y_offs_cnt_start <= viv_s68; + sp_cb_offs_cnt_start <= viv_s69; + sp_cr_offs_cnt_start <= viv_s70; + end + end + assign sp_y_offs_cnt = viv_s65; + assign sp_cb_offs_cnt = viv_s66; + assign sp_cr_offs_cnt = viv_s67; + assign viv_s3 = cfg_out_update_sp && ~viv_s1; + assign viv_s4 = (cfg_out_update_sp && ~viv_s1) || viv_s2; + always @(posedge m_hclk or negedge reset_m_hclk_n) begin + if (~reset_m_hclk_n) begin + sp_y_base_ad <= {29{1'b0}}; + sp_y_size <= {c_bufsize-2{1'b0}}; + sp_cb_base_ad <= {29{1'b0}}; + sp_cb_size <= {c_bufsize-3{1'b0}}; + sp_cr_base_ad <= {29{1'b0}}; + sp_cr_size <= {c_bufsize-3{1'b0}}; + viv_s0 <= 1'b0; + viv_s1 <= 1'b0; + viv_s2 <= 1'b0; + end + else if (soft_rst_m_hclk) begin + sp_y_base_ad <= sp_y_base_ad_init; + sp_y_size <= sp_y_size_init; + sp_cb_base_ad <= sp_cb_base_ad_init; + sp_cb_size <= sp_cb_size_init; + sp_cr_base_ad <= sp_cr_base_ad_init; + sp_cr_size <= sp_cr_size_init; + viv_s0 <= 1'b0; + end + else begin + viv_s1 <= cfg_out_update_sp; + viv_s2 <= viv_s3; + if (soft_upd) begin + viv_s0 <= 1'b0; + end + else if (viv_s3 & init_base_en) begin + viv_s0 <= ~viv_s0; + end + if ((soft_upd | viv_s3 ) & init_base_en) begin + if (soft_upd) begin + sp_y_base_ad <= sp_y_base_ad_init; + sp_cb_base_ad <= sp_cb_base_ad_init; + sp_cr_base_ad <= sp_cr_base_ad_init; + end + else begin + if (sp_pingpong_en && ~viv_s0) begin + sp_y_base_ad <= sp_y_base_ad_init2; + sp_cb_base_ad <= sp_cb_base_ad_init2; + sp_cr_base_ad <= sp_cr_base_ad_init2; + end + else begin + sp_y_base_ad <= sp_y_base_ad_init; + sp_cb_base_ad <= sp_cb_base_ad_init; + sp_cr_base_ad <= sp_cr_base_ad_init; + end + end + sp_y_size <= sp_y_size_init; + sp_cb_size <= sp_cb_size_init; + sp_cr_size <= sp_cr_size_init; + end + end + end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_marvin_mi_out_arbit_mp.v b/ispyocto/rtl/ispyocto/vsisp_marvin_mi_out_arbit_mp.v new file mode 100644 index 0000000..4190dec --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_marvin_mi_out_arbit_mp.v
@@ -0,0 +1,275 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_marvin_mi_out_arbit_mp + ( + m_hclk, + reset_m_hclk_n, + soft_rst_m_hclk, + burst_length_y, + burst_length_c, + mp_y_size, + mp_cb_size, + mp_cr_size, + mp_y_fifo_fill_level, + mp_y_fifo_flush, + mp_cb_fifo_fill_level, + mp_cb_fifo_flush, + mp_cr_fifo_fill_level, + mp_cr_fifo_flush, + y_addr, + cb_addr, + cr_addr, + next_sel, + fifo_select_val, + mp_fifo_select, + burst_len, + mp_y_cur_ptr, + mp_cb_cur_ptr, + mp_cr_cur_ptr + ); +`include "vsisp_marvin_mi.vh" + input m_hclk; + input reset_m_hclk_n; + input soft_rst_m_hclk; + input [c_burst_len_bw-1:0] burst_length_y; + input [c_burst_len_bw-1:0] burst_length_c; + input [c_mi_data_addr:3] mp_y_size; + input [c_mi_data_addr-1:3] mp_cb_size; + input [c_mi_data_addr-1:3] mp_cr_size; + input [c_mi_data_addr:3] mp_y_cur_ptr; + input [c_mi_data_addr-1:3] mp_cb_cur_ptr; + input [c_mi_data_addr-1:3] mp_cr_cur_ptr; + input [c_fifo_depth_bw-1:0] mp_y_fifo_fill_level; + input mp_y_fifo_flush; + input [c_fifo_depth_bw-1:0] mp_cb_fifo_fill_level; + input mp_cb_fifo_flush; + input [c_fifo_depth_bw-1:0] mp_cr_fifo_fill_level; + input mp_cr_fifo_flush; + input next_sel; + output fifo_select_val; + output [1:0] mp_fifo_select; + output [c_burst_len_bw-1:0] burst_len; + input [11:3] y_addr; + input [11:3] cb_addr; + input [11:3] cr_addr; + reg fifo_select_val; + reg [1:0] mp_fifo_select; + reg [c_burst_len_bw-1:0] burst_len; + wire [c_mi_data_addr:3] viv_s0; + wire [c_mi_data_addr-1:3] viv_s1; + wire [c_mi_data_addr-1:3] viv_s2; + reg viv_s3; + reg [1:0] viv_s4; + reg [c_burst_len_bw-1:0] viv_s5; + integer v_loop; + wire viv_s6; + wire viv_s7; + wire viv_s8; + assign viv_s0 = mp_y_size - mp_y_cur_ptr; + assign viv_s1 = mp_cb_size - mp_cb_cur_ptr; + assign viv_s2 = mp_cr_size - mp_cr_cur_ptr; + assign viv_s6 = ((mp_y_fifo_fill_level >= 6'd8) && (mp_y_cur_ptr[6:3] != 4'd0) && (burst_length_y >= 5'd8)) || + ((mp_y_fifo_fill_level >= 6'd4) && (mp_y_cur_ptr[5:3] != 3'd0)) || + ((mp_y_fifo_fill_level >= 6'd2) && (mp_y_cur_ptr[4:3] != 2'd0)) || + ((mp_y_fifo_fill_level > 6'd0) && (mp_y_cur_ptr[3] != 1'd0)) || + ((mp_y_fifo_fill_level > 6'd0) && mp_y_fifo_flush) || + (mp_y_fifo_fill_level >= burst_length_y); + assign viv_s7 = ((mp_cb_fifo_fill_level >= 6'd8) && (mp_cb_cur_ptr[6:3] != 4'd0) && (burst_length_c >= 5'd8)) || + ((mp_cb_fifo_fill_level >= 6'd4) && (mp_cb_cur_ptr[5:3] != 3'd0)) || + ((mp_cb_fifo_fill_level >= 6'd2) && (mp_cb_cur_ptr[4:3] != 2'd0)) || + ((mp_cb_fifo_fill_level > 6'd0) && (mp_cb_cur_ptr[3] != 1'd0)) || + ((mp_cb_fifo_fill_level > 6'd0) && mp_cb_fifo_flush) || + (mp_cb_fifo_fill_level >= burst_length_c); + assign viv_s8 = ((mp_cr_fifo_fill_level >= 6'd8) && (mp_cr_cur_ptr[6:3] != 4'd0) && (burst_length_c >= 5'd8)) || + ((mp_cr_fifo_fill_level >= 6'd4) && (mp_cr_cur_ptr[5:3] != 3'd0)) || + ((mp_cr_fifo_fill_level >= 6'd2) && (mp_cr_cur_ptr[4:3] != 2'd0)) || + ((mp_cr_fifo_fill_level > 6'd0) && (mp_cr_cur_ptr[3] != 1'd0)) || + ((mp_cr_fifo_fill_level > 6'd0) && mp_cr_fifo_flush) || + (mp_cr_fifo_fill_level >= burst_length_c); + always @(*) begin + if (next_sel) begin + viv_s3 = 1'b0; + viv_s4 = mp_fifo_select; + end else if (fifo_select_val == 1'b0) begin + if ( viv_s6 && + (~viv_s7 || (mp_y_fifo_fill_level >= mp_cb_fifo_fill_level)) && + (~viv_s8 || (mp_y_fifo_fill_level >= mp_cr_fifo_fill_level))) begin + viv_s3 = 1'b1; + viv_s4 = 2'b00; + end else if ( viv_s7 && + (~viv_s8 || (mp_cb_fifo_fill_level >= mp_cr_fifo_fill_level))) begin + viv_s3 = 1'b1; + viv_s4 = 2'b01; + end else if (viv_s8) begin + viv_s3 = 1'b1; + viv_s4 = 2'b10; + end else begin + viv_s3 = fifo_select_val; + viv_s4 = mp_fifo_select; + end + end else begin + viv_s3 = fifo_select_val; + viv_s4 = mp_fifo_select; + end + end +wire [8:0] viv_s9=viv_s4 ==2'b0 ? y_addr : viv_s4 ==2'b1 ? cb_addr: cr_addr; +wire [9:0] viv_s10=10'b1000000000-{1'b0,viv_s9}; + always @(*) begin + viv_s5 = burst_len; + if (fifo_select_val == 1'b0) begin + case (viv_s4) + 2'd0: begin + if (viv_s6) begin + if ( (burst_length_y == 5'd16) && + (viv_s0 >= 23'd16) && (mp_y_cur_ptr[6:3] == 4'd0) && + (mp_y_fifo_fill_level >= 6'd16)) begin + if(viv_s10<16) + viv_s5 = viv_s10; + else + viv_s5 = 5'd16; + end + else if (((burst_length_y == 5'd8) || (burst_length_y == 5'd16)) && + (viv_s0 >= 23'd8) && (mp_y_cur_ptr[5:3] == 3'd0) && + (mp_y_fifo_fill_level >= 6'd8)) begin + if(viv_s10<8) + viv_s5 = viv_s10; + else + viv_s5 = 5'd8; + end + else if ((viv_s0 >= 23'd4) && (mp_y_cur_ptr[4:3] == 2'd0) && + (mp_y_fifo_fill_level >= 6'd4)) begin + if(viv_s10<4) + viv_s5 = viv_s10; + else + viv_s5 = 5'd4; + end + else if ((viv_s0 >= 23'd2) && (mp_y_cur_ptr[3] == 1'd0) && + (mp_y_fifo_fill_level >= 6'd2)) begin + if(viv_s10<2) + viv_s5 = viv_s10; + else + viv_s5 = 5'd2; + end + else begin + viv_s5 = 5'd1; + end + end + end + 2'd1: begin + if (viv_s7) begin + if ( (burst_length_c == 5'd16) && + (viv_s1 >= 23'd16) && (mp_cb_cur_ptr[6:3] == 4'd0) && + (mp_cb_fifo_fill_level >= 6'd16)) begin + if(viv_s10<16) + viv_s5 = viv_s10; + else + viv_s5 = 5'd16; + end + else if (((burst_length_c == 5'd8) || (burst_length_c == 5'd16)) && + (viv_s1 >= 23'd8) && (mp_cb_cur_ptr[5:3] == 3'd0) && + (mp_cb_fifo_fill_level >= 6'd8)) begin + if(viv_s10<8) + viv_s5 = viv_s10; + else + viv_s5 = 5'd8; + end + else if ((viv_s1 >= 23'd4) && (mp_cb_cur_ptr[4:3] == 2'd0) && + (mp_cb_fifo_fill_level >= 6'd4)) begin + if(viv_s10<4) + viv_s5 = viv_s10; + else + viv_s5 = 5'd4; + end + else if ((viv_s1 >= 23'd2) && (mp_cb_cur_ptr[3] == 1'd0) && + (mp_cb_fifo_fill_level >= 6'd2)) begin + if(viv_s10<2) + viv_s5 = viv_s10; + else + viv_s5 = 5'd2; + end + else begin + viv_s5 = 5'd1; + end + end + end + default: begin + if (viv_s8) begin + if ( (burst_length_c == 5'd16) && + (viv_s2 >= 23'd16) && (mp_cr_cur_ptr[6:3] == 4'd0) && + (mp_cr_fifo_fill_level >= 6'd16)) begin + if(viv_s10<16) + viv_s5 = viv_s10; + else + viv_s5 = 5'd16; + end + else if (((burst_length_c == 5'd8) || (burst_length_c == 5'd16)) && + (viv_s2 >= 23'd8) && (mp_cr_cur_ptr[5:3] == 3'd0) && + (mp_cr_fifo_fill_level >= 6'd8)) begin + if(viv_s10<8) + viv_s5 = viv_s10; + else + viv_s5 = 5'd8; + end + else if ((viv_s2 >= 23'd4) && (mp_cr_cur_ptr[4:3] == 2'd0) && + (mp_cr_fifo_fill_level >= 6'd4)) begin + if(viv_s10<4) + viv_s5 = viv_s10; + else + viv_s5 = 5'd4; + end + else if ((viv_s2 >= 23'd2) && (mp_cr_cur_ptr[3] == 1'd0) && + (mp_cr_fifo_fill_level >= 6'd2)) begin + if(viv_s10<2) + viv_s5 = viv_s10; + else + viv_s5 = 5'd2; + end + else begin + viv_s5 = 5'd1; + end + end + end + endcase + end else begin + viv_s5 = burst_len; + end + end + always @(posedge m_hclk or negedge reset_m_hclk_n) begin + if (~reset_m_hclk_n) begin + mp_fifo_select <= 2'd0; + fifo_select_val <= 1'b0; + burst_len <= 5'd0; + end + else if (soft_rst_m_hclk) begin + mp_fifo_select <= 2'd0; + fifo_select_val <= 1'b0; + burst_len <= 5'd0; + end + else begin + mp_fifo_select <= viv_s4; + fifo_select_val <= viv_s3; + burst_len <= viv_s5; + end + end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_marvin_mi_out_arbit_sp.v b/ispyocto/rtl/ispyocto/vsisp_marvin_mi_out_arbit_sp.v new file mode 100644 index 0000000..1b1b5f4 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_marvin_mi_out_arbit_sp.v
@@ -0,0 +1,281 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_marvin_mi_out_arbit_sp + ( + m_hclk, + reset_m_hclk_n, + soft_rst_m_hclk, + burst_length_y, + burst_length_c, + sp_y_size, + sp_cb_size, + sp_cr_size, + sp_y_base_ad, + sp_cb_base_ad, + sp_cr_base_ad, + sp_y_fifo_fill_level, + sp_y_fifo_flush, + sp_cb_fifo_fill_level, + sp_cb_fifo_flush, + sp_cr_fifo_fill_level, + sp_cr_fifo_flush, + y_addr, + cb_addr, + cr_addr, + next_sel, + fifo_select_val, + sp_fifo_select, + burst_len, + sp_y_cur_ptr, + sp_cb_cur_ptr, + sp_cr_cur_ptr + ); +`include "vsisp_marvin_mi.vh" + input m_hclk; + input reset_m_hclk_n; + input soft_rst_m_hclk; + input [c_burst_len_bw-1:0] burst_length_y; + input [c_burst_len_bw-1:0] burst_length_c; + input [c_bufsize:3] sp_y_size; + input [c_bufsize-1:3] sp_cb_size; + input [c_bufsize-1:3] sp_cr_size; + input [11:3] sp_y_base_ad; + input [11:3] sp_cb_base_ad; + input [11:3] sp_cr_base_ad; + input [c_fifo_depth_bw-1:0] sp_y_fifo_fill_level; + input sp_y_fifo_flush; + input [c_fifo_depth_bw-1:0] sp_cb_fifo_fill_level; + input sp_cb_fifo_flush; + input [c_fifo_depth_bw-1:0] sp_cr_fifo_fill_level; + input sp_cr_fifo_flush; + input next_sel; + output fifo_select_val; + output [1:0] sp_fifo_select; + output [c_burst_len_bw-1:0] burst_len; + input [c_bufsize:3] sp_y_cur_ptr; + input [c_bufsize-1:3] sp_cb_cur_ptr; + input [c_bufsize-1:3] sp_cr_cur_ptr; + input [11:3] y_addr; + input [11:3] cb_addr; + input [11:3] cr_addr; + reg fifo_select_val; + reg [1:0] sp_fifo_select; + reg [c_burst_len_bw-1:0] burst_len; + wire [c_bufsize:3] viv_s0; + wire [c_bufsize-1:3] viv_s1; + wire [c_bufsize-1:3] viv_s2; + reg viv_s3; + reg [1:0] viv_s4; + reg [c_burst_len_bw-1:0] viv_s5; + integer v_loop; + wire viv_s6; + wire viv_s7; + wire viv_s8; + assign viv_s0 = sp_y_size - sp_y_cur_ptr; + assign viv_s1 = sp_cb_size - sp_cb_cur_ptr; + assign viv_s2 = sp_cr_size - sp_cr_cur_ptr; + assign viv_s6 = ((sp_y_fifo_fill_level >= 6'd8) && (sp_y_cur_ptr[6:3] != 4'd0) && (burst_length_y >= 5'd8)) || + ((sp_y_fifo_fill_level >= 6'd4) && (sp_y_cur_ptr[5:3] != 3'd0)) || + ((sp_y_fifo_fill_level >= 6'd2) && (sp_y_cur_ptr[4:3] != 2'd0)) || + ((sp_y_fifo_fill_level > 6'd0) && (sp_y_cur_ptr[3] != 1'd0)) || + ((sp_y_fifo_fill_level > 6'd0) && sp_y_fifo_flush) || + (sp_y_fifo_fill_level >= burst_length_y); + assign viv_s7 = ((sp_cb_fifo_fill_level >= 6'd8) && (sp_cb_cur_ptr[6:3] != 4'd0) && (burst_length_c >= 5'd8)) || + ((sp_cb_fifo_fill_level >= 6'd4) && (sp_cb_cur_ptr[5:3] != 3'd0)) || + ((sp_cb_fifo_fill_level >= 6'd2) && (sp_cb_cur_ptr[4:3] != 2'd0)) || + ((sp_cb_fifo_fill_level > 6'd0) && (sp_cb_cur_ptr[3] != 1'd0)) || + ((sp_cb_fifo_fill_level > 6'd0) && sp_cb_fifo_flush) || + (sp_cb_fifo_fill_level >= burst_length_c); + assign viv_s8 = ((sp_cr_fifo_fill_level >= 6'd8) && (sp_cr_cur_ptr[6:3] != 4'd0) && (burst_length_c >= 5'd8)) || + ((sp_cr_fifo_fill_level >= 6'd4) && (sp_cr_cur_ptr[5:3] != 3'd0)) || + ((sp_cr_fifo_fill_level >= 6'd2) && (sp_cr_cur_ptr[4:3] != 2'd0)) || + ((sp_cr_fifo_fill_level > 6'd0) && (sp_cr_cur_ptr[3] != 1'd0)) || + ((sp_cr_fifo_fill_level > 6'd0) && sp_cr_fifo_flush) || + (sp_cr_fifo_fill_level >= burst_length_c); + always @(*) begin + if (next_sel) begin + viv_s3 = 1'b0; + viv_s4 = sp_fifo_select; + end else if (fifo_select_val == 1'b0) begin + if ( viv_s6 && + (~viv_s7 || (sp_y_fifo_fill_level >= sp_cb_fifo_fill_level)) && + (~viv_s8 || (sp_y_fifo_fill_level >= sp_cr_fifo_fill_level))) begin + viv_s3 = 1'b1; + viv_s4 = 2'b00; + end else if ( viv_s7 && + (~viv_s8 || (sp_cb_fifo_fill_level >= sp_cr_fifo_fill_level))) begin + viv_s3 = 1'b1; + viv_s4 = 2'b01; + end else if (viv_s8) begin + viv_s3 = 1'b1; + viv_s4 = 2'b10; + end else begin + viv_s3 = fifo_select_val; + viv_s4 = sp_fifo_select; + end + end else begin + viv_s3 = fifo_select_val; + viv_s4 = sp_fifo_select; + end + end +wire [8:0] viv_s9=viv_s4 ==2'b0 ? y_addr : viv_s4 ==2'b1 ? cb_addr: cr_addr; +wire [9:0] viv_s10=10'b1000000000-{1'b0,viv_s9}; + always @(*) begin + viv_s5 = burst_len; + if (fifo_select_val == 1'b0) begin + case (viv_s4) + 2'd0: begin + if (viv_s6) begin + if ( (burst_length_y == 5'd16) && + (viv_s0 >= 23'd16) && (sp_y_cur_ptr[6:3] == 4'd0) && + (sp_y_fifo_fill_level >= 6'd16)) begin + if(viv_s10<16) + viv_s5 = viv_s10; + else + viv_s5 = 5'd16; + end + else if (((burst_length_y == 5'd8) || (burst_length_y == 5'd16)) && + (viv_s0 >= 23'd8) && (sp_y_cur_ptr[5:3] == 3'd0) && + (sp_y_fifo_fill_level >= 6'd8)) begin + if(viv_s10<8) + viv_s5 = viv_s10; + else + viv_s5 = 5'd8; + end + else if ((viv_s0 >= 23'd4) && (sp_y_cur_ptr[4:3] == 2'd0) && + (sp_y_fifo_fill_level >= 6'd4)) begin + if(viv_s10<4) + viv_s5 = viv_s10; + else + viv_s5 = 5'd4; + end + else if ((viv_s0 >= 23'd2) && (sp_y_cur_ptr[3] == 1'd0) && + (sp_y_fifo_fill_level >= 6'd2)) begin + if(viv_s10<2) + viv_s5 = viv_s10; + else + viv_s5 = 5'd2; + end + else begin + viv_s5 = 5'd1; + end + end + end + 2'd1: begin + if (viv_s7) begin + if ( (burst_length_c == 5'd16) && + (viv_s1 >= 23'd16) && (sp_cb_cur_ptr[6:3] == 4'd0) && + (sp_cb_fifo_fill_level >= 6'd16)) begin + if(viv_s10<16) + viv_s5 = viv_s10; + else + viv_s5 = 5'd16; + end + else if (((burst_length_c == 5'd8) || (burst_length_c == 5'd16)) && + (viv_s1 >= 23'd8) && (sp_cb_cur_ptr[5:3] == 3'd0) && + (sp_cb_fifo_fill_level >= 6'd8)) begin + if(viv_s10<8) + viv_s5 = viv_s10; + else + viv_s5 = 5'd8; + end + else if ((viv_s1 >= 23'd4) && (sp_cb_cur_ptr[4:3] == 2'd0) && + (sp_cb_fifo_fill_level >= 6'd4)) begin + if(viv_s10<4) + viv_s5 = viv_s10; + else + viv_s5 = 5'd4; + end + else if ((viv_s1 >= 23'd2) && (sp_cb_cur_ptr[3] == 1'd0) && + (sp_cb_fifo_fill_level >= 6'd2)) begin + if(viv_s10<2) + viv_s5 = viv_s10; + else + viv_s5 = 5'd2; + end + else begin + viv_s5 = 5'd1; + end + end + end + default: begin + if (viv_s8) begin + if ( (burst_length_c == 5'd16) && + (viv_s2 >= 23'd16) && (sp_cr_cur_ptr[6:3] == 4'd0) && + (sp_cr_fifo_fill_level >= 6'd16)) begin + if(viv_s10<16) + viv_s5 = viv_s10; + else + viv_s5 = 5'd16; + end + else if (((burst_length_c == 5'd8) || (burst_length_c == 5'd16)) && + (viv_s2 >= 23'd8) && (sp_cr_cur_ptr[5:3] == 3'd0) && + (sp_cr_fifo_fill_level >= 6'd8)) begin + if(viv_s10<8) + viv_s5 = viv_s10; + else + viv_s5 = 5'd8; + end + else if ((viv_s2 >= 23'd4) && (sp_cr_cur_ptr[4:3] == 2'd0) && + (sp_cr_fifo_fill_level >= 6'd4)) begin + if(viv_s10<4) + viv_s5 = viv_s10; + else + viv_s5 = 5'd4; + end + else if ((viv_s2 >= 23'd2) && (sp_cr_cur_ptr[3] == 1'd0) && + (sp_cr_fifo_fill_level >= 6'd2)) begin + if(viv_s10<2) + viv_s5 = viv_s10; + else + viv_s5 = 5'd2; + end + else begin + viv_s5 = 5'd1; + end + end + end + endcase + end else begin + viv_s5 = burst_len; + end + end + always @(posedge m_hclk or negedge reset_m_hclk_n) begin + if (~reset_m_hclk_n) begin + sp_fifo_select <= 2'd0; + fifo_select_val <= 1'b0; + burst_len <= 5'd0; + end + else if (soft_rst_m_hclk) begin + sp_fifo_select <= 2'd0; + fifo_select_val <= 1'b0; + burst_len <= 5'd0; + end + else begin + sp_fifo_select <= viv_s4; + fifo_select_val <= viv_s3; + burst_len <= viv_s5; + end + end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_marvin_mi_out_bp.v b/ispyocto/rtl/ispyocto/vsisp_marvin_mi_out_bp.v new file mode 100644 index 0000000..7b08e9a --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_marvin_mi_out_bp.v
@@ -0,0 +1,601 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_marvin_mi_out_bp + ( + m_hclk, + reset_m_hclk_n, + soft_rst_m_hclk, + mp_fifo_read64, + mp_fifo_select, + mp_fifo_data, + mp_fifo_h_end, + mp_fifo_v_end, + mp_y_fifo_fill_level, + mp_y_fifo_flush, + mp_cb_fifo_fill_level, + mp_cb_fifo_flush, + mp_cr_fifo_fill_level, + mp_cr_fifo_flush, + soft_upd, + skip, + mp_enable, + jpeg_enable, + raw_enable, + dp_enable, + mp_write_format, + byte_swap, + init_base_en, + init_offset_en, + mp_pingpong_en, + burst_len_lum, + burst_len_chrom, + stat_mp_enable_out, + stat_jpeg_enable_out, + stat_raw_enable_out, + stat_dp_enable_out, + mp_r_base_ad, + mp_r_size, + mp_r_offs_cnt, + mp_r_base_ad_init, + mp_r_base_ad_init2, + mp_r_size_init, + mp_r_offs_cnt_init, + mp_r_offs_cnt_start, + mp_r_irq_offs_init, + mp_r_irq_offs, + mp_gr_base_ad, + mp_gr_size, + mp_gr_offs_cnt, + mp_gr_base_ad_init, + mp_gr_base_ad_init2, + mp_gr_size_init, + mp_gr_offs_cnt_init, + mp_gr_offs_cnt_start, + mp_gb_base_ad, + mp_gb_size, + mp_gb_offs_cnt, + mp_gb_base_ad_init, + mp_gb_base_ad_init2, + mp_gb_size_init, + mp_gb_offs_cnt_init, + mp_gb_offs_cnt_start, + mp_b_base_ad, + mp_b_size, + mp_b_offs_cnt, + mp_b_base_ad_init, + mp_b_base_ad_init2, + mp_b_size_init, + mp_b_offs_cnt_init, + mp_b_offs_cnt_start, + mp_addr_cur_y, + mp_addr_cur_cb, + mp_addr_cur_cr, + handshake_en, + stat_mp_frame_end, + stat_mblk_line, + stat_fill_mp_r, + stat_wrap_mp_r, + stat_wrap_mp_gr, + stat_wrap_mp_gb, + stat_wrap_mp_b, + cfg_in_update_mp, + cfg_out_update_mp, + vci_out_m1_cmdval, + vci_out_m1_plen, + vci_out_m1_eop, + vci_out_m1_address, + vci_out_m1_wdata, + vci_out_m1_be, + vci_out_m1_cmd, + vci_out_m1_const, + vci_out_m1_contig, + vci_out_m1_wrap, + vci_out_m1_cmdack, + vci_out_m1_rspval, + vci_out_m1_reop, + vci_out_m1_rspack, + last_pixel_sig_en, + last_pixel_m1_req, + last_pixel_m1_ack, + mp_byte_swap, + mp_output_format, + mp_y_llength, + cfg_upd_double, + stat_skip_active, + data_mode_en, + plnr_wrt, + val_1st_pxl, + bayer_pat, + line_tgl_en, + mp_line_sens + ); +`include "vsisp_marvin_mi.vh" + input mp_line_sens; + output cfg_upd_double; + output stat_skip_active; + input data_mode_en; + input plnr_wrt; + input val_1st_pxl; + input [1:0] bayer_pat; + output line_tgl_en; + input [3:0] mp_output_format; + input [14:0] mp_y_llength; + input [2:0] mp_byte_swap; + input m_hclk; + input reset_m_hclk_n; + input soft_rst_m_hclk; + output mp_fifo_read64; + output [1:0] mp_fifo_select; + input [63:0] mp_fifo_data; + input mp_fifo_h_end; + input mp_fifo_v_end; + input [c_fifo_depth_bw-1:0] mp_y_fifo_fill_level; + input mp_y_fifo_flush; + input [c_fifo_depth_bw-1:0] mp_cb_fifo_fill_level; + input mp_cb_fifo_flush; + input [c_fifo_depth_bw-1:0] mp_cr_fifo_fill_level; + input mp_cr_fifo_flush; + input soft_upd; + input skip; + input mp_enable; + input jpeg_enable; + input raw_enable; + input dp_enable; + input [1:0] mp_write_format; + input byte_swap; + input init_base_en; + input init_offset_en; + input mp_pingpong_en; + input [1:0] burst_len_lum; + input [1:0] burst_len_chrom; + output stat_mp_enable_out; + output stat_jpeg_enable_out; + output stat_raw_enable_out; + output stat_dp_enable_out; + input [c_mi_data_addr:0] mp_addr_cur_y; + input [c_mi_data_addr:0] mp_addr_cur_cb; + input [c_mi_data_addr:0] mp_addr_cur_cr; + input handshake_en; + input [c_mi_data_addr+3:3] mp_r_base_ad_init; + input [c_mi_data_addr+3:3] mp_r_base_ad_init2; + input [c_mi_data_addr:3] mp_r_size_init; + input [c_mi_data_addr:3] mp_r_offs_cnt_init; + input [c_mi_data_addr:3] mp_r_irq_offs_init; + output [c_mi_data_addr+3:3] mp_r_base_ad; + output [c_mi_data_addr:3] mp_r_size; + output [c_mi_data_addr:3] mp_r_offs_cnt; + output [c_mi_data_addr:3] mp_r_offs_cnt_start; + output [c_mi_data_addr:3] mp_r_irq_offs; + input [c_mi_data_addr+3:3] mp_gr_base_ad_init; + input [c_mi_data_addr+3:3] mp_gr_base_ad_init2; + input [c_mi_data_addr:3] mp_gr_size_init; + input [c_mi_data_addr:3] mp_gr_offs_cnt_init; + output [c_mi_data_addr+3:3] mp_gr_base_ad; + output wire [c_mi_data_addr:3] mp_gr_size; + output [c_mi_data_addr:3] mp_gr_offs_cnt; + output [c_mi_data_addr:3] mp_gr_offs_cnt_start; + input [c_mi_data_addr+3:3] mp_gb_base_ad_init; + input [c_mi_data_addr+3:3] mp_gb_base_ad_init2; + input [c_mi_data_addr:3] mp_gb_size_init; + input [c_mi_data_addr:3] mp_gb_offs_cnt_init; + output [c_mi_data_addr+3:3] mp_gb_base_ad; + output [c_mi_data_addr:3] mp_gb_size; + output [c_mi_data_addr:3] mp_gb_offs_cnt; + output [c_mi_data_addr:3] mp_gb_offs_cnt_start; + input [c_mi_data_addr+3:3] mp_b_base_ad_init; + input [c_mi_data_addr+3:3] mp_b_base_ad_init2; + input [c_mi_data_addr:3] mp_b_size_init; + input [c_mi_data_addr:3] mp_b_offs_cnt_init; + output [c_mi_data_addr+3:3] mp_b_base_ad; + output wire [c_mi_data_addr:3] mp_b_size; + output [c_mi_data_addr:3] mp_b_offs_cnt; + output [c_mi_data_addr:3] mp_b_offs_cnt_start; + output stat_mp_frame_end; + output stat_mblk_line; + output stat_fill_mp_r; + output stat_wrap_mp_r; + output stat_wrap_mp_gr; + output stat_wrap_mp_gb; + output stat_wrap_mp_b; + input cfg_in_update_mp; + output cfg_out_update_mp; + output vci_out_m1_cmdval; + output [8:0] vci_out_m1_plen; + output vci_out_m1_eop; + output [c_mi_data_addr+3:3] vci_out_m1_address; + output [63:0] vci_out_m1_wdata; + output [7:0] vci_out_m1_be; + output [1:0] vci_out_m1_cmd; + output vci_out_m1_const; + output vci_out_m1_contig; + output vci_out_m1_wrap; + input vci_out_m1_cmdack; + input vci_out_m1_rspval; + input vci_out_m1_reop; + output vci_out_m1_rspack; + output last_pixel_m1_req; + input last_pixel_m1_ack; + input last_pixel_sig_en; +assign mp_b_size = {c_mi_data_addr-2{1'b0}}; +assign mp_gr_size = {c_mi_data_addr-2{1'b0}}; + wire [c_mi_data_addr+3:3] viv_s0; + wire [63:0] viv_s1; + wire [c_mi_data_addr:3] viv_s2; + wire [c_mi_data_addr-1:3] viv_s3; + wire [c_mi_data_addr:3] viv_s4; + wire [c_mi_data_addr-1:3] viv_s5; + wire [c_mi_data_addr+3:3] viv_s6; + wire [c_mi_data_addr+3:3] viv_s7; + wire [c_mi_data_addr+3:3] viv_s8; + wire viv_s9; + wire cfg_out_update_mp; + wire stat_skip_active; + wire viv_s10; + wire [c_burst_len_bw-1:0] viv_s11; + reg [c_burst_len_bw-1:0] viv_s12; + reg [c_burst_len_bw-1:0] viv_s13; + wire [c_mi_data_addr:3] viv_s14; + wire [c_mi_data_addr-1:3] viv_s15; + wire [c_mi_data_addr-1:3] viv_s16; + wire viv_s17; + wire [3:0] viv_s18; + wire [127:0] viv_s19; + wire [127:0] viv_s20; +wire [c_mi_data_addr+3:3] viv_s21; +wire [c_mi_data_addr+3:3] viv_s22; +wire [c_mi_data_addr+3:3] viv_s23; +wire [c_mi_data_addr+3:3] viv_s24; + vsisp_marvin_mi_out_updlogic_mp u_marvin_mi_out_updlogic_mp + ( + .m_hclk (m_hclk), + .reset_m_hclk_n (reset_m_hclk_n), + .soft_rst_m_hclk (soft_rst_m_hclk), + .soft_upd (soft_upd), + .skip (skip), + .mp_enable (mp_enable), + .jpeg_enable (jpeg_enable), + .raw_enable (raw_enable), + .dp_enable (dp_enable), + .mp_write_format (mp_write_format), + .stat_mp_enable_out (stat_mp_enable_out), + .stat_jpeg_enable_out (stat_jpeg_enable_out), + .stat_raw_enable_out (stat_raw_enable_out), + .stat_dp_enable_out (stat_dp_enable_out), + .cfg_in_update_mp (cfg_in_update_mp), + .mp_fifo_h_end (mp_fifo_h_end), + .mp_fifo_v_end (mp_fifo_v_end), + .mp_fifo_read64 (mp_fifo_read64), + .mp_fifo_select (mp_fifo_select), + .stat_mp_frame_end (stat_mp_frame_end), + .mp_frame_end (viv_s9), + .cfg_out_update_mp (cfg_out_update_mp), + .stat_skip_active (stat_skip_active) + ); + always @(burst_len_lum)begin + if ((burst_len_lum == 2'b10) && (c_bursts_supported >= 5'd16)) + viv_s12 = 5'd16; + else if ((burst_len_lum > 2'b00) && (c_bursts_supported >= 5'd8)) + viv_s12 = 5'd8; + else + viv_s12 = 5'd4; + end + always @(burst_len_chrom)begin + if ((burst_len_chrom == 2'b10) && (c_bursts_supported >= 5'd16)) + viv_s13 = 5'd16; + else if ((burst_len_chrom > 2'b00) && (c_bursts_supported >= 5'd8)) + viv_s13 = 5'd8; + else + viv_s13 = 5'd4; + end + vsisp_marvin_mi_out_arbit_mp u_marvin_mi_out_arbit_mp + ( + .m_hclk (m_hclk), + .reset_m_hclk_n (reset_m_hclk_n), + .soft_rst_m_hclk (soft_rst_m_hclk), + .burst_length_y (viv_s12), + .burst_length_c (viv_s13), + .mp_y_size (mp_r_size), + .mp_cb_size (mp_r_size[c_mi_data_addr-1:3]), + .mp_cr_size (mp_r_size[c_mi_data_addr-1:3]), + .mp_y_fifo_fill_level (mp_y_fifo_fill_level), + .mp_y_fifo_flush (mp_y_fifo_flush), + .mp_cb_fifo_fill_level(mp_cb_fifo_fill_level), + .mp_cb_fifo_flush (mp_cb_fifo_flush), + .mp_cr_fifo_fill_level(mp_cr_fifo_fill_level), + .mp_cr_fifo_flush (mp_cr_fifo_flush), + .y_addr (viv_s6[11:3]), + .cb_addr (viv_s7[11:3]), + .cr_addr (viv_s8[11:3]), + .next_sel (viv_s17), + .fifo_select_val (viv_s10), + .mp_fifo_select (mp_fifo_select), + .burst_len (viv_s11), + .mp_y_cur_ptr (viv_s14), + .mp_cb_cur_ptr (viv_s15), + .mp_cr_cur_ptr (viv_s16) + ); + wire viv_s25; + wire viv_s26; + wire viv_s27; + wire line_tgl_en; + wire viv_s28 = viv_s26 | viv_s27; + wire viv_s29 = mp_fifo_read64 && mp_fifo_h_end && plnr_wrt; + wire viv_s30 = viv_s29 && mp_fifo_select==2'b00; + wire viv_s31 = viv_s29 && mp_fifo_select==2'b01; + wire viv_s32 = viv_s29 & mp_fifo_v_end; + assign y_hend_r_d = viv_s30 & ~viv_s28 ? 1'b1: line_tgl_en? 1'b0 : viv_s26; + assign cb_hend_r_d= viv_s31 & ~viv_s28 ? 1'b1: line_tgl_en? 1'b0 : viv_s27; + vsisp_dreg_en_1d #(1,1'b0) y_hend_r_reg (.clk(m_hclk), .reset_n(reset_m_hclk_n), .soft_reset(soft_rst_m_hclk), .out(viv_s26), .in(y_hend_r_d), .en(1'b1)); + vsisp_dreg_en_1d #(1,1'b0) cb_hend_r_reg (.clk(m_hclk), .reset_n(reset_m_hclk_n), .soft_reset(soft_rst_m_hclk), .out(viv_s27), .in(cb_hend_r_d), .en(1'b1)); + assign line_tgl_en = viv_s29 && viv_s28; + vsisp_dreg_en_1d #(1,1'b0) line_tgl_reg (.clk(m_hclk), .reset_n(reset_m_hclk_n), .soft_reset(soft_rst_m_hclk), .out(viv_s25), .in(~viv_s25&~viv_s32), .en(line_tgl_en)); + wire [c_fifo_depth_bw-1:0] viv_s33 ; + wire [c_fifo_depth_bw-1:0] viv_s34 ; + wire [c_fifo_depth_bw-1:0] viv_s35 ; + assign viv_s33 = ~viv_s26 ? mp_y_fifo_fill_level : {c_fifo_depth_bw{1'b0}}; + assign viv_s34 = ~viv_s27 ? mp_cb_fifo_fill_level : {c_fifo_depth_bw{1'b0}}; + assign viv_s35 = {c_fifo_depth_bw{1'b0}}; + wire viv_s36 = viv_s25 & plnr_wrt; + wire viv_s37 = mp_fifo_read64 && ~viv_s36; + wire viv_s38 = mp_fifo_read64 && viv_s36; + assign mp_gr_offs_cnt[c_mi_data_addr]=1'b0; + assign mp_b_offs_cnt[c_mi_data_addr] =1'b0; + assign mp_gr_offs_cnt_start[c_mi_data_addr]=1'b0; + assign mp_b_offs_cnt_start[c_mi_data_addr] =1'b0; + vsisp_marvin_mi_out_addrgen_mp u_marvin_mi_out_addrgen_mp_even_line + ( + .mp_line_sens (mp_line_sens), + .mp_output_format (mp_output_format), + .mp_y_llength (mp_y_llength), + .m_hclk (m_hclk), + .reset_m_hclk_n (reset_m_hclk_n), + .soft_rst_m_hclk (soft_rst_m_hclk), + .mp_fifo_h_end (mp_fifo_h_end), + .mp_fifo_v_end (mp_fifo_v_end&(~(data_mode_en & ~stat_skip_active))), + .soft_upd (soft_upd), + .mp_write_format (mp_write_format), + .init_base_en (init_base_en), + .init_offset_en (init_offset_en), + .mp_pingpong_en (mp_pingpong_en), + .mp_y_base_ad (mp_r_base_ad), + .mp_y_size (mp_r_size), + .mp_y_offs_cnt (mp_r_offs_cnt), + .mp_y_base_ad_init (mp_r_base_ad_init), + .mp_y_base_ad_init2 (mp_r_base_ad_init2), + .mp_y_size_init (mp_r_size_init), + .mp_y_offs_cnt_init (mp_r_offs_cnt_init), + .mp_y_offs_cnt_start (mp_r_offs_cnt_start), + .mp_y_irq_offs_init (mp_r_irq_offs_init), + .mp_y_irq_offs (mp_r_irq_offs), + .mp_cb_base_ad (mp_gr_base_ad), + .mp_cb_size (), + .mp_cb_offs_cnt (mp_gr_offs_cnt[c_mi_data_addr-1:3]), + .mp_cb_base_ad_init (mp_gr_base_ad_init), + .mp_cb_base_ad_init2 (mp_gr_base_ad_init2), + .mp_cb_size_init (mp_gr_size_init[c_mi_data_addr-1:3]), + .mp_cb_offs_cnt_init (mp_gr_offs_cnt_init[c_mi_data_addr-1:3]), + .mp_cb_offs_cnt_start(mp_gr_offs_cnt_start[c_mi_data_addr-1:3]), + .mp_cr_base_ad (), + .mp_cr_size (), + .mp_cr_offs_cnt (), + .mp_cr_base_ad_init ({c_mi_data_addr+3-3+1{1'b0}}), + .mp_cr_base_ad_init2 ({c_mi_data_addr+3-3+1{1'b0}}), + .mp_cr_size_init ({c_mi_data_addr-1-3+1{1'b0}}), + .mp_cr_offs_cnt_init ({c_mi_data_addr-1-3+1{1'b0}}), + .mp_cr_offs_cnt_start(), + .vci_out_m1_rspval (vci_out_m1_rspval), + .vci_out_m1_reop (vci_out_m1_reop), + .stat_mblk_line (stat_mblk_line), + .stat_fill_mp_y (stat_fill_mp_r), + .stat_wrap_mp_y (stat_wrap_mp_r), + .stat_wrap_mp_cb (stat_wrap_mp_gr), + .stat_wrap_mp_cr (), + .mp_fifo_read64 (viv_s37), + .mp_fifo_select (mp_fifo_select), + .cfg_out_update_mp (cfg_out_update_mp), + .stat_skip_active (stat_skip_active), + .mp_y_cur_ptr (viv_s2), + .mp_cb_cur_ptr (viv_s3), + .mp_cr_cur_ptr (), + .cfg_upd_double (cfg_upd_double) + ); + vsisp_marvin_mi_out_addrgen_mp u_marvin_mi_out_addrgen_mp_odd_line + ( + .mp_line_sens (mp_line_sens), + .mp_output_format (mp_output_format), + .mp_y_llength (mp_y_llength), + .m_hclk (m_hclk), + .reset_m_hclk_n (reset_m_hclk_n), + .soft_rst_m_hclk (soft_rst_m_hclk), + .mp_fifo_h_end (mp_fifo_h_end), + .mp_fifo_v_end (mp_fifo_v_end), + .soft_upd (soft_upd), + .mp_write_format (mp_write_format), + .init_base_en (init_base_en), + .init_offset_en (init_offset_en), + .mp_pingpong_en (mp_pingpong_en), + .mp_y_base_ad (mp_gb_base_ad), + .mp_y_size (mp_gb_size), + .mp_y_offs_cnt (mp_gb_offs_cnt), + .mp_y_base_ad_init (mp_gb_base_ad_init), + .mp_y_base_ad_init2 (mp_gb_base_ad_init2), + .mp_y_size_init (mp_gb_size_init), + .mp_y_offs_cnt_init (mp_gb_offs_cnt_init), + .mp_y_offs_cnt_start (mp_gb_offs_cnt_start), + .mp_y_irq_offs_init (mp_r_irq_offs_init), + .mp_y_irq_offs (), + .mp_cb_base_ad (mp_b_base_ad), + .mp_cb_size (), + .mp_cb_offs_cnt (mp_b_offs_cnt[c_mi_data_addr-1:3]), + .mp_cb_base_ad_init (mp_b_base_ad_init), + .mp_cb_base_ad_init2 (mp_b_base_ad_init2), + .mp_cb_size_init (mp_b_size_init[c_mi_data_addr-1:3]), + .mp_cb_offs_cnt_init (mp_b_offs_cnt_init[c_mi_data_addr-1:3]), + .mp_cb_offs_cnt_start(mp_b_offs_cnt_start[c_mi_data_addr-1:3]), + .mp_cr_base_ad (), + .mp_cr_size (), + .mp_cr_offs_cnt (), + .mp_cr_base_ad_init ({c_mi_data_addr+3-3+1{1'b0}}), + .mp_cr_base_ad_init2 ({c_mi_data_addr+3-3+1{1'b0}}), + .mp_cr_size_init ({c_mi_data_addr-1-3+1{1'b0}}), + .mp_cr_offs_cnt_init ({c_mi_data_addr-1-3+1{1'b0}}), + .mp_cr_offs_cnt_start(), + .vci_out_m1_rspval (vci_out_m1_rspval), + .vci_out_m1_reop (vci_out_m1_reop), + .stat_mblk_line (stat_mblk_line_odd), + .stat_fill_mp_y (stat_fill_mp_gb), + .stat_wrap_mp_y (stat_wrap_mp_gb), + .stat_wrap_mp_cb (stat_wrap_mp_b), + .stat_wrap_mp_cr (), + .mp_fifo_read64 (viv_s38), + .mp_fifo_select (mp_fifo_select), + .cfg_out_update_mp (cfg_out_update_mp), + .stat_skip_active (stat_skip_active), + .mp_y_cur_ptr (viv_s4), + .mp_cb_cur_ptr (viv_s5), + .mp_cr_cur_ptr (), + .cfg_upd_double () + ); + vsisp_marvin_mi_out_ctrl_mp u_marvin_mi_out_ctrl_mp + ( + .m_hclk (m_hclk), + .reset_m_hclk_n (reset_m_hclk_n), + .soft_rst_m_hclk (soft_rst_m_hclk), + .mp_fifo_read64 (mp_fifo_read64), + .stat_mp_frame_end (stat_mp_frame_end), + .vci_out_m1_cmdval (vci_out_m1_cmdval), + .vci_out_m1_plen (vci_out_m1_plen), + .vci_out_m1_eop (vci_out_m1_eop), + .vci_out_m1_address (vci_out_m1_address), + .vci_out_m1_wdata (vci_out_m1_wdata), + .vci_out_m1_be (vci_out_m1_be), + .vci_out_m1_cmd (vci_out_m1_cmd), + .vci_out_m1_const (vci_out_m1_const), + .vci_out_m1_contig (vci_out_m1_contig), + .vci_out_m1_wrap (vci_out_m1_wrap), + .vci_out_m1_cmdack (vci_out_m1_cmdack), + .vci_out_m1_rspval (vci_out_m1_rspval), + .vci_out_m1_reop (vci_out_m1_reop), + .vci_out_m1_rspack (vci_out_m1_rspack), + .fifo_select_val (viv_s10), + .burst_len (viv_s11), + .address (viv_s0), + .data (viv_s1), + .stat_skip_active (stat_skip_active), + .mp_frame_end (viv_s9), + .next_sel (viv_s17), + .stat_mp_enable_in (stat_mp_enable_out), + .stat_jpeg_enable_in (stat_jpeg_enable_out), + .stat_raw_enable_in (stat_raw_enable_out), + .last_pixel_sig_en (last_pixel_sig_en), + .last_pixel_m1_req (last_pixel_m1_req), + .last_pixel_m1_ack (last_pixel_m1_ack) + ); + assign viv_s14=handshake_en ? mp_addr_cur_y[c_mi_data_addr-3:0]: viv_s36==1'b0 ? viv_s2: viv_s4; + assign viv_s15=handshake_en ? mp_addr_cur_cb[c_mi_data_addr-4:0]:viv_s36==1'b0 ? viv_s3: viv_s5; + assign viv_s16=handshake_en ? mp_addr_cur_cr[c_mi_data_addr-4:0]: {c_mi_data_addr-4+1{1'b0}} ; + assign viv_s6 = (viv_s36==1'b0 ? viv_s21:viv_s23) + {3'b0, viv_s14}; + assign viv_s7 = (viv_s36==1'b0 ? viv_s22:viv_s24) + {4'b0, viv_s15}; + assign viv_s8 = {c_mi_data_addr+1{1'b0}}; + assign viv_s0 = ((mp_fifo_select == 2'd0) ? viv_s6 : 29'h0) | + ((mp_fifo_select == 2'd1) ? viv_s7 : 29'h0) | + ((mp_fifo_select == 2'd2) ? viv_s8 : 29'h0); + assign viv_s18[3:0] = {1'b0,mp_byte_swap[2:0]}; + assign viv_s19[127:0] = {64'h0,mp_fifo_data[63:0]}; + assign viv_s1[63:0] = viv_s20[63:0]; + vsisp_marvin_mi_swap u_marvin_mi_swap(.swap_vector (viv_s18[3:0]), + .data_to_swap (viv_s19[127:0]), + .swapped_data (viv_s20[127:0])); + parameter INIT=0, + OP_UP=1, + OP_WAIT_END_VAL=2; + wire [3:0] viv_s39; + reg [3:0] viv_s40; + reg [1:0] viv_s41; + reg [1:0] viv_s42; + wire [1:0] viv_s43; + reg viv_s44; + reg viv_s45; + reg [1:0] viv_s46; + wire [1:0] viv_s47; + vsisp_dreg_en_1d #(2,2'b0) u_bayer_pat_stat (.clk(m_hclk), .reset_n(reset_m_hclk_n), .soft_reset(soft_rst_m_hclk), .out(viv_s43), .in(viv_s42), .en(1'b1)); + vsisp_dreg_en_1d #(2,2'b0) u_bayer_pat_lock (.clk(m_hclk), .reset_n(reset_m_hclk_n), .soft_reset(soft_rst_m_hclk), .out(viv_s47), .in(viv_s46), .en(1'b1)); + vsisp_dreg_en_1d #(4,4'd0) u_op_cs (.clk(m_hclk), .reset_n(reset_m_hclk_n), .soft_reset(soft_rst_m_hclk), .out(viv_s39), .in(viv_s40), .en(1'b1)); + vsisp_dreg_en_1d #(1,1'd0) u_frame_end_lock (.clk(m_hclk), .reset_n(reset_m_hclk_n), .soft_reset(soft_rst_m_hclk), .out(frame_end_lock), .in(viv_s44), .en(1'b1)); + vsisp_dreg_en_1d #(1,1'd0) u_val_1st_pxl_lock (.clk(m_hclk), .reset_n(reset_m_hclk_n), .soft_reset(soft_rst_m_hclk), .out(val_1st_pxl_lock), .in(viv_s45), .en(1'b1)); + vsisp_dreg_en_2d #(1,1'd0) u_val_1st_pxl_sync2 (.clk(m_hclk), .reset_n(reset_m_hclk_n), .soft_reset(soft_rst_m_hclk), .out(val_1st_pxl_sync2), .in(val_1st_pxl), .en(1'b1)); + vsisp_dreg_en_1d #(1,1'd0) u_val_1st_pxl_sync3 (.clk(m_hclk), .reset_n(reset_m_hclk_n), .soft_reset(soft_rst_m_hclk), .out(val_1st_pxl_sync3), .in(val_1st_pxl_sync2), .en(1'b1)); + wire viv_s48 = val_1st_pxl_sync3 ^ val_1st_pxl_sync2; + always @(*)begin + viv_s45 = val_1st_pxl_lock; + viv_s44 = frame_end_lock; + viv_s42 = viv_s43; + viv_s46 = viv_s47; + if(viv_s48)begin + viv_s45=1'b1; + viv_s46 = bayer_pat; + end + viv_s40 = viv_s39; + case(viv_s39) + INIT:if(val_1st_pxl_lock)begin + viv_s45 = 1'b0; + viv_s40 = OP_UP; + end + OP_UP:begin + viv_s42 = viv_s47; + viv_s40 = OP_WAIT_END_VAL; + end + OP_WAIT_END_VAL:begin + if(stat_mp_frame_end)begin + viv_s44 = 1'b1; + end + else if(frame_end_lock & val_1st_pxl_lock)begin + viv_s40 = OP_UP; + viv_s44 = 1'b0; + viv_s45 = 1'b0; + end + end + default:begin + viv_s40 = INIT; + end + endcase + end + assign viv_s21 = mp_write_format==2'b10 ? mp_r_base_ad: + viv_s43==2'b00 ? mp_r_base_ad: + viv_s43==2'b01 ? mp_gr_base_ad: + viv_s43==2'b10 ? mp_gb_base_ad: + viv_s43==2'b11 ? mp_b_base_ad: mp_r_base_ad; + assign viv_s22= viv_s43==2'b00 ? mp_gr_base_ad: + viv_s43==2'b01 ? mp_r_base_ad: + viv_s43==2'b10 ? mp_b_base_ad: + viv_s43==2'b11 ? mp_gb_base_ad: mp_gr_base_ad; + assign viv_s23= viv_s43==2'b00 ? mp_gb_base_ad: + viv_s43==2'b01 ? mp_b_base_ad: + viv_s43==2'b10 ? mp_r_base_ad: + viv_s43==2'b11 ? mp_gr_base_ad: mp_gb_base_ad; + assign viv_s24 = viv_s43==2'b00 ? mp_b_base_ad: + viv_s43==2'b01 ? mp_gb_base_ad: + viv_s43==2'b10 ? mp_gr_base_ad: + viv_s43==2'b11 ? mp_r_base_ad: mp_b_base_ad; +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_marvin_mi_out_ctrl_mp.v b/ispyocto/rtl/ispyocto/vsisp_marvin_mi_out_ctrl_mp.v new file mode 100644 index 0000000..dd04a7b --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_marvin_mi_out_ctrl_mp.v
@@ -0,0 +1,299 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_marvin_mi_out_ctrl_mp + ( + m_hclk, + reset_m_hclk_n, + soft_rst_m_hclk, + mp_fifo_read64, + stat_mp_frame_end, + vci_out_m1_cmdval, + vci_out_m1_plen, + vci_out_m1_eop, + vci_out_m1_address, + vci_out_m1_wdata, + vci_out_m1_be, + vci_out_m1_cmd, + vci_out_m1_const, + vci_out_m1_contig, + vci_out_m1_wrap, + vci_out_m1_cmdack, + vci_out_m1_rspval, + vci_out_m1_reop, + vci_out_m1_rspack, + fifo_select_val, + burst_len, + address, + data, + stat_skip_active, + mp_frame_end, + next_sel, + stat_mp_enable_in, + stat_jpeg_enable_in, + stat_raw_enable_in, + last_pixel_sig_en, + last_pixel_m1_req, + last_pixel_m1_ack + ); +`include "vsisp_marvin_mi.vh" + input m_hclk; + input reset_m_hclk_n; + input soft_rst_m_hclk; + output mp_fifo_read64; + reg mp_fifo_read64; + output stat_mp_frame_end; + reg stat_mp_frame_end; + reg viv_s0; + reg viv_s1; + output vci_out_m1_cmdval; + output [8:0] vci_out_m1_plen; + output vci_out_m1_eop; + output [c_mi_data_addr+3:3] vci_out_m1_address; + output [63:0] vci_out_m1_wdata; + output [7:0] vci_out_m1_be; + output [1:0] vci_out_m1_cmd; + output vci_out_m1_const; + output vci_out_m1_contig; + output vci_out_m1_wrap; + input vci_out_m1_cmdack; + input vci_out_m1_rspval; + input vci_out_m1_reop; + output vci_out_m1_rspack; + reg vci_out_m1_cmdval; + reg vci_out_m1_eop; + reg [c_mi_data_addr+3:3] vci_out_m1_address; + reg [63:0] vci_out_m1_wdata; + input fifo_select_val; + input [c_burst_len_bw-1:0] burst_len; + input [c_mi_data_addr+3:3] address; + input [63:0] data; + input stat_skip_active; + input mp_frame_end; + output next_sel; + input stat_mp_enable_in; + input stat_jpeg_enable_in; + input stat_raw_enable_in; + reg next_sel; + output last_pixel_m1_req; + input last_pixel_m1_ack; + input last_pixel_sig_en; + reg last_pixel_m1_req; + reg viv_s2; + reg viv_s3; + reg viv_s4; + reg [2:0] viv_s5; + reg [2:0] viv_s6; + reg [c_burst_len_bw-1:0] viv_s7; + reg [c_burst_len_bw-1:0] viv_s8; + wire viv_s9; + reg viv_s10; + reg viv_s11; + parameter c_bvci_idle = 3'b000; + parameter c_single = 3'b001; + parameter c_burst = 3'b010; + parameter c_burst_fake = 3'b011; + parameter c_last_single = 3'b111; + always @(posedge m_hclk or negedge reset_m_hclk_n) begin + if (~reset_m_hclk_n) begin + viv_s5 <= c_bvci_idle; + end + else if (soft_rst_m_hclk) begin + viv_s5 <= c_bvci_idle; + end + else begin + viv_s5 <= viv_s6; + end + end + always @ (viv_s7 or burst_len or viv_s5 or fifo_select_val or + mp_frame_end or vci_out_m1_cmdack or viv_s9 or + vci_out_m1_reop or stat_skip_active or vci_out_m1_cmdval) begin + viv_s2 = 1'b0; + viv_s3 = 1'b0; + viv_s4 = 1'b0; + viv_s8 = viv_s7; + mp_fifo_read64 = 1'b0; + next_sel = 1'b0; + viv_s0 = 1'b0; + viv_s6 = viv_s5; + case (viv_s5) + c_single: begin + if (vci_out_m1_cmdack) begin + next_sel = 1'b1; + viv_s6 = c_bvci_idle; + end + else begin + viv_s3 = 1'b1; + viv_s4 = 1'b1; + end + end + c_burst: begin + viv_s3 = 1'b1; + if (vci_out_m1_cmdack && (viv_s7 == (burst_len - 1))) begin + viv_s4 = 1'b1; + mp_fifo_read64 = 1'b1; + viv_s8 = viv_s7 + 5'd1; + viv_s6 = c_single; + end + else if (vci_out_m1_cmdack) begin + mp_fifo_read64 = 1'b1; + viv_s8 = viv_s7 + 5'd1; + end + end + c_burst_fake: begin + if (viv_s7 == burst_len) begin + next_sel = 1'b1; + viv_s0 = mp_frame_end; + viv_s6 = c_bvci_idle; + end + else begin + mp_fifo_read64 = 1'b1; + viv_s8 = viv_s7 + 5'd1; + end + end + c_last_single: begin + viv_s2 = 1'b1; + if (vci_out_m1_cmdval && vci_out_m1_cmdack) begin + viv_s6 = c_bvci_idle; + end + else begin + viv_s3 = 1'b1; + viv_s4 = 1'b1; + end + end + default: begin + viv_s8 = 5'd0; + if (vci_out_m1_reop) begin + viv_s0 = mp_frame_end; + end + if (fifo_select_val & ~stat_skip_active & (burst_len == 5'd1)) begin + viv_s3 = 1'b1; + viv_s4 = 1'b1; + mp_fifo_read64 = 1'b1; + viv_s8 = 5'd1; + viv_s6 = c_single; + end + else if (fifo_select_val & ~stat_skip_active) begin + viv_s3 = 1'b1; + mp_fifo_read64 = 1'b1; + viv_s8 = 5'd1; + viv_s6 = c_burst; + end + else if (fifo_select_val & stat_skip_active) begin + mp_fifo_read64 = 1'b1; + viv_s8 = 5'd1; + viv_s6 = c_burst_fake; + end + if (viv_s9) begin + viv_s8 = 5'd1; + viv_s6 = c_last_single; + end + end + endcase + end + always @(posedge m_hclk or negedge reset_m_hclk_n) begin + if (~reset_m_hclk_n) begin + vci_out_m1_cmdval <= 1'b0; + vci_out_m1_eop <= 1'b0; + viv_s7 <= {(c_burst_len_bw){1'd0}}; + last_pixel_m1_req <= 1'b0; + end + else if (soft_rst_m_hclk) begin + vci_out_m1_cmdval <= 1'b0; + vci_out_m1_eop <= 1'b0; + viv_s7 <= {(c_burst_len_bw){1'd0}}; + last_pixel_m1_req <= 1'b0; + end + else begin + vci_out_m1_cmdval <= viv_s3; + vci_out_m1_eop <= viv_s4; + viv_s7 <= viv_s8; + if (viv_s2) begin + last_pixel_m1_req <= 1'b1; + end else if (last_pixel_m1_ack) begin + last_pixel_m1_req <= 1'b0; + end + end + end + assign vci_out_m1_cmd = 2'b10; + assign vci_out_m1_contig = 1'b1; + assign vci_out_m1_wrap = 1'b0; + assign vci_out_m1_const = 1'b0; + assign vci_out_m1_plen = (viv_s5 == c_last_single) ? 9'd8 : + {1'b0, burst_len, 3'b000}; + assign vci_out_m1_be = 8'b11111111; + assign vci_out_m1_rspack = 1'b1; + always @(posedge m_hclk or negedge reset_m_hclk_n) begin + if (~reset_m_hclk_n) begin + vci_out_m1_address <= 29'h0; + vci_out_m1_wdata <= 64'h0; + end + else if (soft_rst_m_hclk) begin + vci_out_m1_address <= 29'h0; + vci_out_m1_wdata <= 64'h0; + end + else if (mp_fifo_read64) begin + vci_out_m1_address <= address; + vci_out_m1_wdata <= data; + end + end + assign viv_s9 = (~viv_s11 & viv_s10); + always @(posedge m_hclk or negedge reset_m_hclk_n) begin + if (~reset_m_hclk_n) begin + stat_mp_frame_end <= 1'b0; + viv_s1 <= 1'b0; + viv_s10 <= 1'b0; + viv_s11 <= 1'b0; + end else if (soft_rst_m_hclk) begin + stat_mp_frame_end <= 1'b0; + viv_s1 <= 1'b0; + viv_s10 <= 1'b0; + viv_s11 <= 1'b0; + end else begin + viv_s11 <= viv_s10; + if (last_pixel_sig_en) begin + if (viv_s0) begin + viv_s1 <= 1'b1; + end + end + if (last_pixel_sig_en) begin + if (stat_mp_enable_in) begin + viv_s10 <= viv_s1; + end else if (stat_jpeg_enable_in | stat_raw_enable_in) begin + viv_s10 <= viv_s1; + end else if (last_pixel_m1_ack) begin + viv_s10 <= 1'b0; + end + end + if (last_pixel_sig_en) begin + stat_mp_frame_end <= 1'b0; + if (last_pixel_m1_ack & viv_s1) begin + stat_mp_frame_end <= 1'b1; + viv_s1 <= 1'b0; + end + end else begin + stat_mp_frame_end <= viv_s0; + end + end + end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_marvin_mi_out_ctrl_sp.v b/ispyocto/rtl/ispyocto/vsisp_marvin_mi_out_ctrl_sp.v new file mode 100644 index 0000000..1742187 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_marvin_mi_out_ctrl_sp.v
@@ -0,0 +1,274 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_marvin_mi_out_ctrl_sp + ( + m_hclk, + reset_m_hclk_n, + soft_rst_m_hclk, + sp_fifo_read64, + stat_sp_frame_end, + vci_out_m2_cmdval, + vci_out_m2_plen, + vci_out_m2_eop, + vci_out_m2_address, + vci_out_m2_wdata, + vci_out_m2_be, + vci_out_m2_cmd, + vci_out_m2_const, + vci_out_m2_contig, + vci_out_m2_wrap, + vci_out_m2_cmdack, + vci_out_m2_rspval, + vci_out_m2_reop, + vci_out_m2_rspack, + fifo_select_val, + burst_len, + address, + data, + sp_frame_end, + next_sel, + stat_sp_enable_in, + last_pixel_sig_en, + last_pixel_m2_req, + last_pixel_m2_ack + ); +`include "vsisp_marvin_mi.vh" + input m_hclk; + input reset_m_hclk_n; + input soft_rst_m_hclk; + output sp_fifo_read64; + reg sp_fifo_read64; + output stat_sp_frame_end; + reg stat_sp_frame_end; + reg viv_s0; + reg viv_s1; + output vci_out_m2_cmdval; + output [8:0] vci_out_m2_plen; + output vci_out_m2_eop; + output [31:3] vci_out_m2_address; + output [63:0] vci_out_m2_wdata; + output [7:0] vci_out_m2_be; + output [1:0] vci_out_m2_cmd; + output vci_out_m2_const; + output vci_out_m2_contig; + output vci_out_m2_wrap; + input vci_out_m2_cmdack; + input vci_out_m2_rspval; + input vci_out_m2_reop; + output vci_out_m2_rspack; + reg vci_out_m2_cmdval; + reg vci_out_m2_eop; + reg [31:3] vci_out_m2_address; + reg [63:0] vci_out_m2_wdata; + input fifo_select_val; + input [c_burst_len_bw-1:0] burst_len; + input [31:3] address; + input [63:0] data; + input sp_frame_end; + output next_sel; + input stat_sp_enable_in; + reg next_sel; + output last_pixel_m2_req; + input last_pixel_m2_ack; + input last_pixel_sig_en; + reg last_pixel_m2_req; + reg viv_s2; + reg viv_s3; + reg viv_s4; + reg [1:0] viv_s5; + reg [1:0] viv_s6; + reg [c_burst_len_bw-1:0] viv_s7; + reg [c_burst_len_bw-1:0] viv_s8; + wire viv_s9; + reg viv_s10; + reg viv_s11; + parameter c_bvci_idle = 2'b00; + parameter c_single = 2'b01; + parameter c_burst = 2'b10; + parameter c_last_single = 2'b11; + always @(posedge m_hclk or negedge reset_m_hclk_n) begin + if (~reset_m_hclk_n) begin + viv_s5 <= c_bvci_idle; + end + else if (soft_rst_m_hclk) begin + viv_s5 <= c_bvci_idle; + end + else begin + viv_s5 <= viv_s6; + end + end + always @ (viv_s7 or burst_len or viv_s5 or fifo_select_val or + sp_frame_end or vci_out_m2_cmdack or viv_s9 or + vci_out_m2_reop or vci_out_m2_cmdval) begin + viv_s2 = 1'b0; + viv_s3 = 1'b0; + viv_s4 = 1'b0; + viv_s8 = viv_s7; + sp_fifo_read64 = 1'b0; + next_sel = 1'b0; + viv_s0 = 1'b0; + viv_s6 = viv_s5; + case (viv_s5) + c_single: begin + if (vci_out_m2_cmdack) begin + next_sel = 1'b1; + viv_s6 = c_bvci_idle; + end + else begin + viv_s3 = 1'b1; + viv_s4 = 1'b1; + end + end + c_burst: begin + viv_s3 = 1'b1; + if (vci_out_m2_cmdack && (viv_s7 == (burst_len - 1))) begin + viv_s4 = 1'b1; + sp_fifo_read64 = 1'b1; + viv_s8 = viv_s7 + 5'd1; + viv_s6 = c_single; + end + else if (vci_out_m2_cmdack) begin + sp_fifo_read64 = 1'b1; + viv_s8 = viv_s7 + 5'd1; + end + end + c_last_single: begin + viv_s2 = 1'b1; + if (vci_out_m2_cmdval && vci_out_m2_cmdack) begin + viv_s6 = c_bvci_idle; + end + else begin + viv_s3 = 1'b1; + viv_s4 = 1'b1; + end + end + default: begin + viv_s8 = 5'd0; + if (vci_out_m2_reop) begin + viv_s0 = sp_frame_end; + end + if (fifo_select_val & (burst_len == 5'd1)) begin + viv_s3 = 1'b1; + viv_s4 = 1'b1; + sp_fifo_read64 = 1'b1; + viv_s8 = 5'd1; + viv_s6 = c_single; + end + else if (fifo_select_val) begin + viv_s3 = 1'b1; + sp_fifo_read64 = 1'b1; + viv_s8 = 5'd1; + viv_s6 = c_burst; + end + if (viv_s9) begin + viv_s8 = 5'd1; + viv_s6 = c_last_single; + end + end + endcase + end + always @(posedge m_hclk or negedge reset_m_hclk_n) begin + if (~reset_m_hclk_n) begin + vci_out_m2_cmdval <= 1'b0; + vci_out_m2_eop <= 1'b0; + viv_s7 <= {(c_burst_len_bw){1'd0}}; + last_pixel_m2_req <= 1'b0; + end + else if (soft_rst_m_hclk) begin + vci_out_m2_cmdval <= 1'b0; + vci_out_m2_eop <= 1'b0; + viv_s7 <= {(c_burst_len_bw){1'd0}}; + last_pixel_m2_req <= 1'b0; + end + else begin + vci_out_m2_cmdval <= viv_s3; + vci_out_m2_eop <= viv_s4; + viv_s7 <= viv_s8; + if (viv_s2) begin + last_pixel_m2_req <= 1'b1; + end else if (last_pixel_m2_ack) begin + last_pixel_m2_req <= 1'b0; + end + end + end + assign vci_out_m2_cmd = 2'b10; + assign vci_out_m2_contig = 1'b1; + assign vci_out_m2_wrap = 1'b0; + assign vci_out_m2_const = 1'b0; + assign vci_out_m2_plen = (viv_s5 == c_last_single) ? 9'd8 : + {1'b0, burst_len, 3'b000}; + assign vci_out_m2_be = 8'b11111111; + assign vci_out_m2_rspack = 1'b1; + always @(posedge m_hclk or negedge reset_m_hclk_n) begin + if (~reset_m_hclk_n) begin + vci_out_m2_address <= 29'h0; + vci_out_m2_wdata <= 64'h0; + end + else if (soft_rst_m_hclk) begin + vci_out_m2_address <= 29'h0; + vci_out_m2_wdata <= 64'h0; + end + else if (sp_fifo_read64) begin + vci_out_m2_address <= address; + vci_out_m2_wdata <= data; + end + end + assign viv_s9 = (~viv_s11 & viv_s10); + always @(posedge m_hclk or negedge reset_m_hclk_n) begin + if (~reset_m_hclk_n) begin + stat_sp_frame_end <= 1'b0; + viv_s1 <= 1'b0; + viv_s10 <= 1'b0; + viv_s11 <= 1'b0; + end else if (soft_rst_m_hclk) begin + stat_sp_frame_end <= 1'b0; + viv_s1 <= 1'b0; + viv_s10 <= 1'b0; + viv_s11 <= 1'b0; + end else begin + viv_s11 <= viv_s10; + if (last_pixel_sig_en) begin + if (viv_s0) begin + viv_s1 <= 1'b1; + end + end + if (last_pixel_sig_en) begin + if (stat_sp_enable_in) begin + viv_s10 <= viv_s1; + end else if (last_pixel_m2_ack) begin + viv_s10 <= 1'b0; + end + end + if (last_pixel_sig_en) begin + stat_sp_frame_end <= 1'b0; + if (last_pixel_m2_ack & viv_s1) begin + stat_sp_frame_end <= 1'b1; + viv_s1 <= 1'b0; + end + end else begin + stat_sp_frame_end <= viv_s0; + end + end + end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_marvin_mi_out_mp.v b/ispyocto/rtl/ispyocto/vsisp_marvin_mi_out_mp.v new file mode 100644 index 0000000..f9b72d2 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_marvin_mi_out_mp.v
@@ -0,0 +1,410 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_marvin_mi_out_mp + ( + m_hclk, + reset_m_hclk_n, + soft_rst_m_hclk, + mp_fifo_read64, + mp_fifo_select, + mp_fifo_data, + mp_fifo_h_end, + mp_fifo_v_end, + mp_y_fifo_fill_level, + mp_y_fifo_flush, + mp_cb_fifo_fill_level, + mp_cb_fifo_flush, + mp_cr_fifo_fill_level, + mp_cr_fifo_flush, + soft_upd, + skip, + mp_enable, + jpeg_enable, + raw_enable, + dp_enable, + mp_write_format, + byte_swap, + init_base_en, + init_offset_en, + mp_pingpong_en, + burst_len_lum, + burst_len_chrom, + stat_mp_enable_out, + stat_jpeg_enable_out, + stat_raw_enable_out, + stat_dp_enable_out, + mp_y_base_ad, + mp_y_size, + mp_y_offs_cnt, + mp_y_base_ad_init, + mp_y_base_ad_init2, + mp_y_size_init, + mp_y_offs_cnt_init, + mp_y_offs_cnt_start, + mp_y_irq_offs_init, + mp_y_irq_offs, + mp_cb_base_ad, + mp_cb_size, + mp_cb_offs_cnt, + mp_cb_base_ad_init, + mp_cb_base_ad_init2, + mp_cb_size_init, + mp_cb_offs_cnt_init, + mp_cb_offs_cnt_start, + mp_cr_base_ad, + mp_cr_size, + mp_cr_offs_cnt, + mp_cr_base_ad_init, + mp_cr_base_ad_init2, + mp_cr_size_init, + mp_cr_offs_cnt_init, + mp_cr_offs_cnt_start, + mp_addr_cur_y, + mp_addr_cur_cb, + mp_addr_cur_cr, + handshake_en, + stat_mp_frame_end, + stat_mblk_line, + stat_fill_mp_y, + stat_wrap_mp_y, + stat_wrap_mp_cb, + stat_wrap_mp_cr, + cfg_in_update_mp, + cfg_out_update_mp, + vci_out_m1_cmdval, + vci_out_m1_plen, + vci_out_m1_eop, + vci_out_m1_address, + vci_out_m1_wdata, + vci_out_m1_be, + vci_out_m1_cmd, + vci_out_m1_const, + vci_out_m1_contig, + vci_out_m1_wrap, + vci_out_m1_cmdack, + vci_out_m1_rspval, + vci_out_m1_reop, + vci_out_m1_rspack, + last_pixel_sig_en, + last_pixel_m1_req, + last_pixel_m1_ack, + mp_byte_swap, + mp_output_format, + mp_y_llength, + cfg_upd_double, + stat_skip_active, + mp_line_sens + ); +`include "vsisp_marvin_mi.vh" + input mp_line_sens; + output cfg_upd_double; + output stat_skip_active; + input [3:0] mp_output_format; + input [14:0] mp_y_llength; + input [2:0] mp_byte_swap; + input m_hclk; + input reset_m_hclk_n; + input soft_rst_m_hclk; + output mp_fifo_read64; + output [1:0] mp_fifo_select; + input [63:0] mp_fifo_data; + input mp_fifo_h_end; + input mp_fifo_v_end; + input [c_fifo_depth_bw-1:0] mp_y_fifo_fill_level; + input mp_y_fifo_flush; + input [c_fifo_depth_bw-1:0] mp_cb_fifo_fill_level; + input mp_cb_fifo_flush; + input [c_fifo_depth_bw-1:0] mp_cr_fifo_fill_level; + input mp_cr_fifo_flush; + input soft_upd; + input skip; + input mp_enable; + input jpeg_enable; + input raw_enable; + input dp_enable; + input [1:0] mp_write_format; + input byte_swap; + input init_base_en; + input init_offset_en; + input mp_pingpong_en; + input [1:0] burst_len_lum; + input [1:0] burst_len_chrom; + output stat_mp_enable_out; + output stat_jpeg_enable_out; + output stat_raw_enable_out; + output stat_dp_enable_out; + input [c_mi_data_addr:0] mp_addr_cur_y; + input [c_mi_data_addr:0] mp_addr_cur_cb; + input [c_mi_data_addr:0] mp_addr_cur_cr; + input handshake_en; + input [c_mi_data_addr+3:3] mp_y_base_ad_init; + input [c_mi_data_addr+3:3] mp_y_base_ad_init2; + input [c_mi_data_addr:3] mp_y_size_init; + input [c_mi_data_addr:3] mp_y_offs_cnt_init; + input [c_mi_data_addr:3] mp_y_irq_offs_init; + output [c_mi_data_addr+3:3] mp_y_base_ad; + output [c_mi_data_addr:3] mp_y_size; + output [c_mi_data_addr:3] mp_y_offs_cnt; + output [c_mi_data_addr:3] mp_y_offs_cnt_start; + output [c_mi_data_addr:3] mp_y_irq_offs; + input [c_mi_data_addr+3:3] mp_cb_base_ad_init; + input [c_mi_data_addr+3:3] mp_cb_base_ad_init2; + input [c_mi_data_addr-1:3] mp_cb_size_init; + input [c_mi_data_addr-1:3] mp_cb_offs_cnt_init; + output [c_mi_data_addr+3:3] mp_cb_base_ad; + output [c_mi_data_addr-1:3] mp_cb_size; + output [c_mi_data_addr-1:3] mp_cb_offs_cnt; + output [c_mi_data_addr-1:3] mp_cb_offs_cnt_start; + input [c_mi_data_addr+3:3] mp_cr_base_ad_init; + input [c_mi_data_addr+3:3] mp_cr_base_ad_init2; + input [c_mi_data_addr-1:3] mp_cr_size_init; + input [c_mi_data_addr-1:3] mp_cr_offs_cnt_init; + output [c_mi_data_addr+3:3] mp_cr_base_ad; + output [c_mi_data_addr-1:3] mp_cr_size; + output [c_mi_data_addr-1:3] mp_cr_offs_cnt; + output [c_mi_data_addr-1:3] mp_cr_offs_cnt_start; + output stat_mp_frame_end; + output stat_mblk_line; + output stat_fill_mp_y; + output stat_wrap_mp_y; + output stat_wrap_mp_cb; + output stat_wrap_mp_cr; + input cfg_in_update_mp; + output cfg_out_update_mp; + output vci_out_m1_cmdval; + output [8:0] vci_out_m1_plen; + output vci_out_m1_eop; + output [c_mi_data_addr+3:3] vci_out_m1_address; + output [63:0] vci_out_m1_wdata; + output [7:0] vci_out_m1_be; + output [1:0] vci_out_m1_cmd; + output vci_out_m1_const; + output vci_out_m1_contig; + output vci_out_m1_wrap; + input vci_out_m1_cmdack; + input vci_out_m1_rspval; + input vci_out_m1_reop; + output vci_out_m1_rspack; + output last_pixel_m1_req; + input last_pixel_m1_ack; + input last_pixel_sig_en; + wire [c_mi_data_addr+3:3] viv_s0; + wire [63:0] viv_s1; + wire [c_mi_data_addr:3] viv_s2; + wire [c_mi_data_addr-1:3] viv_s3; + wire [c_mi_data_addr-1:3] viv_s4; + wire [c_mi_data_addr+3:3] viv_s5; + wire [c_mi_data_addr+3:3] viv_s6; + wire [c_mi_data_addr+3:3] viv_s7; + wire viv_s8; + wire cfg_out_update_mp; + wire stat_skip_active; + wire viv_s9; + wire [c_burst_len_bw-1:0] viv_s10; + reg [c_burst_len_bw-1:0] viv_s11; + reg [c_burst_len_bw-1:0] viv_s12; + wire [c_mi_data_addr:3] viv_s13; + wire [c_mi_data_addr-1:3] viv_s14; + wire [c_mi_data_addr-1:3] viv_s15; + wire viv_s16; + wire [3:0] viv_s17; + wire [127:0] viv_s18; + wire [127:0] viv_s19; + vsisp_marvin_mi_out_updlogic_mp u_marvin_mi_out_updlogic_mp + ( + .m_hclk (m_hclk), + .reset_m_hclk_n (reset_m_hclk_n), + .soft_rst_m_hclk (soft_rst_m_hclk), + .soft_upd (soft_upd), + .skip (skip), + .mp_enable (mp_enable), + .jpeg_enable (jpeg_enable), + .raw_enable (raw_enable), + .dp_enable (dp_enable), + .mp_write_format (mp_write_format), + .stat_mp_enable_out (stat_mp_enable_out), + .stat_jpeg_enable_out (stat_jpeg_enable_out), + .stat_raw_enable_out (stat_raw_enable_out), + .stat_dp_enable_out (stat_dp_enable_out), + .cfg_in_update_mp (cfg_in_update_mp), + .mp_fifo_h_end (mp_fifo_h_end), + .mp_fifo_v_end (mp_fifo_v_end), + .mp_fifo_read64 (mp_fifo_read64), + .mp_fifo_select (mp_fifo_select), + .stat_mp_frame_end (stat_mp_frame_end), + .mp_frame_end (viv_s8), + .cfg_out_update_mp (cfg_out_update_mp), + .stat_skip_active (stat_skip_active) + ); + always @(burst_len_lum)begin + if ((burst_len_lum == 2'b10) && (c_bursts_supported >= 5'd16)) + viv_s11 = 5'd16; + else if ((burst_len_lum > 2'b00) && (c_bursts_supported >= 5'd8)) + viv_s11 = 5'd8; + else + viv_s11 = 5'd4; + end + always @(burst_len_chrom)begin + if ((burst_len_chrom == 2'b10) && (c_bursts_supported >= 5'd16)) + viv_s12 = 5'd16; + else if ((burst_len_chrom > 2'b00) && (c_bursts_supported >= 5'd8)) + viv_s12 = 5'd8; + else + viv_s12 = 5'd4; + end + vsisp_marvin_mi_out_arbit_mp u_marvin_mi_out_arbit_mp + ( + .m_hclk (m_hclk), + .reset_m_hclk_n (reset_m_hclk_n), + .soft_rst_m_hclk (soft_rst_m_hclk), + .burst_length_y (viv_s11), + .burst_length_c (viv_s12), + .mp_y_size (mp_y_size), + .mp_cb_size (mp_cb_size), + .mp_cr_size (mp_cr_size), + .mp_y_fifo_fill_level (mp_y_fifo_fill_level), + .mp_y_fifo_flush (mp_y_fifo_flush), + .mp_cb_fifo_fill_level(mp_cb_fifo_fill_level), + .mp_cb_fifo_flush (mp_cb_fifo_flush), + .mp_cr_fifo_fill_level(mp_cr_fifo_fill_level), + .mp_cr_fifo_flush (mp_cr_fifo_flush), + .y_addr (viv_s5[11:3]), + .cb_addr (viv_s6[11:3]), + .cr_addr (viv_s7[11:3]), + .next_sel (viv_s16), + .fifo_select_val (viv_s9), + .mp_fifo_select (mp_fifo_select), + .burst_len (viv_s10), + .mp_y_cur_ptr (viv_s13), + .mp_cb_cur_ptr (viv_s14), + .mp_cr_cur_ptr (viv_s15) + ); + vsisp_marvin_mi_out_addrgen_mp u_marvin_mi_out_addrgen_mp + ( + .mp_line_sens (mp_line_sens), + .mp_output_format (mp_output_format), + .mp_y_llength (mp_y_llength), + .m_hclk (m_hclk), + .reset_m_hclk_n (reset_m_hclk_n), + .soft_rst_m_hclk (soft_rst_m_hclk), + .mp_fifo_h_end (mp_fifo_h_end), + .mp_fifo_v_end (mp_fifo_v_end), + .soft_upd (soft_upd), + .mp_write_format (mp_write_format), + .init_base_en (init_base_en), + .init_offset_en (init_offset_en), + .mp_pingpong_en (mp_pingpong_en), + .mp_y_base_ad (mp_y_base_ad), + .mp_y_size (mp_y_size), + .mp_y_offs_cnt (mp_y_offs_cnt), + .mp_y_base_ad_init (mp_y_base_ad_init), + .mp_y_base_ad_init2 (mp_y_base_ad_init2), + .mp_y_size_init (mp_y_size_init), + .mp_y_offs_cnt_init (mp_y_offs_cnt_init), + .mp_y_offs_cnt_start (mp_y_offs_cnt_start), + .mp_y_irq_offs_init (mp_y_irq_offs_init), + .mp_y_irq_offs (mp_y_irq_offs), + .mp_cb_base_ad (mp_cb_base_ad), + .mp_cb_size (mp_cb_size), + .mp_cb_offs_cnt (mp_cb_offs_cnt), + .mp_cb_base_ad_init (mp_cb_base_ad_init), + .mp_cb_base_ad_init2 (mp_cb_base_ad_init2), + .mp_cb_size_init (mp_cb_size_init), + .mp_cb_offs_cnt_init (mp_cb_offs_cnt_init), + .mp_cb_offs_cnt_start(mp_cb_offs_cnt_start), + .mp_cr_base_ad (mp_cr_base_ad), + .mp_cr_size (mp_cr_size), + .mp_cr_offs_cnt (mp_cr_offs_cnt), + .mp_cr_base_ad_init (mp_cr_base_ad_init), + .mp_cr_base_ad_init2 (mp_cr_base_ad_init2), + .mp_cr_size_init (mp_cr_size_init), + .mp_cr_offs_cnt_init (mp_cr_offs_cnt_init), + .mp_cr_offs_cnt_start(mp_cr_offs_cnt_start), + .vci_out_m1_rspval (vci_out_m1_rspval), + .vci_out_m1_reop (vci_out_m1_reop), + .stat_mblk_line (stat_mblk_line), + .stat_fill_mp_y (stat_fill_mp_y), + .stat_wrap_mp_y (stat_wrap_mp_y), + .stat_wrap_mp_cb (stat_wrap_mp_cb), + .stat_wrap_mp_cr (stat_wrap_mp_cr), + .mp_fifo_read64 (mp_fifo_read64), + .mp_fifo_select (mp_fifo_select), + .cfg_out_update_mp (cfg_out_update_mp), + .stat_skip_active (stat_skip_active), + .mp_y_cur_ptr (viv_s2), + .mp_cb_cur_ptr (viv_s3), + .mp_cr_cur_ptr (viv_s4), + .cfg_upd_double (cfg_upd_double) + ); + vsisp_marvin_mi_out_ctrl_mp u_marvin_mi_out_ctrl_mp + ( + .m_hclk (m_hclk), + .reset_m_hclk_n (reset_m_hclk_n), + .soft_rst_m_hclk (soft_rst_m_hclk), + .mp_fifo_read64 (mp_fifo_read64), + .stat_mp_frame_end (stat_mp_frame_end), + .vci_out_m1_cmdval (vci_out_m1_cmdval), + .vci_out_m1_plen (vci_out_m1_plen), + .vci_out_m1_eop (vci_out_m1_eop), + .vci_out_m1_address (vci_out_m1_address), + .vci_out_m1_wdata (vci_out_m1_wdata), + .vci_out_m1_be (vci_out_m1_be), + .vci_out_m1_cmd (vci_out_m1_cmd), + .vci_out_m1_const (vci_out_m1_const), + .vci_out_m1_contig (vci_out_m1_contig), + .vci_out_m1_wrap (vci_out_m1_wrap), + .vci_out_m1_cmdack (vci_out_m1_cmdack), + .vci_out_m1_rspval (vci_out_m1_rspval), + .vci_out_m1_reop (vci_out_m1_reop), + .vci_out_m1_rspack (vci_out_m1_rspack), + .fifo_select_val (viv_s9), + .burst_len (viv_s10), + .address (viv_s0), + .data (viv_s1), + .stat_skip_active (stat_skip_active), + .mp_frame_end (viv_s8), + .next_sel (viv_s16), + .stat_mp_enable_in (stat_mp_enable_out), + .stat_jpeg_enable_in (stat_jpeg_enable_out), + .stat_raw_enable_in (stat_raw_enable_out), + .last_pixel_sig_en (last_pixel_sig_en), + .last_pixel_m1_req (last_pixel_m1_req), + .last_pixel_m1_ack (last_pixel_m1_ack) + ); + assign viv_s13=handshake_en ? mp_addr_cur_y[c_mi_data_addr-3:0]: viv_s2; + assign viv_s14=handshake_en ? mp_addr_cur_cb[c_mi_data_addr-4:0]: viv_s3; + assign viv_s15=handshake_en ? mp_addr_cur_cr[c_mi_data_addr-4:0]: viv_s4; + assign viv_s5 = mp_y_base_ad + {3'b0, viv_s13}; + assign viv_s6 = mp_cb_base_ad + {4'b0, viv_s14}; + assign viv_s7 = mp_cr_base_ad + {4'b0, viv_s15}; + assign viv_s0 = ((mp_fifo_select == 2'd0) ? viv_s5 : 29'h0) | + ((mp_fifo_select == 2'd1) ? viv_s6 : 29'h0) | + ((mp_fifo_select == 2'd2) ? viv_s7 : 29'h0); + assign viv_s17[3:0] = {1'b0,mp_byte_swap[2:0]}; + assign viv_s18[127:0] = {64'h0,mp_fifo_data[63:0]}; + assign viv_s1[63:0] = viv_s19[63:0]; + vsisp_marvin_mi_swap u_marvin_mi_swap(.swap_vector (viv_s17[3:0]), + .data_to_swap (viv_s18[127:0]), + .swapped_data (viv_s19[127:0])); +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_marvin_mi_out_sp.v b/ispyocto/rtl/ispyocto/vsisp_marvin_mi_out_sp.v new file mode 100644 index 0000000..3185422 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_marvin_mi_out_sp.v
@@ -0,0 +1,372 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_marvin_mi_out_sp + ( + m_hclk, + reset_m_hclk_n, + soft_rst_m_hclk, + sp_fifo_read64, + sp_fifo_select, + sp_fifo_data, + sp_fifo_h_end, + sp_fifo_v_end, + sp_y_fifo_fill_level, + sp_y_fifo_flush, + sp_cb_fifo_fill_level, + sp_cb_fifo_flush, + sp_cr_fifo_fill_level, + sp_cr_fifo_flush, + soft_upd, + sp_enable, + dp_enable, + h_flip, + v_flip, + rot, + sp_write_format, + sp_output_format, + byte_swap, + init_base_en, + init_offset_en, + sp_pingpong_en, + burst_len_lum, + burst_len_chrom, + stat_sp_enable_out, + stat_dp_enable_out, + sp_y_base_ad, + sp_y_size, + sp_y_offs_cnt, + sp_y_base_ad_init, + sp_y_base_ad_init2, + sp_y_size_init, + sp_y_offs_cnt_init, + sp_y_offs_cnt_start, + sp_y_pic_width, + sp_y_llength, + sp_y_pic_size, + sp_cb_base_ad, + sp_cb_size, + sp_cb_offs_cnt, + sp_cb_base_ad_init, + sp_cb_base_ad_init2, + sp_cb_size_init, + sp_cb_offs_cnt_init, + sp_cb_offs_cnt_start, + sp_cr_base_ad, + sp_cr_size, + sp_cr_offs_cnt, + sp_cr_base_ad_init, + sp_cr_base_ad_init2, + sp_cr_size_init, + sp_cr_offs_cnt_init, + sp_cr_offs_cnt_start, + stat_sp_frame_end, + stat_wrap_sp_y, + stat_wrap_sp_cb, + stat_wrap_sp_cr, + cfg_in_update_sp, + cfg_out_update_sp, + vci_out_m2_cmdval, + vci_out_m2_plen, + vci_out_m2_eop, + vci_out_m2_address, + vci_out_m2_wdata, + vci_out_m2_be, + vci_out_m2_cmd, + vci_out_m2_const, + vci_out_m2_contig, + vci_out_m2_wrap, + vci_out_m2_cmdack, + vci_out_m2_rspval, + vci_out_m2_reop, + vci_out_m2_rspack, + last_pixel_sig_en, + last_pixel_m2_req, + last_pixel_m2_ack, + sp_byte_swap + ); +`include "vsisp_marvin_mi.vh" + input [2:0] sp_byte_swap; + input m_hclk; + input reset_m_hclk_n; + input soft_rst_m_hclk; + output sp_fifo_read64; + output [1:0] sp_fifo_select; + input [63:0] sp_fifo_data; + input sp_fifo_h_end; + input sp_fifo_v_end; + input [c_fifo_depth_bw-1:0] sp_y_fifo_fill_level; + input sp_y_fifo_flush; + input [c_fifo_depth_bw-1:0] sp_cb_fifo_fill_level; + input sp_cb_fifo_flush; + input [c_fifo_depth_bw-1:0] sp_cr_fifo_fill_level; + input sp_cr_fifo_flush; + input soft_upd; + input sp_enable; + input dp_enable; + input h_flip; + input v_flip; + input rot; + input [1:0] sp_write_format; + input [2:0] sp_output_format; + input byte_swap; + input init_base_en; + input init_offset_en; + input sp_pingpong_en; + input [1:0] burst_len_lum; + input [1:0] burst_len_chrom; + output stat_sp_enable_out; + output stat_dp_enable_out; + output [31:3] sp_y_base_ad; + output [c_bufsize:3] sp_y_size; + output [c_bufsize:3] sp_y_offs_cnt; + input [31:3] sp_y_base_ad_init; + input [31:3] sp_y_base_ad_init2; + input [c_bufsize:3] sp_y_size_init; + input [c_bufsize:3] sp_y_offs_cnt_init; + output [c_bufsize:3] sp_y_offs_cnt_start; + input [14:0] sp_y_pic_width; + input [14:0] sp_y_llength; + input [c_bufsize:0] sp_y_pic_size; + output [31:3] sp_cb_base_ad; + output [c_bufsize-1:3] sp_cb_size; + output [c_bufsize-1:3] sp_cb_offs_cnt; + input [31:3] sp_cb_base_ad_init; + input [31:3] sp_cb_base_ad_init2; + input [c_bufsize-1:3] sp_cb_size_init; + input [c_bufsize-1:3] sp_cb_offs_cnt_init; + output [c_bufsize-1:3] sp_cb_offs_cnt_start; + output [31:3] sp_cr_base_ad; + output [c_bufsize-1:3] sp_cr_size; + output [c_bufsize-1:3] sp_cr_offs_cnt; + input [31:3] sp_cr_base_ad_init; + input [31:3] sp_cr_base_ad_init2; + input [c_bufsize-1:3] sp_cr_size_init; + input [c_bufsize-1:3] sp_cr_offs_cnt_init; + output [c_bufsize-1:3] sp_cr_offs_cnt_start; + output stat_sp_frame_end; + output stat_wrap_sp_y; + output stat_wrap_sp_cb; + output stat_wrap_sp_cr; + input cfg_in_update_sp; + output cfg_out_update_sp; + output vci_out_m2_cmdval; + output [8:0] vci_out_m2_plen; + output vci_out_m2_eop; + output [31:3] vci_out_m2_address; + output [63:0] vci_out_m2_wdata; + output [7:0] vci_out_m2_be; + output [1:0] vci_out_m2_cmd; + output vci_out_m2_const; + output vci_out_m2_contig; + output vci_out_m2_wrap; + input vci_out_m2_cmdack; + input vci_out_m2_rspval; + input vci_out_m2_reop; + output vci_out_m2_rspack; + output last_pixel_m2_req; + input last_pixel_m2_ack; + input last_pixel_sig_en; + wire [31:3] viv_s0; + wire [63:0] viv_s1; + wire viv_s2; + wire cfg_out_update_sp; + wire viv_s3; + wire [c_burst_len_bw-1:0] viv_s4; + reg [c_burst_len_bw-1:0] viv_s5; + reg [c_burst_len_bw-1:0] viv_s6; + wire [c_bufsize:3] viv_s7; + wire [c_bufsize-1:3] viv_s8; + wire [c_bufsize-1:3] viv_s9; + wire [31:3] viv_s10; + wire [31:3] viv_s11; + wire [31:3] viv_s12; + wire viv_s13; + wire [3:0] viv_s14; + wire [127:0] viv_s15; + wire [127:0] viv_s16; + vsisp_marvin_mi_out_updlogic_sp u_marvin_mi_out_updlogic_sp + ( + .m_hclk (m_hclk), + .reset_m_hclk_n (reset_m_hclk_n), + .soft_rst_m_hclk (soft_rst_m_hclk), + .soft_upd (soft_upd), + .sp_enable (sp_enable), + .dp_enable (dp_enable), + .sp_write_format (sp_write_format), + .sp_output_format (sp_output_format), + .stat_sp_enable_out (stat_sp_enable_out), + .stat_dp_enable_out (stat_dp_enable_out), + .cfg_in_update_sp (cfg_in_update_sp), + .sp_fifo_h_end (sp_fifo_h_end), + .sp_fifo_v_end (sp_fifo_v_end), + .sp_fifo_read64 (sp_fifo_read64), + .sp_fifo_select (sp_fifo_select), + .stat_sp_frame_end (stat_sp_frame_end), + .sp_frame_end (viv_s2), + .cfg_out_update_sp (cfg_out_update_sp) + ); + always @(burst_len_lum)begin + if ((burst_len_lum == 2'b10) && (c_bursts_supported >= 5'd16)) + viv_s5 = 5'd16; + else if ((burst_len_lum > 2'b00) && (c_bursts_supported >= 5'd8)) + viv_s5 = 5'd8; + else + viv_s5 = 5'd4; + end + always @(burst_len_chrom)begin + if ((burst_len_chrom == 2'b10) && (c_bursts_supported >= 5'd16)) + viv_s6 = 5'd16; + else if ((burst_len_chrom > 2'b00) && (c_bursts_supported >= 5'd8)) + viv_s6 = 5'd8; + else + viv_s6 = 5'd4; + end + vsisp_marvin_mi_out_arbit_sp u_marvin_mi_out_arbit_sp + ( + .m_hclk (m_hclk), + .reset_m_hclk_n (reset_m_hclk_n), + .soft_rst_m_hclk (soft_rst_m_hclk), + .burst_length_y (viv_s5), + .burst_length_c (viv_s6), + .sp_y_size (sp_y_size), + .sp_cb_size (sp_cb_size), + .sp_cr_size (sp_cr_size), + .sp_y_base_ad (sp_y_base_ad[11:3]), + .sp_cb_base_ad (sp_cb_base_ad[11:3]), + .sp_cr_base_ad (sp_cr_base_ad[11:3]), + .y_addr (viv_s10[11:3]), + .cb_addr (viv_s11[11:3]), + .cr_addr (viv_s12[11:3]), + .sp_y_fifo_fill_level (sp_y_fifo_fill_level), + .sp_y_fifo_flush (sp_y_fifo_flush ), + .sp_cb_fifo_fill_level (sp_cb_fifo_fill_level), + .sp_cb_fifo_flush (sp_cb_fifo_flush), + .sp_cr_fifo_fill_level (sp_cr_fifo_fill_level), + .sp_cr_fifo_flush (sp_cr_fifo_flush), + .next_sel (viv_s13), + .fifo_select_val (viv_s3), + .sp_fifo_select (sp_fifo_select), + .burst_len (viv_s4), + .sp_y_cur_ptr (viv_s7), + .sp_cb_cur_ptr (viv_s8), + .sp_cr_cur_ptr (viv_s9) + ); + vsisp_marvin_mi_out_addrgen_sp u_marvin_mi_out_addrgen_sp + ( + .m_hclk (m_hclk), + .reset_m_hclk_n (reset_m_hclk_n), + .soft_rst_m_hclk (soft_rst_m_hclk), + .sp_fifo_h_end (sp_fifo_h_end), + .sp_fifo_v_end (sp_fifo_v_end), + .soft_upd (soft_upd), + .h_flip (h_flip), + .v_flip (v_flip), + .rot (rot), + .sp_write_format (sp_write_format), + .sp_output_format (sp_output_format), + .init_base_en (init_base_en), + .init_offset_en (init_offset_en), + .sp_pingpong_en (sp_pingpong_en), + .sp_y_base_ad (sp_y_base_ad), + .sp_y_size (sp_y_size), + .sp_y_offs_cnt (sp_y_offs_cnt), + .sp_y_base_ad_init (sp_y_base_ad_init), + .sp_y_base_ad_init2 (sp_y_base_ad_init2), + .sp_y_size_init (sp_y_size_init), + .sp_y_offs_cnt_init (sp_y_offs_cnt_init ), + .sp_y_offs_cnt_start (sp_y_offs_cnt_start), + .sp_y_pic_width (sp_y_pic_width), + .sp_y_llength (sp_y_llength), + .sp_y_pic_size (sp_y_pic_size), + .sp_cb_base_ad (sp_cb_base_ad), + .sp_cb_size (sp_cb_size), + .sp_cb_offs_cnt (sp_cb_offs_cnt), + .sp_cb_base_ad_init (sp_cb_base_ad_init ), + .sp_cb_base_ad_init2 (sp_cb_base_ad_init2 ), + .sp_cb_size_init (sp_cb_size_init ), + .sp_cb_offs_cnt_init (sp_cb_offs_cnt_init), + .sp_cb_offs_cnt_start (sp_cb_offs_cnt_start), + .sp_cr_base_ad (sp_cr_base_ad), + .sp_cr_size (sp_cr_size), + .sp_cr_offs_cnt (sp_cr_offs_cnt), + .sp_cr_base_ad_init (sp_cr_base_ad_init), + .sp_cr_base_ad_init2 (sp_cr_base_ad_init2), + .sp_cr_size_init (sp_cr_size_init), + .sp_cr_offs_cnt_init (sp_cr_offs_cnt_init), + .sp_cr_offs_cnt_start (sp_cr_offs_cnt_start), + .stat_wrap_sp_y (stat_wrap_sp_y), + .stat_wrap_sp_cb (stat_wrap_sp_cb), + .stat_wrap_sp_cr (stat_wrap_sp_cr), + .sp_fifo_read64 (sp_fifo_read64), + .sp_fifo_select (sp_fifo_select), + .cfg_out_update_sp (cfg_out_update_sp), + .sp_y_cur_ptr (viv_s7), + .sp_cb_cur_ptr (viv_s8), + .sp_cr_cur_ptr (viv_s9) + ); + vsisp_marvin_mi_out_ctrl_sp u_marvin_mi_out_ctrl_sp + ( + .m_hclk (m_hclk), + .reset_m_hclk_n (reset_m_hclk_n), + .soft_rst_m_hclk (soft_rst_m_hclk), + .sp_fifo_read64 (sp_fifo_read64), + .stat_sp_frame_end (stat_sp_frame_end), + .vci_out_m2_cmdval (vci_out_m2_cmdval), + .vci_out_m2_plen (vci_out_m2_plen), + .vci_out_m2_eop (vci_out_m2_eop), + .vci_out_m2_address (vci_out_m2_address), + .vci_out_m2_wdata (vci_out_m2_wdata), + .vci_out_m2_be (vci_out_m2_be), + .vci_out_m2_cmd (vci_out_m2_cmd), + .vci_out_m2_const (vci_out_m2_const), + .vci_out_m2_contig (vci_out_m2_contig), + .vci_out_m2_wrap (vci_out_m2_wrap), + .vci_out_m2_cmdack (vci_out_m2_cmdack), + .vci_out_m2_rspval (vci_out_m2_rspval), + .vci_out_m2_reop (vci_out_m2_reop), + .vci_out_m2_rspack (vci_out_m2_rspack), + .fifo_select_val (viv_s3), + .burst_len (viv_s4), + .address (viv_s0), + .data (viv_s1), + .sp_frame_end (viv_s2), + .next_sel (viv_s13), + .stat_sp_enable_in (stat_sp_enable_out), + .last_pixel_sig_en (last_pixel_sig_en), + .last_pixel_m2_req (last_pixel_m2_req), + .last_pixel_m2_ack (last_pixel_m2_ack) + ); + assign viv_s10 = sp_y_base_ad + {3'b0, viv_s7}; + assign viv_s11 = sp_cb_base_ad + {4'b0, viv_s8}; + assign viv_s12 = sp_cr_base_ad + {4'b0, viv_s9}; + assign viv_s0 = ((sp_fifo_select == 2'd0) ? viv_s10 : 29'h0) | + ((sp_fifo_select == 2'd1) ? viv_s11 : 29'h0) | + ((sp_fifo_select == 2'd2) ? viv_s12 : 29'h0); + assign viv_s14[3:0] = {1'b0,sp_byte_swap[2:0]}; + assign viv_s15[127:0] = {64'h0,sp_fifo_data[63:0]}; + assign viv_s1[63:0] = viv_s16[63:0]; + vsisp_marvin_mi_swap u_marvin_mi_swap(.swap_vector (viv_s14[3:0]), + .data_to_swap (viv_s15[127:0]), + .swapped_data (viv_s16[127:0])); +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_marvin_mi_out_updlogic_mp.v b/ispyocto/rtl/ispyocto/vsisp_marvin_mi_out_updlogic_mp.v new file mode 100644 index 0000000..e3d2fb1 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_marvin_mi_out_updlogic_mp.v
@@ -0,0 +1,209 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_marvin_mi_out_updlogic_mp + ( + m_hclk, + reset_m_hclk_n, + soft_rst_m_hclk, + soft_upd, + skip, + mp_enable, + jpeg_enable, + raw_enable, + dp_enable, + mp_write_format, + stat_mp_enable_out, + stat_jpeg_enable_out, + stat_raw_enable_out, + stat_dp_enable_out, + cfg_in_update_mp, + mp_fifo_h_end, + mp_fifo_v_end, + mp_fifo_read64, + mp_fifo_select, + stat_mp_frame_end, + mp_frame_end, + cfg_out_update_mp, + stat_skip_active + ); + input m_hclk; + input reset_m_hclk_n; + input soft_rst_m_hclk; + input soft_upd; + input skip; + input mp_enable; + input jpeg_enable; + input raw_enable; + input dp_enable; + input [1:0] mp_write_format; + output stat_mp_enable_out; + output stat_jpeg_enable_out; + output stat_raw_enable_out; + output stat_dp_enable_out; + reg stat_mp_enable_out; + reg stat_jpeg_enable_out; + reg stat_raw_enable_out; + reg stat_dp_enable_out; + input cfg_in_update_mp; + input mp_fifo_h_end; + input mp_fifo_v_end; + input mp_fifo_read64; + input [1:0] mp_fifo_select; + input stat_mp_frame_end; + output mp_frame_end; + output cfg_out_update_mp; + output stat_skip_active; + reg mp_frame_end; + reg cfg_out_update_mp; + reg stat_skip_active; + reg viv_s0; + reg viv_s1; + reg viv_s2; + reg viv_s3; + always @ (viv_s1 or viv_s2 or + mp_write_format or viv_s0 or + stat_jpeg_enable_out or stat_mp_enable_out or + stat_raw_enable_out or stat_dp_enable_out) begin + if (stat_mp_enable_out & (mp_write_format == 2'b00)) begin + mp_frame_end = viv_s0 & viv_s1 & + viv_s2; + end + else if (stat_mp_enable_out & (mp_write_format == 2'b01)) begin + mp_frame_end = viv_s0 & viv_s1; + end + else if (stat_mp_enable_out & ((mp_write_format == 2'b10) || (mp_write_format == 2'b11))) begin + mp_frame_end = viv_s0; + end + else if (stat_jpeg_enable_out) begin + mp_frame_end = viv_s0; + end + else if (stat_raw_enable_out) begin + mp_frame_end = viv_s0; + end + else if (stat_dp_enable_out) begin + mp_frame_end = viv_s0; + end + else begin + mp_frame_end = 1'b0; + end + end + always @(posedge m_hclk or negedge reset_m_hclk_n) begin + if (~reset_m_hclk_n) begin + cfg_out_update_mp <= 1'b0; + end + else if (soft_rst_m_hclk) begin + cfg_out_update_mp <= 1'b0; + end + else if (( stat_mp_frame_end | + ~(stat_mp_enable_out | stat_jpeg_enable_out | + stat_raw_enable_out | stat_dp_enable_out) ) & + viv_s3) begin + cfg_out_update_mp <= 1'b1; + end + else if (~cfg_in_update_mp) begin + cfg_out_update_mp <= 1'b0; + end + end + always @(posedge m_hclk or negedge reset_m_hclk_n) begin + if (~reset_m_hclk_n) begin + viv_s3 <= 1'b0; + end + else if (soft_rst_m_hclk) begin + viv_s3 <= 1'b0; + end + else begin + if (cfg_in_update_mp) begin + viv_s3 <= 1'b1; + end + else if (cfg_out_update_mp) begin + viv_s3 <= 1'b0; + end + end + end + always @(posedge m_hclk or negedge reset_m_hclk_n) begin + if (~reset_m_hclk_n) begin + viv_s0 <= 1'b0; + viv_s1 <= 1'b0; + viv_s2 <= 1'b0; + end + else if (soft_rst_m_hclk) begin + viv_s0 <= 1'b0; + viv_s1 <= 1'b0; + viv_s2 <= 1'b0; + end + else begin + if (stat_mp_frame_end) begin + viv_s0 <= 1'b0; + viv_s1 <= 1'b0; + viv_s2 <= 1'b0; + end + if (mp_fifo_h_end & mp_fifo_v_end & mp_fifo_read64 & + (mp_fifo_select == 2'd0)) begin + viv_s0 <= 1'b1; + end + if (mp_fifo_h_end & mp_fifo_v_end & mp_fifo_read64 & + (mp_fifo_select == 2'd1)) begin + viv_s1 <= 1'b1; + end + if (mp_fifo_h_end & mp_fifo_v_end & mp_fifo_read64 & + (mp_fifo_select == 2'd2)) begin + viv_s2 <= 1'b1; + end + end + end + always @(posedge m_hclk or negedge reset_m_hclk_n) begin + if (~reset_m_hclk_n) begin + stat_skip_active <= 1'b0; + end + else if (soft_rst_m_hclk) begin + stat_skip_active <= 1'b0; + end + else begin + if (skip) begin + stat_skip_active <= 1'b1; + end + else if (stat_mp_frame_end) begin + stat_skip_active <= 1'b0; + end + end + end + always @(posedge m_hclk or negedge reset_m_hclk_n) begin + if (~reset_m_hclk_n) begin + stat_mp_enable_out <= 1'b0; + stat_jpeg_enable_out <= 1'b0; + stat_raw_enable_out <= 1'b0; + stat_dp_enable_out <= 1'b0; + end + else begin + if (soft_upd | cfg_out_update_mp) begin + stat_mp_enable_out <= mp_enable; + stat_raw_enable_out <= raw_enable; + stat_dp_enable_out <= dp_enable; + end + if (soft_upd) begin + stat_jpeg_enable_out <= jpeg_enable; + end + end + end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_marvin_mi_out_updlogic_sp.v b/ispyocto/rtl/ispyocto/vsisp_marvin_mi_out_updlogic_sp.v new file mode 100644 index 0000000..a52ca55 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_marvin_mi_out_updlogic_sp.v
@@ -0,0 +1,172 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_marvin_mi_out_updlogic_sp + ( + m_hclk, + reset_m_hclk_n, + soft_rst_m_hclk, + soft_upd, + sp_enable, + dp_enable, + sp_write_format, + sp_output_format, + stat_sp_enable_out, + stat_dp_enable_out, + cfg_in_update_sp, + sp_fifo_h_end, + sp_fifo_v_end, + sp_fifo_read64, + sp_fifo_select, + stat_sp_frame_end, + sp_frame_end, + cfg_out_update_sp + ); + input m_hclk; + input reset_m_hclk_n; + input soft_rst_m_hclk; + input soft_upd; + input sp_enable; + input dp_enable; + input [1:0] sp_write_format; + input [2:0] sp_output_format; + output stat_sp_enable_out; + output stat_dp_enable_out; + reg stat_sp_enable_out; + reg stat_dp_enable_out; + input cfg_in_update_sp; + input sp_fifo_h_end; + input sp_fifo_v_end; + input sp_fifo_read64; + input [1:0] sp_fifo_select; + input stat_sp_frame_end; + output sp_frame_end; + output cfg_out_update_sp; + reg sp_frame_end; + reg cfg_out_update_sp; + reg viv_s0; + reg viv_s1; + reg viv_s2; + reg viv_s3; + always @ (viv_s1 or viv_s2 or + sp_output_format or sp_write_format or viv_s0 or + stat_sp_enable_out or stat_dp_enable_out) begin + if (stat_sp_enable_out & (sp_output_format[2] == 1'b1)) begin + sp_frame_end = viv_s0; + end + else if (stat_sp_enable_out & (sp_output_format[2:0] == 3'b0)) begin + sp_frame_end = viv_s0; + end + else if (stat_sp_enable_out & (sp_write_format == 2'b00)) begin + sp_frame_end = viv_s0 & viv_s1 & + viv_s2; + end + else if (stat_sp_enable_out & (sp_write_format == 2'b01)) begin + sp_frame_end = viv_s0 & viv_s1; + end + else if (stat_sp_enable_out & (sp_write_format == 2'b10)) begin + sp_frame_end = viv_s0; + end + else if (stat_dp_enable_out) begin + sp_frame_end = viv_s0; + end + else begin + sp_frame_end = 1'b0; + end + end + always @(posedge m_hclk or negedge reset_m_hclk_n) begin + if (~reset_m_hclk_n) begin + cfg_out_update_sp <= 1'b0; + end + else if (soft_rst_m_hclk) begin + cfg_out_update_sp <= 1'b0; + end + else if ((stat_sp_frame_end | + ~(stat_sp_enable_out | stat_dp_enable_out)) & + viv_s3) begin + cfg_out_update_sp <= 1'b1; + end + else if (~cfg_in_update_sp) begin + cfg_out_update_sp <= 1'b0; + end + end + always @(posedge m_hclk or negedge reset_m_hclk_n) begin + if (~reset_m_hclk_n) begin + viv_s3 <= 1'b0; + end + else if (soft_rst_m_hclk) begin + viv_s3 <= 1'b0; + end + else begin + if (cfg_in_update_sp) begin + viv_s3 <= 1'b1; + end + else if (cfg_out_update_sp) begin + viv_s3 <= 1'b0; + end + end + end + always @(posedge m_hclk or negedge reset_m_hclk_n) begin + if (~reset_m_hclk_n) begin + viv_s0 <= 1'b0; + viv_s1 <= 1'b0; + viv_s2 <= 1'b0; + end + else if (soft_rst_m_hclk) begin + viv_s0 <= 1'b0; + viv_s1 <= 1'b0; + viv_s2 <= 1'b0; + end + else begin + if (stat_sp_frame_end) begin + viv_s0 <= 1'b0; + viv_s1 <= 1'b0; + viv_s2 <= 1'b0; + end + if (sp_fifo_h_end & sp_fifo_v_end & sp_fifo_read64 & + (sp_fifo_select == 2'd0)) begin + viv_s0 <= 1'b1; + end + if (sp_fifo_h_end & sp_fifo_v_end & sp_fifo_read64 & + (sp_fifo_select == 2'd1)) begin + viv_s1 <= 1'b1; + end + if (sp_fifo_h_end & sp_fifo_v_end & sp_fifo_read64 & + (sp_fifo_select == 2'd2)) begin + viv_s2 <= 1'b1; + end + end + end + always @(posedge m_hclk or negedge reset_m_hclk_n) begin + if (~reset_m_hclk_n) begin + stat_sp_enable_out <= 1'b0; + stat_dp_enable_out <= 1'b0; + end + else begin + if (soft_upd | cfg_out_update_sp) begin + stat_sp_enable_out <= sp_enable; + stat_dp_enable_out <= dp_enable; + end + end + end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_marvin_mi_regs.v b/ispyocto/rtl/ispyocto/vsisp_marvin_mi_regs.v new file mode 100644 index 0000000..ad030fa --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_marvin_mi_regs.v
@@ -0,0 +1,2613 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_marvin_mi_regs + ( + clk, + reset_n, + jpeg_clk, + reset_jpeg_clk_n, + m_hclk, + reset_m_hclk_n, + m_hclk_cfg, + reset_m_hclk_cfg_n, + cfg_mi_val, + cfg_mi_addr, + cfg_mi_rd, + cfg_mi_wdata, + cfg_mi_rdata, + cfg_mi_ack, + mi_mp_frame_end_int, + mi_sp_frame_end_int, + mi_mblk_line_int, + mi_fill_mp_y_int, + mi_wrap_mp_y_int, + mi_wrap_mp_cb_int, + mi_wrap_mp_cr_int, + mi_wrap_sp_y_int, + mi_wrap_sp_cb_int, + mi_wrap_sp_cr_int, + mi_dma_ready_int, + mi_mp_handshk_int, + mi_mp_handshk_sw_int, + soft_upd_in, + mp_enable_in, + sp_enable_in, + jpeg_enable_in, + dp_enable_in, + raw_enable_in, + h_flip_in, + rot_in, + mp_write_format_in, + sp_write_format_in, + sp_input_format_in, + cfg_y_full, + cfg_crcb_full, + cfg_422noncosited, + sp_output_format_in, + sp_y_pic_width_in, + sp_y_pic_height_in, + stat_mp_enable_in, + stat_sp_enable_in, + stat_jpeg_enable_in, + stat_dp_enable_in, + stat_raw_enable_in, + stat_byte_cnt_raw_val, + stat_byte_cnt_raw, + stat_byte_cnt_raw_ack, + stat_byte_cnt_jpeg_val, + stat_byte_cnt_jpeg, + stat_byte_cnt_jpeg_ack, + stat_byte_cnt_dp_val, + stat_byte_cnt_dp, + stat_byte_cnt_dp_ack, + soft_upd_out, + skip, + mp_enable_out, + sp_enable_out, + jpeg_enable_out, + raw_enable_out, + dp_enable_out, + h_flip_out, + v_flip_out, + rot_out, + mp_write_format_out, + sp_write_format_out, + sp_output_format_out, + byte_swap, + init_base_en, + init_offset_en, + mp_pingpong_en, + sp_pingpong_en, + mp_auto_update, + sp_auto_update, + burst_len_lum, + burst_len_chrom, + stat_mp_enable_out, + stat_sp_enable_out, + stat_jpeg_enable_out, + stat_raw_enable_out, + stat_dp_enable_out, + mp_y_base_ad, + mp_y_size, + mp_y_offs_cnt, + mp_y_base_ad_init, + mp_y_base_ad_init2, + mp_y_size_init, + mp_y_offs_cnt_init, + mp_y_offs_cnt_start, + mp_y_irq_offs_init, + mp_y_irq_offs, + mp_cb_base_ad, + mp_cb_size, + mp_cb_offs_cnt, + mp_cb_base_ad_init, + mp_cb_base_ad_init2, + mp_cb_size_init, + mp_cb_offs_cnt_init, + mp_cb_offs_cnt_start, + mp_cr_base_ad, + mp_cr_size, + mp_cr_offs_cnt, + mp_cr_base_ad_init, + mp_cr_base_ad_init2, + mp_cr_size_init, + mp_cr_offs_cnt_init, + mp_cr_offs_cnt_start, + sp_y_base_ad, + sp_y_size, + sp_y_offs_cnt, + sp_y_base_ad_init, + sp_y_base_ad_init2, + sp_y_size_init, + sp_y_offs_cnt_init, + sp_y_offs_cnt_start, + sp_y_pic_width, + sp_y_llength, + sp_y_pic_size, + sp_cb_base_ad, + sp_cb_size, + sp_cb_offs_cnt, + sp_cb_base_ad_init, + sp_cb_base_ad_init2, + sp_cb_size_init, + sp_cb_offs_cnt_init, + sp_cb_offs_cnt_start, + sp_cr_base_ad, + sp_cr_size, + sp_cr_offs_cnt, + sp_cr_base_ad_init, + sp_cr_base_ad_init2, + sp_cr_size_init, + sp_cr_offs_cnt_init, + sp_cr_offs_cnt_start, + dma_read_format_in, + dma_rgb_format_in, + dma_start, + stat_dma_active, + dma_burst_len_lum, + dma_burst_len_chrom, + dma_read_format_out, + dma_rgb_format_out, + dma_inout_format, + dma_byte_swap, + dma_continuous_en, + dma_bayer_format, + dma_frame_end_disable, + dma_y_pic_start_ad, + dma_y_pic_width, + dma_y_llength, + dma_y_pic_size, + dma_cb_pic_start_ad, + dma_cr_pic_start_ad, + dma_y_pic_width_in, + dma_y_llength_in, + dma_y_pic_size_in, + dma_y_raw_fmt_in, + dma_y_raw_lval, + dma_y_raw_lval_in, + stat_mp_y_full, + stat_mp_cb_full, + stat_mp_cr_full, + stat_sp_y_full, + stat_sp_cb_full, + stat_sp_cr_full, + stat_bp_in_full, + stat_bp_ecl_full, + stat_bp_ocl_full, + stat_mp_frame_end, + stat_sp_frame_end, + stat_mblk_line, + stat_fill_mp_y, + stat_wrap_mp_y, + stat_wrap_mp_cb, + stat_wrap_mp_cr, + stat_wrap_sp_y, + stat_wrap_sp_cb, + stat_wrap_sp_cr, + stat_dma_ready, + last_pixel_sig_en, + nv21_main, + nv21_self, + nv21_dma_read, + mp_y_pic_width_out, + mp_y_pic_height_out, + mp_y_pic_size_out, + mp_output_format_out, + mp_y_llength_out, + mp_slice_offset_y_out, + mp_slice_offset_c_out, + mp_lsb_alignment_out, + mp_little_endian_out, + mp_byte_swap_out, + sp_byte_swap_out, + dma_byte_swap_out, + sw_mi_fifo_depth_ctrl_out, + bp_wr_path_enable_in, + bp_wr_path_enable_out, + bp_auto_update, + bp_wr_raw_bit_in, + bp_wr_aligned_in, + bp_wr_write_format_in, + bp_wr_write_format_out, + bp_wr_burst_len, + bp_wr_byte_swap, + bp_wr_size, + bp_wr_size_init, + bp_wr_llength, + bp_wr_pic_width, + bp_wr_pic_height, + bp_wr_irq_offs, + bp_wr_irq_offs_init, + bp_wr_offs_cnt_init, + bp_r_base_ad, + bp_r_base_ad_init, + bp_r_offs_cnt, + bp_r_offs_cnt_start, + bp_gr_base_ad, + bp_gr_base_ad_init, + bp_gr_offs_cnt, + bp_gr_offs_cnt_start, + bp_gb_base_ad, + bp_gb_base_ad_init, + bp_gb_offs_cnt, + bp_gb_offs_cnt_start, + bp_b_base_ad, + bp_b_base_ad_init, + bp_b_offs_cnt, + bp_b_offs_cnt_start, + stat_bp_frame_end, + stat_fill_bp_r, + stat_wrap_bp_r, + stat_wrap_bp_gr, + stat_wrap_bp_gb, + stat_wrap_bp_b, + mi_bp_frame_end_int, + mi_fill_bp_r_int, + mi_wrap_bp_r_int, + mi_wrap_bp_gr_int, + mi_wrap_bp_gb_int, + mi_wrap_bp_b_int, + handshake_en, + starage_format, + data_format, + slice_size, + ack_count, + slice_buf_size, + mp_interrupt, + handshake_mode_0, + slice_cnt_int , + sw_addr_mp_y , + sw_addr_mp_cb , + sw_addr_mp_cr , + sw_interrupt ); +output [31:0] mp_y_pic_width_out; +output [31:0] mp_y_pic_height_out; +output [31:0] mp_y_pic_size_out; +output [3:0] mp_output_format_out; +output [14:0] mp_y_llength_out; +output [28:0] mp_slice_offset_y_out; +output [28:0] mp_slice_offset_c_out; +output mp_lsb_alignment_out; +output mp_little_endian_out; +output [2:0] mp_byte_swap_out; +output [2:0] sp_byte_swap_out; +output [2:0] dma_byte_swap_out; +output [1:0] sw_mi_fifo_depth_ctrl_out; +output [1:0] starage_format; +output [1:0] data_format; +output [7:0] slice_size; +output [7:0] slice_buf_size; +output [7:0] ack_count; +output handshake_en; +input mp_interrupt; +output handshake_mode_0; +output [7:0] slice_cnt_int ; +input [31:0] sw_addr_mp_y ; +input [31:0] sw_addr_mp_cb ; +input [31:0] sw_addr_mp_cr ; +input sw_interrupt ; +reg handshake_mode_0; +reg [7:0] slice_cnt_int ; +reg viv_s0; +reg viv_s1; +reg [1:0] starage_format; +reg [1:0] data_format; +reg [7:0] slice_size; +reg [7:0] slice_buf_size; +reg [7:0] ack_count; +reg handshake_en; +reg [1:0] sw_mi_fifo_depth_ctrl_out; +reg [3:0] mp_output_format_out; +reg [14:0] mp_y_llength_out; +reg [28:0] mp_slice_offset_y_out; +reg [28:0] mp_slice_offset_c_out; +reg mp_lsb_alignment_out; +reg mp_little_endian_out; +reg [2:0] mp_byte_swap_out; +reg [2:0] sp_byte_swap_out; +reg [2:0] dma_byte_swap_out; +reg [31:0] mp_y_pic_width_out; +reg [31:0] mp_y_pic_height_out; +reg [31:0] mp_y_pic_size_out; + parameter c_mi_ctrl = 9'h00; + parameter c_mi_init = 9'h04; + parameter c_mi_mp_y_base_ad_init = 9'h08; + parameter c_mi_mp_y_size_init = 9'h0C; + parameter c_mi_mp_y_offs_cnt_init = 9'h10; + parameter c_mi_mp_y_offs_cnt_start = 9'h14; + parameter c_mi_mp_y_irq_offs_init = 9'h18; + parameter c_mi_mp_cb_base_ad_init = 9'h1C; + parameter c_mi_mp_cb_size_init = 9'h20; + parameter c_mi_mp_cb_offs_cnt_init = 9'h24; + parameter c_mi_mp_cb_offs_cnt_start = 9'h28; + parameter c_mi_mp_cr_base_ad_init = 9'h2C; + parameter c_mi_mp_cr_size_init = 9'h30; + parameter c_mi_mp_cr_offs_cnt_init = 9'h34; + parameter c_mi_mp_cr_offs_cnt_start = 9'h38; + parameter c_mi_sp_y_base_ad_init = 9'h3C; + parameter c_mi_sp_y_size_init = 9'h40; + parameter c_mi_sp_y_offs_cnt_init = 9'h44; + parameter c_mi_sp_y_offs_cnt_start = 9'h48; + parameter c_mi_sp_y_pic_width = 9'h114; + parameter c_mi_sp_y_llength = 9'h4C; + parameter c_mi_sp_y_pic_height = 9'h118; + parameter c_mi_sp_y_pic_size = 9'h11C; + parameter c_mi_sp_cb_base_ad_init = 9'h50; + parameter c_mi_sp_cb_size_init = 9'h54; + parameter c_mi_sp_cb_offs_cnt_init = 9'h58; + parameter c_mi_sp_cb_offs_cnt_start = 9'h5C; + parameter c_mi_sp_cr_base_ad_init = 9'h60; + parameter c_mi_sp_cr_size_init = 9'h64; + parameter c_mi_sp_cr_offs_cnt_init = 9'h68; + parameter c_mi_sp_cr_offs_cnt_start = 9'h6C; + parameter c_mi_byte_cnt = 9'h70; + parameter c_mi_ctrl_shd = 9'h74; + parameter c_mi_mp_y_base_ad_shd = 9'h78; + parameter c_mi_mp_y_size_shd = 9'h7C; + parameter c_mi_mp_y_offs_cnt_shd = 9'h80; + parameter c_mi_mp_y_irq_offs_shd = 9'h84; + parameter c_mi_mp_cb_base_ad_shd = 9'h88; + parameter c_mi_mp_cb_size_shd = 9'h8C; + parameter c_mi_mp_cb_offs_cnt_shd = 9'h90; + parameter c_mi_mp_cr_base_ad_shd = 9'h94; + parameter c_mi_mp_cr_size_shd = 9'h98; + parameter c_mi_mp_cr_offs_cnt_shd = 9'h9C; + parameter c_mi_sp_y_base_ad_shd = 9'hA0; + parameter c_mi_sp_y_size_shd = 9'hA4; + parameter c_mi_sp_y_offs_cnt_shd = 9'hA8; + parameter c_mi_sp_cb_base_ad_shd = 9'hB0; + parameter c_mi_sp_cb_size_shd = 9'hB4; + parameter c_mi_sp_cb_offs_cnt_shd = 9'hB8; + parameter c_mi_sp_cr_base_ad_shd = 9'hBC; + parameter c_mi_sp_cr_size_shd = 9'hC0; + parameter c_mi_sp_cr_offs_cnt_shd = 9'hC4; + parameter c_mi_dma_ctrl = 9'h120; + parameter c_mi_dma_start = 9'h124; + parameter c_mi_dma_status = 9'h128; + parameter c_mi_dma_y_pic_start_ad = 9'hC8; + parameter c_mi_dma_y_pic_width = 9'hCC; + parameter c_mi_dma_y_llength = 9'hD0; + parameter c_mi_dma_y_pic_size = 9'hD4; + parameter c_mi_dma_cb_pic_start_ad = 9'hD8; + parameter c_mi_dma_cr_pic_start_ad = 9'hE8; + parameter c_mi_imsc = 9'hF8; + parameter c_mi_ris = 9'hFC; + parameter c_mi_mis = 9'h100; + parameter c_mi_icr = 9'h104; + parameter c_mi_isr = 9'h108; + parameter c_mi_status = 9'h10C; + parameter c_mi_status_clr = 9'h110; + parameter c_mi_pixel_cnt = 9'h12C; + parameter c_mi_mp_y_base_ad_init2 = 9'h130; + parameter c_mi_mp_cb_base_ad_init2 = 9'h134; + parameter c_mi_mp_cr_base_ad_init2 = 9'h138; + parameter c_mi_sp_y_base_ad_init2 = 9'h13C; + parameter c_mi_sp_cb_base_ad_init2 = 9'h140; + parameter c_mi_sp_cr_base_ad_init2 = 9'h144; + parameter c_mi_xtd_format_ctrl = 9'h148; + parameter c_mi_mp_handshake = 9'h14c; + parameter c_mi_mp_y_llength = 9'h150; + parameter c_mi_mp_y_slice_offset = 9'h154; + parameter c_mi_mp_c_slice_offset = 9'h158; + parameter c_mi_mp_out_align_format = 9'h15c; + parameter c_mi_mp_output_fifo_size = 9'h160; + parameter c_mi_mp_y_pic_width = 9'h164; + parameter c_mi_mp_y_pic_height = 9'h168; + parameter c_mi_mp_y_pic_size = 9'h16c; + parameter c_mi_mp_sw_handsk = 9'h170; + parameter c_mi_mp_sw_add_y = 9'h174; + parameter c_mi_mp_sw_add_cb = 9'h178; + parameter c_mi_mp_sw_add_cr = 9'h17c; + parameter C_MI_BP_BASE = 9'h180; + parameter c_mi_bp_ctrl = C_MI_BP_BASE +0*4; + parameter c_mi_bp_r_base_ad_shd = C_MI_BP_BASE +1*4; + parameter c_mi_bp_gr_base_ad_shd = C_MI_BP_BASE +2*4; + parameter c_mi_bp_gb_base_ad_shd = C_MI_BP_BASE +3*4; + parameter c_mi_bp_b_base_ad_shd = C_MI_BP_BASE +4*4; + parameter c_mi_bp_r_offs_cnt_shd = C_MI_BP_BASE +5*4; + parameter c_mi_bp_gr_offs_cnt_shd = C_MI_BP_BASE +6*4; + parameter c_mi_bp_gb_offs_cnt_shd = C_MI_BP_BASE +7*4; + parameter c_mi_bp_b_offs_cnt_shd = C_MI_BP_BASE +8*4; + parameter c_mi_bp_wr_offs_cnt_init = C_MI_BP_BASE +9*4; + parameter c_mi_bp_wr_irq_offs_shd = C_MI_BP_BASE +10*4; + parameter c_mi_bp_wr_irq_offs_init = C_MI_BP_BASE +11*4; + parameter c_mi_bp_wr_size_shd = C_MI_BP_BASE +12*4; + parameter c_mi_bp_wr_size_init = C_MI_BP_BASE +13*4; + parameter c_mi_bp_wr_llength = C_MI_BP_BASE +14*4; + parameter c_mi_bp_pic_width = C_MI_BP_BASE +15*4; + parameter c_mi_bp_pic_height = C_MI_BP_BASE +16*4; + parameter c_mi_bp_pic_size = C_MI_BP_BASE +17*4; + parameter c_mi_bp_r_offs_cnt_start = C_MI_BP_BASE +18*4; + parameter c_mi_bp_gr_offs_cnt_start = C_MI_BP_BASE +19*4; + parameter c_mi_bp_gb_offs_cnt_start = C_MI_BP_BASE +20*4; + parameter c_mi_bp_b_offs_cnt_start = C_MI_BP_BASE +21*4; + parameter c_mi_bp_r_base_ad_init = C_MI_BP_BASE +22*4; + parameter c_mi_bp_gr_base_ad_init = C_MI_BP_BASE +23*4; + parameter c_mi_bp_gb_base_ad_init = C_MI_BP_BASE +24*4; + parameter c_mi_bp_b_base_ad_init = C_MI_BP_BASE +25*4; + parameter c_mi_mp_dma_y_raw_fmt = C_MI_BP_BASE +26*4; + parameter c_mi_mp_dma_y_raw_lval = C_MI_BP_BASE +27*4; + parameter c_bp_int_cnt = 6; +`include "vsisp_marvin_mi.vh" + input clk; + input reset_n; + input jpeg_clk; + input reset_jpeg_clk_n; + input m_hclk; + input reset_m_hclk_n; + input m_hclk_cfg; + input reset_m_hclk_cfg_n; + input cfg_mi_val; + input [8:2] cfg_mi_addr; + input cfg_mi_rd; + input [31:0] cfg_mi_wdata; + output [31:0] cfg_mi_rdata; + output cfg_mi_ack; + reg [31:0] cfg_mi_rdata; + reg cfg_mi_ack; + output mi_mp_frame_end_int; + output mi_sp_frame_end_int; + output mi_mblk_line_int; + output mi_fill_mp_y_int; + output mi_wrap_mp_y_int; + output mi_wrap_mp_cb_int; + output mi_wrap_mp_cr_int; + output mi_wrap_sp_y_int; + output mi_wrap_sp_cb_int; + output mi_wrap_sp_cr_int; + output mi_dma_ready_int; + output mi_mp_handshk_int; + output mi_mp_handshk_sw_int; + output soft_upd_in; + output mp_enable_in; + output sp_enable_in; + output jpeg_enable_in; + output [1:0] dp_enable_in; + output raw_enable_in; + output h_flip_in; + output rot_in; + output [1:0] mp_write_format_in; + output [1:0] sp_write_format_in; + output [1:0] sp_input_format_in; + output cfg_y_full; + output cfg_crcb_full; + output cfg_422noncosited; + output [2:0] sp_output_format_in; + output [14:0] sp_y_pic_width_in; + output [14:0] sp_y_pic_height_in; + input stat_mp_enable_in; + input stat_sp_enable_in; + input stat_jpeg_enable_in; + input [1:0] stat_dp_enable_in; + input stat_raw_enable_in; + input stat_byte_cnt_raw_val; + input [c_bufsize-1:0] stat_byte_cnt_raw; + output stat_byte_cnt_raw_ack; + input stat_byte_cnt_jpeg_val; + input [c_bufsize-1:0] stat_byte_cnt_jpeg; + output stat_byte_cnt_jpeg_ack; + input stat_byte_cnt_dp_val; + input [c_bufsize-1:0] stat_byte_cnt_dp; + output stat_byte_cnt_dp_ack; + reg soft_upd_in; + reg [14:0] sp_y_pic_width_in; + reg [14:0] sp_y_pic_height_in; + output soft_upd_out; + output skip; + output mp_enable_out; + output sp_enable_out; + output jpeg_enable_out; + output raw_enable_out; + output [1:0] dp_enable_out; + output h_flip_out; + output v_flip_out; + output rot_out; + output [1:0] mp_write_format_out; + output [1:0] sp_write_format_out; + output [2:0] sp_output_format_out; + output byte_swap; + output init_base_en; + output init_offset_en; + output mp_pingpong_en; + output sp_pingpong_en; + output mp_auto_update; + output sp_auto_update; + output [1:0] burst_len_lum; + output [1:0] burst_len_chrom; + reg skip; + reg byte_swap; + reg viv_s2; + reg viv_s3; + reg viv_s4; + reg init_base_en; + reg init_offset_en; + reg mp_pingpong_en; + reg sp_pingpong_en; + reg mp_auto_update; + reg sp_auto_update; + reg [1:0] burst_len_lum; + reg [1:0] burst_len_chrom; + input stat_mp_enable_out; + input stat_sp_enable_out; + input stat_jpeg_enable_out; + input stat_raw_enable_out; + input [1:0] stat_dp_enable_out; + input [31:3] mp_y_base_ad; + input [c_bufsize:3] mp_y_size; + input [c_bufsize:3] mp_y_offs_cnt; + output [31:3] mp_y_base_ad_init; + output [31:3] mp_y_base_ad_init2; + output [c_bufsize:3] mp_y_size_init; + output [c_bufsize:3] mp_y_offs_cnt_init; + input [c_bufsize:3] mp_y_offs_cnt_start; + output [c_bufsize:3] mp_y_irq_offs_init; + input [c_bufsize:3] mp_y_irq_offs; + reg [31:3] mp_y_base_ad_init; + reg [31:3] mp_y_base_ad_init2; + reg [c_bufsize:3] mp_y_size_init; + reg [c_bufsize:3] mp_y_offs_cnt_init; + reg [c_bufsize:3] mp_y_irq_offs_init; + input [31:3] mp_cb_base_ad; + input [c_bufsize-1:3] mp_cb_size; + input [c_bufsize-1:3] mp_cb_offs_cnt; + output [31:3] mp_cb_base_ad_init; + output [31:3] mp_cb_base_ad_init2; + output [c_bufsize-1:3] mp_cb_size_init; + output [c_bufsize-1:3] mp_cb_offs_cnt_init; + input [c_bufsize-1:3] mp_cb_offs_cnt_start; + reg [31:3] mp_cb_base_ad_init; + reg [31:3] mp_cb_base_ad_init2; + reg [c_bufsize-1:3] mp_cb_size_init; + reg [c_bufsize-1:3] mp_cb_offs_cnt_init; + input [31:3] mp_cr_base_ad; + input [c_bufsize-1:3] mp_cr_size; + input [c_bufsize-1:3] mp_cr_offs_cnt; + output [31:3] mp_cr_base_ad_init; + output [31:3] mp_cr_base_ad_init2; + output [c_bufsize-1:3] mp_cr_size_init; + output [c_bufsize-1:3] mp_cr_offs_cnt_init; + input [c_bufsize-1:3] mp_cr_offs_cnt_start; + reg [31:3] mp_cr_base_ad_init; + reg [31:3] mp_cr_base_ad_init2; + reg [c_bufsize-1:3] mp_cr_size_init; + reg [c_bufsize-1:3] mp_cr_offs_cnt_init; + input [31:3] sp_y_base_ad; + input [c_bufsize:3] sp_y_size; + input [c_bufsize:3] sp_y_offs_cnt; + output [31:3] sp_y_base_ad_init; + output [31:3] sp_y_base_ad_init2; + output [c_bufsize:3] sp_y_size_init; + output [c_bufsize:3] sp_y_offs_cnt_init; + input [c_bufsize:3] sp_y_offs_cnt_start; + output [14:0] sp_y_pic_width; + output [14:0] sp_y_llength; + output [c_bufsize:0] sp_y_pic_size; + reg [31:3] sp_y_base_ad_init; + reg [31:3] sp_y_base_ad_init2; + reg [c_bufsize:3] sp_y_size_init; + reg [c_bufsize:3] sp_y_offs_cnt_init; + reg [14:0] sp_y_pic_width; + reg [14:0] sp_y_llength; + reg [c_bufsize:0] sp_y_pic_size; + input [31:3] sp_cb_base_ad; + input [c_bufsize-1:3] sp_cb_size; + input [c_bufsize-1:3] sp_cb_offs_cnt; + output [31:3] sp_cb_base_ad_init; + output [31:3] sp_cb_base_ad_init2; + output [c_bufsize-1:3] sp_cb_size_init; + output [c_bufsize-1:3] sp_cb_offs_cnt_init; + input [c_bufsize-1:3] sp_cb_offs_cnt_start; + reg [31:3] sp_cb_base_ad_init; + reg [31:3] sp_cb_base_ad_init2; + reg [c_bufsize-1:3] sp_cb_size_init; + reg [c_bufsize-1:3] sp_cb_offs_cnt_init; + input [31:3] sp_cr_base_ad; + input [c_bufsize-1:3] sp_cr_size; + input [c_bufsize-1:3] sp_cr_offs_cnt; + output [31:3] sp_cr_base_ad_init; + output [31:3] sp_cr_base_ad_init2; + output [c_bufsize-1:3] sp_cr_size_init; + output [c_bufsize-1:3] sp_cr_offs_cnt_init; + input [c_bufsize-1:3] sp_cr_offs_cnt_start; + reg [31:3] sp_cr_base_ad_init; + reg [31:3] sp_cr_base_ad_init2; + reg [c_bufsize-1:3] sp_cr_size_init; + reg [c_bufsize-1:3] sp_cr_offs_cnt_init; + output [1:0] dma_read_format_in; + output [1:0] dma_rgb_format_in; + output dma_start; + input stat_dma_active; + output [1:0] dma_burst_len_lum; + output [1:0] dma_burst_len_chrom; + output [1:0] dma_read_format_out; + output [1:0] dma_rgb_format_out; + output [1:0] dma_inout_format; + output dma_byte_swap; + output dma_continuous_en; + output [3:0] dma_bayer_format; + output dma_frame_end_disable; + output [31:0] dma_y_pic_start_ad; + output [14:0] dma_y_pic_width; + output [14:0] dma_y_llength; + output [c_bufsize-1:0] dma_y_pic_size; + output [31:0] dma_cb_pic_start_ad; + output [31:0] dma_cr_pic_start_ad; + output [14:0] dma_y_pic_width_in; + output [14:0] dma_y_llength_in; + output [c_bufsize-1:0] dma_y_pic_size_in; + output [5:0] dma_y_raw_fmt_in; + output [14:0] dma_y_raw_lval; + output [14:0] dma_y_raw_lval_in; + reg dma_start; + reg [1:0] dma_burst_len_lum; + reg [1:0] dma_burst_len_chrom; + reg [1:0] dma_inout_format; + reg dma_byte_swap; + reg dma_continuous_en; + reg dma_frame_end_disable; + reg [31:0] dma_y_pic_start_ad; + reg [14:0] dma_y_pic_width; + reg [14:0] dma_y_llength; + reg [c_bufsize-1:0] dma_y_pic_size; + reg [31:0] dma_cb_pic_start_ad; + reg [31:0] dma_cr_pic_start_ad; + reg [5:0] viv_s5; + reg [14:0] dma_y_raw_lval; + wire[14:0] dma_y_raw_lval_in; + input stat_mp_y_full; + input stat_mp_cb_full; + input stat_mp_cr_full; + input stat_sp_y_full; + input stat_sp_cb_full; + input stat_sp_cr_full; + input stat_bp_in_full; + input stat_bp_ecl_full; + input stat_bp_ocl_full; + input stat_mp_frame_end; + input stat_sp_frame_end; + input stat_mblk_line; + input stat_fill_mp_y; + input stat_wrap_mp_y; + input stat_wrap_mp_cb; + input stat_wrap_mp_cr; + input stat_wrap_sp_y; + input stat_wrap_sp_cb; + input stat_wrap_sp_cr; + input stat_dma_ready; + input stat_bp_frame_end; + input stat_fill_bp_r; + input stat_wrap_bp_r; + input stat_wrap_bp_gr; + input stat_wrap_bp_gb; + input stat_wrap_bp_b; + output mi_bp_frame_end_int; + output mi_fill_bp_r_int; + output mi_wrap_bp_r_int; + output mi_wrap_bp_gr_int; + output mi_wrap_bp_gb_int; + output mi_wrap_bp_b_int; + output last_pixel_sig_en; + reg last_pixel_sig_en; + output reg nv21_main; + output reg nv21_self; + output reg nv21_dma_read; + reg [3:0] viv_s6; + reg viv_s7; + reg viv_s8; + reg viv_s9; + reg [1:0] viv_s10; + reg [1:0] viv_s11; + reg [1:0] viv_s12; + reg [2:0] viv_s13; + reg viv_s14; + reg [14:0] viv_s15; + reg [c_bufsize-1:0] viv_s16; + reg [c_bufsize-1:0] viv_s17; + reg [1:0] viv_s18; + reg [1:0] viv_s19; + reg [3:0] dma_bayer_format; + reg [9:0] viv_s20; + reg viv_s21; + reg viv_s22; + reg viv_s23; + reg viv_s24; + reg viv_s25; + reg viv_s26; + reg viv_s27; + reg viv_s28; + reg viv_s29; + reg [13+c_bp_int_cnt:0] viv_s30; + reg [13+c_bp_int_cnt:0] viv_s31; + reg [13+c_bp_int_cnt:0] viv_s32; + reg [ 5+3:0] viv_s33; + reg [ 5+3:0] viv_s34; + reg [ 5+3:0] viv_s35; + reg viv_s36; + reg viv_s37; + reg viv_s38; + reg viv_s39; + reg viv_s40; + reg viv_s41; + reg [1:0] viv_s42; + reg [1:0] viv_s43; + reg viv_s44; + reg viv_s45; + reg viv_s46; + reg viv_s47; + reg viv_s48; + reg viv_s49; + reg viv_s50; + reg viv_s51; + reg viv_s52; + reg [1:0] viv_s53; + reg [1:0] viv_s54; + reg [1:0] viv_s55; + reg [1:0] viv_s56; + reg [1:0] viv_s57; + reg [1:0] viv_s58; + reg [2:0] viv_s59; + reg [2:0] viv_s60; + reg viv_s61; + reg viv_s62; + reg viv_s63; + reg viv_s64; + reg viv_s65; + reg viv_s66; + reg viv_s67; + reg viv_s68; + reg viv_s69; + reg viv_s70; + reg viv_s71; + wire viv_s72; + reg viv_s73; + reg viv_s74; + reg viv_s75; + reg viv_s76; + reg viv_s77; + wire viv_s78; + reg viv_s79; + reg viv_s80; + reg viv_s81; + reg viv_s82; + reg viv_s83; + reg viv_s84; + reg viv_s85; + reg viv_s86; + reg viv_s87; + reg viv_s88; + reg viv_s89; + reg viv_s90; + reg viv_s91; + reg viv_s92; + reg viv_s93; + reg viv_s94; + reg viv_s95; + reg [1:0] viv_s96; + reg [1:0] viv_s97; + reg viv_s98; + reg viv_s99; + reg [1:0] viv_s100; + reg [1:0] viv_s101; + reg [1:0] viv_s102; + reg [1:0] viv_s103; + reg viv_s104; + reg viv_s105; + reg viv_s106; + reg viv_s107; + reg viv_s108; + reg viv_s109; + reg viv_s110; + reg viv_s111; + reg viv_s112; + reg viv_s113; + reg viv_s114; + reg viv_s115; + reg viv_s116; + reg viv_s117; + reg viv_s118; + reg viv_s119; + reg viv_s120; + reg viv_s121; + reg viv_s122; + reg viv_s123; + reg viv_s124; + reg viv_s125; + reg [1:0] viv_s126; + reg [3:0] viv_s127; + reg [3:0] viv_s128; + wire [5:0] viv_s129; + wire [5:0] viv_s130; + output bp_auto_update; + output [1:0] bp_wr_burst_len; + output [2:0] bp_wr_byte_swap; + output bp_wr_path_enable_in; + output bp_wr_path_enable_out; + output [3:0] bp_wr_raw_bit_in; + output [1:0] bp_wr_aligned_in; + output [1:0] bp_wr_write_format_in; + output [1:0] bp_wr_write_format_out; + input [c_mi_data_addr:3] bp_wr_size; + output [c_mi_data_addr:3] bp_wr_size_init; + output [14:0] bp_wr_llength; + output [14:0] bp_wr_pic_width; + output [14:0] bp_wr_pic_height; + output [c_mi_data_addr:3] bp_wr_offs_cnt_init; + input [c_mi_data_addr:3] bp_wr_irq_offs; + output [c_mi_data_addr:3] bp_wr_irq_offs_init; + input [c_mi_data_addr+3:3] bp_r_base_ad; + output [c_mi_data_addr+3:3] bp_r_base_ad_init; + input [c_mi_data_addr:3] bp_r_offs_cnt; + input [c_mi_data_addr:3] bp_r_offs_cnt_start; + input [c_mi_data_addr+3:3] bp_gr_base_ad; + output [c_mi_data_addr+3:3] bp_gr_base_ad_init; + input [c_mi_data_addr:3] bp_gr_offs_cnt; + input [c_mi_data_addr:3] bp_gr_offs_cnt_start; + input [c_mi_data_addr+3:3] bp_gb_base_ad; + output [c_mi_data_addr+3:3] bp_gb_base_ad_init; + input [c_mi_data_addr:3] bp_gb_offs_cnt; + input [c_mi_data_addr:3] bp_gb_offs_cnt_start; + input [c_mi_data_addr+3:3] bp_b_base_ad; + output [c_mi_data_addr+3:3] bp_b_base_ad_init; + input [c_mi_data_addr:3] bp_b_offs_cnt; + input [c_mi_data_addr:3] bp_b_offs_cnt_start; + reg viv_s131; + reg bp_auto_update; + reg [3:0] viv_s132; + reg [1:0] viv_s133; + reg [1:0] viv_s134; + reg [1:0] bp_wr_burst_len; + reg [2:0] bp_wr_byte_swap; + wire [c_mi_data_addr:3] bp_wr_size; + reg [c_mi_data_addr:3] bp_wr_size_init; + reg [14:0] bp_wr_llength; + reg [14:0] bp_wr_pic_width; + reg [14:0] bp_wr_pic_height; + reg [c_mi_data_addr:0] viv_s135; + reg [c_mi_data_addr:3] bp_wr_offs_cnt_init; + wire [c_mi_data_addr:3] bp_wr_irq_offs; + reg [c_mi_data_addr:3] bp_wr_irq_offs_init; + wire [c_mi_data_addr+3:3] bp_r_base_ad; + reg [c_mi_data_addr+3:3] bp_r_base_ad_init; + wire [c_mi_data_addr:3] bp_r_offs_cnt; + wire [c_mi_data_addr:3] bp_r_offs_cnt_start; + wire [c_mi_data_addr+3:3] bp_gr_base_ad; + reg [c_mi_data_addr+3:3] bp_gr_base_ad_init; + wire [c_mi_data_addr:3] bp_gr_offs_cnt; + wire [c_mi_data_addr:3] bp_gr_offs_cnt_start; + wire [c_mi_data_addr+3:3] bp_gb_base_ad; + reg [c_mi_data_addr+3:3] bp_gb_base_ad_init; + wire [c_mi_data_addr:3] bp_gb_offs_cnt; + wire [c_mi_data_addr:3] bp_gb_offs_cnt_start; + wire [c_mi_data_addr+3:3] bp_b_base_ad; + reg [c_mi_data_addr+3:3] bp_b_base_ad_init; + wire [c_mi_data_addr:3] bp_b_offs_cnt; + wire [c_mi_data_addr:3] bp_b_offs_cnt_start; + always @(posedge m_hclk_cfg or negedge reset_m_hclk_cfg_n) begin + if (~reset_m_hclk_cfg_n) begin + cfg_mi_rdata <= {32{1'b0}}; + cfg_mi_ack <= 1'b0; + viv_s6 <= 4'b0; + viv_s7 <= 1'b0; + viv_s8 <= 1'b0; + viv_s9 <= 1'b0; + byte_swap <= 1'b0; + viv_s2 <= 1'b0; + viv_s3 <= 1'b0; + viv_s4 <= 1'b0; + burst_len_lum <= 2'b00; + burst_len_chrom <= 2'b00; + init_base_en <= 1'b0; + init_offset_en <= 1'b0; + mp_pingpong_en <= 1'b0; + sp_pingpong_en <= 1'b0; + mp_auto_update <= 1'b0; + sp_auto_update <= 1'b0; + viv_s10 <= 2'b00; + viv_s11 <= 2'b00; + viv_s12 <= 2'b00; + viv_s13 <= 3'b000; + viv_s14 <= 1'b0; + skip <= 1'b0; + mp_y_base_ad_init <= {29{1'b0}}; + mp_y_size_init <= {c_bufsize-2{1'b0}}; + mp_y_offs_cnt_init <= {c_bufsize-2{1'b0}}; + mp_y_irq_offs_init <= {c_bufsize-2{1'b0}}; + mp_cb_base_ad_init <= {29{1'b0}}; + mp_cb_size_init <= {c_bufsize-3{1'b0}}; + mp_cb_offs_cnt_init <= {c_bufsize-3{1'b0}}; + mp_cr_base_ad_init <= {29{1'b0}}; + mp_cr_size_init <= {c_bufsize-3{1'b0}}; + mp_cr_offs_cnt_init <= {c_bufsize-3{1'b0}}; + sp_y_base_ad_init <= {29{1'b0}}; + sp_y_size_init <= {c_bufsize-2{1'b0}}; + sp_y_offs_cnt_init <= {c_bufsize-2{1'b0}}; + viv_s69 <= 1'b0; + sp_y_pic_width <= {15{1'b0}}; + sp_y_llength <= {15{1'b0}}; + viv_s75 <= 1'b0; + viv_s15 <= {15{1'b0}}; + sp_y_pic_size <= {c_bufsize+1{1'b0}}; + sp_cb_base_ad_init <= {29{1'b0}}; + sp_cb_size_init <= {c_bufsize-3{1'b0}}; + sp_cb_offs_cnt_init <= {c_bufsize-3{1'b0}}; + sp_cr_base_ad_init <= {29{1'b0}}; + sp_cr_size_init <= {c_bufsize-3{1'b0}}; + sp_cr_offs_cnt_init <= {c_bufsize-3{1'b0}}; + dma_burst_len_lum <= 2'b00; + dma_burst_len_chrom <= 2'b00; + viv_s18 <= 2'b00; + viv_s19 <= 2'b00; + dma_bayer_format <= 4'b00; + dma_inout_format <= 2'b00; + dma_byte_swap <= 1'b0; + dma_continuous_en <= 1'b0; + dma_frame_end_disable <= 1'b0; + dma_start <= 1'b0; + dma_y_pic_start_ad <= {32{1'b0}}; + dma_y_pic_width <= {15{1'b0}}; + dma_y_llength <= {15{1'b0}}; + dma_y_pic_size <= {c_bufsize{1'b0}}; + dma_cb_pic_start_ad <= {32{1'b0}}; + dma_cr_pic_start_ad <= {32{1'b0}}; + viv_s5 <= {6{1'b0}}; + dma_y_raw_lval <= {15{1'b0}}; + viv_s20 <= {10{1'b0}}; + viv_s21 <= {1{1'b0}}; + viv_s22 <= {1{1'b0}}; + viv_s23 <= {1{1'b0}}; + viv_s24 <= {1{1'b0}}; + viv_s25 <= {1{1'b0}}; + viv_s26 <= {1{1'b0}}; + viv_s27 <= {1{1'b0}}; + viv_s28 <= {1{1'b0}}; + viv_s29 <= {1{1'b0}}; + last_pixel_sig_en <= 1'b0; + mp_y_base_ad_init2 <= {29{1'b0}}; + mp_cb_base_ad_init2 <= {29{1'b0}}; + mp_cr_base_ad_init2 <= {29{1'b0}}; + sp_y_base_ad_init2 <= {29{1'b0}}; + sp_cb_base_ad_init2 <= {29{1'b0}}; + sp_cr_base_ad_init2 <= {29{1'b0}}; + nv21_main <= 1'b0; + nv21_self <= 1'b0; + nv21_dma_read <= 1'b0; + mp_y_pic_width_out <= 32'h0; + mp_y_pic_height_out <= 32'h0; + mp_y_pic_size_out <= 32'h0; + sw_mi_fifo_depth_ctrl_out <= 2'h0; + mp_output_format_out <= 4'h0; + mp_y_llength_out <= 15'h0; + mp_slice_offset_y_out <= 29'h0; + mp_slice_offset_c_out <= 29'h0; + mp_lsb_alignment_out <= 1'h0; + mp_little_endian_out <= 1'b0; + mp_byte_swap_out <= 3'h0; + sp_byte_swap_out <= 3'h0; + dma_byte_swap_out <= 3'h0; + handshake_en <= 1'b0; + starage_format[1:0] <= 2'b0; + data_format[1:0] <= 2'b0; + slice_size[7:0] <= 8'b0; + slice_buf_size[7:0] <= 8'b0; + ack_count[7:0] <= 8'd16; + viv_s1 <= 1'b0; + viv_s0 <= 1'b0; + handshake_mode_0 <= 1'b0; + slice_cnt_int[7:0] <= 8'h0; + viv_s131 <= 1'b0; + bp_auto_update <= 1'b0; + viv_s132 <= 4'b0; + viv_s133 <= 2'b0; + viv_s134 <= 2'b0; + bp_wr_burst_len <= 2'b0; + bp_wr_byte_swap <= 3'b0; + bp_wr_size_init <={c_mi_data_addr-3+1{1'b0}}; + bp_wr_llength <={15{1'b0}}; + bp_wr_pic_width <={15{1'b0}}; + bp_wr_pic_height <={15{1'b0}}; + viv_s135 <={c_mi_data_addr+1{1'b0}}; + bp_wr_offs_cnt_init <={c_mi_data_addr-3+1{1'b0}}; + bp_wr_irq_offs_init <={c_mi_data_addr-3+1{1'b0}}; + bp_r_base_ad_init <={c_mi_data_addr+3-3+1{1'b0}}; + bp_gr_base_ad_init <={c_mi_data_addr+3-3+1{1'b0}}; + bp_gb_base_ad_init <={c_mi_data_addr+3-3+1{1'b0}}; + bp_b_base_ad_init <={c_mi_data_addr+3-3+1{1'b0}}; + end + else begin + cfg_mi_rdata <= {32{1'b0}}; + cfg_mi_ack <= 1'b0; + viv_s14 <= 1'b0; + skip <= 1'b0; + dma_start <= 1'b0; + if (cfg_mi_val & ~cfg_mi_ack) begin + cfg_mi_ack <= 1'b1; + case ({cfg_mi_addr, 2'b00}) + c_mi_ctrl: begin + if (~cfg_mi_rd) begin + viv_s6 <= cfg_mi_wdata[3:0]; + viv_s7 <= cfg_mi_wdata[4]; + viv_s8 <= cfg_mi_wdata[5]; + viv_s9 <= cfg_mi_wdata[6]; + byte_swap <= cfg_mi_wdata[7]; + viv_s2 <= cfg_mi_wdata[8]; + viv_s3 <= cfg_mi_wdata[9]; + viv_s4 <= cfg_mi_wdata[10]; + mp_pingpong_en <= cfg_mi_wdata[11]; + sp_pingpong_en <= cfg_mi_wdata[12]; + mp_auto_update <= cfg_mi_wdata[13]; + sp_auto_update <= cfg_mi_wdata[14]; + last_pixel_sig_en <= cfg_mi_wdata[15]; + burst_len_lum <= cfg_mi_wdata[17:16]; + burst_len_chrom <= cfg_mi_wdata[19:18]; + init_base_en <= cfg_mi_wdata[20]; + init_offset_en <= cfg_mi_wdata[21]; + viv_s10 <= cfg_mi_wdata[23:22]; + viv_s11 <= cfg_mi_wdata[25:24]; + viv_s12 <= cfg_mi_wdata[27:26]; + viv_s13 <= cfg_mi_wdata[30:28]; + end + else begin + cfg_mi_rdata[3:0] <= viv_s6; + cfg_mi_rdata[4] <= viv_s7; + cfg_mi_rdata[5] <= viv_s8; + cfg_mi_rdata[6] <= viv_s9; + cfg_mi_rdata[7] <= byte_swap; + cfg_mi_rdata[8] <= viv_s2; + cfg_mi_rdata[9] <= viv_s3; + cfg_mi_rdata[10] <= viv_s4; + cfg_mi_rdata[11] <= mp_pingpong_en; + cfg_mi_rdata[12] <= sp_pingpong_en; + cfg_mi_rdata[13] <= mp_auto_update; + cfg_mi_rdata[14] <= sp_auto_update; + cfg_mi_rdata[15] <= last_pixel_sig_en; + cfg_mi_rdata[17:16] <= burst_len_lum; + cfg_mi_rdata[19:18] <= burst_len_chrom; + cfg_mi_rdata[20] <= init_base_en; + cfg_mi_rdata[21] <= init_offset_en; + cfg_mi_rdata[23:22] <= viv_s10; + cfg_mi_rdata[25:24] <= viv_s11; + cfg_mi_rdata[27:26] <= viv_s12; + cfg_mi_rdata[30:28] <= viv_s13; + end + end + c_mi_init: begin + if (~cfg_mi_rd) begin + skip <= cfg_mi_wdata[2]; + viv_s14 <= cfg_mi_wdata[4]; + mp_output_format_out[3:0] <= cfg_mi_wdata[8:5]; + end + else begin + cfg_mi_rdata[8:5] <= mp_output_format_out[3:0]; + end + end + c_mi_mp_y_base_ad_init: begin + if (~cfg_mi_rd) begin + mp_y_base_ad_init <= cfg_mi_wdata[31:3]; + end + else begin + cfg_mi_rdata[31:3] <= mp_y_base_ad_init; + end + end + c_mi_mp_y_size_init: begin + if (~cfg_mi_rd) begin + mp_y_size_init <= cfg_mi_wdata[c_bufsize:3]; + end + else begin + cfg_mi_rdata[c_bufsize:3] <= mp_y_size_init; + end + end + c_mi_mp_y_offs_cnt_init: begin + if (~cfg_mi_rd) begin + mp_y_offs_cnt_init <= cfg_mi_wdata[c_bufsize:3]; + end + else begin + cfg_mi_rdata[c_bufsize:3] <= mp_y_offs_cnt_init; + end + end + c_mi_mp_y_offs_cnt_start: begin + if (cfg_mi_rd) begin + cfg_mi_rdata[c_bufsize:3] <= mp_y_offs_cnt_start; + end + end + c_mi_mp_y_irq_offs_init: begin + if (~cfg_mi_rd) begin + mp_y_irq_offs_init <= cfg_mi_wdata[c_bufsize:3]; + end + else begin + cfg_mi_rdata[c_bufsize:3] <= mp_y_irq_offs_init; + end + end + c_mi_mp_cb_base_ad_init: begin + if (~cfg_mi_rd) begin + mp_cb_base_ad_init <= cfg_mi_wdata[31:3]; + end + else begin + cfg_mi_rdata[31:3] <= mp_cb_base_ad_init; + end + end + c_mi_mp_cb_size_init: begin + if (~cfg_mi_rd) begin + mp_cb_size_init <= cfg_mi_wdata[c_bufsize-1:3]; + end + else begin + cfg_mi_rdata[c_bufsize-1:3] <= mp_cb_size_init; + end + end + c_mi_mp_cb_offs_cnt_init: begin + if (~cfg_mi_rd) begin + mp_cb_offs_cnt_init <= cfg_mi_wdata[c_bufsize-1:3]; + end + else begin + cfg_mi_rdata[c_bufsize-1:3] <= mp_cb_offs_cnt_init; + end + end + c_mi_mp_cb_offs_cnt_start: begin + if (cfg_mi_rd) begin + cfg_mi_rdata[c_bufsize-1:3] <= mp_cb_offs_cnt_start; + end + end + c_mi_mp_cr_base_ad_init: begin + if (~cfg_mi_rd) begin + mp_cr_base_ad_init <= cfg_mi_wdata[31:3]; + end + else begin + cfg_mi_rdata[31:3] <= mp_cr_base_ad_init; + end + end + c_mi_mp_cr_size_init: begin + if (~cfg_mi_rd) begin + mp_cr_size_init <= cfg_mi_wdata[c_bufsize-1:3]; + end + else begin + cfg_mi_rdata[c_bufsize-1:3] <= mp_cr_size_init; + end + end + c_mi_mp_cr_offs_cnt_init: begin + if (~cfg_mi_rd) begin + mp_cr_offs_cnt_init <= cfg_mi_wdata[c_bufsize-1:3]; + end + else begin + cfg_mi_rdata[c_bufsize-1:3] <= mp_cr_offs_cnt_init; + end + end + c_mi_mp_cr_offs_cnt_start: begin + if (cfg_mi_rd) begin + cfg_mi_rdata[c_bufsize-1:3] <= mp_cr_offs_cnt_start; + end + end + c_mi_sp_y_base_ad_init: begin + if (~cfg_mi_rd) begin + sp_y_base_ad_init <= cfg_mi_wdata[31:3]; + end + else begin + cfg_mi_rdata[31:3] <= sp_y_base_ad_init; + end + end + c_mi_sp_y_size_init: begin + if (~cfg_mi_rd) begin + sp_y_size_init <= cfg_mi_wdata[c_bufsize:3]; + end + else begin + cfg_mi_rdata[c_bufsize:3] <= sp_y_size_init; + end + end + c_mi_sp_y_offs_cnt_init: begin + if (~cfg_mi_rd) begin + sp_y_offs_cnt_init <= cfg_mi_wdata[c_bufsize:3]; + end + else begin + cfg_mi_rdata[c_bufsize:3] <= sp_y_offs_cnt_init; + end + end + c_mi_sp_y_offs_cnt_start: begin + if (cfg_mi_rd) begin + cfg_mi_rdata[c_bufsize:3] <= sp_y_offs_cnt_start; + end + end + c_mi_sp_y_pic_width: begin + if (~cfg_mi_rd) begin + if (~viv_s69) begin + sp_y_pic_width <= cfg_mi_wdata[14:0]; + viv_s69 <= 1'b1; + end + else begin + cfg_mi_ack <= 1'b0; + end + end + else begin + cfg_mi_rdata[14:0] <= sp_y_pic_width; + end + end + c_mi_sp_y_llength: begin + if (~cfg_mi_rd) begin + sp_y_llength <= cfg_mi_wdata[14:0]; + end + else begin + cfg_mi_rdata[14:0] <= sp_y_llength; + end + end + c_mi_sp_y_pic_height: begin + if (~cfg_mi_rd) begin + if (viv_s75 == 1'b0) begin + viv_s15 <= cfg_mi_wdata[14:0]; + viv_s75 <= 1'b1; + end + else begin + cfg_mi_ack <= 1'b0; + end + end + else begin + cfg_mi_rdata[14:0] <= viv_s15; + end + end + c_mi_sp_y_pic_size: begin + sp_y_pic_size[c_bufsize:25] <= {(c_bufsize-24){1'b0}}; + if (~cfg_mi_rd) begin + sp_y_pic_size[24:0] <= cfg_mi_wdata[24:0]; + end + else begin + cfg_mi_rdata[24:0] <= sp_y_pic_size[24:0]; + end + end + c_mi_sp_cb_base_ad_init: begin + if (~cfg_mi_rd) begin + sp_cb_base_ad_init <= cfg_mi_wdata[31:3]; + end + else begin + cfg_mi_rdata[31:3] <= sp_cb_base_ad_init; + end + end + c_mi_sp_cb_size_init: begin + if (~cfg_mi_rd) begin + sp_cb_size_init <= cfg_mi_wdata[c_bufsize-1:3]; + end + else begin + cfg_mi_rdata[c_bufsize-1:3] <= sp_cb_size_init; + end + end + c_mi_sp_cb_offs_cnt_init: begin + if (~cfg_mi_rd) begin + sp_cb_offs_cnt_init <= cfg_mi_wdata[c_bufsize-1:3]; + end + else begin + cfg_mi_rdata[c_bufsize-1:3] <= sp_cb_offs_cnt_init; + end + end + c_mi_sp_cb_offs_cnt_start: begin + if (cfg_mi_rd) begin + cfg_mi_rdata[c_bufsize-1:3] <= sp_cb_offs_cnt_start; + end + end + c_mi_sp_cr_base_ad_init: begin + if (~cfg_mi_rd) begin + sp_cr_base_ad_init <= cfg_mi_wdata[31:3]; + end + else begin + cfg_mi_rdata[31:3] <= sp_cr_base_ad_init; + end + end + c_mi_sp_cr_size_init: begin + if (~cfg_mi_rd) begin + sp_cr_size_init <= cfg_mi_wdata[c_bufsize-1:3]; + end + else begin + cfg_mi_rdata[c_bufsize-1:3] <= sp_cr_size_init; + end + end + c_mi_sp_cr_offs_cnt_init: begin + if (~cfg_mi_rd) begin + sp_cr_offs_cnt_init <= cfg_mi_wdata[c_bufsize-1:3]; + end + else begin + cfg_mi_rdata[c_bufsize-1:3] <= sp_cr_offs_cnt_init; + end + end + c_mi_sp_cr_offs_cnt_start: begin + if (cfg_mi_rd) begin + cfg_mi_rdata[c_bufsize-1:3] <= sp_cr_offs_cnt_start; + end + end + c_mi_byte_cnt: begin + if (cfg_mi_rd) begin + cfg_mi_rdata[c_bufsize-1:0] <= viv_s16; + end + end + c_mi_ctrl_shd: begin + if (cfg_mi_rd) begin + cfg_mi_rdata[19:16] <= viv_s127; + cfg_mi_rdata[3:0] <= viv_s128; + end + end + c_mi_mp_y_base_ad_shd: begin + if (cfg_mi_rd) begin + cfg_mi_rdata[31:3] <= mp_y_base_ad; + end + end + c_mi_mp_y_size_shd: begin + if (cfg_mi_rd) begin + cfg_mi_rdata[c_bufsize:3] <= mp_y_size; + end + end + c_mi_mp_y_offs_cnt_shd: begin + if (cfg_mi_rd) begin + cfg_mi_rdata[c_bufsize:3] <= mp_y_offs_cnt; + end + end + c_mi_mp_y_irq_offs_shd: begin + if (cfg_mi_rd) begin + cfg_mi_rdata[c_bufsize:3] <= mp_y_irq_offs; + end + end + c_mi_mp_cb_base_ad_shd: begin + if (cfg_mi_rd) begin + cfg_mi_rdata[31:3] <= mp_cb_base_ad; + end + end + c_mi_mp_cb_size_shd: begin + if (cfg_mi_rd) begin + cfg_mi_rdata[c_bufsize-1:3] <= mp_cb_size; + end + end + c_mi_mp_cb_offs_cnt_shd: begin + if (cfg_mi_rd) begin + cfg_mi_rdata[c_bufsize-1:3] <= mp_cb_offs_cnt; + end + end + c_mi_mp_cr_base_ad_shd: begin + if (cfg_mi_rd) begin + cfg_mi_rdata[31:3] <= mp_cr_base_ad; + end + end + c_mi_mp_cr_size_shd: begin + if (cfg_mi_rd) begin + cfg_mi_rdata[c_bufsize-1:3] <= mp_cr_size; + end + end + c_mi_mp_cr_offs_cnt_shd: begin + if (cfg_mi_rd) begin + cfg_mi_rdata[c_bufsize-1:3] <= mp_cr_offs_cnt; + end + end + c_mi_sp_y_base_ad_shd: begin + if (cfg_mi_rd) begin + cfg_mi_rdata[31:3] <= sp_y_base_ad; + end + end + c_mi_sp_y_size_shd: begin + if (cfg_mi_rd) begin + cfg_mi_rdata[c_bufsize:3] <= sp_y_size; + end + end + c_mi_sp_y_offs_cnt_shd: begin + if (cfg_mi_rd) begin + cfg_mi_rdata[c_bufsize:3] <= sp_y_offs_cnt; + end + end + c_mi_sp_cb_base_ad_shd: begin + if (cfg_mi_rd) begin + cfg_mi_rdata[31:3] <= sp_cb_base_ad; + end + end + c_mi_sp_cb_size_shd: begin + if (cfg_mi_rd) begin + cfg_mi_rdata[c_bufsize-1:3] <= sp_cb_size; + end + end + c_mi_sp_cb_offs_cnt_shd: begin + if (cfg_mi_rd) begin + cfg_mi_rdata[c_bufsize-1:3] <= sp_cb_offs_cnt; + end + end + c_mi_sp_cr_base_ad_shd: begin + if (cfg_mi_rd) begin + cfg_mi_rdata[31:3] <= sp_cr_base_ad; + end + end + c_mi_sp_cr_size_shd: begin + if (cfg_mi_rd) begin + cfg_mi_rdata[c_bufsize-1:3] <= sp_cr_size; + end + end + c_mi_sp_cr_offs_cnt_shd: begin + if (cfg_mi_rd) begin + cfg_mi_rdata[c_bufsize-1:3] <= sp_cr_offs_cnt; + end + end + c_mi_dma_ctrl: begin + if (~cfg_mi_rd) begin + dma_burst_len_lum <= cfg_mi_wdata[1:0]; + dma_burst_len_chrom <= cfg_mi_wdata[3:2]; + viv_s18 <= cfg_mi_wdata[5:4]; + dma_inout_format <= cfg_mi_wdata[7:6]; + dma_byte_swap <= cfg_mi_wdata[8]; + dma_continuous_en <= cfg_mi_wdata[9]; + dma_frame_end_disable <= cfg_mi_wdata[10]; + viv_s19 <= cfg_mi_wdata[13:12]; + dma_bayer_format <= cfg_mi_wdata[17:14]; + end + else begin + cfg_mi_rdata[1:0] <= dma_burst_len_lum; + cfg_mi_rdata[3:2] <= dma_burst_len_chrom; + cfg_mi_rdata[5:4] <= viv_s18; + cfg_mi_rdata[7:6] <= dma_inout_format; + cfg_mi_rdata[8] <= dma_byte_swap; + cfg_mi_rdata[9] <= dma_continuous_en; + cfg_mi_rdata[10] <= dma_frame_end_disable; + cfg_mi_rdata[13:12] <= viv_s19; + cfg_mi_rdata[17:14] <= dma_bayer_format; + end + end + c_mi_dma_start: begin + if (~cfg_mi_rd) begin + dma_start <= cfg_mi_wdata[0]; + end + end + c_mi_dma_status: begin + if (cfg_mi_rd) begin + cfg_mi_rdata[0] <= stat_dma_active; + end + end + c_mi_dma_y_pic_start_ad: begin + if (~cfg_mi_rd) begin + dma_y_pic_start_ad <= cfg_mi_wdata[31:0]; + end + else begin + cfg_mi_rdata[31:0] <= dma_y_pic_start_ad; + end + end + c_mi_dma_y_pic_width: begin + if (~cfg_mi_rd) begin + dma_y_pic_width <= cfg_mi_wdata[14:0]; + end + else begin + cfg_mi_rdata[14:0] <= dma_y_pic_width; + end + end + c_mi_dma_y_llength: begin + if (~cfg_mi_rd) begin + dma_y_llength <= cfg_mi_wdata[14:0]; + end + else begin + cfg_mi_rdata[14:0] <= dma_y_llength; + end + end + c_mi_dma_y_pic_size: begin + if (~cfg_mi_rd) begin + dma_y_pic_size <= cfg_mi_wdata[c_bufsize-1:0]; + end + else begin + cfg_mi_rdata[c_bufsize-1:0] <= dma_y_pic_size; + end + end + c_mi_dma_cb_pic_start_ad: begin + if (~cfg_mi_rd) begin + dma_cb_pic_start_ad <= cfg_mi_wdata[31:0]; + end + else begin + cfg_mi_rdata[31:0] <= dma_cb_pic_start_ad; + end + end + c_mi_dma_cr_pic_start_ad: begin + if (~cfg_mi_rd) begin + dma_cr_pic_start_ad <= cfg_mi_wdata[31:0]; + end + else begin + cfg_mi_rdata[31:0] <= dma_cr_pic_start_ad; + end + end + c_mi_imsc: begin + if (~cfg_mi_rd) begin + viv_s29 <= cfg_mi_wdata[19]; + viv_s28 <= cfg_mi_wdata[18]; + viv_s27 <= cfg_mi_wdata[17]; + viv_s26 <= cfg_mi_wdata[16]; + viv_s25 <= cfg_mi_wdata[15]; + viv_s24 <= cfg_mi_wdata[14]; + viv_s23 <= cfg_mi_wdata[13]; + viv_s22 <= cfg_mi_wdata[12]; + viv_s21 <= cfg_mi_wdata[11]; + viv_s20[9:0] <= cfg_mi_wdata[9:0]; + end + else begin + cfg_mi_rdata[19] <= viv_s29; + cfg_mi_rdata[18] <= viv_s28; + cfg_mi_rdata[17] <= viv_s27; + cfg_mi_rdata[16] <= viv_s26; + cfg_mi_rdata[15] <= viv_s25; + cfg_mi_rdata[14] <= viv_s24; + cfg_mi_rdata[13] <= viv_s23; + cfg_mi_rdata[12] <= viv_s22; + cfg_mi_rdata[11] <= viv_s21; + cfg_mi_rdata[9:0] <= viv_s20[9:0]; + end + end + c_mi_ris: begin + if (cfg_mi_rd) begin + cfg_mi_rdata[19] <= viv_s30[19]; + cfg_mi_rdata[18] <= viv_s30[18]; + cfg_mi_rdata[17] <= viv_s30[17]; + cfg_mi_rdata[16] <= viv_s30[16]; + cfg_mi_rdata[15] <= viv_s30[15]; + cfg_mi_rdata[14] <= viv_s30[14]; + cfg_mi_rdata[13] <= viv_s30[13]; + cfg_mi_rdata[12] <= viv_s30[12]; + cfg_mi_rdata[11] <= viv_s30[11]; + cfg_mi_rdata[9:0] <= viv_s30[9:0]; + end + end + c_mi_mis: begin + if (cfg_mi_rd) begin + cfg_mi_rdata[19:0] <= viv_s30 & {viv_s29,viv_s28,viv_s27,viv_s26,viv_s25,viv_s24,viv_s23,viv_s22,viv_s21,1'b0,viv_s20}; + end + end + c_mi_status: begin + if (cfg_mi_rd) begin + cfg_mi_rdata[2:0] <= viv_s33[2:0]; + cfg_mi_rdata[6:4] <= viv_s33[5:3]; + cfg_mi_rdata[6+3:7] <= viv_s33[5+3:6]; + end + end + c_mi_pixel_cnt: begin + if (cfg_mi_rd) begin + cfg_mi_rdata[c_bufsize-1:0] <= viv_s17; + end + end + c_mi_mp_y_base_ad_init2: begin + if (~cfg_mi_rd) begin + mp_y_base_ad_init2 <= cfg_mi_wdata[31:3]; + end + else begin + cfg_mi_rdata[31:3] <= mp_y_base_ad_init2; + end + end + c_mi_mp_cb_base_ad_init2: begin + if (~cfg_mi_rd) begin + mp_cb_base_ad_init2 <= cfg_mi_wdata[31:3]; + end + else begin + cfg_mi_rdata[31:3] <= mp_cb_base_ad_init2; + end + end + c_mi_mp_cr_base_ad_init2: begin + if (~cfg_mi_rd) begin + mp_cr_base_ad_init2 <= cfg_mi_wdata[31:3]; + end + else begin + cfg_mi_rdata[31:3] <= mp_cr_base_ad_init2; + end + end + c_mi_sp_y_base_ad_init2: begin + if (~cfg_mi_rd) begin + sp_y_base_ad_init2 <= cfg_mi_wdata[31:3]; + end + else begin + cfg_mi_rdata[31:3] <= sp_y_base_ad_init2; + end + end + c_mi_sp_cb_base_ad_init2: begin + if (~cfg_mi_rd) begin + sp_cb_base_ad_init2 <= cfg_mi_wdata[31:3]; + end + else begin + cfg_mi_rdata[31:3] <= sp_cb_base_ad_init2; + end + end + c_mi_sp_cr_base_ad_init2: begin + if (~cfg_mi_rd) begin + sp_cr_base_ad_init2 <= cfg_mi_wdata[31:3]; + end + else begin + cfg_mi_rdata[31:3] <= sp_cr_base_ad_init2; + end + end + c_mi_xtd_format_ctrl: begin + if (~cfg_mi_rd) begin + nv21_main <= cfg_mi_wdata[0]; + nv21_self <= cfg_mi_wdata[1]; + nv21_dma_read <= cfg_mi_wdata[2]; + end + else begin + cfg_mi_rdata[0] <= nv21_main; + cfg_mi_rdata[1] <= nv21_self; + cfg_mi_rdata[2] <= nv21_dma_read; + end + end + c_mi_mp_handshake: begin + if (~cfg_mi_rd) + begin + handshake_en <= cfg_mi_wdata[0]; + starage_format[1:0] <= cfg_mi_wdata[2:1]; + data_format[1:0] <= cfg_mi_wdata[4:3]; + slice_size[7:0] <= cfg_mi_wdata[12:5]; + slice_buf_size[7:0] <= cfg_mi_wdata[20:13]; + ack_count[7:0] <= cfg_mi_wdata[28:21]; + end + else + begin + if(cfg_mi_rd) + begin + cfg_mi_rdata[0] <= handshake_en; + cfg_mi_rdata[2:1] <= starage_format[1:0]; + cfg_mi_rdata[4:3] <= data_format[1:0]; + cfg_mi_rdata[12:5] <= slice_size[7:0]; + cfg_mi_rdata[20:13] <= slice_buf_size[7:0]; + cfg_mi_rdata[28:21] <= ack_count[7:0]; + end + end + end + c_mi_mp_sw_handsk: begin + if (~cfg_mi_rd) + begin + handshake_mode_0 <= cfg_mi_wdata[0]; + slice_cnt_int[7:0] <= cfg_mi_wdata[15:8]; + end + else + begin + if(cfg_mi_rd) + begin + cfg_mi_rdata[0] <= handshake_mode_0; + cfg_mi_rdata[15:8] <= slice_cnt_int[7:0]; + end + end + end + c_mi_mp_sw_add_y: begin + if(cfg_mi_rd) + cfg_mi_rdata[31:0] <= sw_addr_mp_y[31:0]; + end + c_mi_mp_sw_add_cb: begin + if(cfg_mi_rd) + cfg_mi_rdata[31:0] <= sw_addr_mp_cb[31:0]; + end + c_mi_mp_sw_add_cr: begin + if(cfg_mi_rd) + cfg_mi_rdata[31:0] <= sw_addr_mp_cr[31:0]; + end + c_mi_mp_y_llength: begin + if (~cfg_mi_rd) + begin + mp_y_llength_out[14:0] <= cfg_mi_wdata[14:0]; + end + else + begin + if(cfg_mi_rd) + begin + cfg_mi_rdata[14:0] <= mp_y_llength_out[14:0]; + end + end + end + c_mi_mp_y_slice_offset: begin + if (~cfg_mi_rd) + begin + mp_slice_offset_y_out[28:0] <= cfg_mi_wdata[31:3]; + end + else + begin + if(cfg_mi_rd) + begin + cfg_mi_rdata[31:3] <= mp_slice_offset_y_out[28:0]; + end + end + end + c_mi_mp_c_slice_offset: begin + if (~cfg_mi_rd) + begin + mp_slice_offset_c_out[28:0] <= cfg_mi_wdata[31:3]; + end + else + begin + if(cfg_mi_rd) + begin + cfg_mi_rdata[31:3] <= mp_slice_offset_c_out[28:0]; + end + end + end + c_mi_mp_out_align_format:begin + if (~cfg_mi_rd) + begin + mp_lsb_alignment_out <= cfg_mi_wdata[0]; + mp_byte_swap_out[2:0] <= cfg_mi_wdata[3:1]; + sp_byte_swap_out[2:0] <= cfg_mi_wdata[6:4]; + dma_byte_swap_out[2:0] <= cfg_mi_wdata[9:7]; + mp_little_endian_out <= cfg_mi_wdata[10]; + end + else + begin + if(cfg_mi_rd) + begin + cfg_mi_rdata[0] <= mp_lsb_alignment_out; + cfg_mi_rdata[3:1] <= mp_byte_swap_out[2:0]; + cfg_mi_rdata[6:4] <= sp_byte_swap_out[2:0]; + cfg_mi_rdata[9:7] <= dma_byte_swap_out[2:0]; + cfg_mi_rdata[10] <= mp_little_endian_out; + end + end + end + c_mi_mp_output_fifo_size:begin + if (~cfg_mi_rd) + begin + sw_mi_fifo_depth_ctrl_out[1:0] <= cfg_mi_wdata[1:0]; + end + else + begin + if(cfg_mi_rd) + begin + cfg_mi_rdata[1:0] <= sw_mi_fifo_depth_ctrl_out[1:0]; + end + end + end + c_mi_mp_y_pic_width: begin + if (~cfg_mi_rd) + begin + mp_y_pic_width_out[31:0] <= cfg_mi_wdata[31:0]; + end + else + begin + if(cfg_mi_rd) + begin + cfg_mi_rdata[31:0] <= mp_y_pic_width_out[31:0]; + end + end + end + c_mi_mp_y_pic_height: begin + if (~cfg_mi_rd) + begin + mp_y_pic_height_out[31:0] <= cfg_mi_wdata[31:0]; + end + else + begin + if(cfg_mi_rd) + begin + cfg_mi_rdata[31:0] <= mp_y_pic_height_out[31:0]; + end + end + end + c_mi_mp_y_pic_size: begin + if (~cfg_mi_rd) + begin + mp_y_pic_size_out[31:0] <= cfg_mi_wdata[31:0]; + end + else + begin + if(cfg_mi_rd) + begin + cfg_mi_rdata[31:0] <= mp_y_pic_size_out[31:0]; + end + end + end + c_mi_bp_ctrl: begin + if (~cfg_mi_rd) + begin + viv_s131 <= cfg_mi_wdata[0]; + bp_auto_update <= cfg_mi_wdata[1]; + viv_s132 <= cfg_mi_wdata[5:2]; + viv_s133 <= cfg_mi_wdata[7:6]; + viv_s134 <= cfg_mi_wdata[9:8]; + bp_wr_burst_len <= cfg_mi_wdata[11:10]; + bp_wr_byte_swap <= cfg_mi_wdata[14:12]; + end + else + begin + if(cfg_mi_rd) + begin + cfg_mi_rdata[0] <= viv_s131; + cfg_mi_rdata[1] <= bp_auto_update; + cfg_mi_rdata[5:2] <= viv_s132; + cfg_mi_rdata[7:6] <= viv_s133; + cfg_mi_rdata[9:8] <= viv_s134; + cfg_mi_rdata[11:10]<= bp_wr_burst_len; + cfg_mi_rdata[14:12]<= bp_wr_byte_swap; + cfg_mi_rdata[31:15] <= {31-15+1{1'b0}}; + end + end + end + c_mi_bp_wr_size_shd: begin + if(cfg_mi_rd) + begin + cfg_mi_rdata[31:3] <= bp_wr_size[c_mi_data_addr:3]; + end + end + c_mi_bp_wr_size_init: begin + if (~cfg_mi_rd) + begin + bp_wr_size_init[c_mi_data_addr:3] <= cfg_mi_wdata[31:3]; + end + else + begin + if(cfg_mi_rd) + begin + cfg_mi_rdata[31:3] <= bp_wr_size_init[c_mi_data_addr:3]; + end + end + end + c_mi_bp_wr_llength: begin + if (~cfg_mi_rd) + begin + bp_wr_llength[14:0] <= cfg_mi_wdata[14:0]; + end + else + begin + if(cfg_mi_rd) + begin + cfg_mi_rdata[31:0] <= {{31-14{1'b0}},bp_wr_llength[14:0]}; + end + end + end + c_mi_bp_wr_offs_cnt_init: begin + if (~cfg_mi_rd) + begin + bp_wr_offs_cnt_init[c_mi_data_addr:3] <= cfg_mi_wdata[31:3]; + end + else + begin + if(cfg_mi_rd) + begin + cfg_mi_rdata[31:3] <= bp_wr_offs_cnt_init[c_mi_data_addr:3]; + end + end + end + c_mi_bp_wr_irq_offs_shd:begin + if(cfg_mi_rd)begin + cfg_mi_rdata[31:0] <= {bp_wr_irq_offs[c_mi_data_addr:3],3'b0}; + end + end + c_mi_bp_wr_irq_offs_init: begin + if (~cfg_mi_rd) + begin + bp_wr_irq_offs_init[c_mi_data_addr:3] <= cfg_mi_wdata[31:3]; + end + else + begin + if(cfg_mi_rd) + begin + cfg_mi_rdata[31:3] <= bp_wr_irq_offs_init[c_mi_data_addr:3]; + end + end + end + c_mi_bp_pic_width: begin + if (~cfg_mi_rd) + begin + bp_wr_pic_width[14:0] <= cfg_mi_wdata[14:0]; + end + else + begin + if(cfg_mi_rd) + begin + cfg_mi_rdata[31:0] <= {{31-14{1'b0}},bp_wr_pic_width[14:0]}; + end + end + end + c_mi_bp_pic_height: begin + if (~cfg_mi_rd) + begin + bp_wr_pic_height[14:0] <= cfg_mi_wdata[14:0]; + end + else + begin + if(cfg_mi_rd) + begin + cfg_mi_rdata[31:0] <= {{31-14{1'b0}},bp_wr_pic_height[14:0]}; + end + end + end + c_mi_bp_pic_size: begin + if (~cfg_mi_rd) begin + viv_s135 <= cfg_mi_wdata[c_mi_data_addr:0]; + end + else begin + cfg_mi_rdata <= viv_s135; + end + end + c_mi_bp_r_base_ad_shd: begin + if(cfg_mi_rd) + begin + cfg_mi_rdata[31:3] <= bp_r_base_ad[c_mi_data_addr+3:3]; + end + end + c_mi_bp_r_base_ad_init: begin + if (~cfg_mi_rd) + begin + bp_r_base_ad_init[c_mi_data_addr+3:3] <= cfg_mi_wdata[31:3]; + end + else + begin + if(cfg_mi_rd) + begin + cfg_mi_rdata[31:3] <= bp_r_base_ad_init[c_mi_data_addr+3:3]; + end + end + end + c_mi_bp_r_offs_cnt_start: begin + if(cfg_mi_rd) + begin + cfg_mi_rdata[31:3] <= bp_r_offs_cnt_start[c_mi_data_addr:3]; + end + end + c_mi_bp_gr_base_ad_shd: begin + if(cfg_mi_rd) + begin + cfg_mi_rdata[31:3] <= bp_gr_base_ad[c_mi_data_addr+3:3]; + end + end + c_mi_bp_gr_base_ad_init: begin + if (~cfg_mi_rd) + begin + bp_gr_base_ad_init[c_mi_data_addr+3:3] <= cfg_mi_wdata[31:3]; + end + else + begin + if(cfg_mi_rd) + begin + cfg_mi_rdata[31:3] <= bp_gr_base_ad_init[c_mi_data_addr+3:3]; + end + end + end + c_mi_bp_gr_offs_cnt_start: begin + if(cfg_mi_rd) + begin + cfg_mi_rdata[31:3] <= bp_gr_offs_cnt_start[c_mi_data_addr:3]; + end + end + c_mi_bp_gb_base_ad_shd: begin + if(cfg_mi_rd) + begin + cfg_mi_rdata[31:3] <= bp_gb_base_ad[c_mi_data_addr+3:3]; + end + end + c_mi_bp_gb_base_ad_init: begin + if (~cfg_mi_rd) + begin + bp_gb_base_ad_init[c_mi_data_addr+3:3] <= cfg_mi_wdata[31:3]; + end + else + begin + if(cfg_mi_rd) + begin + cfg_mi_rdata[31:3] <= bp_gb_base_ad_init[c_mi_data_addr+3:3]; + end + end + end + c_mi_bp_gb_offs_cnt_start: begin + if(cfg_mi_rd) + begin + cfg_mi_rdata[31:3] <= bp_gb_offs_cnt_start[c_mi_data_addr:3]; + end + end + c_mi_bp_b_base_ad_shd: begin + if(cfg_mi_rd) + begin + cfg_mi_rdata[31:3] <= bp_b_base_ad[c_mi_data_addr+3:3]; + end + end + c_mi_bp_r_offs_cnt_shd: begin + if(cfg_mi_rd)begin + cfg_mi_rdata[31:0] <= {bp_r_offs_cnt,3'b0}; + end + end + c_mi_bp_gr_offs_cnt_shd: begin + if(cfg_mi_rd)begin + cfg_mi_rdata[31:0] <= {bp_gr_offs_cnt,3'b0}; + end + end + c_mi_bp_gb_offs_cnt_shd: begin + if(cfg_mi_rd)begin + cfg_mi_rdata[31:0] <= {bp_gb_offs_cnt,3'b0}; + end + end + c_mi_bp_b_offs_cnt_shd: begin + if(cfg_mi_rd)begin + cfg_mi_rdata[31:0] <= {bp_b_offs_cnt,3'b0}; + end + end + c_mi_bp_b_base_ad_init: begin + if (~cfg_mi_rd) + begin + bp_b_base_ad_init[c_mi_data_addr+3:3] <= cfg_mi_wdata[31:3]; + end + else + begin + if(cfg_mi_rd) + begin + cfg_mi_rdata[31:3] <= bp_b_base_ad_init[c_mi_data_addr+3:3]; + end + end + end + c_mi_bp_b_offs_cnt_start: begin + if(cfg_mi_rd) + begin + cfg_mi_rdata[31:3] <= bp_b_offs_cnt_start[c_mi_data_addr:3]; + end + end + c_mi_mp_dma_y_raw_fmt:begin + if(~cfg_mi_rd)begin + viv_s5 <= cfg_mi_wdata[5:0]; + end + else begin + cfg_mi_rdata <= {26'h0, viv_s5[5:0]}; + end + end + c_mi_mp_dma_y_raw_lval:begin + if(~cfg_mi_rd)begin + dma_y_raw_lval <= cfg_mi_wdata[14:0]; + end + else begin + cfg_mi_rdata <= {17'h0, dma_y_raw_lval[14:0]}; + end + end + default: begin + end + endcase + end + if (viv_s72) begin + viv_s69 <= 1'b0; + end + if (viv_s78) begin + viv_s75 <= 1'b0; + end + end + end + wire bp_wr_path_enable_in; + wire [3:0] bp_wr_raw_bit_in; + wire [1:0] bp_wr_aligned_in; + wire [1:0] bp_wr_write_format_in; + wire [1:0] bp_wr_write_format_out; + vsisp_dreg_en_2d #(1,1'b0) u_bp_wr_path_enable_Reg (.clk(jpeg_clk), .reset_n(reset_jpeg_clk_n), .soft_reset(1'b0), .out(bp_wr_path_enable_in), .in(viv_s131), .en(1'b1)); + vsisp_dreg_en_2d #(4,4'b0) u_bp_wr_raw_bit_Reg (.clk(jpeg_clk), .reset_n(reset_jpeg_clk_n), .soft_reset(1'b0), .out(bp_wr_raw_bit_in), .in(viv_s132), .en(1'b1)); + vsisp_dreg_en_2d #(2,2'b0) u_bp_wr_aligned_Reg (.clk(jpeg_clk), .reset_n(reset_jpeg_clk_n), .soft_reset(1'b0), .out(bp_wr_aligned_in), .in(viv_s133), .en(1'b1)); + vsisp_dreg_en_2d #(2,2'b0) u_bp_wr_write_format_Reg (.clk(jpeg_clk), .reset_n(reset_jpeg_clk_n), .soft_reset(1'b0), .out(bp_wr_write_format_in), .in(viv_s134), .en(1'b1)); + wire [14:0] dma_y_pic_width_in; + wire [14:0] dma_y_llength_in; + wire [c_bufsize-1:0] dma_y_pic_size_in; + wire [5:0] dma_y_raw_fmt_in; + vsisp_dreg_en_2d #(15,15'b0) u_dma_y_pic_width_Reg (.clk(jpeg_clk), .reset_n(reset_jpeg_clk_n), .soft_reset(1'b0), .out(dma_y_pic_width_in), .in(dma_y_pic_width), .en(1'b1)); + vsisp_dreg_en_2d #(15,15'b0) u_dma_y_llength_Reg (.clk(jpeg_clk), .reset_n(reset_jpeg_clk_n), .soft_reset(1'b0), .out(dma_y_llength_in), .in(dma_y_llength), .en(1'b1)); + vsisp_dreg_en_2d #(c_bufsize,{c_bufsize{1'b0}}) u_dma_y_pic_size_Reg (.clk(jpeg_clk), .reset_n(reset_jpeg_clk_n), .soft_reset(1'b0), .out(dma_y_pic_size_in), .in(dma_y_pic_size), .en(1'b1)); + vsisp_dreg_en_2d #(6,6'b0) u_dma_y_raw_fmt_Reg (.clk(jpeg_clk), .reset_n(reset_jpeg_clk_n), .soft_reset(1'b0), .out(dma_y_raw_fmt_in), .in(viv_s5), .en(1'b1)); + vsisp_dreg_en_2d #(15,15'b0) u_dma_y_raw_lval_Reg (.clk(jpeg_clk), .reset_n(reset_jpeg_clk_n), .soft_reset(1'b0), .out(dma_y_raw_lval_in), .in(dma_y_raw_lval), .en(1'b1)); + assign bp_wr_path_enable_out = viv_s131; + assign bp_wr_write_format_out= viv_s134; + always @(*) begin + viv_s126 = 2'b0; + viv_s122 = 1'b0; + viv_s123 = 1'b0; + viv_s124 = 1'b0; + viv_s125 = 1'b0; + case (viv_s6) + 4'b0001: begin + viv_s122 = 1'b1; + end + 4'b0010: begin + viv_s123 = 1'b1; + end + 4'b0011: begin + viv_s122 = 1'b1; + viv_s123 = 1'b1; + end + 4'b0100: begin + viv_s124 = 1'b1; + end + 4'b0110: begin + viv_s123 = 1'b1; + viv_s124 = 1'b1; + end + 4'b1000: begin + viv_s125 = 1'b1; + end + 4'b1001: begin + viv_s122 = 1'b1; + viv_s126 = 2'b10; + end + 4'b1010: begin + viv_s123 = 1'b1; + viv_s126 = 2'b01; + end + 4'b1100: begin + viv_s124 = 1'b1; + viv_s126 = 2'b10; + end + 4'b1101: begin + viv_s126 = 2'b01; + end + 4'b1110: begin + viv_s126 = 2'b10; + end + 4'b1111: begin + viv_s125 = 1'b1; + viv_s126 = 2'b10; + end + default: begin + end + endcase + end + assign viv_s129 = {stat_dp_enable_out,stat_raw_enable_out, + stat_jpeg_enable_out,stat_sp_enable_out, + stat_mp_enable_out}; + assign viv_s130 = {viv_s97, viv_s99, + viv_s95,viv_s93, + viv_s91}; + always @(*) begin + if (viv_s126 == 2'b00) begin + viv_s127 = {stat_raw_enable_out, stat_jpeg_enable_out, + stat_sp_enable_out, stat_mp_enable_out}; + viv_s128 = {viv_s99, viv_s95, + viv_s93, viv_s91}; + end + else begin + case (viv_s129) + 6'b100001: begin + viv_s127 = 4'b1001; + end + 6'b010010: begin + viv_s127 = 4'b1010; + end + 6'b100100: begin + viv_s127 = 4'b1100; + end + 6'b010000: begin + viv_s127 = 4'b1101; + end + 6'b100000: begin + viv_s127 = 4'b1110; + end + 6'b101000: begin + viv_s127 = 4'b1111; + end + default: begin + viv_s127 = 4'b0000; + end + endcase + case (viv_s130) + 6'b100001: begin + viv_s128 = 4'b1001; + end + 6'b010010: begin + viv_s128 = 4'b1010; + end + 6'b100100: begin + viv_s128 = 4'b1100; + end + 6'b010000: begin + viv_s128 = 4'b1101; + end + 6'b100000: begin + viv_s128 = 4'b1110; + end + 6'b101000: begin + viv_s128 = 4'b1111; + end + default: begin + viv_s128 = 4'b0000; + end + endcase + end + end + always @(posedge m_hclk or negedge reset_m_hclk_n) begin + if (~reset_m_hclk_n) begin + viv_s30 <= {14+c_bp_int_cnt{1'b0}}; + end + else begin + viv_s30 <= viv_s31; + end + end + always @(*) begin + viv_s32 = viv_s30; + if (cfg_mi_val & ({cfg_mi_addr, 2'b00} == c_mi_icr)) begin + if (~cfg_mi_rd) begin + viv_s32 = viv_s30 & ~(cfg_mi_wdata[13+c_bp_int_cnt:0]); + end + end + else if (cfg_mi_val && ({cfg_mi_addr, 2'b00} == c_mi_isr)) begin + if (~cfg_mi_rd) begin + viv_s32 = viv_s30 | cfg_mi_wdata[13+c_bp_int_cnt:0]; + end + end + end + always @(*) begin + viv_s31[ 0] = viv_s32[ 0] | stat_mp_frame_end; + viv_s31[ 1] = viv_s32[ 1] | stat_sp_frame_end; + viv_s31[ 2] = viv_s32[ 2] | stat_mblk_line; + viv_s31[ 3] = viv_s32[ 3] | stat_fill_mp_y; + viv_s31[ 4] = viv_s32[ 4] | stat_wrap_mp_y; + viv_s31[ 5] = viv_s32[ 5] | stat_wrap_mp_cb; + viv_s31[ 6] = viv_s32[ 6] | stat_wrap_mp_cr; + viv_s31[ 7] = viv_s32[ 7] | stat_wrap_sp_y; + viv_s31[ 8] = viv_s32[ 8] | stat_wrap_sp_cb; + viv_s31[ 9] = viv_s32[ 9] | stat_wrap_sp_cr; + viv_s31[10] = 1'b0; + viv_s31[11] = viv_s32[11] | stat_dma_ready; + viv_s31[12] = viv_s32[12] | mp_interrupt; + viv_s31[13] = viv_s32[13] | sw_interrupt; + viv_s31[14] = viv_s32[14] | stat_bp_frame_end; + viv_s31[15] = viv_s32[15] | stat_fill_bp_r; + viv_s31[16] = viv_s32[16] | stat_wrap_bp_r; + viv_s31[17] = viv_s32[17] | stat_wrap_bp_gr; + viv_s31[18] = viv_s32[18] | stat_wrap_bp_gb; + viv_s31[19] = viv_s32[19] | stat_wrap_bp_b; + end + always @(posedge m_hclk or negedge reset_m_hclk_n) begin + if (~reset_m_hclk_n) begin + viv_s33 <= {6+3{1'b0}}; + end + else begin + viv_s33 <= viv_s34; + end + end + always @(*) begin + viv_s35 = viv_s33; + if (cfg_mi_val && ({cfg_mi_addr, 2'b00} == c_mi_status_clr)) begin + if (~cfg_mi_rd) begin + viv_s35 = viv_s33 & ~({cfg_mi_wdata[6+3:4],cfg_mi_wdata[2:0]}); + end + end + end + always @(*) begin + viv_s34[0] = viv_s35[0] | viv_s105; + viv_s34[1] = viv_s35[1] | viv_s107; + viv_s34[2] = viv_s35[2] | viv_s109; + viv_s34[3] = viv_s35[3] | viv_s111; + viv_s34[4] = viv_s35[4] | viv_s113; + viv_s34[5] = viv_s35[5] | viv_s115; + viv_s34[6] = viv_s35[6] | viv_s117; + viv_s34[7] = viv_s35[7] | viv_s119; + viv_s34[8] = viv_s35[8] | viv_s121; + end + assign mi_mp_frame_end_int = viv_s30[ 0] & viv_s20[ 0]; + assign mi_sp_frame_end_int = viv_s30[ 1] & viv_s20[ 1]; + assign mi_mblk_line_int = viv_s30[ 2] & viv_s20[ 2]; + assign mi_fill_mp_y_int = viv_s30[ 3] & viv_s20[ 3]; + assign mi_wrap_mp_y_int = viv_s30[ 4] & viv_s20[ 4]; + assign mi_wrap_mp_cb_int = viv_s30[ 5] & viv_s20[ 5]; + assign mi_wrap_mp_cr_int = viv_s30[ 6] & viv_s20[ 6]; + assign mi_wrap_sp_y_int = viv_s30[ 7] & viv_s20[ 7]; + assign mi_wrap_sp_cb_int = viv_s30[ 8] & viv_s20[ 8]; + assign mi_wrap_sp_cr_int = viv_s30[ 9] & viv_s20[ 9]; + assign mi_dma_ready_int = viv_s30[11] & viv_s21; + assign mi_mp_handshk_int = viv_s30[12] & viv_s22; + assign mi_mp_handshk_sw_int = viv_s30[13] & viv_s23; + assign mi_bp_frame_end_int = viv_s30[14] & viv_s24; + assign mi_fill_bp_r_int = viv_s30[15] & viv_s25; + assign mi_wrap_bp_r_int = viv_s30[16] & viv_s26; + assign mi_wrap_bp_gr_int = viv_s30[17] & viv_s27; + assign mi_wrap_bp_gb_int = viv_s30[18] & viv_s28; + assign mi_wrap_bp_b_int = viv_s30[19] & viv_s29; + always @(posedge jpeg_clk or negedge reset_jpeg_clk_n) begin + if (~reset_jpeg_clk_n) begin + viv_s36 <= 1'b0; + viv_s37 <= 1'b0; + viv_s38 <= 1'b0; + viv_s39 <= 1'b0; + viv_s40 <= 1'b0; + viv_s41 <= 1'b0; + viv_s42 <= 2'b0; + viv_s43 <= 2'b0; + viv_s44 <= 1'b0; + viv_s45 <= 1'b0; + viv_s46 <= 1'b0; + viv_s47 <= 1'b0; + viv_s48 <= 1'b0; + viv_s49 <= 1'b0; + viv_s50 <= 1'b0; + viv_s51 <= 1'b0; + viv_s52 <= 1'b0; + viv_s53 <= 2'b00; + viv_s54 <= 2'b00; + viv_s55 <= 2'b00; + viv_s56 <= 2'b00; + viv_s57 <= 2'b00; + viv_s58 <= 2'b00; + viv_s59 <= 3'b000; + viv_s60 <= 3'b000; + end + else begin + viv_s36 <= viv_s122; + viv_s37 <= viv_s36; + viv_s38 <= viv_s123; + viv_s39 <= viv_s38; + viv_s40 <= viv_s124; + viv_s41 <= viv_s40; + viv_s42 <= viv_s126; + viv_s43 <= viv_s42; + viv_s44 <= viv_s125; + viv_s45 <= viv_s44; + viv_s46 <= viv_s7; + viv_s47 <= viv_s46; + viv_s48 <= viv_s9; + viv_s49 <= viv_s48; + viv_s50 <= viv_s2; + viv_s51 <= viv_s3; + viv_s52 <= viv_s4; + viv_s53 <= viv_s10; + viv_s54 <= viv_s53; + viv_s55 <= viv_s11; + viv_s56 <= viv_s55; + viv_s57 <= viv_s12; + viv_s58 <= viv_s57; + viv_s59 <= viv_s13; + viv_s60 <= viv_s59; + end + end + assign mp_enable_in = viv_s37; + assign mp_enable_out = viv_s122; + assign sp_enable_in = viv_s39; + assign sp_enable_out = viv_s123; + assign jpeg_enable_in = viv_s41; + assign jpeg_enable_out = viv_s124; + assign dp_enable_in = viv_s43; + assign dp_enable_out = viv_s126; + assign raw_enable_in = viv_s45; + assign raw_enable_out = viv_s125; + assign h_flip_in = viv_s47; + assign h_flip_out = viv_s7; + assign v_flip_out = viv_s8; + assign rot_in = viv_s49; + assign rot_out = viv_s9; + assign mp_write_format_in = viv_s54; + assign mp_write_format_out = viv_s10; + assign sp_write_format_in = viv_s56; + assign cfg_y_full = viv_s50; + assign cfg_crcb_full = viv_s51; + assign cfg_422noncosited = viv_s52; + assign sp_write_format_out = viv_s11; + assign sp_input_format_in = viv_s58; + assign sp_output_format_in = viv_s60; + assign sp_output_format_out = viv_s13; + always @(posedge m_hclk or negedge reset_m_hclk_n) begin + if (~reset_m_hclk_n) begin + viv_s61 <= 1'b0; + viv_s64 <= 1'b0; + viv_s65 <= 1'b0; + viv_s62 <= 1'b0; + viv_s63 <= 1'b0; + end + else begin + if (viv_s14) + viv_s61 <= 1'b1; + else if (viv_s63) + viv_s61 <= 1'b0; + viv_s64 <= viv_s14; + viv_s65 <= viv_s14 | viv_s64; + viv_s62 <= viv_s67; + viv_s63 <= viv_s62; + end + end + assign soft_upd_out = viv_s65; + always @(posedge jpeg_clk or negedge reset_jpeg_clk_n) begin + if (~reset_jpeg_clk_n) begin + viv_s66 <= 1'b0; + viv_s67 <= 1'b0; + viv_s68 <= 1'b0; + end + else begin + viv_s66 <= viv_s61; + viv_s67 <= viv_s66; + viv_s68 <= viv_s67; + end + end + always @(posedge jpeg_clk or negedge reset_jpeg_clk_n) begin + if (~reset_jpeg_clk_n) begin + soft_upd_in <= 1'b0; + end + else begin + soft_upd_in <= viv_s67 & ~viv_s68; + end + end + always @(posedge jpeg_clk or negedge reset_jpeg_clk_n) begin + if (~reset_jpeg_clk_n) begin + viv_s70 <= 1'b0; + viv_s71 <= 1'b0; + end + else begin + viv_s70 <= viv_s69; + viv_s71 <= viv_s70; + end + end + always @(posedge jpeg_clk or negedge reset_jpeg_clk_n) begin + if (~reset_jpeg_clk_n) begin + sp_y_pic_width_in <= 15'h0; + end + else if (viv_s71) begin + sp_y_pic_width_in <= sp_y_pic_width[14:0]; + end + end + always @(posedge m_hclk_cfg or negedge reset_m_hclk_cfg_n) begin + if (~reset_m_hclk_cfg_n) begin + viv_s73 <= 1'b0; + viv_s74 <= 1'b0; + end + else begin + viv_s73 <= viv_s71; + viv_s74 <= viv_s73; + end + end + assign viv_s72 = viv_s74; + always @(posedge jpeg_clk or negedge reset_jpeg_clk_n) begin + if (~reset_jpeg_clk_n) begin + viv_s76 <= 1'b0; + viv_s77 <= 1'b0; + end + else begin + viv_s76 <= viv_s75; + viv_s77 <= viv_s76; + end + end + always @(posedge jpeg_clk or negedge reset_jpeg_clk_n) begin + if (~reset_jpeg_clk_n) begin + sp_y_pic_height_in <= 15'h0; + end + else if (viv_s77) begin + sp_y_pic_height_in <= viv_s15; + end + end + always @(posedge m_hclk_cfg or negedge reset_m_hclk_cfg_n) begin + if (~reset_m_hclk_cfg_n) begin + viv_s79 <= 1'b0; + viv_s80 <= 1'b0; + end + else begin + viv_s79 <= viv_s77; + viv_s80 <= viv_s79; + end + end + assign viv_s78 = viv_s80; + always @(posedge m_hclk or negedge reset_m_hclk_n) begin + if (~reset_m_hclk_n) begin + viv_s81 <= 1'b0; + viv_s82 <= 1'b0; + viv_s83 <= 1'b0; + viv_s84 <= 1'b0; + viv_s85 <= 1'b0; + viv_s86 <= 1'b0; + viv_s87 <= 1'b0; + viv_s88 <= 1'b0; + viv_s89 <= 1'b0; + end + else begin + viv_s81 <= stat_byte_cnt_raw_val; + viv_s82 <= viv_s81; + viv_s83 <= viv_s82; + viv_s84 <= stat_byte_cnt_jpeg_val; + viv_s85 <= viv_s84; + viv_s86 <= viv_s85; + viv_s87 <= stat_byte_cnt_dp_val; + viv_s88 <= viv_s87; + viv_s89 <= viv_s88; + end + end + always @(posedge m_hclk or negedge reset_m_hclk_n) begin + if (~reset_m_hclk_n) begin + viv_s16 <= {c_bufsize{1'b0}}; + end + else if (viv_s82 & ~viv_s83) begin + viv_s16 <= stat_byte_cnt_raw; + end + else if (viv_s85 & ~viv_s86) begin + viv_s16 <= stat_byte_cnt_jpeg; + end + end + always @(posedge m_hclk or negedge reset_m_hclk_n) begin + if (~reset_m_hclk_n) begin + viv_s17 <= {c_bufsize{1'b0}}; + end + else if (viv_s88 & ~viv_s89) begin + viv_s17 <= stat_byte_cnt_dp; + end + end + assign stat_byte_cnt_raw_ack = viv_s83; + assign stat_byte_cnt_jpeg_ack = viv_s86; + assign stat_byte_cnt_dp_ack = viv_s89; + always @(posedge jpeg_clk or negedge reset_jpeg_clk_n) begin + if (~reset_jpeg_clk_n) begin + viv_s90 <= 1'b0; + viv_s91 <= 1'b0; + viv_s92 <= 1'b0; + viv_s93 <= 1'b0; + viv_s94 <= 1'b0; + viv_s95 <= 1'b0; + viv_s96 <= 2'b0; + viv_s97 <= 2'b0; + viv_s98 <= 1'b0; + viv_s99 <= 1'b0; + end + else begin + viv_s90 <= stat_mp_enable_in; + viv_s91 <= viv_s90; + viv_s92 <= stat_sp_enable_in; + viv_s93 <= viv_s92; + viv_s94 <= stat_jpeg_enable_in; + viv_s95 <= viv_s94; + viv_s96 <= stat_dp_enable_in; + viv_s97 <= viv_s96; + viv_s98 <= stat_raw_enable_in; + viv_s99 <= viv_s98; + end + end + reg viv_s136; + reg viv_s137; + reg viv_s138; + always @(posedge clk or negedge reset_n) begin + if (~reset_n) begin + viv_s100 <= 2'b00; + viv_s101 <= 2'b00; + viv_s102 <= 2'b00; + viv_s103 <= 2'b00; + viv_s136 <= 1'b0; + viv_s137 <= 1'b0; + viv_s138 <= 1'b0; + end + else begin + viv_s100 <= viv_s18; + viv_s101 <= viv_s100; + viv_s102 <= viv_s19; + viv_s103 <= viv_s102; + viv_s136 <= stat_mp_y_full; + viv_s137 <= stat_mp_cb_full; + viv_s138 <= stat_mp_cr_full; + end + end + assign dma_read_format_in = 2'b10; + assign dma_read_format_out = 2'b10; + assign dma_rgb_format_in = 2'b10; + assign dma_rgb_format_out = 2'b01; + always @(posedge jpeg_clk or negedge reset_jpeg_clk_n) begin + if (~reset_jpeg_clk_n) begin + viv_s104 <= 1'b0; + viv_s105 <= 1'b0; + viv_s106 <= 1'b0; + viv_s107 <= 1'b0; + viv_s108 <= 1'b0; + viv_s109 <= 1'b0; + viv_s110 <= 1'b0; + viv_s111 <= 1'b0; + viv_s112 <= 1'b0; + viv_s113 <= 1'b0; + viv_s114 <= 1'b0; + viv_s115 <= 1'b0; + viv_s116 <= 1'b0; + viv_s117 <= 1'b0; + viv_s118 <= 1'b0; + viv_s119 <= 1'b0; + viv_s120 <= 1'b0; + viv_s121 <= 1'b0; + end + else begin + viv_s104 <= viv_s136; + viv_s105 <= viv_s104; + viv_s106 <= viv_s137; + viv_s107 <= viv_s106; + viv_s108 <= viv_s138; + viv_s109 <= viv_s108; + viv_s110 <= stat_sp_y_full; + viv_s111 <= viv_s110; + viv_s112 <= stat_sp_cb_full; + viv_s113 <= viv_s112; + viv_s114 <= stat_sp_cr_full; + viv_s115 <= viv_s114; + viv_s116 <= stat_bp_in_full; + viv_s117 <= viv_s116; + viv_s118 <= stat_bp_ecl_full; + viv_s119 <= viv_s118; + viv_s120 <= stat_bp_ocl_full; + viv_s121 <= viv_s120; + end + end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_marvin_mi_swap.v b/ispyocto/rtl/ispyocto/vsisp_marvin_mi_swap.v new file mode 100644 index 0000000..593473f --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_marvin_mi_swap.v
@@ -0,0 +1,161 @@ +//**************************************************************************** +// +// Copyright 2023 Vivante Corp. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_marvin_mi_swap ( + swap_vector, + data_to_swap, + swapped_data); +input [3:0] swap_vector; +input [127:0] data_to_swap; +output [127:0] swapped_data; +wire [127:0] swapped_data; +reg [63:0] viv_s0; +reg [63:0] viv_s1; +reg [31:0] viv_s2; +reg [31:0] viv_s3; +reg [31:0] viv_s4; +reg [31:0] viv_s5; +reg [15:0] viv_s6; +reg [15:0] viv_s7; +reg [15:0] viv_s8; +reg [15:0] viv_s9; +reg [15:0] viv_s10; +reg [15:0] viv_s11; +reg [15:0] viv_s12; +reg [15:0] viv_s13; +reg [7:0] viv_s14; +reg [7:0] viv_s15; +reg [7:0] viv_s16; +reg [7:0] viv_s17; +reg [7:0] viv_s18; +reg [7:0] viv_s19; +reg [7:0] viv_s20; +reg [7:0] viv_s21; +reg [7:0] viv_s22; +reg [7:0] viv_s23; +reg [7:0] viv_s24; +reg [7:0] viv_s25; +reg [7:0] viv_s26; +reg [7:0] viv_s27; +reg [7:0] viv_s28; +reg [7:0] viv_s29; +assign swapped_data = {viv_s29, viv_s28, viv_s27, viv_s26, + viv_s25, viv_s24, viv_s23, viv_s22, + viv_s21, viv_s20, viv_s19, viv_s18, + viv_s17, viv_s16, viv_s15, viv_s14}; +always @(swap_vector or data_to_swap) + begin : swap_64bits_proc + if (swap_vector[3] == 1'b 0) + begin + viv_s0 = data_to_swap[63:0]; + viv_s1 = data_to_swap[127:64]; + end + else + begin + viv_s0 = data_to_swap[127:64]; + viv_s1 = data_to_swap[63:0]; + end + end +always @(swap_vector or viv_s0 or viv_s1) + begin : swap_32bits_proc + if (swap_vector[2] == 1'b 0) + begin + viv_s2 = viv_s0[31:0]; + viv_s3 = viv_s0[63:32]; + viv_s4 = viv_s1[31:0]; + viv_s5 = viv_s1[63:32]; + end + else + begin + viv_s2 = viv_s0[63:32]; + viv_s3 = viv_s0[31:0]; + viv_s4 = viv_s1[63:32]; + viv_s5 = viv_s1[31:0]; + end + end +always @(swap_vector or viv_s2 or viv_s3 or viv_s4 or viv_s5) + begin : swap_16bits_proc + if (swap_vector[1] == 1'b 0) + begin + viv_s6 = viv_s2[15:0]; + viv_s7 = viv_s2[31:16]; + viv_s8 = viv_s3[15:0]; + viv_s9 = viv_s3[31:16]; + viv_s10 = viv_s4[15:0]; + viv_s11 = viv_s4[31:16]; + viv_s12 = viv_s5[15:0]; + viv_s13 = viv_s5[31:16]; + end + else + begin + viv_s6 = viv_s2[31:16]; + viv_s7 = viv_s2[15:0]; + viv_s8 = viv_s3[31:16]; + viv_s9 = viv_s3[15:0]; + viv_s10 = viv_s4[31:16]; + viv_s11 = viv_s4[15:0]; + viv_s12 = viv_s5[31:16]; + viv_s13 = viv_s5[15:0]; + end + end +always @(swap_vector or viv_s6 or viv_s7 or viv_s8 or viv_s9 + or viv_s10 or viv_s11 or viv_s12 or viv_s13) + begin : swap_final_bytes_proc + if (swap_vector[0] == 1'b 0) + begin + viv_s14 = viv_s6[7:0]; + viv_s15 = viv_s6[15:8]; + viv_s16 = viv_s7[7:0]; + viv_s17 = viv_s7[15:8]; + viv_s18 = viv_s8[7:0]; + viv_s19 = viv_s8[15:8]; + viv_s20 = viv_s9[7:0]; + viv_s21 = viv_s9[15:8]; + viv_s22 = viv_s10[7:0]; + viv_s23 = viv_s10[15:8]; + viv_s24 = viv_s11[7:0]; + viv_s25 = viv_s11[15:8]; + viv_s26 = viv_s12[7:0]; + viv_s27 = viv_s12[15:8]; + viv_s28 = viv_s13[7:0]; + viv_s29 = viv_s13[15:8]; + end + else + begin + viv_s14 = viv_s6[15:8]; + viv_s15 = viv_s6[7:0]; + viv_s16 = viv_s7[15:8]; + viv_s17 = viv_s7[7:0]; + viv_s18 = viv_s8[15:8]; + viv_s19 = viv_s8[7:0]; + viv_s20 = viv_s9[15:8]; + viv_s21 = viv_s9[7:0]; + viv_s22 = viv_s10[15:8]; + viv_s23 = viv_s10[7:0]; + viv_s24 = viv_s11[15:8]; + viv_s25 = viv_s11[7:0]; + viv_s26 = viv_s12[15:8]; + viv_s27 = viv_s12[7:0]; + viv_s28 = viv_s13[15:8]; + viv_s29 = viv_s13[7:0]; + end + end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_marvin_pvci_reg_stage.v b/ispyocto/rtl/ispyocto/vsisp_marvin_pvci_reg_stage.v new file mode 100644 index 0000000..9737d25 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_marvin_pvci_reg_stage.v
@@ -0,0 +1,79 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_marvin_pvci_reg_stage + ( clk, + reset_n, + pwdata_i, + paddr_i, + pval_i, + prd_i, + pack_o, + prdata_o, + pwdata_o, + paddr_o, + pval_o, + prd_o, + pack_i, + prdata_i + ); + parameter c_data_width = 32; + input clk; + input reset_n; + input [c_data_width-1:0] pwdata_i; + input [c_data_width-1:0] paddr_i; + input pval_i; + input prd_i; + output pack_o; + output [c_data_width-1:0] prdata_o; + output [c_data_width-1:0] pwdata_o; + input [c_data_width-1:0] prdata_i; + output [c_data_width-1:0] paddr_o; + output pval_o; + output prd_o; + input pack_i; + reg [c_data_width-1:0] prdata_o; + reg pval_o; + reg pack_o; + reg [c_data_width-1:0] pwdata_o; + reg [c_data_width-1:0] paddr_o; + reg prd_o; + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + prdata_o <= 32'b0; + pwdata_o <= 32'b0; + paddr_o <= 32'b0; + pval_o <= 1'b0; + pack_o <= 1'b0; + prd_o <= 1'b0; + end + else begin + prdata_o <= prdata_i; + pwdata_o <= pwdata_i; + paddr_o <= paddr_i; + pval_o <= pval_i && ~pack_i && ~pack_o; + pack_o <= pack_i; + prd_o <= prd_i; + end + end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_marvin_top_a.v b/ispyocto/rtl/ispyocto/vsisp_marvin_top_a.v new file mode 100644 index 0000000..346a788 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_marvin_top_a.v
@@ -0,0 +1,1710 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_marvin_top_a + ( + clk, + reset_n, + sclk, + s_hclk, + m_hclk, + regs_disable_isp_clk, + axi_m1_marvin_awvalid, + axi_m1_marvin_awaddr, + axi_m1_marvin_awlen, + axi_m1_marvin_awsize, + axi_m1_marvin_awburst, + axi_m1_marvin_awlock, + axi_m1_marvin_awcache, + axi_m1_marvin_awprot, + axi_m1_marvin_awid, + axi_m1_marvin_awready, + axi_m1_marvin_wvalid, + axi_m1_marvin_wlast, + axi_m1_marvin_wdata, + axi_m1_marvin_wstrb, + axi_m1_marvin_wid, + axi_m1_marvin_wready, + axi_m1_marvin_bvalid, + axi_m1_marvin_bresp, + axi_m1_marvin_bid, + axi_m1_marvin_bready, + axi_m2_marvin_awvalid, + axi_m2_marvin_awaddr, + axi_m2_marvin_awlen, + axi_m2_marvin_awsize, + axi_m2_marvin_awburst, + axi_m2_marvin_awlock, + axi_m2_marvin_awcache, + axi_m2_marvin_awprot, + axi_m2_marvin_awid, + axi_m2_marvin_awready, + axi_m2_marvin_wvalid, + axi_m2_marvin_wlast, + axi_m2_marvin_wdata, + axi_m2_marvin_wstrb, + axi_m2_marvin_wid, + axi_m2_marvin_wready, + axi_m2_marvin_bvalid, + axi_m2_marvin_bresp, + axi_m2_marvin_bid, + axi_m2_marvin_bready, + hsel_s, + haddr_s, + htrans_s, + hwrite_s, + hwdata_s, + hrdata_s, + hresp_s, + hready_s, + s_data, + s_hsync, + s_vsync, + s_valid, + disable_isp, + scan_mode, + mi_irq, + isp_irq, + isp_fifo_ram_clk, + isp_fifo_cs_n, + isp_fifo_wr_n, + isp_fifo_addr, + isp_fifo_wdata, + isp_fifo_rdata, + isp_rgb_ram_clk, + isp_ispram_addr, + isp_ispram_wdata, + isp_ispram_rdata, + isp_ispram_wr_n, + isp_ispram_cs_n, + rszm_mram_clk, + rszm_mramy_wr_n, + rszm_mramy_cs_n, + rszm_mramy_addr, + rszm_mramy_wdata, + rszm_mramy_rdata, + rszm_mramc_wr_n, + rszm_mramc_cs_n, + rszm_mramc_addr, + rszm_mramc_wdata, + rszm_mramc_rdata, + rszs_sram_clk, + rszs_sramy_wr_n, + rszs_sramy_cs_n, + rszs_sramy_addr, + rszs_sramy_wdata, + rszs_sramy_rdata, + rszs_sramc_wr_n, + rszs_sramc_cs_n, + rszs_sramc_addr, + rszs_sramc_wdata, + rszs_sramc_rdata, + mp_y_fifo_sram_wdata , + mp_y_fifo_sram_rdata , + mp_y_fifo_sram_addr , + mp_y_fifo_sram_cs_n , + mp_y_fifo_sram_we_n , + mp_cb_fifo_sram_wdata , + mp_cb_fifo_sram_rdata , + mp_cb_fifo_sram_addr , + mp_cb_fifo_sram_cs_n , + mp_cb_fifo_sram_we_n , + mp_cr_fifo_sram_wdata , + mp_cr_fifo_sram_rdata , + mp_cr_fifo_sram_addr , + mp_cr_fifo_sram_cs_n , + mp_cr_fifo_sram_we_n , + out_y_r_frame_start, + out_y_r_frame_end, + out_y_r_line_start, + out_y_r_line_end, + out_cb_g_frame_start, + out_cb_g_frame_end, + out_cb_g_line_start, + out_cb_g_line_end, + out_cr_b_frame_start, + out_cr_b_frame_end, + out_cr_b_line_start, + out_cr_b_line_end, + out_y_r_ack_stream, + out_cb_g_ack_stream, + out_cr_b_ack_stream, + out_y_r_val_stream, + out_y_r_data_stream, + out_cb_g_val_stream, + out_cb_g_data_stream, + out_cr_b_val_stream, + out_cr_b_data_stream + ); + parameter c_cfg_addr_word = 32; + parameter c_cfg_wdata_word = 32; + parameter c_cfg_rdata16_word = 16; + parameter c_cfg_rdata32_word = 32; + parameter c_prdata_word = 32; +`include "vsisp_marvin_id.vh" +`include "vsisp_isp.vh" +`include "vsisp_jpeg_r2b.vh" +`include "vsisp_ram_sizes.vh" + input clk; + input reset_n; + input sclk; + input s_hclk; + input m_hclk; + output regs_disable_isp_clk; + output axi_m1_marvin_awvalid; + output [31:3] axi_m1_marvin_awaddr; + output [3:0] axi_m1_marvin_awlen; + output [2:0] axi_m1_marvin_awsize; + output [1:0] axi_m1_marvin_awburst; + output [1:0] axi_m1_marvin_awlock; + output [3:0] axi_m1_marvin_awcache; + output [2:0] axi_m1_marvin_awprot; + output [3:0] axi_m1_marvin_awid; + input axi_m1_marvin_awready; + output axi_m1_marvin_wvalid; + output axi_m1_marvin_wlast; + output [63:0] axi_m1_marvin_wdata; + output [7:0] axi_m1_marvin_wstrb; + output [3:0] axi_m1_marvin_wid; + input axi_m1_marvin_wready; + input axi_m1_marvin_bvalid; + input [1:0] axi_m1_marvin_bresp; + input [3:0] axi_m1_marvin_bid; + output axi_m1_marvin_bready; + output axi_m2_marvin_awvalid; + output [31:3] axi_m2_marvin_awaddr; + output [3:0] axi_m2_marvin_awlen; + output [2:0] axi_m2_marvin_awsize; + output [1:0] axi_m2_marvin_awburst; + output [1:0] axi_m2_marvin_awlock; + output [3:0] axi_m2_marvin_awcache; + output [2:0] axi_m2_marvin_awprot; + output [3:0] axi_m2_marvin_awid; + input axi_m2_marvin_awready; + output axi_m2_marvin_wvalid; + output axi_m2_marvin_wlast; + output [63:0] axi_m2_marvin_wdata; + output [7:0] axi_m2_marvin_wstrb; + output [3:0] axi_m2_marvin_wid; + input axi_m2_marvin_wready; + input axi_m2_marvin_bvalid; + input [1:0] axi_m2_marvin_bresp; + input [3:0] axi_m2_marvin_bid; + output axi_m2_marvin_bready; + wire axi_rd_marvin_arvalid; + wire [31:3] axi_rd_marvin_araddr; + wire [3:0] axi_rd_marvin_arlen; + wire [2:0] axi_rd_marvin_arsize; + wire [1:0] axi_rd_marvin_arburst; + wire [1:0] axi_rd_marvin_arlock; + wire [3:0] axi_rd_marvin_arcache; + wire [2:0] axi_rd_marvin_arprot; + wire [3:0] axi_rd_marvin_arid; + wire axi_rd_marvin_arready; + wire axi_rd_marvin_rvalid; + wire axi_rd_marvin_rlast; + wire [63:0] axi_rd_marvin_rdata; + wire [1:0] axi_rd_marvin_rresp; + wire [3:0] axi_rd_marvin_rid; + wire axi_rd_marvin_rready; + input hsel_s; + input [31:0] haddr_s; + input [1:0] htrans_s; + input hwrite_s; + input [31:0] hwdata_s; + output [31:0] hrdata_s; + output [1:0] hresp_s; + output hready_s; + input [11:0] s_data; + input s_hsync; + input s_vsync; + input s_valid; + input disable_isp; + input scan_mode; + output mi_irq; + output isp_irq; + output out_y_r_frame_start; + output out_y_r_frame_end; + output out_y_r_line_start; + output out_y_r_line_end; + output out_cb_g_frame_start; + output out_cb_g_frame_end; + output out_cb_g_line_start; + output out_cb_g_line_end; + output out_cr_b_frame_start; + output out_cr_b_frame_end; + output out_cr_b_line_start; + output out_cr_b_line_end; + output out_y_r_val_stream; + output wire [ 7: 0] out_y_r_data_stream; + output out_cb_g_val_stream; + output wire [ 7: 0] out_cb_g_data_stream; + output out_cr_b_val_stream; + output wire [ 7: 0] out_cr_b_data_stream; + input out_y_r_ack_stream; + input out_cb_g_ack_stream; + input out_cr_b_ack_stream; + output isp_fifo_ram_clk; + output isp_fifo_cs_n; + output isp_fifo_wr_n; + output [c_ispfifo_aw-1:0] isp_fifo_addr; + output [c_ispfifo_dw-1:0] isp_fifo_wdata; + input [c_ispfifo_dw-1:0] isp_fifo_rdata; + output isp_rgb_ram_clk; + output [c_aw_dem_mem-1:0] isp_ispram_addr; + output [c_dw_dem_mem-1:0] isp_ispram_wdata; + input [c_dw_dem_mem-1:0] isp_ispram_rdata; + output isp_ispram_wr_n; + output isp_ispram_cs_n; + output rszm_mram_clk; + output rszm_mramy_wr_n; + output rszm_mramy_cs_n; + output [c_aw_mrsz-1:0] rszm_mramy_addr; + output [31:0] rszm_mramy_wdata; + input [31:0] rszm_mramy_rdata; + output rszm_mramc_wr_n; + output rszm_mramc_cs_n; + output [c_aw_mrsz-1:0] rszm_mramc_addr; + output [31:0] rszm_mramc_wdata; + input [31:0] rszm_mramc_rdata; + output rszs_sram_clk; + output rszs_sramy_wr_n; + output rszs_sramy_cs_n; + output [c_aw_srsz-1:0] rszs_sramy_addr; + output [31:0] rszs_sramy_wdata; + input [31:0] rszs_sramy_rdata; + output rszs_sramc_wr_n; + output rszs_sramc_cs_n; + output [c_aw_srsz-1:0] rszs_sramc_addr; + output [31:0] rszs_sramc_wdata; + input [31:0] rszs_sramc_rdata; + output [65:0] mp_y_fifo_sram_wdata ; + input [65:0] mp_y_fifo_sram_rdata ; + output [ c_mi_mp_y_aw-1:0] mp_y_fifo_sram_addr ; + output mp_y_fifo_sram_cs_n ; + output mp_y_fifo_sram_we_n ; + output [65:0] mp_cb_fifo_sram_wdata ; + input [65:0] mp_cb_fifo_sram_rdata ; + output [ c_mi_mp_c_aw-1:0] mp_cb_fifo_sram_addr ; + output mp_cb_fifo_sram_cs_n ; + output mp_cb_fifo_sram_we_n ; + output [65:0] mp_cr_fifo_sram_wdata ; + input [65:0] mp_cr_fifo_sram_rdata ; + output [ c_mi_mp_c_aw-1:0] mp_cr_fifo_sram_addr ; + output mp_cr_fifo_sram_cs_n ; + output mp_cr_fifo_sram_we_n ; + wire regs_sample_edge; + wire [11:0] sensor_fifo_data; + wire sensor_fifo_hsync; + wire sensor_fifo_vsync; + wire sensor_fifo_val; + wire sensor_fifo_ack; + wire sclk_mux_en; + wire sclk_n; + wire sclk_gated; + wire sclk_gated_tmp; + wire [11:0] if_sel_data; + wire if_sel_hsync; + wire if_sel_vsync; + wire if_sel_val; + wire if_sel_ack; + wire if_sel_valack; + wire pipeline_full; + wire [31:0] paddr; + wire [31:0] pwdata; + wire [31:0] prdata; + wire pval; + wire pack; + wire prd; + wire [16-1:0] isp_raw_out_data; + wire isp_raw_out_h_end; + wire isp_raw_out_v_end; + wire isp_raw_out_val; + wire isp_raw_out_cfg_upd; + wire isp_raw_out_ack ; + wire raw_mode; + wire format_conv_ctrl; + wire [19:0] isp_data; + wire isp_val; + wire isp_ack; + wire isp_h_end; + wire isp_v_end; + wire isp_cfg_upd; + wire [9:0] ycsp_y_data; + wire [9:0] ycsp_y_s_data; + wire ycsp_y_val; + wire ycsp_y_ack; + wire ycsp_y_h_end; + wire ycsp_y_v_end; + wire ycsp_y_cfg_upd; + wire [9:0] ycsp_c_data; + wire [9:0] ycsp_c_s_data; + wire ycsp_c_val; + wire ycsp_c_ack; + wire ycsp_c_h_end; + wire ycsp_c_v_end; + wire ycsp_c_cfg_upd; + wire [7:0] format_conv_y_data; + wire format_conv_y_val; + wire format_conv_y_ack; + wire format_conv_y_in_ack; + wire format_conv_y_h_end; + wire format_conv_y_v_end; + wire format_conv_y_cfg_upd; + wire [7:0] format_conv_c_data; + wire format_conv_c_val; + wire format_conv_c_ack; + wire format_conv_c_in_ack; + wire format_conv_c_h_end; + wire format_conv_c_v_end; + wire format_conv_c_cfg_upd; + wire [7:0] fifo_rszm_y_data; + wire fifo_rszm_y_val; + wire fifo_rszm_y_ack; + wire fifo_rszm_y_h_end; + wire fifo_rszm_y_v_end; + wire fifo_rszm_y_cfg_upd; + wire [7:0] ycsp_spmux_y_data; + wire ycsp_spmux_y_val; + wire ycsp_spmux_y_ack; + wire ycsp_spmux_y_h_end; + wire ycsp_spmux_y_v_end; + wire [7:0] fifo_rszm_c_data; + wire fifo_rszm_c_val; + wire fifo_rszm_c_ack; + wire fifo_rszm_c_h_end; + wire fifo_rszm_c_v_end; + wire fifo_rszm_c_cfg_upd; + wire [7:0] ycsp_spmux_c_data; + wire ycsp_spmux_c_val; + wire ycsp_spmux_c_ack; + wire ycsp_spmux_c_h_end; + wire ycsp_spmux_c_v_end; + wire ycsp_rszall_cfg_upd; + wire [7:0] rszm_y_data; + wire rszm_y_val; + wire rszm_y_ack; + wire rszm_y_h_end; + wire rszm_y_v_end; + wire rszm_y_cfg_upd; + wire [7:0] rszm_c_data; + wire rszm_c_val; + wire rszm_c_ack; + wire rszm_c_h_end; + wire rszm_c_v_end; + wire rszm_c_cfg_upd; + wire [7:0] out_y_data; + wire out_y_val; + wire out_y_h_end; + wire out_y_v_end; + wire [7:0] out_c_data; + wire out_c_val; + wire out_c_h_end; + wire out_c_v_end; + wire out_cfg_upd; + wire jpeg_mi_val; + wire [63:0] jpeg_mi_data; + wire jpeg_mi_ack; + wire [2:0] jpeg_mi_byte_no; + wire jpeg_mi_end; + wire [31:0] isp_dp_data; + wire isp_dp_end; + wire isp_dp_val; + wire isp_dp_ack; + wire [7:0] mi_dmamux_y_data; + wire mi_dmamux_y_val; + wire mi_dmamux_y_h_end; + wire mi_dmamux_y_v_end; + wire mi_dmamux_y_cfg_upd; + wire mi_dmamux_y_ack; + wire [7:0] mi_dmamux_c_data; + wire mi_dmamux_c_val; + wire mi_dmamux_c_h_end; + wire mi_dmamux_c_v_end; + wire mi_dmamux_c_cfg_upd; + wire mi_dmamux_c_ack; + wire [7:0] dmamux_spmux_y_data; + wire dmamux_spmux_y_val; + wire dmamux_spmux_y_h_end; + wire dmamux_spmux_y_v_end; + wire dmamux_spmux_y_ack; + wire dmamux_spmux_y_cfg_upd; + wire [7:0] dmamux_spmux_c_data; + wire dmamux_spmux_c_val; + wire dmamux_spmux_c_h_end; + wire dmamux_spmux_c_v_end; + wire dmamux_spmux_c_ack; + wire dmamux_spmux_c_cfg_upd; + wire [7:0] dmamux_simp_y_data; + wire dmamux_simp_y_val; + wire dmamux_simp_y_h_end; + wire dmamux_simp_y_v_end; + wire dmamux_simp_y_ack; + wire [7:0] dmamux_simp_c_data; + wire dmamux_simp_c_val; + wire dmamux_simp_c_h_end; + wire dmamux_simp_c_v_end; + wire dmamux_simp_c_ack; + wire [7:0] dmamux_iemux_y_data; + wire dmamux_iemux_y_val; + wire dmamux_iemux_y_h_end; + wire dmamux_iemux_y_v_end; + wire dmamux_iemux_y_ack; + wire [7:0] dmamux_iemux_c_data; + wire dmamux_iemux_c_val; + wire dmamux_iemux_c_h_end; + wire dmamux_iemux_c_v_end; + wire dmamux_iemux_c_ack; + wire [15:0] dmamux_isp_data; + wire dmamux_isp_val; + wire dmamux_isp_h_end; + wire dmamux_isp_v_end; + wire dmamux_isp_ack; + wire [7:0] dmamux_dpmux_y_data; + wire dmamux_dpmux_y_val; + wire dmamux_dpmux_y_h_end; + wire dmamux_dpmux_y_v_end; + wire dmamux_dpmux_y_ack; + wire dmamux_dpmux_y_cfg_upd; + wire [7:0] dmamux_dpmux_c_data; + wire dmamux_dpmux_c_val; + wire dmamux_dpmux_c_h_end; + wire dmamux_dpmux_c_v_end; + wire dmamux_dpmux_c_ack; + wire dmamux_dpmux_c_cfg_upd; + wire spmux_fifo_y_val; + wire [7:0] spmux_fifo_y_data; + wire spmux_fifo_y_h_end; + wire spmux_fifo_y_v_end; + wire spmux_fifo_y_ack; + wire spmux_fifo_y_cfg_upd; + wire spmux_fifo_c_val; + wire [7:0] spmux_fifo_c_data; + wire spmux_fifo_c_h_end; + wire spmux_fifo_c_v_end; + wire spmux_fifo_c_ack; + wire spmux_fifo_c_cfg_upd; + wire [7:0] fifo_rszs_y_data; + wire fifo_rszs_y_val; + wire fifo_rszs_y_h_end; + wire fifo_rszs_y_v_end; + wire fifo_rszs_y_ack; + wire fifo_rszs_y_cfg_upd; + wire [7:0] fifo_rszs_c_data; + wire fifo_rszs_c_val; + wire fifo_rszs_c_h_end; + wire fifo_rszs_c_v_end; + wire fifo_rszs_c_ack; + wire fifo_rszs_c_cfg_upd; + wire rszs_fifo_y_val; + wire [7:0] rszs_fifo_y_data; + wire rszs_fifo_y_h_end; + wire rszs_fifo_y_v_end; + wire rszs_fifo_y_ack; + wire rszs_fifo_y_cfg_upd; + wire rszs_fifo_c_val; + wire [7:0] rszs_fifo_c_data; + wire rszs_fifo_c_h_end; + wire rszs_fifo_c_v_end; + wire rszs_fifo_c_ack; + wire rszs_fifo_c_cfg_upd; + wire fifo_mi_y_val; + wire [7:0] fifo_mi_y_data; + wire fifo_mi_y_h_end; + wire fifo_mi_y_v_end; + wire fifo_mi_y_ack; + wire fifo_mi_y_cfg_upd; + wire fifo_mi_c_val; + wire [7:0] fifo_mi_c_data; + wire fifo_mi_c_h_end; + wire fifo_mi_c_v_end; + wire fifo_mi_c_ack; + wire fifo_mi_c_cfg_upd; + wire ahbs_ctrl_pval_all; + wire ahbs_ctrl_pack_all; + wire [c_prdata_word-1:0] ahbs_ctrl_prdata_all; + wire ctrl_pval_all; + wire ctrl_pack_all; + wire [c_prdata_word-1:0] ctrl_prdata_all; + wire ahbs_ctrl_pval_mi; + wire ahbs_ctrl_pack_mi; + wire [c_prdata_word-1:0] ahbs_ctrl_prdata_mi; + wire ctrl_pval_mi; + wire ctrl_pack_mi; + wire [c_prdata_word-1:0] ctrl_prdata_mi; + wire soft_rst_marvin; + wire ctrl_reset_clk_n; + wire ctrl_reset_s_hclk_n; + wire ctrl_reset_sclk_n; + wire ctrl_reset_m_hclk_n; + wire [c_cfg_addr_word-1:0] ctrl_mi_addr; + wire ctrl_mi_rd; + wire [c_cfg_wdata_word-1:0] ctrl_mi_wdata; + wire [c_cfg_addr_word-1:0] ctrl_all_addr; + wire ctrl_all_rd; + wire [c_cfg_wdata_word-1:0] ctrl_all_wdata; + wire [c_cfg_rdata32_word-1:0] ctrl_isp_rdata; + wire ctrl_isp_val; + wire ctrl_isp_ack; + wire [c_cfg_rdata32_word-1:0] ctrl_rszm_rdata; + wire ctrl_rszm_val; + wire ctrl_rszm_ack; + wire [c_cfg_rdata32_word-1:0] ctrl_rszs_rdata; + wire ctrl_rszs_val; + wire ctrl_rszs_ack; + wire [c_cfg_rdata32_word-1:0] ctrl_mi_rdata; + wire ctrl_mi_val; + wire ctrl_mi_ack; + wire ctrl_isp_clk; + wire clk_isp_rgb_ram; + wire ctrl_rszm_clk; + wire ctrl_rszs_clk; + wire ctrl_mi_clk; + wire ctrl_isp_clk_cfg; + wire ctrl_rszm_clk_cfg; + wire ctrl_rszs_clk_cfg; + wire ctrl_mi_m_hclk_cfg; + wire ctrl_isp_soft_rst; + wire ctrl_yc_soft_rst; + wire ctrl_rszm_soft_rst; + wire ctrl_rszs_soft_rst; + wire ctrl_mi_soft_rst; + wire mi_clk_en_mhclk; + wire soft_rst_mi_mhclk; + wire isp_clk_en; + wire mi_mp_frame_end_int; + wire mi_sp_frame_end_int; + wire mi_mblk_line_int; + wire mi_fill_mp_y_int; + wire mi_wrap_mp_y_int; + wire mi_wrap_mp_cb_int; + wire mi_wrap_mp_cr_int; + wire mi_wrap_sp_y_int; + wire mi_wrap_sp_cb_int; + wire mi_wrap_sp_cr_int; + wire mi_dma_ready_int; + wire mi_mp_handshk_int; + wire mi_mp_handshk_sw_int; + wire isp_hist_end_int; + wire isp_exp_end_int; + wire isp_fl_cap_int; + wire isp_afm_fin_int; + wire isp_afm_lum_of_int; + wire isp_afm_sum_of_int; + wire isp_sh_off_int; + wire isp_sh_on_int; + wire isp_fl_off_int; + wire isp_fl_on_int; + wire isp_h_start_int; + wire isp_v_start_int; + wire isp_size_err_int; + wire isp_frame_int; + wire isp_frame_in_int; + wire isp_dataloss_int; + wire isp_off_int; + wire isp_awb_done_int; + wire isp_vsm_done_int; + wire rot_en; + wire rotram_cs_n; + wire rotram_we_n; + wire [3:0] rotram_wr_n; + wire [13:0] rotram_addr; + wire [31:0] rotram_rdata; + wire [31:0] rotram_wdata; + wire bvci_out_m1_cmdval; + wire [8:0] bvci_out_m1_plen; + wire bvci_out_m1_eop; + wire [31:3] bvci_out_m1_address; + wire [63:0] bvci_out_m1_wdata; + wire [7:0] bvci_out_m1_be; + wire [1:0] bvci_out_m1_cmd; + wire bvci_out_m1_const; + wire bvci_out_m1_contig; + wire bvci_out_m1_wrap; + wire bvci_out_m1_cmdack; + wire bvci_out_m1_rspval; + wire bvci_out_m1_reop; + wire bvci_out_m1_rspack; + wire bvci_out_m2_cmdval; + wire [8:0] bvci_out_m2_plen; + wire bvci_out_m2_eop; + wire [31:3] bvci_out_m2_address; + wire [63:0] bvci_out_m2_wdata; + wire [7:0] bvci_out_m2_be; + wire [1:0] bvci_out_m2_cmd; + wire bvci_out_m2_const; + wire bvci_out_m2_contig; + wire bvci_out_m2_wrap; + wire bvci_out_m2_cmdack; + wire bvci_out_m2_rspval; + wire bvci_out_m2_reop; + wire bvci_out_m2_rspack; + wire bvci_in_cmdval; + wire [31:3] bvci_in_address; + wire [7:0] bvci_in_be; + wire [1:0] bvci_in_cmd; + wire bvci_in_eop; + wire [8:0] bvci_in_plen; + wire bvci_in_contig; + wire bvci_in_const; + wire bvci_in_wrap; + wire bvci_in_rspack; + wire [63:0] bvci_in_rdata; + wire bvci_in_cmdack; + wire bvci_in_rspval; + wire bvci_in_reop; + wire [11:0] rszm_mramy_addr_tmp; + wire [11:0] rszm_mramc_addr_tmp; + wire [11:0] rszs_sramy_addr_tmp; + wire [11:0] rszs_sramc_addr_tmp; + wire mp_lsb_flag; + wire [3:0] mp_output_format; + wire mp_little_endian; + wire [31:0] paddr_tmp; + wire [31:0] pwdata_tmp; + wire [31:0] prdata_tmp; + wire pval_tmp; + wire pack_tmp; + wire prd_tmp; + wire scan_mode_src; +`ifdef FPGA + assign scan_mode_src = 0; +`else + assign scan_mode_src = scan_mode; +`endif + assign isp_fifo_ram_clk = ctrl_isp_clk; + assign isp_rgb_ram_clk = clk_isp_rgb_ram; + assign rszm_mram_clk = ctrl_rszm_clk; + assign rszs_sram_clk = ctrl_rszs_clk; + vsisp_ahb2pvci u_ahb2pvci_marvin ( + .hclk (s_hclk), + .hreset_n (ctrl_reset_s_hclk_n), + .pval (pval), + .paddress (paddr), + .pwdata (pwdata), + .prd (prd), + .pack (pack), + .prdata (prdata), + .hsel (hsel_s), + .hrdata (hrdata_s), + .haddr (haddr_s), + .hwdata (hwdata_s), + .hwrite (hwrite_s), + .hready_in (hready_s), + .htrans (htrans_s), + .hresp (hresp_s), + .hready (hready_s) + ); + vsisp_sensor_fifo u_sensor_fifo + ( + .sclk (sclk_gated), + .reset_sclk_n (ctrl_reset_sclk_n), + .mclk (ctrl_isp_clk), + .reset_mclk_n (ctrl_reset_clk_n), + .s_data (s_data), + .s_hsync (s_hsync), + .s_vsync (s_vsync), + .s_valid (s_valid), + .s_fifo_data (sensor_fifo_data), + .s_fifo_hsync (sensor_fifo_hsync), + .s_fifo_vsync (sensor_fifo_vsync), + .s_fifo_val (sensor_fifo_val), + .s_fifo_ack (sensor_fifo_ack), + .s_fifo_full () + ); + assign if_sel_val = sensor_fifo_val; + assign if_sel_data = sensor_fifo_data; + assign if_sel_hsync = sensor_fifo_hsync; + assign if_sel_vsync = sensor_fifo_vsync; + assign sensor_fifo_ack = if_sel_ack; + assign pipeline_full = if_sel_val && ~if_sel_ack; + assign if_sel_valack = if_sel_val && if_sel_ack; + vsisp_isp #(.c_ispfifo_aw (c_ispfifo_aw)) u_isp + ( + .clk_not_gated (clk), + .clk (ctrl_isp_clk), + .reset_clk_n (ctrl_reset_clk_n), + .clk_isp_rgb_ram (clk_isp_rgb_ram), + .clk_cfg (ctrl_isp_clk_cfg), + .reset_cfg_n (ctrl_reset_clk_n), + .soft_rst (ctrl_isp_soft_rst), + .s_data (if_sel_data), + .s_hsync (if_sel_hsync), + .s_vsync (if_sel_vsync), + .s_data_val (if_sel_valack), + .s_data_ack (if_sel_ack), + .regs_sample_edge (regs_sample_edge), + .pipeline_full (pipeline_full), + .disable_isp (disable_isp), + .regs_disable_isp_clk (regs_disable_isp_clk), + .isp_data (isp_data), + .isp_val (isp_val), + .isp_ack (isp_ack), + .isp_h_end (isp_h_end), + .isp_v_end (isp_v_end), + .isp_cfg_upd (isp_cfg_upd), + .raw_out_data (isp_raw_out_data ), + .raw_out_h_end (isp_raw_out_h_end ), + .raw_out_v_end (isp_raw_out_v_end ), + .raw_out_val (isp_raw_out_val ), + .raw_out_cfg_upd (isp_raw_out_cfg_upd ), + .raw_out_ack (isp_raw_out_ack ), + .raw_mode (raw_mode ), + .format_conv_ctrl (format_conv_ctrl), + .cfg_addr (ctrl_all_addr), + .cfg_wdata (ctrl_all_wdata), + .cfg_rdata (ctrl_isp_rdata), + .cfg_rd (ctrl_all_rd), + .cfg_val (ctrl_isp_val), + .cfg_ack (ctrl_isp_ack), + .isp_fifo_cs_n (isp_fifo_cs_n), + .isp_fifo_we_n (isp_fifo_wr_n), + .isp_fifo_addr (isp_fifo_addr), + .isp_fifo_wdata (isp_fifo_wdata), + .isp_fifo_rdata (isp_fifo_rdata), + .ispram_addr (isp_ispram_addr), + .ispram_wdata (isp_ispram_wdata), + .ispram_rdata (isp_ispram_rdata), + .ispram_we_n (isp_ispram_wr_n), + .ispram_cs_n (isp_ispram_cs_n), + .isp_int_exp_end (isp_exp_end_int), + .isp_int_awb_done (isp_awb_done_int), + .isp_int_h_start (isp_h_start_int), + .isp_int_v_start (isp_v_start_int), + .isp_int_size_err (isp_size_err_int), + .isp_int_frame_in (isp_frame_in_int), + .isp_int_dataloss (isp_dataloss_int), + .test_mode (scan_mode_src), + .isp_clk_en (isp_clk_en) + ); +vsisp_yc_split #(.data_width(c_dw_do)) u_yc_split +( + .clk ( ctrl_rszm_clk ), + .reset_n ( ctrl_reset_clk_n ), + .soft_rst ( ctrl_rszm_soft_rst ), + .cfg_chan_mode ( 2'h3 ), + .in_data ( isp_data ), + .in_h_end ( isp_h_end ), + .in_v_end ( isp_v_end ), + .in_cfg_upd ( isp_cfg_upd ), + .in_val ( isp_val ), + .in_ack ( isp_ack ), + .out_y_m_data ( ycsp_y_data ), + .out_y_m_val ( ycsp_y_val ), + .out_y_m_ack ( ycsp_y_ack ), + .out_y_m_h_end ( ycsp_y_h_end ), + .out_y_m_v_end ( ycsp_y_v_end ), + .out_c_m_data ( ycsp_c_data ), + .out_c_m_val ( ycsp_c_val ), + .out_c_m_ack ( ycsp_c_ack ), + .out_c_m_h_end ( ycsp_c_h_end ), + .out_c_m_v_end ( ycsp_c_v_end ), + .out_y_s_data ( ycsp_y_s_data ), + .out_y_s_val ( spmux_fifo_y_val ), + .out_y_s_ack ( spmux_fifo_y_ack ), + .out_y_s_h_end ( spmux_fifo_y_h_end ), + .out_y_s_v_end ( spmux_fifo_y_v_end ), + .out_c_s_data ( ycsp_c_s_data ), + .out_c_s_val ( spmux_fifo_c_val ), + .out_c_s_ack ( spmux_fifo_c_ack ), + .out_c_s_h_end ( spmux_fifo_c_h_end ), + .out_c_s_v_end ( spmux_fifo_c_v_end ), + .out_cfg_upd ( out_cfg_upd ), + .out_ext_y_data ( ), + .out_ext_y_val ( ), + .out_ext_y_ack ( 1'b1 ), + .out_ext_y_h_end ( ), + .out_ext_y_v_end ( ), + .out_ext_c_data ( ), + .out_ext_c_val ( ), + .out_ext_c_ack ( 1'b1 ), + .out_ext_c_h_end ( ), + .out_ext_c_v_end ( ) +) ; +assign ycsp_y_cfg_upd = out_cfg_upd; +assign ycsp_c_cfg_upd = out_cfg_upd; +assign spmux_fifo_y_cfg_upd = out_cfg_upd; +assign spmux_fifo_c_cfg_upd = out_cfg_upd; +assign ycsp_y_ack = 1'b1; +assign ycsp_c_ack = 1'b1; +assign spmux_fifo_y_data = ycsp_y_s_data[9:2]; +assign spmux_fifo_c_data = ycsp_c_s_data[9:2]; +assign ctrl_rszm_rdata = 'b0; +assign ctrl_rszm_ack = 'b0; +assign rszm_mramc_wr_n = 'b0; +assign rszm_mramc_cs_n = 'b0; +assign rszm_mramc_addr = 'b0; +assign rszm_mramc_wdata = 'b0; +assign rszm_mramy_wr_n = 'b0; +assign rszm_mramy_cs_n = 'b0; +assign rszm_mramy_addr = 'b0; +assign rszm_mramy_wdata = 'b0; + wire [15:0] isp_raw_out_data_new; + reg mp_lsb_flag_dly1, mp_lsb_flag_dly2; + reg [3:0] mp_output_format_dly1, mp_output_format_dly2; + reg mp_little_endian_dly1,mp_little_endian_dly2; + always @(posedge clk or negedge reset_n) begin + if(!reset_n) begin + mp_lsb_flag_dly1 <= 1'b0; + mp_lsb_flag_dly2 <= 1'b0; + mp_output_format_dly1 <= 4'd0; + mp_output_format_dly2 <= 4'd0; + mp_little_endian_dly1 <= 1'b0; + mp_little_endian_dly2 <= 1'b0; + end + else begin + mp_lsb_flag_dly1 <= mp_lsb_flag; + mp_lsb_flag_dly2 <= mp_lsb_flag_dly1; + mp_output_format_dly1 <= mp_output_format; + mp_output_format_dly2 <= mp_output_format_dly1; + mp_little_endian_dly1 <= mp_little_endian; + mp_little_endian_dly2 <= mp_little_endian_dly1; + end + end + assign isp_raw_out_data_new = mp_lsb_flag_dly2 ? ((mp_output_format_dly2 == 4'b0100) ? (isp_raw_out_data >> 4) : + (mp_output_format_dly2 == 4'b0111) ? (isp_raw_out_data >> 6) : + isp_raw_out_data ) : + isp_raw_out_data; + wire [7:0] raw_y_data; + wire [7:0] raw_c_data; + wire raw_y_ack; + wire raw_c_ack; + assign raw_y_data = ((mp_output_format_dly2 == 4'b0101) ? isp_raw_out_data_new [15:8] : (mp_little_endian_dly2 ? isp_raw_out_data_new [7:0] : isp_raw_out_data_new [15:8])); + assign raw_y_val = isp_raw_out_val && isp_raw_out_ack ; + assign raw_y_h_end = isp_raw_out_h_end; + assign raw_y_v_end = isp_raw_out_v_end; + assign raw_y_cfg_upd = isp_raw_out_cfg_upd ; + assign raw_c_data = ((mp_output_format_dly2 == 4'b0101) ? 8'h0 : (mp_little_endian_dly2 ? isp_raw_out_data_new [15:8] : isp_raw_out_data_new [7:0])); + assign raw_c_val = ((mp_output_format_dly2 == 4'b0101) ? 1'b0 : isp_raw_out_val && isp_raw_out_ack); + assign raw_c_h_end = isp_raw_out_h_end ; + assign raw_c_v_end = isp_raw_out_v_end ; + assign raw_c_cfg_upd = isp_raw_out_cfg_upd ; + assign isp_raw_out_ack = (mp_output_format_dly2 == 4'b0101) ? raw_y_ack : raw_y_ack && raw_c_ack; + wire [7:0] raw_y_data_2to3; + wire [7:0] raw_cb_data_2to3; + wire [7:0] raw_cr_data_2to3; + wire raw_y_ack_2to3; + wire raw_cb_ack_2to3; + wire raw_cr_ack_2to3; + vsisp_marvin_mi_2to3 u_mi_2to3 + ( + .clk (ctrl_mi_clk), + .reset_n (ctrl_reset_clk_n), + .soft_rst (ctrl_mi_soft_rst), + .in_y_val (raw_y_val), + .in_y_data (raw_y_data), + .in_y_h_end (raw_y_h_end), + .in_y_v_end (raw_y_v_end), + .in_y_cfg_upd (raw_y_cfg_upd), + .in_y_ack (raw_y_ack), + .in_c_val (raw_c_val), + .in_c_data (raw_c_data), + .in_c_h_end (raw_c_h_end), + .in_c_v_end (raw_c_v_end), + .in_c_cfg_upd (raw_c_cfg_upd), + .in_c_ack (raw_c_ack), + .out_y_val (raw_y_val_2to3), + .out_y_data (raw_y_data_2to3), + .out_y_h_end (raw_y_h_end_2to3), + .out_y_v_end (raw_y_v_end_2to3), + .out_y_cfg_update (raw_y_cfg_upd_2to3), + .out_y_ack (raw_y_ack_2to3), + .out_cb_val (raw_cb_val_2to3), + .out_cb_data (raw_cb_data_2to3), + .out_cb_h_end (raw_cb_h_end_2to3), + .out_cb_v_end (raw_cb_v_end_2to3), + .out_cb_cfg_update (raw_cb_cfg_upd_2to3), + .out_cb_ack (raw_cb_ack_2to3), + .out_cr_val (raw_cr_val_2to3), + .out_cr_data (raw_cr_data_2to3), + .out_cr_h_end (raw_cr_h_end_2to3), + .out_cr_v_end (raw_cr_v_end_2to3), + .out_cr_cfg_update (raw_cr_cfg_upd_2to3), + .out_cr_ack (raw_cr_ack_2to3) + ); + wire [7:0] fifo_dpmux_y_data; + wire [7:0] fifo_dpmux_cb_data; + wire [7:0] fifo_dpmux_cr_data; + wire fifo_dpmux_y_ack; + wire fifo_dpmux_cb_ack; + wire fifo_dpmux_cr_ack; + assign fifo_dpmux_y_val = raw_mode ? raw_y_val_2to3 : 'b0 ; + assign fifo_dpmux_y_data = raw_mode ? raw_y_data_2to3 : 'b0 ; + assign fifo_dpmux_y_h_end = raw_mode ? raw_y_h_end_2to3 : 'b0 ; + assign fifo_dpmux_y_v_end = raw_mode ? raw_y_v_end_2to3 : 'b0 ; + assign fifo_dpmux_y_cfg_upd = raw_mode ? raw_y_cfg_upd_2to3 : 'b0 ; + assign fifo_dpmux_cb_val = raw_mode ? raw_cb_val_2to3 : 'b0 ; + assign fifo_dpmux_cb_data = raw_mode ? raw_cb_data_2to3 : 'b0 ; + assign fifo_dpmux_cb_h_end = raw_mode ? raw_cb_h_end_2to3 : 'b0 ; + assign fifo_dpmux_cb_v_end = raw_mode ? raw_cb_v_end_2to3 : 'b0 ; + assign fifo_dpmux_cb_cfg_upd = raw_mode ? raw_cb_cfg_upd_2to3 : 'b0 ; + assign fifo_dpmux_cr_val = raw_mode ? raw_cr_val_2to3 : 'b0 ; + assign fifo_dpmux_cr_data = raw_mode ? raw_cr_data_2to3 : 'b0 ; + assign fifo_dpmux_cr_h_end = raw_mode ? raw_cr_h_end_2to3 : 'b0 ; + assign fifo_dpmux_cr_v_end = raw_mode ? raw_cr_v_end_2to3 : 'b0 ; + assign fifo_dpmux_cr_cfg_upd = raw_mode ? raw_cr_cfg_upd_2to3 : 'b0 ; + assign raw_y_ack_2to3 = raw_mode ? fifo_dpmux_y_ack : 1'b1; + assign raw_cb_ack_2to3 = raw_mode ? fifo_dpmux_cb_ack : 1'b1; + assign raw_cr_ack_2to3 = raw_mode ? fifo_dpmux_cr_ack : 1'b1; + assign rszm2mi_y_ack = raw_mode ? 1'b1 : fifo_dpmux_y_ack; + assign rszm2mi_cb_ack = raw_mode ? 1'b1 : fifo_dpmux_cb_ack; + assign rszm2mi_cr_ack = raw_mode ? 1'b1 : fifo_dpmux_cr_ack; +wire mi_handshk_bresp_in; +assign mi_handshk_bresp_in = axi_m1_marvin_bvalid && (axi_m1_marvin_bresp==2'b00); + assign jpeg_mi_val = 1'b0; + assign jpeg_mi_data = 64'b0; + assign jpeg_mi_byte_no = 3'b0; + assign jpeg_mi_end = 1'b0; + assign isp_dp_data = 32'd0; + assign isp_dp_end = 1'b0; + assign isp_dp_val = 1'b0; + assign isp_dp_ack = 1'b0; +wire [7:0] rszs2mi_y_data; +wire rszs2mi_y_val; +wire rszs2mi_y_v_end; +wire rszs2mi_y_h_end; +wire rszs2mi_y_cfg_upd; +wire rszs2mi_y_ack; +wire [7:0] rszs2mi_cb_data; +wire rszs2mi_cb_val; +wire rszs2mi_cb_v_end; +wire rszs2mi_cb_h_end; +wire rszs2mi_cb_cfg_upd; +wire rszs2mi_cb_ack; +wire [7:0] rszs2mi_cr_data; +wire rszs2mi_cr_val; +wire rszs2mi_cr_v_end; +wire rszs2mi_cr_h_end; +wire rszs2mi_cr_cfg_upd; +wire rszs2mi_cr_ack; + vsisp_fifo4fe #(11) u3_fifo4fe( + .clk ( ctrl_rszs_clk ), + .reset_n ( ctrl_reset_clk_n ), + .soft_rst ( ctrl_rszs_soft_rst ), + .fifo_data_i ({spmux_fifo_y_h_end, + spmux_fifo_y_v_end, + spmux_fifo_y_cfg_upd, + spmux_fifo_y_data}), + .fifo_val_i (spmux_fifo_y_val), + .fifo_ack_o (spmux_fifo_y_ack), + .fifo_data_o ({fifo_rszs_y_h_end, + fifo_rszs_y_v_end, + fifo_rszs_y_cfg_upd, + fifo_rszs_y_data}), + .fifo_val_o (fifo_rszs_y_val), + .fifo_ack_i (fifo_rszs_y_ack) + ); + vsisp_fifo4fe #(11) u4_fifo4fe( + .clk ( ctrl_rszs_clk ), + .reset_n ( ctrl_reset_clk_n ), + .soft_rst ( ctrl_rszs_soft_rst ), + .fifo_data_i ({spmux_fifo_c_h_end, + spmux_fifo_c_v_end, + spmux_fifo_c_cfg_upd, + spmux_fifo_c_data}), + .fifo_val_i (spmux_fifo_c_val), + .fifo_ack_o (spmux_fifo_c_ack), + .fifo_data_o ({fifo_rszs_c_h_end, + fifo_rszs_c_v_end, + fifo_rszs_c_cfg_upd, + fifo_rszs_c_data}), + .fifo_val_o (fifo_rszs_c_val), + .fifo_ack_i (fifo_rszs_c_ack) + ); + vsisp_resize_conv u_self_resize + ( + .clk (ctrl_rszs_clk), + .reset_n (ctrl_reset_clk_n), + .clk_cfg (ctrl_rszs_clk_cfg), + .reset_cfg_n (ctrl_reset_clk_n), + .soft_rst (ctrl_rszs_soft_rst), + .cfg_val (ctrl_rszs_val), + .cfg_addr (ctrl_all_addr[6:2]), + .cfg_rd (ctrl_all_rd), + .cfg_wdata (ctrl_all_wdata[31:0]), + .cfg_rdata (ctrl_rszs_rdata[31:0]), + .cfg_ack (ctrl_rszs_ack), + .in_y_pix_data (fifo_rszs_y_data), + .in_y_val (fifo_rszs_y_val), + .in_y_h_end (fifo_rszs_y_h_end), + .in_y_v_end (fifo_rszs_y_v_end), + .in_y_cfg_upd (fifo_rszs_y_cfg_upd), + .in_y_ack (fifo_rszs_y_ack), + .in_c_pix_data (fifo_rszs_c_data), + .in_c_val (fifo_rszs_c_val), + .in_c_h_end (fifo_rszs_c_h_end), + .in_c_v_end (fifo_rszs_c_v_end), + .in_c_cfg_upd (fifo_rszs_c_cfg_upd), + .in_c_ack (fifo_rszs_c_ack), + .out_y_r_data (rszs2mi_y_data), + .out_y_r_val (rszs2mi_y_val), + .out_y_r_h_end (rszs2mi_y_h_end), + .out_y_r_v_end (rszs2mi_y_v_end), + .out_y_r_cfg_upd (rszs2mi_y_cfg_upd), + .out_y_r_ack (rszs2mi_y_ack), + .out_cb_g_data (rszs2mi_cb_data), + .out_cb_g_val (rszs2mi_cb_val), + .out_cb_g_h_end (rszs2mi_cb_h_end), + .out_cb_g_v_end (rszs2mi_cb_v_end), + .out_cb_g_cfg_upd (rszs2mi_cb_cfg_upd), + .out_cb_g_ack (rszs2mi_cb_ack), + .out_cr_b_data (rszs2mi_cr_data), + .out_cr_b_val (rszs2mi_cr_val), + .out_cr_b_h_end (rszs2mi_cr_h_end), + .out_cr_b_v_end (rszs2mi_cr_v_end), + .out_cr_b_cfg_upd (rszs2mi_cr_cfg_upd), + .out_cr_b_ack (rszs2mi_cr_ack), + .ram_y_wr_n (rszs_sramy_wr_n), + .ram_y_cs_n (rszs_sramy_cs_n), + .ram_y_addr (rszs_sramy_addr_tmp), + .ram_y_wdata (rszs_sramy_wdata), + .ram_y_rdata (rszs_sramy_rdata), + .ram_c_wr_n (rszs_sramc_wr_n), + .ram_c_cs_n (rszs_sramc_cs_n), + .ram_c_addr (rszs_sramc_addr_tmp), + .ram_c_wdata (rszs_sramc_wdata), + .ram_c_rdata (rszs_sramc_rdata), + .out_y_r_val_stream (out_y_r_val_stream), + .out_y_r_data_stream (out_y_r_data_stream), + .out_cb_g_val_stream (out_cb_g_val_stream), + .out_cb_g_data_stream (out_cb_g_data_stream), + .out_cr_b_val_stream (out_cr_b_val_stream), + .out_cr_b_data_stream (out_cr_b_data_stream), + .out_y_r_ack_stream(out_y_r_ack_stream), + .out_cb_g_ack_stream(out_cb_g_ack_stream), + .out_cr_b_ack_stream(out_cr_b_ack_stream), + .out_y_r_frame_start (out_y_r_frame_start), + .out_y_r_frame_end (out_y_r_frame_end), + .out_y_r_line_start (out_y_r_line_start), + .out_y_r_line_end (out_y_r_line_end), + .out_cb_g_frame_start (out_cb_g_frame_start), + .out_cb_g_frame_end (out_cb_g_frame_end), + .out_cb_g_line_start (out_cb_g_line_start), + .out_cb_g_line_end (out_cb_g_line_end), + .out_cr_b_frame_start (out_cr_b_frame_start), + .out_cr_b_frame_end (out_cr_b_frame_end), + .out_cr_b_line_start (out_cr_b_line_start), + .out_cr_b_line_end (out_cr_b_line_end) + ); + assign rszs_sramy_addr = rszs_sramy_addr_tmp[c_aw_mrsz-1:0]; + assign rszs_sramc_addr = rszs_sramc_addr_tmp[c_aw_mrsz-1:0]; + vsisp_marvin_mi #( + .c_rot_line_length (c_rot_line_length), + .c_rot_ram_aw (c_rot_ram_aw) + ) + u_marvin_mi + ( + .isp_0_ack(1'b1), + .bresp_in(mi_handshk_bresp_in), + .isp_0_ready(), + .isp_0_attr(), + .clk (ctrl_mi_clk ), + .reset_n (ctrl_reset_clk_n ), + .soft_rst (ctrl_mi_soft_rst ), + .m_hclk (m_hclk ), + .reset_m_hclk_n (ctrl_reset_m_hclk_n ), + .m_hclk_cfg (ctrl_mi_m_hclk_cfg ), + .reset_m_hclk_cfg_n (ctrl_reset_m_hclk_n ), + .soft_rst_m_hclk (soft_rst_mi_mhclk ), + .jpeg_clk (ctrl_mi_clk ), + .reset_jpeg_clk_n (ctrl_reset_clk_n ), + .test_mode (scan_mode_src ), + .mp_lsb_alignment_out(mp_lsb_flag ), + .mp_output_format_out(mp_output_format ), + .mp_little_endian_out(mp_little_endian ), + .cfg_mi_val (ctrl_mi_val), + .cfg_mi_addr (ctrl_mi_addr[8:2]), + .cfg_mi_rd (ctrl_mi_rd), + .cfg_mi_wdata (ctrl_mi_wdata), + .cfg_mi_rdata (ctrl_mi_rdata), + .cfg_mi_ack (ctrl_mi_ack), + .in_mp_y_val (fifo_dpmux_y_val), + .in_mp_y_data (fifo_dpmux_y_data), + .in_mp_y_h_end (fifo_dpmux_y_h_end), + .in_mp_y_v_end (fifo_dpmux_y_v_end), + .in_mp_y_cfg_upd (fifo_dpmux_y_cfg_upd), + .in_mp_y_ack (fifo_dpmux_y_ack), + .in_mp_cb_val (fifo_dpmux_cb_val), + .in_mp_cb_data (fifo_dpmux_cb_data), + .in_mp_cb_h_end (fifo_dpmux_cb_h_end), + .in_mp_cb_v_end (fifo_dpmux_cb_v_end), + .in_mp_cb_cfg_upd (fifo_dpmux_cb_cfg_upd), + .in_mp_cb_ack (fifo_dpmux_cb_ack), + .in_mp_cr_val (fifo_dpmux_cr_val), + .in_mp_cr_data (fifo_dpmux_cr_data), + .in_mp_cr_h_end (fifo_dpmux_cr_h_end), + .in_mp_cr_v_end (fifo_dpmux_cr_v_end), + .in_mp_cr_cfg_upd (fifo_dpmux_cr_cfg_upd), + .in_mp_cr_ack (fifo_dpmux_cr_ack), + .in_sp_y_val (rszs2mi_y_val), + .in_sp_y_data (rszs2mi_y_data), + .in_sp_y_h_end (rszs2mi_y_h_end), + .in_sp_y_v_end (rszs2mi_y_v_end), + .in_sp_y_cfg_upd (rszs2mi_y_cfg_upd), + .in_sp_y_ack (rszs2mi_y_ack), + .in_sp_cb_val (rszs2mi_cb_val), + .in_sp_cb_data (rszs2mi_cb_data), + .in_sp_cb_h_end (rszs2mi_cb_h_end), + .in_sp_cb_v_end (rszs2mi_cb_v_end), + .in_sp_cb_cfg_upd (rszs2mi_cb_cfg_upd), + .in_sp_cb_ack (rszs2mi_cb_ack), + .in_sp_cr_val (rszs2mi_cr_val), + .in_sp_cr_data (rszs2mi_cr_data), + .in_sp_cr_h_end (rszs2mi_cr_h_end), + .in_sp_cr_v_end (rszs2mi_cr_v_end), + .in_sp_cr_cfg_upd (rszs2mi_cr_cfg_upd), + .in_sp_cr_ack (rszs2mi_cr_ack), + .in_jpeg_val (jpeg_mi_val), + .in_jpeg_data ({jpeg_mi_data[ 7: 0], + jpeg_mi_data[15: 8], + jpeg_mi_data[23:16], + jpeg_mi_data[31:24], + jpeg_mi_data[39:32], + jpeg_mi_data[47:40], + jpeg_mi_data[55:48], + jpeg_mi_data[63:56]}), + .in_jpeg_end (jpeg_mi_end), + .in_jpeg_byte_no (jpeg_mi_byte_no), + .in_jpeg_ack (), + .in_dp_data (isp_dp_data), + .in_dp_end (isp_dp_end), + .in_dp_val (isp_dp_val), + .in_dp_ack (), + .in_bp_val (1'b0 ), + .in_bp_data (16'b0 ), + .in_bp_h_end (1'b0 ), + .in_bp_v_end (1'b0 ), + .in_bp_cfg_upd (1'b0 ), + .in_bp_ack ( ), + .in_bp_frame_end (1'b0 ), + .bayer_pat (2'b0 ), + .data_mode_en (1'b0 ), + .vci_out_m1_cmdval (bvci_out_m1_cmdval), + .vci_out_m1_plen (bvci_out_m1_plen), + .vci_out_m1_eop (bvci_out_m1_eop), + .vci_out_m1_address (bvci_out_m1_address), + .vci_out_m1_wdata (bvci_out_m1_wdata), + .vci_out_m1_be (bvci_out_m1_be), + .vci_out_m1_cmd (bvci_out_m1_cmd), + .vci_out_m1_const (bvci_out_m1_const), + .vci_out_m1_contig (bvci_out_m1_contig), + .vci_out_m1_wrap (bvci_out_m1_wrap), + .vci_out_m1_cmdack (bvci_out_m1_cmdack), + .vci_out_m1_rspval (bvci_out_m1_rspval), + .vci_out_m1_reop (bvci_out_m1_reop), + .vci_out_m1_rspack (bvci_out_m1_rspack), + .vci_out_m2_cmdval (bvci_out_m2_cmdval), + .vci_out_m2_plen (bvci_out_m2_plen), + .vci_out_m2_eop (bvci_out_m2_eop), + .vci_out_m2_address (bvci_out_m2_address), + .vci_out_m2_wdata (bvci_out_m2_wdata), + .vci_out_m2_be (bvci_out_m2_be), + .vci_out_m2_cmd (bvci_out_m2_cmd), + .vci_out_m2_const (bvci_out_m2_const), + .vci_out_m2_contig (bvci_out_m2_contig), + .vci_out_m2_wrap (bvci_out_m2_wrap), + .vci_out_m2_cmdack (bvci_out_m2_cmdack), + .vci_out_m2_rspval (bvci_out_m2_rspval), + .vci_out_m2_reop (bvci_out_m2_reop), + .vci_out_m2_rspack (bvci_out_m2_rspack), + .vci_out_m3_cmdval (), + .vci_out_m3_plen (), + .vci_out_m3_eop (), + .vci_out_m3_address (), + .vci_out_m3_wdata (), + .vci_out_m3_be (), + .vci_out_m3_cmd (), + .vci_out_m3_const (), + .vci_out_m3_contig (), + .vci_out_m3_wrap (), + .vci_out_m3_cmdack (1'b1), + .vci_out_m3_rspval (1'b1), + .vci_out_m3_reop (1'b1), + .vci_out_m3_rspack (), + .out_y_val (mi_dmamux_y_val), + .out_y_data (mi_dmamux_y_data), + .out_y_h_end (mi_dmamux_y_h_end), + .out_y_v_end (mi_dmamux_y_v_end), + .out_y_cfg_update (mi_dmamux_y_cfg_upd), + .out_y_ack (1'b1), + .out_c_val (mi_dmamux_c_val), + .out_c_data (mi_dmamux_c_data), + .out_c_h_end (mi_dmamux_c_h_end), + .out_c_v_end (mi_dmamux_c_v_end), + .out_c_cfg_update (mi_dmamux_c_cfg_upd), + .out_c_ack (1'b1), + .vci_in_cmdval (bvci_in_cmdval ), + .vci_in_plen (bvci_in_plen ), + .vci_in_eop (bvci_in_eop ), + .vci_in_address (bvci_in_address), + .vci_in_be (bvci_in_be ), + .vci_in_cmd (bvci_in_cmd ), + .vci_in_const (bvci_in_const ), + .vci_in_contig (bvci_in_contig ), + .vci_in_wrap (bvci_in_wrap ), + .vci_in_cmdack (bvci_in_cmdack ), + .vci_in_rspval (bvci_in_rspval ), + .vci_in_reop (bvci_in_reop ), + .vci_in_rdata (bvci_in_rdata ), + .vci_in_rspack (bvci_in_rspack ), + .mi_mp_frame_end_int (mi_mp_frame_end_int), + .mi_bp_frame_end_int (mi_bp_frame_end_int), + .mi_sp_frame_end_int (mi_sp_frame_end_int), + .mi_mblk_line_int (mi_mblk_line_int), + .mi_fill_mp_y_int (mi_fill_mp_y_int), + .mi_fill_bp_r_int (mi_fill_bp_r_int), + .mi_wrap_mp_y_int (mi_wrap_mp_y_int), + .mi_wrap_mp_cb_int (mi_wrap_mp_cb_int), + .mi_wrap_mp_cr_int (mi_wrap_mp_cr_int), + .mi_wrap_bp_r_int (mi_wrap_mp_r_int), + .mi_wrap_bp_gr_int (mi_wrap_mp_gr_int), + .mi_wrap_bp_gb_int (mi_wrap_mp_gb_int), + .mi_wrap_bp_b_int (mi_wrap_mp_b_int), + .mi_wrap_sp_y_int (mi_wrap_sp_y_int), + .mi_wrap_sp_cb_int (mi_wrap_sp_cb_int), + .mi_wrap_sp_cr_int (mi_wrap_sp_cr_int), + .mi_dma_ready_int (mi_dma_ready_int), + .mi_mp_handshk_int (mi_mp_handshk_int), + .mi_mp_handshk_sw_int(mi_mp_handshk_sw_int), + .rot_en (rot_en ), + .ram_cs_n (rotram_cs_n ), + .ram_we_n (rotram_we_n ), + .ram_addr (rotram_addr ), + .ram_wdata (rotram_wdata), + .ram_rdata (32'h0), + .mp_y_fifo_sram_DIN (mp_y_fifo_sram_rdata ), + .mp_y_fifo_sram_DOUT (mp_y_fifo_sram_wdata ), + .mp_y_fifo_sram_ADDR (mp_y_fifo_sram_addr ), + .mp_y_fifo_sram_CEN (mp_y_fifo_sram_cs_n ), + .mp_y_fifo_sram_WEN (mp_y_fifo_sram_we_n ), + .mp_cb_fifo_sram_DIN (mp_cb_fifo_sram_rdata ), + .mp_cb_fifo_sram_DOUT (mp_cb_fifo_sram_wdata ), + .mp_cb_fifo_sram_ADDR (mp_cb_fifo_sram_addr ), + .mp_cb_fifo_sram_CEN (mp_cb_fifo_sram_cs_n ), + .mp_cb_fifo_sram_WEN (mp_cb_fifo_sram_we_n ), + .mp_cr_fifo_sram_DIN (mp_cr_fifo_sram_rdata ), + .mp_cr_fifo_sram_DOUT (mp_cr_fifo_sram_wdata ), + .mp_cr_fifo_sram_ADDR (mp_cr_fifo_sram_addr ), + .mp_cr_fifo_sram_CEN (mp_cr_fifo_sram_cs_n ), + .mp_cr_fifo_sram_WEN (mp_cr_fifo_sram_we_n ), + .bp_ec_fifo_sram_DIN (66'd0 ), + .bp_ec_fifo_sram_DOUT ( ), + .bp_ec_fifo_sram_ADDR ( ), + .bp_ec_fifo_sram_CEN ( ), + .bp_ec_fifo_sram_WEN ( ), + .bp_oc_fifo_sram_DIN (66'd0 ), + .bp_oc_fifo_sram_DOUT ( ), + .bp_oc_fifo_sram_ADDR ( ), + .bp_oc_fifo_sram_CEN ( ), + .bp_oc_fifo_sram_WEN ( ), + .last_pixel_m1_req (last_pixel_m1_req), + .last_pixel_m1_ack (1'b1), + .last_pixel_m2_req(), + .last_pixel_m2_ack(1'b1), + .last_pixel_m3_req (last_pixel_m3_req), + .last_pixel_m3_ack (1'b1) + ); + vsisp_marvin_pvci_reg_stage u_marvin_pvci_reg_stage + (.clk (s_hclk), + .reset_n (ctrl_reset_s_hclk_n), + .pwdata_i (pwdata), + .paddr_i (paddr), + .pval_i (pval), + .prd_i (prd), + .pack_o (pack), + .prdata_o (prdata), + .pwdata_o (pwdata_tmp), + .paddr_o (paddr_tmp), + .pval_o (pval_tmp), + .prd_o (prd_tmp), + .pack_i (pack_tmp), + .prdata_i (prdata_tmp) + ); + vsisp_pvci_mux u_pvci_mux + ( + .paddr (paddr_tmp[11:0]), + .hval (pval_tmp), + .hack (pack_tmp), + .hrdata (prdata_tmp), + .val_all (ahbs_ctrl_pval_all), + .ack_all (ahbs_ctrl_pack_all), + .rdata_all (ahbs_ctrl_prdata_all), + .val_mi (ahbs_ctrl_pval_mi), + .ack_mi (ahbs_ctrl_pack_mi), + .rdata_mi (ahbs_ctrl_prdata_mi) + ); + vsisp_pvci_sync u_pvci_sync_all + ( + .hclk (s_hclk), + .hreset_n (ctrl_reset_s_hclk_n), + .clk (clk), + .reset_clk_n (ctrl_reset_clk_n), + .hval (ahbs_ctrl_pval_all), + .hack (ahbs_ctrl_pack_all), + .hrdata (ahbs_ctrl_prdata_all), + .val (ctrl_pval_all), + .ack (ctrl_pack_all), + .rdata (ctrl_prdata_all) + ); + vsisp_pvci_sync u_pvci_sync_mi + ( + .hclk (s_hclk), + .hreset_n (ctrl_reset_s_hclk_n), + .clk (m_hclk), + .reset_clk_n (ctrl_reset_m_hclk_n), + .hval (ahbs_ctrl_pval_mi), + .hack (ahbs_ctrl_pack_mi), + .hrdata (ahbs_ctrl_prdata_mi), + .val (ctrl_pval_mi), + .ack (ctrl_pack_mi), + .rdata (ctrl_prdata_mi) + ); + vsisp_marvin_ctrl + u_marvin_ctrl + ( + .clk (clk), + .reset_n (reset_n), + .ctrl_reset_clk_n(ctrl_reset_clk_n), + .m_hclk (m_hclk), + .reset_m_hclk_n (ctrl_reset_m_hclk_n), + .soft_rst_marvin (soft_rst_marvin), + .paddr (paddr_tmp), + .pwdata (pwdata_tmp), + .prdata (ctrl_prdata_all), + .pval (ctrl_pval_all), + .prd (prd_tmp), + .pack (ctrl_pack_all), + .cfg_addr (ctrl_all_addr), + .cfg_wdata (ctrl_all_wdata), + .cfg_rd (ctrl_all_rd), + .cfg_rdata_isp (ctrl_isp_rdata), + .cfg_val_isp (ctrl_isp_val), + .cfg_ack_isp (ctrl_isp_ack), + .cfg_rdata_mrsz (ctrl_rszm_rdata), + .cfg_val_mrsz (ctrl_rszm_val), + .cfg_ack_mrsz (ctrl_rszm_ack), + .cfg_rdata_srsz (ctrl_rszs_rdata), + .cfg_val_srsz (ctrl_rszs_val), + .cfg_ack_srsz (ctrl_rszs_ack), + .clk_isp (ctrl_isp_clk), + .clk_mrsz (ctrl_rszm_clk), + .clk_srsz (ctrl_rszs_clk), + .clk_mi (ctrl_mi_clk), + .clk_cfg_isp (ctrl_isp_clk_cfg), + .clk_cfg_mrsz (ctrl_rszm_clk_cfg), + .clk_cfg_srsz (ctrl_rszs_clk_cfg), + .soft_rst_isp (ctrl_isp_soft_rst), + .soft_rst_yc (ctrl_yc_soft_rst), + .soft_rst_mrsz (ctrl_rszm_soft_rst), + .soft_rst_srsz (ctrl_rszs_soft_rst), + .soft_rst_mi (ctrl_mi_soft_rst), + .mi_clk_en_mhclk (mi_clk_en_mhclk), + .soft_rst_mi_mhclk (soft_rst_mi_mhclk), + .isp_clk_en (isp_clk_en), + .test_mode (scan_mode_src) + ); + vsisp_mi_jpeg_ctrl u_mi_ctrl + ( + .clk (m_hclk), + .reset_clk_n (ctrl_reset_m_hclk_n), + .paddr (paddr_tmp), + .pwdata (pwdata_tmp), + .prdata (ctrl_prdata_mi), + .pval (ctrl_pval_mi), + .prd (prd_tmp), + .pack (ctrl_pack_mi), + .cfg_addr (ctrl_mi_addr), + .cfg_wdata (ctrl_mi_wdata), + .cfg_rd (ctrl_mi_rd), + .cfg_rdata (ctrl_mi_rdata), + .cfg_val (ctrl_mi_val), + .cfg_ack (ctrl_mi_ack), + .clk_cfg (ctrl_mi_m_hclk_cfg), + .clk_en (mi_clk_en_mhclk), + .test_mode (scan_mode_src) + ); + assign sclk_gated = sclk; + vsisp_marvin_ctrl_reset_gen u_marvin_ctrl_sclk_reset ( + .reset_n(reset_n), + .clk(sclk), + .soft_rst_i(soft_rst_marvin), + .reset_out_n(ctrl_reset_sclk_n), + .test_mode(scan_mode_src) + ); + vsisp_marvin_ctrl_reset_gen u_marvin_ctrl_clk_reset ( + .reset_n(reset_n), + .clk(clk), + .soft_rst_i(soft_rst_marvin), + .reset_out_n(ctrl_reset_clk_n), + .test_mode(scan_mode_src) + ); + vsisp_marvin_ctrl_reset_gen u_marvin_ctrl_s_hclk_reset ( + .reset_n(reset_n), + .clk(s_hclk), + .soft_rst_i(soft_rst_marvin), + .reset_out_n(ctrl_reset_s_hclk_n), + .test_mode(scan_mode_src) + ); + vsisp_marvin_ctrl_reset_gen u_marvin_ctrl_m_hclk_reset ( + .reset_n(reset_n), + .clk(m_hclk), + .soft_rst_i(soft_rst_marvin), + .reset_out_n(ctrl_reset_m_hclk_n), + .test_mode(scan_mode_src) + ); + vsisp_marvin_irq_handler u_marvin_irq_handler + ( + .clk (clk), + .reset_n (ctrl_reset_clk_n), + .jpeg_clk (clk), + .reset_jpeg_clk_n (ctrl_reset_clk_n), + .isp_hist_end_int (1'b0), + .isp_exp_end_int (isp_exp_end_int), + .isp_fl_cap_int (1'b0), + .isp_afm_fin_int (1'b0), + .isp_afm_lum_of_int (1'b0), + .isp_afm_sum_of_int (1'b0), + .isp_sh_off_int (1'b0), + .isp_sh_on_int (1'b0), + .isp_fl_off_int (1'b0), + .isp_fl_on_int (1'b0), + .isp_h_start_int (isp_h_start_int), + .isp_v_start_int (isp_v_start_int), + .isp_frame_in_int (isp_frame_in_int), + .isp_awb_done_int (isp_awb_done_int), + .isp_vsm_done_int (1'b0), + .isp_size_err_int (isp_size_err_int), + .isp_frame_int (1'b0), + .isp_dataloss_int (isp_dataloss_int), + .isp_off_int (1'b0), + .mi_mp_frame_end_int (mi_mp_frame_end_int), + .mi_bp_frame_end_int (1'b0), + .mi_sp_frame_end_int (mi_sp_frame_end_int), + .mi_mblk_line_int (mi_mblk_line_int), + .mi_fill_mp_y_int (mi_fill_mp_y_int), + .mi_fill_bp_r_int (1'b0), + .mi_wrap_mp_y_int (mi_wrap_mp_y_int), + .mi_wrap_mp_cb_int (mi_wrap_mp_cb_int), + .mi_wrap_mp_cr_int (1'b0), + .mi_wrap_bp_r_int (1'b0), + .mi_wrap_bp_gr_int (1'b0), + .mi_wrap_bp_gb_int (1'b0), + .mi_wrap_bp_b_int (1'b0), + .mi_wrap_sp_y_int (mi_wrap_sp_y_int), + .mi_wrap_sp_cb_int (1'b0), + .mi_wrap_sp_cr_int (1'b0), + .mi_dma_ready_int (1'b0), + .mi_mp_handshk_int (1'b0), + .mi_mp_handshk_sw_int(1'b0), + .jpeg_err_int (11'h0), + .jpeg_stat_int (2'h0), + .mi_irq (mi_irq), + .isp_irq (isp_irq), + .jpeg_stat_irq (), + .jpeg_err_irq () + ); + vsisp_bvci2axi_wr u_bvci2axi_wr_mp + ( + .clk (m_hclk), + .reset_n (ctrl_reset_m_hclk_n), + .bvci_cmdval (bvci_out_m1_cmdval), + .bvci_cmdack (bvci_out_m1_cmdack), + .bvci_cmd (bvci_out_m1_cmd), + .bvci_plen (bvci_out_m1_plen), + .bvci_contig (bvci_out_m1_contig), + .bvci_wrap (bvci_out_m1_wrap), + .bvci_address (bvci_out_m1_address), + .bvci_be (bvci_out_m1_be), + .bvci_eop (bvci_out_m1_eop), + .bvci_rspval (bvci_out_m1_rspval), + .bvci_rspack (bvci_out_m1_rspack), + .bvci_reop (bvci_out_m1_reop), + .bvci_wdata (bvci_out_m1_wdata), + .axi_wr_marvin_awvalid(axi_m1_marvin_awvalid), + .axi_wr_marvin_awaddr (axi_m1_marvin_awaddr), + .axi_wr_marvin_awlen (axi_m1_marvin_awlen), + .axi_wr_marvin_awsize (axi_m1_marvin_awsize), + .axi_wr_marvin_awburst(axi_m1_marvin_awburst), + .axi_wr_marvin_awlock (axi_m1_marvin_awlock), + .axi_wr_marvin_awcache(axi_m1_marvin_awcache), + .axi_wr_marvin_awprot (axi_m1_marvin_awprot), + .axi_wr_marvin_awid (axi_m1_marvin_awid), + .axi_wr_marvin_awready(axi_m1_marvin_awready), + .axi_wr_marvin_wvalid (axi_m1_marvin_wvalid), + .axi_wr_marvin_wlast (axi_m1_marvin_wlast), + .axi_wr_marvin_wdata (axi_m1_marvin_wdata), + .axi_wr_marvin_wstrb (axi_m1_marvin_wstrb), + .axi_wr_marvin_wid (axi_m1_marvin_wid), + .axi_wr_marvin_wready (axi_m1_marvin_wready), + .axi_wr_marvin_bvalid (axi_m1_marvin_bvalid), + .axi_wr_marvin_bresp (axi_m1_marvin_bresp), + .axi_wr_marvin_bid (axi_m1_marvin_bid), + .axi_wr_marvin_bready (axi_m1_marvin_bready) + ); + vsisp_bvci2axi_wr u_bvci2axi_wr_sp + ( + .clk (m_hclk), + .reset_n (ctrl_reset_m_hclk_n), + .bvci_cmdval (bvci_out_m2_cmdval), + .bvci_cmdack (bvci_out_m2_cmdack), + .bvci_cmd (bvci_out_m2_cmd), + .bvci_plen (bvci_out_m2_plen), + .bvci_contig (bvci_out_m2_contig), + .bvci_wrap (bvci_out_m2_wrap), + .bvci_address (bvci_out_m2_address), + .bvci_be (bvci_out_m2_be), + .bvci_eop (bvci_out_m2_eop), + .bvci_rspval (bvci_out_m2_rspval), + .bvci_rspack (bvci_out_m2_rspack), + .bvci_reop (bvci_out_m2_reop), + .bvci_wdata (bvci_out_m2_wdata), + .axi_wr_marvin_awvalid(axi_m2_marvin_awvalid), + .axi_wr_marvin_awaddr (axi_m2_marvin_awaddr), + .axi_wr_marvin_awlen (axi_m2_marvin_awlen), + .axi_wr_marvin_awsize (axi_m2_marvin_awsize), + .axi_wr_marvin_awburst(axi_m2_marvin_awburst), + .axi_wr_marvin_awlock (axi_m2_marvin_awlock), + .axi_wr_marvin_awcache(axi_m2_marvin_awcache), + .axi_wr_marvin_awprot (axi_m2_marvin_awprot), + .axi_wr_marvin_awid (axi_m2_marvin_awid), + .axi_wr_marvin_awready(axi_m2_marvin_awready), + .axi_wr_marvin_wvalid (axi_m2_marvin_wvalid), + .axi_wr_marvin_wlast (axi_m2_marvin_wlast), + .axi_wr_marvin_wdata (axi_m2_marvin_wdata), + .axi_wr_marvin_wstrb (axi_m2_marvin_wstrb), + .axi_wr_marvin_wid (axi_m2_marvin_wid), + .axi_wr_marvin_wready (axi_m2_marvin_wready), + .axi_wr_marvin_bvalid (axi_m2_marvin_bvalid), + .axi_wr_marvin_bresp (axi_m2_marvin_bresp), + .axi_wr_marvin_bid (axi_m2_marvin_bid), + .axi_wr_marvin_bready (axi_m2_marvin_bready) + ); + assign bvci_in_cmdack = 1'b1; + assign bvci_in_rspval = 1'b1; + assign bvci_in_reop = 1'b1; + assign bvci_in_rdata = 64'b0; + assign axi_rd_marvin_arvalid = 1'b0; + assign axi_rd_marvin_araddr = 29'b0; + assign axi_rd_marvin_arlen = 4'b0; + assign axi_rd_marvin_arsize = 3'b0; + assign axi_rd_marvin_arburst = 2'b0; + assign axi_rd_marvin_arlock = 2'b0; + assign axi_rd_marvin_arcache = 4'b0; + assign axi_rd_marvin_arprot = 3'b0; + assign axi_rd_marvin_arid = 4'b0; + assign axi_rd_marvin_rready = 1'b1; +`ifdef FPGA_DEBUG_ISP + (* mark_debug = "true" *)reg [15:0] probing__s1_data/* synthesis syn_noprune=1 syn_preserve = 1 */; // in sensor pixel data [c_dw-1:0] + (* mark_debug = "true" *)reg probing__s1_hsync/* synthesis syn_noprune=1 syn_preserve = 1 */; // in horizontal synchronization signal + (* mark_debug = "true" *)reg probing__s1_vsync/* synthesis syn_noprune=1 syn_preserve = 1 */; // in vertical synchronization signal + (* mark_debug = "true" *)reg probing__s1_valid/* synthesis syn_noprune=1 syn_preserve = 1 */; + (* mark_debug = "true" *) reg probing__axi_m1_marvin_awvalid; + (* mark_debug = "true" *) reg [31:3] probing__axi_m1_marvin_awaddr; + (* mark_debug = "true" *) reg [3:0] probing__axi_m1_marvin_awlen; + (* mark_debug = "true" *) reg [2:0] probing__axi_m1_marvin_awsize; + (* mark_debug = "true" *) reg [1:0] probing__axi_m1_marvin_awburst; + (* mark_debug = "true" *) reg [1:0] probing__axi_m1_marvin_awlock; + (* mark_debug = "true" *) reg [3:0] probing__axi_m1_marvin_awcache; + (* mark_debug = "true" *) reg [2:0] probing__axi_m1_marvin_awprot; + (* mark_debug = "true" *) reg [3:0] probing__axi_m1_marvin_awid; + (* mark_debug = "true" *) reg probing__axi_m1_marvin_awready; + (* mark_debug = "true" *) reg probing__axi_m1_marvin_wvalid; + (* mark_debug = "true" *) reg probing__axi_m1_marvin_wlast; + (* mark_debug = "true" *) reg [63:0] probing__axi_m1_marvin_wdata; + (* mark_debug = "true" *) reg [7:0] probing__axi_m1_marvin_wstrb; + (* mark_debug = "true" *) reg [3:0] probing__axi_m1_marvin_wid; + (* mark_debug = "true" *) reg probing__axi_m1_marvin_wready; + (* mark_debug = "true" *) reg probing__axi_m1_marvin_bvalid; + (* mark_debug = "true" *) reg [1:0] probing__axi_m1_marvin_bresp; + (* mark_debug = "true" *) reg [3:0] probing__axi_m1_marvin_bid; + (* mark_debug = "true" *) reg probing__axi_m1_marvin_bready; + (* mark_debug = "true" *) reg probing__axi_m2_marvin_awvalid; + (* mark_debug = "true" *) reg [31:3] probing__axi_m2_marvin_awaddr; + (* mark_debug = "true" *) reg [3:0] probing__axi_m2_marvin_awlen; + (* mark_debug = "true" *) reg [2:0] probing__axi_m2_marvin_awsize; + (* mark_debug = "true" *) reg [1:0] probing__axi_m2_marvin_awburst; + (* mark_debug = "true" *) reg [1:0] probing__axi_m2_marvin_awlock; + (* mark_debug = "true" *) reg [3:0] probing__axi_m2_marvin_awcache; + (* mark_debug = "true" *) reg [2:0] probing__axi_m2_marvin_awprot; + (* mark_debug = "true" *) reg [3:0] probing__axi_m2_marvin_awid; + (* mark_debug = "true" *) reg probing__axi_m2_marvin_awready; + (* mark_debug = "true" *) reg probing__axi_m2_marvin_wvalid; + (* mark_debug = "true" *) reg probing__axi_m2_marvin_wlast; + (* mark_debug = "true" *) reg [63:0] probing__axi_m2_marvin_wdata; + (* mark_debug = "true" *) reg [7:0] probing__axi_m2_marvin_wstrb; + (* mark_debug = "true" *) reg [3:0] probing__axi_m2_marvin_wid; + (* mark_debug = "true" *) reg probing__axi_m2_marvin_wready; + (* mark_debug = "true" *) reg probing__axi_m2_marvin_bvalid; + (* mark_debug = "true" *) reg [1:0] probing__axi_m2_marvin_bresp; + (* mark_debug = "true" *) reg [3:0] probing__axi_m2_marvin_bid; + (* mark_debug = "true" *) reg probing__axi_m2_marvin_bready; +always@(posedge sclk)begin + probing__s1_data <= s_data ; + probing__s1_hsync <= s_hsync ; + probing__s1_vsync <= s_vsync ; + probing__s1_valid <= s_valid ; +end +always @(posedge m_hclk) begin +probing__axi_m1_marvin_awvalid <= axi_m1_marvin_awvalid ; +probing__axi_m1_marvin_awaddr <= axi_m1_marvin_awaddr ; +probing__axi_m1_marvin_awlen <= axi_m1_marvin_awlen ; +probing__axi_m1_marvin_awsize <= axi_m1_marvin_awsize ; +probing__axi_m1_marvin_awburst <= axi_m1_marvin_awburst ; +probing__axi_m1_marvin_awlock <= axi_m1_marvin_awlock ; +probing__axi_m1_marvin_awcache <= axi_m1_marvin_awcache ; +probing__axi_m1_marvin_awprot <= axi_m1_marvin_awprot ; +probing__axi_m1_marvin_awid <= axi_m1_marvin_awid ; +probing__axi_m1_marvin_awready <= axi_m1_marvin_awready ; +probing__axi_m1_marvin_wvalid <= axi_m1_marvin_wvalid ; +probing__axi_m1_marvin_wlast <= axi_m1_marvin_wlast ; +probing__axi_m1_marvin_wdata <= axi_m1_marvin_wdata ; +probing__axi_m1_marvin_wstrb <= axi_m1_marvin_wstrb ; +probing__axi_m1_marvin_wid <= axi_m1_marvin_wid ; +probing__axi_m1_marvin_wready <= axi_m1_marvin_wready ; +probing__axi_m1_marvin_bvalid <= axi_m1_marvin_bvalid ; +probing__axi_m1_marvin_bresp <= axi_m1_marvin_bresp ; +probing__axi_m1_marvin_bid <= axi_m1_marvin_bid ; +probing__axi_m1_marvin_bready <= axi_m1_marvin_bready ; +probing__axi_m2_marvin_awvalid <= axi_m2_marvin_awvalid ; +probing__axi_m2_marvin_awaddr <= axi_m2_marvin_awaddr ; +probing__axi_m2_marvin_awlen <= axi_m2_marvin_awlen ; +probing__axi_m2_marvin_awsize <= axi_m2_marvin_awsize ; +probing__axi_m2_marvin_awburst <= axi_m2_marvin_awburst ; +probing__axi_m2_marvin_awlock <= axi_m2_marvin_awlock ; +probing__axi_m2_marvin_awcache <= axi_m2_marvin_awcache ; +probing__axi_m2_marvin_awprot <= axi_m2_marvin_awprot ; +probing__axi_m2_marvin_awid <= axi_m2_marvin_awid ; +probing__axi_m2_marvin_awready <= axi_m2_marvin_awready ; +probing__axi_m2_marvin_wvalid <= axi_m2_marvin_wvalid ; +probing__axi_m2_marvin_wlast <= axi_m2_marvin_wlast ; +probing__axi_m2_marvin_wdata <= axi_m2_marvin_wdata ; +probing__axi_m2_marvin_wstrb <= axi_m2_marvin_wstrb ; +probing__axi_m2_marvin_wid <= axi_m2_marvin_wid ; +probing__axi_m2_marvin_wready <= axi_m2_marvin_wready ; +probing__axi_m2_marvin_bvalid <= axi_m2_marvin_bvalid ; +probing__axi_m2_marvin_bresp <= axi_m2_marvin_bresp ; +probing__axi_m2_marvin_bid <= axi_m2_marvin_bid ; +probing__axi_m2_marvin_bready <= axi_m2_marvin_bready ; +end +`endif +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_mi_bayer_split.v b/ispyocto/rtl/ispyocto/vsisp_mi_bayer_split.v new file mode 100644 index 0000000..f5366b0 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_mi_bayer_split.v
@@ -0,0 +1,81 @@ +//**************************************************************************** +// +// Copyright 2023 Vivante Corp. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_mi_bayer_split( + clk, + reset_n, + soft_reset, + in_data, + in_hend, + in_vend, + in_val, + in_ack, + out_data0, + out_hend0, + out_vend0, + out_val0, + out_ack0, + out_data1, + out_hend1, + out_vend1, + out_val1, + out_ack1 +); + parameter data_width=16; + input clk; + input reset_n; + input soft_reset; + input [data_width-1:0] in_data; + input in_hend; + input in_vend; + input in_val; + output in_ack; + output [data_width-1:0] out_data0; + output out_hend0; + output out_vend0; + output out_val0; + input out_ack0; + output [data_width-1:0] out_data1; + output out_hend1; + output out_vend1; + output out_val1; + input out_ack1; + wire viv_s0; + wire viv_s1; + wire [data_width-1:0] viv_s2; + assign in_ack = viv_s0==1'b0 ? out_ack0: + out_ack1; + wire viv_s3 = out_val0 & out_ack0; + wire viv_s4 = in_val && in_ack && viv_s0==1'b0 ? 1'b1: + viv_s3 ? 1'b0: + viv_s1; + vsisp_dreg_en_1d #(1,1'b0) pixel_ptr_reg (.clk(clk), .reset_n(reset_n), .soft_reset(soft_reset), .out(viv_s0), .in(~viv_s0), .en(in_val & in_ack)); + vsisp_dreg_en_1d #(1,1'b0) out_val0_tmp_reg (.clk(clk), .reset_n(reset_n), .soft_reset(soft_reset), .out(viv_s1), .in(viv_s4), .en(1'b1)); + vsisp_dreg_en_1d #(data_width,{data_width{1'b0}}) out_data0_tmp_reg (.clk(clk), .reset_n(reset_n), .soft_reset(soft_reset), .out(viv_s2), .in(in_data), .en(in_val & in_ack & (viv_s0==1'b0) )); + assign out_val0 = out_val1 & viv_s1; + assign out_data0 = viv_s2; + assign out_hend0 = in_hend; + assign out_vend0 = in_vend; + assign out_val1 = in_val & viv_s0==1'b1; + assign out_data1 = in_data; + assign out_hend1 = in_hend; + assign out_vend1 = in_vend; +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_mi_dp_outstage.v b/ispyocto/rtl/ispyocto/vsisp_mi_dp_outstage.v new file mode 100644 index 0000000..8be2aea --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_mi_dp_outstage.v
@@ -0,0 +1,127 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + + module vsisp_mi_dp_outstage( + clk, + reset_n, + soft_reset, + in_val, + in_data, + in_hend, + in_vend, + in_ack, + in_duo, + out_val, + out_data, + out_hend, + out_vend, + out_ack + ); + input clk; + input reset_n; + input soft_reset; + input in_val; + input [127:0] in_data; + input in_hend; + input in_vend; + output in_ack; + input in_duo; + output out_val; + output [63:0] out_data; + output out_hend; + output out_vend; + input out_ack; + wire viv_s0 = out_val & out_ack; + wire viv_s1 = in_val & in_ack; + wire viv_s2 = viv_s1 & ~in_duo; + wire viv_s3 = viv_s1 & in_duo; + reg in_ack; + reg [1:0] viv_s4; + always @(posedge clk or negedge reset_n)begin + if(!reset_n)begin + in_ack <= 1'b0; + end + else if(soft_reset)begin + in_ack <= 1'b0; + end + else begin + if(viv_s1)begin + in_ack <=1'b0; + end + else if(viv_s4==2'b0 || viv_s4==2'b1 && viv_s0)begin + in_ack <= 1'b1; + end + end + end + always @(posedge clk or negedge reset_n)begin + if(!reset_n)begin + viv_s4 <=2'b0; + end + else if(soft_reset)begin + viv_s4 <=2'b0; + end + else begin + if(viv_s0)begin + if(viv_s2) viv_s4 <= viv_s4; + else if(viv_s3) viv_s4<= viv_s4 + 2'b01; + else viv_s4 <= viv_s4 - 2'b1; + end + else begin + if(viv_s2) viv_s4 <= viv_s4 + 2'b01; + else if(viv_s3) viv_s4 <= viv_s4 + 2'b10; + end + end + end +reg viv_s5; +reg [65:0] viv_s6, viv_s7; +always @(posedge clk or negedge reset_n)begin + if(!reset_n) viv_s5 <=1'b0; + else if(soft_reset) viv_s5 <=1'b0; + else begin + if(viv_s1) viv_s5 <= 1'b0; + else if(viv_s0) viv_s5 <= viv_s5 + 1'b1; + end +end +always @(posedge clk or negedge reset_n)begin + if(!reset_n) begin + viv_s6 <= 66'h0; + viv_s7 <= 66'h0; + end + else if(soft_reset) begin + viv_s6 <= 66'h0; + viv_s7 <= 66'h0; + end + else begin + if(viv_s2) begin + viv_s6 <= {in_hend, in_vend, in_data[0+:64]}; + end + else if(viv_s3)begin + viv_s6 <= { 1'b0, 1'b0, in_data[0+:64]}; + viv_s7 <= {in_hend, in_vend, in_data[64+:64]}; + end + end +end +assign out_val = viv_s4 !=0; +assign {out_hend, out_vend, out_data} = viv_s5 == 1'b0 ? viv_s6: + viv_s7; + endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_mi_dp_raw.v b/ispyocto/rtl/ispyocto/vsisp_mi_dp_raw.v new file mode 100644 index 0000000..9601287 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_mi_dp_raw.v
@@ -0,0 +1,674 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_mi_dp_raw +( +clk, +reset_n, +soft_rst, +rformat, +ralignen, +rpadpseud, +in_raw, +in_h_end, +in_v_end, +in_ack, +in_val, +out_h_end, +out_v_end, +out_fifo_full, +out_val, +out_raw, +out_cfg_upd, +out_duo, +cfg_in_update, +cfg_out_update, +auto_update, +path_enable +); +parameter pack_width=128; +parameter raw_width = 16; +input clk, reset_n; +input soft_rst; +input [3:0] rformat; +input [1:0] ralignen; +input rpadpseud; +input [raw_width-1: 0] in_raw; +input in_h_end, in_v_end, in_val; +output out_h_end, out_v_end; +output out_val; +output out_cfg_upd; +output out_duo; +output in_ack; +output [pack_width-1: 0] out_raw; +input out_fifo_full; +input path_enable; +output cfg_in_update; +input cfg_out_update; +input auto_update; +wire cfg_out_update; +reg cfg_in_update; +reg [pack_width-1+12: 0] viv_s0; +wire [pack_width-1: 0] viv_s1; +wire viv_s2 = in_val & path_enable; +wire viv_s3 = in_h_end & viv_s2; +wire viv_s4 = in_v_end & viv_s3; +wire viv_s5 = ~out_fifo_full; +integer i; +parameter fmtw=5; +localparam i8_w =8; +localparam i10_w =10; +localparam i12_w =12; +localparam i14_w =14; +localparam i16_w =16; +parameter RAW8 =5'bxx000,r8i =5'd0; +parameter RAW10=5'b00001,r10i=5'd1; +parameter RAW12=5'b00010,r12i=5'd2; +parameter RAW14=5'b00011,r14i=5'd3; +parameter RAW16=5'bxx100,r16i=5'd4; +parameter RAW10ALN={2'b01, RAW10[2:0]}, r10ai=5'd5; +parameter RAW12ALN={2'b01, RAW12[2:0]}, r12ai=5'd6; +parameter RAW14ALN={2'b01, RAW14[2:0]}, r14ai=5'd7; +parameter RAW10ALN16={2'b1x, RAW10[2:0]}, r10ahi=5'd8; +parameter RAW12ALN16={2'b1x, RAW12[2:0]}, r12ahi=5'd9; +parameter RAW14ALN16={2'b1x, RAW14[2:0]}, r14ahi=5'd10; +parameter [11*fmtw-1:0] format_cfg= {RAW14ALN16, RAW12ALN16, RAW10ALN16, + RAW14ALN,RAW12ALN,RAW10ALN, + RAW16,RAW14,RAW12, RAW10, RAW8}; +reg [pack_width-1:0] viv_s6; +reg [1:0] viv_s7; +wire viv_s8; +wire viv_s9; +assign viv_s9 = |viv_s7[1:0]; +assign viv_s8 = viv_s9 & viv_s5; +reg [1:0] viv_s10; +wire [1:0] viv_s11; +assign viv_s11 = {1'b0,viv_s7[1]}; +wire [4:0] viv_s12={ralignen[1:0],rformat[2:0]}; +wire viv_s13; +assign viv_s13=viv_s2&in_ack; +wire viv_s14; +assign viv_s14 = out_val & viv_s5; +reg viv_s15, viv_s16; +reg [raw_width-1:0] viv_s17; +always @(posedge clk or negedge reset_n)begin + if(~reset_n)begin + viv_s16 <= 1'b0; + end + else begin + if(~viv_s16)begin + viv_s16 <= viv_s4; + end + else if(out_v_end & viv_s14) begin + viv_s16 <= 1'b0; + end + end +end +always @(posedge clk or negedge reset_n)begin + if(~reset_n)begin + viv_s17 <= 1'b0; + viv_s15 <=1'b0; + end + else begin + viv_s17 <= viv_s13 ? in_raw: viv_s17; + viv_s15 <= viv_s13 ? viv_s3 : viv_s15; + end +end +reg [3:0] viv_s18; +reg [3:0] viv_s19; +wire [3:0] viv_s20; +reg [2:0] viv_s21; +reg [2:0] viv_s22; +wire [2:0] viv_s23; +assign viv_s20=viv_s18 + 1'b1; +assign viv_s23 = viv_s21 + 1'b1; +wire [raw_width-1:0] viv_s24 = viv_s12[2:0]== RAW10[2:0] ? in_raw[raw_width-1-:i10_w]: + viv_s12[2:0]== RAW12[2:0] ? in_raw[raw_width-1-:i12_w]: + viv_s12[2:0]== RAW14[2:0] ? in_raw[raw_width-1-:i14_w]: + in_raw[raw_width-1:0]; +`ifdef DEBUG +integer infocnt=0; +initial begin +forever begin + @(posedge clk); + if(infocnt > 1000) $finish; +end +end +`endif +always @(*)begin + viv_s19 = viv_s18; + viv_s22 = viv_s21; + viv_s19 = viv_s18; + viv_s10 = viv_s14? viv_s11: viv_s7; + if(viv_s13)begin + casex(viv_s12[4:0]) + RAW8:begin + viv_s19 = viv_s20; + viv_s10=&viv_s18[3:0]; + end + RAW10:begin + if(viv_s21==4 && viv_s18==11 || viv_s18==12)begin + viv_s19 = 0; + if(viv_s21==4) viv_s22 = 0; + else viv_s22 = viv_s23; + end + else viv_s19 = viv_s20; + if(viv_s18==12) viv_s10=2'b10; + else if(viv_s21==4 && viv_s18==11) viv_s10=2'b01; + end + RAW12:begin + if(viv_s21==2 && viv_s18==9 || viv_s18==10)begin + viv_s19 =0; + if(viv_s21==2) viv_s22 = 0; + else viv_s22 = viv_s23; + end + else viv_s19 = viv_s20; + if(viv_s18==10) viv_s10=2'b10; + else if(viv_s21==2 && viv_s18==9) viv_s10=2'b01; + end + RAW14:begin + if(viv_s18==9 || viv_s21!=0&&viv_s18==8 )begin + viv_s19 = 0; + if(viv_s21==6) viv_s22 = 0; + else viv_s22 = viv_s23; + end + else viv_s19 = viv_s20; + if(viv_s21==6 && viv_s18==8) viv_s10=2'b01; + else if(viv_s18==9 || viv_s21!=0&&viv_s18==8) viv_s10=2'b10; + end + RAW10ALN16,RAW12ALN16,RAW14ALN16,RAW16:begin + viv_s19 = viv_s20[2:0]; + viv_s10=&viv_s18[2:0]; + end + RAW10ALN:begin + if(viv_s18==11) begin + viv_s19 =0; + viv_s10=2'b01; + end + else viv_s19 = viv_s20; + end + RAW12ALN:begin + if(viv_s18==9) begin + viv_s19 = 0; + viv_s10=2'b01; + end + else viv_s19 = viv_s20; + end + RAW14ALN:begin + if(viv_s18==8) begin + viv_s19 = 0; + viv_s10=2'b01; + end + else viv_s19 = viv_s20; + end + default:; + endcase + end +if (viv_s13) begin + if(|viv_s10)begin + if(viv_s3) viv_s10 = viv_s10; + else viv_s10 = 2'b01; + end + else if(viv_s3) viv_s10 = 2'b01; + else viv_s10 = viv_s11; + if(viv_s3) viv_s19 = 0; + else viv_s19 = viv_s19; +end + if(viv_s7[1:0]==2'b10 && viv_s14==1'b1 || viv_s10[1:0]==2'b01 && viv_s3==1'b1 && viv_s13) viv_s22 = 3'd0; +end +reg [6:0] viv_s25; +reg [7:0] viv_s26; +reg viv_s27, out_duo; +always @(*)begin + viv_s26 = {1'b0,viv_s25}; + viv_s27 = out_duo; + if(viv_s13)begin + casex(viv_s12[4:0]) + RAW8:begin + viv_s26 = {1'b0,viv_s25} + i8_w; + end + RAW10:begin + viv_s26 = {1'b0,viv_s25} + i10_w; + end + RAW12:begin + viv_s26 = {1'b0,viv_s25} + i12_w; + end + RAW14:begin + viv_s26 = {1'b0,viv_s25} + i14_w; + end + RAW10ALN16,RAW12ALN16,RAW14ALN16,RAW16:begin + viv_s26 = {1'b0,viv_s25} + i16_w; + end + RAW10ALN:begin + if(viv_s18>=8'h05) begin + viv_s26 = 8'h41; + end + else begin + viv_s26 = 8'h00; + end + end + RAW12ALN:begin + if(viv_s18>=8'h04) begin + viv_s26 = 8'h41; + end + else begin + viv_s26 = 8'h00; + end + end + RAW14ALN:begin + if(viv_s18>=8'h03) begin + viv_s26 = 8'h41; + end + else begin + viv_s26 = 8'h00; + end + end + default:; + endcase + end +if (viv_s13) begin + if(viv_s26>8'h40)begin + viv_s27 = 1'b1; + end + else begin + viv_s27 = 1'b0; + end + if(viv_s3) viv_s26 = 8'h0; +end +else if (viv_s14) begin + viv_s27 = 1'b0; +end +end +always @(posedge clk or negedge reset_n)begin + if(!reset_n)begin + out_duo <= 1'b0; + viv_s25 <= 7'h0; + end + else begin + out_duo <= viv_s27; + viv_s25 <= viv_s26[6:0]; + end +end +reg [3:0] viv_s28; +reg [pack_width-1+i14_w:0] viv_s29; +reg [pack_width-1+i14_w:0] viv_s30; +parameter i10_rem_w= {4'd8, 4'd6, 4'd4, 4'd2, 4'd0}; +parameter i12_rem_w= {4'd8,4'd4,4'd0}; +parameter i14_rem_w= {4'd2, 4'd4, 4'd6, 4'd8, 4'd10, 4'd12, 4'd0}; +always @(*)begin + viv_s29 = viv_s30; + casex (viv_s12[4:0]) + format_cfg[r8i*fmtw+:fmtw]:begin + for(i=0;i<16;i=i+1)begin + if(viv_s18==i && viv_s13 )begin + viv_s29[i*i8_w+:i8_w]=in_raw[raw_width-1-:i8_w]; + end + else if(viv_s8==1'b1)begin + viv_s29[i*i8_w+:i8_w]={(i8_w){rpadpseud}}; + end + end + end + format_cfg[r10i*fmtw+:fmtw]:begin + case(viv_s21) + 3'b000:begin + for(i=0;i<13;i=i+1)begin + if(viv_s18==i && viv_s13 )begin + viv_s29[i*i10_w+:i10_w] =in_raw[raw_width-1-:i10_w]; + end + else if(viv_s8==1'b1)begin + viv_s29[i*i10_w+:i10_w] ={(i10_w){rpadpseud}}; + end + end + end + 3'b001:begin + if(viv_s8==1)begin + viv_s29[i10_rem_w[1*4+:4]-1:0]=viv_s17[raw_width-1-:i10_rem_w[1*4+:4]]; + end + else viv_s29[i10_rem_w[1*4+:4]-1:0]=viv_s30[i10_rem_w[1*4+:4]-1:0]; + for(i=0;i<13;i=i+1)begin + if(viv_s18==i && viv_s13 )begin + viv_s29[i*i10_w+i10_rem_w[1*4+:4]+:i10_w] = in_raw[raw_width-1-:i10_w]; + end + else if(viv_s8==1'b1)begin + viv_s29[i*i10_w+i10_rem_w[1*4+:4]+:i10_w] = {(i10_w){rpadpseud}}; + end + end + end + 3'b010:begin + if(viv_s8==1)begin + viv_s29[i10_rem_w[2*4+:4]-1:0]=viv_s17[raw_width-1-:i10_rem_w[2*4+:4]]; + end + else viv_s29[i10_rem_w[2*4+:4]-1:0]=viv_s30[i10_rem_w[2*4+:4]-1:0]; + for(i=0;i<13;i=i+1)begin + if(viv_s18==i && viv_s13 )begin + viv_s29[i*i10_w+i10_rem_w[2*4+:4]+:i10_w] = in_raw[raw_width-1-:i10_w]; + end + else if(viv_s8==1'b1)begin + viv_s29[i*i10_w+i10_rem_w[2*4+:4]+:i10_w] = {(i10_w){rpadpseud}}; + end + end + end + 3'b011:begin + if(viv_s8==1)begin + viv_s29[i10_rem_w[3*4+:4]-1:0]=viv_s17[raw_width-1-:i10_rem_w[3*4+:4]]; + end + else viv_s29[i10_rem_w[3*4+:4]-1:0]=viv_s30[i10_rem_w[3*4+:4]-1:0]; + for(i=0;i<13;i=i+1)begin + if(viv_s18==i && viv_s13 )begin + viv_s29[i*i10_w+i10_rem_w[3*4+:4]+:i10_w] = in_raw[raw_width-1-:i10_w]; + end + else if(viv_s8==1'b1)begin + viv_s29[i*i10_w+i10_rem_w[3*4+:4]+:i10_w] = {(i10_w){rpadpseud}}; + end + end + end + 3'b100:begin + if(viv_s8==1)begin + viv_s29[i10_rem_w[4*4+:4]-1:0]=viv_s17[raw_width-1-:i10_rem_w[4*4+:4]]; + end + else viv_s29[i10_rem_w[4*4+:4]-1:0]=viv_s30[i10_rem_w[4*4+:4]-1:0]; + for(i=0;i<13;i=i+1)begin + if(viv_s18==i && viv_s13 )begin + viv_s29[i*i10_w+i10_rem_w[4*4+:4]+:i10_w] = in_raw[raw_width-1-:i10_w]; + end + else if(viv_s8==1'b1)begin + viv_s29[i*i10_w+i10_rem_w[4*4+:4]+:i10_w] = {(i10_w){rpadpseud}}; + end + end + end + default:; + endcase + end + format_cfg[r12i*fmtw+:fmtw]: + case(viv_s21) + 3'b000:begin + for(i=0;i<11;i=i+1)begin + if(viv_s18==i && viv_s13 )begin + viv_s29[i*i12_w+i12_rem_w[0*4+:4]+:i12_w] = in_raw[raw_width-1-:i12_w]; + end + else if(viv_s8==1'b1)begin + viv_s29[i*i12_w+i12_rem_w[0*4+:4]+:i12_w] = {(i12_w){1'b0}}; + end + end + end + 3'b001:begin + if(viv_s8==1'b1) begin + viv_s29[i12_rem_w[1*4+:4]-1:0] = viv_s17[raw_width-1-:i12_rem_w[1*4+:4]]; + end + else begin + viv_s29[i12_rem_w[1*4+:4]-1:0] = viv_s30[i12_rem_w[1*4+:4]-1:0]; + end + for(i=0;i<11;i=i+1)begin + if(viv_s18==i && viv_s13 )begin + viv_s29[i*i12_w+i12_rem_w[1*4+:4]+:i12_w] = in_raw[raw_width-1-:i12_w]; + end + else if(viv_s8==1'b1)begin + viv_s29[i*i12_w+i12_rem_w[1*4+:4]+:i12_w] = {(i12_w){1'b0}}; + end + end + end + 3'b010:begin + if(viv_s8==1'b1) begin + viv_s29[i12_rem_w[2*4+:4]-1:0] = viv_s17[raw_width-1-:i12_rem_w[2*4+:4]]; + end + else begin + viv_s29[i12_rem_w[2*4+:4]-1:0] = viv_s30[i12_rem_w[2*4+:4]-1:0]; + end + for(i=0;i<11;i=i+1)begin + if(viv_s18==i && viv_s13 )begin + viv_s29[i*i12_w+i12_rem_w[2*4+:4]+:i12_w] = in_raw[raw_width-1-:i12_w]; + `ifdef DEBUG + $display($realtime,,"if1: the current viv_s18 =%h, i=%h, in_raw[raw_width-1-:i12_w]=%h", viv_s18, i, in_raw[raw_width-1-:i12_w]); + $display($realtime,,"viv_s29[%h*i12_w+i12_rem_w[2*4+:4]+:i12_w]=%h",i,viv_s29[i*i12_w+i12_rem_w[2*4+:4]+:i12_w]); + $display($realtime,,"viv_s29=%h",viv_s29); + infocnt++; + `endif + end + else if(viv_s8==1'b1)begin + viv_s29[i*i12_w+i12_rem_w[2*4+:4]+:i12_w] = {(i12_w){1'b0}}; + `ifdef DEBUG + $display($realtime,,"if2: the current viv_s18 =%h, i=%h, in_raw[raw_width-1-:i12_w]=%h", viv_s18, i, in_raw[raw_width-1-:i12_w]); + $display($realtime,,"viv_s29[%h*i12_w+i12_rem_w[2*4+:4]+:i12_w]=%h",i,viv_s29[i*i12_w+i12_rem_w[2*4+:4]+:i12_w]); + $display($realtime,,"viv_s29=%h",viv_s29); + infocnt++; + `endif + end + end + end + default:; + endcase + format_cfg[r14i*fmtw+:fmtw]: + case(viv_s21) + 3'd0:begin + for(i=0;i<10;i=i+1)begin + if(viv_s18==i && viv_s13 )begin + viv_s29[i*i14_w+i14_rem_w[0*4+:4]+:i14_w] = in_raw[raw_width-1-:i14_w]; + end + else if(viv_s8==1'b1)begin + viv_s29[i*i14_w+i14_rem_w[0*4+:4]+:i14_w] = {(i14_w){rpadpseud}}; + end + end + end + 3'd1:begin + if(viv_s8==1'b1)begin + viv_s29[i14_rem_w[1*4+:4]-1:0] = viv_s17[raw_width-1-:i14_rem_w[1*4+:4]]; + end + else begin + viv_s29[i14_rem_w[1*4+:4]-1:0] = viv_s30[i14_rem_w[1*4+:4]-1:0]; + end + for(i=0;i<9;i=i+1)begin + if(viv_s18==i && viv_s13 )begin + viv_s29[i*i14_w+i14_rem_w[1*4+:4]+:i14_w] = in_raw[raw_width-1-:i14_w]; + end + else if(viv_s8==1'b1)begin + viv_s29[i*i14_w+i14_rem_w[1*4+:4]+:i14_w] = {(i14_w){rpadpseud}}; + end + end + end + 3'd2:begin + if(viv_s8==1'b1)begin + viv_s29[i14_rem_w[2*4+:4]-1:0] = viv_s17[raw_width-1-:i14_rem_w[2*4+:4]]; + end + else begin + viv_s29[i14_rem_w[2*4+:4]-1:0] = viv_s30[i14_rem_w[2*4+:4]-1:0]; + end + for(i=0;i<9;i=i+1)begin + if(viv_s18==i && viv_s13 )begin + viv_s29[i*i14_w+i14_rem_w[2*4+:4]+:i14_w] = in_raw[raw_width-1-:i14_w]; + end + else if(viv_s8==1'b1)begin + viv_s29[i*i14_w+i14_rem_w[2*4+:4]+:i14_w] = {(i14_w){rpadpseud}}; + end + end + end + 3'd3:begin + if(viv_s8==1'b1)begin + viv_s29[i14_rem_w[3*4+:4]-1:0] = viv_s17[raw_width-1-:i14_rem_w[3*4+:4]]; + end + else begin + viv_s29[i14_rem_w[3*4+:4]-1:0] = viv_s30[i14_rem_w[3*4+:4]-1:0]; + end + for(i=0;i<9;i=i+1)begin + if(viv_s18==i && viv_s13 )begin + viv_s29[i*i14_w+i14_rem_w[3*4+:4]+:i14_w] = in_raw[raw_width-1-:i14_w]; + end + else if(viv_s8==1'b1)begin + viv_s29[i*i14_w+i14_rem_w[3*4+:4]+:i14_w] = {(i14_w){rpadpseud}}; + end + end + end + 3'd4:begin + if(viv_s8==1'b1)begin + viv_s29[i14_rem_w[4*4+:4]-1:0] = viv_s17[raw_width-1-:i14_rem_w[4*4+:4]]; + end + else begin + viv_s29[i14_rem_w[4*4+:4]-1:0] = viv_s30[i14_rem_w[4*4+:4]-1:0]; + end + for(i=0;i<9;i=i+1)begin + if(viv_s18==i && viv_s13 )begin + viv_s29[i*i14_w+i14_rem_w[4*4+:4]+:i14_w] = in_raw[raw_width-1-:i14_w]; + end + else if(viv_s8==1'b1)begin + viv_s29[i*i14_w+i14_rem_w[4*4+:4]+:i14_w] = {(i14_w){rpadpseud}}; + end + end + end + 3'd5:begin + if(viv_s8==1'b1)begin + viv_s29[i14_rem_w[5*4+:4]-1:0] = viv_s17[raw_width-1-:i14_rem_w[5*4+:4]]; + end + else begin + viv_s29[i14_rem_w[5*4+:4]-1:0] = viv_s30[i14_rem_w[5*4+:4]-1:0]; + end + for(i=0;i<9;i=i+1)begin + if(viv_s18==i && viv_s13 )begin + viv_s29[i*i14_w+i14_rem_w[5*4+:4]+:i14_w] = in_raw[raw_width-1-:i14_w]; + end + else if(viv_s8==1'b1)begin + viv_s29[i*i14_w+i14_rem_w[5*4+:4]+:i14_w] = {(i14_w){rpadpseud}}; + end + end + end + 3'd6:begin + if(viv_s8==1'b1)begin + viv_s29[i14_rem_w[6*4+:4]-1:0] = viv_s17[raw_width-1-:i14_rem_w[6*4+:4]]; + end + else begin + viv_s29[i14_rem_w[6*4+:4]-1:0] = viv_s30[i14_rem_w[6*4+:4]-1:0]; + end + for(i=0;i<9;i=i+1)begin + if(viv_s18==i && viv_s13 )begin + viv_s29[i*i14_w+i14_rem_w[6*4+:4]+:i14_w] = in_raw[raw_width-1-:i14_w]; + end + else if(viv_s8==1'b1)begin + viv_s29[i*i14_w+i14_rem_w[6*4+:4]+:i14_w] = {(i14_w){rpadpseud}}; + end + end + end + default:begin + viv_s29 = viv_s30; + end + endcase + format_cfg[r16i*fmtw+:fmtw]:begin + for(i=0;i<8;i=i+1)begin + if(viv_s18==i && viv_s13 )begin + viv_s29[i*i16_w+:i16_w]=in_raw[raw_width-1-:i16_w]; + end + else if(viv_s8==1'b1)begin + viv_s29[i*i16_w+:i16_w]={(i16_w){rpadpseud}}; + end + end + end + format_cfg[r10ahi*fmtw+:fmtw],format_cfg[r12ahi*fmtw+:fmtw],format_cfg[r14ahi*fmtw+:fmtw]:begin + for(i=0;i<8;i=i+1)begin + if(viv_s18==i && viv_s13 )begin + viv_s29[i*i16_w+:i16_w]=viv_s24; + end + else if(viv_s8==1'b1)begin + viv_s29[i*i16_w+:i16_w]={(i16_w){rpadpseud}}; + end + end + end + format_cfg[r10ai*fmtw+:fmtw]:begin + for(i=0;i<12;i=i+1)begin + if(viv_s18==i && viv_s13 )begin + viv_s29[i*i10_w+(i/3)*2+:i10_w] = in_raw[raw_width-1-:i10_w]; + end + else if(viv_s8==1'b1) begin + viv_s29[i*i10_w+(i/3)*2+:i10_w] = {(i10_w){rpadpseud}}; + end + end + end + format_cfg[r12ai*fmtw+:fmtw]:begin + for(i=0;i<10;i=i+1)begin + if(viv_s18==i && viv_s13)begin + viv_s29[i*i12_w+(i/5)*4+:i12_w] = in_raw[raw_width-1-:i12_w]; + end + else if(viv_s8 == 1'b1)begin + viv_s29[i*i12_w+(i/5)*4+:i12_w] = {(i12_w){rpadpseud}}; + end + end + end + format_cfg[r14ai*fmtw+:fmtw]:begin + for(i=0;i<9;i=i+1)begin + if(viv_s18==i && viv_s13)begin + viv_s29[i*i14_w+:i14_w] = in_raw[raw_width-1-:i14_w]; + end + else if(viv_s8==1'b1)begin + viv_s29[i*i14_w+:i14_w] = {(i14_w){rpadpseud}}; + end + end + end + default:; + endcase +end +always @(posedge clk or negedge reset_n)begin + if(!reset_n)begin + viv_s30[pack_width-1+i14_w:pack_width]<={(i14_w){1'b0}}; + viv_s30[pack_width-1:0]<={(pack_width){1'b0}}; + viv_s18 <= 4'b0; + viv_s21 <= 3'b0; + viv_s7 <= 2'b0; + end + else begin + viv_s30[pack_width-1+i14_w:pack_width]<={(i14_w){1'b0}}; + viv_s30[pack_width-1:0]<=viv_s29[pack_width-1:0]; + viv_s18 <= viv_s19; + viv_s21 <= viv_s22; + viv_s7 <= viv_s10; + end +end +reg viv_s31; +always @(posedge clk or negedge reset_n) begin + if (~reset_n) begin + cfg_in_update <= 1'b0; + end + else if (soft_rst) begin + cfg_in_update <= 1'b0; + end + else begin + cfg_in_update <= viv_s31; + end +end +always @(posedge clk or negedge reset_n) begin + if (~reset_n) begin + viv_s31 <= 1'b0; + end + else if (soft_rst) begin + viv_s31 <= 1'b0; + end + else begin + if(out_val & viv_s5 & out_v_end & out_h_end & (out_cfg_upd | auto_update)) + viv_s31 <= 1'b1; + else if (cfg_out_update)begin + viv_s31 <= 1'b0; + end + end +end +assign out_val = viv_s9 & viv_s5; +assign out_h_end = viv_s15 && viv_s7[1]!=1'b1; +assign out_raw = viv_s30; +assign in_ack = viv_s7[1:0]==2'b00 || (~viv_s7[1]&viv_s5); +assign out_v_end = (viv_s16&& out_h_end); +assign out_cfg_upd = 1'b0; +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_mi_fifo_core.v b/ispyocto/rtl/ispyocto/vsisp_mi_fifo_core.v new file mode 100644 index 0000000..0e8a49d --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_mi_fifo_core.v
@@ -0,0 +1,197 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_mi_fifo_core + ( + wr_clk, + wr_reset_n, + rd_clk, + rd_reset_n, + rotation, + wr_en, + wdata, + wr_h_end, + wr_v_end, + fifo_full, + rd_en, + rdata, + rd_h_end, + rd_v_end, + fifo_empty, + fifo_fill_level, + fifo_flush + ); + parameter c_fifo_depth = 8; + parameter c_data_width = 64; + parameter c_depth_burst_ratio = 2; + parameter c_addr_width = (c_fifo_depth <= 1) ? 0 : + (c_fifo_depth <= 2) ? 1 : + (c_fifo_depth <= 4) ? 2 : + (c_fifo_depth <= 8) ? 3 : + (c_fifo_depth <= 16) ? 4 : + (c_fifo_depth <= 32) ? 5 : + (c_fifo_depth <= 64) ? 6 : + (c_fifo_depth <= 128) ? 7 : 8; + input wr_clk; + input wr_reset_n; + input rd_clk; + input rd_reset_n; + input rotation; + input [c_data_width-1:0] wdata; + input wr_en; + input wr_h_end; + input wr_v_end; + output fifo_full; + wire fifo_full; + input rd_en; + output [c_data_width-1:0] rdata; + wire [c_data_width-1:0] rdata; + output rd_h_end; + wire rd_h_end; + output rd_v_end; + wire rd_v_end; + output fifo_empty; + wire fifo_empty; + output [c_addr_width:0] fifo_fill_level; + reg [c_addr_width:0] fifo_fill_level; + output fifo_flush; + reg fifo_flush; + function [c_addr_width:0] f_bin2gray; + input [c_addr_width:0] viv_s0; + begin + f_bin2gray = viv_s0 ^ {1'b0, viv_s0[c_addr_width:1]}; + end + endfunction + function [c_addr_width:0] f_gray2bin; + input [c_addr_width:0] gray_value; + reg [c_addr_width:0] viv_s0; + integer v_bitpos; + begin + viv_s0 = {gray_value[c_addr_width], {c_addr_width{1'b0}}}; + for (v_bitpos =c_addr_width - 1; v_bitpos >= 0;v_bitpos = v_bitpos - 1) + viv_s0[v_bitpos] = gray_value[v_bitpos] ^ viv_s0[v_bitpos + 1]; + f_gray2bin = viv_s0; + end + endfunction + reg [c_data_width-1:0] fifo_data[c_fifo_depth-1:0]; + reg [c_fifo_depth-1:0] viv_s1; + reg [c_fifo_depth-1:0] viv_s2; + wire [c_addr_width:0] viv_s3; + wire [c_addr_width:0] viv_s4; + reg [c_addr_width:0] viv_s5; + reg [c_addr_width:0] viv_s6; + reg [c_addr_width:0] viv_s7; + wire [c_addr_width:0] viv_s8; + wire [c_addr_width:0] viv_s9; + reg [c_addr_width:0] viv_s10; + reg [c_addr_width:0] viv_s11; + reg [c_addr_width:0] viv_s12; + wire [c_addr_width:0] viv_s13; + integer v_loop1; + integer v_loop2; + always @(posedge wr_clk or negedge wr_reset_n) + begin + if (~wr_reset_n) begin + for(v_loop1 = 0; v_loop1 < c_fifo_depth; v_loop1 = v_loop1 + 1) begin + fifo_data [v_loop1] <= {c_data_width{1'b0}} ; + viv_s1[v_loop1] <= 1'b0; + viv_s2[v_loop1] <= 1'b0; + end + end + else begin + if (wr_en) begin + fifo_data [viv_s3[c_addr_width-1:0]] <= wdata; + viv_s1[viv_s3[c_addr_width-1:0]] <= wr_h_end; + viv_s2[viv_s3[c_addr_width-1:0]] <= wr_v_end; + end + end + end + always @(posedge wr_clk or negedge wr_reset_n) + begin + if (~wr_reset_n) begin + viv_s5 <= {c_addr_width+1{1'b0}}; + end + else begin + if (wr_en) begin + viv_s5 <= f_bin2gray(viv_s3 + 1'b1); + end + end + end + assign viv_s3 = f_gray2bin(viv_s5); + always @(posedge rd_clk or negedge rd_reset_n) + begin + if (~rd_reset_n) begin + viv_s6 <= {c_addr_width+1{1'b0}}; + viv_s7 <= {c_addr_width+1{1'b0}}; + end + else begin + viv_s6 <= viv_s5; + viv_s7 <= viv_s6; + end + end + assign viv_s4 = f_gray2bin(viv_s7); + assign fifo_full = (viv_s3[c_addr_width] != viv_s9[c_addr_width]) + & (viv_s3[c_addr_width-1:0] == viv_s9[c_addr_width-1:0]); + assign rdata = fifo_data [viv_s8[c_addr_width-1:0]]; + assign rd_h_end = viv_s1[viv_s8[c_addr_width-1:0]] && !fifo_empty; + assign rd_v_end = viv_s2[viv_s8[c_addr_width-1:0]] && !fifo_empty; + always @(posedge rd_clk or negedge rd_reset_n) + begin + if (~rd_reset_n) begin + viv_s10 <= {c_addr_width+1{1'b0}}; + end + else begin + if (rd_en) begin + viv_s10 <= f_bin2gray(viv_s8 + 1'b1); + end + end + end + assign viv_s8 = f_gray2bin(viv_s10); + always @(posedge wr_clk or negedge wr_reset_n) + begin + if (~wr_reset_n) begin + viv_s11 <= {c_addr_width+1{1'b0}}; + viv_s12 <= {c_addr_width+1{1'b0}}; + end + else begin + viv_s11 <= viv_s10; + viv_s12 <= viv_s11; + end + end + assign viv_s9 = f_gray2bin(viv_s12); + assign fifo_empty = (viv_s4 == viv_s8); + assign viv_s13 = viv_s4 - viv_s8; + always @(*) + begin + fifo_fill_level = viv_s13; + fifo_flush = 1'b0; + for (v_loop2 = (c_fifo_depth / c_depth_burst_ratio) - 1; v_loop2 >= 0; v_loop2 = v_loop2 - 1) + if ((viv_s13 > v_loop2) && + ( viv_s1[(viv_s8[c_addr_width-1:0] + v_loop2) & {c_addr_width{1'b1}}] | + (viv_s2[(viv_s8[c_addr_width-1:0] + v_loop2) & {c_addr_width{1'b1}}] && rotation) ) ) + begin + fifo_fill_level = v_loop2 + 1; + fifo_flush = 1'b1; + end + end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_mi_fifo_ram.v b/ispyocto/rtl/ispyocto/vsisp_mi_fifo_ram.v new file mode 100644 index 0000000..608664a --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_mi_fifo_ram.v
@@ -0,0 +1,379 @@ +//**************************************************************************** +// +// Copyright 2023 Vivante Corp. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_mi_fifo_ram( + clk, + resetn, + fifo_synch_reset, + sw_fifo_depth_ctrl, + fifo_write_e_lz, + fifo_write_data, + fifo_read_e_lz, + fifo_validread_am, + fifo_validwrite_vz, + fifo_validread_vz, + fifo_read_data, + fifo_sram_buf_full, + fifo_sram_DIN, + fifo_sram_DOUT, + fifo_sram_ADDR, + fifo_sram_CEN, + fifo_sram_WEN); + parameter FIFO_DATA_WIDTH = 16; + parameter FIFO_DEPTH = 4; + parameter SRAM_ADDRWIDTH = 4; + parameter FIFO_SRAM_REGS = 3; + parameter FIFO_DESCRIPTION = "default_name"; + integer i; + parameter FIFO_IDLE = 2'b00; + parameter FIFO_TO_REG = 2'b01; + parameter FIFO_TO_SRAM = 2'b10; + input clk; + input resetn; + input fifo_synch_reset; + input [1:0] sw_fifo_depth_ctrl; + input fifo_write_e_lz; + input [FIFO_DATA_WIDTH-1:0] fifo_write_data; + input fifo_read_e_lz; + output [SRAM_ADDRWIDTH:0] fifo_validread_am; + output fifo_validwrite_vz; + output fifo_validread_vz; + output [FIFO_DATA_WIDTH-1:0] fifo_read_data; + output fifo_sram_buf_full; + input [FIFO_DATA_WIDTH-1:0] fifo_sram_DIN; + output [FIFO_DATA_WIDTH-1:0] fifo_sram_DOUT; + output [SRAM_ADDRWIDTH-1:0] fifo_sram_ADDR; + output fifo_sram_CEN; + output fifo_sram_WEN; + reg [SRAM_ADDRWIDTH:0] viv_s0; + wire fifo_validwrite_vz; + wire fifo_validread_vz; + wire [FIFO_DATA_WIDTH-1:0] fifo_read_data; + wire [FIFO_DATA_WIDTH-1:0] fifo_sram_DOUT; + wire [SRAM_ADDRWIDTH-1:0] fifo_sram_ADDR; + wire fifo_sram_CEN; + wire fifo_sram_WEN; +//synopsys translate_off +parameter FIFO_FULL_PRINT_THRESHOLD_CYCLES = 15000; +parameter FIFO_EMPTY_PRINT_THRESHOLD_CYCLES = 15000; +integer fifo_full_count; +integer fifo_empty_count; +integer fifo_report_on_stuck_proc_print_once; +integer fifo_report_empty_stuck_proc_print_once; +reg [SRAM_ADDRWIDTH:0] viv_s1; +always @(negedge resetn or posedge clk) +begin + if (resetn == 1'b 0) + viv_s1 <= 0; + else if(viv_s0 > viv_s1) + viv_s1 <= viv_s0; +end +//synopsys translate_on + reg [FIFO_DATA_WIDTH-1:0] reg_data_array[FIFO_SRAM_REGS-1:0]; + reg [FIFO_DATA_WIDTH-1:0] viv_s2; + reg [SRAM_ADDRWIDTH-1:0] viv_s3; + reg [SRAM_ADDRWIDTH-1:0] viv_s4; + integer sram_buf_addr; + integer reg_rd_ptr; + integer reg_wr_ptr; + integer reg_buf_addr; + wire [SRAM_ADDRWIDTH:0] viv_s5; + wire [SRAM_ADDRWIDTH:0] viv_s6; + reg [1:0] viv_s7,viv_s8; + reg viv_s9; + reg viv_s10; + reg viv_s11; + reg viv_s12; + reg viv_s13; + reg viv_s14; + reg viv_s15; + reg viv_s16; + reg viv_s17; + reg viv_s18; + reg viv_s19; + reg viv_s20; + reg viv_s21; + reg viv_s22; + wire viv_s23; + wire viv_s24; + wire viv_s25; + wire viv_s26 ; + wire viv_s27; + wire viv_s28 ; + wire viv_s29 ; + wire viv_s30 ; + assign viv_s5 = (sw_fifo_depth_ctrl == 2'b00) ? (FIFO_DEPTH ) : + (sw_fifo_depth_ctrl == 2'b01) ? (FIFO_DEPTH >> 1) : + (sw_fifo_depth_ctrl == 2'b10) ? (FIFO_DEPTH >> 2) : + (sw_fifo_depth_ctrl == 2'b11) ? (FIFO_DEPTH >> 3) : FIFO_DEPTH; + assign viv_s6 = viv_s5 - 1'b1; + assign fifo_validwrite_vz = viv_s30; + assign fifo_validread_vz = viv_s29; + assign fifo_validread_am = viv_s0; + assign fifo_sram_WEN = viv_s18 ; + assign fifo_sram_CEN = viv_s19 ; + assign fifo_sram_ADDR = (viv_s20 == 1'b1) ? viv_s4 : + (viv_s21 == 1'b1) ? viv_s3 : 0 ; + assign fifo_sram_DOUT = viv_s2; + assign fifo_read_data = reg_data_array[reg_rd_ptr]; + assign viv_s25 = (reg_buf_addr == 0 ) ? 1 : 0; + assign viv_s26 = (reg_buf_addr == FIFO_SRAM_REGS) ? 1 : 0; + assign viv_s27 = (sram_buf_addr == 0 ) ? 1 : 0; + assign viv_s28 = (sram_buf_addr == viv_s5 ) ? 1 : 0; + assign fifo_sram_buf_full = viv_s28; + assign viv_s29 = (viv_s25)? 0 : 1; + assign viv_s30 = (viv_s28 | (viv_s23 & (viv_s7 == FIFO_TO_SRAM)) + | (viv_s23 & viv_s26 & viv_s27) | viv_s9) ? 0 : 1; + assign viv_s23 = fifo_read_e_lz & viv_s29; + assign viv_s24 = fifo_write_e_lz & viv_s30; + always @(*) + begin + viv_s8 = viv_s7; + viv_s16 = viv_s23; + viv_s17 = 0; + viv_s13 = 0; + viv_s14 = 0; + viv_s12 = 0; + viv_s11 = 1; + viv_s10 = 1; + viv_s15 = 0; + case(viv_s7) + FIFO_IDLE: + if(viv_s24 == 1 && viv_s27 == 1 && viv_s25 == 1) + begin + viv_s17 = 1; + viv_s8 = FIFO_TO_REG; + end + FIFO_TO_REG: + if(viv_s24 == 1) + if(viv_s26==0) + viv_s17 = 1; + else + begin + viv_s13 = 1; + viv_s11 = 0; + viv_s10 = 0; + viv_s8 = FIFO_TO_SRAM; + end + else if(viv_s27 == 1 && viv_s25 == 1) + viv_s8 = FIFO_IDLE; + FIFO_TO_SRAM: + begin + if(viv_s23 == 1) + viv_s15 = 1; + if((viv_s24 == 1) && (viv_s28 == 0 && viv_s23 == 0)) + begin + viv_s13 = 1; + viv_s11 = 0; + viv_s10 = 0; + end + if(viv_s23 == 1 && viv_s27 == 0) + begin + viv_s12 = 1; + viv_s11 = 0; + end + if(viv_s20 == 1) + viv_s14 = 1; + if((viv_s27 == 1) && (viv_s24 == 0)) + begin + if(viv_s25 == 1) + viv_s8 = FIFO_IDLE; + else if((viv_s22 == 1)&&(viv_s20 == 0)) + viv_s8 = FIFO_TO_REG; + end + end + default: viv_s8 = FIFO_IDLE; + endcase + end + always @ (posedge clk or negedge resetn) + if(resetn == 1'b0) + begin + viv_s7 <= FIFO_IDLE; + viv_s18 <= 1; + viv_s19 <= 1; + viv_s20 <= 0; + viv_s21 <= 0; + viv_s22 <= 0; + viv_s9 <= 0; + end + else if(fifo_synch_reset == 1'b0) + begin + viv_s7 <= FIFO_IDLE; + viv_s18 <= 1; + viv_s19 <= 1; + viv_s20 <= 0; + viv_s21 <= 0; + viv_s22 <= 0; + viv_s9 <= 0; + end + else + begin + viv_s7 <= viv_s8; + viv_s18 <= viv_s10; + viv_s19 <= viv_s11; + viv_s20 <= viv_s12; + viv_s21 <= viv_s13; + viv_s22 <= viv_s14; + viv_s9 <= viv_s15; + end + always @ (posedge clk or negedge resetn) + begin + if(resetn == 1'b0) + viv_s0 <= 0; + else if(fifo_synch_reset == 1'b0) + viv_s0 <= 0; + else if(viv_s16 == 1 && (viv_s17 == 1 || viv_s13 == 1)) + viv_s0 <= viv_s0; + else if(viv_s16 == 0 && (viv_s17 == 1 || viv_s13 == 1)) + viv_s0 <= viv_s0 + 1; + else if(viv_s16 == 1 && viv_s17 == 0 && viv_s13 == 0) + viv_s0 <= viv_s0 - 1; + end + always @ (posedge clk or negedge resetn) + begin + if(resetn == 1'b0) + viv_s3 <= 0; + else if(fifo_synch_reset == 1'b0) + viv_s3 <= 0; + else if(viv_s21 == 1'b1) + begin + if(viv_s3 == viv_s6) + viv_s3 <= 0; + else + viv_s3 <= viv_s3 + 1'b1; + end + end + always @ (posedge clk or negedge resetn) + begin + if(resetn == 1'b0) + viv_s4 <= 0; + else if(fifo_synch_reset == 1'b0) + viv_s4 <= 0; + else if(viv_s20 == 1'b1) + begin + if(viv_s4 == viv_s6) + viv_s4 <= 0; + else + viv_s4 <= viv_s4 + 1'b1; + end + end + always @ (posedge clk or negedge resetn) + begin + if(resetn == 1'b0) + for(i = 0;i < FIFO_SRAM_REGS;i=i+1) + reg_data_array[i] <= 0; + else if(fifo_synch_reset == 1'b0) + for(i = 0;i < FIFO_SRAM_REGS;i=i+1) + reg_data_array[i] <= 0; + else if(viv_s17) + reg_data_array[reg_wr_ptr] <= fifo_write_data; + else if(viv_s22) + reg_data_array[reg_wr_ptr] <= fifo_sram_DIN; + end + always @ (posedge clk or negedge resetn) + begin + if(resetn == 1'b0) + viv_s2 <= 0; + else if(fifo_synch_reset == 1'b0) + viv_s2 <= 0; + else + if(viv_s13) viv_s2 <= fifo_write_data; + end + always @ (posedge clk or negedge resetn) + begin + if(resetn == 1'b0) + reg_wr_ptr <= 0; + else if(fifo_synch_reset == 1'b0) + reg_wr_ptr <= 0; + else + if(viv_s17 == 1'b1 || viv_s22 == 1'b1) + if(reg_wr_ptr == FIFO_SRAM_REGS-1) + reg_wr_ptr <= 0; + else + reg_wr_ptr <= reg_wr_ptr + 1; + end + always @ (posedge clk or negedge resetn) + begin + if(resetn == 1'b0) + reg_rd_ptr <= 0; + else if(fifo_synch_reset == 1'b0) + reg_rd_ptr <= 0; + else + if(viv_s16 == 1'b1 ) + if(reg_rd_ptr == FIFO_SRAM_REGS-1) + reg_rd_ptr <= 0; + else if(viv_s25 == 0) + reg_rd_ptr <= reg_rd_ptr + 1; + end + always @ (posedge clk or negedge resetn) + begin + if(resetn == 1'b0) + sram_buf_addr <= 0; + else if(fifo_synch_reset == 1'b0) + sram_buf_addr <= 0; + else if(viv_s12 == 1'b0 && viv_s13 == 1'b1) + sram_buf_addr <= sram_buf_addr + 1; + else if(viv_s12 == 1'b1 && viv_s13 == 1'b0) + sram_buf_addr <= sram_buf_addr - 1; + end + always @ (posedge clk or negedge resetn) + begin + if(resetn == 1'b0) + reg_buf_addr <= 0; + else if(fifo_synch_reset == 1'b0) + reg_buf_addr <= 0; + else if(viv_s16 == 1 && (viv_s17 == 1 || viv_s22 == 1)) + reg_buf_addr <= reg_buf_addr; + else if(viv_s16 == 0 && (viv_s17 == 1 || viv_s22 == 1)) + reg_buf_addr <= reg_buf_addr + 1; + else if(viv_s16 == 1 && viv_s17 == 0 && viv_s22 == 0) + reg_buf_addr <= reg_buf_addr - 1; + end +//synopsys translate_off +always @(negedge resetn or posedge clk) + begin : count_jamming_cycles_proc + if (resetn == 1'b 0) + begin + fifo_full_count <= 0; + fifo_empty_count <= 0; + end + else + begin + if (fifo_write_e_lz == 1'b 1 & viv_s30 == 1'b 0) + begin + fifo_full_count <= fifo_full_count + 1'b 1; + end + else + begin + fifo_full_count <= 0; + end + if (fifo_read_e_lz == 1'b 1 & viv_s29 == 1'b 0) + begin + fifo_empty_count <= fifo_empty_count + 1'b 1; + end + else + begin + fifo_empty_count <= 0; + end + end + end +//synopsys translate_on +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_mi_jpeg_ctrl.v b/ispyocto/rtl/ispyocto/vsisp_mi_jpeg_ctrl.v new file mode 100644 index 0000000..637ba35 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_mi_jpeg_ctrl.v
@@ -0,0 +1,125 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_mi_jpeg_ctrl + ( + clk, + reset_clk_n, + paddr, + pwdata, + prdata, + pval, + prd, + pack, + cfg_addr, + cfg_wdata, + cfg_rd, + cfg_rdata, + cfg_val, + cfg_ack, + clk_cfg, + clk_en, + test_mode + ); + parameter c_mod_addr0 = 12'he00; + parameter c_mod_addr1 = 12'hfec; +`include "vsisp_marvin_ctrl.vh" + input clk; + input reset_clk_n; + input [c_paddr_word-1:0] paddr; + input [c_pwdata_word-1:0] pwdata; + output [c_prdata_word-1:0] prdata; + input pval; + input prd; + output pack; + output [c_cfg_addr_word-1:0] cfg_addr; + output [c_cfg_wdata_word-1:0] cfg_wdata; + output cfg_rd; + input [c_cfg_rdata32_word-1:0] cfg_rdata; + output cfg_val; + input cfg_ack; + input clk_en; + output clk_cfg; + input test_mode; + reg viv_s0; + reg viv_s1; + reg viv_s2; + reg [c_cfg_wdata_word-1:0] cfg_wdata; + reg cfg_rd; + reg [c_cfg_addr_word-1:0] cfg_addr; + reg viv_s3; + wire [c_prdata_word-1:0] prdata; + wire pack; + wire viv_s4; + wire viv_s5; + always @(posedge clk or negedge reset_clk_n) begin + if (!reset_clk_n) begin + viv_s0 <= 1'b0; + viv_s1 <= 1'b0; + viv_s2 <= 1'b0; + cfg_wdata <= {c_cfg_wdata_word{1'b0}}; + cfg_rd <= 1'b0; + cfg_addr <= {c_paddr_word{1'b0}}; + end + else begin + viv_s0 <= pval; + viv_s1 <= viv_s0; + viv_s2 <= viv_s1; + cfg_wdata <= pwdata[c_cfg_wdata_word-1:0]; + cfg_rd <= prd; + cfg_addr <= paddr[c_paddr_word-1:0]; + end + end + always @(posedge clk or negedge reset_clk_n) begin + if (!reset_clk_n) begin + viv_s3 <= 1'b0; + end + else begin + if (viv_s3) begin + viv_s3 <= 1'b0; + end + else begin + if (paddr[11:0] >= c_mod_addr0 && paddr[11:0] <= c_mod_addr1 ) begin + if (pval) begin + if (!clk_en) begin + viv_s3 <= 1'b1; + end + end + end + end + end + end + assign viv_s4 = pval || viv_s0 || viv_s1 || viv_s2; + assign viv_s5 = ((paddr[11:0] >= c_mod_addr0 && paddr[11:0] <= c_mod_addr1) && + (viv_s4) && clk_en) ? 1'b1 : 1'b0; + vsisp_m4_clock_gating u_cfg_clock_gating_share + ( + .per_clk_i (clk), + .pdft_scan_mode_i (test_mode), + .gating_en_i (viv_s5), + .clk_o (clk_cfg) + ); + assign pack = (viv_s3 || cfg_ack) ? 1'b1: 1'b0; + assign prdata = (viv_s3) ? c_prdata_ctrl_off : cfg_rdata; + assign cfg_val = pval && clk_en; +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_pvci_mux.v b/ispyocto/rtl/ispyocto/vsisp_pvci_mux.v new file mode 100644 index 0000000..2b5b3bc --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_pvci_mux.v
@@ -0,0 +1,74 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_pvci_mux ( + paddr, + hval, + hack, + hrdata, + val_all, + ack_all, + rdata_all, + val_mi, + ack_mi, + rdata_mi + ); + parameter g_data_width = 32; + parameter c_paddr_word = 12; + parameter isp_end_addr = 12'he00; + parameter mi_end_addr = 12'hff0; + input [c_paddr_word-1:0] paddr; + input hval; + output hack; + output [g_data_width-1:0] hrdata; + output val_all; + input ack_all; + input [g_data_width-1:0] rdata_all; + output val_mi; + input ack_mi; + input [g_data_width-1:0] rdata_mi; + reg hack; + reg [g_data_width-1:0] hrdata; + reg val_all; + reg val_mi; + always @(*) begin + val_all = 1'b0; + val_mi = 1'b0; + hrdata = 32'd0; + hack = 1'b1; + if (paddr[11:0] < isp_end_addr) begin + val_all = hval; + hrdata = rdata_all; + hack = ack_all; + end else if (paddr[11:0] < mi_end_addr) begin + val_mi = hval; + hrdata = rdata_mi; + hack = ack_mi; + end else begin + val_all = 1'b0; + val_mi = 1'b0; + hrdata = 32'd0; + hack = 1'b1; + end + end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_pvci_sync.v b/ispyocto/rtl/ispyocto/vsisp_pvci_sync.v new file mode 100644 index 0000000..9f7897b --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_pvci_sync.v
@@ -0,0 +1,152 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_pvci_sync ( + hclk, + hreset_n, + clk, + reset_clk_n, + hval, + hack, + hrdata, + val, + ack, + rdata); + parameter g_data_width = 32; + parameter c_h_reset = 2'd0; + parameter c_h_wait_val = 2'd1; + parameter c_h_wait_ack = 2'd2; + parameter c_h_wait_nack = 2'd3; + parameter c_s_reset = 2'd0; + parameter c_s_wait_val = 2'd1; + parameter c_s_wait_ack = 2'd3; + parameter c_s_wait_nval = 2'd2; + input hclk; + input hreset_n; + input clk; + input reset_clk_n; + input hval; + output hack; + output [g_data_width-1:0] hrdata; + output val; + input ack; + input [g_data_width-1:0] rdata; + reg [1:0] viv_s0; + reg [1:0] viv_s1; + reg [g_data_width-1:0] viv_s2; + wire viv_s3; + wire viv_s4; + reg viv_s5; + reg viv_s6; + reg viv_s7; + reg viv_s8; + wire viv_s9; + assign viv_s3 = ((viv_s0 == c_h_wait_val) && hval) || + ((viv_s0 == c_h_wait_ack) && (!viv_s6)); + assign hrdata = viv_s2; + assign hack = ((viv_s0 == c_h_wait_ack) && viv_s6); + assign viv_s9 = (!viv_s6); + always @(posedge hclk or negedge hreset_n) begin + if (hreset_n == 1'b0) begin + viv_s5 <= 1'b0; + viv_s6 <= 1'b0; + end + else begin + viv_s5 <= viv_s4; + viv_s6 <= viv_s5; + end + end + always @(posedge hclk or negedge hreset_n) begin + if (hreset_n == 1'b0) begin + viv_s0 <= c_h_reset; + end + else begin + case (viv_s0) + c_h_reset: begin + viv_s0 <= c_h_wait_val; + end + c_h_wait_val: begin + if (hval) begin + viv_s0 <= c_h_wait_ack; + end + end + c_h_wait_ack: begin + if (~hval) begin + viv_s0 <= c_h_wait_val; + end + else begin + if (viv_s6) begin + viv_s0 <= c_h_wait_nack; + end + end + end + default: begin + if (viv_s9) begin + viv_s0 <= c_h_wait_val; + end + end + endcase + end + end + assign val = (viv_s1 == c_s_wait_ack) || ((viv_s1 == c_s_wait_val) && viv_s8); + assign viv_s4 = ((viv_s1 == c_s_wait_nval) && viv_s8); + always @(posedge clk or negedge reset_clk_n) begin + if (reset_clk_n == 1'b0) begin + viv_s7 <= 1'b0; + viv_s8 <= 1'b0; + end + else begin + viv_s7 <= viv_s3; + viv_s8 <= viv_s7; + end + end + always @(posedge clk or negedge reset_clk_n) begin + if (reset_clk_n == 1'b0) begin + viv_s1 <= c_s_reset; + viv_s2 <= {g_data_width{1'b0}}; + end + else begin + case (viv_s1) + c_s_reset: begin + viv_s1 <= c_s_wait_val; + end + c_s_wait_val: begin + if (viv_s8) begin + viv_s1 <= c_s_wait_ack; + end + end + c_s_wait_ack: begin + if (ack) begin + viv_s1 <= c_s_wait_nval; + viv_s2 <= rdata; + end + end + default: begin + if (!viv_s8) begin + viv_s1 <= c_s_wait_val; + end + end + endcase + end + end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_resize_conv.v b/ispyocto/rtl/ispyocto/vsisp_resize_conv.v new file mode 100644 index 0000000..af5c68c --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_resize_conv.v
@@ -0,0 +1,549 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_resize_conv + (clk, + reset_n, + clk_cfg, + reset_cfg_n, + soft_rst, + cfg_val, + cfg_addr, + cfg_rd, + cfg_wdata, + cfg_rdata, + cfg_ack, + in_y_pix_data, + in_y_val, + in_y_h_end, + in_y_v_end, + in_y_cfg_upd, + in_y_ack, + ram_y_wr_n, + ram_y_cs_n, + ram_y_addr, + ram_y_wdata, + ram_y_rdata, + in_c_pix_data, + in_c_val, + in_c_h_end, + in_c_v_end, + in_c_cfg_upd, + in_c_ack, + ram_c_wr_n, + ram_c_cs_n, + ram_c_addr, + ram_c_wdata, + ram_c_rdata, + out_y_r_val, + out_y_r_data, + out_y_r_h_end, + out_y_r_v_end, + out_y_r_cfg_upd, + out_y_r_ack, + out_cb_g_val, + out_cb_g_data, + out_cb_g_h_end, + out_cb_g_v_end, + out_cb_g_cfg_upd, + out_cb_g_ack, + out_cr_b_val, + out_cr_b_data, + out_cr_b_h_end, + out_cr_b_v_end, + out_cr_b_cfg_upd, + out_cr_b_ack, + out_y_r_frame_start, + out_y_r_frame_end, + out_y_r_line_start, + out_y_r_line_end, + out_cb_g_frame_start, + out_cb_g_frame_end, + out_cb_g_line_start, + out_cb_g_line_end, + out_cr_b_frame_start, + out_cr_b_frame_end, + out_cr_b_line_start, + out_cr_b_line_end, + out_y_r_ack_stream, + out_cb_g_ack_stream, + out_cr_b_ack_stream, + out_y_r_val_stream, + out_y_r_data_stream, + out_cb_g_val_stream, + out_cb_g_data_stream, + out_cr_b_val_stream, + out_cr_b_data_stream +); +`include "vsisp_self_resize.vh" + input clk; + input reset_n; + input clk_cfg; + input reset_cfg_n; + input soft_rst; + input cfg_val; + input [6:2] cfg_addr; + input cfg_rd; + input [31:0] cfg_wdata; + output [31:0] cfg_rdata; + output cfg_ack; + input [7:0] in_y_pix_data; + input in_y_val; + input in_y_h_end; + input in_y_v_end; + input in_y_cfg_upd; + output in_y_ack; + output ram_y_wr_n; + output ram_y_cs_n; + output [c_ram_width-1:0] ram_y_addr; + output [31:0] ram_y_wdata; + input [31:0] ram_y_rdata; + input [7:0] in_c_pix_data; + input in_c_val; + input in_c_h_end; + input in_c_v_end; + input in_c_cfg_upd; + output in_c_ack; + output ram_c_wr_n; + output ram_c_cs_n; + output [c_ram_width-1:0] ram_c_addr; + output [31:0] ram_c_wdata; + input [31:0] ram_c_rdata; + output out_y_r_val; + output wire [ 7: 0] out_y_r_data; + output out_y_r_h_end; + output out_y_r_v_end; + output out_y_r_cfg_upd; + input out_y_r_ack; + output out_cb_g_val; + output wire [ 7: 0] out_cb_g_data; + output out_cb_g_h_end; + output out_cb_g_v_end; + output out_cb_g_cfg_upd; + input out_cb_g_ack; + output out_cr_b_val; + output wire [ 7: 0] out_cr_b_data; + output out_cr_b_h_end; + output out_cr_b_v_end; + output out_cr_b_cfg_upd; + input out_cr_b_ack; + output out_y_r_frame_start; + output out_y_r_frame_end; + output out_y_r_line_start; + output out_y_r_line_end; + output out_cb_g_frame_start; + output out_cb_g_frame_end; + output out_cb_g_line_start; + output out_cb_g_line_end; + output out_cr_b_frame_start; + output out_cr_b_frame_end; + output out_cr_b_line_start; + output out_cr_b_line_end; + output out_y_r_val_stream; + output wire [ 7: 0] out_y_r_data_stream; + output out_cb_g_val_stream; + output wire [ 7: 0] out_cb_g_data_stream; + output out_cr_b_val_stream; + output wire [ 7: 0] out_cr_b_data_stream; + input out_y_r_ack_stream; + input out_cb_g_ack_stream; + input out_cr_b_ack_stream; + wire viv_s0; + wire viv_s1; + wire viv_s2; + wire viv_s3; + wire viv_s4; + wire viv_s5; + wire viv_s6; + wire viv_s7; + wire viv_s8; + wire viv_s9; + wire [c_scale_h - 1:0] viv_s10; + wire [c_scale_h - 1:0] viv_s11; + wire [c_scale_h - 1:0] viv_s12; + wire [c_scale_v - 1:0] viv_s13; + wire [c_scale_v - 1:0] viv_s14; + wire [c_phase_h - 1:0] viv_s15; + wire [c_phase_h - 1:0] viv_s16; + wire [c_phase_v - 1:0] viv_s17; + wire [c_phase_v - 1:0] viv_s18; + wire viv_s19; + wire [size_width- 1:0] viv_s20; + wire [size_width- 1:0] viv_s21; + wire [size_width- 1:0] viv_s22; + wire [size_width- 1:0] viv_s23; + wire viv_s24; + wire viv_s25; + wire viv_s26; + wire viv_s27; + wire viv_s28; + wire viv_s29; + wire viv_s30; + wire viv_s31; + wire [c_scale_h-1:0] viv_s32; + wire [c_scale_h-1:0] viv_s33; + wire [c_scale_h-1:0] viv_s34; + wire [c_scale_v-1:0] viv_s35; + wire [c_scale_v-1:0] viv_s36; + wire [c_scale_h-1:0] viv_s37; + wire [c_scale_h-1:0] viv_s38; + wire [c_scale_v-1:0] viv_s39; + wire [c_scale_v-1:0] viv_s40; + wire [c_scale_lut_addr - 1:0] viv_s41; + wire [c_scale_lut_addr - 1:0] viv_s42; + wire [c_scale_lut - 1:0] viv_s43; + wire [c_scale_lut - 1:0] viv_s44; + wire [c_scale_lut_addr - 1:0] viv_s45; + wire [c_scale_lut_addr - 1:0] viv_s46; + wire [c_scale_lut - 1:0] viv_s47; + wire [c_scale_lut - 1:0] viv_s48; + wire [ 1: 0] viv_s49; + wire viv_s50; + wire viv_s51; + wire viv_s52; + wire [ 2: 0] viv_s53; + wire viv_s54; + wire viv_s55; + wire [7:0] viv_s56; + wire viv_s57; + wire viv_s58; + wire viv_s59; + wire viv_s60; + wire viv_s61; + wire [7:0] viv_s62; + wire viv_s63; + wire viv_s64; + wire viv_s65; + wire viv_s66; + wire viv_s67; + wire viv_s68; + wire [7:0] viv_s69; + wire viv_s70; + wire viv_s71; + wire viv_s72; + wire viv_s73; + wire viv_s74; + wire [7:0] viv_s75; + wire viv_s76; + wire viv_s77; + wire viv_s78; + wire viv_s79; + wire viv_s80; + wire [7:0] viv_s81; + wire viv_s82; + wire viv_s83; + wire viv_s84; + wire viv_s85; + vsisp_resize_conv_ctrl u_resize_conv_ctrl + (.clk_cfg(clk_cfg), + .reset_cfg_n(reset_cfg_n), + .val(cfg_val), + .addr(cfg_addr), + .rd(cfg_rd), + .wdata(cfg_wdata), + .rdata(cfg_rdata), + .ack(cfg_ack), + .cfg_upd(viv_s0), + .gen_cfg_upd(viv_s1), + .scale_hy_en(viv_s2), + .scale_hc_en(viv_s3), + .scale_vy_en(viv_s4), + .scale_vc_en(viv_s5), + .scale_hy_up(viv_s6), + .scale_hc_up(viv_s7), + .scale_vy_up(viv_s8), + .scale_vc_up(viv_s9), + .scale_hy(viv_s10), + .scale_hcb(viv_s11), + .scale_hcr(viv_s12), + .scale_vy(viv_s13), + .scale_vc(viv_s14), + .phase_hy(viv_s15), + .phase_hc(viv_s16), + .phase_vy(viv_s17), + .phase_vc(viv_s18), + .y_scale_h_lut_ad(viv_s41), + .y_scale_v_lut_ad(viv_s42), + .y_scale_h_lut(viv_s43), + .y_scale_v_lut(viv_s44), + .chroma_scale_h_lut_ad(viv_s45), + .chroma_scale_v_lut_ad(viv_s46), + .chroma_scale_h_lut(viv_s47), + .chroma_scale_v_lut(viv_s48), + .scale_hy_en_sdw(viv_s24), + .scale_hc_en_sdw(viv_s25), + .scale_vy_en_sdw(viv_s26), + .scale_vc_en_sdw(viv_s27), + .scale_hy_up_sdw(viv_s28), + .scale_hc_up_sdw(viv_s29), + .scale_vy_up_sdw(viv_s30), + .scale_vc_up_sdw(viv_s31), + .scale_hy_sdw(viv_s32), + .scale_hcb_sdw(viv_s33), + .scale_hcr_sdw(viv_s34), + .scale_vy_sdw(viv_s35), + .scale_vc_sdw(viv_s36), + .phase_hy_sdw(viv_s37), + .phase_hc_sdw(viv_s38), + .phase_vy_sdw(viv_s39), + .phase_vc_sdw(viv_s40), + .sp_input_format(viv_s49), + .cfg_y_full(viv_s50), + .cfg_crcb_full(viv_s51), + .cfg_422noncosited(viv_s52), + .sp_output_format(viv_s53)); + vsisp_self_resize u_self_resize + (.clk(clk), + .reset_n (reset_n), + .soft_rst (soft_rst), + .in_y_pix_data (in_y_pix_data), + .in_y_val (in_y_val), + .in_y_h_end (in_y_h_end), + .in_y_v_end (in_y_v_end), + .in_y_cfg_upd (in_y_cfg_upd), + .in_y_ack (in_y_ack), + .out_y_pix_data (viv_s56), + .out_y_val (viv_s57), + .out_y_h_end (viv_s58), + .out_y_v_end (viv_s59), + .out_y_cfg_upd (viv_s60), + .out_y_ack (viv_s61), + .ram_y_wr_n (ram_y_wr_n), + .ram_y_cs_n (ram_y_cs_n), + .ram_y_addr (ram_y_addr), + .ram_y_wdata (ram_y_wdata), + .ram_y_rdata (ram_y_rdata), + .in_c_pix_data (in_c_pix_data), + .in_c_val (in_c_val), + .in_c_h_end (in_c_h_end), + .in_c_v_end (in_c_v_end), + .in_c_cfg_upd (in_c_cfg_upd), + .in_c_ack (in_c_ack), + .out_c_pix_data (viv_s62), + .out_c_val (viv_s63), + .out_c_h_end (viv_s64), + .out_c_v_end (viv_s65), + .out_c_cfg_upd (viv_s66), + .out_c_ack (viv_s67), + .ram_c_wr_n (ram_c_wr_n), + .ram_c_cs_n (ram_c_cs_n), + .ram_c_addr (ram_c_addr), + .ram_c_wdata (ram_c_wdata), + .ram_c_rdata (ram_c_rdata), + .cfg_upd(viv_s0), + .gen_cfg_upd(viv_s1), + .scale_hy_en(viv_s2), + .scale_hc_en(viv_s3), + .scale_vy_en(viv_s4), + .scale_vc_en(viv_s5), + .scale_hy_up(viv_s6), + .scale_hc_up(viv_s7), + .scale_vy_up(viv_s8), + .scale_vc_up(viv_s9), + .scale_hy(viv_s10), + .scale_hcb(viv_s11), + .scale_hcr(viv_s12), + .scale_vy(viv_s13), + .scale_vc(viv_s14), + .phase_hy(viv_s15), + .phase_hc(viv_s16), + .phase_vy(viv_s17), + .phase_vc(viv_s18), + .y_scale_h_lut_ad(viv_s41), + .y_scale_v_lut_ad(viv_s42), + .y_scale_h_lut(viv_s43), + .y_scale_v_lut(viv_s44), + .chroma_scale_h_lut_ad(viv_s45), + .chroma_scale_v_lut_ad(viv_s46), + .chroma_scale_h_lut(viv_s47), + .chroma_scale_v_lut(viv_s48), + .scale_hy_en_sdw(viv_s24), + .scale_hc_en_sdw(viv_s25), + .scale_vy_en_sdw(viv_s26), + .scale_vc_en_sdw(viv_s27), + .scale_hy_up_sdw(viv_s28), + .scale_hc_up_sdw(viv_s29), + .scale_vy_up_sdw(viv_s30), + .scale_vc_up_sdw(viv_s31), + .scale_hy_sdw(viv_s32), + .scale_hcb_sdw(viv_s33), + .scale_hcr_sdw(viv_s34), + .scale_vy_sdw(viv_s35), + .scale_vc_sdw(viv_s36), + .phase_hy_sdw(viv_s37), + .phase_hc_sdw(viv_s38), + .phase_vy_sdw(viv_s39), + .phase_vc_sdw(viv_s40)); + vsisp_resize_to_conv_2to3 u1_resize_to_conv_2to3 + ( + .clk (clk), + .reset_n (reset_n), + .soft_rst (soft_rst), + .in_y_val (viv_s57), + .in_y_data (viv_s56), + .in_y_h_end (viv_s58), + .in_y_v_end (viv_s59), + .in_y_cfg_upd (viv_s60), + .in_y_ack (viv_s61), + .in_c_val (viv_s63), + .in_c_data (viv_s62), + .in_c_h_end (viv_s64), + .in_c_v_end (viv_s65), + .in_c_cfg_upd (viv_s66), + .in_c_ack (viv_s67), + .out_y_val (viv_s68), + .out_y_data (viv_s69), + .out_y_h_end (viv_s70), + .out_y_v_end (viv_s71), + .out_y_cfg_update (viv_s72), + .out_y_ack (viv_s73), + .out_cb_val (viv_s74), + .out_cb_data (viv_s75), + .out_cb_h_end (viv_s76), + .out_cb_v_end (viv_s77), + .out_cb_cfg_update (viv_s78), + .out_cb_ack (viv_s79), + .out_cr_val (viv_s80), + .out_cr_data (viv_s81), + .out_cr_h_end (viv_s82), + .out_cr_v_end (viv_s83), + .out_cr_cfg_update (viv_s84), + .out_cr_ack (viv_s85) + ); + wire viv_s86; + wire [7:0] viv_s87; + wire viv_s88; + wire viv_s89; + wire viv_s90; + wire viv_s91; +vsisp_conv_dpsfe #(11) u1_conv_dpsfe( + .clk ( clk ), + .reset_n ( reset_n ), + .soft_rst ( soft_rst ), + .dpsfe_data_i ({viv_s69,viv_s70,viv_s71,viv_s72}), + .dpsfe_val_i (viv_s68 ), + .dpsfe_ack_o (viv_s73 ), + .dpsfe_data_o ({viv_s87,viv_s88,viv_s89,viv_s90}), + .dpsfe_val_o (viv_s86), + .dpsfe_ack_i (viv_s91) +); + wire viv_s92; + wire [7:0] viv_s93; + wire viv_s94; + wire viv_s95; + wire viv_s96; + wire viv_s97; +vsisp_conv_dpsfe #(11) u2_conv_dpsfe( + .clk ( clk ), + .reset_n ( reset_n ), + .soft_rst ( soft_rst ), + .dpsfe_data_i ({viv_s87,viv_s88,viv_s89,viv_s90}), + .dpsfe_val_i (viv_s86 ), + .dpsfe_ack_o (viv_s91 ), + .dpsfe_data_o ({viv_s93,viv_s94,viv_s95,viv_s96}), + .dpsfe_val_o (viv_s92), + .dpsfe_ack_i (viv_s97) +); + wire viv_s98; + wire [7:0] viv_s99; + wire viv_s100; + wire viv_s101; + wire viv_s102; + wire viv_s103; +vsisp_conv_dpsfe #(11) u3_conv_dpsfe( + .clk ( clk ), + .reset_n ( reset_n ), + .soft_rst ( soft_rst ), + .dpsfe_data_i ({viv_s93,viv_s94,viv_s95,viv_s96}), + .dpsfe_val_i (viv_s92 ), + .dpsfe_ack_o (viv_s97 ), + .dpsfe_data_o ({viv_s99,viv_s100,viv_s101,viv_s102}), + .dpsfe_val_o (viv_s98), + .dpsfe_ack_i (viv_s103) +); + vsisp_conv u_conv + ( + .clk (clk), + .reset_n (reset_n), + .soft_rst (soft_rst), + .in_y_val (viv_s98), + .in_y_data (viv_s99), + .in_y_h_end (viv_s100), + .in_y_v_end (viv_s101), + .in_y_cfg_upd (viv_s102), + .in_y_ack (viv_s103), + .in_cb_val (viv_s74), + .in_cb_data (viv_s75), + .in_cb_h_end (viv_s76), + .in_cb_v_end (viv_s77), + .in_cb_cfg_upd (viv_s78), + .in_cb_ack (viv_s79), + .in_cr_val (viv_s80), + .in_cr_data (viv_s81), + .in_cr_h_end (viv_s82), + .in_cr_v_end (viv_s83), + .in_cr_cfg_upd (viv_s84), + .in_cr_ack (viv_s85), + .out_y_r_val (out_y_r_val), + .out_y_r_data (out_y_r_data), + .out_y_r_h_end (out_y_r_h_end), + .out_y_r_v_end (out_y_r_v_end), + .out_y_r_cfg_upd (out_y_r_cfg_upd), + .out_y_r_ack (out_y_r_ack && out_y_r_ack_stream), + .out_cb_g_val (out_cb_g_val), + .out_cb_g_data (out_cb_g_data), + .out_cb_g_h_end (out_cb_g_h_end), + .out_cb_g_v_end (out_cb_g_v_end), + .out_cb_g_cfg_upd (out_cb_g_cfg_upd), + .out_cb_g_ack (out_cb_g_ack && out_cb_g_ack_stream), + .out_cr_b_val (out_cr_b_val), + .out_cr_b_data (out_cr_b_data), + .out_cr_b_h_end (out_cr_b_h_end), + .out_cr_b_v_end (out_cr_b_v_end), + .out_cr_b_cfg_upd (out_cr_b_cfg_upd), + .out_cr_b_ack (out_cr_b_ack && out_cr_b_ack_stream ), + .sp_input_format (viv_s49), + .cfg_y_full (viv_s50), + .cfg_crcb_full (viv_s51), + .cfg_422noncosited (viv_s52), + .sp_output_format (viv_s53), + .out_y_r_frame_start (out_y_r_frame_start), + .out_y_r_frame_end (out_y_r_frame_end), + .out_y_r_line_start (out_y_r_line_start), + .out_y_r_line_end (out_y_r_line_end), + .out_cb_g_frame_start (out_cb_g_frame_start), + .out_cb_g_frame_end (out_cb_g_frame_end), + .out_cb_g_line_start (out_cb_g_line_start), + .out_cb_g_line_end (out_cb_g_line_end), + .out_cr_b_frame_start (out_cr_b_frame_start), + .out_cr_b_frame_end (out_cr_b_frame_end), + .out_cr_b_line_start (out_cr_b_line_start), + .out_cr_b_line_end (out_cr_b_line_end), + .out_y_r_val_stream (out_y_r_val_stream), + .out_cb_g_val_stream (out_cb_g_val_stream), + .out_cr_b_val_stream (out_cr_b_val_stream) + ); +assign out_y_r_data_stream = out_y_r_data; +assign out_cb_g_data_stream = out_cb_g_data; +assign out_cr_b_data_stream = out_cr_b_data; +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_resize_conv_ctrl.v b/ispyocto/rtl/ispyocto/vsisp_resize_conv_ctrl.v new file mode 100644 index 0000000..bc00edf --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_resize_conv_ctrl.v
@@ -0,0 +1,442 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_resize_conv_ctrl + ( + clk_cfg, + reset_cfg_n, + val, + addr, + rd, + wdata, + rdata, + ack, + cfg_upd, + gen_cfg_upd, + scale_hy_en, + scale_hc_en, + scale_vy_en, + scale_vc_en, + scale_hy_up, + scale_hc_up, + scale_vy_up, + scale_vc_up, + scale_hy, + scale_hcb, + scale_hcr, + scale_vy, + scale_vc, + phase_hy, + phase_hc, + phase_vy, + phase_vc, + y_scale_h_lut_ad, + y_scale_v_lut_ad, + y_scale_h_lut, + y_scale_v_lut, + chroma_scale_h_lut_ad, + chroma_scale_v_lut_ad, + chroma_scale_h_lut, + chroma_scale_v_lut, + scale_hy_en_sdw, + scale_hc_en_sdw, + scale_vy_en_sdw, + scale_vc_en_sdw, + scale_hy_up_sdw, + scale_hc_up_sdw, + scale_vy_up_sdw, + scale_vc_up_sdw, + scale_hy_sdw, + scale_hcb_sdw, + scale_hcr_sdw, + scale_vy_sdw, + scale_vc_sdw, + phase_hy_sdw, + phase_hc_sdw, + phase_vy_sdw, + phase_vc_sdw, + sp_input_format, + cfg_y_full, + cfg_crcb_full, + cfg_422noncosited, + sp_output_format + ); +`include "vsisp_self_resize.vh" + input clk_cfg; + input reset_cfg_n; + input val; + input [6:2] addr; + input rd; + input [31:0] wdata; + output [31:0] rdata; + reg [31:0] rdata; + output ack; + output cfg_upd; + output gen_cfg_upd; + output scale_hy_en; + output scale_hc_en; + output scale_vy_en; + output scale_vc_en; + output scale_hy_up; + output scale_hc_up; + output scale_vy_up; + output scale_vc_up; + output [c_scale_h - 1:0] scale_hy; + output [c_scale_h - 1:0] scale_hcb; + output [c_scale_h - 1:0] scale_hcr; + output [c_scale_v - 1:0] scale_vy; + output [c_scale_v - 1:0] scale_vc; + output [c_phase_h - 1:0] phase_hy; + output [c_phase_h - 1:0] phase_hc; + output [c_phase_v - 1:0] phase_vy; + output [c_phase_v - 1:0] phase_vc; + input scale_hy_en_sdw; + input scale_hc_en_sdw; + input scale_vy_en_sdw; + input scale_vc_en_sdw; + input scale_hy_up_sdw; + input scale_hc_up_sdw; + input scale_vy_up_sdw; + input scale_vc_up_sdw; + input [c_scale_h-1:0] scale_hy_sdw; + input [c_scale_h-1:0] scale_hcb_sdw; + input [c_scale_h-1:0] scale_hcr_sdw; + input [c_scale_v-1:0] scale_vy_sdw; + input [c_scale_v-1:0] scale_vc_sdw; + input [c_scale_h-1:0] phase_hy_sdw; + input [c_scale_h-1:0] phase_hc_sdw; + input [c_scale_v-1:0] phase_vy_sdw; + input [c_scale_v-1:0] phase_vc_sdw; + input [c_scale_lut_addr - 1:0] y_scale_h_lut_ad; + input [c_scale_lut_addr - 1:0] y_scale_v_lut_ad; + output [c_scale_lut - 1:0] y_scale_h_lut; + output [c_scale_lut - 1:0] y_scale_v_lut; + input [c_scale_lut_addr - 1:0] chroma_scale_h_lut_ad; + input [c_scale_lut_addr - 1:0] chroma_scale_v_lut_ad; + output [c_scale_lut - 1:0] chroma_scale_h_lut; + output [c_scale_lut - 1:0] chroma_scale_v_lut; + output [ 1: 0] sp_input_format; + output cfg_y_full; + output cfg_crcb_full; + output cfg_422noncosited; + output [ 2: 0] sp_output_format; + reg cfg_upd; + reg gen_cfg_upd; + reg [7:0] viv_s0; + reg [c_scale_h - 1:0] viv_s1; + reg [c_scale_h - 1:0] viv_s2; + reg [c_scale_h - 1:0] viv_s3; + reg [c_scale_v - 1:0] viv_s4; + reg [c_scale_v - 1:0] viv_s5; + reg [c_phase_h - 1:0] viv_s6; + reg [c_phase_h - 1:0] viv_s7; + reg [c_phase_v - 1:0] viv_s8; + reg [c_phase_v - 1:0] viv_s9; + reg [c_scale_lut_addr - 1:0] viv_s10; + reg viv_s11; + reg [7:0] viv_s12; + wire [c_scale_lut_addr - 1:0] viv_s13; + wire [c_scale_lut_addr - 1:0] viv_s14; + wire [c_scale_lut_addr - 1:0] viv_s15; + wire [c_scale_lut_addr - 1:0] viv_s16; + wire [c_scale_lut_addr - 1:0] viv_s17; + reg [c_scale_lut - 1:0] v_lut[c_number_of_lut - 1:0]; + assign viv_s13 = viv_s10; + assign viv_s14 = y_scale_h_lut_ad; + assign viv_s15 = y_scale_v_lut_ad; + assign viv_s16 = chroma_scale_h_lut_ad; + assign viv_s17 = chroma_scale_v_lut_ad; + wire viv_s18= val & (addr==c_resize_scale_lut); + always @(posedge clk_cfg or negedge reset_cfg_n) + begin : config_proc + if (~reset_cfg_n) + begin + viv_s0 <= 8'b0; + viv_s1 <= {c_scale_h{1'b0}}; + viv_s2 <= {c_scale_h{1'b0}}; + viv_s3 <= {c_scale_h{1'b0}}; + viv_s4 <= {c_scale_v{1'b0}}; + viv_s5 <= {c_scale_v{1'b0}}; + viv_s6 <= {c_phase_h{1'b0}}; + viv_s7 <= {c_phase_h{1'b0}}; + viv_s8 <= {c_phase_v{1'b0}}; + viv_s9 <= {c_phase_v{1'b0}}; + viv_s10 <= {c_scale_lut_addr{1'b0}}; + gen_cfg_upd <= 1'b0; + cfg_upd <= 1'b0; + rdata <= 32'b0; + viv_s11 <= 1'b0; + viv_s12 <= 8'b0; + end + else + begin + rdata <= 32'b0; + cfg_upd <= 1'b0; + if(viv_s11 & viv_s18) begin + viv_s10 <= viv_s10 + 1'b1; + end + if (val) begin + if (~viv_s11) begin + viv_s11 <= 1'b1; + end + else begin + viv_s11 <= 1'b0; + end + case (addr) + c_resize_ctrl : + begin + if (~rd) begin + viv_s0 <= wdata[7:0]; + cfg_upd <= wdata[8]; + gen_cfg_upd <= wdata[9]; + end + else begin + rdata[9:0]<= {gen_cfg_upd,1'b0,viv_s0}; + end + end + c_resize_scale_hy : + begin + if (~rd) begin + viv_s1 <= wdata[c_scale_h - 1:0]; + end + else begin + rdata[c_scale_h - 1:0] <= viv_s1; + end + end + c_resize_scale_hcb : + begin + if (~rd) begin + viv_s2 <= wdata[c_scale_h - 1:0]; + end + else begin + rdata[c_scale_h - 1:0] <= viv_s2; + end + end + c_resize_scale_hcr : + begin + if (~rd) begin + viv_s3 <= wdata[c_scale_h - 1:0]; + end + else begin + rdata[c_scale_h - 1:0] <= viv_s3; + end + end + c_resize_scale_vy : + begin + if (~rd) begin + viv_s4 <= wdata[c_scale_v - 1:0]; + end + else begin + rdata[c_scale_v - 1:0] <= viv_s4; + end + end + c_resize_scale_vc : + begin + if (~rd) begin + viv_s5 <= wdata[c_scale_v - 1:0]; + end + else begin + rdata[c_scale_v - 1:0] <= viv_s5; + end + end + c_resize_phase_hy : + begin + if (~rd) begin + viv_s6 <= wdata[c_phase_h - 1:0]; + end + else begin + rdata[c_phase_h - 1:0] <= viv_s6; + end + end + c_resize_phase_hc : + begin + if (~rd) begin + viv_s7 <= wdata[c_phase_h - 1:0]; + end + else begin + rdata[c_phase_h - 1:0] <= viv_s7; + end + end + c_resize_phase_vy : + begin + if (~rd) begin + viv_s8 <= wdata[c_phase_v - 1:0]; + end + else begin + rdata[c_phase_v - 1:0] <= viv_s8; + end + end + c_resize_phase_vc : + begin + if (~rd) begin + viv_s9 <= wdata[c_phase_v - 1:0]; + end + else begin + rdata[c_phase_v - 1:0] <= viv_s9; + end + end + c_resize_scale_lut_addr : + begin + if (~rd) begin + viv_s10 <= wdata[c_scale_lut_addr-1:0]; + end + else begin + rdata[c_scale_lut-1:0] <= viv_s10; + end + end + c_resize_scale_lut : + begin + if (rd) begin + rdata[c_scale_lut-1:0] <= v_lut[viv_s13]; + end + end + format_conv_ctrl : + begin + if (~rd) begin + viv_s12 <= wdata[7:0]; + end + else begin + rdata <= {24'h0,viv_s12[7:0]}; + end + end + c_resize_ctrl_sdw : + begin + if (rd) begin + rdata[0] <= scale_hy_en_sdw; + rdata[1] <= scale_hc_en_sdw; + rdata[2] <= scale_vy_en_sdw; + rdata[3] <= scale_vc_en_sdw; + rdata[4] <= scale_hy_up_sdw; + rdata[5] <= scale_hc_up_sdw; + rdata[6] <= scale_vy_up_sdw; + rdata[7] <= scale_vc_up_sdw; + end + end + c_resize_scale_hy_sdw : + begin + if (rd) begin + rdata[c_scale_h-1:0] <= scale_hy_sdw; + end + end + c_resize_scale_hcb_sdw : + begin + if (rd) begin + rdata[c_scale_h-1:0] <= scale_hcb_sdw; + end + end + c_resize_scale_hcr_sdw : + begin + if (rd) begin + rdata[c_scale_h-1:0] <= scale_hcr_sdw; + end + end + c_resize_scale_vy_sdw : + begin + if (rd) begin + rdata[c_scale_v-1:0] <= scale_vy_sdw; + end + end + c_resize_scale_vc_sdw : + begin + if (rd) begin + rdata[c_scale_v-1:0] <= scale_vc_sdw; + end + end + c_resize_phase_hy_sdw : + begin + if (rd) begin + rdata[c_scale_h-1:0] <= phase_hy_sdw; + end + end + c_resize_phase_hc_sdw : + begin + if (rd) begin + rdata[c_scale_h-1:0] <= phase_hc_sdw; + end + end + c_resize_phase_vy_sdw : + begin + if (rd) begin + rdata[c_scale_v-1:0] <= phase_vy_sdw; + end + end + c_resize_phase_vc_sdw : + begin + if (rd) begin + rdata[c_scale_v-1:0] <= phase_vc_sdw; + end + end + default : + begin + rdata <= 32'b0; + end + endcase + end + end + end + always @(posedge clk_cfg or negedge reset_cfg_n) + begin : look_up_proc + if (~reset_cfg_n) begin + begin : xhdl_8 + integer v_i; + for(v_i = 0; v_i <= c_number_of_lut - 1; v_i = v_i + 1) begin + v_lut[v_i] <= {c_scale_lut{1'b0}}; + end + end + end + else begin + if (~rd & val) begin + if (addr == c_resize_scale_lut) begin + v_lut[viv_s13] <= wdata[c_scale_lut-1:0]; + end + end + end + end + assign y_scale_h_lut = v_lut[viv_s14]; + assign y_scale_v_lut = v_lut[viv_s15]; + assign chroma_scale_h_lut = v_lut[viv_s16]; + assign chroma_scale_v_lut = v_lut[viv_s17]; + assign ack = viv_s11; + assign scale_hy_en = viv_s0[0]; + assign scale_hc_en = viv_s0[1]; + assign scale_vy_en = viv_s0[2]; + assign scale_vc_en = viv_s0[3]; + assign scale_hy_up = viv_s0[4]; + assign scale_hc_up = viv_s0[5]; + assign scale_vy_up = viv_s0[6]; + assign scale_vc_up = viv_s0[7]; + assign scale_hy = viv_s1; + assign scale_hcb = viv_s2; + assign scale_hcr = viv_s3; + assign scale_vy = viv_s4; + assign scale_vc = viv_s5; + assign phase_hy = viv_s6; + assign phase_hc = viv_s7; + assign phase_vy = viv_s8; + assign phase_vc = viv_s9; + assign sp_input_format = viv_s12[1:0]; + assign sp_output_format = viv_s12[4:2]; + assign cfg_y_full = viv_s12[5]; + assign cfg_crcb_full = viv_s12[6]; + assign cfg_422noncosited = viv_s12[7]; +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_resize_to_conv_2to3.v b/ispyocto/rtl/ispyocto/vsisp_resize_to_conv_2to3.v new file mode 100644 index 0000000..0b8695b --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_resize_to_conv_2to3.v
@@ -0,0 +1,207 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_resize_to_conv_2to3 ( + clk, + reset_n, + soft_rst, + in_y_val, + in_y_data, + in_y_h_end, + in_y_v_end, + in_y_cfg_upd, + in_y_ack, + in_c_val, + in_c_data, + in_c_h_end, + in_c_v_end, + in_c_cfg_upd, + in_c_ack, + out_y_val, + out_y_data, + out_y_h_end, + out_y_v_end, + out_y_cfg_update, + out_y_ack, + out_cb_val, + out_cb_data, + out_cb_h_end, + out_cb_v_end, + out_cb_cfg_update, + out_cb_ack, + out_cr_val, + out_cr_data, + out_cr_h_end, + out_cr_v_end, + out_cr_cfg_update, + out_cr_ack +); +parameter data_width=8; +parameter pack_data_width=11; +input clk; +input reset_n; +input soft_rst; +input in_y_val; +input [data_width-1:0] in_y_data; +input in_y_h_end; +input in_y_v_end; +input in_y_cfg_upd; +output in_y_ack; +wire in_y_ack; +input in_c_val; +input [data_width-1:0] in_c_data; +input in_c_h_end; +input in_c_v_end; +input in_c_cfg_upd; +output in_c_ack; +wire in_c_ack; +output out_y_val; +output [data_width-1:0] out_y_data; +output out_y_h_end; +output out_y_v_end; +output out_y_cfg_update; +input out_y_ack; +wire out_y_val; +wire [data_width-1:0] out_y_data; +wire out_y_h_end; +wire out_y_v_end; +wire out_y_cfg_update; +output out_cb_val; +output [data_width-1:0] out_cb_data; +output out_cb_h_end; +output out_cb_v_end; +output out_cb_cfg_update; +input out_cb_ack; +wire out_cb_val; +reg [data_width-1:0] out_cb_data; +wire out_cb_h_end; +wire out_cb_v_end; +wire out_cb_cfg_update; +output out_cr_val; +output [data_width-1:0] out_cr_data; +output out_cr_h_end; +output out_cr_v_end; +output out_cr_cfg_update; +input out_cr_ack; +wire out_cr_val; +reg [data_width-1:0] out_cr_data; +wire out_cr_h_end; +wire out_cr_v_end; +wire out_cr_cfg_update; +wire [pack_data_width-1:0] viv_s0; +wire [pack_data_width-1:0] viv_s1; +wire viv_s2; +wire [data_width-1:0] viv_s3; +wire viv_s4; +wire viv_s5; +wire viv_s6; +wire viv_s7; +wire [pack_data_width*2-1:0] viv_s8; +wire [pack_data_width*2-1:0] viv_s9; +wire [data_width-1:0] viv_s10; +wire [data_width-1:0] viv_s11; +assign viv_s8 = {in_y_data, in_c_data}; +assign viv_s10 = viv_s8[data_width*2-1 : data_width]; +assign viv_s11 = viv_s8[data_width-1 : 0]; +assign out_y_data = viv_s10; +assign out_y_val = in_y_val; +assign out_y_h_end = in_y_h_end; +assign out_y_v_end = in_y_v_end; +assign out_y_cfg_update = in_y_cfg_upd; +assign in_y_ack = out_y_ack; +assign viv_s0 = {in_c_cfg_upd, in_c_v_end, in_c_h_end, viv_s11}; +vsisp_conv_dpsbe #(pack_data_width) u_c_buf( + .clk ( clk ), + .reset_n ( reset_n ), + .soft_rst ( soft_rst ), + .dpsbe_data_i ( viv_s0 ), + .dpsbe_val_i ( in_c_val ), + .dpsbe_ack_o ( in_c_ack ), + .dpsbe_data_o ( viv_s1 ), + .dpsbe_val_o ( viv_s2 ), + .dpsbe_ack_i ( viv_s7 ) +); +assign viv_s3 = viv_s1[data_width-1:0]; +assign viv_s4 = viv_s1[data_width]; +assign viv_s5 = viv_s1[data_width+1]; +assign viv_s6 = viv_s1[data_width+2]; +reg viv_s12; +reg viv_s13; +reg viv_s14; +reg viv_s15; +wire viv_s16; +wire viv_s17; +wire viv_s18; +reg viv_s19; +wire viv_s20; +assign viv_s20 = out_cb_ack & out_cr_ack & viv_s18; +assign viv_s17 = viv_s20; +assign out_cb_val = viv_s20; +assign out_cb_h_end = viv_s12; +assign out_cb_v_end = viv_s13; +assign out_cb_cfg_update = viv_s14; +assign out_cr_val = viv_s20; +assign out_cr_h_end = viv_s12; +assign out_cr_v_end = viv_s13; +assign out_cr_cfg_update = viv_s14; +always @(posedge clk or negedge reset_n) begin + if (~reset_n) begin + out_cb_data <= {data_width{1'b0}}; + out_cr_data <= {data_width{1'b0}}; + viv_s12 <= 1'b0; + viv_s13 <= 1'b0; + viv_s14 <= 1'b0; + viv_s15 <= 1'b0; + viv_s19 <= 1'b0; + end + else if (soft_rst) begin + out_cb_data <= {data_width{1'b0}}; + out_cr_data <= {data_width{1'b0}}; + viv_s12 <= 1'b0; + viv_s13 <= 1'b0; + viv_s14 <= 1'b0; + viv_s15 <= 1'b0; + viv_s19 <= 1'b0; + end + else begin + if (viv_s2 & viv_s7) begin + viv_s19 <= (viv_s4) ? 1'b0 : ~viv_s19; + end + if (viv_s16) begin + viv_s15 <= viv_s2 & viv_s19; + if (viv_s19) begin + out_cr_data <= viv_s3; + end + else begin + out_cb_data <= viv_s3; + end + viv_s14 <= viv_s6; + viv_s12 <= viv_s4; + viv_s13 <= viv_s5; + end + end +end +assign viv_s16 = viv_s17 | (~viv_s15); +assign viv_s7 = viv_s16; +assign viv_s18 = viv_s15; +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_self_hor_c_scale.v b/ispyocto/rtl/ispyocto/vsisp_self_hor_c_scale.v new file mode 100644 index 0000000..9e6bd5c --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_self_hor_c_scale.v
@@ -0,0 +1,663 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_self_hor_c_scale + ( + clk, + reset_n, + soft_rst, + cfg_upd, + gen_cfg_upd, + scale_h_en, + scale_h_up, + scale_hcb, + scale_hcr, + phase_h, + scale_h_lut_ad, + scale_h_lut, + scale_h_en_sdw, + scale_h_up_sdw, + scale_hcb_sdw, + scale_hcr_sdw, + phase_h_sdw, + in_pix_data, + in_val, + in_h_end, + in_v_end, + in_cfg_upd, + in_ack, + out_pix_data, + out_val, + out_h_end, + out_v_end, + out_cfg_upd, + out_ack); +parameter fifo_addr_width=6; +parameter fifo_depth=2**(fifo_addr_width-1); +`include "vsisp_self_resize.vh" + input clk; + input reset_n; + input soft_rst; + input cfg_upd; + input gen_cfg_upd; + input scale_h_en; + input scale_h_up; + input [c_scale_h - 1:0] scale_hcb; + input [c_scale_h - 1:0] scale_hcr; + input [c_phase_h - 1:0] phase_h; + output scale_h_en_sdw; + reg scale_h_en_sdw; + output scale_h_up_sdw; + reg scale_h_up_sdw; + output [c_scale_h - 1:0] scale_hcb_sdw; + reg [c_scale_h - 1:0] scale_hcb_sdw; + output [c_scale_h - 1:0] scale_hcr_sdw; + reg [c_scale_h - 1:0] scale_hcr_sdw; + output [c_scale_h - 1:0] phase_h_sdw; + reg [c_scale_h - 1:0] phase_h_sdw; + output [c_scale_lut_addr - 1:0] scale_h_lut_ad; + wire [c_scale_lut_addr - 1:0] scale_h_lut_ad; + input [c_scale_lut - 1:0] scale_h_lut; + input [7:0] in_pix_data; + input in_val; + input in_h_end; + input in_v_end; + input in_cfg_upd; + output in_ack; + reg in_ack; + wire viv_s0; + output [7:0] out_pix_data; + reg [7:0] out_pix_data; + output out_val; + reg out_val; + output out_h_end; + reg out_h_end; + output out_v_end; + reg out_v_end; + output out_cfg_upd; + wire out_cfg_upd; + input out_ack; + reg viv_s1; + reg viv_s2; + reg viv_s3; + reg viv_s4; + reg viv_s5; + reg viv_s6; + wire viv_s7; + reg viv_s8; + reg viv_s9; + wire viv_s10; + parameter c_idle = 1'b0; + parameter c_output = 1'b1; + reg [c_lbuf_h - 1:0] viv_s11; + reg [c_lbuf_h - 1:0] viv_s12; + wire [c_lbuf_h - 1:0] viv_s13; + wire [(c_scale_h * 2) - 1:0] viv_s14; + wire [(c_scale_h * 2) - 1:0] viv_s15; + wire [(c_scale_h * 2) - 1:0] viv_s16; + wire [(c_scale_h * 2) - 1:0] viv_s17; + reg [c_scale_h - 1:0] viv_s18; + reg [c_scale_h - 1:0] viv_s19; + wire [c_scale_h - 1:0] viv_s20; + wire [c_scale_h - 1:0] viv_s21; + reg [c_scale_h:0] viv_s22; + wire [c_scale_h - 1:0] viv_s23; + reg [c_scale_h - 1:0] viv_s24; + reg [c_scale_h - 1:0] viv_s25; + reg [c_scale_h - 1:0] viv_s26; + reg [c_scale_h - 1:0] viv_s27; + wire [c_scale_h - 1:0] viv_s28; + wire [c_scale_h - 1:0] viv_s29; + wire [c_scale_h - 1:0] viv_s30; + wire [c_scale_h - 1:0] viv_s31; + wire [15:0] viv_s32; + wire [c_scale_h :0] viv_s33; + wire viv_s34; + reg viv_s35; + reg viv_s36; + reg [c_lbuf_h - 1:0] viv_s37; + reg viv_s38; + reg viv_s39; + reg [c_scale_h - 1:0] viv_s40; + reg viv_s41; + reg viv_s42; + reg [7:0] viv_s43; + reg viv_s44; + reg viv_s45; + reg viv_s46; + reg [c_lbuf_h + 1:0] viv_s47; + reg [9:0] viv_s48; + reg viv_s49; + reg viv_s50; + wire [7:0] viv_s51; + wire viv_s52; + wire viv_s53; + wire viv_s54; + wire viv_s55; + reg viv_s56; + reg [7:0] viv_s57; + reg viv_s58; + reg viv_s59; + reg viv_s60; + wire viv_s61; + reg viv_s62; + reg [7:0] viv_s63; + reg [7:0] viv_s64; + reg [7:0] viv_s65; + reg viv_s66; + reg viv_s67; + reg viv_s68; + reg viv_s69; + reg viv_s70; + reg viv_s71; + reg viv_s72; + reg viv_s73; + reg [10:0] fifo_cb[fifo_depth-1:0]; + reg [10:0] fifo_cr[fifo_depth-1:0]; + reg [fifo_addr_width-1:0] viv_s74; + reg [fifo_addr_width-1:0] viv_s75; + reg [fifo_addr_width-1:0] viv_s76; + reg [fifo_addr_width-1:0] viv_s77; + wire [10:0] viv_s78; + wire viv_s79; + wire viv_s80; + wire viv_s81; + reg [19:0] viv_s82; + always @(posedge clk or negedge reset_n) + begin : proc_shadow + if (~reset_n) + begin + scale_h_en_sdw <= 1'b0; + scale_h_up_sdw <= 1'b0; + scale_hcb_sdw <= {c_scale_h{1'b0}}; + scale_hcr_sdw <= {c_scale_h{1'b0}}; + phase_h_sdw <= {c_scale_h{1'b0}}; + end + else + begin + if (viv_s81) + begin + scale_h_en_sdw <= scale_h_en; + scale_h_up_sdw <= scale_h_up; + scale_hcb_sdw <= scale_hcb; + scale_hcr_sdw <= scale_hcr; + phase_h_sdw <= phase_h; + end + end + end + assign viv_s81 = (out_val & out_h_end & out_v_end & out_ack & (out_cfg_upd || gen_cfg_upd)) | + cfg_upd; + assign viv_s23 = viv_s35 ? scale_hcr_sdw : scale_hcb_sdw; + assign viv_s32 = {16{1'b0}}; + assign viv_s33 = viv_s22 - {1'b0, phase_h_sdw}; + assign viv_s34 = viv_s22[c_scale_h] & viv_s33[c_scale_h] + & |(viv_s33[c_scale_h-1:0]); + assign viv_s78 = viv_s36 ? fifo_cr[viv_s77[fifo_addr_width-2:0]] : fifo_cb[viv_s75[fifo_addr_width-2:0]]; + assign viv_s80 = viv_s36 ? (viv_s76==viv_s77) : (viv_s74==viv_s75); + assign viv_s79 = viv_s35 ? (viv_s76[fifo_addr_width-2:0]==viv_s77[fifo_addr_width-2:0]) & ~(viv_s76[fifo_addr_width-1]==viv_s77[fifo_addr_width-1]) + : (viv_s74[fifo_addr_width-2:0]==viv_s75[fifo_addr_width-2:0]) & ~(viv_s74[fifo_addr_width-1]==viv_s75[fifo_addr_width-1]); + vsisp_add_h_end u_add_h_end + ( + .clk(clk), + .reset_n(reset_n), + .soft_rst(soft_rst), + .in_c_data_i(in_pix_data), + .in_c_h_end_i(in_h_end), + .in_c_v_end_i(in_v_end), + .in_c_cfg_upd_i(in_cfg_upd), + .in_c_val_i(in_val & scale_h_en_sdw), + .in_c_ack_o(viv_s0), + .out_c_data_o(viv_s51), + .out_c_h_end_o(viv_s53), + .out_c_v_end_o(viv_s54), + .out_c_cfg_upd_o(viv_s55), + .out_c_val_o(viv_s52), + .out_c_ack_i(viv_s56) + ); + always @(scale_h_en_sdw or viv_s61 or in_pix_data or in_val or in_h_end or + in_v_end or out_ack or in_cfg_upd or viv_s78 or viv_s80 or + viv_s79 or viv_s4 or viv_s51 or viv_s52 or + viv_s53 or viv_s54 or viv_s55 or viv_s0) + begin : proc_bypass + if (scale_h_en_sdw) + begin + viv_s63 = viv_s51; + viv_s66 = viv_s52; + viv_s67 = viv_s53; + viv_s68 = viv_s54; + viv_s70 = viv_s55; + viv_s56 = viv_s61; + in_ack = viv_s0; + out_pix_data = viv_s78[7:0]; + out_h_end = viv_s78[8] & viv_s4 & ~viv_s80; + out_v_end = viv_s78[9] & ~viv_s80; + viv_s73 = viv_s78[10] & ~viv_s80; + out_val = ~viv_s80; + viv_s69 = ~viv_s79; + end + else + begin + viv_s63 = 8'b0; + viv_s66 = 1'b0; + viv_s67 = 1'b0; + viv_s68 = 1'b0; + viv_s70 = 1'b0; + viv_s56 = 1'b1; + in_ack = out_ack; + out_pix_data = in_pix_data; + out_val = in_val; + out_h_end = in_h_end; + out_v_end = in_v_end; + viv_s73 = in_cfg_upd; + viv_s69 = 1'b0; + end + end + assign out_cfg_upd = viv_s73; + always @(*) + begin : proc_calc + viv_s22 = ({1'b0, viv_s20}) + ({1'b0, viv_s23}); + if (scale_h_up_sdw) begin + viv_s24 = {viv_s32[c_scale_h - 1:10], viv_s13[7:0], 2'b00}; + viv_s25 = viv_s21; + viv_s26 = ({viv_s32[c_scale_h - 1:10], viv_s63, 2'b00}); + viv_s27 = viv_s21; + end + else begin + if ((viv_s22[c_scale_h]) == 1'b1) begin + viv_s24 = {viv_s32[c_scale_h - 1:10], viv_s63, 2'b00}; + viv_s25 = viv_s22[c_scale_h - 1:0]; + end + else begin + viv_s24 = {viv_s32[c_scale_h - 1:10], viv_s63, 2'b00}; + if (viv_s1) + viv_s25 = viv_s23+phase_h_sdw; + else + viv_s25 = viv_s23; + end + viv_s26 = {viv_s32[c_scale_h - 1:10], viv_s63, 2'b00}; + viv_s27 = viv_s20; + end + end + vsisp_self_hor_mult u_self_hor_mult + ( + .a_y1(viv_s28), + .b_y1(viv_s29), + .a_y2(viv_s30), + .b_y2(viv_s31), + .mult_y1(viv_s16), + .mult_y2(viv_s17)); + assign viv_s28 = viv_s24; + assign viv_s29 = viv_s25; + assign viv_s30 = viv_s26; + assign viv_s31 = viv_s27; + assign viv_s14 = {2'b0, viv_s16[(c_scale_h * 2) - 1:2]}; + assign viv_s15 = {2'b0, viv_s17[(c_scale_h * 2) - 1:2]}; + always @(posedge clk or negedge reset_n) + begin : proc_scale_regs + if (~reset_n) begin + viv_s1 <= 1'b1; + viv_s2 <= 1'b0; + viv_s3 <= 1'b0; + viv_s5 <= 1'b0; + viv_s6 <= 1'b0; + viv_s11 <= {c_lbuf_h{1'b0}}; + viv_s18 <= {c_scale_h{1'b0}}; + viv_s8 <= c_idle; + viv_s12 <= {c_lbuf_h{1'b0}}; + viv_s19 <= {c_scale_h{1'b0}}; + viv_s9 <= c_idle; + viv_s62 <= 1'b1; + viv_s57 <= 8'b0; + viv_s58 <= 1'b0; + viv_s59 <= 1'b0; + viv_s60 <= 1'b0; + viv_s72 <= 1'b0; + viv_s35 <= 1'b0; + viv_s36 <= 1'b0; + viv_s64 <= 8'b0; + viv_s65 <= 8'b0; + viv_s4 <= 1'b0; + viv_s82 <= 20'd0; + end + else begin + if (soft_rst) + begin + viv_s1 <= 1'b1; + viv_s2 <= 1'b0; + viv_s3 <= 1'b0; + viv_s4 <= 1'b0; + viv_s5 <= 1'b0; + viv_s6 <= 1'b0; + viv_s11 <= {c_lbuf_h{1'b0}}; + viv_s18 <= phase_h_sdw; + viv_s8 <= c_idle; + viv_s12 <= {c_lbuf_h{1'b0}}; + viv_s19 <= phase_h_sdw; + viv_s9 <= c_idle; + viv_s62 <= 1'b1; + viv_s57 <= 8'b0; + viv_s58 <= 1'b0; + viv_s59 <= 1'b0; + viv_s60 <= 1'b0; + viv_s72 <= 1'b0; + viv_s35 <= 1'b0; + viv_s36 <= 1'b0; + viv_s64 <= 8'b0; + viv_s65 <= 8'b0; + viv_s82 <= 20'd0; + end + else + begin + viv_s1 <= viv_s38; + if (viv_s66 & viv_s61) viv_s2 <= viv_s67; + if (viv_s58 & viv_s69) viv_s3 <= viv_s59; + if (~viv_s80 & out_ack) viv_s4 <= viv_s78[8]; + if (out_val & out_ack) begin + if (out_h_end) begin + viv_s82 <= 20'd0; + end else begin + viv_s82 <= viv_s82 + 20'd1; + end + end + if (~scale_h_up_sdw) begin + if (viv_s35) begin + viv_s9 <= viv_s41; + if (viv_s81) begin + viv_s18 <= phase_h; + viv_s19 <= phase_h; + viv_s11 <= {c_lbuf_h{1'b0}}; + viv_s12 <= {c_lbuf_h{1'b0}}; + end else begin + viv_s19 <= viv_s40; + viv_s12 <= viv_s37; + end + viv_s6 <= viv_s39; + viv_s65 <= viv_s63; + end else begin + viv_s8 <= viv_s41; + if (viv_s81) begin + viv_s18 <= phase_h; + viv_s19 <= phase_h; + viv_s11 <= {c_lbuf_h{1'b0}}; + viv_s12 <= {c_lbuf_h{1'b0}}; + end else begin + viv_s11 <= viv_s37; + viv_s18 <= viv_s40; + end + viv_s5 <= viv_s39; + viv_s64 <= viv_s63; + end + end else begin + if (viv_s35) begin + viv_s65 <= viv_s63; + viv_s9 <= viv_s41; + if (viv_s81) begin + viv_s18 <= phase_h; + viv_s19 <= phase_h; + viv_s11 <= {c_lbuf_h{1'b0}}; + viv_s12 <= {c_lbuf_h{1'b0}}; + end else begin + viv_s19 <= viv_s40; + viv_s12 <= viv_s37; + end + viv_s6 <= viv_s39; + viv_s65 <= viv_s63; + end else begin + viv_s8 <= viv_s41; + if (viv_s81) begin + viv_s11 <= {c_lbuf_h{1'b0}}; + viv_s12 <= {c_lbuf_h{1'b0}}; + viv_s18 <= phase_h; + viv_s19 <= phase_h; + end else begin + viv_s11 <= viv_s37; + viv_s18 <= viv_s40; + end + viv_s5 <= viv_s39; + viv_s64 <= viv_s63; + end + end + viv_s62 <= viv_s42; + viv_s57 <= viv_s43; + viv_s58 <= viv_s44; + viv_s59 <= viv_s45; + viv_s60 <= viv_s46; + viv_s72 <= viv_s71; + viv_s35 <= viv_s49; + viv_s36 <= viv_s50; + end + end + end + assign viv_s20 = viv_s35? viv_s19 : viv_s18; + assign viv_s10 = viv_s35? viv_s9 : viv_s8; + assign viv_s13 = viv_s35? viv_s12 : viv_s11; + assign viv_s7 = viv_s35? viv_s6 : viv_s5; + always @ (*) + begin : proc_scale + viv_s37 = viv_s13; + viv_s38 = viv_s1; + viv_s39 = viv_s7; + viv_s40 = viv_s20; + viv_s41 = viv_s10; + viv_s42 = viv_s62; + viv_s43 = viv_s57; + viv_s44 = viv_s58; + viv_s45 = viv_s59; + viv_s46 = viv_s60; + viv_s71 = viv_s72; + viv_s47 = {c_lbuf_h + 2{1'b0}}; + viv_s48 = 10'b0; + viv_s49 = viv_s35; + viv_s50 = viv_s36; + if (out_val & out_ack) begin + if (out_h_end) + viv_s50 = 1'b0; + else + viv_s50 = ~viv_s36; + end + if (viv_s66 & viv_s61) + if (viv_s67 & viv_s2) + viv_s49 = 1'b0; + else + viv_s49 = ~viv_s35; + if (viv_s58 & viv_s69) begin + viv_s44 = 1'b0; + viv_s45 = 1'b0; + viv_s71 = 1'b0; + if (viv_s3 & viv_s59 & viv_s60) begin + viv_s46 = 1'b0; + end + end + if (viv_s70 & viv_s66 & viv_s61 ) viv_s71 = 1'b1; + else viv_s71 = 1'b0; + viv_s42 = viv_s69; + if (~scale_h_up_sdw) begin + if (viv_s66 & viv_s61) begin + if ((viv_s22[c_scale_h]) | viv_s67) begin + viv_s44 = 1'b1; + viv_s48 = viv_s13[c_lbuf_h - 1:c_lbuf_h - 10] + + ({viv_s63, 2'b10}) - + viv_s15[c_scale_h + 7:c_scale_h - 2]; + if (viv_s1) begin + viv_s43 = viv_s63; + end else begin + viv_s43 = viv_s48[9:2]; + end + viv_s47 = viv_s14[c_scale_h + 7: + c_scale_h - c_lbuf_h + 6]; + viv_s46 = viv_s68; + end + else begin + viv_s47 = ({viv_s13, 2'b00}) + + viv_s14[c_scale_h + 7:c_scale_h - c_lbuf_h + 6]; + end + viv_s37 = viv_s47[c_lbuf_h + 1:2]; + viv_s40 = viv_s22[c_scale_h - 1:0]; + if (viv_s35) + viv_s38 = 1'b0; + if (viv_s67) begin + viv_s45 = 1'b1; + viv_s37 = {c_lbuf_h{1'b0}}; + viv_s40 = phase_h_sdw; + if (viv_s2) begin + viv_s38 = 1'b1; + end + end + end + end + else begin + if (viv_s69) begin + if ((viv_s22[c_scale_h]) == 1'b0 & ~viv_s1) begin + viv_s42 = 1'b0; + end + if (viv_s7) begin + if (viv_s66) begin + if (~viv_s33[c_scale_h] + & (|viv_s33[c_scale_h:0])) begin + viv_s45 = 1'b1; + viv_s44 = 1'b1; + viv_s43 = (viv_s13[7:0]); + viv_s46 = viv_s68; + viv_s40 = phase_h_sdw; + viv_s37 = {c_lbuf_h{1'b0}}; + viv_s38 = viv_s2; + viv_s41 = c_output; + viv_s42 = viv_s69; + viv_s39 = 1'b0; + end else begin + viv_s45 = 1'b0; + viv_s44 = 1'b1; + viv_s43 = (viv_s13[7:0]); + viv_s46 = viv_s68; + viv_s40 = viv_s22[c_scale_h - 1:0]; + viv_s41 = c_output; + viv_s42 = 1'b0; + viv_s39 = 1'b1; + end + end + end else begin + if (viv_s66) begin + if (viv_s61 & viv_s35) viv_s38 = 1'b0; + if (viv_s61 & viv_s2 & viv_s67) begin + viv_s38 = 1'b1; + end + if (~viv_s1 | ~(|phase_h_sdw)) begin + viv_s44 = 1'b1; + if (viv_s1)begin + viv_s48 = ({viv_s63, 2'b00}); + end + else begin + viv_s48 = (({viv_s13[7:0], 2'b00}) + + viv_s15[c_scale_h + 7:c_scale_h - 2] - + viv_s14[c_scale_h + 7:c_scale_h - 2]); + end + viv_s43 = viv_s48[9:2]; + viv_s45 = viv_s67 & viv_s34; + viv_s46 = viv_s68; + viv_s41 = c_output; + viv_s40 = viv_s22[c_scale_h - 1:0]; + if (viv_s67) begin + if (viv_s34) begin + viv_s40 = phase_h_sdw; + viv_s37 = {c_lbuf_h{1'b0}}; + end else begin + viv_s42 = 1'b0; + if (viv_s22[c_scale_h]) + viv_s39 = 1'b1; + end + end + end + if ((viv_s22[c_scale_h]) | viv_s1) begin + viv_s37 = {viv_s32[c_lbuf_h - 9:0],viv_s63}; + if (~viv_s67 | viv_s34) + viv_s42 = viv_s69; + end + else begin + viv_s42 = 1'b0; + end + end + else begin + if (viv_s10 == c_output) begin + viv_s44 = 1'b0; + viv_s41 = c_idle; + end + end + end + end else begin + if (viv_s10 == c_output) begin + viv_s42 = 1'b0; + end + end + end + end + assign viv_s61 = viv_s42; + always @ (posedge clk or negedge reset_n) + begin: proc_fifo + if (~reset_n) begin + viv_s74 <= {fifo_addr_width{1'b0}}; + viv_s76 <= {fifo_addr_width{1'b0}}; + viv_s75 <= {fifo_addr_width{1'b0}}; + viv_s77 <= {fifo_addr_width{1'b0}}; + begin : rstfifo1 + integer v_i; + for(v_i = 0; v_i <= fifo_depth-1; v_i = v_i + 1) begin + fifo_cb[v_i] <= {11{1'b0}}; + fifo_cr[v_i] <= {11{1'b0}}; + end + end + end else begin + if (soft_rst) begin + viv_s74 <= {fifo_addr_width{1'b0}}; + viv_s76 <= {fifo_addr_width{1'b0}}; + viv_s75 <= {fifo_addr_width{1'b0}}; + viv_s77 <= {fifo_addr_width{1'b0}}; + begin : rstfifo2 + integer v_j; + for(v_j = 0; v_j <= fifo_depth-1; v_j = v_j + 1) begin + fifo_cb[v_j] <= {11{1'b0}}; + fifo_cr[v_j] <= {11{1'b0}}; + end + end + end else begin + if (viv_s44 & ~viv_s79) begin + if (~viv_s35) begin + fifo_cb[viv_s74[fifo_addr_width-2:0]] <= {viv_s71, viv_s46, viv_s45, viv_s43}; + viv_s74 <= viv_s74+6'd1; + end else begin + fifo_cr[viv_s76[fifo_addr_width-2:0]] <= {viv_s71, viv_s46, viv_s45, viv_s43}; + viv_s76 <= viv_s76+6'd1; + end + end + if (~viv_s80 & out_ack) begin + if (viv_s36) begin + viv_s77 <= viv_s77 + 6'd1; + end else begin + viv_s75 <= viv_s75 + 6'd1; + end + end + end + end + end + assign scale_h_lut_ad = (viv_s20[c_scale_h - 1:c_scale_h - c_scale_lut_addr]); + assign viv_s21 = {(scale_h_lut), viv_s32[c_scale_h - c_scale_lut - 1:0]}; +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_self_hor_mult.v b/ispyocto/rtl/ispyocto/vsisp_self_hor_mult.v new file mode 100644 index 0000000..ef4f96d --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_self_hor_mult.v
@@ -0,0 +1,50 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_self_hor_mult + ( + a_y1, + b_y1, + a_y2, + b_y2, + mult_y1, + mult_y2); +`include "vsisp_self_resize.vh" + input [c_scale_h - 1:0] a_y1; + input [c_scale_h - 1:0] b_y1; + input [c_scale_h - 1:0] a_y2; + input [c_scale_h - 1:0] b_y2; + output [(c_scale_h * 2) - 1:0] mult_y1; + reg [(c_scale_h * 2) - 1:0] mult_y1; + output [(c_scale_h * 2) - 1:0] mult_y2; + reg [(c_scale_h * 2) - 1:0] mult_y2; + reg [(c_scale_h * 2) - 5:0] viv_s0; + reg [(c_scale_h * 2) - 5:0] viv_s1; + always @(*) + begin : proc_calc + viv_s0 = a_y1[c_scale_h - 1:2] * b_y1[c_scale_h - 1:2]; + viv_s1 = a_y2[c_scale_h - 1:2] * b_y2[c_scale_h - 1:2]; + mult_y1 = {viv_s0,4'b0}; + mult_y2 = {viv_s1,4'b0}; + end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_self_hor_scale.v b/ispyocto/rtl/ispyocto/vsisp_self_hor_scale.v new file mode 100644 index 0000000..0f764b4 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_self_hor_scale.v
@@ -0,0 +1,450 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_self_hor_scale + ( + clk, + reset_n, + soft_rst, + cfg_upd, + gen_cfg_upd, + scale_h_en, + scale_h_up, + scale_h, + phase_h, + scale_h_lut_ad, + scale_h_lut, + scale_h_en_sdw, + scale_h_up_sdw, + scale_h_sdw, + phase_h_sdw, + in_pix_data, + in_val, + in_h_end, + in_v_end, + in_cfg_upd, + in_ack, + out_pix_data, + out_val, + out_h_end, + out_v_end, + out_cfg_upd, + out_ack); +`include "vsisp_self_resize.vh" + input clk; + input reset_n; + input soft_rst; + input cfg_upd; + input gen_cfg_upd; + input scale_h_en; + input scale_h_up; + input [c_scale_h - 1:0] scale_h; + input [c_phase_h - 1:0] phase_h; + output [c_scale_lut_addr - 1:0] scale_h_lut_ad; + wire [c_scale_lut_addr - 1:0] scale_h_lut_ad; + input [c_scale_lut - 1:0] scale_h_lut; + input [7:0] in_pix_data; + input in_val; + input in_h_end; + input in_v_end; + input in_cfg_upd; + output in_ack; + reg in_ack; + output [7:0] out_pix_data; + reg [7:0] out_pix_data; + output out_val; + reg out_val; + output out_h_end; + reg out_h_end; + output out_v_end; + reg out_v_end; + output out_cfg_upd; + input out_ack; + output scale_h_en_sdw; + reg scale_h_en_sdw; + output scale_h_up_sdw; + reg scale_h_up_sdw; + output [c_scale_h - 1:0] scale_h_sdw; + reg [c_scale_h - 1:0] scale_h_sdw; + output [c_scale_h - 1:0] phase_h_sdw; + reg [c_scale_h - 1:0] phase_h_sdw; + reg viv_s0; + reg viv_s1; + reg viv_s2; + parameter c_idle = 1'b0; + parameter c_output = 1'b1; + reg [c_lbuf_h - 1:0] viv_s3; + wire [(c_scale_h * 2) - 1:0] viv_s4; + wire [(c_scale_h * 2) - 1:0] viv_s5; + wire [(c_scale_h * 2) - 1:0] viv_s6; + wire [(c_scale_h * 2) - 1:0] viv_s7; + reg [c_scale_h - 1:0] viv_s8; + wire [c_scale_h - 1:0] viv_s9; + reg [c_scale_h:0] viv_s10; + wire [c_scale_h - 1:0] viv_s11; + reg [c_scale_h - 1:0] viv_s12; + reg [c_scale_h - 1:0] viv_s13; + reg [c_scale_h - 1:0] viv_s14; + reg [c_scale_h - 1:0] viv_s15; + wire [c_scale_h - 1:0] viv_s16; + wire [c_scale_h - 1:0] viv_s17; + wire [c_scale_h - 1:0] viv_s18; + wire [c_scale_h - 1:0] viv_s19; + wire [15:0] viv_s20; + wire [c_scale_h :0] viv_s21; + wire viv_s22; + reg [c_lbuf_h - 1:0] viv_s23; + reg viv_s24; + reg viv_s25; + reg [c_scale_h - 1:0] viv_s26; + reg viv_s27; + reg viv_s28; + reg [7:0] viv_s29; + reg viv_s30; + reg viv_s31; + reg viv_s32; + reg [c_lbuf_h + 1:0] viv_s33; + reg [9:0] viv_s34; + reg [7:0] viv_s35; + reg viv_s36; + reg viv_s37; + reg viv_s38; + wire viv_s39; + reg viv_s40; + reg [7:0] viv_s41; + reg viv_s42; + reg viv_s43; + reg viv_s44; + reg viv_s45; + reg viv_s46; + reg viv_s47; + reg viv_s48; + reg viv_s49; + wire viv_s50; + reg [19:0] viv_s51; + assign viv_s50 = (out_val & out_h_end & out_v_end & out_ack & (out_cfg_upd || gen_cfg_upd)) | + cfg_upd; + assign viv_s11 = scale_h_sdw; + assign viv_s20 = {16{1'b0}}; + assign viv_s21 = viv_s10 - {1'b0, phase_h_sdw}; + assign viv_s22 = viv_s10[c_scale_h] & viv_s21[c_scale_h] + & |(viv_s21[c_scale_h-1:0]); + always @(posedge clk or negedge reset_n) + begin : proc_shadow + if (~reset_n) + begin + scale_h_en_sdw <= 1'b0; + scale_h_up_sdw <= 1'b0; + scale_h_sdw <= {c_scale_h{1'b0}}; + phase_h_sdw <= {c_scale_h{1'b0}}; + end + else + begin + if (viv_s50) + begin + scale_h_en_sdw <= scale_h_en; + scale_h_up_sdw <= scale_h_up; + scale_h_sdw <= scale_h; + phase_h_sdw <= phase_h; + end + end + end + always @(scale_h_en_sdw or viv_s39 or in_pix_data or in_val or in_h_end or + in_v_end or viv_s35 or viv_s36 or viv_s37 or viv_s38 or out_ack or + in_cfg_upd or viv_s48) + begin : proc_bypass + if (scale_h_en_sdw) + begin + viv_s41 = (in_pix_data[7:0]); + viv_s42 = in_val; + viv_s43 = in_h_end; + viv_s44 = in_v_end; + viv_s46 = in_cfg_upd; + in_ack = viv_s39; + out_pix_data = viv_s35; + out_val = viv_s36; + out_h_end = viv_s37; + out_v_end = viv_s38; + viv_s49 = viv_s48; + viv_s45 = out_ack; + end + else + begin + viv_s41 = 8'b0; + viv_s42 = 1'b0; + viv_s43 = 1'b0; + viv_s44 = 1'b0; + viv_s46 = 1'b0; + in_ack = out_ack; + out_pix_data = in_pix_data; + out_val = in_val; + out_h_end = in_h_end; + out_v_end = in_v_end; + viv_s49 = in_cfg_upd; + viv_s45 = 1'b0; + end + end + assign out_cfg_upd = viv_s49; + always @(*) + begin : proc_calc + viv_s10 = ({1'b0, viv_s8}) + ({1'b0, viv_s11}); + if (scale_h_up_sdw) begin + viv_s12 = {viv_s20[c_scale_h - 1:10], viv_s3[7:0], 2'b00}; + viv_s13 = viv_s9; + viv_s14 = ({viv_s20[c_scale_h - 1:10], viv_s41, 2'b00}); + viv_s15 = viv_s9; + end + else begin + if ((viv_s10[c_scale_h]) == 1'b1) begin + viv_s12 = {viv_s20[c_scale_h - 1:10], viv_s41, 2'b00}; + viv_s13 = viv_s10[c_scale_h - 1:0]; + end + else begin + viv_s12 = {viv_s20[c_scale_h - 1:10], viv_s41, 2'b00}; + if (viv_s0) + viv_s13 = viv_s11+phase_h_sdw; + else + viv_s13 = viv_s11; + end + viv_s14 = {viv_s20[c_scale_h - 1:10], viv_s41, 2'b00}; + viv_s15 = viv_s8; + end + end + vsisp_self_hor_mult u_self_hor_mult + ( + .a_y1(viv_s16), + .b_y1(viv_s17), + .a_y2(viv_s18), + .b_y2(viv_s19), + .mult_y1(viv_s6), + .mult_y2(viv_s7)); + assign viv_s16 = viv_s12; + assign viv_s17 = viv_s13; + assign viv_s18 = viv_s14; + assign viv_s19 = viv_s15; + assign viv_s4 = {2'b0, viv_s6[(c_scale_h * 2) - 1:2]}; + assign viv_s5 = {2'b0, viv_s7[(c_scale_h * 2) - 1:2]}; + always @(posedge clk or negedge reset_n) + begin : proc_scale_regs + if (~reset_n) begin + viv_s3 <= {c_lbuf_h{1'b0}}; + viv_s0 <= 1'b1; + viv_s1 <= 1'b0; + viv_s8 <= {c_scale_h{1'b0}}; + viv_s2 <= c_idle; + viv_s40 <= 1'b1; + viv_s35 <= 8'b0; + viv_s36 <= 1'b0; + viv_s37 <= 1'b0; + viv_s38 <= 1'b0; + viv_s48 <= 1'b0; + viv_s51 <= 20'd0; + end + else begin + if (soft_rst) + begin + viv_s3 <= {c_lbuf_h{1'b0}}; + viv_s0 <= 1'b1; + viv_s1 <= 1'b0; + viv_s8 <= phase_h_sdw; + viv_s2 <= c_idle; + viv_s40 <= 1'b1; + viv_s35 <= 8'b0; + viv_s36 <= 1'b0; + viv_s37 <= 1'b0; + viv_s38 <= 1'b0; + viv_s48 <= 1'b0; + viv_s51 <= 20'd0; + end + else + begin + if (out_val & out_ack) begin + if (out_h_end) begin + viv_s51 <= 20'd0; + end else begin + viv_s51 <= viv_s51 + 20'd1; + end + end + viv_s0 <= viv_s24; + viv_s1 <= viv_s25; + viv_s2 <= viv_s27; + viv_s40 <= viv_s28; + viv_s8 <= viv_s26; + if (viv_s50) + begin + viv_s3 <= {c_lbuf_h{1'b0}}; + viv_s8 <= phase_h; + end + else + begin + viv_s3 <= viv_s23; + viv_s8 <= viv_s26; + end + viv_s35 <= viv_s29; + viv_s36 <= viv_s30; + viv_s37 <= viv_s31; + viv_s38 <= viv_s32; + viv_s48 <= viv_s47; + end + end + end + always @(*) + begin : proc_scale + viv_s23 = viv_s3; + viv_s24 = viv_s0; + viv_s25 = viv_s1; + viv_s26 = viv_s8; + viv_s27 = viv_s2; + viv_s28 = viv_s40; + viv_s29 = viv_s35; + viv_s30 = viv_s36; + viv_s31 = viv_s37; + viv_s32 = viv_s38; + viv_s47 = viv_s48; + viv_s33 = {c_lbuf_h + 2{1'b0}}; + viv_s34 = 10'b0; + if (viv_s36 & viv_s45) begin + viv_s30 = 1'b0; + viv_s31 = 1'b0; + viv_s47 = 1'b0; + if (viv_s37 & viv_s38) begin + viv_s32 = 1'b0; + end + end + if (viv_s46 & viv_s42 & viv_s39 ) viv_s47 = 1'b1; + else viv_s47 = 1'b0; + viv_s28 = viv_s45; + if (~scale_h_up_sdw) begin + if (viv_s42 & viv_s39) begin + if ((viv_s10[c_scale_h]) | viv_s43) begin + viv_s30 = 1'b1; + viv_s34 = viv_s3[c_lbuf_h - 1:c_lbuf_h - 10] + + ({viv_s41, 2'b10}) - + viv_s5[c_scale_h + 7:c_scale_h - 2]; + viv_s29 = viv_s34[9:2]; + viv_s33 = viv_s4[c_scale_h + 7: + c_scale_h - c_lbuf_h + 6]; + viv_s32 = viv_s44; + end + else begin + viv_s33 = ({viv_s3, 2'b00}) + + viv_s4[c_scale_h + 7:c_scale_h - c_lbuf_h + 6]; + end + viv_s23 = viv_s33[c_lbuf_h + 1:2]; + viv_s26 = viv_s10[c_scale_h - 1:0]; + viv_s24 = 1'b0; + if (viv_s43) begin + viv_s31 = 1'b1; + viv_s23 = {c_lbuf_h{1'b0}}; + viv_s26 = phase_h_sdw; + viv_s24 = 1'b1; + end + end + end + else begin + if (viv_s45) begin + if ((viv_s10[c_scale_h]) == 1'b0 & ~viv_s0) begin + viv_s28 = 1'b0; + end + if (viv_s1) begin + if (viv_s42) begin + if (~viv_s21[c_scale_h] + & (|viv_s21[c_scale_h:0])) begin + viv_s31 = 1'b1; + viv_s30 = 1'b1; + viv_s29 = (viv_s3[7:0]); + viv_s32 = viv_s44; + viv_s26 = phase_h_sdw; + viv_s23 = {c_lbuf_h{1'b0}}; + viv_s24 = 1'b1; + viv_s27 = c_output; + viv_s28 = viv_s45; + viv_s25 = 1'b0; + end else begin + viv_s31 = 1'b0; + viv_s30 = 1'b1; + viv_s29 = (viv_s3[7:0]); + viv_s32 = viv_s44; + viv_s26 = viv_s10[c_scale_h - 1:0]; + viv_s27 = c_output; + viv_s28 = 1'b0; + viv_s25 = 1'b1; + end + end + end else begin + if (viv_s42) begin + if (~viv_s0 | ~(|phase_h_sdw)) begin + viv_s30 = 1'b1; + if (viv_s0)begin + viv_s34 = ({viv_s41, 2'b00}); + end + else begin + viv_s34 = (({viv_s3[7:0], 2'b00}) + + viv_s5[c_scale_h + 7:c_scale_h - 2] - + viv_s4[c_scale_h + 7:c_scale_h - 2]); + end + viv_s29 = viv_s34[9:2]; + viv_s31 = viv_s43 & viv_s22; + viv_s32 = viv_s44; + viv_s27 = c_output; + viv_s26 = viv_s10[c_scale_h - 1:0]; + if (viv_s43) begin + if (viv_s22) begin + viv_s26 = phase_h_sdw; + viv_s23 = {c_lbuf_h{1'b0}}; + viv_s24 = 1'b1; + end else begin + viv_s28 = 1'b0; + if (viv_s10[c_scale_h]) + viv_s25 = 1'b1; + end + end + end + if ((viv_s10[c_scale_h]) | viv_s0) begin + viv_s23 = {viv_s20[c_lbuf_h - 9:0],viv_s41}; + if (viv_s0) viv_s24 = 1'b0; + if (~viv_s43 | viv_s22) + viv_s28 = viv_s45; + end + else begin + viv_s28 = 1'b0; + end + end + else begin + if (viv_s2 == c_output) begin + viv_s30 = 1'b0; + viv_s27 = c_idle; + end + end + end + end else begin + if (viv_s2 == c_output) begin + viv_s28 = 1'b0; + end + end + end + end + assign viv_s39 = viv_s28; + assign scale_h_lut_ad = (viv_s8[c_scale_h - 1:c_scale_h - c_scale_lut_addr]); + assign viv_s9 = {(scale_h_lut), viv_s20[c_scale_h - c_scale_lut - 1:0]}; +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_self_resize.v b/ispyocto/rtl/ispyocto/vsisp_self_resize.v new file mode 100644 index 0000000..2bbce4a --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_self_resize.v
@@ -0,0 +1,337 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_self_resize + (clk, + reset_n, + soft_rst, + in_y_pix_data, + in_y_val, + in_y_h_end, + in_y_v_end, + in_y_cfg_upd, + in_y_ack, + out_y_pix_data, + out_y_val, + out_y_h_end, + out_y_v_end, + out_y_cfg_upd, + out_y_ack, + ram_y_wr_n, + ram_y_cs_n, + ram_y_addr, + ram_y_wdata, + ram_y_rdata, + in_c_pix_data, + in_c_val, + in_c_h_end, + in_c_v_end, + in_c_cfg_upd, + in_c_ack, + out_c_pix_data, + out_c_val, + out_c_h_end, + out_c_v_end, + out_c_cfg_upd, + out_c_ack, + ram_c_wr_n, + ram_c_cs_n, + ram_c_addr, + ram_c_wdata, + ram_c_rdata, + cfg_upd, + gen_cfg_upd, + scale_hy_en, + scale_hc_en, + scale_vy_en, + scale_vc_en, + scale_hy_up, + scale_hc_up, + scale_vy_up, + scale_vc_up, + scale_hy, + scale_hcb, + scale_hcr, + scale_vy, + scale_vc, + phase_hy, + phase_hc, + phase_vy, + phase_vc, + y_scale_h_lut_ad, + y_scale_v_lut_ad, + y_scale_h_lut, + y_scale_v_lut, + chroma_scale_h_lut_ad, + chroma_scale_v_lut_ad, + chroma_scale_h_lut, + chroma_scale_v_lut, + scale_hy_en_sdw, + scale_hc_en_sdw, + scale_vy_en_sdw, + scale_vc_en_sdw, + scale_hy_up_sdw, + scale_hc_up_sdw, + scale_vy_up_sdw, + scale_vc_up_sdw, + scale_hy_sdw, + scale_hcb_sdw, + scale_hcr_sdw, + scale_vy_sdw, + scale_vc_sdw, + phase_hy_sdw, + phase_hc_sdw, + phase_vy_sdw, + phase_vc_sdw +); +`include "vsisp_self_resize.vh" + input clk; + input reset_n; + input soft_rst; + input [7:0] in_y_pix_data; + input in_y_val; + input in_y_h_end; + input in_y_v_end; + input in_y_cfg_upd; + output in_y_ack; + output [7:0] out_y_pix_data; + output out_y_val; + output out_y_h_end; + output out_y_v_end; + output out_y_cfg_upd; + input out_y_ack; + output ram_y_wr_n; + output ram_y_cs_n; + output [c_ram_width-1:0] ram_y_addr; + output [31:0] ram_y_wdata; + input [31:0] ram_y_rdata; + input [7:0] in_c_pix_data; + input in_c_val; + input in_c_h_end; + input in_c_v_end; + input in_c_cfg_upd; + output in_c_ack; + output [7:0] out_c_pix_data; + output out_c_val; + output out_c_h_end; + output out_c_v_end; + output out_c_cfg_upd; + input out_c_ack; + output ram_c_wr_n; + output ram_c_cs_n; + output [c_ram_width-1:0] ram_c_addr; + output [31:0] ram_c_wdata; + input [31:0] ram_c_rdata; + input cfg_upd; + input gen_cfg_upd; + input scale_hy_en; + input scale_hc_en; + input scale_vy_en; + input scale_vc_en; + input scale_hy_up; + input scale_hc_up; + input scale_vy_up; + input scale_vc_up; + input [c_scale_h - 1:0] scale_hy; + input [c_scale_h - 1:0] scale_hcb; + input [c_scale_h - 1:0] scale_hcr; + input [c_scale_v - 1:0] scale_vy; + input [c_scale_v - 1:0] scale_vc; + input [c_phase_h - 1:0] phase_hy; + input [c_scale_v - 1:0] phase_hc; + input [c_phase_h - 1:0] phase_vy; + input [c_scale_v - 1:0] phase_vc; + output [c_scale_lut_addr - 1:0] y_scale_h_lut_ad; + output [c_scale_lut_addr - 1:0] y_scale_v_lut_ad; + input [c_scale_lut - 1:0] y_scale_h_lut; + input [c_scale_lut - 1:0] y_scale_v_lut; + output [c_scale_lut_addr - 1:0] chroma_scale_h_lut_ad; + output [c_scale_lut_addr - 1:0] chroma_scale_v_lut_ad; + input [c_scale_lut - 1:0] chroma_scale_h_lut; + input [c_scale_lut - 1:0] chroma_scale_v_lut; + output scale_hy_en_sdw; + output scale_hc_en_sdw; + output scale_vy_en_sdw; + output scale_vc_en_sdw; + output scale_hy_up_sdw; + output scale_hc_up_sdw; + output scale_vy_up_sdw; + output scale_vc_up_sdw; + output [c_scale_h - 1:0] scale_hy_sdw; + output [c_scale_h - 1:0] scale_hcb_sdw; + output [c_scale_h - 1:0] scale_hcr_sdw; + output [c_scale_v - 1:0] scale_vy_sdw; + output [c_scale_v - 1:0] scale_vc_sdw; + output [c_scale_h - 1:0] phase_hy_sdw; + output [c_scale_h - 1:0] phase_hc_sdw; + output [c_scale_v - 1:0] phase_vy_sdw; + output [c_scale_v - 1:0] phase_vc_sdw; + wire[7:0] viv_s0; + wire viv_s1; + wire viv_s2; + wire viv_s3; + wire viv_s4; + wire viv_s5; + wire [7:0] viv_s6; + wire viv_s7; + wire viv_s8; + wire viv_s9; + wire viv_s10; + wire viv_s11; + wire[7:0] viv_s12; + wire viv_s13; + wire viv_s14; + wire viv_s15; + wire viv_s16; + wire viv_s17; + wire [7:0] viv_s18; + wire viv_s19; + wire viv_s20; + wire viv_s21; + wire viv_s22; + wire viv_s23; + vsisp_self_rsz_dpsbe u2_self_y_rsz_dpsbe + ( + .clk(clk), + .reset_n(reset_n), + .soft_rst(soft_rst), + .in_pix_data (viv_s6), + .in_val (viv_s7), + .in_h_end (viv_s8), + .in_v_end (viv_s9), + .in_cfg_upd (viv_s10), + .in_ack (viv_s11), + .out_pix_data (out_y_pix_data), + .out_val (out_y_val), + .out_h_end (out_y_h_end), + .out_v_end (out_y_v_end), + .out_cfg_upd (out_y_cfg_upd), + .out_ack (out_y_ack)); + vsisp_self_rsz_dpsbe u2_self_c_rsz_dpsbe + ( + .clk(clk), + .reset_n(reset_n), + .soft_rst(soft_rst), + .in_pix_data (viv_s18), + .in_val (viv_s19), + .in_h_end (viv_s20), + .in_v_end (viv_s21), + .in_cfg_upd (viv_s22), + .in_ack (viv_s23), + .out_pix_data (out_c_pix_data), + .out_val (out_c_val), + .out_h_end (out_c_h_end), + .out_v_end (out_c_v_end), + .out_cfg_upd (out_c_cfg_upd), + .out_ack (out_c_ack)); + vsisp_self_resize_scale u_self_y_resize_scale + ( + .clk(clk), + .reset_n(reset_n), + .soft_rst(soft_rst), + .cfg_upd(cfg_upd), + .gen_cfg_upd(gen_cfg_upd), + .scale_h_en(scale_hy_en), + .scale_v_en(scale_vy_en), + .scale_h_up(scale_hy_up), + .scale_v_up(scale_vy_up), + .scale_h(scale_hy), + .scale_v(scale_vy), + .phase_h(phase_hy), + .phase_v(phase_vy), + .scale_h_lut_ad(y_scale_h_lut_ad), + .scale_v_lut_ad(y_scale_v_lut_ad), + .scale_h_lut(y_scale_h_lut), + .scale_v_lut(y_scale_v_lut), + .scale_h_en_sdw(scale_hy_en_sdw), + .scale_v_en_sdw(scale_vy_en_sdw), + .scale_h_up_sdw(scale_hy_up_sdw), + .scale_v_up_sdw(scale_vy_up_sdw), + .scale_h_sdw(scale_hy_sdw), + .scale_v_sdw(scale_vy_sdw), + .phase_h_sdw(phase_hy_sdw), + .phase_v_sdw(phase_vy_sdw), + .in_pix_data(in_y_pix_data), + .in_val(in_y_val), + .in_h_end(in_y_h_end), + .in_v_end(in_y_v_end), + .in_cfg_upd(in_y_cfg_upd), + .in_ack(in_y_ack), + .out_pix_data(viv_s6), + .out_val(viv_s7), + .out_h_end(viv_s8), + .out_v_end(viv_s9), + .out_cfg_upd(viv_s10), + .out_ack(viv_s11), + .ram_wr_n(ram_y_wr_n), + .ram_cs_n(ram_y_cs_n), + .ram_addr(ram_y_addr), + .ram_wdata(ram_y_wdata), + .ram_rdata(ram_y_rdata)); + vsisp_self_resize_c_scale u_self_resize_c_scale + ( + .clk(clk), + .reset_n(reset_n), + .soft_rst(soft_rst), + .cfg_upd(cfg_upd), + .gen_cfg_upd(gen_cfg_upd), + .scale_h_en(scale_hc_en), + .scale_v_en(scale_vc_en), + .scale_h_up(scale_hc_up), + .scale_v_up(scale_vc_up), + .scale_hcb(scale_hcb), + .scale_hcr(scale_hcr), + .scale_v(scale_vc), + .phase_h(phase_hc), + .phase_v(phase_vc), + .scale_h_lut_ad(chroma_scale_h_lut_ad), + .scale_v_lut_ad(chroma_scale_v_lut_ad), + .scale_h_lut(chroma_scale_h_lut), + .scale_v_lut(chroma_scale_v_lut), + .scale_h_en_sdw(scale_hc_en_sdw), + .scale_v_en_sdw(scale_vc_en_sdw), + .scale_h_up_sdw(scale_hc_up_sdw), + .scale_v_up_sdw(scale_vc_up_sdw), + .scale_hcb_sdw(scale_hcb_sdw), + .scale_hcr_sdw(scale_hcr_sdw), + .scale_v_sdw(scale_vc_sdw), + .phase_h_sdw(phase_hc_sdw), + .phase_v_sdw(phase_vc_sdw), + .in_pix_data(in_c_pix_data), + .in_val(in_c_val), + .in_h_end(in_c_h_end), + .in_v_end(in_c_v_end), + .in_cfg_upd(in_c_cfg_upd), + .in_ack(in_c_ack), + .out_pix_data(viv_s18), + .out_val(viv_s19), + .out_h_end(viv_s20), + .out_v_end(viv_s21), + .out_cfg_upd(viv_s22), + .out_ack(viv_s23), + .ram_wr_n(ram_c_wr_n), + .ram_cs_n(ram_c_cs_n), + .ram_addr(ram_c_addr), + .ram_wdata(ram_c_wdata), + .ram_rdata(ram_c_rdata)); +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_self_resize_c_scale.v b/ispyocto/rtl/ispyocto/vsisp_self_resize_c_scale.v new file mode 100644 index 0000000..bfb7073 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_self_resize_c_scale.v
@@ -0,0 +1,188 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_self_resize_c_scale + ( + clk, + reset_n, + soft_rst, + cfg_upd, + gen_cfg_upd, + scale_h_en, + scale_v_en, + scale_h_up, + scale_v_up, + scale_hcb, + scale_hcr, + scale_v, + phase_h, + phase_v, + scale_h_lut_ad, + scale_v_lut_ad, + scale_h_lut, + scale_v_lut, + scale_h_en_sdw, + scale_v_en_sdw, + scale_h_up_sdw, + scale_v_up_sdw, + scale_hcb_sdw, + scale_hcr_sdw, + scale_v_sdw, + phase_h_sdw, + phase_v_sdw, + in_pix_data, + in_val, + in_h_end, + in_v_end, + in_cfg_upd, + in_ack, + out_pix_data, + out_val, + out_h_end, + out_v_end, + out_cfg_upd, + out_ack, + ram_wr_n, + ram_cs_n, + ram_addr, + ram_wdata, + ram_rdata); +`include "vsisp_self_resize.vh" + input clk; + input reset_n; + input soft_rst; + input cfg_upd; + input gen_cfg_upd; + input scale_h_en; + input scale_v_en; + input scale_h_up; + input scale_v_up; + input [c_scale_h - 1:0] scale_hcb; + input [c_scale_h - 1:0] scale_hcr; + input [c_scale_v - 1:0] scale_v; + input [c_phase_h - 1:0] phase_h; + input [c_phase_v - 1:0] phase_v; + output [c_scale_lut_addr - 1:0] scale_h_lut_ad; + wire [c_scale_lut_addr - 1:0] scale_h_lut_ad; + output [c_scale_lut_addr - 1:0] scale_v_lut_ad; + wire [c_scale_lut_addr - 1:0] scale_v_lut_ad; + input [c_scale_lut - 1:0] scale_h_lut; + input [c_scale_lut - 1:0] scale_v_lut; + output scale_h_en_sdw; + output scale_v_en_sdw; + output scale_h_up_sdw; + output scale_v_up_sdw; + output [c_scale_h - 1:0] scale_hcb_sdw; + output [c_scale_h - 1:0] scale_hcr_sdw; + output [c_scale_v - 1:0] scale_v_sdw; + output [c_scale_h - 1:0] phase_h_sdw; + output [c_scale_v - 1:0] phase_v_sdw; + input [7:0] in_pix_data; + input in_val; + input in_h_end; + input in_v_end; + input in_cfg_upd; + output in_ack; + output [7:0] out_pix_data; + output out_val; + output out_h_end; + output out_v_end; + output out_cfg_upd; + input out_ack; + output ram_wr_n; + output ram_cs_n; + output [c_ram_width-1:0] ram_addr; + output [31:0] ram_wdata; + input [31:0] ram_rdata; + wire [7:0] viv_s0; + wire viv_s1; + wire viv_s2; + wire viv_s3; + wire viv_s4; + wire viv_s5; + vsisp_self_hor_c_scale u_self_hor_c_scale + ( + .clk(clk), + .reset_n(reset_n), + .soft_rst(soft_rst), + .cfg_upd(cfg_upd), + .gen_cfg_upd(gen_cfg_upd), + .scale_h_en(scale_h_en), + .scale_h_up(scale_h_up), + .scale_hcb(scale_hcb), + .scale_hcr(scale_hcr), + .phase_h(phase_h), + .scale_h_lut_ad(scale_h_lut_ad), + .scale_h_lut(scale_h_lut), + .scale_h_en_sdw(scale_h_en_sdw), + .scale_h_up_sdw(scale_h_up_sdw), + .scale_hcb_sdw(scale_hcb_sdw), + .scale_hcr_sdw(scale_hcr_sdw), + .phase_h_sdw(phase_h_sdw), + .in_pix_data(in_pix_data), + .in_val(in_val), + .in_h_end(in_h_end), + .in_v_end(in_v_end), + .in_cfg_upd(in_cfg_upd), + .in_ack(in_ack), + .out_pix_data(viv_s0), + .out_val(viv_s1), + .out_h_end(viv_s2), + .out_v_end(viv_s3), + .out_cfg_upd(viv_s4), + .out_ack(viv_s5)); + vsisp_self_vert_scale u_self_vert_scale + ( + .clk(clk), + .reset_n(reset_n), + .soft_rst(soft_rst), + .cfg_upd(cfg_upd), + .gen_cfg_upd(gen_cfg_upd), + .scale_v_en(scale_v_en), + .scale_v_up(scale_v_up), + .scale_v(scale_v), + .phase_v(phase_v), + .scale_v_lut_ad(scale_v_lut_ad), + .scale_v_lut(scale_v_lut), + .scale_v_en_sdw(scale_v_en_sdw), + .scale_v_up_sdw(scale_v_up_sdw), + .scale_v_sdw(scale_v_sdw), + .phase_v_sdw(phase_v_sdw), + .in_pix_data(viv_s0), + .in_val(viv_s1), + .in_h_end(viv_s2), + .in_v_end(viv_s3), + .in_cfg_upd(viv_s4), + .in_ack(viv_s5), + .out_pix_data(out_pix_data), + .out_val(out_val), + .out_h_end(out_h_end), + .out_v_end(out_v_end), + .out_cfg_upd(out_cfg_upd), + .out_ack(out_ack), + .ram_wr_n(ram_wr_n), + .ram_cs_n(ram_cs_n), + .ram_addr(ram_addr), + .ram_wdata(ram_wdata), + .ram_rdata(ram_rdata)); +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_self_resize_scale.v b/ispyocto/rtl/ispyocto/vsisp_self_resize_scale.v new file mode 100644 index 0000000..cdc85ee --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_self_resize_scale.v
@@ -0,0 +1,182 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_self_resize_scale + ( + clk, + reset_n, + soft_rst, + cfg_upd, + gen_cfg_upd, + scale_h_en, + scale_v_en, + scale_h_up, + scale_v_up, + scale_h, + scale_v, + phase_h, + phase_v, + scale_h_lut_ad, + scale_v_lut_ad, + scale_h_lut, + scale_v_lut, + scale_h_en_sdw, + scale_v_en_sdw, + scale_h_up_sdw, + scale_v_up_sdw, + scale_h_sdw, + scale_v_sdw, + phase_h_sdw, + phase_v_sdw, + in_pix_data, + in_val, + in_h_end, + in_v_end, + in_cfg_upd, + in_ack, + out_pix_data, + out_val, + out_h_end, + out_v_end, + out_cfg_upd, + out_ack, + ram_wr_n, + ram_cs_n, + ram_addr, + ram_wdata, + ram_rdata); +`include "vsisp_self_resize.vh" + input clk; + input reset_n; + input soft_rst; + input cfg_upd; + input gen_cfg_upd; + input scale_h_en; + input scale_v_en; + input scale_h_up; + input scale_v_up; + input [c_scale_h - 1:0] scale_h; + input [c_scale_v - 1:0] scale_v; + input [c_phase_h - 1:0] phase_h; + input [c_phase_v - 1:0] phase_v; + output [c_scale_lut_addr - 1:0] scale_h_lut_ad; + wire [c_scale_lut_addr - 1:0] scale_h_lut_ad; + output [c_scale_lut_addr - 1:0] scale_v_lut_ad; + wire [c_scale_lut_addr - 1:0] scale_v_lut_ad; + input [c_scale_lut - 1:0] scale_h_lut; + input [c_scale_lut - 1:0] scale_v_lut; + input [7:0] in_pix_data; + input in_val; + input in_h_end; + input in_v_end; + input in_cfg_upd; + output in_ack; + output scale_h_en_sdw; + output scale_v_en_sdw; + output scale_h_up_sdw; + output scale_v_up_sdw; + output [c_scale_h - 1:0] scale_h_sdw; + output [c_scale_v - 1:0] scale_v_sdw; + output [c_scale_h - 1:0] phase_h_sdw; + output [c_scale_v - 1:0] phase_v_sdw; + output [7:0] out_pix_data; + output out_val; + output out_h_end; + output out_v_end; + output out_cfg_upd; + input out_ack; + output ram_wr_n; + output ram_cs_n; + output [c_ram_width-1:0] ram_addr; + output [31:0] ram_wdata; + input [31:0] ram_rdata; + wire [7:0] viv_s0; + wire viv_s1; + wire viv_s2; + wire viv_s3; + wire viv_s4; + wire viv_s5; + vsisp_self_hor_scale u_self_hor_scale + ( + .clk(clk), + .reset_n(reset_n), + .soft_rst(soft_rst), + .cfg_upd(cfg_upd), + .gen_cfg_upd(gen_cfg_upd), + .scale_h_en(scale_h_en), + .scale_h_up(scale_h_up), + .scale_h(scale_h), + .phase_h(phase_h), + .scale_h_lut_ad(scale_h_lut_ad), + .scale_h_lut(scale_h_lut), + .scale_h_en_sdw(scale_h_en_sdw), + .scale_h_up_sdw(scale_h_up_sdw), + .scale_h_sdw(scale_h_sdw), + .phase_h_sdw(phase_h_sdw), + .in_pix_data(in_pix_data), + .in_val(in_val), + .in_h_end(in_h_end), + .in_v_end(in_v_end), + .in_cfg_upd(in_cfg_upd), + .in_ack(in_ack), + .out_pix_data(viv_s0), + .out_val(viv_s1), + .out_h_end(viv_s2), + .out_v_end(viv_s3), + .out_cfg_upd(viv_s4), + .out_ack(viv_s5)); + vsisp_self_vert_scale u_self_vert_scale + ( + .clk(clk), + .reset_n(reset_n), + .soft_rst(soft_rst), + .cfg_upd(cfg_upd), + .gen_cfg_upd(gen_cfg_upd), + .scale_v_en(scale_v_en), + .scale_v_up(scale_v_up), + .scale_v(scale_v), + .phase_v(phase_v), + .scale_v_lut_ad(scale_v_lut_ad), + .scale_v_lut(scale_v_lut), + .scale_v_en_sdw(scale_v_en_sdw), + .scale_v_up_sdw(scale_v_up_sdw), + .scale_v_sdw(scale_v_sdw), + .phase_v_sdw(phase_v_sdw), + .in_pix_data(viv_s0), + .in_val(viv_s1), + .in_h_end(viv_s2), + .in_v_end(viv_s3), + .in_cfg_upd(viv_s4), + .in_ack(viv_s5), + .out_pix_data(out_pix_data), + .out_val(out_val), + .out_h_end(out_h_end), + .out_v_end(out_v_end), + .out_cfg_upd(out_cfg_upd), + .out_ack(out_ack), + .ram_wr_n(ram_wr_n), + .ram_cs_n(ram_cs_n), + .ram_addr(ram_addr), + .ram_wdata(ram_wdata), + .ram_rdata(ram_rdata)); +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_self_rsz_dpsbe.v b/ispyocto/rtl/ispyocto/vsisp_self_rsz_dpsbe.v new file mode 100644 index 0000000..f6be34a --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_self_rsz_dpsbe.v
@@ -0,0 +1,119 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_self_rsz_dpsbe + (clk, + reset_n, + soft_rst, + in_pix_data, + in_val, + in_h_end, + in_v_end, + in_cfg_upd, + in_ack, + out_pix_data, + out_val, + out_h_end, + out_v_end, + out_cfg_upd, + out_ack); + input clk; + input reset_n; + input soft_rst; + input [7:0] in_pix_data; + input in_val; + input in_h_end; + input in_v_end; + input in_cfg_upd; + output in_ack; + output [7:0] out_pix_data; + wire [7:0] out_pix_data; + output out_val; + output out_h_end; + output out_v_end; + output out_cfg_upd; + input out_ack; + reg [7:0] viv_s0; + reg viv_s1; + reg viv_s2; + reg viv_s3; + reg viv_s4; + reg viv_s5; + reg [7:0] viv_s6; + reg viv_s7; + reg viv_s8; + reg viv_s9; + reg viv_s10; + reg viv_s11; + always @(posedge clk or negedge reset_n) + begin : sync_dpsbe_proc + if (~reset_n) begin + viv_s6 <= 8'b0; + viv_s7 <= 1'b0; + viv_s8 <= 1'b0; + viv_s9 <= 1'b0; + viv_s10 <= 1'b0; + viv_s11 <= 1'b0; + end + else begin + if (soft_rst) begin + viv_s7 <= 1'b0; + viv_s11 <= 1'b0; + end else begin + viv_s11 <= ~(~out_ack & viv_s1); + if (viv_s11) begin + viv_s6 <= in_pix_data; + viv_s7 <= in_val; + viv_s8 <= in_h_end; + viv_s9 <= in_v_end; + viv_s10 <= in_cfg_upd; + end + end + end + end + always @(*) begin : comb_dpsbe_proc + viv_s5 = viv_s11; + if (viv_s11) + begin + viv_s0 = in_pix_data; + viv_s1 = in_val; + viv_s2 = in_h_end; + viv_s3 = in_v_end; + viv_s4 = in_cfg_upd; + end + else + begin + viv_s0 = viv_s6; + viv_s1 = viv_s7; + viv_s2 = viv_s8; + viv_s3 = viv_s9; + viv_s4 = viv_s10; + end + end + assign out_pix_data = viv_s0; + assign out_val = viv_s1; + assign out_h_end = viv_s2; + assign out_v_end = viv_s3; + assign out_cfg_upd = viv_s4; + assign in_ack = viv_s5; +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_self_vert_mult.v b/ispyocto/rtl/ispyocto/vsisp_self_vert_mult.v new file mode 100644 index 0000000..ffacac7 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_self_vert_mult.v
@@ -0,0 +1,49 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_self_vert_mult + (a_y1, + b_y1, + a_y2, + b_y2, + mult_y1, + mult_y2); +`include "vsisp_self_resize.vh" + input [c_scale_v - 1:0] a_y1; + input [c_scale_v - 1:0] b_y1; + input [c_scale_v - 1:0] a_y2; + input [c_scale_v - 1:0] b_y2; + output [(c_scale_v * 2) - 1:0] mult_y1; + reg [(c_scale_v * 2) - 1:0] mult_y1; + output [(c_scale_v * 2) - 1:0] mult_y2; + reg [(c_scale_v * 2) - 1:0] mult_y2; + reg [(c_scale_v * 2) - 5:0] viv_s0; + reg [(c_scale_v * 2) - 5:0] viv_s1; + always @(*) + begin : proc_calc + viv_s0 = a_y1[c_scale_v - 1:2] * b_y1[c_scale_v - 1:2]; + viv_s1 = a_y2[c_scale_v - 1:2] * b_y2[c_scale_v - 1:2]; + mult_y1 = {viv_s0,4'b0}; + mult_y2 = {viv_s1,4'b0}; + end +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_self_vert_scale.v b/ispyocto/rtl/ispyocto/vsisp_self_vert_scale.v new file mode 100644 index 0000000..af980ed --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_self_vert_scale.v
@@ -0,0 +1,1196 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_self_vert_scale + ( + clk, + reset_n, + soft_rst, + cfg_upd, + gen_cfg_upd, + scale_v_en, + scale_v_up, + scale_v, + phase_v, + scale_v_lut_ad, + scale_v_lut, + scale_v_en_sdw, + scale_v_up_sdw, + scale_v_sdw, + phase_v_sdw, + in_pix_data, + in_val, + in_h_end, + in_v_end, + in_cfg_upd, + in_ack, + out_pix_data, + out_val, + out_h_end, + out_v_end, + out_cfg_upd, + out_ack, + ram_wr_n, + ram_cs_n, + ram_addr, + ram_wdata, + ram_rdata); +`include "vsisp_self_resize.vh" + input clk; + input reset_n; + input soft_rst; + input cfg_upd; + input gen_cfg_upd; + input scale_v_en; + input scale_v_up; + input [c_scale_v - 1:0] scale_v; + input [c_phase_v - 1:0] phase_v; + output [c_scale_lut_addr - 1:0] scale_v_lut_ad; + wire [c_scale_lut_addr - 1:0] scale_v_lut_ad; + input [c_scale_lut - 1:0] scale_v_lut; + input [7:0] in_pix_data; + input in_val; + input in_h_end; + input in_v_end; + output in_ack; + reg in_ack; + input in_cfg_upd; + output [7:0] out_pix_data; + reg [7:0] out_pix_data; + output out_val; + reg out_val; + output out_h_end; + reg out_h_end; + output out_v_end; + reg out_v_end; + output out_cfg_upd; + input out_ack; + output scale_v_en_sdw; + reg scale_v_en_sdw; + output scale_v_up_sdw; + reg scale_v_up_sdw; + output [c_scale_v - 1:0] scale_v_sdw; + reg [c_scale_v - 1:0] scale_v_sdw; + output [c_scale_v - 1:0] phase_v_sdw; + reg [c_scale_v - 1:0] phase_v_sdw; + output ram_wr_n; + output ram_cs_n; + output [c_ram_width-1:0] ram_addr; + reg [c_ram_width-1:0] ram_addr; + output [31:0] ram_wdata; + reg [31:0] ram_wdata; + input [31:0] ram_rdata; + reg viv_s0; + reg viv_s1; + reg viv_s2; + reg viv_s3; + reg viv_s4; + reg viv_s5; + reg viv_s6; + reg viv_s7; + reg [1:0] viv_s8; + parameter c_idle = 2'b00; + parameter c_second = 2'b01; + parameter c_between = 2'b10; + reg viv_s9; + reg viv_s10; + reg viv_s11; + reg viv_s12; + reg viv_s13; + reg [31:0] viv_s14; + reg viv_s15; + reg viv_s16; + reg [7:0] viv_s17; + reg viv_s18; + reg viv_s19; + reg viv_s20; + reg viv_s21; + reg [7:0] viv_s22; + reg viv_s23; + reg viv_s24; + reg viv_s25; + reg viv_s26; + reg viv_s27; + reg viv_s28; + reg viv_s29; + reg [15:0] viv_s30; + reg [15:0] viv_s31; + reg [c_ram_width:0] viv_s32; + reg [c_ram_width-1:0] viv_s33; + reg [c_ram_width-1:0] viv_s34; + reg [c_ram_width-1:0] viv_s35; + reg [c_ram_width-1:0] viv_s36; + reg [c_ram_width:0] viv_s37; + reg [31:0] viv_s38; + wire [(c_scale_v * 2) - 1:0] viv_s39; + wire [(c_scale_v * 2) - 1:0] viv_s40; + wire [(c_scale_v * 2) - 1:0] viv_s41; + wire [(c_scale_v * 2) - 1:0] viv_s42; + wire [c_scale_v - 1:0] viv_s43; + reg [c_scale_v - 1:0] viv_s44; + reg [c_scale_v:0] viv_s45; + wire [c_scale_v:0] viv_s46; + wire [c_scale_v - 1:0] viv_s47; + reg [c_scale_v - 1:0] viv_s48; + reg [c_scale_v - 1:0] viv_s49; + reg [c_scale_v - 1:0] viv_s50; + reg [c_scale_v - 1:0] viv_s51; + wire [c_scale_v - 1:0] viv_s52; + wire [c_scale_v - 1:0] viv_s53; + wire [c_scale_v - 1:0] viv_s54; + wire [c_scale_v - 1:0] viv_s55; + wire [63:0] viv_s56; + wire [7:0] viv_s57; + wire [c_scale_v :0] viv_s58; + wire viv_s59; + reg [15:0] viv_s60; + reg [15:0] viv_s61; + reg [15:0] viv_s62; + reg [15:0] viv_s63; + reg [15:0] viv_s64; + reg [15:0] viv_s65; + reg [c_lbuf_v + 1:0] viv_s66; + reg viv_s67; + reg viv_s68; + reg viv_s69; + reg viv_s70; + reg [c_scale_h - 1:0] viv_s71; + reg [1:0] viv_s72; + reg viv_s73; + reg viv_s74; + reg [7:0] viv_s75; + reg [9:0] viv_s76; + reg viv_s77; + reg viv_s78; + reg viv_s79; + reg viv_s80; + reg viv_s81; + reg viv_s82; + reg [c_ram_width:0] viv_s83; + reg [c_ram_width-1:0] viv_s84; + reg [c_ram_width-1:0] viv_s85; + reg [c_ram_width-1:0] viv_s86; + reg [c_ram_width:0] viv_s87; + reg [7:0] viv_s88; + reg viv_s89; + reg viv_s90; + reg viv_s91; + reg viv_s92; + reg [7:0] viv_s93; + reg viv_s94; + reg viv_s95; + reg viv_s96; + reg viv_s97; + reg viv_s98; + reg viv_s99; + reg viv_s100; + reg viv_s101; + reg viv_s102; + reg viv_s103; + reg viv_s104; + wire viv_s105; + wire viv_s106; + wire viv_s107; + wire viv_s108; + wire viv_s109; + wire viv_s110; + reg [19:0] viv_s111; + reg [19:0] viv_s112; + assign viv_s105 = (out_val & out_h_end & out_v_end & out_ack & (out_cfg_upd || gen_cfg_upd)) | + cfg_upd; + assign viv_s106 = viv_s89 & viv_s97 & viv_s90 & viv_s91; + assign viv_s107 = viv_s94 & viv_s92; + assign viv_s108 = viv_s79 & viv_s97; + assign viv_s109 = viv_s9 & viv_s10; + assign viv_s110 = (viv_s45[c_scale_v] & viv_s46[c_scale_v]); + assign viv_s47 = scale_v_sdw; + assign viv_s56 = 64'b0; + assign viv_s57 = 8'b0; + assign viv_s58 = viv_s45 - {1'b0, phase_v_sdw}; + assign viv_s59 = viv_s45[c_scale_v] & viv_s58[c_scale_v] + & |(viv_s58[c_scale_v-1:0]); + assign viv_s46 = viv_s45[c_scale_v-1:0] + viv_s47; + always @(posedge clk or negedge reset_n) + begin : proc_shadow + if (~reset_n) + begin + scale_v_en_sdw <= 1'b0; + scale_v_up_sdw <= 1'b0; + scale_v_sdw <= {c_scale_v{1'b0}}; + phase_v_sdw <= {c_scale_v{1'b0}}; + end + else + begin + if (viv_s105) + begin + scale_v_en_sdw <= scale_v_en; + scale_v_up_sdw <= scale_v_up; + scale_v_sdw <= scale_v; + phase_v_sdw <= phase_v; + end + end + end + always @(scale_v_en_sdw or in_pix_data or in_val or in_h_end or in_v_end or + viv_s21 or viv_s22 or viv_s23 or viv_s24 or + viv_s25 or out_ack or in_cfg_upd or viv_s99) + begin : proc_bypass + if (scale_v_en_sdw) + begin + viv_s17 = (in_pix_data[7:0]); + viv_s18 = in_val; + viv_s19 = in_h_end; + viv_s20 = in_v_end; + viv_s98 = in_cfg_upd; + in_ack = viv_s21; + out_pix_data = viv_s22; + out_val = viv_s23; + out_h_end = viv_s24; + out_v_end = viv_s25; + viv_s103 = viv_s99; + viv_s26 = out_ack; + end + else + begin + viv_s17 = 8'b0; + viv_s18 = 1'b0; + viv_s19 = 1'b0; + viv_s20 = 1'b0; + viv_s98 = 1'b0; + viv_s26 = 1'b0; + out_pix_data = in_pix_data; + out_val = in_val; + out_h_end = in_h_end; + out_v_end = in_v_end; + viv_s103 = in_cfg_upd; + in_ack = out_ack; + end + end + assign out_cfg_upd = viv_s103; + always @(viv_s17 or viv_s18 or viv_s19 or + viv_s20 or viv_s92 or viv_s27 or viv_s4 or viv_s98) + begin : proc_even_width + viv_s93 = viv_s17; + viv_s94 = viv_s18; + viv_s96 = viv_s20; + viv_s102 = viv_s98; + if (~viv_s27) + begin + if (viv_s18 & viv_s19 & ~viv_s4) + begin + if (viv_s92) + begin + viv_s28 = 1'b1; + end + else + begin + viv_s28 = 1'b0; + end + viv_s21 = 1'b0; + viv_s95 = 1'b0; + viv_s102 = 1'b0; + end + else + begin + viv_s28 = 1'b0; + viv_s21 = viv_s92; + viv_s95 = viv_s19; + viv_s102 = viv_s98; + end + end + else + begin + viv_s28 = ~viv_s92; + viv_s21 = viv_s92; + viv_s95 = viv_s19; + viv_s102 = viv_s98; + end + end + reg viv_s113; + always @(posedge clk or negedge reset_n) begin + if(~reset_n) begin + viv_s113 <= 1'b0; + end + else begin + if(viv_s102) begin + viv_s113 <= 1'b1; + end + if(viv_s89 & viv_s97 & viv_s90 & viv_s91) begin + viv_s113 <= 1'b0; + end + end + end + wire viv_s114 = viv_s102 || viv_s113; + always @(posedge clk or negedge reset_n) + begin : proc_add_pel_regs + if (~reset_n) + begin + viv_s27 <= 1'b0; + viv_s29 <= 1'b0; + end + else + begin + if (soft_rst) + begin + viv_s27 <= 1'b0; + viv_s29 <= 1'b0; + end + else + begin + viv_s27 <= viv_s28; + if (viv_s28) + begin + viv_s29 <= 1'b1; + end + if (viv_s106) + begin + viv_s29 <= 1'b0; + end + end + end + end + always @(viv_s88 or viv_s91 or viv_s26 or viv_s89 or viv_s90 or + viv_s29 or viv_s33 or viv_s6 or viv_s101 or viv_s100) + begin : proc_odd_width + viv_s22 = viv_s88; + viv_s25 = viv_s91; + viv_s97 = viv_s26; + if (~viv_s29) + begin + viv_s23 = viv_s89; + viv_s24 = viv_s90; + viv_s99 = viv_s101; + end + else + begin + if ((viv_s33 == {c_ram_width{1'b0}}) & (viv_s6 == 1'b0)) + begin + viv_s24 = viv_s89; + viv_s23 = viv_s89; + viv_s99 = viv_s100; + end + else + begin + viv_s24 = 1'b0; + viv_s23 = viv_s89 & ~viv_s90; + viv_s99 = 1'b0; + end + end + end + always @(viv_s90 or viv_s6 or viv_s108) + begin : proc_write_odd + if (viv_s108) + begin + if (viv_s90) + begin + viv_s74 = 1'b0; + end + else + begin + viv_s74 = ~viv_s6; + end + end + else + begin + viv_s74 = viv_s6; + end + end + always @(*) + begin : proc_calc + viv_s45 = ({1'b0, viv_s44}) + ({1'b0, viv_s47}); + if (scale_v_up_sdw) + begin + viv_s48 = {viv_s56[c_scale_v - 1:10], viv_s30[7:0], 2'b00}; + viv_s49 = viv_s43; + end + else + begin + if ((viv_s45[c_scale_v]) == 1'b1) + begin + viv_s48 = {viv_s56[c_scale_v - 1:10], viv_s93, 2'b00}; + viv_s49 = viv_s45[c_scale_v - 1:0]; + end + else + begin + viv_s48 = {viv_s56[c_scale_v - 1:10], viv_s93, 2'b00}; + if (viv_s0) + viv_s49 = viv_s47+phase_v_sdw; + else + viv_s49 = viv_s47; + end + end + if (viv_s8 == c_between) + begin + viv_s50 = ({viv_s56[c_scale_v - 1:10], viv_s30[15:8], 2'b00}); + viv_s51 = viv_s43; + end + else + begin + viv_s50 = ({viv_s56[c_scale_v - 1:10], viv_s93, 2'b00}); + if (scale_v_up_sdw) + begin + viv_s51 = viv_s43; + end + else + begin + viv_s51 = viv_s44; + end + end + end + vsisp_self_vert_mult u_self_vert_mult + ( + .a_y1(viv_s52), + .b_y1(viv_s53), + .a_y2(viv_s54), + .b_y2(viv_s55), + .mult_y1(viv_s41), + .mult_y2(viv_s42)); + assign viv_s52 = viv_s48; + assign viv_s53 = viv_s49; + assign viv_s54 = viv_s50; + assign viv_s55 = viv_s51; + assign viv_s39 = {2'b0, viv_s41[(c_scale_v * 2) - 1:2]}; + assign viv_s40 = {2'b0, viv_s42[(c_scale_v * 2) - 1:2]}; + always @(posedge clk or negedge reset_n) + begin : proc_scale_regs + if (~reset_n) + begin + viv_s44 <= {c_scale_v{1'b0}}; + viv_s4 <= 1'b0; + viv_s0 <= 1'b1; + viv_s1 <= 1'b1; + viv_s32 <= {c_ram_width+1{1'b0}}; + viv_s37 <= c_max_hsize-1; + viv_s6 <= 1'b0; + viv_s8 <= c_idle; + viv_s2 <= 1'b0; + viv_s3 <= 1'b0; + viv_s88 <= 8'b0; + viv_s89 <= 1'b0; + viv_s79 <= 1'b0; + viv_s90 <= 1'b0; + viv_s91 <= 1'b0; + viv_s101 <= 1'b0; + viv_s31 <= 16'b0; + viv_s104 <= 1'b0; + viv_s111 <= 20'd0; + viv_s112 <= 20'd0; + end + else + begin + if (soft_rst) + begin + viv_s44 <= phase_v_sdw; + viv_s4 <= 1'b0; + viv_s0 <= 1'b1; + viv_s1 <= 1'b1; + viv_s32 <= {c_ram_width+1{1'b0}}; + viv_s37 <= c_max_hsize-1; + viv_s6 <= 1'b0; + viv_s8 <= c_idle; + viv_s2 <= 1'b0; + viv_s3 <= 1'b0; + viv_s88 <= 8'b0; + viv_s89 <= 1'b0; + viv_s79 <= 1'b0; + viv_s90 <= 1'b0; + viv_s91 <= 1'b0; + viv_s101 <= 1'b0; + viv_s31 <= 16'b0; + viv_s104 <= 1'b0; + viv_s111 <= 20'd0; + viv_s112 <= 20'd0; + end + else + begin + viv_s4 <= viv_s82; + viv_s0 <= viv_s67; + viv_s1 <= viv_s68; + viv_s32 <= viv_s83; + viv_s37 <= viv_s87; + viv_s6 <= viv_s74; + viv_s8 <= viv_s72; + viv_s2 <= viv_s69; + viv_s3 <= viv_s70; + viv_s44 <= viv_s71; + if (viv_s105) + begin + viv_s44 <= phase_v; + end + else + begin + viv_s44 <= viv_s71; + end + viv_s88 <= viv_s75; + viv_s91 <= viv_s81; + viv_s90 <= viv_s80; + viv_s31 <= viv_s65; + viv_s101 <= viv_s100; + viv_s89 <= viv_s77; + viv_s79 <= viv_s78; + if (viv_s107) begin + viv_s104 <= viv_s96; + end + if (viv_s89 & viv_s97) begin + if (viv_s90) begin + viv_s112 <= 20'd0; + end else begin + viv_s112 <= viv_s112 + 20'd1; + end + end + if (viv_s89 & viv_s97 & viv_s90) begin + if (viv_s91) begin + viv_s111 <= 20'd0; + end else begin + viv_s111 <= viv_s111 + 20'd1; + end + end + end + end + end + always @(*) + begin : proc_scale + viv_s71 = viv_s44; + viv_s82 = viv_s4; + viv_s67 = viv_s0; + viv_s68 = viv_s1; + viv_s73 = viv_s97; + viv_s69 = viv_s2; + viv_s70 = viv_s3; + viv_s72 = viv_s8; + viv_s83 = viv_s32; + viv_s87 = viv_s37; + viv_s75 = viv_s88; + viv_s77 = viv_s89 & ~viv_s97; + viv_s78 = viv_s89 & ~viv_s97; + viv_s80 = viv_s90 & ~viv_s97; + viv_s81 = viv_s91 & ~(viv_s90 & viv_s97); + viv_s100 = viv_s101 & ~viv_s97; + viv_s65 = viv_s31; + viv_s76 = 10'b0; + viv_s66 = {c_lbuf_v + 2{1'b0}}; + if (viv_s107) begin + viv_s82 = ~viv_s4; + end + case (viv_s8) + c_between : + begin + if (viv_s97) + begin + viv_s77 = 1'b1; + viv_s78 = 1'b1; + viv_s81 = 1'b0; + if (viv_s32 == viv_s37) + begin + viv_s80 = 1'b1; + end + else + begin + viv_s80 = 1'b0; + end + if (viv_s3 | (viv_s2 & ~(|viv_s44))) + viv_s76 = ({viv_s30[7:0],2'b00}); + else + viv_s76 = viv_s39[(c_scale_v + 7):(c_scale_v - 2)]+ + {viv_s30[15:8], 2'b00} - + viv_s40[(c_scale_v + 7):(c_scale_v - 2)]; + viv_s75 = viv_s76[9:2]; + if (viv_s2) + begin + viv_s81 = 1'b1; + viv_s65 = 16'b0; + if(viv_s80) begin + viv_s100 = viv_s114; + end + end + if (viv_s32 == viv_s37) + begin + viv_s83 = {c_ram_width+1{1'b0}}; + if (viv_s2 == 1'b1) + begin + viv_s71 = phase_v_sdw; + viv_s72 = c_idle; + viv_s87 = c_max_hsize-1; + end + else begin + viv_s71 = viv_s45[c_scale_v - 1:0]; + if (viv_s104) + if (viv_s3) + if (viv_s46 > {1'b0,phase_v_sdw}) + viv_s69 = 1'b1; + else + viv_s69 = 1'b0; + else + if ((viv_s45[c_scale_v] | viv_s46[c_scale_v]) + & (viv_s46[c_scale_v-1:0] > phase_v_sdw)) + viv_s69 = 1'b1; + else + viv_s69 = 1'b0; + else + viv_s69 = 1'b0; + if (viv_s45[c_scale_v]) + begin + if (viv_s104) begin + viv_s70 = 1'b1; + viv_s72 = c_between; + end else begin + viv_s72 = c_second; + end + end + else + begin + viv_s72 = c_between; + end + end + end + else + begin + viv_s83 = viv_s32 + 1'd1; + viv_s72 = c_between; + end + end + end + c_second : + begin + if (viv_s107) + begin + viv_s77 = 1'b1; + viv_s78 = 1'b1; + viv_s81 = 1'b0; + viv_s80 = viv_s95; + viv_s76 = viv_s40[(c_scale_v + 7):(c_scale_v - 2)] + + ({viv_s30[7:0], 2'b00}) - + viv_s39[(c_scale_v + 7):(c_scale_v - 2)]; + viv_s75 = viv_s76[9:2]; + viv_s65[15:8] = viv_s30[7:0]; + viv_s65[7:0] = viv_s93; + if (viv_s96 & viv_s59) + begin + viv_s81 = 1'b1; + viv_s65 = 16'b0; + if(viv_s80) begin + viv_s100 = viv_s114; + end + end + if (~viv_s95) + begin + viv_s83 = viv_s32 + 1'd1; + viv_s72 = c_second; + end + else + begin + viv_s83 = {c_ram_width+1{1'b0}}; + viv_s87 = viv_s32; + if (viv_s96 & + (((viv_s45[c_scale_v] | viv_s46[c_scale_v]) & + (viv_s46[c_scale_v-1:0] > phase_v_sdw)) | viv_s110)) + viv_s69 = 1'b1; + else + viv_s69 = 1'b0; + if (viv_s45[c_scale_v]) + begin + if (viv_s2) + begin + viv_s71 = phase_v_sdw; + viv_s72 = c_idle; + viv_s87 = c_max_hsize-1; + end + else + begin + viv_s71 = viv_s45[c_scale_v - 1:0]; + if (viv_s96 == 1'b1) begin + if (viv_s59 == 1'b1) begin + viv_s72 = c_idle; + end else begin + viv_s72 = c_between; + viv_s70 = 1'b1; + end + end else begin + viv_s72 = c_second; + end + end + end + else + begin + viv_s71 = viv_s45[c_scale_v - 1:0]; + viv_s72 = c_between; + end + end + end + end + default : + begin + if (~scale_v_up_sdw) + begin + if (viv_s107) + begin + if ((viv_s45[c_scale_v]) | viv_s96) + begin + viv_s77 = 1'b1; + viv_s78 = 1'b1; + if(viv_s0) begin + viv_s76 = 10'h0 + + {viv_s93, 2'b10} - + viv_s40[c_scale_v + 7:c_scale_v - 2]; + end else begin + viv_s76 = viv_s30[c_lbuf_v - 1:c_lbuf_v - 10] + + {viv_s93, 2'b10} - + viv_s40[c_scale_v + 7:c_scale_v - 2]; + end + viv_s75 = viv_s76[9:2]; + viv_s66 = viv_s39[c_scale_v + 7:c_scale_v - c_lbuf_v + 6]; + viv_s65 = {viv_s56[15:c_lbuf_v], viv_s66[c_lbuf_v + 1:2]}; + viv_s80 = viv_s95; + viv_s81 = viv_s96; + end + else + begin + if (viv_s0) + begin + viv_s66 = viv_s39[c_scale_v + 7: c_scale_v - c_lbuf_v + 6]; + end + else + begin + viv_s66 = ({viv_s30[c_lbuf_v - 1:0], 2'b00}) + + viv_s39[c_scale_v + 7:c_scale_v - c_lbuf_v + 6]; + end + viv_s65 = {viv_s56[15:c_lbuf_v], viv_s66[c_lbuf_v + 1:2]}; + end + if (viv_s96) + begin + viv_s65 = 16'b0; + viv_s100 = viv_s102; + end + if (viv_s95) + begin + viv_s68 = 1'b1; + if (viv_s96) + begin + viv_s67 = 1'b1; + viv_s71 = phase_v_sdw; + end + else + begin + viv_s67 = 1'b0; + viv_s71 = viv_s45[c_scale_v - 1:0]; + end + end + if (viv_s1 & ~viv_s95) + begin + viv_s68 = 1'b0; + end + end + end + else + begin + viv_s70 = 1'b0; + viv_s69 = 1'b0; + viv_s71 = phase_v_sdw; + if (viv_s107) + begin + viv_s78 = 1'b1; + viv_s77 = ~(|phase_v_sdw); + viv_s80 = viv_s95; + viv_s81 = viv_s96; + viv_s75 = viv_s93; + viv_s65[7:0] = viv_s93; + if (~viv_s95) + begin + viv_s72 = c_idle; + viv_s83 = viv_s32 + 1'd1; + end + else + begin + viv_s87 = viv_s32; + viv_s83 = {c_ram_width+1{1'b0}}; + viv_s72 = c_second; + if (~(|phase_v_sdw)) + viv_s71 = viv_s45[c_scale_v - 1:0]; + end + end + end + end + endcase + end + always @(*) + begin : proc_outmode + if (~scale_v_up_sdw) + begin + viv_s7 = viv_s45[c_scale_v] | viv_s90 | viv_s96; + viv_s92 = viv_s73 | ~viv_s7; + end + else + begin + if (viv_s8 == c_between) + begin + viv_s7 = 1'b1; + end + else + begin + viv_s7 = 1'b0; + end + viv_s92 = viv_s73 & ~viv_s7; + end + end + always @(posedge clk or negedge reset_n) + begin : proc_write_ram_regs + if (~reset_n) + begin + viv_s14 <= 32'b0; + viv_s13 <= 1'b0; + viv_s35 <= (c_max_hsize/2)-1; + viv_s33 <= {c_ram_width{1'b0}}; + viv_s34 <= {c_ram_width{1'b0}}; + viv_s36 <= (c_max_hsize/2)-1; + viv_s60 <= 16'b0; + viv_s61 <= 16'b0; + viv_s64 <= 16'b0; + viv_s63 <= 16'b0; + viv_s62 <= 16'b0; + viv_s5 <= 1'b0; + viv_s9 <= 1'b0; + viv_s10 <= 1'b1; + viv_s11 <= 1'b1; + viv_s38 <= 32'b0; + viv_s12 <= 1'b0; + end + else + begin + if (soft_rst) + begin + viv_s14 <= 32'b0; + viv_s13 <= 1'b0; + viv_s35 <= (c_max_hsize/2)-1; + viv_s33 <= {c_ram_width{1'b0}}; + viv_s34 <= {c_ram_width{1'b0}}; + viv_s36 <= (c_max_hsize/2)-1; + viv_s60 <= 16'b0; + viv_s61 <= 16'b0; + viv_s64 <= 16'b0; + viv_s63 <= 16'b0; + viv_s62 <= 16'b0; + viv_s5 <= 1'b0; + viv_s9 <= 1'b0; + viv_s10 <= 1'b1; + viv_s11 <= 1'b1; + viv_s38 <= 32'b0; + viv_s12 <= 1'b0; + end + else + begin + viv_s13 <= 1'b0; + viv_s5 <= viv_s4; + viv_s9 <= viv_s94; + viv_s10 <= viv_s92; + viv_s11 <= viv_s97; + viv_s12 <= viv_s13; + if (~scale_v_up_sdw) + begin + viv_s33 <= viv_s84; + viv_s35 <= viv_s85; + viv_s36 <= viv_s86; + if (viv_s107) + begin + if (viv_s4) + begin + viv_s60 <= (viv_s31); + end + else + begin + viv_s61 <= (viv_s31); + end + end + if (viv_s109) + begin + if (~viv_s5) + begin + viv_s62 <= ram_rdata[31:16]; + viv_s64 <= ram_rdata[15:0]; + end + else + begin + viv_s63 <= viv_s64; + end + end + end + else + begin + case (viv_s8) + c_between : + begin + if (viv_s108) + begin + if (~viv_s6) + begin + viv_s34 <= viv_s33; + if (viv_s33 == viv_s36) + begin + viv_s33 <= {c_ram_width{1'b0}}; + end + else + begin + viv_s33 <= viv_s33 + 1'd1; + end + end + end + end + c_second : + begin + if (viv_s4) + begin + if (viv_s107) + begin + viv_s13 <= 1'b1; + viv_s14 <= {viv_s60, + ({viv_s30[7:0], + viv_s93})}; + if (viv_s35 == viv_s36) + begin + viv_s35 <= {c_ram_width{1'b0}}; + end + else + begin + viv_s35 <= viv_s35 + 1'd1; + end + viv_s34 <= viv_s33; + if (viv_s33 == viv_s36) + begin + viv_s33 <= {c_ram_width{1'b0}}; + end + else + begin + viv_s33 <= viv_s33 + 1'd1; + end + end + end + else + begin + if (viv_s107) + begin + viv_s60 <= ({viv_s30[7:0], + viv_s93}); + end + end + end + default : + begin + if (viv_s107) + begin + if (viv_s4) + begin + viv_s13 <= 1'b1; + viv_s14 <= {viv_s60, + viv_s57[7:0], + (viv_s93)}; + if (viv_s35 == viv_s36) + begin + viv_s35 <= {c_ram_width{1'b0}}; + end + else + begin + viv_s35 <= viv_s35 + 1'b1; + end + if (viv_s95) + begin + viv_s36 <= viv_s35 + 1'b1; + viv_s33 <= {c_ram_width{1'b0}}+1'b1; + viv_s34 <= viv_s33; + end + end + else + begin + viv_s60 <= {viv_s57[7:0], + (viv_s93)}; + end + end + end + endcase + end + if (viv_s91 & viv_s90 & viv_s108) + begin + viv_s36 <= (c_max_hsize/2)-1; + viv_s33 <= {c_ram_width{1'b0}}; + viv_s35 <= (c_max_hsize/2)-1; + end + if (viv_s6 & viv_s79 & viv_s11) + begin + viv_s38 <= ram_rdata; + end + end + end + end + always @(*) + begin : proc_ram + viv_s86 = viv_s36; + viv_s85 = viv_s35; + viv_s84 = viv_s33; + if (~scale_v_up_sdw) + begin + viv_s15 = scale_v_en_sdw & viv_s4; + viv_s16 = scale_v_en_sdw & viv_s94; + ram_wdata = ({viv_s60, viv_s61}); + if (viv_s4 == 1'b0) + begin + ram_addr = viv_s33; + end + else + begin + ram_addr = viv_s35; + end + end + else + begin + viv_s16 = scale_v_en_sdw; + viv_s15 = viv_s13; + ram_wdata = viv_s14; + if (viv_s109 & viv_s5) + begin + ram_addr = viv_s35; + end + else + begin + if (viv_s97) + begin + ram_addr = viv_s33; + end + else + begin + ram_addr = viv_s34; + end + end + end + if (viv_s8 != c_between) + begin + if (~scale_v_up_sdw) + begin + if (viv_s4) + begin + viv_s30 = (viv_s63[15:0]); + end + else + begin + viv_s30 = (viv_s62[15:0]); + end + if (viv_s107) + begin + if (viv_s95 & viv_s0) + begin + viv_s86 = viv_s35 + 1'd1; + viv_s84 = {c_ram_width{1'b0}} + 1'b1; + end + if (viv_s4) + begin + if (viv_s35 == viv_s36) + begin + viv_s85 = {c_ram_width{1'b0}}; + end + else + begin + viv_s85 = viv_s35 + 1'd1; + end + if (viv_s0 == 1'b0) + begin + if (viv_s33 == viv_s36) + begin + viv_s84 = {c_ram_width{1'b0}}; + end + else + begin + viv_s84 = viv_s33 + 1'd1; + end + end + end + else + begin + viv_s85 = viv_s35; + viv_s84 = viv_s33; + end + end + end + else + begin + if (viv_s4) + begin + viv_s30 = (viv_s38[15:0]); + end + else + begin + if (~viv_s9) begin + if((viv_s6==1) & (viv_s32=={c_ram_width+1{1'b0}})) begin + viv_s30 = (ram_rdata[31:16]); + end + else + begin + viv_s30 = (viv_s38[31:16]); + end + end + else + begin + if (viv_s12) + begin + viv_s30 = (viv_s38[31:16]); + end + else + begin + viv_s30 = (ram_rdata[31:16]); + end + end + end + end + end + else + begin + if (viv_s6) + begin + if (~viv_s11) + begin + viv_s30 = (viv_s38[31:16]); + end + else + begin + if (viv_s12) + begin + viv_s30 = (viv_s38[31:16]); + end + else + begin + viv_s30 = (ram_rdata[31:16]); + end + end + end + else + begin + viv_s30 = (viv_s38[15:0]); + end + end + if (viv_s91 & viv_s90 & viv_s108) + begin + viv_s86 = (c_max_hsize/2)-1; + viv_s85 = (c_max_hsize/2)-1; + viv_s84 = {c_ram_width{1'b0}}; + end + end + assign ram_wr_n = ~viv_s15; + assign ram_cs_n = ~viv_s16; + assign scale_v_lut_ad = (viv_s44[c_scale_v - 1:c_scale_v - c_scale_lut_addr]); + assign viv_s43 = {(scale_v_lut), viv_s56[c_scale_v - c_scale_lut - 1:0]}; +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_sensor_fifo.v b/ispyocto/rtl/ispyocto/vsisp_sensor_fifo.v new file mode 100644 index 0000000..e93569f --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_sensor_fifo.v
@@ -0,0 +1,114 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_sensor_fifo + ( + sclk, + reset_sclk_n, + mclk, + reset_mclk_n, + s_data, + s_hsync, + s_vsync, + s_valid, + s_fifo_val, + s_fifo_data, + s_fifo_hsync, + s_fifo_vsync, + s_fifo_ack, + s_fifo_full + ); + parameter c_fifo_depth = 4; + parameter c_dw_si = 12; + parameter c_data_width = c_dw_si + 3; + parameter c_addr_width = (c_fifo_depth <= 1 ) ? 0 : + (c_fifo_depth <= 2 ) ? 1 : + (c_fifo_depth <= 4 ) ? 2 : + (c_fifo_depth <= 8 ) ? 3 : + (c_fifo_depth <= 16 ) ? 4 : + (c_fifo_depth <= 32 ) ? 5 : + (c_fifo_depth <= 64 ) ? 6 : + (c_fifo_depth <= 128 ) ? 7 : 8; + input sclk; + input reset_sclk_n; + input mclk; + input reset_mclk_n; + input [c_dw_si-1:0] s_data; + input s_hsync; + input s_vsync; + input s_valid; + output [c_dw_si-1:0] s_fifo_data; + wire [c_dw_si-1:0] s_fifo_data; + output s_fifo_val; + wire s_fifo_val; + output s_fifo_hsync; + wire s_fifo_hsync; + output s_fifo_vsync; + wire s_fifo_vsync; + input s_fifo_ack; + output s_fifo_full; + wire s_fifo_full; + wire [c_data_width-1:0] viv_s0; + wire viv_s1; + wire viv_s2; + wire [c_addr_width:0] viv_s3; + wire viv_s4; + wire [c_data_width-1:0] viv_s5; + wire viv_s6; + wire viv_s7; + wire [c_addr_width:0] viv_s8; + wire [c_data_width-1:0] viv_s9; + assign viv_s1 = 1'b1; + assign viv_s0 = {s_vsync, s_hsync, s_valid, s_data}; + vsisp_sync_fifo_core #(c_fifo_depth, c_data_width) u_sync_fifo_core + ( + .wr_clk (sclk ), + .wr_reset_n (reset_sclk_n ), + .rd_clk (mclk ), + .rd_reset_n (reset_mclk_n ), + .wr_en (viv_s1 ), + .wdata (viv_s0 ), + .fifo_full (viv_s2 ), + .wr_fill_level (viv_s3), + .rd_en (viv_s4 ), + .rdata (viv_s5 ), + .fifo_empty (viv_s7 ), + .rd_fill_level (viv_s8) + ); + vsisp_sync_fifo_outp #(c_data_width) u_sync_fifo_outp + ( + .rd_clk (mclk ), + .rd_reset_n (reset_mclk_n ), + .rd_val (viv_s6 ), + .rd_data (viv_s9 ), + .rd_ack (s_fifo_ack ), + .rd_en (viv_s4 ), + .rdata (viv_s5 ), + .fifo_empty (viv_s7 ) + ); + assign s_fifo_data = viv_s9[c_dw_si-1:0]; + assign s_fifo_val = viv_s9[c_dw_si]&viv_s6; + assign s_fifo_hsync = viv_s9[c_dw_si+1]; + assign s_fifo_vsync = viv_s9[c_dw_si+2]; + assign s_fifo_full = (viv_s8 == c_fifo_depth); +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_sync_fifo_core.v b/ispyocto/rtl/ispyocto/vsisp_sync_fifo_core.v new file mode 100644 index 0000000..c56662b --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_sync_fifo_core.v
@@ -0,0 +1,154 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_sync_fifo_core + ( + wr_clk, + wr_reset_n, + rd_clk, + rd_reset_n, + wr_en, + wdata, + fifo_full, + wr_fill_level, + rd_en, + rdata, + fifo_empty, + rd_fill_level + ); + parameter c_fifo_depth = 4; + parameter c_data_width = 8; + parameter c_addr_width = (c_fifo_depth <= 1) ? 0 : + (c_fifo_depth <= 2) ? 1 : + (c_fifo_depth <= 4) ? 2 : + (c_fifo_depth <= 8) ? 3 : + (c_fifo_depth <= 16) ? 4 : + (c_fifo_depth <= 32) ? 5 : + (c_fifo_depth <= 64) ? 6 : + (c_fifo_depth <= 128) ? 7 : 8; + input wr_clk; + input wr_reset_n; + input rd_clk; + input rd_reset_n; + input wr_en; + input [c_data_width-1:0] wdata; + output fifo_full; + wire fifo_full; + output [c_addr_width:0] wr_fill_level; + wire [c_addr_width:0] wr_fill_level; + output [c_data_width-1:0] rdata; + input rd_en; + wire [c_data_width-1:0] rdata; + output fifo_empty; + wire fifo_empty; + output [c_addr_width:0] rd_fill_level; + wire [c_addr_width:0] rd_fill_level; + function [c_addr_width:0] f_bin2gray; + input [c_addr_width:0] viv_s0; + begin + f_bin2gray = viv_s0 ^ {1'b0, viv_s0[c_addr_width:1]}; + end + endfunction + function [c_addr_width:0] f_gray2bin; + input [c_addr_width:0] gray_value; + reg [c_addr_width:0] viv_s0; + integer v_bitpos; + begin + viv_s0 = {gray_value[c_addr_width], {c_addr_width{1'b0}}}; + for (v_bitpos = c_addr_width - 1;v_bitpos >= 0;v_bitpos = v_bitpos - 1) + viv_s0[v_bitpos] = gray_value[v_bitpos] ^ viv_s0[v_bitpos + 1]; + f_gray2bin = viv_s0; + end + endfunction + reg [c_data_width-1:0] vsisp_fifo[c_fifo_depth-1:0]; + reg [c_addr_width:0] viv_s1; + wire [c_addr_width:0] viv_s2; + reg [c_addr_width:0] viv_s3; + reg [c_addr_width:0] viv_s4; + reg [c_addr_width:0] viv_s5; + reg [c_addr_width:0] viv_s6; + wire [c_addr_width:0] viv_s7; + reg [c_addr_width:0] viv_s8; + reg [c_addr_width:0] viv_s9; + reg [c_addr_width:0] viv_s10; + integer v_index; + always @(posedge wr_clk or negedge wr_reset_n) + begin + if (~wr_reset_n) begin + viv_s1 <= {c_addr_width+1{1'b0}}; + viv_s3 <= {c_addr_width+1{1'b0}}; + for(v_index = 0; v_index < c_fifo_depth; v_index = v_index + 1) + vsisp_fifo[v_index] <= {c_data_width{1'b0}} ; + end + else begin + if (wr_en) begin + vsisp_fifo[viv_s1[c_addr_width-1:0]] <= wdata; + viv_s1 <= viv_s1 + 1'b1; + viv_s3 <= f_bin2gray(viv_s1 + 1'b1); + end + end + end + always @(posedge rd_clk or negedge rd_reset_n) + begin + if (~rd_reset_n) begin + viv_s4 <= {c_addr_width+1{1'b0}}; + viv_s5 <= {c_addr_width+1{1'b0}}; + end + else begin + viv_s4 <= viv_s3; + viv_s5 <= viv_s4; + end + end + assign viv_s7 = f_gray2bin(viv_s10); + assign fifo_full = (viv_s1[c_addr_width] != viv_s7[c_addr_width]) + & (viv_s1[c_addr_width-1:0] == viv_s7[c_addr_width-1:0]); + assign wr_fill_level = viv_s1 - viv_s7; + always @(posedge rd_clk or negedge rd_reset_n) + begin + if (~rd_reset_n) begin + viv_s6 <= {c_addr_width+1{1'b0}}; + viv_s8 <= {c_addr_width+1{1'b0}}; + end + else begin + if (rd_en) begin + viv_s6 <= viv_s6 + 1'b1; + viv_s8 <= f_bin2gray(viv_s6 + 1'b1); + end + end + end + assign rdata = vsisp_fifo[viv_s6[c_addr_width-1:0]]; + always @(posedge wr_clk or negedge wr_reset_n) + begin + if (~wr_reset_n) begin + viv_s9 <= {c_addr_width+1{1'b0}}; + viv_s10 <= {c_addr_width+1{1'b0}}; + end + else begin + viv_s9 <= viv_s8; + viv_s10 <= viv_s9; + end + end + assign viv_s2 = f_gray2bin(viv_s5); + assign fifo_empty = (viv_s2 == viv_s6); + assign rd_fill_level = viv_s2 - viv_s6; +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_sync_fifo_outp.v b/ispyocto/rtl/ispyocto/vsisp_sync_fifo_outp.v new file mode 100644 index 0000000..be35d6e --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_sync_fifo_outp.v
@@ -0,0 +1,72 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_sync_fifo_outp + ( + rd_clk, + rd_reset_n, + rd_val, + rd_data, + rd_ack, + rd_en, + rdata, + fifo_empty + ); + parameter c_data_width = 8; + input rd_clk; + input rd_reset_n; + output rd_val; + wire rd_val; + output [c_data_width-1:0] rd_data; + reg [c_data_width-1:0] rd_data; + input rd_ack; + output rd_en; + wire rd_en; + input [c_data_width-1:0] rdata; + input fifo_empty; + wire viv_s0; + wire [c_data_width-1:0] viv_s1; + wire viv_s2; + reg viv_s3; + wire viv_s4; + always @(posedge rd_clk or negedge rd_reset_n) begin + if (!rd_reset_n) begin + rd_data <= {c_data_width{1'b0}}; + viv_s3 <= 1'b0; + end + else begin + if (viv_s4) begin + viv_s3 <= viv_s0; + if (viv_s0) begin + rd_data <= viv_s1; + end + end + end + end + assign viv_s4 = rd_ack | (~viv_s3); + assign viv_s2 = viv_s4; + assign rd_val = viv_s3; + assign viv_s1 = rdata; + assign viv_s0 = ~fifo_empty; + assign rd_en = viv_s2 & ~fifo_empty; +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_sync_fifo_reset_gen_rd.v b/ispyocto/rtl/ispyocto/vsisp_sync_fifo_reset_gen_rd.v new file mode 100644 index 0000000..1e31ec4 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_sync_fifo_reset_gen_rd.v
@@ -0,0 +1,44 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_sync_fifo_reset_gen_rd + ( + rd_clk, + reset_n, + soft_reset, +test_mode, + rd_reset_n + ); + input rd_clk; + input reset_n; + input soft_reset; + input test_mode; + output rd_reset_n; + vsisp_marvin_ctrl_reset_gen u_marvin_ctrl_reset_gen ( + .reset_n(reset_n), + .clk(rd_clk), + .soft_rst_i(soft_reset), + .reset_out_n(rd_reset_n), + .test_mode(test_mode) + ); +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_sync_fifo_reset_gen_wr.v b/ispyocto/rtl/ispyocto/vsisp_sync_fifo_reset_gen_wr.v new file mode 100644 index 0000000..f13a9b7 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_sync_fifo_reset_gen_wr.v
@@ -0,0 +1,44 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_sync_fifo_reset_gen_wr + ( + wr_clk, + reset_n, + soft_reset, +test_mode, + wr_reset_n + ); + input wr_clk; + input reset_n; + input soft_reset; + input test_mode; + output wr_reset_n; + vsisp_marvin_ctrl_reset_gen u_marvin_ctrl_reset_gen ( + .reset_n(reset_n), + .clk(wr_clk), + .soft_rst_i(soft_reset), + .reset_out_n(wr_reset_n), + .test_mode(test_mode) + ); +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_vs_marvin_ramshell.v b/ispyocto/rtl/ispyocto/vsisp_vs_marvin_ramshell.v new file mode 100644 index 0000000..fc91cce --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_vs_marvin_ramshell.v
@@ -0,0 +1,249 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_vs_marvin_ramshell + ( + reset_, + regs_disable_isp_clk, + scan_mode, + isp_fifo_ram_clk, + isp_fifo_cs_n, + isp_fifo_wr_n, + isp_fifo_addr, + isp_fifo_wdata, + isp_fifo_rdata, + isp_rgb_ram_clk, + isp_ispram_addr, + isp_ispram_wdata, + isp_ispram_rdata, + isp_ispram_wr_n, + isp_ispram_cs_n, + rszm_mram_clk, + rszm_mramy_wr_n, + rszm_mramy_cs_n, + rszm_mramy_addr, + rszm_mramy_wdata, + rszm_mramy_rdata, + rszm_mramc_wr_n, + rszm_mramc_cs_n, + rszm_mramc_addr, + rszm_mramc_wdata, + rszm_mramc_rdata, + rszs_sram_clk, + rszs_sramy_wr_n, + rszs_sramy_cs_n, + rszs_sramy_addr, + rszs_sramy_wdata, + rszs_sramy_rdata, + rszs_sramc_wr_n, + rszs_sramc_cs_n, + rszs_sramc_addr, + rszs_sramc_wdata, + rszs_sramc_rdata, + mp_y_fifo_sram_wdata , + mp_y_fifo_sram_rdata , + mp_y_fifo_sram_addr , + mp_y_fifo_sram_cs_n , + mp_y_fifo_sram_we_n , + mp_cb_fifo_sram_wdata , + mp_cb_fifo_sram_rdata , + mp_cb_fifo_sram_addr , + mp_cb_fifo_sram_cs_n , + mp_cb_fifo_sram_we_n , + mp_cr_fifo_sram_wdata , + mp_cr_fifo_sram_rdata , + mp_cr_fifo_sram_addr , + mp_cr_fifo_sram_cs_n , + mp_cr_fifo_sram_we_n + ); +`include "vsisp_isp.vh" +`include "vsisp_ram_sizes.vh" + input reset_; + input regs_disable_isp_clk; + input scan_mode; + input isp_fifo_ram_clk; + input isp_fifo_cs_n; + input isp_fifo_wr_n; + input [c_ispfifo_aw-1:0] isp_fifo_addr; + input [c_ispfifo_dw-1:0] isp_fifo_wdata; + output [c_ispfifo_dw-1:0] isp_fifo_rdata; + input isp_rgb_ram_clk; + input [c_aw_dem_mem-1:0] isp_ispram_addr; + input [c_dw_dem_mem-1:0] isp_ispram_wdata; + output [c_dw_dem_mem-1:0] isp_ispram_rdata; + input isp_ispram_wr_n; + input isp_ispram_cs_n; + input rszm_mram_clk; + input rszm_mramy_wr_n; + input rszm_mramy_cs_n; + input [c_aw_mrsz-1:0] rszm_mramy_addr; + input [31:0] rszm_mramy_wdata; + output [31:0] rszm_mramy_rdata; + input rszm_mramc_wr_n; + input rszm_mramc_cs_n; + input [c_aw_mrsz-1:0] rszm_mramc_addr; + input [31:0] rszm_mramc_wdata; + output [31:0] rszm_mramc_rdata; + input rszs_sram_clk; + input rszs_sramy_wr_n; + input rszs_sramy_cs_n; + input [c_aw_srsz-1:0] rszs_sramy_addr; + input [31:0] rszs_sramy_wdata; + output [31:0] rszs_sramy_rdata; + input rszs_sramc_wr_n; + input rszs_sramc_cs_n; + input [c_aw_srsz-1:0] rszs_sramc_addr; + input [31:0] rszs_sramc_wdata; + output [31:0] rszs_sramc_rdata; + input [65:0] mp_y_fifo_sram_wdata ; + output [65:0] mp_y_fifo_sram_rdata ; + input [ c_mi_mp_y_aw-1:0] mp_y_fifo_sram_addr ; + input mp_y_fifo_sram_cs_n ; + input mp_y_fifo_sram_we_n ; + input [65:0] mp_cb_fifo_sram_wdata ; + output [65:0] mp_cb_fifo_sram_rdata ; + input [ c_mi_mp_c_aw-1:0] mp_cb_fifo_sram_addr ; + input mp_cb_fifo_sram_cs_n ; + input mp_cb_fifo_sram_we_n ; + input [65:0] mp_cr_fifo_sram_wdata ; + output [65:0] mp_cr_fifo_sram_rdata ; + input [ c_mi_mp_c_aw -1:0] mp_cr_fifo_sram_addr ; + input mp_cr_fifo_sram_cs_n ; + input mp_cr_fifo_sram_we_n ; + wire [15:0] GC_CONTROL = {11'b0,regs_disable_isp_clk,3'b100,scan_mode}; + wire [31:0] mcReg_registerTimingControl = 32'h30000; + `ifdef ISP_FPGA +RAM_128X28_FPGA u_isp_fifo( + .clka (isp_fifo_ram_clk), + .ena (~isp_fifo_cs_n), + .wea (~isp_fifo_wr_n), + .addra(isp_fifo_addr), + .dina (isp_fifo_wdata), + .douta(isp_fifo_rdata) +); + `else + vsisp_isp_isp_fifo_wrapper u_isp_fifo( + .GC_CONTROL(GC_CONTROL), + .cEn0_(isp_fifo_cs_n), + .mcReg_registerTimingControl(mcReg_registerTimingControl), + .reset_(reset_), + .rwAddr0(isp_fifo_addr), + .rwclk0(isp_fifo_ram_clk), + .wData0(isp_fifo_wdata), + .wEn0_(isp_fifo_wr_n), + .rData0(isp_fifo_rdata) + ); + `endif + `ifdef ISP_FPGA +RAM_960X168_FPGA u_ispram( + .clka (isp_rgb_ram_clk), + .ena (~isp_ispram_cs_n), + .wea (~isp_ispram_wr_n), + .addra(isp_ispram_addr), + .dina (isp_ispram_wdata), + .douta(isp_ispram_rdata) +); + `else + vsisp_isp_isp_ram_wrapper u_ispram( + .GC_CONTROL(GC_CONTROL), + .cEn0_(isp_ispram_cs_n), + .mcReg_registerTimingControl(mcReg_registerTimingControl), + .reset_(reset_), + .rwAddr0(isp_ispram_addr), + .rwclk0(isp_rgb_ram_clk), + .wData0(isp_ispram_wdata), + .wEn0_(isp_ispram_wr_n), + .rData0(isp_ispram_rdata) + ); + `endif + assign rszm_mramy_rdata = 32'd0; + assign rszm_mramc_rdata = 32'd0; + `ifdef ISP_FPGA + RAM_1024X32_FPGA u_srsz_y_rszram( + .clka (rszs_sram_clk), + .ena (~rszs_sramy_cs_n), + .wea (~rszs_sramy_wr_n), + .addra(rszs_sramy_addr), + .dina (rszs_sramy_wdata), + .douta(rszs_sramy_rdata) + ); + `else + vsisp_isp_srsz_y_wrapper u_srsz_y_rszram( + .GC_CONTROL(GC_CONTROL), + .cEn0_(rszs_sramy_cs_n), + .mcReg_registerTimingControl(mcReg_registerTimingControl), + .reset_(reset_), + .rwAddr0(rszs_sramy_addr), + .rwclk0(rszs_sram_clk), + .wData0(rszs_sramy_wdata), + .wEn0_(rszs_sramy_wr_n), + .rData0(rszs_sramy_rdata) + ); + `endif + `ifdef ISP_FPGA + RAM_1024X32_FPGA u_srsz_c_rszram( + .clka (rszs_sram_clk), + .ena (~rszs_sramc_cs_n), + .wea (~rszs_sramc_wr_n), + .addra(rszs_sramc_addr), + .dina (rszs_sramc_wdata), + .douta(rszs_sramc_rdata) + ); + `else + vsisp_isp_srsz_c_wrapper u_srsz_c_rszram( + .GC_CONTROL(GC_CONTROL), + .cEn0_(rszs_sramc_cs_n), + .mcReg_registerTimingControl(mcReg_registerTimingControl), + .reset_(reset_), + .rwAddr0(rszs_sramc_addr), + .rwclk0(rszs_sram_clk), + .wData0(rszs_sramc_wdata), + .wEn0_(rszs_sramc_wr_n), + .rData0(rszs_sramc_rdata) + ); + `endif + `ifdef ISP_FPGA +RAM_80X66_FPGA u_mi_sram_fifo_y( + .clka (isp_fifo_ram_clk ), + .dina (mp_y_fifo_sram_wdata ), + .douta(mp_y_fifo_sram_rdata ) + .addra(mp_y_fifo_sram_addr ), + .ena (~mp_y_fifo_sram_cs_n ), + .wea (~mp_y_fifo_sram_we_n ), +); + `else + vsisp_isp_miv1_mp_sramy_wrapper u_mi_sram_fifo_y( + .GC_CONTROL(GC_CONTROL), + .mcReg_registerTimingControl(mcReg_registerTimingControl), + .reset_ (reset_), + .rwclk0 (isp_fifo_ram_clk ), + .wData0 (mp_y_fifo_sram_wdata), + .rData0 (mp_y_fifo_sram_rdata), + .rwAddr0 (mp_y_fifo_sram_addr ), + .cEn0_ (mp_y_fifo_sram_cs_n ), + .wEn0_ (mp_y_fifo_sram_we_n ) + ); + `endif + assign mp_cb_fifo_sram_rdata = 66'd0; + assign mp_cr_fifo_sram_rdata = 66'd0; +endmodule
diff --git a/ispyocto/rtl/ispyocto/vsisp_yc_split.v b/ispyocto/rtl/ispyocto/vsisp_yc_split.v new file mode 100644 index 0000000..0426eb1 --- /dev/null +++ b/ispyocto/rtl/ispyocto/vsisp_yc_split.v
@@ -0,0 +1,360 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Portions Copyright (c) 2003 Silicon Image GmbH, used with permission +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_yc_split + ( + clk, + reset_n, + soft_rst, + cfg_chan_mode, + in_data, + in_h_end, + in_v_end, + in_cfg_upd, + in_val, + in_ack, + out_y_m_data, + out_y_m_val, + out_y_m_ack, + out_y_m_h_end, + out_y_m_v_end, + out_c_m_data, + out_c_m_val, + out_c_m_ack, + out_c_m_h_end, + out_c_m_v_end, + out_y_s_data, + out_y_s_val, + out_y_s_ack, + out_y_s_h_end, + out_y_s_v_end, + out_c_s_data, + out_c_s_val, + out_c_s_ack, + out_c_s_h_end, + out_c_s_v_end, + out_cfg_upd, + out_ext_y_data, + out_ext_y_val, + out_ext_y_ack, + out_ext_y_h_end, + out_ext_y_v_end, + out_ext_c_data, + out_ext_c_val, + out_ext_c_ack, + out_ext_c_h_end, + out_ext_c_v_end + ); + parameter data_width = 10; + input clk; + input reset_n; + input soft_rst; + input [1:0] cfg_chan_mode; + input [2*data_width-1:0] in_data; + input in_h_end; + input in_v_end; + input in_cfg_upd; + input in_val; + output in_ack; + output [data_width-1:0] out_y_m_data; + output out_y_m_val; + input out_y_m_ack; + output out_y_m_h_end; + output out_y_m_v_end; + output [data_width-1:0] out_c_m_data; + output out_c_m_val; + input out_c_m_ack; + output out_c_m_h_end; + output out_c_m_v_end; + output [data_width-1:0] out_y_s_data; + output out_y_s_val; + input out_y_s_ack; + output out_y_s_h_end; + output out_y_s_v_end; + output [data_width-1:0] out_c_s_data; + output out_c_s_val; + input out_c_s_ack; + output out_c_s_h_end; + output out_c_s_v_end; + output out_cfg_upd; + output [data_width-1:0] out_ext_y_data; + output out_ext_y_val; + input out_ext_y_ack; + output out_ext_y_h_end; + output out_ext_y_v_end; + output [data_width-1:0] out_ext_c_data; + output out_ext_c_val; + input out_ext_c_ack; + output out_ext_c_h_end; + output out_ext_c_v_end; + reg [2*data_width-1:0] viv_s0; + reg viv_s1; + reg viv_s2; + reg viv_s3; + reg viv_s4; + reg viv_s5; + wire viv_s6; + wire [2*data_width-1:0] viv_s7; + wire viv_s8; + wire viv_s9; + wire viv_s10; + wire viv_s11; + wire viv_s12; + reg [data_width-1:0] viv_s13; + reg [data_width-1:0] viv_s14; + reg viv_s15; + reg viv_s16; + reg viv_s17; + reg viv_s18; + reg viv_s19; + reg viv_s20; + reg viv_s21; + reg viv_s22; + reg viv_s23; + wire viv_s24; + wire viv_s25; + reg [data_width-1:0] out_y_m_data; + reg out_y_m_h_end; + reg out_y_m_v_end; + reg [data_width-1:0] out_c_m_data; + reg out_c_m_h_end; + reg out_c_m_v_end; + reg [data_width-1:0] out_y_s_data; + reg out_y_s_h_end; + reg out_y_s_v_end; + reg [data_width-1:0] out_c_s_data; + reg out_c_s_h_end; + reg out_c_s_v_end; + reg [data_width-1:0] out_ext_y_data; + reg out_ext_y_h_end; + reg out_ext_y_v_end; + reg [data_width-1:0] out_ext_c_data; + reg out_ext_c_h_end; + reg out_ext_c_v_end; + wire out_ext_y_val; + wire out_ext_c_val; + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + viv_s0 <= {2*data_width{1'b0}}; + viv_s1 <= 1'b0; + viv_s2 <= 1'b0; + viv_s3 <= 1'b0; + viv_s4 <= 1'b0; + viv_s5 <= 1'b0; + end + else begin + if (soft_rst) begin + viv_s0 <= {2*data_width{1'b0}}; + viv_s1 <= 1'b0; + viv_s2 <= 1'b0; + viv_s3 <= 1'b0; + viv_s4 <= 1'b0; + viv_s5 <= 1'b0; + end else begin + viv_s5 <= viv_s25 | (!viv_s6); + if (viv_s5) begin + viv_s1 <= in_val; + end + if (viv_s5) begin + viv_s0 <= in_data; + viv_s2 <= in_h_end; + viv_s3 <= in_v_end; + viv_s4 <= in_cfg_upd; + end + end + end + end + assign viv_s6=viv_s5 ? in_val : viv_s1; + assign viv_s7 =viv_s5 ? in_data : viv_s0; + assign viv_s8 =viv_s6; + assign viv_s9 =viv_s5 ? in_h_end : viv_s2; + assign viv_s10 =viv_s5 ? in_v_end : viv_s3; + assign viv_s11=viv_s5 ? in_cfg_upd : viv_s4; + assign viv_s12 =viv_s5; + assign in_ack =viv_s12; + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + viv_s13 <= {data_width{1'b0}}; + viv_s14 <= {data_width{1'b0}}; + viv_s15 <= 1'b0; + viv_s16 <= 1'b0; + viv_s17 <= 1'b0; + viv_s18 <= 1'b0; + viv_s19 <= 1'b0; + viv_s20 <= 1'b0; + viv_s21 <= 1'b0; + viv_s22 <= 1'b0; + viv_s23 <= 1'b0; + end + else begin + if (soft_rst) begin + viv_s13 <= {data_width{1'b0}}; + viv_s14 <= {data_width{1'b0}}; + viv_s15 <= 1'b0; + viv_s16 <= 1'b0; + viv_s17 <= 1'b0; + viv_s18 <= 1'b0; + viv_s19 <= 1'b0; + viv_s20 <= 1'b0; + viv_s21 <= 1'b0; + viv_s22 <= 1'b0; + viv_s23 <= 1'b0; + end else begin + if (viv_s24) begin + viv_s13 <= viv_s7[2*data_width-1:data_width]; + viv_s14 <= viv_s7[data_width-1 :0]; + viv_s15 <= viv_s9; + viv_s16 <= viv_s10; + viv_s17 <= viv_s11; + viv_s22 <= viv_s8; + viv_s23 <= viv_s8; + case (cfg_chan_mode) + 2'd0: begin + viv_s18 <= 1'b0; + viv_s20 <= 1'b0; + viv_s19 <= 1'b0; + viv_s21 <= 1'b0; + end + 2'd1: begin + viv_s18 <= viv_s8; + viv_s20 <= viv_s8; + viv_s19 <= 1'b0; + viv_s21 <= 1'b0; + end + 2'd2: begin + viv_s18 <= 1'b0; + viv_s20 <= 1'b0; + viv_s19 <= viv_s8; + viv_s21 <= viv_s8; + end + default: begin + viv_s18 <= viv_s8; + viv_s20 <= viv_s8; + viv_s19 <= viv_s8; + viv_s21 <= viv_s8; + end + endcase + end else begin + if (out_y_m_ack) begin + viv_s18 <= 1'b0; + end + if (out_y_s_ack) begin + viv_s19 <= 1'b0; + end + if (out_c_m_ack) begin + viv_s20 <= 1'b0; + end + if (out_c_s_ack) begin + viv_s21 <= 1'b0; + end + if (out_ext_y_ack) begin + viv_s22 <= 1'b0; + end + if (out_ext_c_ack) begin + viv_s23 <= 1'b0; + end + end + end + end + end + assign viv_s24 = (~viv_s18 | out_y_m_ack) && + (~viv_s19 | out_y_s_ack) && + (~viv_s20 | out_c_m_ack) && + (~viv_s21 | out_c_s_ack) && + (~viv_s23 | out_ext_c_ack) && + (~viv_s22 | out_ext_y_ack); + assign viv_s25 = viv_s24; + always @(*) begin + out_ext_c_data = viv_s14; + out_ext_c_h_end = viv_s15; + out_ext_c_v_end = viv_s16; + out_ext_y_data = viv_s13; + out_ext_y_h_end = viv_s15; + out_ext_y_v_end = viv_s16; + case (cfg_chan_mode) + 2'd0: begin + out_y_m_data = {data_width{1'b0}}; + out_y_m_h_end = 1'b0; + out_y_m_v_end = 1'b0; + out_c_m_data = 8'b0; + out_c_m_h_end = 1'b0; + out_c_m_v_end = 1'b0; + out_y_s_data = {data_width{1'b0}}; + out_y_s_h_end = 1'b0; + out_y_s_v_end = 1'b0; + out_c_s_data = 8'b0; + out_c_s_h_end = 1'b0; + out_c_s_v_end = 1'b0; + end + 2'd1: begin + out_y_m_data = viv_s13; + out_y_m_h_end = viv_s15; + out_y_m_v_end = viv_s16; + out_c_m_data = viv_s14; + out_c_m_h_end = viv_s15; + out_c_m_v_end = viv_s16; + out_y_s_data = {data_width{1'b0}}; + out_y_s_h_end = 1'b0; + out_y_s_v_end = 1'b0; + out_c_s_data = {data_width{1'b0}}; + out_c_s_h_end = 1'b0; + out_c_s_v_end = 1'b0; + end + 2'd2: begin + out_y_m_data = {data_width{1'b0}}; + out_y_m_h_end = 1'b0; + out_y_m_v_end = 1'b0; + out_c_m_data = {data_width{1'b0}}; + out_c_m_h_end = 1'b0; + out_c_m_v_end = 1'b0; + out_y_s_data = viv_s13; + out_y_s_h_end = viv_s15; + out_y_s_v_end = viv_s16; + out_c_s_data = viv_s14; + out_c_s_h_end = viv_s15; + out_c_s_v_end = viv_s16; + end + default: begin + out_y_m_data = viv_s13; + out_y_m_h_end = viv_s15; + out_y_m_v_end = viv_s16; + out_c_m_data = viv_s14; + out_c_m_h_end = viv_s15; + out_c_m_v_end = viv_s16; + out_y_s_data = viv_s13; + out_y_s_h_end = viv_s15; + out_y_s_v_end = viv_s16; + out_c_s_data = viv_s14; + out_c_s_h_end = viv_s15; + out_c_s_v_end = viv_s16; + end + endcase + end + assign out_ext_y_val = viv_s22; + assign out_ext_c_val = viv_s23; + assign out_y_m_val = viv_s18; + assign out_y_s_val = viv_s19; + assign out_c_m_val = viv_s20; + assign out_c_s_val = viv_s21; + assign out_cfg_upd = viv_s17; +endmodule
diff --git a/ispyocto/rtl/rams/vsisp_RAM1P128W28B_SS.v b/ispyocto/rtl/rams/vsisp_RAM1P128W28B_SS.v new file mode 100644 index 0000000..5bf5b66 --- /dev/null +++ b/ispyocto/rtl/rams/vsisp_RAM1P128W28B_SS.v
@@ -0,0 +1,88 @@ +//**************************************************************************** +// +// Copyright 2023 Vivante Corp. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_RAM1P128W28B_SS(D,Q,CLK,CEB,WEB,BWEB,A,CLKEN,TESTEN); + input [28-1:0] D; + output [28-1:0] Q; + input CLK; + input CEB; + input WEB; + input [28-1:0] BWEB; + input [7-1:0] A; + input CLKEN; + input TESTEN; +`ifdef CG_IN_RAM +wire CLK_; +vsisp_GC_CG_MOD GC_CG_READ(.enable(CLKEN), .ck_in(CLK), .ck_out(CLK_), .test(TESTEN)); +`else +wire CLK_ = CLK; +`endif + reg [28-1:0] mem_core [0:128-1]; + wire [28-1:0] temp = mem_core[A]; + `ifdef CG_IN_RAM + always @(posedge CLK_) + `else + always @(posedge CLK) + `endif + if (~WEB & ~CEB) mem_core[A] <= (temp & BWEB) | (D & ~BWEB); + wire [28-1:0] QN = mem_core[A]; + wire [28-1:0] Q; + vsisp_gc_den_reg #(28) QReg (.out(Q), .clk(CLK_), .in(QN), .reset_(1'b1), .en(~CEB & WEB)); + `ifdef VIVANTE_COLLECT_TOGGLE_INFO_IN_FLOPS_AND_RAMS + `ifdef VIVANTE_SAIF_TRIGGER + reg [31:0] clkToggle; + reg [31:0] outputToggle; + reg [31:0] toggleRegion; + integer i; + initial begin + clkToggle = 0; + outputToggle = 0; + toggleRegion = 0; + end + always @(negedge CLK_) begin + if(~CEB) begin + clkToggle <= clkToggle + 1'b1; + if ((QN != Q) & WEB) begin + for (i = 0; i <= 28-1; i = i + 1) begin + if(QN[i] != Q[i]) begin + outputToggle = outputToggle + 1'b1; + end + end + end + if(clkToggle[31] | outputToggle[31]) begin + $display("ERROR: %m - Toggle counter overflow."); + #10000; + $finish; + end + end + end + initial begin + forever begin + @(posedge `VIVANTE_SAIF_TRIGGER); + $display ("vsisp_RAM1P128W28B_SS TOGGLE: %d : %m : WIDTH: %d, CLK_TOGGLE: %d, OUT_TOGGLE: %d",toggleRegion,28,clkToggle,outputToggle); + clkToggle = 0; + outputToggle = 0; + toggleRegion = toggleRegion + 1; + end + end + `endif + `endif +endmodule
diff --git a/ispyocto/rtl/rams/vsisp_RAM1P320W168B_SS.v b/ispyocto/rtl/rams/vsisp_RAM1P320W168B_SS.v new file mode 100644 index 0000000..f5f1727 --- /dev/null +++ b/ispyocto/rtl/rams/vsisp_RAM1P320W168B_SS.v
@@ -0,0 +1,88 @@ +//**************************************************************************** +// +// Copyright 2023 Vivante Corp. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_RAM1P320W168B_SS(D,Q,CLK,CEB,WEB,BWEB,A,CLKEN,TESTEN); + input [168-1:0] D; + output [168-1:0] Q; + input CLK; + input CEB; + input WEB; + input [168-1:0] BWEB; + input [9-1:0] A; + input CLKEN; + input TESTEN; +`ifdef CG_IN_RAM +wire CLK_; +vsisp_GC_CG_MOD GC_CG_READ(.enable(CLKEN), .ck_in(CLK), .ck_out(CLK_), .test(TESTEN)); +`else +wire CLK_ = CLK; +`endif + reg [168-1:0] mem_core [0:320-1]; + wire [168-1:0] temp = mem_core[A]; + `ifdef CG_IN_RAM + always @(posedge CLK_) + `else + always @(posedge CLK) + `endif + if (~WEB & ~CEB) mem_core[A] <= (temp & BWEB) | (D & ~BWEB); + wire [168-1:0] QN = mem_core[A]; + wire [168-1:0] Q; + vsisp_gc_den_reg #(168) QReg (.out(Q), .clk(CLK_), .in(QN), .reset_(1'b1), .en(~CEB & WEB)); + `ifdef VIVANTE_COLLECT_TOGGLE_INFO_IN_FLOPS_AND_RAMS + `ifdef VIVANTE_SAIF_TRIGGER + reg [31:0] clkToggle; + reg [31:0] outputToggle; + reg [31:0] toggleRegion; + integer i; + initial begin + clkToggle = 0; + outputToggle = 0; + toggleRegion = 0; + end + always @(negedge CLK_) begin + if(~CEB) begin + clkToggle <= clkToggle + 1'b1; + if ((QN != Q) & WEB) begin + for (i = 0; i <= 168-1; i = i + 1) begin + if(QN[i] != Q[i]) begin + outputToggle = outputToggle + 1'b1; + end + end + end + if(clkToggle[31] | outputToggle[31]) begin + $display("ERROR: %m - Toggle counter overflow."); + #10000; + $finish; + end + end + end + initial begin + forever begin + @(posedge `VIVANTE_SAIF_TRIGGER); + $display ("vsisp_RAM1P320W168B_SS TOGGLE: %d : %m : WIDTH: %d, CLK_TOGGLE: %d, OUT_TOGGLE: %d",toggleRegion,168,clkToggle,outputToggle); + clkToggle = 0; + outputToggle = 0; + toggleRegion = toggleRegion + 1; + end + end + `endif + `endif +endmodule
diff --git a/ispyocto/rtl/rams/vsisp_RAM1P320W32B_SS.v b/ispyocto/rtl/rams/vsisp_RAM1P320W32B_SS.v new file mode 100644 index 0000000..89adbc7 --- /dev/null +++ b/ispyocto/rtl/rams/vsisp_RAM1P320W32B_SS.v
@@ -0,0 +1,88 @@ +//**************************************************************************** +// +// Copyright 2023 Vivante Corp. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_RAM1P320W32B_SS(D,Q,CLK,CEB,WEB,BWEB,A,CLKEN,TESTEN); + input [32-1:0] D; + output [32-1:0] Q; + input CLK; + input CEB; + input WEB; + input [32-1:0] BWEB; + input [9-1:0] A; + input CLKEN; + input TESTEN; +`ifdef CG_IN_RAM +wire CLK_; +vsisp_GC_CG_MOD GC_CG_READ(.enable(CLKEN), .ck_in(CLK), .ck_out(CLK_), .test(TESTEN)); +`else +wire CLK_ = CLK; +`endif + reg [32-1:0] mem_core [0:320-1]; + wire [32-1:0] temp = mem_core[A]; + `ifdef CG_IN_RAM + always @(posedge CLK_) + `else + always @(posedge CLK) + `endif + if (~WEB & ~CEB) mem_core[A] <= (temp & BWEB) | (D & ~BWEB); + wire [32-1:0] QN = mem_core[A]; + wire [32-1:0] Q; + vsisp_gc_den_reg #(32) QReg (.out(Q), .clk(CLK_), .in(QN), .reset_(1'b1), .en(~CEB & WEB)); + `ifdef VIVANTE_COLLECT_TOGGLE_INFO_IN_FLOPS_AND_RAMS + `ifdef VIVANTE_SAIF_TRIGGER + reg [31:0] clkToggle; + reg [31:0] outputToggle; + reg [31:0] toggleRegion; + integer i; + initial begin + clkToggle = 0; + outputToggle = 0; + toggleRegion = 0; + end + always @(negedge CLK_) begin + if(~CEB) begin + clkToggle <= clkToggle + 1'b1; + if ((QN != Q) & WEB) begin + for (i = 0; i <= 32-1; i = i + 1) begin + if(QN[i] != Q[i]) begin + outputToggle = outputToggle + 1'b1; + end + end + end + if(clkToggle[31] | outputToggle[31]) begin + $display("ERROR: %m - Toggle counter overflow."); + #10000; + $finish; + end + end + end + initial begin + forever begin + @(posedge `VIVANTE_SAIF_TRIGGER); + $display ("vsisp_RAM1P320W32B_SS TOGGLE: %d : %m : WIDTH: %d, CLK_TOGGLE: %d, OUT_TOGGLE: %d",toggleRegion,32,clkToggle,outputToggle); + clkToggle = 0; + outputToggle = 0; + toggleRegion = toggleRegion + 1; + end + end + `endif + `endif +endmodule
diff --git a/ispyocto/rtl/rams/vsisp_RAM1P80W66B_SS.v b/ispyocto/rtl/rams/vsisp_RAM1P80W66B_SS.v new file mode 100644 index 0000000..09f28e8 --- /dev/null +++ b/ispyocto/rtl/rams/vsisp_RAM1P80W66B_SS.v
@@ -0,0 +1,88 @@ +//**************************************************************************** +// +// Copyright 2023 Vivante Corp. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module vsisp_RAM1P80W66B_SS(D,Q,CLK,CEB,WEB,BWEB,A,CLKEN,TESTEN); + input [66-1:0] D; + output [66-1:0] Q; + input CLK; + input CEB; + input WEB; + input [66-1:0] BWEB; + input [7-1:0] A; + input CLKEN; + input TESTEN; +`ifdef CG_IN_RAM +wire CLK_; +vsisp_GC_CG_MOD GC_CG_READ(.enable(CLKEN), .ck_in(CLK), .ck_out(CLK_), .test(TESTEN)); +`else +wire CLK_ = CLK; +`endif + reg [66-1:0] mem_core [0:80-1]; + wire [66-1:0] temp = mem_core[A]; + `ifdef CG_IN_RAM + always @(posedge CLK_) + `else + always @(posedge CLK) + `endif + if (~WEB & ~CEB) mem_core[A] <= (temp & BWEB) | (D & ~BWEB); + wire [66-1:0] QN = mem_core[A]; + wire [66-1:0] Q; + vsisp_gc_den_reg #(66) QReg (.out(Q), .clk(CLK_), .in(QN), .reset_(1'b1), .en(~CEB & WEB)); + `ifdef VIVANTE_COLLECT_TOGGLE_INFO_IN_FLOPS_AND_RAMS + `ifdef VIVANTE_SAIF_TRIGGER + reg [31:0] clkToggle; + reg [31:0] outputToggle; + reg [31:0] toggleRegion; + integer i; + initial begin + clkToggle = 0; + outputToggle = 0; + toggleRegion = 0; + end + always @(negedge CLK_) begin + if(~CEB) begin + clkToggle <= clkToggle + 1'b1; + if ((QN != Q) & WEB) begin + for (i = 0; i <= 66-1; i = i + 1) begin + if(QN[i] != Q[i]) begin + outputToggle = outputToggle + 1'b1; + end + end + end + if(clkToggle[31] | outputToggle[31]) begin + $display("ERROR: %m - Toggle counter overflow."); + #10000; + $finish; + end + end + end + initial begin + forever begin + @(posedge `VIVANTE_SAIF_TRIGGER); + $display ("vsisp_RAM1P80W66B_SS TOGGLE: %d : %m : WIDTH: %d, CLK_TOGGLE: %d, OUT_TOGGLE: %d",toggleRegion,66,clkToggle,outputToggle); + clkToggle = 0; + outputToggle = 0; + toggleRegion = toggleRegion + 1; + end + end + `endif + `endif +endmodule
diff --git a/ispyocto/rtl/undef/vsisp_vsi_undef.v b/ispyocto/rtl/undef/vsisp_vsi_undef.v new file mode 100644 index 0000000..a9a92ae --- /dev/null +++ b/ispyocto/rtl/undef/vsisp_vsi_undef.v
@@ -0,0 +1,13 @@ +`undef VIVANTE_ASYNC_RESET +`undef RAM_IF_OUT +`undef MI_BURST_16_DMAFIFO_16 +`undef AQ_TIMESCALE_ON +`undef MARVIN_USE_SRAMFIFO_MIBP +`undef MARVIN_SCLK_MUX_DISABLE +`undef MARVIN_USE_SELF_PATH +`undef VIVANTE_RESET_DATA_FLOPS +`undef YUV_STREAM_OUT +`undef ISP_USE_TPG +`undef MARVIN_USE_SRAMFIFO_MIMP +`undef VS_USE_SRAMFIFO_MIMP +`undef ISP_USE_DGAIN