commit fd76e9f2edda0841547e9986f7dd749c60eaa26f
author Adam Jesionowski <jesionowski@google.com> Mon Jul 19 19:16:49 2021 +0000
committer Gerrit Code Review <noreply-gerritcodereview@google.com> Mon Jul 19 19:16:49 2021 +0000
tree f7299122ad82611a1005bf74a41e626cbc147415
parent 74425d190e76523e6605b647bb7643cc8618a027
parent cc7902e7a40902f6e86db85264d60687d023be4a

Merge "Update crt0 and matcha.ld to support IREE."

springbok/crt0.s

diff --git a/springbok/crt0.s b/springbok/crt0.s
index 8904159..08c7490 100644
--- a/springbok/crt0.s
+++ b/springbok/crt0.s
@@ -44,14 +44,14 @@
         csrw mstatus, a0
 
         # Set lmul=8 and clear the register file
-        vsetvli t0, zero, e8, m8
+        vsetvli t0, zero, e8, m8, ta, ma 
         vmv.v.i v0, 0
         vmv.v.i v8, 0
         vmv.v.i v16, 0
         vmv.v.i v24, 0
 
         # Set lmul=1
-        vsetvli t0, zero, e8, m1
+        vsetvli t0, zero, e8, m1, ta, ma 
 
         # Set vector extension to "clean"
         xori a0, a0, 0x600
@@ -60,7 +60,11 @@
         ###############################################################
         # Reset all other CSRs, and perform any other processor setup #
         ###############################################################
-        # TODO(jonathantate): Fill this out
+        # Enable floating point unit
+        csrr a0, mstatus
+        li a1, 0x2000
+        or a0, a0, a1
+        csrw mstatus, a0
 
         #############################################################
         # Clear BSS, stack and unused DTCM memory, set up sentinels #