Add vzext and vsext tests.

Change-Id: Id89ababab60effe35dc14e24467c330a7c3d26b5

tests/CMakeLists.txt

diff --git a/tests/CMakeLists.txt b/tests/CMakeLists.txt
index 4cd5d32..b98912a 100644
--- a/tests/CMakeLists.txt
+++ b/tests/CMakeLists.txt
@@ -83,6 +83,24 @@
    -Xlinker --defsym=__itcm_length__=128K
 )
 
+vec_cc_generated_test(
+  NAME
+    vsext
+  OPFMT
+    VXUNARY0
+  LINKOPTS
+   -Xlinker --defsym=__itcm_length__=128K
+)
+
+vec_cc_generated_test(
+  NAME
+    vzext
+  OPFMT
+    VXUNARY0
+  LINKOPTS
+   -Xlinker --defsym=__itcm_length__=128K
+)
+
 vec_cc_test(
   NAME
     vsetvl_test
@@ -125,4 +143,3 @@
   TIMEOUT
     40
 )
-

tests/scripts/generate_vector_tests.py

diff --git a/tests/scripts/generate_vector_tests.py b/tests/scripts/generate_vector_tests.py
index b3e002d..47f39fd 100644
--- a/tests/scripts/generate_vector_tests.py
+++ b/tests/scripts/generate_vector_tests.py
@@ -27,6 +27,7 @@
     'OPIVV':'opivv_test.tpl.cpp',
     'OPIVI':'opivi_test.tpl.cpp',
     'OPIVX':'opivx_test.tpl.cpp',
+    'VXUNARY0':'vxunary0_test.tpl.cpp'
 }
 
 parser.add_argument('--instruction-format',

tests/templates/vxunary0_test.tpl.cpp

diff --git a/tests/templates/vxunary0_test.tpl.cpp b/tests/templates/vxunary0_test.tpl.cpp
new file mode 100644
index 0000000..b43e968
--- /dev/null
+++ b/tests/templates/vxunary0_test.tpl.cpp
@@ -0,0 +1,57 @@
+<%inherit file="base.tpl.cpp"/>\
+
+namespace ${op_code}_test {
+namespace {
+
+using namespace test_v_helpers;
+
+uint8_t src_vector_1[MAXVL_BYTES];
+uint8_t dest_vector[MAXVL_BYTES];
+uint8_t ref_dest_vector[MAXVL_BYTES];
+
+class ${op_code.capitalize()}Test : public ::testing::Test {
+ protected:
+  void SetUp() override { zero_vector_registers(); }
+  void TearDown() override { zero_vector_registers(); }
+};
+% for fraction, sew in [(4, 32), (2, 16)]:
+% for lmul in [1, 2, 4, 8]:
+<%
+sign_type = "u" if "z" in op_code else ""
+src_type = "%sint%d_t" % (sign_type, sew/fraction)
+dest_type = "%sint%d_t" % (sign_type, sew)
+%>\
+TEST_F(${op_code.capitalize()}Test, VF${fraction}e${sew}m${lmul}) {
+  for (int i = 0; i < AVL_COUNT; i++) {
+    int32_t avl = AVLS[i];
+    int vlmax;
+    int vl;
+    std::tie(vlmax, vl) = vector_test_setup<${dest_type}>(
+        VLMUL::LMUL_M${lmul}, avl,
+        {src_vector_1, dest_vector, ref_dest_vector});
+    if (avl > vlmax) {
+      continue;
+    }
+    ${src_type} *ptr_vec_1 = reinterpret_cast<${src_type} *>(src_vector_1);
+    ${dest_type} *ptr_dest_vec = reinterpret_cast<${dest_type} *>(dest_vector);
+    ${dest_type} *ptr_ref_dest_vec = reinterpret_cast<${dest_type} *>(ref_dest_vector);
+    fill_random_vector<${src_type}>(ptr_vec_1, avl);
+    memset(dest_vector, 0, sizeof(dest_vector));
+    memset(ref_dest_vector, 0, sizeof(ref_dest_vector));
+    softrvv::${op_code}_v<${dest_type}, ${src_type}>(ptr_ref_dest_vec, ptr_vec_1, avl);
+    // Load vector registers
+    __asm__ volatile("vle${sew//fraction}.v v8, (%0)" : : "r"(ptr_vec_1));
+
+    // Run target instruction
+    __asm__ volatile("${op_code}.vf${fraction} v24, v8" ::);
+
+    // Store result vector register
+    __asm__ volatile("vse${sew}.v v24, (%0)" : : "r"(ptr_dest_vec));
+    // Check vector elements
+    assert_vec_elem_eq<${dest_type}>(vlmax, dest_vector, ref_dest_vector);
+  }
+}
+%endfor
+%endfor
+}  // namespace
+}  // namespace ${op_code}_test