/*
 * Copyright 2023 Google LLC
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

#include "vector_tests/include/test_vector.h"

#include <springbok.h>

#define MSTATUS_VS 0x00000600
#define enable_vec()                                        \
  do {                                                      \
    __asm__ volatile("csrs mstatus, %[bits];" ::[bits] "r"( \
        MSTATUS_VS & (MSTATUS_VS >> 1)));                   \
  } while (0);

uint32_t get_vtype(uint8_t vsew, uint8_t vlmul, bool tail_agnostic,
                   bool mask_agnostic) {
  return (vlmul & 0x7) | (vsew & 0x7) << 3 | (tail_agnostic & 0x1) << 6 |
         (mask_agnostic & 0x1) << 7;
}

uint32_t get_vtype_e8(uint8_t vlmul, bool tail_agnostic, bool mask_agnostic) {
  uint8_t vsew = 0;
  return get_vtype(vsew, vlmul, tail_agnostic, mask_agnostic);
}

uint32_t get_vtype_e16(uint8_t vlmul, bool tail_agnostic, bool mask_agnostic) {
  uint8_t vsew = 1;
  return get_vtype(vsew, vlmul, tail_agnostic, mask_agnostic);
}

uint32_t get_vtype_e32(uint8_t vlmul, bool tail_agnostic, bool mask_agnostic) {
  uint8_t vsew = 2;
  return get_vtype(vsew, vlmul, tail_agnostic, mask_agnostic);
}

uint32_t get_vtype_e64(uint8_t vlmul, bool tail_agnostic, bool mask_agnostic) {
  uint8_t vsew = 3;
  return get_vtype(vsew, vlmul, tail_agnostic, mask_agnostic);
}

int main(void) {
  LOG_INFO("Hello test_vector.c");
  LOG_INFO("Built at: " __DATE__ ", " __TIME__);

  uint32_t misa;
  __asm__ volatile("csrr %0, misa" : "=r"(misa));
  LOG_INFO("MISA: 0x%08x", (unsigned int)misa);

  uint32_t mstatus;
  __asm__ volatile("csrr %0, mstatus" : "=r"(mstatus));
  LOG_INFO("BEFORE MSTATUS: 0x%08x", (unsigned int)mstatus);

  enable_vec();

  __asm__ volatile("csrr %0, mstatus" : "=r"(mstatus));
  LOG_INFO("AFTER MSTATUS: 0x%08x", (unsigned int)mstatus);

  uint32_t vlenb;
  __asm__ volatile("csrr %0, vlenb" : "=r"(vlenb));
  LOG_INFO("VLENB: 0x%08x, VLEN: %u", (unsigned int)vlenb, vlenb << 3);

  assert(test_vector());
  LOG_INFO("test_main done.");
  return 0;
}