<%inherit file="base.tpl.cpp"/>\

namespace ${op_code}_vv_test {
namespace {

using namespace test_v_helpers;

uint8_t src_vector_1[MAXVL_BYTES];
uint8_t src_vector_2[MAXVL_BYTES];
uint8_t dest_vector[MAXVL_BYTES];
uint8_t ref_dest_vector[MAXVL_BYTES];

class ${op_code.capitalize()}Test : public ::testing::Test {
 protected:
  void SetUp() override { zero_vector_registers(); }
  void TearDown() override { zero_vector_registers(); }
};
<%
widening = parent.module.is_widening(op_code)
sews = parent.module.get_sews(op_code)
lmuls = parent.module.get_lmuls(op_code)
ref_opcode = parent.module.get_ref_opcode(op_code)
%>\
% for sew in sews:
% for lmul in lmuls:
<%
dest_type = parent.module.get_dest_type(op_code, sew)
src_type = parent.module.get_src_type(op_code, sew)
%>\

TEST_F(${op_code.capitalize()}Test, ${op_code.lower()}_vv${sew}m${lmul}) {
  for (int i = 0; i < AVL_COUNT; i++) {
    int32_t avl = AVLS[i];
    int vlmax;
    int vl;
    std::tie(vlmax, vl) = vector_test_setup<${src_type}>(
        VLMUL::LMUL_M${lmul}, avl,
        {src_vector_1, src_vector_2, dest_vector, ref_dest_vector});
    if (avl > vlmax) {
      continue;
    }
    ${src_type} *ptr_vec_1 = reinterpret_cast<${src_type} *>(src_vector_1);
    ${src_type} *ptr_vec_2 = reinterpret_cast<${src_type} *>(src_vector_2);
    ${dest_type} *ptr_dest_vec = reinterpret_cast<${dest_type} *>(dest_vector);
    ${dest_type} *ptr_ref_dest_vec = reinterpret_cast<${dest_type} *>(ref_dest_vector);

    // set up values to test up to index of the AVL
    fill_random_vector<${src_type}>(ptr_vec_1, avl);
    fill_random_vector<${src_type}>(ptr_vec_2, avl);
    memset(dest_vector, 0, MAXVL_BYTES);
    memset(ref_dest_vector, 0, MAXVL_BYTES);

    // Generate reference vector
% if widening:
    softrvv::${ref_opcode}_vv<${dest_type}, ${src_type}>(ptr_ref_dest_vec, ptr_vec_2, ptr_vec_1, avl);
%else:
    softrvv::${ref_opcode}_vv<${dest_type}>(ptr_ref_dest_vec, ptr_vec_2, ptr_vec_1, avl);
% endif
    // Load vector registers
    __asm__ volatile("vle${sew}.v v8, (%0)" : : "r"(ptr_vec_1));
    __asm__ volatile("vle${sew}.v v16, (%0)" : : "r"(ptr_vec_2));

    // Run target instruction
    __asm__ volatile("${op_code}.vv v24, v16, v8");

    // Store result vector register
% if widening:
    __asm__ volatile("vse${sew*2}.v v24, (%0)" : : "r"(ptr_dest_vec));
% else:
    __asm__ volatile("vse${sew}.v v24, (%0)" : : "r"(ptr_dest_vec));
% endif
    // Check vector elements
    assert_vec_elem_eq<${dest_type}>(vlmax, dest_vector, ref_dest_vector);
  }
}
%endfor
%endfor

}  // namespace
}  // namespace ${op_code}_vv_test