commit 15ae3a55e6ae457f82bbe96b69c400d4a8fff664
author Cindy Liu <hcindyl@google.com> Mon Sep 25 12:48:43 2023 -0700
committer Cindy Liu <hcindyl@google.com> Mon Sep 25 12:52:48 2023 -0700
tree 5fca740228a4525b915838a81b7c4234c030071e
parent 6c463d3239b9b92a14c75d4932b3cc6d3c47ac4c

Temporarily diable RVV disable test

Broken by https://github.com/antmicro/tlib/commit/5601901

Bug: 301981842
Change-Id: Ie564a51ca599d371d1bb6cb99a65316b4a8685f1

softrvv/tests/vec_disable_test.cpp

diff --git a/softrvv/tests/vec_disable_test.cpp b/softrvv/tests/vec_disable_test.cpp
index 579d7b5..c6626a6 100644
--- a/softrvv/tests/vec_disable_test.cpp
+++ b/softrvv/tests/vec_disable_test.cpp
@@ -5,7 +5,6 @@
 #include <stdlib.h>
 
 #include "pw_unit_test/framework.h"
-#include "softrvv.h"
 
 namespace vec_disable_test {
 namespace {
@@ -21,7 +20,8 @@
   void TearDown() override { softrvv::enable_rvv(); }
 };
 
-TEST_F(VecDisableTest, vec_disable) {
+// TODO(b/301981842): Re-enable the test.
+TEST_F(VecDisableTest, DISABLED_vec_disable) {
   uint32_t vl = 0;
   __asm__ volatile("vsetivli %[VL], %[AVL], e32, m1, tu, mu"
                    : [VL] "=r"(vl)