| [package] |
| name = "opentitan-matcha" |
| version = "0.1.0" |
| authors = ["Tock Project Developers <tock-dev@googlegroups.com>"] |
| build = "build.rs" |
| edition = "2018" |
| |
| [dependencies] |
| components = { path = "../../tock/boards/components" } |
| rv32i = { path = "../../tock/arch/rv32i" } |
| capsules = { path = "../../tock/capsules" } |
| kernel = { path = "../../tock/kernel" } |
| matcha = { path = "../chip" } |
| lowrisc = { path = "../../tock/chips/lowrisc" } |
| blob_fs = { path = "../../tock/libraries/blob_fs" } |
| |
| [features] |
| # OpenTitan Matcha SoC design can be synthesized or compiled for different targets. A |
| # target can be a specific FPGA board, an ASIC technology, or a simulation tool. |
| # Please see: https://docs.opentitan.org/doc/ug/getting_started/ for further |
| # information. |
| # |
| # OpenTitan Matcha CPU and possibly other components must be configured appropriately |
| # for a specific target: |
| # - fpga_nexysvideo: |
| # OpenTitan Matcha SoC design running on Nexys Video Artix-7 FPGA. |
| # |
| # - sim_verilator: |
| # OpenTitan Matcha SoC design simulated in Verilator. |
| fpga_nexysvideo = ["matcha/config_fpga_nexysvideo"] |
| sim_verilator = ["matcha/config_sim_verilator"] |
