diff --git a/hal/Cargo.toml b/hal/Cargo.toml
index 0ef0341..82d74bc 100644
--- a/hal/Cargo.toml
+++ b/hal/Cargo.toml
@@ -7,4 +7,3 @@
 core2 = { version = "0.3", default-features = false }
 kernel          = { path = "../../tock/kernel" }
 matcha_config   = { path = "../config" }
-reg_constants   = { path = "../reg_constants" }
diff --git a/hal/src/lib.rs b/hal/src/lib.rs
index 981df34..4cd367b 100644
--- a/hal/src/lib.rs
+++ b/hal/src/lib.rs
@@ -7,6 +7,7 @@
 
 pub mod dprintf_hal;
 pub mod mailbox_hal;
+pub mod plic_constants;
 pub mod plic_hal;
 pub mod timer_hal;
 pub mod uart_hal;
diff --git a/hal/src/plic_constants.rs b/hal/src/plic_constants.rs
new file mode 100644
index 0000000..6e9d598
--- /dev/null
+++ b/hal/src/plic_constants.rs
@@ -0,0 +1,1679 @@
+// Generated register constants for RV_PLIC
+
+// Copyright information found in source file:
+// Copyright lowRISC contributors.
+
+// Licensing information found in source file:
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// Number of interrupt sources
+pub const RV_PLIC_PARAM_NUM_SRC: u32 = 193;
+
+// Number of Targets (Harts)
+pub const RV_PLIC_PARAM_NUM_TARGET: u32 = 2;
+
+// Width of priority signals
+pub const RV_PLIC_PARAM_PRIO_WIDTH: u32 = 2;
+
+// Number of alerts
+pub const RV_PLIC_PARAM_NUM_ALERTS: u32 = 1;
+
+// Register width
+pub const RV_PLIC_PARAM_REG_WIDTH: u32 = 32;
+
+// Interrupt Source 0 Priority
+pub const RV_PLIC_PRIO0_REG_OFFSET: usize = 0x0;
+pub const RV_PLIC_PRIO0_PRIO0_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO0_PRIO0_OFFSET: usize = 0;
+
+// Interrupt Source 1 Priority
+pub const RV_PLIC_PRIO1_REG_OFFSET: usize = 0x4;
+pub const RV_PLIC_PRIO1_PRIO1_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO1_PRIO1_OFFSET: usize = 0;
+
+// Interrupt Source 2 Priority
+pub const RV_PLIC_PRIO2_REG_OFFSET: usize = 0x8;
+pub const RV_PLIC_PRIO2_PRIO2_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO2_PRIO2_OFFSET: usize = 0;
+
+// Interrupt Source 3 Priority
+pub const RV_PLIC_PRIO3_REG_OFFSET: usize = 0xc;
+pub const RV_PLIC_PRIO3_PRIO3_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO3_PRIO3_OFFSET: usize = 0;
+
+// Interrupt Source 4 Priority
+pub const RV_PLIC_PRIO4_REG_OFFSET: usize = 0x10;
+pub const RV_PLIC_PRIO4_PRIO4_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO4_PRIO4_OFFSET: usize = 0;
+
+// Interrupt Source 5 Priority
+pub const RV_PLIC_PRIO5_REG_OFFSET: usize = 0x14;
+pub const RV_PLIC_PRIO5_PRIO5_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO5_PRIO5_OFFSET: usize = 0;
+
+// Interrupt Source 6 Priority
+pub const RV_PLIC_PRIO6_REG_OFFSET: usize = 0x18;
+pub const RV_PLIC_PRIO6_PRIO6_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO6_PRIO6_OFFSET: usize = 0;
+
+// Interrupt Source 7 Priority
+pub const RV_PLIC_PRIO7_REG_OFFSET: usize = 0x1c;
+pub const RV_PLIC_PRIO7_PRIO7_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO7_PRIO7_OFFSET: usize = 0;
+
+// Interrupt Source 8 Priority
+pub const RV_PLIC_PRIO8_REG_OFFSET: usize = 0x20;
+pub const RV_PLIC_PRIO8_PRIO8_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO8_PRIO8_OFFSET: usize = 0;
+
+// Interrupt Source 9 Priority
+pub const RV_PLIC_PRIO9_REG_OFFSET: usize = 0x24;
+pub const RV_PLIC_PRIO9_PRIO9_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO9_PRIO9_OFFSET: usize = 0;
+
+// Interrupt Source 10 Priority
+pub const RV_PLIC_PRIO10_REG_OFFSET: usize = 0x28;
+pub const RV_PLIC_PRIO10_PRIO10_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO10_PRIO10_OFFSET: usize = 0;
+
+// Interrupt Source 11 Priority
+pub const RV_PLIC_PRIO11_REG_OFFSET: usize = 0x2c;
+pub const RV_PLIC_PRIO11_PRIO11_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO11_PRIO11_OFFSET: usize = 0;
+
+// Interrupt Source 12 Priority
+pub const RV_PLIC_PRIO12_REG_OFFSET: usize = 0x30;
+pub const RV_PLIC_PRIO12_PRIO12_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO12_PRIO12_OFFSET: usize = 0;
+
+// Interrupt Source 13 Priority
+pub const RV_PLIC_PRIO13_REG_OFFSET: usize = 0x34;
+pub const RV_PLIC_PRIO13_PRIO13_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO13_PRIO13_OFFSET: usize = 0;
+
+// Interrupt Source 14 Priority
+pub const RV_PLIC_PRIO14_REG_OFFSET: usize = 0x38;
+pub const RV_PLIC_PRIO14_PRIO14_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO14_PRIO14_OFFSET: usize = 0;
+
+// Interrupt Source 15 Priority
+pub const RV_PLIC_PRIO15_REG_OFFSET: usize = 0x3c;
+pub const RV_PLIC_PRIO15_PRIO15_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO15_PRIO15_OFFSET: usize = 0;
+
+// Interrupt Source 16 Priority
+pub const RV_PLIC_PRIO16_REG_OFFSET: usize = 0x40;
+pub const RV_PLIC_PRIO16_PRIO16_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO16_PRIO16_OFFSET: usize = 0;
+
+// Interrupt Source 17 Priority
+pub const RV_PLIC_PRIO17_REG_OFFSET: usize = 0x44;
+pub const RV_PLIC_PRIO17_PRIO17_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO17_PRIO17_OFFSET: usize = 0;
+
+// Interrupt Source 18 Priority
+pub const RV_PLIC_PRIO18_REG_OFFSET: usize = 0x48;
+pub const RV_PLIC_PRIO18_PRIO18_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO18_PRIO18_OFFSET: usize = 0;
+
+// Interrupt Source 19 Priority
+pub const RV_PLIC_PRIO19_REG_OFFSET: usize = 0x4c;
+pub const RV_PLIC_PRIO19_PRIO19_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO19_PRIO19_OFFSET: usize = 0;
+
+// Interrupt Source 20 Priority
+pub const RV_PLIC_PRIO20_REG_OFFSET: usize = 0x50;
+pub const RV_PLIC_PRIO20_PRIO20_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO20_PRIO20_OFFSET: usize = 0;
+
+// Interrupt Source 21 Priority
+pub const RV_PLIC_PRIO21_REG_OFFSET: usize = 0x54;
+pub const RV_PLIC_PRIO21_PRIO21_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO21_PRIO21_OFFSET: usize = 0;
+
+// Interrupt Source 22 Priority
+pub const RV_PLIC_PRIO22_REG_OFFSET: usize = 0x58;
+pub const RV_PLIC_PRIO22_PRIO22_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO22_PRIO22_OFFSET: usize = 0;
+
+// Interrupt Source 23 Priority
+pub const RV_PLIC_PRIO23_REG_OFFSET: usize = 0x5c;
+pub const RV_PLIC_PRIO23_PRIO23_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO23_PRIO23_OFFSET: usize = 0;
+
+// Interrupt Source 24 Priority
+pub const RV_PLIC_PRIO24_REG_OFFSET: usize = 0x60;
+pub const RV_PLIC_PRIO24_PRIO24_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO24_PRIO24_OFFSET: usize = 0;
+
+// Interrupt Source 25 Priority
+pub const RV_PLIC_PRIO25_REG_OFFSET: usize = 0x64;
+pub const RV_PLIC_PRIO25_PRIO25_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO25_PRIO25_OFFSET: usize = 0;
+
+// Interrupt Source 26 Priority
+pub const RV_PLIC_PRIO26_REG_OFFSET: usize = 0x68;
+pub const RV_PLIC_PRIO26_PRIO26_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO26_PRIO26_OFFSET: usize = 0;
+
+// Interrupt Source 27 Priority
+pub const RV_PLIC_PRIO27_REG_OFFSET: usize = 0x6c;
+pub const RV_PLIC_PRIO27_PRIO27_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO27_PRIO27_OFFSET: usize = 0;
+
+// Interrupt Source 28 Priority
+pub const RV_PLIC_PRIO28_REG_OFFSET: usize = 0x70;
+pub const RV_PLIC_PRIO28_PRIO28_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO28_PRIO28_OFFSET: usize = 0;
+
+// Interrupt Source 29 Priority
+pub const RV_PLIC_PRIO29_REG_OFFSET: usize = 0x74;
+pub const RV_PLIC_PRIO29_PRIO29_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO29_PRIO29_OFFSET: usize = 0;
+
+// Interrupt Source 30 Priority
+pub const RV_PLIC_PRIO30_REG_OFFSET: usize = 0x78;
+pub const RV_PLIC_PRIO30_PRIO30_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO30_PRIO30_OFFSET: usize = 0;
+
+// Interrupt Source 31 Priority
+pub const RV_PLIC_PRIO31_REG_OFFSET: usize = 0x7c;
+pub const RV_PLIC_PRIO31_PRIO31_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO31_PRIO31_OFFSET: usize = 0;
+
+// Interrupt Source 32 Priority
+pub const RV_PLIC_PRIO32_REG_OFFSET: usize = 0x80;
+pub const RV_PLIC_PRIO32_PRIO32_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO32_PRIO32_OFFSET: usize = 0;
+
+// Interrupt Source 33 Priority
+pub const RV_PLIC_PRIO33_REG_OFFSET: usize = 0x84;
+pub const RV_PLIC_PRIO33_PRIO33_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO33_PRIO33_OFFSET: usize = 0;
+
+// Interrupt Source 34 Priority
+pub const RV_PLIC_PRIO34_REG_OFFSET: usize = 0x88;
+pub const RV_PLIC_PRIO34_PRIO34_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO34_PRIO34_OFFSET: usize = 0;
+
+// Interrupt Source 35 Priority
+pub const RV_PLIC_PRIO35_REG_OFFSET: usize = 0x8c;
+pub const RV_PLIC_PRIO35_PRIO35_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO35_PRIO35_OFFSET: usize = 0;
+
+// Interrupt Source 36 Priority
+pub const RV_PLIC_PRIO36_REG_OFFSET: usize = 0x90;
+pub const RV_PLIC_PRIO36_PRIO36_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO36_PRIO36_OFFSET: usize = 0;
+
+// Interrupt Source 37 Priority
+pub const RV_PLIC_PRIO37_REG_OFFSET: usize = 0x94;
+pub const RV_PLIC_PRIO37_PRIO37_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO37_PRIO37_OFFSET: usize = 0;
+
+// Interrupt Source 38 Priority
+pub const RV_PLIC_PRIO38_REG_OFFSET: usize = 0x98;
+pub const RV_PLIC_PRIO38_PRIO38_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO38_PRIO38_OFFSET: usize = 0;
+
+// Interrupt Source 39 Priority
+pub const RV_PLIC_PRIO39_REG_OFFSET: usize = 0x9c;
+pub const RV_PLIC_PRIO39_PRIO39_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO39_PRIO39_OFFSET: usize = 0;
+
+// Interrupt Source 40 Priority
+pub const RV_PLIC_PRIO40_REG_OFFSET: usize = 0xa0;
+pub const RV_PLIC_PRIO40_PRIO40_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO40_PRIO40_OFFSET: usize = 0;
+
+// Interrupt Source 41 Priority
+pub const RV_PLIC_PRIO41_REG_OFFSET: usize = 0xa4;
+pub const RV_PLIC_PRIO41_PRIO41_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO41_PRIO41_OFFSET: usize = 0;
+
+// Interrupt Source 42 Priority
+pub const RV_PLIC_PRIO42_REG_OFFSET: usize = 0xa8;
+pub const RV_PLIC_PRIO42_PRIO42_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO42_PRIO42_OFFSET: usize = 0;
+
+// Interrupt Source 43 Priority
+pub const RV_PLIC_PRIO43_REG_OFFSET: usize = 0xac;
+pub const RV_PLIC_PRIO43_PRIO43_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO43_PRIO43_OFFSET: usize = 0;
+
+// Interrupt Source 44 Priority
+pub const RV_PLIC_PRIO44_REG_OFFSET: usize = 0xb0;
+pub const RV_PLIC_PRIO44_PRIO44_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO44_PRIO44_OFFSET: usize = 0;
+
+// Interrupt Source 45 Priority
+pub const RV_PLIC_PRIO45_REG_OFFSET: usize = 0xb4;
+pub const RV_PLIC_PRIO45_PRIO45_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO45_PRIO45_OFFSET: usize = 0;
+
+// Interrupt Source 46 Priority
+pub const RV_PLIC_PRIO46_REG_OFFSET: usize = 0xb8;
+pub const RV_PLIC_PRIO46_PRIO46_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO46_PRIO46_OFFSET: usize = 0;
+
+// Interrupt Source 47 Priority
+pub const RV_PLIC_PRIO47_REG_OFFSET: usize = 0xbc;
+pub const RV_PLIC_PRIO47_PRIO47_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO47_PRIO47_OFFSET: usize = 0;
+
+// Interrupt Source 48 Priority
+pub const RV_PLIC_PRIO48_REG_OFFSET: usize = 0xc0;
+pub const RV_PLIC_PRIO48_PRIO48_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO48_PRIO48_OFFSET: usize = 0;
+
+// Interrupt Source 49 Priority
+pub const RV_PLIC_PRIO49_REG_OFFSET: usize = 0xc4;
+pub const RV_PLIC_PRIO49_PRIO49_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO49_PRIO49_OFFSET: usize = 0;
+
+// Interrupt Source 50 Priority
+pub const RV_PLIC_PRIO50_REG_OFFSET: usize = 0xc8;
+pub const RV_PLIC_PRIO50_PRIO50_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO50_PRIO50_OFFSET: usize = 0;
+
+// Interrupt Source 51 Priority
+pub const RV_PLIC_PRIO51_REG_OFFSET: usize = 0xcc;
+pub const RV_PLIC_PRIO51_PRIO51_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO51_PRIO51_OFFSET: usize = 0;
+
+// Interrupt Source 52 Priority
+pub const RV_PLIC_PRIO52_REG_OFFSET: usize = 0xd0;
+pub const RV_PLIC_PRIO52_PRIO52_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO52_PRIO52_OFFSET: usize = 0;
+
+// Interrupt Source 53 Priority
+pub const RV_PLIC_PRIO53_REG_OFFSET: usize = 0xd4;
+pub const RV_PLIC_PRIO53_PRIO53_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO53_PRIO53_OFFSET: usize = 0;
+
+// Interrupt Source 54 Priority
+pub const RV_PLIC_PRIO54_REG_OFFSET: usize = 0xd8;
+pub const RV_PLIC_PRIO54_PRIO54_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO54_PRIO54_OFFSET: usize = 0;
+
+// Interrupt Source 55 Priority
+pub const RV_PLIC_PRIO55_REG_OFFSET: usize = 0xdc;
+pub const RV_PLIC_PRIO55_PRIO55_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO55_PRIO55_OFFSET: usize = 0;
+
+// Interrupt Source 56 Priority
+pub const RV_PLIC_PRIO56_REG_OFFSET: usize = 0xe0;
+pub const RV_PLIC_PRIO56_PRIO56_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO56_PRIO56_OFFSET: usize = 0;
+
+// Interrupt Source 57 Priority
+pub const RV_PLIC_PRIO57_REG_OFFSET: usize = 0xe4;
+pub const RV_PLIC_PRIO57_PRIO57_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO57_PRIO57_OFFSET: usize = 0;
+
+// Interrupt Source 58 Priority
+pub const RV_PLIC_PRIO58_REG_OFFSET: usize = 0xe8;
+pub const RV_PLIC_PRIO58_PRIO58_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO58_PRIO58_OFFSET: usize = 0;
+
+// Interrupt Source 59 Priority
+pub const RV_PLIC_PRIO59_REG_OFFSET: usize = 0xec;
+pub const RV_PLIC_PRIO59_PRIO59_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO59_PRIO59_OFFSET: usize = 0;
+
+// Interrupt Source 60 Priority
+pub const RV_PLIC_PRIO60_REG_OFFSET: usize = 0xf0;
+pub const RV_PLIC_PRIO60_PRIO60_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO60_PRIO60_OFFSET: usize = 0;
+
+// Interrupt Source 61 Priority
+pub const RV_PLIC_PRIO61_REG_OFFSET: usize = 0xf4;
+pub const RV_PLIC_PRIO61_PRIO61_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO61_PRIO61_OFFSET: usize = 0;
+
+// Interrupt Source 62 Priority
+pub const RV_PLIC_PRIO62_REG_OFFSET: usize = 0xf8;
+pub const RV_PLIC_PRIO62_PRIO62_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO62_PRIO62_OFFSET: usize = 0;
+
+// Interrupt Source 63 Priority
+pub const RV_PLIC_PRIO63_REG_OFFSET: usize = 0xfc;
+pub const RV_PLIC_PRIO63_PRIO63_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO63_PRIO63_OFFSET: usize = 0;
+
+// Interrupt Source 64 Priority
+pub const RV_PLIC_PRIO64_REG_OFFSET: usize = 0x100;
+pub const RV_PLIC_PRIO64_PRIO64_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO64_PRIO64_OFFSET: usize = 0;
+
+// Interrupt Source 65 Priority
+pub const RV_PLIC_PRIO65_REG_OFFSET: usize = 0x104;
+pub const RV_PLIC_PRIO65_PRIO65_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO65_PRIO65_OFFSET: usize = 0;
+
+// Interrupt Source 66 Priority
+pub const RV_PLIC_PRIO66_REG_OFFSET: usize = 0x108;
+pub const RV_PLIC_PRIO66_PRIO66_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO66_PRIO66_OFFSET: usize = 0;
+
+// Interrupt Source 67 Priority
+pub const RV_PLIC_PRIO67_REG_OFFSET: usize = 0x10c;
+pub const RV_PLIC_PRIO67_PRIO67_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO67_PRIO67_OFFSET: usize = 0;
+
+// Interrupt Source 68 Priority
+pub const RV_PLIC_PRIO68_REG_OFFSET: usize = 0x110;
+pub const RV_PLIC_PRIO68_PRIO68_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO68_PRIO68_OFFSET: usize = 0;
+
+// Interrupt Source 69 Priority
+pub const RV_PLIC_PRIO69_REG_OFFSET: usize = 0x114;
+pub const RV_PLIC_PRIO69_PRIO69_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO69_PRIO69_OFFSET: usize = 0;
+
+// Interrupt Source 70 Priority
+pub const RV_PLIC_PRIO70_REG_OFFSET: usize = 0x118;
+pub const RV_PLIC_PRIO70_PRIO70_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO70_PRIO70_OFFSET: usize = 0;
+
+// Interrupt Source 71 Priority
+pub const RV_PLIC_PRIO71_REG_OFFSET: usize = 0x11c;
+pub const RV_PLIC_PRIO71_PRIO71_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO71_PRIO71_OFFSET: usize = 0;
+
+// Interrupt Source 72 Priority
+pub const RV_PLIC_PRIO72_REG_OFFSET: usize = 0x120;
+pub const RV_PLIC_PRIO72_PRIO72_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO72_PRIO72_OFFSET: usize = 0;
+
+// Interrupt Source 73 Priority
+pub const RV_PLIC_PRIO73_REG_OFFSET: usize = 0x124;
+pub const RV_PLIC_PRIO73_PRIO73_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO73_PRIO73_OFFSET: usize = 0;
+
+// Interrupt Source 74 Priority
+pub const RV_PLIC_PRIO74_REG_OFFSET: usize = 0x128;
+pub const RV_PLIC_PRIO74_PRIO74_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO74_PRIO74_OFFSET: usize = 0;
+
+// Interrupt Source 75 Priority
+pub const RV_PLIC_PRIO75_REG_OFFSET: usize = 0x12c;
+pub const RV_PLIC_PRIO75_PRIO75_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO75_PRIO75_OFFSET: usize = 0;
+
+// Interrupt Source 76 Priority
+pub const RV_PLIC_PRIO76_REG_OFFSET: usize = 0x130;
+pub const RV_PLIC_PRIO76_PRIO76_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO76_PRIO76_OFFSET: usize = 0;
+
+// Interrupt Source 77 Priority
+pub const RV_PLIC_PRIO77_REG_OFFSET: usize = 0x134;
+pub const RV_PLIC_PRIO77_PRIO77_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO77_PRIO77_OFFSET: usize = 0;
+
+// Interrupt Source 78 Priority
+pub const RV_PLIC_PRIO78_REG_OFFSET: usize = 0x138;
+pub const RV_PLIC_PRIO78_PRIO78_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO78_PRIO78_OFFSET: usize = 0;
+
+// Interrupt Source 79 Priority
+pub const RV_PLIC_PRIO79_REG_OFFSET: usize = 0x13c;
+pub const RV_PLIC_PRIO79_PRIO79_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO79_PRIO79_OFFSET: usize = 0;
+
+// Interrupt Source 80 Priority
+pub const RV_PLIC_PRIO80_REG_OFFSET: usize = 0x140;
+pub const RV_PLIC_PRIO80_PRIO80_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO80_PRIO80_OFFSET: usize = 0;
+
+// Interrupt Source 81 Priority
+pub const RV_PLIC_PRIO81_REG_OFFSET: usize = 0x144;
+pub const RV_PLIC_PRIO81_PRIO81_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO81_PRIO81_OFFSET: usize = 0;
+
+// Interrupt Source 82 Priority
+pub const RV_PLIC_PRIO82_REG_OFFSET: usize = 0x148;
+pub const RV_PLIC_PRIO82_PRIO82_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO82_PRIO82_OFFSET: usize = 0;
+
+// Interrupt Source 83 Priority
+pub const RV_PLIC_PRIO83_REG_OFFSET: usize = 0x14c;
+pub const RV_PLIC_PRIO83_PRIO83_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO83_PRIO83_OFFSET: usize = 0;
+
+// Interrupt Source 84 Priority
+pub const RV_PLIC_PRIO84_REG_OFFSET: usize = 0x150;
+pub const RV_PLIC_PRIO84_PRIO84_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO84_PRIO84_OFFSET: usize = 0;
+
+// Interrupt Source 85 Priority
+pub const RV_PLIC_PRIO85_REG_OFFSET: usize = 0x154;
+pub const RV_PLIC_PRIO85_PRIO85_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO85_PRIO85_OFFSET: usize = 0;
+
+// Interrupt Source 86 Priority
+pub const RV_PLIC_PRIO86_REG_OFFSET: usize = 0x158;
+pub const RV_PLIC_PRIO86_PRIO86_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO86_PRIO86_OFFSET: usize = 0;
+
+// Interrupt Source 87 Priority
+pub const RV_PLIC_PRIO87_REG_OFFSET: usize = 0x15c;
+pub const RV_PLIC_PRIO87_PRIO87_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO87_PRIO87_OFFSET: usize = 0;
+
+// Interrupt Source 88 Priority
+pub const RV_PLIC_PRIO88_REG_OFFSET: usize = 0x160;
+pub const RV_PLIC_PRIO88_PRIO88_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO88_PRIO88_OFFSET: usize = 0;
+
+// Interrupt Source 89 Priority
+pub const RV_PLIC_PRIO89_REG_OFFSET: usize = 0x164;
+pub const RV_PLIC_PRIO89_PRIO89_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO89_PRIO89_OFFSET: usize = 0;
+
+// Interrupt Source 90 Priority
+pub const RV_PLIC_PRIO90_REG_OFFSET: usize = 0x168;
+pub const RV_PLIC_PRIO90_PRIO90_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO90_PRIO90_OFFSET: usize = 0;
+
+// Interrupt Source 91 Priority
+pub const RV_PLIC_PRIO91_REG_OFFSET: usize = 0x16c;
+pub const RV_PLIC_PRIO91_PRIO91_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO91_PRIO91_OFFSET: usize = 0;
+
+// Interrupt Source 92 Priority
+pub const RV_PLIC_PRIO92_REG_OFFSET: usize = 0x170;
+pub const RV_PLIC_PRIO92_PRIO92_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO92_PRIO92_OFFSET: usize = 0;
+
+// Interrupt Source 93 Priority
+pub const RV_PLIC_PRIO93_REG_OFFSET: usize = 0x174;
+pub const RV_PLIC_PRIO93_PRIO93_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO93_PRIO93_OFFSET: usize = 0;
+
+// Interrupt Source 94 Priority
+pub const RV_PLIC_PRIO94_REG_OFFSET: usize = 0x178;
+pub const RV_PLIC_PRIO94_PRIO94_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO94_PRIO94_OFFSET: usize = 0;
+
+// Interrupt Source 95 Priority
+pub const RV_PLIC_PRIO95_REG_OFFSET: usize = 0x17c;
+pub const RV_PLIC_PRIO95_PRIO95_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO95_PRIO95_OFFSET: usize = 0;
+
+// Interrupt Source 96 Priority
+pub const RV_PLIC_PRIO96_REG_OFFSET: usize = 0x180;
+pub const RV_PLIC_PRIO96_PRIO96_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO96_PRIO96_OFFSET: usize = 0;
+
+// Interrupt Source 97 Priority
+pub const RV_PLIC_PRIO97_REG_OFFSET: usize = 0x184;
+pub const RV_PLIC_PRIO97_PRIO97_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO97_PRIO97_OFFSET: usize = 0;
+
+// Interrupt Source 98 Priority
+pub const RV_PLIC_PRIO98_REG_OFFSET: usize = 0x188;
+pub const RV_PLIC_PRIO98_PRIO98_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO98_PRIO98_OFFSET: usize = 0;
+
+// Interrupt Source 99 Priority
+pub const RV_PLIC_PRIO99_REG_OFFSET: usize = 0x18c;
+pub const RV_PLIC_PRIO99_PRIO99_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO99_PRIO99_OFFSET: usize = 0;
+
+// Interrupt Source 100 Priority
+pub const RV_PLIC_PRIO100_REG_OFFSET: usize = 0x190;
+pub const RV_PLIC_PRIO100_PRIO100_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO100_PRIO100_OFFSET: usize = 0;
+
+// Interrupt Source 101 Priority
+pub const RV_PLIC_PRIO101_REG_OFFSET: usize = 0x194;
+pub const RV_PLIC_PRIO101_PRIO101_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO101_PRIO101_OFFSET: usize = 0;
+
+// Interrupt Source 102 Priority
+pub const RV_PLIC_PRIO102_REG_OFFSET: usize = 0x198;
+pub const RV_PLIC_PRIO102_PRIO102_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO102_PRIO102_OFFSET: usize = 0;
+
+// Interrupt Source 103 Priority
+pub const RV_PLIC_PRIO103_REG_OFFSET: usize = 0x19c;
+pub const RV_PLIC_PRIO103_PRIO103_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO103_PRIO103_OFFSET: usize = 0;
+
+// Interrupt Source 104 Priority
+pub const RV_PLIC_PRIO104_REG_OFFSET: usize = 0x1a0;
+pub const RV_PLIC_PRIO104_PRIO104_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO104_PRIO104_OFFSET: usize = 0;
+
+// Interrupt Source 105 Priority
+pub const RV_PLIC_PRIO105_REG_OFFSET: usize = 0x1a4;
+pub const RV_PLIC_PRIO105_PRIO105_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO105_PRIO105_OFFSET: usize = 0;
+
+// Interrupt Source 106 Priority
+pub const RV_PLIC_PRIO106_REG_OFFSET: usize = 0x1a8;
+pub const RV_PLIC_PRIO106_PRIO106_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO106_PRIO106_OFFSET: usize = 0;
+
+// Interrupt Source 107 Priority
+pub const RV_PLIC_PRIO107_REG_OFFSET: usize = 0x1ac;
+pub const RV_PLIC_PRIO107_PRIO107_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO107_PRIO107_OFFSET: usize = 0;
+
+// Interrupt Source 108 Priority
+pub const RV_PLIC_PRIO108_REG_OFFSET: usize = 0x1b0;
+pub const RV_PLIC_PRIO108_PRIO108_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO108_PRIO108_OFFSET: usize = 0;
+
+// Interrupt Source 109 Priority
+pub const RV_PLIC_PRIO109_REG_OFFSET: usize = 0x1b4;
+pub const RV_PLIC_PRIO109_PRIO109_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO109_PRIO109_OFFSET: usize = 0;
+
+// Interrupt Source 110 Priority
+pub const RV_PLIC_PRIO110_REG_OFFSET: usize = 0x1b8;
+pub const RV_PLIC_PRIO110_PRIO110_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO110_PRIO110_OFFSET: usize = 0;
+
+// Interrupt Source 111 Priority
+pub const RV_PLIC_PRIO111_REG_OFFSET: usize = 0x1bc;
+pub const RV_PLIC_PRIO111_PRIO111_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO111_PRIO111_OFFSET: usize = 0;
+
+// Interrupt Source 112 Priority
+pub const RV_PLIC_PRIO112_REG_OFFSET: usize = 0x1c0;
+pub const RV_PLIC_PRIO112_PRIO112_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO112_PRIO112_OFFSET: usize = 0;
+
+// Interrupt Source 113 Priority
+pub const RV_PLIC_PRIO113_REG_OFFSET: usize = 0x1c4;
+pub const RV_PLIC_PRIO113_PRIO113_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO113_PRIO113_OFFSET: usize = 0;
+
+// Interrupt Source 114 Priority
+pub const RV_PLIC_PRIO114_REG_OFFSET: usize = 0x1c8;
+pub const RV_PLIC_PRIO114_PRIO114_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO114_PRIO114_OFFSET: usize = 0;
+
+// Interrupt Source 115 Priority
+pub const RV_PLIC_PRIO115_REG_OFFSET: usize = 0x1cc;
+pub const RV_PLIC_PRIO115_PRIO115_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO115_PRIO115_OFFSET: usize = 0;
+
+// Interrupt Source 116 Priority
+pub const RV_PLIC_PRIO116_REG_OFFSET: usize = 0x1d0;
+pub const RV_PLIC_PRIO116_PRIO116_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO116_PRIO116_OFFSET: usize = 0;
+
+// Interrupt Source 117 Priority
+pub const RV_PLIC_PRIO117_REG_OFFSET: usize = 0x1d4;
+pub const RV_PLIC_PRIO117_PRIO117_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO117_PRIO117_OFFSET: usize = 0;
+
+// Interrupt Source 118 Priority
+pub const RV_PLIC_PRIO118_REG_OFFSET: usize = 0x1d8;
+pub const RV_PLIC_PRIO118_PRIO118_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO118_PRIO118_OFFSET: usize = 0;
+
+// Interrupt Source 119 Priority
+pub const RV_PLIC_PRIO119_REG_OFFSET: usize = 0x1dc;
+pub const RV_PLIC_PRIO119_PRIO119_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO119_PRIO119_OFFSET: usize = 0;
+
+// Interrupt Source 120 Priority
+pub const RV_PLIC_PRIO120_REG_OFFSET: usize = 0x1e0;
+pub const RV_PLIC_PRIO120_PRIO120_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO120_PRIO120_OFFSET: usize = 0;
+
+// Interrupt Source 121 Priority
+pub const RV_PLIC_PRIO121_REG_OFFSET: usize = 0x1e4;
+pub const RV_PLIC_PRIO121_PRIO121_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO121_PRIO121_OFFSET: usize = 0;
+
+// Interrupt Source 122 Priority
+pub const RV_PLIC_PRIO122_REG_OFFSET: usize = 0x1e8;
+pub const RV_PLIC_PRIO122_PRIO122_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO122_PRIO122_OFFSET: usize = 0;
+
+// Interrupt Source 123 Priority
+pub const RV_PLIC_PRIO123_REG_OFFSET: usize = 0x1ec;
+pub const RV_PLIC_PRIO123_PRIO123_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO123_PRIO123_OFFSET: usize = 0;
+
+// Interrupt Source 124 Priority
+pub const RV_PLIC_PRIO124_REG_OFFSET: usize = 0x1f0;
+pub const RV_PLIC_PRIO124_PRIO124_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO124_PRIO124_OFFSET: usize = 0;
+
+// Interrupt Source 125 Priority
+pub const RV_PLIC_PRIO125_REG_OFFSET: usize = 0x1f4;
+pub const RV_PLIC_PRIO125_PRIO125_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO125_PRIO125_OFFSET: usize = 0;
+
+// Interrupt Source 126 Priority
+pub const RV_PLIC_PRIO126_REG_OFFSET: usize = 0x1f8;
+pub const RV_PLIC_PRIO126_PRIO126_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO126_PRIO126_OFFSET: usize = 0;
+
+// Interrupt Source 127 Priority
+pub const RV_PLIC_PRIO127_REG_OFFSET: usize = 0x1fc;
+pub const RV_PLIC_PRIO127_PRIO127_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO127_PRIO127_OFFSET: usize = 0;
+
+// Interrupt Source 128 Priority
+pub const RV_PLIC_PRIO128_REG_OFFSET: usize = 0x200;
+pub const RV_PLIC_PRIO128_PRIO128_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO128_PRIO128_OFFSET: usize = 0;
+
+// Interrupt Source 129 Priority
+pub const RV_PLIC_PRIO129_REG_OFFSET: usize = 0x204;
+pub const RV_PLIC_PRIO129_PRIO129_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO129_PRIO129_OFFSET: usize = 0;
+
+// Interrupt Source 130 Priority
+pub const RV_PLIC_PRIO130_REG_OFFSET: usize = 0x208;
+pub const RV_PLIC_PRIO130_PRIO130_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO130_PRIO130_OFFSET: usize = 0;
+
+// Interrupt Source 131 Priority
+pub const RV_PLIC_PRIO131_REG_OFFSET: usize = 0x20c;
+pub const RV_PLIC_PRIO131_PRIO131_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO131_PRIO131_OFFSET: usize = 0;
+
+// Interrupt Source 132 Priority
+pub const RV_PLIC_PRIO132_REG_OFFSET: usize = 0x210;
+pub const RV_PLIC_PRIO132_PRIO132_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO132_PRIO132_OFFSET: usize = 0;
+
+// Interrupt Source 133 Priority
+pub const RV_PLIC_PRIO133_REG_OFFSET: usize = 0x214;
+pub const RV_PLIC_PRIO133_PRIO133_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO133_PRIO133_OFFSET: usize = 0;
+
+// Interrupt Source 134 Priority
+pub const RV_PLIC_PRIO134_REG_OFFSET: usize = 0x218;
+pub const RV_PLIC_PRIO134_PRIO134_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO134_PRIO134_OFFSET: usize = 0;
+
+// Interrupt Source 135 Priority
+pub const RV_PLIC_PRIO135_REG_OFFSET: usize = 0x21c;
+pub const RV_PLIC_PRIO135_PRIO135_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO135_PRIO135_OFFSET: usize = 0;
+
+// Interrupt Source 136 Priority
+pub const RV_PLIC_PRIO136_REG_OFFSET: usize = 0x220;
+pub const RV_PLIC_PRIO136_PRIO136_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO136_PRIO136_OFFSET: usize = 0;
+
+// Interrupt Source 137 Priority
+pub const RV_PLIC_PRIO137_REG_OFFSET: usize = 0x224;
+pub const RV_PLIC_PRIO137_PRIO137_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO137_PRIO137_OFFSET: usize = 0;
+
+// Interrupt Source 138 Priority
+pub const RV_PLIC_PRIO138_REG_OFFSET: usize = 0x228;
+pub const RV_PLIC_PRIO138_PRIO138_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO138_PRIO138_OFFSET: usize = 0;
+
+// Interrupt Source 139 Priority
+pub const RV_PLIC_PRIO139_REG_OFFSET: usize = 0x22c;
+pub const RV_PLIC_PRIO139_PRIO139_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO139_PRIO139_OFFSET: usize = 0;
+
+// Interrupt Source 140 Priority
+pub const RV_PLIC_PRIO140_REG_OFFSET: usize = 0x230;
+pub const RV_PLIC_PRIO140_PRIO140_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO140_PRIO140_OFFSET: usize = 0;
+
+// Interrupt Source 141 Priority
+pub const RV_PLIC_PRIO141_REG_OFFSET: usize = 0x234;
+pub const RV_PLIC_PRIO141_PRIO141_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO141_PRIO141_OFFSET: usize = 0;
+
+// Interrupt Source 142 Priority
+pub const RV_PLIC_PRIO142_REG_OFFSET: usize = 0x238;
+pub const RV_PLIC_PRIO142_PRIO142_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO142_PRIO142_OFFSET: usize = 0;
+
+// Interrupt Source 143 Priority
+pub const RV_PLIC_PRIO143_REG_OFFSET: usize = 0x23c;
+pub const RV_PLIC_PRIO143_PRIO143_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO143_PRIO143_OFFSET: usize = 0;
+
+// Interrupt Source 144 Priority
+pub const RV_PLIC_PRIO144_REG_OFFSET: usize = 0x240;
+pub const RV_PLIC_PRIO144_PRIO144_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO144_PRIO144_OFFSET: usize = 0;
+
+// Interrupt Source 145 Priority
+pub const RV_PLIC_PRIO145_REG_OFFSET: usize = 0x244;
+pub const RV_PLIC_PRIO145_PRIO145_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO145_PRIO145_OFFSET: usize = 0;
+
+// Interrupt Source 146 Priority
+pub const RV_PLIC_PRIO146_REG_OFFSET: usize = 0x248;
+pub const RV_PLIC_PRIO146_PRIO146_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO146_PRIO146_OFFSET: usize = 0;
+
+// Interrupt Source 147 Priority
+pub const RV_PLIC_PRIO147_REG_OFFSET: usize = 0x24c;
+pub const RV_PLIC_PRIO147_PRIO147_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO147_PRIO147_OFFSET: usize = 0;
+
+// Interrupt Source 148 Priority
+pub const RV_PLIC_PRIO148_REG_OFFSET: usize = 0x250;
+pub const RV_PLIC_PRIO148_PRIO148_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO148_PRIO148_OFFSET: usize = 0;
+
+// Interrupt Source 149 Priority
+pub const RV_PLIC_PRIO149_REG_OFFSET: usize = 0x254;
+pub const RV_PLIC_PRIO149_PRIO149_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO149_PRIO149_OFFSET: usize = 0;
+
+// Interrupt Source 150 Priority
+pub const RV_PLIC_PRIO150_REG_OFFSET: usize = 0x258;
+pub const RV_PLIC_PRIO150_PRIO150_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO150_PRIO150_OFFSET: usize = 0;
+
+// Interrupt Source 151 Priority
+pub const RV_PLIC_PRIO151_REG_OFFSET: usize = 0x25c;
+pub const RV_PLIC_PRIO151_PRIO151_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO151_PRIO151_OFFSET: usize = 0;
+
+// Interrupt Source 152 Priority
+pub const RV_PLIC_PRIO152_REG_OFFSET: usize = 0x260;
+pub const RV_PLIC_PRIO152_PRIO152_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO152_PRIO152_OFFSET: usize = 0;
+
+// Interrupt Source 153 Priority
+pub const RV_PLIC_PRIO153_REG_OFFSET: usize = 0x264;
+pub const RV_PLIC_PRIO153_PRIO153_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO153_PRIO153_OFFSET: usize = 0;
+
+// Interrupt Source 154 Priority
+pub const RV_PLIC_PRIO154_REG_OFFSET: usize = 0x268;
+pub const RV_PLIC_PRIO154_PRIO154_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO154_PRIO154_OFFSET: usize = 0;
+
+// Interrupt Source 155 Priority
+pub const RV_PLIC_PRIO155_REG_OFFSET: usize = 0x26c;
+pub const RV_PLIC_PRIO155_PRIO155_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO155_PRIO155_OFFSET: usize = 0;
+
+// Interrupt Source 156 Priority
+pub const RV_PLIC_PRIO156_REG_OFFSET: usize = 0x270;
+pub const RV_PLIC_PRIO156_PRIO156_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO156_PRIO156_OFFSET: usize = 0;
+
+// Interrupt Source 157 Priority
+pub const RV_PLIC_PRIO157_REG_OFFSET: usize = 0x274;
+pub const RV_PLIC_PRIO157_PRIO157_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO157_PRIO157_OFFSET: usize = 0;
+
+// Interrupt Source 158 Priority
+pub const RV_PLIC_PRIO158_REG_OFFSET: usize = 0x278;
+pub const RV_PLIC_PRIO158_PRIO158_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO158_PRIO158_OFFSET: usize = 0;
+
+// Interrupt Source 159 Priority
+pub const RV_PLIC_PRIO159_REG_OFFSET: usize = 0x27c;
+pub const RV_PLIC_PRIO159_PRIO159_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO159_PRIO159_OFFSET: usize = 0;
+
+// Interrupt Source 160 Priority
+pub const RV_PLIC_PRIO160_REG_OFFSET: usize = 0x280;
+pub const RV_PLIC_PRIO160_PRIO160_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO160_PRIO160_OFFSET: usize = 0;
+
+// Interrupt Source 161 Priority
+pub const RV_PLIC_PRIO161_REG_OFFSET: usize = 0x284;
+pub const RV_PLIC_PRIO161_PRIO161_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO161_PRIO161_OFFSET: usize = 0;
+
+// Interrupt Source 162 Priority
+pub const RV_PLIC_PRIO162_REG_OFFSET: usize = 0x288;
+pub const RV_PLIC_PRIO162_PRIO162_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO162_PRIO162_OFFSET: usize = 0;
+
+// Interrupt Source 163 Priority
+pub const RV_PLIC_PRIO163_REG_OFFSET: usize = 0x28c;
+pub const RV_PLIC_PRIO163_PRIO163_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO163_PRIO163_OFFSET: usize = 0;
+
+// Interrupt Source 164 Priority
+pub const RV_PLIC_PRIO164_REG_OFFSET: usize = 0x290;
+pub const RV_PLIC_PRIO164_PRIO164_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO164_PRIO164_OFFSET: usize = 0;
+
+// Interrupt Source 165 Priority
+pub const RV_PLIC_PRIO165_REG_OFFSET: usize = 0x294;
+pub const RV_PLIC_PRIO165_PRIO165_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO165_PRIO165_OFFSET: usize = 0;
+
+// Interrupt Source 166 Priority
+pub const RV_PLIC_PRIO166_REG_OFFSET: usize = 0x298;
+pub const RV_PLIC_PRIO166_PRIO166_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO166_PRIO166_OFFSET: usize = 0;
+
+// Interrupt Source 167 Priority
+pub const RV_PLIC_PRIO167_REG_OFFSET: usize = 0x29c;
+pub const RV_PLIC_PRIO167_PRIO167_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO167_PRIO167_OFFSET: usize = 0;
+
+// Interrupt Source 168 Priority
+pub const RV_PLIC_PRIO168_REG_OFFSET: usize = 0x2a0;
+pub const RV_PLIC_PRIO168_PRIO168_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO168_PRIO168_OFFSET: usize = 0;
+
+// Interrupt Source 169 Priority
+pub const RV_PLIC_PRIO169_REG_OFFSET: usize = 0x2a4;
+pub const RV_PLIC_PRIO169_PRIO169_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO169_PRIO169_OFFSET: usize = 0;
+
+// Interrupt Source 170 Priority
+pub const RV_PLIC_PRIO170_REG_OFFSET: usize = 0x2a8;
+pub const RV_PLIC_PRIO170_PRIO170_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO170_PRIO170_OFFSET: usize = 0;
+
+// Interrupt Source 171 Priority
+pub const RV_PLIC_PRIO171_REG_OFFSET: usize = 0x2ac;
+pub const RV_PLIC_PRIO171_PRIO171_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO171_PRIO171_OFFSET: usize = 0;
+
+// Interrupt Source 172 Priority
+pub const RV_PLIC_PRIO172_REG_OFFSET: usize = 0x2b0;
+pub const RV_PLIC_PRIO172_PRIO172_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO172_PRIO172_OFFSET: usize = 0;
+
+// Interrupt Source 173 Priority
+pub const RV_PLIC_PRIO173_REG_OFFSET: usize = 0x2b4;
+pub const RV_PLIC_PRIO173_PRIO173_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO173_PRIO173_OFFSET: usize = 0;
+
+// Interrupt Source 174 Priority
+pub const RV_PLIC_PRIO174_REG_OFFSET: usize = 0x2b8;
+pub const RV_PLIC_PRIO174_PRIO174_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO174_PRIO174_OFFSET: usize = 0;
+
+// Interrupt Source 175 Priority
+pub const RV_PLIC_PRIO175_REG_OFFSET: usize = 0x2bc;
+pub const RV_PLIC_PRIO175_PRIO175_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO175_PRIO175_OFFSET: usize = 0;
+
+// Interrupt Source 176 Priority
+pub const RV_PLIC_PRIO176_REG_OFFSET: usize = 0x2c0;
+pub const RV_PLIC_PRIO176_PRIO176_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO176_PRIO176_OFFSET: usize = 0;
+
+// Interrupt Source 177 Priority
+pub const RV_PLIC_PRIO177_REG_OFFSET: usize = 0x2c4;
+pub const RV_PLIC_PRIO177_PRIO177_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO177_PRIO177_OFFSET: usize = 0;
+
+// Interrupt Source 178 Priority
+pub const RV_PLIC_PRIO178_REG_OFFSET: usize = 0x2c8;
+pub const RV_PLIC_PRIO178_PRIO178_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO178_PRIO178_OFFSET: usize = 0;
+
+// Interrupt Source 179 Priority
+pub const RV_PLIC_PRIO179_REG_OFFSET: usize = 0x2cc;
+pub const RV_PLIC_PRIO179_PRIO179_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO179_PRIO179_OFFSET: usize = 0;
+
+// Interrupt Source 180 Priority
+pub const RV_PLIC_PRIO180_REG_OFFSET: usize = 0x2d0;
+pub const RV_PLIC_PRIO180_PRIO180_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO180_PRIO180_OFFSET: usize = 0;
+
+// Interrupt Source 181 Priority
+pub const RV_PLIC_PRIO181_REG_OFFSET: usize = 0x2d4;
+pub const RV_PLIC_PRIO181_PRIO181_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO181_PRIO181_OFFSET: usize = 0;
+
+// Interrupt Source 182 Priority
+pub const RV_PLIC_PRIO182_REG_OFFSET: usize = 0x2d8;
+pub const RV_PLIC_PRIO182_PRIO182_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO182_PRIO182_OFFSET: usize = 0;
+
+// Interrupt Source 183 Priority
+pub const RV_PLIC_PRIO183_REG_OFFSET: usize = 0x2dc;
+pub const RV_PLIC_PRIO183_PRIO183_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO183_PRIO183_OFFSET: usize = 0;
+
+// Interrupt Source 184 Priority
+pub const RV_PLIC_PRIO184_REG_OFFSET: usize = 0x2e0;
+pub const RV_PLIC_PRIO184_PRIO184_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO184_PRIO184_OFFSET: usize = 0;
+
+// Interrupt Source 185 Priority
+pub const RV_PLIC_PRIO185_REG_OFFSET: usize = 0x2e4;
+pub const RV_PLIC_PRIO185_PRIO185_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO185_PRIO185_OFFSET: usize = 0;
+
+// Interrupt Source 186 Priority
+pub const RV_PLIC_PRIO186_REG_OFFSET: usize = 0x2e8;
+pub const RV_PLIC_PRIO186_PRIO186_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO186_PRIO186_OFFSET: usize = 0;
+
+// Interrupt Source 187 Priority
+pub const RV_PLIC_PRIO187_REG_OFFSET: usize = 0x2ec;
+pub const RV_PLIC_PRIO187_PRIO187_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO187_PRIO187_OFFSET: usize = 0;
+
+// Interrupt Source 188 Priority
+pub const RV_PLIC_PRIO188_REG_OFFSET: usize = 0x2f0;
+pub const RV_PLIC_PRIO188_PRIO188_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO188_PRIO188_OFFSET: usize = 0;
+
+// Interrupt Source 189 Priority
+pub const RV_PLIC_PRIO189_REG_OFFSET: usize = 0x2f4;
+pub const RV_PLIC_PRIO189_PRIO189_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO189_PRIO189_OFFSET: usize = 0;
+
+// Interrupt Source 190 Priority
+pub const RV_PLIC_PRIO190_REG_OFFSET: usize = 0x2f8;
+pub const RV_PLIC_PRIO190_PRIO190_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO190_PRIO190_OFFSET: usize = 0;
+
+// Interrupt Source 191 Priority
+pub const RV_PLIC_PRIO191_REG_OFFSET: usize = 0x2fc;
+pub const RV_PLIC_PRIO191_PRIO191_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO191_PRIO191_OFFSET: usize = 0;
+
+// Interrupt Source 192 Priority
+pub const RV_PLIC_PRIO192_REG_OFFSET: usize = 0x300;
+pub const RV_PLIC_PRIO192_PRIO192_MASK: u32 = 0x3;
+pub const RV_PLIC_PRIO192_PRIO192_OFFSET: usize = 0;
+
+// Interrupt Pending (common parameters)
+pub const RV_PLIC_IP_P_FIELD_WIDTH: u32 = 1;
+pub const RV_PLIC_IP_P_FIELDS_PER_REG: u32 = 32;
+pub const RV_PLIC_IP_MULTIREG_COUNT: u32 = 7;
+
+// Interrupt Pending
+pub const RV_PLIC_IP_0_REG_OFFSET: usize = 0x1000;
+pub const RV_PLIC_IP_0_P_0_BIT: u32 = 0;
+pub const RV_PLIC_IP_0_P_1_BIT: u32 = 1;
+pub const RV_PLIC_IP_0_P_2_BIT: u32 = 2;
+pub const RV_PLIC_IP_0_P_3_BIT: u32 = 3;
+pub const RV_PLIC_IP_0_P_4_BIT: u32 = 4;
+pub const RV_PLIC_IP_0_P_5_BIT: u32 = 5;
+pub const RV_PLIC_IP_0_P_6_BIT: u32 = 6;
+pub const RV_PLIC_IP_0_P_7_BIT: u32 = 7;
+pub const RV_PLIC_IP_0_P_8_BIT: u32 = 8;
+pub const RV_PLIC_IP_0_P_9_BIT: u32 = 9;
+pub const RV_PLIC_IP_0_P_10_BIT: u32 = 10;
+pub const RV_PLIC_IP_0_P_11_BIT: u32 = 11;
+pub const RV_PLIC_IP_0_P_12_BIT: u32 = 12;
+pub const RV_PLIC_IP_0_P_13_BIT: u32 = 13;
+pub const RV_PLIC_IP_0_P_14_BIT: u32 = 14;
+pub const RV_PLIC_IP_0_P_15_BIT: u32 = 15;
+pub const RV_PLIC_IP_0_P_16_BIT: u32 = 16;
+pub const RV_PLIC_IP_0_P_17_BIT: u32 = 17;
+pub const RV_PLIC_IP_0_P_18_BIT: u32 = 18;
+pub const RV_PLIC_IP_0_P_19_BIT: u32 = 19;
+pub const RV_PLIC_IP_0_P_20_BIT: u32 = 20;
+pub const RV_PLIC_IP_0_P_21_BIT: u32 = 21;
+pub const RV_PLIC_IP_0_P_22_BIT: u32 = 22;
+pub const RV_PLIC_IP_0_P_23_BIT: u32 = 23;
+pub const RV_PLIC_IP_0_P_24_BIT: u32 = 24;
+pub const RV_PLIC_IP_0_P_25_BIT: u32 = 25;
+pub const RV_PLIC_IP_0_P_26_BIT: u32 = 26;
+pub const RV_PLIC_IP_0_P_27_BIT: u32 = 27;
+pub const RV_PLIC_IP_0_P_28_BIT: u32 = 28;
+pub const RV_PLIC_IP_0_P_29_BIT: u32 = 29;
+pub const RV_PLIC_IP_0_P_30_BIT: u32 = 30;
+pub const RV_PLIC_IP_0_P_31_BIT: u32 = 31;
+
+// Interrupt Pending
+pub const RV_PLIC_IP_1_REG_OFFSET: usize = 0x1004;
+pub const RV_PLIC_IP_1_P_32_BIT: u32 = 0;
+pub const RV_PLIC_IP_1_P_33_BIT: u32 = 1;
+pub const RV_PLIC_IP_1_P_34_BIT: u32 = 2;
+pub const RV_PLIC_IP_1_P_35_BIT: u32 = 3;
+pub const RV_PLIC_IP_1_P_36_BIT: u32 = 4;
+pub const RV_PLIC_IP_1_P_37_BIT: u32 = 5;
+pub const RV_PLIC_IP_1_P_38_BIT: u32 = 6;
+pub const RV_PLIC_IP_1_P_39_BIT: u32 = 7;
+pub const RV_PLIC_IP_1_P_40_BIT: u32 = 8;
+pub const RV_PLIC_IP_1_P_41_BIT: u32 = 9;
+pub const RV_PLIC_IP_1_P_42_BIT: u32 = 10;
+pub const RV_PLIC_IP_1_P_43_BIT: u32 = 11;
+pub const RV_PLIC_IP_1_P_44_BIT: u32 = 12;
+pub const RV_PLIC_IP_1_P_45_BIT: u32 = 13;
+pub const RV_PLIC_IP_1_P_46_BIT: u32 = 14;
+pub const RV_PLIC_IP_1_P_47_BIT: u32 = 15;
+pub const RV_PLIC_IP_1_P_48_BIT: u32 = 16;
+pub const RV_PLIC_IP_1_P_49_BIT: u32 = 17;
+pub const RV_PLIC_IP_1_P_50_BIT: u32 = 18;
+pub const RV_PLIC_IP_1_P_51_BIT: u32 = 19;
+pub const RV_PLIC_IP_1_P_52_BIT: u32 = 20;
+pub const RV_PLIC_IP_1_P_53_BIT: u32 = 21;
+pub const RV_PLIC_IP_1_P_54_BIT: u32 = 22;
+pub const RV_PLIC_IP_1_P_55_BIT: u32 = 23;
+pub const RV_PLIC_IP_1_P_56_BIT: u32 = 24;
+pub const RV_PLIC_IP_1_P_57_BIT: u32 = 25;
+pub const RV_PLIC_IP_1_P_58_BIT: u32 = 26;
+pub const RV_PLIC_IP_1_P_59_BIT: u32 = 27;
+pub const RV_PLIC_IP_1_P_60_BIT: u32 = 28;
+pub const RV_PLIC_IP_1_P_61_BIT: u32 = 29;
+pub const RV_PLIC_IP_1_P_62_BIT: u32 = 30;
+pub const RV_PLIC_IP_1_P_63_BIT: u32 = 31;
+
+// Interrupt Pending
+pub const RV_PLIC_IP_2_REG_OFFSET: usize = 0x1008;
+pub const RV_PLIC_IP_2_P_64_BIT: u32 = 0;
+pub const RV_PLIC_IP_2_P_65_BIT: u32 = 1;
+pub const RV_PLIC_IP_2_P_66_BIT: u32 = 2;
+pub const RV_PLIC_IP_2_P_67_BIT: u32 = 3;
+pub const RV_PLIC_IP_2_P_68_BIT: u32 = 4;
+pub const RV_PLIC_IP_2_P_69_BIT: u32 = 5;
+pub const RV_PLIC_IP_2_P_70_BIT: u32 = 6;
+pub const RV_PLIC_IP_2_P_71_BIT: u32 = 7;
+pub const RV_PLIC_IP_2_P_72_BIT: u32 = 8;
+pub const RV_PLIC_IP_2_P_73_BIT: u32 = 9;
+pub const RV_PLIC_IP_2_P_74_BIT: u32 = 10;
+pub const RV_PLIC_IP_2_P_75_BIT: u32 = 11;
+pub const RV_PLIC_IP_2_P_76_BIT: u32 = 12;
+pub const RV_PLIC_IP_2_P_77_BIT: u32 = 13;
+pub const RV_PLIC_IP_2_P_78_BIT: u32 = 14;
+pub const RV_PLIC_IP_2_P_79_BIT: u32 = 15;
+pub const RV_PLIC_IP_2_P_80_BIT: u32 = 16;
+pub const RV_PLIC_IP_2_P_81_BIT: u32 = 17;
+pub const RV_PLIC_IP_2_P_82_BIT: u32 = 18;
+pub const RV_PLIC_IP_2_P_83_BIT: u32 = 19;
+pub const RV_PLIC_IP_2_P_84_BIT: u32 = 20;
+pub const RV_PLIC_IP_2_P_85_BIT: u32 = 21;
+pub const RV_PLIC_IP_2_P_86_BIT: u32 = 22;
+pub const RV_PLIC_IP_2_P_87_BIT: u32 = 23;
+pub const RV_PLIC_IP_2_P_88_BIT: u32 = 24;
+pub const RV_PLIC_IP_2_P_89_BIT: u32 = 25;
+pub const RV_PLIC_IP_2_P_90_BIT: u32 = 26;
+pub const RV_PLIC_IP_2_P_91_BIT: u32 = 27;
+pub const RV_PLIC_IP_2_P_92_BIT: u32 = 28;
+pub const RV_PLIC_IP_2_P_93_BIT: u32 = 29;
+pub const RV_PLIC_IP_2_P_94_BIT: u32 = 30;
+pub const RV_PLIC_IP_2_P_95_BIT: u32 = 31;
+
+// Interrupt Pending
+pub const RV_PLIC_IP_3_REG_OFFSET: usize = 0x100c;
+pub const RV_PLIC_IP_3_P_96_BIT: u32 = 0;
+pub const RV_PLIC_IP_3_P_97_BIT: u32 = 1;
+pub const RV_PLIC_IP_3_P_98_BIT: u32 = 2;
+pub const RV_PLIC_IP_3_P_99_BIT: u32 = 3;
+pub const RV_PLIC_IP_3_P_100_BIT: u32 = 4;
+pub const RV_PLIC_IP_3_P_101_BIT: u32 = 5;
+pub const RV_PLIC_IP_3_P_102_BIT: u32 = 6;
+pub const RV_PLIC_IP_3_P_103_BIT: u32 = 7;
+pub const RV_PLIC_IP_3_P_104_BIT: u32 = 8;
+pub const RV_PLIC_IP_3_P_105_BIT: u32 = 9;
+pub const RV_PLIC_IP_3_P_106_BIT: u32 = 10;
+pub const RV_PLIC_IP_3_P_107_BIT: u32 = 11;
+pub const RV_PLIC_IP_3_P_108_BIT: u32 = 12;
+pub const RV_PLIC_IP_3_P_109_BIT: u32 = 13;
+pub const RV_PLIC_IP_3_P_110_BIT: u32 = 14;
+pub const RV_PLIC_IP_3_P_111_BIT: u32 = 15;
+pub const RV_PLIC_IP_3_P_112_BIT: u32 = 16;
+pub const RV_PLIC_IP_3_P_113_BIT: u32 = 17;
+pub const RV_PLIC_IP_3_P_114_BIT: u32 = 18;
+pub const RV_PLIC_IP_3_P_115_BIT: u32 = 19;
+pub const RV_PLIC_IP_3_P_116_BIT: u32 = 20;
+pub const RV_PLIC_IP_3_P_117_BIT: u32 = 21;
+pub const RV_PLIC_IP_3_P_118_BIT: u32 = 22;
+pub const RV_PLIC_IP_3_P_119_BIT: u32 = 23;
+pub const RV_PLIC_IP_3_P_120_BIT: u32 = 24;
+pub const RV_PLIC_IP_3_P_121_BIT: u32 = 25;
+pub const RV_PLIC_IP_3_P_122_BIT: u32 = 26;
+pub const RV_PLIC_IP_3_P_123_BIT: u32 = 27;
+pub const RV_PLIC_IP_3_P_124_BIT: u32 = 28;
+pub const RV_PLIC_IP_3_P_125_BIT: u32 = 29;
+pub const RV_PLIC_IP_3_P_126_BIT: u32 = 30;
+pub const RV_PLIC_IP_3_P_127_BIT: u32 = 31;
+
+// Interrupt Pending
+pub const RV_PLIC_IP_4_REG_OFFSET: usize = 0x1010;
+pub const RV_PLIC_IP_4_P_128_BIT: u32 = 0;
+pub const RV_PLIC_IP_4_P_129_BIT: u32 = 1;
+pub const RV_PLIC_IP_4_P_130_BIT: u32 = 2;
+pub const RV_PLIC_IP_4_P_131_BIT: u32 = 3;
+pub const RV_PLIC_IP_4_P_132_BIT: u32 = 4;
+pub const RV_PLIC_IP_4_P_133_BIT: u32 = 5;
+pub const RV_PLIC_IP_4_P_134_BIT: u32 = 6;
+pub const RV_PLIC_IP_4_P_135_BIT: u32 = 7;
+pub const RV_PLIC_IP_4_P_136_BIT: u32 = 8;
+pub const RV_PLIC_IP_4_P_137_BIT: u32 = 9;
+pub const RV_PLIC_IP_4_P_138_BIT: u32 = 10;
+pub const RV_PLIC_IP_4_P_139_BIT: u32 = 11;
+pub const RV_PLIC_IP_4_P_140_BIT: u32 = 12;
+pub const RV_PLIC_IP_4_P_141_BIT: u32 = 13;
+pub const RV_PLIC_IP_4_P_142_BIT: u32 = 14;
+pub const RV_PLIC_IP_4_P_143_BIT: u32 = 15;
+pub const RV_PLIC_IP_4_P_144_BIT: u32 = 16;
+pub const RV_PLIC_IP_4_P_145_BIT: u32 = 17;
+pub const RV_PLIC_IP_4_P_146_BIT: u32 = 18;
+pub const RV_PLIC_IP_4_P_147_BIT: u32 = 19;
+pub const RV_PLIC_IP_4_P_148_BIT: u32 = 20;
+pub const RV_PLIC_IP_4_P_149_BIT: u32 = 21;
+pub const RV_PLIC_IP_4_P_150_BIT: u32 = 22;
+pub const RV_PLIC_IP_4_P_151_BIT: u32 = 23;
+pub const RV_PLIC_IP_4_P_152_BIT: u32 = 24;
+pub const RV_PLIC_IP_4_P_153_BIT: u32 = 25;
+pub const RV_PLIC_IP_4_P_154_BIT: u32 = 26;
+pub const RV_PLIC_IP_4_P_155_BIT: u32 = 27;
+pub const RV_PLIC_IP_4_P_156_BIT: u32 = 28;
+pub const RV_PLIC_IP_4_P_157_BIT: u32 = 29;
+pub const RV_PLIC_IP_4_P_158_BIT: u32 = 30;
+pub const RV_PLIC_IP_4_P_159_BIT: u32 = 31;
+
+// Interrupt Pending
+pub const RV_PLIC_IP_5_REG_OFFSET: usize = 0x1014;
+pub const RV_PLIC_IP_5_P_160_BIT: u32 = 0;
+pub const RV_PLIC_IP_5_P_161_BIT: u32 = 1;
+pub const RV_PLIC_IP_5_P_162_BIT: u32 = 2;
+pub const RV_PLIC_IP_5_P_163_BIT: u32 = 3;
+pub const RV_PLIC_IP_5_P_164_BIT: u32 = 4;
+pub const RV_PLIC_IP_5_P_165_BIT: u32 = 5;
+pub const RV_PLIC_IP_5_P_166_BIT: u32 = 6;
+pub const RV_PLIC_IP_5_P_167_BIT: u32 = 7;
+pub const RV_PLIC_IP_5_P_168_BIT: u32 = 8;
+pub const RV_PLIC_IP_5_P_169_BIT: u32 = 9;
+pub const RV_PLIC_IP_5_P_170_BIT: u32 = 10;
+pub const RV_PLIC_IP_5_P_171_BIT: u32 = 11;
+pub const RV_PLIC_IP_5_P_172_BIT: u32 = 12;
+pub const RV_PLIC_IP_5_P_173_BIT: u32 = 13;
+pub const RV_PLIC_IP_5_P_174_BIT: u32 = 14;
+pub const RV_PLIC_IP_5_P_175_BIT: u32 = 15;
+pub const RV_PLIC_IP_5_P_176_BIT: u32 = 16;
+pub const RV_PLIC_IP_5_P_177_BIT: u32 = 17;
+pub const RV_PLIC_IP_5_P_178_BIT: u32 = 18;
+pub const RV_PLIC_IP_5_P_179_BIT: u32 = 19;
+pub const RV_PLIC_IP_5_P_180_BIT: u32 = 20;
+pub const RV_PLIC_IP_5_P_181_BIT: u32 = 21;
+pub const RV_PLIC_IP_5_P_182_BIT: u32 = 22;
+pub const RV_PLIC_IP_5_P_183_BIT: u32 = 23;
+pub const RV_PLIC_IP_5_P_184_BIT: u32 = 24;
+pub const RV_PLIC_IP_5_P_185_BIT: u32 = 25;
+pub const RV_PLIC_IP_5_P_186_BIT: u32 = 26;
+pub const RV_PLIC_IP_5_P_187_BIT: u32 = 27;
+pub const RV_PLIC_IP_5_P_188_BIT: u32 = 28;
+pub const RV_PLIC_IP_5_P_189_BIT: u32 = 29;
+pub const RV_PLIC_IP_5_P_190_BIT: u32 = 30;
+pub const RV_PLIC_IP_5_P_191_BIT: u32 = 31;
+
+// Interrupt Pending
+pub const RV_PLIC_IP_6_REG_OFFSET: usize = 0x1018;
+pub const RV_PLIC_IP_6_P_192_BIT: u32 = 0;
+
+// Interrupt Enable for Target 0 (common parameters)
+pub const RV_PLIC_IE0_E_FIELD_WIDTH: u32 = 1;
+pub const RV_PLIC_IE0_E_FIELDS_PER_REG: u32 = 32;
+pub const RV_PLIC_IE0_MULTIREG_COUNT: u32 = 7;
+
+// Interrupt Enable for Target 0
+pub const RV_PLIC_IE0_0_REG_OFFSET: usize = 0x2000;
+pub const RV_PLIC_IE0_0_E_0_BIT: u32 = 0;
+pub const RV_PLIC_IE0_0_E_1_BIT: u32 = 1;
+pub const RV_PLIC_IE0_0_E_2_BIT: u32 = 2;
+pub const RV_PLIC_IE0_0_E_3_BIT: u32 = 3;
+pub const RV_PLIC_IE0_0_E_4_BIT: u32 = 4;
+pub const RV_PLIC_IE0_0_E_5_BIT: u32 = 5;
+pub const RV_PLIC_IE0_0_E_6_BIT: u32 = 6;
+pub const RV_PLIC_IE0_0_E_7_BIT: u32 = 7;
+pub const RV_PLIC_IE0_0_E_8_BIT: u32 = 8;
+pub const RV_PLIC_IE0_0_E_9_BIT: u32 = 9;
+pub const RV_PLIC_IE0_0_E_10_BIT: u32 = 10;
+pub const RV_PLIC_IE0_0_E_11_BIT: u32 = 11;
+pub const RV_PLIC_IE0_0_E_12_BIT: u32 = 12;
+pub const RV_PLIC_IE0_0_E_13_BIT: u32 = 13;
+pub const RV_PLIC_IE0_0_E_14_BIT: u32 = 14;
+pub const RV_PLIC_IE0_0_E_15_BIT: u32 = 15;
+pub const RV_PLIC_IE0_0_E_16_BIT: u32 = 16;
+pub const RV_PLIC_IE0_0_E_17_BIT: u32 = 17;
+pub const RV_PLIC_IE0_0_E_18_BIT: u32 = 18;
+pub const RV_PLIC_IE0_0_E_19_BIT: u32 = 19;
+pub const RV_PLIC_IE0_0_E_20_BIT: u32 = 20;
+pub const RV_PLIC_IE0_0_E_21_BIT: u32 = 21;
+pub const RV_PLIC_IE0_0_E_22_BIT: u32 = 22;
+pub const RV_PLIC_IE0_0_E_23_BIT: u32 = 23;
+pub const RV_PLIC_IE0_0_E_24_BIT: u32 = 24;
+pub const RV_PLIC_IE0_0_E_25_BIT: u32 = 25;
+pub const RV_PLIC_IE0_0_E_26_BIT: u32 = 26;
+pub const RV_PLIC_IE0_0_E_27_BIT: u32 = 27;
+pub const RV_PLIC_IE0_0_E_28_BIT: u32 = 28;
+pub const RV_PLIC_IE0_0_E_29_BIT: u32 = 29;
+pub const RV_PLIC_IE0_0_E_30_BIT: u32 = 30;
+pub const RV_PLIC_IE0_0_E_31_BIT: u32 = 31;
+
+// Interrupt Enable for Target 0
+pub const RV_PLIC_IE0_1_REG_OFFSET: usize = 0x2004;
+pub const RV_PLIC_IE0_1_E_32_BIT: u32 = 0;
+pub const RV_PLIC_IE0_1_E_33_BIT: u32 = 1;
+pub const RV_PLIC_IE0_1_E_34_BIT: u32 = 2;
+pub const RV_PLIC_IE0_1_E_35_BIT: u32 = 3;
+pub const RV_PLIC_IE0_1_E_36_BIT: u32 = 4;
+pub const RV_PLIC_IE0_1_E_37_BIT: u32 = 5;
+pub const RV_PLIC_IE0_1_E_38_BIT: u32 = 6;
+pub const RV_PLIC_IE0_1_E_39_BIT: u32 = 7;
+pub const RV_PLIC_IE0_1_E_40_BIT: u32 = 8;
+pub const RV_PLIC_IE0_1_E_41_BIT: u32 = 9;
+pub const RV_PLIC_IE0_1_E_42_BIT: u32 = 10;
+pub const RV_PLIC_IE0_1_E_43_BIT: u32 = 11;
+pub const RV_PLIC_IE0_1_E_44_BIT: u32 = 12;
+pub const RV_PLIC_IE0_1_E_45_BIT: u32 = 13;
+pub const RV_PLIC_IE0_1_E_46_BIT: u32 = 14;
+pub const RV_PLIC_IE0_1_E_47_BIT: u32 = 15;
+pub const RV_PLIC_IE0_1_E_48_BIT: u32 = 16;
+pub const RV_PLIC_IE0_1_E_49_BIT: u32 = 17;
+pub const RV_PLIC_IE0_1_E_50_BIT: u32 = 18;
+pub const RV_PLIC_IE0_1_E_51_BIT: u32 = 19;
+pub const RV_PLIC_IE0_1_E_52_BIT: u32 = 20;
+pub const RV_PLIC_IE0_1_E_53_BIT: u32 = 21;
+pub const RV_PLIC_IE0_1_E_54_BIT: u32 = 22;
+pub const RV_PLIC_IE0_1_E_55_BIT: u32 = 23;
+pub const RV_PLIC_IE0_1_E_56_BIT: u32 = 24;
+pub const RV_PLIC_IE0_1_E_57_BIT: u32 = 25;
+pub const RV_PLIC_IE0_1_E_58_BIT: u32 = 26;
+pub const RV_PLIC_IE0_1_E_59_BIT: u32 = 27;
+pub const RV_PLIC_IE0_1_E_60_BIT: u32 = 28;
+pub const RV_PLIC_IE0_1_E_61_BIT: u32 = 29;
+pub const RV_PLIC_IE0_1_E_62_BIT: u32 = 30;
+pub const RV_PLIC_IE0_1_E_63_BIT: u32 = 31;
+
+// Interrupt Enable for Target 0
+pub const RV_PLIC_IE0_2_REG_OFFSET: usize = 0x2008;
+pub const RV_PLIC_IE0_2_E_64_BIT: u32 = 0;
+pub const RV_PLIC_IE0_2_E_65_BIT: u32 = 1;
+pub const RV_PLIC_IE0_2_E_66_BIT: u32 = 2;
+pub const RV_PLIC_IE0_2_E_67_BIT: u32 = 3;
+pub const RV_PLIC_IE0_2_E_68_BIT: u32 = 4;
+pub const RV_PLIC_IE0_2_E_69_BIT: u32 = 5;
+pub const RV_PLIC_IE0_2_E_70_BIT: u32 = 6;
+pub const RV_PLIC_IE0_2_E_71_BIT: u32 = 7;
+pub const RV_PLIC_IE0_2_E_72_BIT: u32 = 8;
+pub const RV_PLIC_IE0_2_E_73_BIT: u32 = 9;
+pub const RV_PLIC_IE0_2_E_74_BIT: u32 = 10;
+pub const RV_PLIC_IE0_2_E_75_BIT: u32 = 11;
+pub const RV_PLIC_IE0_2_E_76_BIT: u32 = 12;
+pub const RV_PLIC_IE0_2_E_77_BIT: u32 = 13;
+pub const RV_PLIC_IE0_2_E_78_BIT: u32 = 14;
+pub const RV_PLIC_IE0_2_E_79_BIT: u32 = 15;
+pub const RV_PLIC_IE0_2_E_80_BIT: u32 = 16;
+pub const RV_PLIC_IE0_2_E_81_BIT: u32 = 17;
+pub const RV_PLIC_IE0_2_E_82_BIT: u32 = 18;
+pub const RV_PLIC_IE0_2_E_83_BIT: u32 = 19;
+pub const RV_PLIC_IE0_2_E_84_BIT: u32 = 20;
+pub const RV_PLIC_IE0_2_E_85_BIT: u32 = 21;
+pub const RV_PLIC_IE0_2_E_86_BIT: u32 = 22;
+pub const RV_PLIC_IE0_2_E_87_BIT: u32 = 23;
+pub const RV_PLIC_IE0_2_E_88_BIT: u32 = 24;
+pub const RV_PLIC_IE0_2_E_89_BIT: u32 = 25;
+pub const RV_PLIC_IE0_2_E_90_BIT: u32 = 26;
+pub const RV_PLIC_IE0_2_E_91_BIT: u32 = 27;
+pub const RV_PLIC_IE0_2_E_92_BIT: u32 = 28;
+pub const RV_PLIC_IE0_2_E_93_BIT: u32 = 29;
+pub const RV_PLIC_IE0_2_E_94_BIT: u32 = 30;
+pub const RV_PLIC_IE0_2_E_95_BIT: u32 = 31;
+
+// Interrupt Enable for Target 0
+pub const RV_PLIC_IE0_3_REG_OFFSET: usize = 0x200c;
+pub const RV_PLIC_IE0_3_E_96_BIT: u32 = 0;
+pub const RV_PLIC_IE0_3_E_97_BIT: u32 = 1;
+pub const RV_PLIC_IE0_3_E_98_BIT: u32 = 2;
+pub const RV_PLIC_IE0_3_E_99_BIT: u32 = 3;
+pub const RV_PLIC_IE0_3_E_100_BIT: u32 = 4;
+pub const RV_PLIC_IE0_3_E_101_BIT: u32 = 5;
+pub const RV_PLIC_IE0_3_E_102_BIT: u32 = 6;
+pub const RV_PLIC_IE0_3_E_103_BIT: u32 = 7;
+pub const RV_PLIC_IE0_3_E_104_BIT: u32 = 8;
+pub const RV_PLIC_IE0_3_E_105_BIT: u32 = 9;
+pub const RV_PLIC_IE0_3_E_106_BIT: u32 = 10;
+pub const RV_PLIC_IE0_3_E_107_BIT: u32 = 11;
+pub const RV_PLIC_IE0_3_E_108_BIT: u32 = 12;
+pub const RV_PLIC_IE0_3_E_109_BIT: u32 = 13;
+pub const RV_PLIC_IE0_3_E_110_BIT: u32 = 14;
+pub const RV_PLIC_IE0_3_E_111_BIT: u32 = 15;
+pub const RV_PLIC_IE0_3_E_112_BIT: u32 = 16;
+pub const RV_PLIC_IE0_3_E_113_BIT: u32 = 17;
+pub const RV_PLIC_IE0_3_E_114_BIT: u32 = 18;
+pub const RV_PLIC_IE0_3_E_115_BIT: u32 = 19;
+pub const RV_PLIC_IE0_3_E_116_BIT: u32 = 20;
+pub const RV_PLIC_IE0_3_E_117_BIT: u32 = 21;
+pub const RV_PLIC_IE0_3_E_118_BIT: u32 = 22;
+pub const RV_PLIC_IE0_3_E_119_BIT: u32 = 23;
+pub const RV_PLIC_IE0_3_E_120_BIT: u32 = 24;
+pub const RV_PLIC_IE0_3_E_121_BIT: u32 = 25;
+pub const RV_PLIC_IE0_3_E_122_BIT: u32 = 26;
+pub const RV_PLIC_IE0_3_E_123_BIT: u32 = 27;
+pub const RV_PLIC_IE0_3_E_124_BIT: u32 = 28;
+pub const RV_PLIC_IE0_3_E_125_BIT: u32 = 29;
+pub const RV_PLIC_IE0_3_E_126_BIT: u32 = 30;
+pub const RV_PLIC_IE0_3_E_127_BIT: u32 = 31;
+
+// Interrupt Enable for Target 0
+pub const RV_PLIC_IE0_4_REG_OFFSET: usize = 0x2010;
+pub const RV_PLIC_IE0_4_E_128_BIT: u32 = 0;
+pub const RV_PLIC_IE0_4_E_129_BIT: u32 = 1;
+pub const RV_PLIC_IE0_4_E_130_BIT: u32 = 2;
+pub const RV_PLIC_IE0_4_E_131_BIT: u32 = 3;
+pub const RV_PLIC_IE0_4_E_132_BIT: u32 = 4;
+pub const RV_PLIC_IE0_4_E_133_BIT: u32 = 5;
+pub const RV_PLIC_IE0_4_E_134_BIT: u32 = 6;
+pub const RV_PLIC_IE0_4_E_135_BIT: u32 = 7;
+pub const RV_PLIC_IE0_4_E_136_BIT: u32 = 8;
+pub const RV_PLIC_IE0_4_E_137_BIT: u32 = 9;
+pub const RV_PLIC_IE0_4_E_138_BIT: u32 = 10;
+pub const RV_PLIC_IE0_4_E_139_BIT: u32 = 11;
+pub const RV_PLIC_IE0_4_E_140_BIT: u32 = 12;
+pub const RV_PLIC_IE0_4_E_141_BIT: u32 = 13;
+pub const RV_PLIC_IE0_4_E_142_BIT: u32 = 14;
+pub const RV_PLIC_IE0_4_E_143_BIT: u32 = 15;
+pub const RV_PLIC_IE0_4_E_144_BIT: u32 = 16;
+pub const RV_PLIC_IE0_4_E_145_BIT: u32 = 17;
+pub const RV_PLIC_IE0_4_E_146_BIT: u32 = 18;
+pub const RV_PLIC_IE0_4_E_147_BIT: u32 = 19;
+pub const RV_PLIC_IE0_4_E_148_BIT: u32 = 20;
+pub const RV_PLIC_IE0_4_E_149_BIT: u32 = 21;
+pub const RV_PLIC_IE0_4_E_150_BIT: u32 = 22;
+pub const RV_PLIC_IE0_4_E_151_BIT: u32 = 23;
+pub const RV_PLIC_IE0_4_E_152_BIT: u32 = 24;
+pub const RV_PLIC_IE0_4_E_153_BIT: u32 = 25;
+pub const RV_PLIC_IE0_4_E_154_BIT: u32 = 26;
+pub const RV_PLIC_IE0_4_E_155_BIT: u32 = 27;
+pub const RV_PLIC_IE0_4_E_156_BIT: u32 = 28;
+pub const RV_PLIC_IE0_4_E_157_BIT: u32 = 29;
+pub const RV_PLIC_IE0_4_E_158_BIT: u32 = 30;
+pub const RV_PLIC_IE0_4_E_159_BIT: u32 = 31;
+
+// Interrupt Enable for Target 0
+pub const RV_PLIC_IE0_5_REG_OFFSET: usize = 0x2014;
+pub const RV_PLIC_IE0_5_E_160_BIT: u32 = 0;
+pub const RV_PLIC_IE0_5_E_161_BIT: u32 = 1;
+pub const RV_PLIC_IE0_5_E_162_BIT: u32 = 2;
+pub const RV_PLIC_IE0_5_E_163_BIT: u32 = 3;
+pub const RV_PLIC_IE0_5_E_164_BIT: u32 = 4;
+pub const RV_PLIC_IE0_5_E_165_BIT: u32 = 5;
+pub const RV_PLIC_IE0_5_E_166_BIT: u32 = 6;
+pub const RV_PLIC_IE0_5_E_167_BIT: u32 = 7;
+pub const RV_PLIC_IE0_5_E_168_BIT: u32 = 8;
+pub const RV_PLIC_IE0_5_E_169_BIT: u32 = 9;
+pub const RV_PLIC_IE0_5_E_170_BIT: u32 = 10;
+pub const RV_PLIC_IE0_5_E_171_BIT: u32 = 11;
+pub const RV_PLIC_IE0_5_E_172_BIT: u32 = 12;
+pub const RV_PLIC_IE0_5_E_173_BIT: u32 = 13;
+pub const RV_PLIC_IE0_5_E_174_BIT: u32 = 14;
+pub const RV_PLIC_IE0_5_E_175_BIT: u32 = 15;
+pub const RV_PLIC_IE0_5_E_176_BIT: u32 = 16;
+pub const RV_PLIC_IE0_5_E_177_BIT: u32 = 17;
+pub const RV_PLIC_IE0_5_E_178_BIT: u32 = 18;
+pub const RV_PLIC_IE0_5_E_179_BIT: u32 = 19;
+pub const RV_PLIC_IE0_5_E_180_BIT: u32 = 20;
+pub const RV_PLIC_IE0_5_E_181_BIT: u32 = 21;
+pub const RV_PLIC_IE0_5_E_182_BIT: u32 = 22;
+pub const RV_PLIC_IE0_5_E_183_BIT: u32 = 23;
+pub const RV_PLIC_IE0_5_E_184_BIT: u32 = 24;
+pub const RV_PLIC_IE0_5_E_185_BIT: u32 = 25;
+pub const RV_PLIC_IE0_5_E_186_BIT: u32 = 26;
+pub const RV_PLIC_IE0_5_E_187_BIT: u32 = 27;
+pub const RV_PLIC_IE0_5_E_188_BIT: u32 = 28;
+pub const RV_PLIC_IE0_5_E_189_BIT: u32 = 29;
+pub const RV_PLIC_IE0_5_E_190_BIT: u32 = 30;
+pub const RV_PLIC_IE0_5_E_191_BIT: u32 = 31;
+
+// Interrupt Enable for Target 0
+pub const RV_PLIC_IE0_6_REG_OFFSET: usize = 0x2018;
+pub const RV_PLIC_IE0_6_E_192_BIT: u32 = 0;
+
+// Interrupt Enable for Target 1 (common parameters)
+pub const RV_PLIC_IE1_E_FIELD_WIDTH: u32 = 1;
+pub const RV_PLIC_IE1_E_FIELDS_PER_REG: u32 = 32;
+pub const RV_PLIC_IE1_MULTIREG_COUNT: u32 = 7;
+
+// Interrupt Enable for Target 1
+pub const RV_PLIC_IE1_0_REG_OFFSET: usize = 0x2100;
+pub const RV_PLIC_IE1_0_E_0_BIT: u32 = 0;
+pub const RV_PLIC_IE1_0_E_1_BIT: u32 = 1;
+pub const RV_PLIC_IE1_0_E_2_BIT: u32 = 2;
+pub const RV_PLIC_IE1_0_E_3_BIT: u32 = 3;
+pub const RV_PLIC_IE1_0_E_4_BIT: u32 = 4;
+pub const RV_PLIC_IE1_0_E_5_BIT: u32 = 5;
+pub const RV_PLIC_IE1_0_E_6_BIT: u32 = 6;
+pub const RV_PLIC_IE1_0_E_7_BIT: u32 = 7;
+pub const RV_PLIC_IE1_0_E_8_BIT: u32 = 8;
+pub const RV_PLIC_IE1_0_E_9_BIT: u32 = 9;
+pub const RV_PLIC_IE1_0_E_10_BIT: u32 = 10;
+pub const RV_PLIC_IE1_0_E_11_BIT: u32 = 11;
+pub const RV_PLIC_IE1_0_E_12_BIT: u32 = 12;
+pub const RV_PLIC_IE1_0_E_13_BIT: u32 = 13;
+pub const RV_PLIC_IE1_0_E_14_BIT: u32 = 14;
+pub const RV_PLIC_IE1_0_E_15_BIT: u32 = 15;
+pub const RV_PLIC_IE1_0_E_16_BIT: u32 = 16;
+pub const RV_PLIC_IE1_0_E_17_BIT: u32 = 17;
+pub const RV_PLIC_IE1_0_E_18_BIT: u32 = 18;
+pub const RV_PLIC_IE1_0_E_19_BIT: u32 = 19;
+pub const RV_PLIC_IE1_0_E_20_BIT: u32 = 20;
+pub const RV_PLIC_IE1_0_E_21_BIT: u32 = 21;
+pub const RV_PLIC_IE1_0_E_22_BIT: u32 = 22;
+pub const RV_PLIC_IE1_0_E_23_BIT: u32 = 23;
+pub const RV_PLIC_IE1_0_E_24_BIT: u32 = 24;
+pub const RV_PLIC_IE1_0_E_25_BIT: u32 = 25;
+pub const RV_PLIC_IE1_0_E_26_BIT: u32 = 26;
+pub const RV_PLIC_IE1_0_E_27_BIT: u32 = 27;
+pub const RV_PLIC_IE1_0_E_28_BIT: u32 = 28;
+pub const RV_PLIC_IE1_0_E_29_BIT: u32 = 29;
+pub const RV_PLIC_IE1_0_E_30_BIT: u32 = 30;
+pub const RV_PLIC_IE1_0_E_31_BIT: u32 = 31;
+
+// Interrupt Enable for Target 1
+pub const RV_PLIC_IE1_1_REG_OFFSET: usize = 0x2104;
+pub const RV_PLIC_IE1_1_E_32_BIT: u32 = 0;
+pub const RV_PLIC_IE1_1_E_33_BIT: u32 = 1;
+pub const RV_PLIC_IE1_1_E_34_BIT: u32 = 2;
+pub const RV_PLIC_IE1_1_E_35_BIT: u32 = 3;
+pub const RV_PLIC_IE1_1_E_36_BIT: u32 = 4;
+pub const RV_PLIC_IE1_1_E_37_BIT: u32 = 5;
+pub const RV_PLIC_IE1_1_E_38_BIT: u32 = 6;
+pub const RV_PLIC_IE1_1_E_39_BIT: u32 = 7;
+pub const RV_PLIC_IE1_1_E_40_BIT: u32 = 8;
+pub const RV_PLIC_IE1_1_E_41_BIT: u32 = 9;
+pub const RV_PLIC_IE1_1_E_42_BIT: u32 = 10;
+pub const RV_PLIC_IE1_1_E_43_BIT: u32 = 11;
+pub const RV_PLIC_IE1_1_E_44_BIT: u32 = 12;
+pub const RV_PLIC_IE1_1_E_45_BIT: u32 = 13;
+pub const RV_PLIC_IE1_1_E_46_BIT: u32 = 14;
+pub const RV_PLIC_IE1_1_E_47_BIT: u32 = 15;
+pub const RV_PLIC_IE1_1_E_48_BIT: u32 = 16;
+pub const RV_PLIC_IE1_1_E_49_BIT: u32 = 17;
+pub const RV_PLIC_IE1_1_E_50_BIT: u32 = 18;
+pub const RV_PLIC_IE1_1_E_51_BIT: u32 = 19;
+pub const RV_PLIC_IE1_1_E_52_BIT: u32 = 20;
+pub const RV_PLIC_IE1_1_E_53_BIT: u32 = 21;
+pub const RV_PLIC_IE1_1_E_54_BIT: u32 = 22;
+pub const RV_PLIC_IE1_1_E_55_BIT: u32 = 23;
+pub const RV_PLIC_IE1_1_E_56_BIT: u32 = 24;
+pub const RV_PLIC_IE1_1_E_57_BIT: u32 = 25;
+pub const RV_PLIC_IE1_1_E_58_BIT: u32 = 26;
+pub const RV_PLIC_IE1_1_E_59_BIT: u32 = 27;
+pub const RV_PLIC_IE1_1_E_60_BIT: u32 = 28;
+pub const RV_PLIC_IE1_1_E_61_BIT: u32 = 29;
+pub const RV_PLIC_IE1_1_E_62_BIT: u32 = 30;
+pub const RV_PLIC_IE1_1_E_63_BIT: u32 = 31;
+
+// Interrupt Enable for Target 1
+pub const RV_PLIC_IE1_2_REG_OFFSET: usize = 0x2108;
+pub const RV_PLIC_IE1_2_E_64_BIT: u32 = 0;
+pub const RV_PLIC_IE1_2_E_65_BIT: u32 = 1;
+pub const RV_PLIC_IE1_2_E_66_BIT: u32 = 2;
+pub const RV_PLIC_IE1_2_E_67_BIT: u32 = 3;
+pub const RV_PLIC_IE1_2_E_68_BIT: u32 = 4;
+pub const RV_PLIC_IE1_2_E_69_BIT: u32 = 5;
+pub const RV_PLIC_IE1_2_E_70_BIT: u32 = 6;
+pub const RV_PLIC_IE1_2_E_71_BIT: u32 = 7;
+pub const RV_PLIC_IE1_2_E_72_BIT: u32 = 8;
+pub const RV_PLIC_IE1_2_E_73_BIT: u32 = 9;
+pub const RV_PLIC_IE1_2_E_74_BIT: u32 = 10;
+pub const RV_PLIC_IE1_2_E_75_BIT: u32 = 11;
+pub const RV_PLIC_IE1_2_E_76_BIT: u32 = 12;
+pub const RV_PLIC_IE1_2_E_77_BIT: u32 = 13;
+pub const RV_PLIC_IE1_2_E_78_BIT: u32 = 14;
+pub const RV_PLIC_IE1_2_E_79_BIT: u32 = 15;
+pub const RV_PLIC_IE1_2_E_80_BIT: u32 = 16;
+pub const RV_PLIC_IE1_2_E_81_BIT: u32 = 17;
+pub const RV_PLIC_IE1_2_E_82_BIT: u32 = 18;
+pub const RV_PLIC_IE1_2_E_83_BIT: u32 = 19;
+pub const RV_PLIC_IE1_2_E_84_BIT: u32 = 20;
+pub const RV_PLIC_IE1_2_E_85_BIT: u32 = 21;
+pub const RV_PLIC_IE1_2_E_86_BIT: u32 = 22;
+pub const RV_PLIC_IE1_2_E_87_BIT: u32 = 23;
+pub const RV_PLIC_IE1_2_E_88_BIT: u32 = 24;
+pub const RV_PLIC_IE1_2_E_89_BIT: u32 = 25;
+pub const RV_PLIC_IE1_2_E_90_BIT: u32 = 26;
+pub const RV_PLIC_IE1_2_E_91_BIT: u32 = 27;
+pub const RV_PLIC_IE1_2_E_92_BIT: u32 = 28;
+pub const RV_PLIC_IE1_2_E_93_BIT: u32 = 29;
+pub const RV_PLIC_IE1_2_E_94_BIT: u32 = 30;
+pub const RV_PLIC_IE1_2_E_95_BIT: u32 = 31;
+
+// Interrupt Enable for Target 1
+pub const RV_PLIC_IE1_3_REG_OFFSET: usize = 0x210c;
+pub const RV_PLIC_IE1_3_E_96_BIT: u32 = 0;
+pub const RV_PLIC_IE1_3_E_97_BIT: u32 = 1;
+pub const RV_PLIC_IE1_3_E_98_BIT: u32 = 2;
+pub const RV_PLIC_IE1_3_E_99_BIT: u32 = 3;
+pub const RV_PLIC_IE1_3_E_100_BIT: u32 = 4;
+pub const RV_PLIC_IE1_3_E_101_BIT: u32 = 5;
+pub const RV_PLIC_IE1_3_E_102_BIT: u32 = 6;
+pub const RV_PLIC_IE1_3_E_103_BIT: u32 = 7;
+pub const RV_PLIC_IE1_3_E_104_BIT: u32 = 8;
+pub const RV_PLIC_IE1_3_E_105_BIT: u32 = 9;
+pub const RV_PLIC_IE1_3_E_106_BIT: u32 = 10;
+pub const RV_PLIC_IE1_3_E_107_BIT: u32 = 11;
+pub const RV_PLIC_IE1_3_E_108_BIT: u32 = 12;
+pub const RV_PLIC_IE1_3_E_109_BIT: u32 = 13;
+pub const RV_PLIC_IE1_3_E_110_BIT: u32 = 14;
+pub const RV_PLIC_IE1_3_E_111_BIT: u32 = 15;
+pub const RV_PLIC_IE1_3_E_112_BIT: u32 = 16;
+pub const RV_PLIC_IE1_3_E_113_BIT: u32 = 17;
+pub const RV_PLIC_IE1_3_E_114_BIT: u32 = 18;
+pub const RV_PLIC_IE1_3_E_115_BIT: u32 = 19;
+pub const RV_PLIC_IE1_3_E_116_BIT: u32 = 20;
+pub const RV_PLIC_IE1_3_E_117_BIT: u32 = 21;
+pub const RV_PLIC_IE1_3_E_118_BIT: u32 = 22;
+pub const RV_PLIC_IE1_3_E_119_BIT: u32 = 23;
+pub const RV_PLIC_IE1_3_E_120_BIT: u32 = 24;
+pub const RV_PLIC_IE1_3_E_121_BIT: u32 = 25;
+pub const RV_PLIC_IE1_3_E_122_BIT: u32 = 26;
+pub const RV_PLIC_IE1_3_E_123_BIT: u32 = 27;
+pub const RV_PLIC_IE1_3_E_124_BIT: u32 = 28;
+pub const RV_PLIC_IE1_3_E_125_BIT: u32 = 29;
+pub const RV_PLIC_IE1_3_E_126_BIT: u32 = 30;
+pub const RV_PLIC_IE1_3_E_127_BIT: u32 = 31;
+
+// Interrupt Enable for Target 1
+pub const RV_PLIC_IE1_4_REG_OFFSET: usize = 0x2110;
+pub const RV_PLIC_IE1_4_E_128_BIT: u32 = 0;
+pub const RV_PLIC_IE1_4_E_129_BIT: u32 = 1;
+pub const RV_PLIC_IE1_4_E_130_BIT: u32 = 2;
+pub const RV_PLIC_IE1_4_E_131_BIT: u32 = 3;
+pub const RV_PLIC_IE1_4_E_132_BIT: u32 = 4;
+pub const RV_PLIC_IE1_4_E_133_BIT: u32 = 5;
+pub const RV_PLIC_IE1_4_E_134_BIT: u32 = 6;
+pub const RV_PLIC_IE1_4_E_135_BIT: u32 = 7;
+pub const RV_PLIC_IE1_4_E_136_BIT: u32 = 8;
+pub const RV_PLIC_IE1_4_E_137_BIT: u32 = 9;
+pub const RV_PLIC_IE1_4_E_138_BIT: u32 = 10;
+pub const RV_PLIC_IE1_4_E_139_BIT: u32 = 11;
+pub const RV_PLIC_IE1_4_E_140_BIT: u32 = 12;
+pub const RV_PLIC_IE1_4_E_141_BIT: u32 = 13;
+pub const RV_PLIC_IE1_4_E_142_BIT: u32 = 14;
+pub const RV_PLIC_IE1_4_E_143_BIT: u32 = 15;
+pub const RV_PLIC_IE1_4_E_144_BIT: u32 = 16;
+pub const RV_PLIC_IE1_4_E_145_BIT: u32 = 17;
+pub const RV_PLIC_IE1_4_E_146_BIT: u32 = 18;
+pub const RV_PLIC_IE1_4_E_147_BIT: u32 = 19;
+pub const RV_PLIC_IE1_4_E_148_BIT: u32 = 20;
+pub const RV_PLIC_IE1_4_E_149_BIT: u32 = 21;
+pub const RV_PLIC_IE1_4_E_150_BIT: u32 = 22;
+pub const RV_PLIC_IE1_4_E_151_BIT: u32 = 23;
+pub const RV_PLIC_IE1_4_E_152_BIT: u32 = 24;
+pub const RV_PLIC_IE1_4_E_153_BIT: u32 = 25;
+pub const RV_PLIC_IE1_4_E_154_BIT: u32 = 26;
+pub const RV_PLIC_IE1_4_E_155_BIT: u32 = 27;
+pub const RV_PLIC_IE1_4_E_156_BIT: u32 = 28;
+pub const RV_PLIC_IE1_4_E_157_BIT: u32 = 29;
+pub const RV_PLIC_IE1_4_E_158_BIT: u32 = 30;
+pub const RV_PLIC_IE1_4_E_159_BIT: u32 = 31;
+
+// Interrupt Enable for Target 1
+pub const RV_PLIC_IE1_5_REG_OFFSET: usize = 0x2114;
+pub const RV_PLIC_IE1_5_E_160_BIT: u32 = 0;
+pub const RV_PLIC_IE1_5_E_161_BIT: u32 = 1;
+pub const RV_PLIC_IE1_5_E_162_BIT: u32 = 2;
+pub const RV_PLIC_IE1_5_E_163_BIT: u32 = 3;
+pub const RV_PLIC_IE1_5_E_164_BIT: u32 = 4;
+pub const RV_PLIC_IE1_5_E_165_BIT: u32 = 5;
+pub const RV_PLIC_IE1_5_E_166_BIT: u32 = 6;
+pub const RV_PLIC_IE1_5_E_167_BIT: u32 = 7;
+pub const RV_PLIC_IE1_5_E_168_BIT: u32 = 8;
+pub const RV_PLIC_IE1_5_E_169_BIT: u32 = 9;
+pub const RV_PLIC_IE1_5_E_170_BIT: u32 = 10;
+pub const RV_PLIC_IE1_5_E_171_BIT: u32 = 11;
+pub const RV_PLIC_IE1_5_E_172_BIT: u32 = 12;
+pub const RV_PLIC_IE1_5_E_173_BIT: u32 = 13;
+pub const RV_PLIC_IE1_5_E_174_BIT: u32 = 14;
+pub const RV_PLIC_IE1_5_E_175_BIT: u32 = 15;
+pub const RV_PLIC_IE1_5_E_176_BIT: u32 = 16;
+pub const RV_PLIC_IE1_5_E_177_BIT: u32 = 17;
+pub const RV_PLIC_IE1_5_E_178_BIT: u32 = 18;
+pub const RV_PLIC_IE1_5_E_179_BIT: u32 = 19;
+pub const RV_PLIC_IE1_5_E_180_BIT: u32 = 20;
+pub const RV_PLIC_IE1_5_E_181_BIT: u32 = 21;
+pub const RV_PLIC_IE1_5_E_182_BIT: u32 = 22;
+pub const RV_PLIC_IE1_5_E_183_BIT: u32 = 23;
+pub const RV_PLIC_IE1_5_E_184_BIT: u32 = 24;
+pub const RV_PLIC_IE1_5_E_185_BIT: u32 = 25;
+pub const RV_PLIC_IE1_5_E_186_BIT: u32 = 26;
+pub const RV_PLIC_IE1_5_E_187_BIT: u32 = 27;
+pub const RV_PLIC_IE1_5_E_188_BIT: u32 = 28;
+pub const RV_PLIC_IE1_5_E_189_BIT: u32 = 29;
+pub const RV_PLIC_IE1_5_E_190_BIT: u32 = 30;
+pub const RV_PLIC_IE1_5_E_191_BIT: u32 = 31;
+
+// Interrupt Enable for Target 1
+pub const RV_PLIC_IE1_6_REG_OFFSET: usize = 0x2118;
+pub const RV_PLIC_IE1_6_E_192_BIT: u32 = 0;
+
+// Threshold of priority for Target 0
+pub const RV_PLIC_THRESHOLD0_REG_OFFSET: usize = 0x200000;
+pub const RV_PLIC_THRESHOLD0_THRESHOLD0_MASK: u32 = 0x3;
+pub const RV_PLIC_THRESHOLD0_THRESHOLD0_OFFSET: usize = 0;
+
+// Claim interrupt by read, complete interrupt by write for Target 0.
+pub const RV_PLIC_CC0_REG_OFFSET: usize = 0x200004;
+pub const RV_PLIC_CC0_CC0_MASK: u32 = 0xff;
+pub const RV_PLIC_CC0_CC0_OFFSET: usize = 0;
+
+// Threshold of priority for Target 1
+pub const RV_PLIC_THRESHOLD1_REG_OFFSET: usize = 0x201000;
+pub const RV_PLIC_THRESHOLD1_THRESHOLD1_MASK: u32 = 0x3;
+pub const RV_PLIC_THRESHOLD1_THRESHOLD1_OFFSET: usize = 0;
+
+// Claim interrupt by read, complete interrupt by write for Target 1.
+pub const RV_PLIC_CC1_REG_OFFSET: usize = 0x201004;
+pub const RV_PLIC_CC1_CC1_MASK: u32 = 0xff;
+pub const RV_PLIC_CC1_CC1_OFFSET: usize = 0;
+
+// msip for Hart 0.
+pub const RV_PLIC_MSIP0_REG_OFFSET: usize = 0x4000000;
+pub const RV_PLIC_MSIP0_MSIP0_BIT: u32 = 0;
+
+// msip for Hart 1.
+pub const RV_PLIC_MSIP1_REG_OFFSET: usize = 0x4000004;
+pub const RV_PLIC_MSIP1_MSIP1_BIT: u32 = 0;
+
+// Alert Test Register.
+pub const RV_PLIC_ALERT_TEST_REG_OFFSET: usize = 0x4004000;
+pub const RV_PLIC_ALERT_TEST_FATAL_FAULT_BIT: u32 = 0;
+
+// End generated register constants for RV_PLIC
\ No newline at end of file
diff --git a/hal/src/plic_hal.rs b/hal/src/plic_hal.rs
index 84abce7..f85c56c 100644
--- a/hal/src/plic_hal.rs
+++ b/hal/src/plic_hal.rs
@@ -1,6 +1,6 @@
 //! Platform Level Interrupt Control peripheral driver.
 
-use reg_constants::plic::*;
+use crate::plic_constants::*;
 use kernel::common::registers::{register_bitfields, register_structs, ReadOnly, ReadWrite};
 use kernel::common::StaticRef;
 
diff --git a/reg_constants/Cargo.toml b/reg_constants/Cargo.toml
deleted file mode 100644
index 9dae8d7..0000000
--- a/reg_constants/Cargo.toml
+++ /dev/null
@@ -1,6 +0,0 @@
-[package]
-name = "reg_constants"
-version = "0.1.0"
-edition = "2018"
-
-[dependencies]
diff --git a/reg_constants/build.rs b/reg_constants/build.rs
deleted file mode 100644
index f5c6c7e..0000000
--- a/reg_constants/build.rs
+++ /dev/null
@@ -1,27 +0,0 @@
-use std::env;
-use std::process::Command;
-
-fn main() {
-    let out_dir = env::var("OUT_DIR").unwrap();
-    let python = env::var("PYTHON").unwrap_or("python3".to_string());
-
-    let regtool =
-        env::var("MATCHA_REGTOOL").expect("missing environment variable 'MATCHA_REGTOOL'");
-    println!("cargo:rerun-if-env-changed=MATCHA_REGTOOL");
-    println!("cargo:rerun-if-changed={}", regtool);
-
-    let plic_hjson =
-        env::var("MATCHA_PLIC_HJSON").expect("missing environment variable 'MATCHA_PLIC_HJSON'");
-    println!("cargo:rerun-if-env-changed=MATCHA_PLIC_HJSON");
-    println!("cargo:rerun-if-changed={}", plic_hjson);
-
-    let mut cmd = Command::new("/usr/bin/env");
-    cmd.arg(python)
-        .arg(regtool)
-        .arg("-R")
-        .arg("-o")
-        .arg(format!("{}/plic.rs", out_dir))
-        .arg(plic_hjson);
-    println!("Running: {:?}", cmd);
-    assert!(cmd.status().unwrap().success());
-}
diff --git a/reg_constants/src/lib.rs b/reg_constants/src/lib.rs
deleted file mode 100644
index 7854058..0000000
--- a/reg_constants/src/lib.rs
+++ /dev/null
@@ -1,5 +0,0 @@
-#![no_std]
-
-pub mod plic {
-    include!(concat!(env!("OUT_DIR"), "/plic.rs"));
-}