diff --git a/app/.cargo/config.toml b/app/.cargo/config.toml
index 63e62c3..4db3c2d 100644
--- a/app/.cargo/config.toml
+++ b/app/.cargo/config.toml
@@ -1,9 +1,10 @@
 [build]
 target = "riscv32imc-unknown-none-elf"
 target-dir = "../../../out/matcha"
+# linker script flag "-C" "link-arg=-Tlayout_matcha.ld" is defined externally
+# to separate debug vs. release mode.
 rustflags = [
-    "-C", "relocation-model=static",
-    "-C", "link-arg=-Tlayout_matcha.ld",
+    "-C", "relocation-model=static"
 ]
 
 # this doesn't work in our version of cargo yet
diff --git a/app/layout_matcha_debug.ld b/app/layout_matcha_debug.ld
new file mode 100644
index 0000000..096b5a4
--- /dev/null
+++ b/app/layout_matcha_debug.ld
@@ -0,0 +1,18 @@
+/* Layout for the RISC-V 32 boards, used by the examples in this repository. */
+
+MEMORY {
+  /*
+   * The TBF header can change in size so use 0x40 combined with
+   * --protected-region-size with elf2tab to cover a header upto that
+   * size.
+   *
+   * Note that the SRAM address may need to be changed depending on
+   * the kernel binary, check for the actual address of APP_MEMORY!
+   */
+  FLASH (rx) : ORIGIN = 0x20800040, LENGTH = 0x800000 - 0x40
+  SRAM (rwx) : ORIGIN = 0x10800000, LENGTH = 0x800000
+}
+
+MPU_MIN_ALIGN = 1K;
+
+INCLUDE layout_generic.ld
diff --git a/platform/.cargo/config.toml b/platform/.cargo/config.toml
index d92c351..cadd9fd 100644
--- a/platform/.cargo/config.toml
+++ b/platform/.cargo/config.toml
@@ -1,8 +1,9 @@
 [build]
 target = "riscv32imc-unknown-none-elf"
 target-dir = "../../../out/matcha"
+# linker script flag "-C" "link-arg=-Tlayout.ld" is defined externally
+# to separate debug vs. release mode.
 rustflags = [
-    "-C", "link-arg=-Tlayout.ld",
     "-C", "linker=rust-lld",
     "-C", "linker-flavor=ld.lld",
     "-C", "relocation-model=dynamic-no-pic",
diff --git a/platform/layout_debug.ld b/platform/layout_debug.ld
new file mode 100644
index 0000000..4ef628e
--- /dev/null
+++ b/platform/layout_debug.ld
@@ -0,0 +1,25 @@
+MEMORY
+{
+  /*
+  For debugging, use 8M rom, 8M prog, 16M ram.
+  */
+  rom   (rx)  : ORIGIN = 0x20000000, LENGTH = 0x0800000
+  prog  (rx)  : ORIGIN = 0x20800000, LENGTH = 0x0800000
+  ram   (!rx) : ORIGIN = 0x10000000, LENGTH = 0x1000000
+}
+
+MPU_MIN_ALIGN = 1K;
+SECTIONS {
+    /*
+     * The flash header needs to match what the boot ROM for OpenTitan is
+     * expecting.  At the moment, it contains only the entry point, but it
+     * will eventually contain the signature -- and (hopefully?!) some
+     * versioning information to make it slightly easier to debug when the
+     * boot ROM and Tock are out of sync with respect to the definition...
+     */
+    .flash_header : {
+        LONG(_stext)
+    } > rom
+}
+
+INCLUDE kernel_layout.ld