hal/src/lib.rs

// Copyright 2022 Google LLC
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
//     https://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.

//! Anything in Matcha that needs to poke hardware registers directly will
//! go in this crate.

#![no_std]
#![feature(asm)]
#![feature(const_fn)]

pub mod dprintf_hal;
pub mod mailbox_hal;
pub mod plic_constants;
pub mod plic_hal;
pub mod rv_core_ibex_hal;
pub mod smc_ctrl_hal;
pub mod spi_host_hal;
pub mod timer_hal;
pub mod uart_hal;

// Software interrupt enable bits in MIE
pub const USIE_BIT: u32 = 1 << 0;
pub const SSIE_BIT: u32 = 1 << 1;
pub const MSIE_BIT: u32 = 1 << 3;

// External interrupt enable bits in MIE
pub const UEIE_BIT: u32 = 1 << 8;
pub const SEIE_BIT: u32 = 1 << 9;
pub const MEIE_BIT: u32 = 1 << 11;

// Global interrupt enable bits in MSTATUS
pub const UIE_BIT: u32 = 0b00000001;
pub const SIE_BIT: u32 = 0b00000010;
pub const MIE_BIT: u32 = 0b00001000;

pub unsafe fn set_mtvec(v: u32) {
    asm!("csrw mtvec, {}", in(reg) v);
}

pub unsafe fn set_mstatus_bits(mask: u32) {
    asm!("csrrs zero, mstatus, {}", in(reg) mask);
}

pub unsafe fn clear_mstatus_bits(mask: u32) {
    asm!("csrrc zero, mstatus, {}", in(reg) mask);
}

pub unsafe fn set_mie_bits(mask: u32) {
    asm!("csrrs zero, mie, {}", in(reg) mask);
}

pub unsafe fn clear_mie_bits(mask: u32) {
    asm!("csrrc zero, mie, {}", in(reg) mask);
}