| //! Anything in Matcha that needs to poke hardware registers directly will |
| //! go in this crate. |
| |
| #![no_std] |
| #![feature(asm)] |
| |
| pub mod debug_uart; |
| pub mod mailbox; |
| pub mod plic; |
| pub mod plic_constants; |
| |
| // Software interrupt enable bits in MIE |
| pub const USIE_BIT: u32 = 1 << 0; |
| pub const SSIE_BIT: u32 = 1 << 1; |
| pub const MSIE_BIT: u32 = 1 << 3; |
| |
| // External interrupt enable bits in MIE |
| pub const UEIE_BIT: u32 = 1 << 8; |
| pub const SEIE_BIT: u32 = 1 << 9; |
| pub const MEIE_BIT: u32 = 1 << 11; |
| |
| // Global interrupt enable bits in MSTATUS |
| pub const UIE_BIT: u32 = 0b00000001; |
| pub const SIE_BIT: u32 = 0b00000010; |
| pub const MIE_BIT: u32 = 0b00001000; |
| |
| pub unsafe fn set_mtvec(v: u32) { |
| asm!("csrw mtvec, {}", in(reg) v); |
| } |
| |
| pub unsafe fn set_mstatus_bits(mask: u32) { |
| asm!("csrrs zero, mstatus, {}", in(reg) mask); |
| } |
| |
| pub unsafe fn clear_mstatus_bits(mask: u32) { |
| asm!("csrrc zero, mstatus, {}", in(reg) mask); |
| } |
| |
| pub unsafe fn set_mie_bits(mask: u32) { |
| asm!("csrrs zero, mie, {}", in(reg) mask); |
| } |
| |
| pub unsafe fn clear_mie_bits(mask: u32) { |
| asm!("csrrc zero, mie, {}", in(reg) mask); |
| } |
