)]}'
{
  "commit": "336612e65fd9beab627b683d5e3795ba9bdab555",
  "tree": "f97afde5c910b210add5adc431aa8ad0554e4048",
  "parents": [
    "28bb4471fa07b5da0e4025430e7f2337af7e4cae"
  ],
  "author": {
    "name": "Cindy Liu",
    "email": "hcindyl@google.com",
    "time": "Sat Jun 17 14:32:16 2023 -0700"
  },
  "committer": {
    "name": "Cindy Liu",
    "email": "hcindyl@google.com",
    "time": "Tue Jun 20 14:12:05 2023 -0700"
  },
  "message": "Add Kelvin ISA doc\n\nMigrated from the experimental doc with clean up. Some notable fixes:\n\n* Add vector register configuration section\n* `getvl` example to align with Kelvin\u0027s 256 SIMD\n* `cache.x` is refined to core level `flush` ops\n* Fix bitfield assignment and explanation for `xlog`\n* Remove unsupported prefetch\n* Add `vdiv` and `vrem` based on instrinsic header and ISS\n  implementation\n* Adjust the header level of each of the subsections\n\nChange-Id: I34e27624a317bf5a896492083331c664b20c03c8\n",
  "tree_diff": [
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "97b8cdcd80141b07a84a11d5d254814d9027039c",
      "new_mode": 33188,
      "new_path": "docs/kelvin_isa.md"
    }
  ]
}