| commit | c42bc05c4b11d5d0264a98f90907aa650fab4a52 | [log] [tgz] |
|---|---|---|
| author | Cindy Liu <hcindyl@google.com> | Wed Nov 15 11:10:42 2023 -0800 |
| committer | Cindy Liu <hcindyl@google.com> | Wed Nov 15 12:57:10 2023 -0800 |
| tree | 589a6b294ed6ad49ba813c16191c0dcf5864d52b | |
| parent | 6664a052550d6e7b84a222a5b9150dfbe37f38ac [diff] |
Add uncached memory access support to scalar store PiperOrigin-RevId: 582740507
This project contains the instruction simulator of Kelvin ML core based on MPACT-Sim and MPACT-RiscV. The simulator supports RISC-V 32im configuration + Kelvin-specific SIMD instructions. Please review ISA Spec for more detail
sim Simulator implementations | ˪ proto Trace dump protobuf definition. | ˪ renode Renode(https://github.com/renode/renode) integration interface | ˪ test Simulated instruction / Framework function unit tests
To build all targets, run
bazel build //...
Specifically, the simulator standalone binary can be built with
bazel build //sim:kelvin_sim