format Inst32Format[32] {
  fields:
    unsigned bits[25];
    unsigned opcode[7];
};

// Risc-V R-Type format.
format RType[32] : Inst32Format {
  fields:
    unsigned func7[7];
    unsigned rs2[5];
    unsigned rs1[5];
    unsigned func3[3];
    unsigned rd[5];
    unsigned opcode[7];
  overlays:
    unsigned r_uimm5[5] = rs2;
};

// Risc-V I-Type format.
format IType[32] : Inst32Format {
  fields:
    signed imm12[12];
    unsigned rs1[5];
    unsigned func3[3];
    unsigned rd[5];
    unsigned opcode[7];
  overlays:
    unsigned u_imm12[12] = imm12;
    unsigned i_uimm5[5] = rs1;
};

// Risc-V S-Type format.
format SType[32] : Inst32Format {
  fields:
    unsigned imm7[7];
    unsigned rs2[5];
    unsigned rs1[5];
    unsigned func3[3];
    unsigned imm5[5];
    unsigned opcode[7];
  overlays:
    signed s_imm[12] = imm7, imm5;
};

// Risc-V B-Type format.
format BType[32] : Inst32Format {
  fields:
    unsigned imm7[7];
    unsigned rs2[5];
    unsigned rs1[5];
    unsigned func3[3];
    unsigned imm5[5];
    unsigned opcode[7];
  overlays:
    signed b_imm[13] = imm7[6], imm5[0], imm7[5..0], imm5[4..1], 0b0;
};

// Risc-V U-Type format.
format UType[32] : Inst32Format {
  fields:
    unsigned imm20[20];
    unsigned rd[5];
    unsigned opcode[7];
  overlays:
    unsigned u_imm[32] = imm20, 0b0000'0000'0000;
};

// Risc-V J-Type format.
format JType[32] : Inst32Format {
  fields:
    unsigned imm20[20];
    unsigned rd[5];
    unsigned opcode[7];
  overlays:
    signed j_imm[21] = imm20[19, 7..0, 8, 18..9], 0b0;
};

// Risc-V Fence format.
format Fence[32] : Inst32Format {
  fields:
    unsigned fm[4];
    unsigned pred[4];
    unsigned succ[4];
    unsigned rs1[5];
    unsigned func3[3];
    unsigned rd[5];
    unsigned opcode[7];
};

// Kelvin system instruction format (cache, getvl).
format KelvinSystemType[32] : Inst32Format {
  fields:
    unsigned func2[4];
    unsigned m[1];
    unsigned mode[2];
    unsigned rs2[5];
    unsigned rs1[5];
    unsigned func1[3];
    unsigned rd[5];
    unsigned opcode[7];
};

// Kelvin 2 args Vector format.
format KelvinV2ArgsType[32] {
  fields:
    unsigned func2[6];
    unsigned vs2[6];
    unsigned vs1[6];
    unsigned sz[2]; // .b==0b00, .h==0b01, .w==0b10
    unsigned vd[6];
    unsigned m[1];
    unsigned func1[3];
    unsigned form[2]; // .vv==0b00, .vx==0b10, .xx==0b11
  overlays:  // For accumulation register support.
    unsigned vs1_low3[3] = vs1[2..0];
    unsigned vs1_low2[2] = vs1[1..0];
    unsigned vd_low2[2] = vd[1..0];
};

// Kelvin 3 args vector format.
format KelvinV3ArgsType[32] {
  fields:
    unsigned vs3[6];
    unsigned vs2[6];
    unsigned vs1[6];
    unsigned func3_hi[2];
    unsigned vd[6];
    unsigned m[1];
    unsigned func3_lo[2];
    unsigned form[3];  // .vvv=0b001, .vxv=0b101.
  overlays:
    unsigned vs1_low3[3] = vs1[2..0];
    unsigned vs3_low3[3] = vs3[2..0];
};