| commit | 6664a052550d6e7b84a222a5b9150dfbe37f38ac | [log] [tgz] |
|---|---|---|
| author | Cindy Liu <hcindyl@google.com> | Fri Oct 27 08:16:30 2023 -0700 |
| committer | Cindy Liu <hcindyl@google.com> | Fri Oct 27 10:30:33 2023 -0700 |
| tree | 52101d7e9b67451d5d9c9a9248bd641b884ca0d7 | |
| parent | 03c7e2c4dbbe39662629159c15f7bafccd35a445 [diff] |
Fix `vstq` address offset error PiperOrigin-RevId: 577205259
This project contains the instruction simulator of Kelvin ML core based on MPACT-Sim and MPACT-RiscV. The simulator supports RISC-V 32im configuration + Kelvin-specific SIMD instructions. Please review ISA Spec for more detail
sim Simulator implementations | ˪ proto Trace dump protobuf definition. | ˪ renode Renode(https://github.com/renode/renode) integration interface | ˪ test Simulated instruction / Framework function unit tests
To build all targets, run
bazel build //...
Specifically, the simulator standalone binary can be built with
bazel build //sim:kelvin_sim