Add `reg info` and `vreg info` debug commands
Add custom commands to print all the available scalar and vector register content in the interactive mode.
PiperOrigin-RevId: 560111860
diff --git a/WORKSPACE b/WORKSPACE
index 75d2e3f..00af9e3 100644
--- a/WORKSPACE
+++ b/WORKSPACE
@@ -6,17 +6,17 @@
# MPACT-RiscV repo
http_archive(
name = "com_google_mpact-riscv",
- sha256 = "244236ecf63f812eedf4e1c80e79276374d4c8a9222860220706522edf093fc8",
- strip_prefix = "mpact-riscv-8b0c6b7fa4f48d6dba99c1a4abba3bb548577cad",
- url = "https://github.com/google/mpact-riscv/archive/8b0c6b7fa4f48d6dba99c1a4abba3bb548577cad.tar.gz",
+ sha256 = "9b617e364fb64b49f2ddd83c9eb0c012d3afee1569ad85262e0ccaf8a29ae760",
+ strip_prefix = "mpact-riscv-7b5ba3433b2c39752ca9a35d1b1ce48a7fec8722",
+ url = "https://github.com/google/mpact-riscv/archive/7b5ba3433b2c39752ca9a35d1b1ce48a7fec8722.tar.gz",
)
# MPACT-Sim repo
http_archive(
name = "com_google_mpact-sim",
- sha256 = "8b35b5f172f241fd207f5f54d81aacab1617dea16607b36e3417ef47f2366afc",
- strip_prefix = "mpact-sim-c4b68d7bdef36b9eb2e85f8dc22ccc4eb27ba4c5",
- url = "https://github.com/google/mpact-sim/archive/c4b68d7bdef36b9eb2e85f8dc22ccc4eb27ba4c5.tar.gz",
+ sha256 = "1f0e6ea27b0487a5d997f85efaebdf60a1f1dbb478c30b25d3c6b41e9d4b4028",
+ strip_prefix = "mpact-sim-e1b7b0adeb53875908995674a8555b68c4821903",
+ url = "https://github.com/google/mpact-sim/archive/e1b7b0adeb53875908995674a8555b68c4821903.tar.gz",
)
load("@com_google_mpact-sim//:repos.bzl", "mpact_sim_repos")
diff --git a/sim/BUILD b/sim/BUILD
index 8f3bb8e..b84f1c3 100644
--- a/sim/BUILD
+++ b/sim/BUILD
@@ -162,12 +162,17 @@
"//sim/test:testfiles/rv32soft_fp.elf",
],
deps = [
+ ":kelvin_state",
":kelvin_top",
"@com_google_absl//absl/flags:flag",
"@com_google_absl//absl/flags:parse",
"@com_google_absl//absl/flags:usage",
"@com_google_absl//absl/log",
+ "@com_google_absl//absl/strings",
+ "@com_google_absl//absl/strings:str_format",
"@com_google_mpact-riscv//riscv:debug_command_shell",
+ "@com_google_mpact-riscv//riscv:riscv_state",
"@com_google_mpact-sim//mpact/sim/util/program_loader:elf_loader",
+ "@com_googlesource_code_re2//:re2",
],
)
diff --git a/sim/kelvin_sim.cc b/sim/kelvin_sim.cc
index b60a923..2e55304 100644
--- a/sim/kelvin_sim.cc
+++ b/sim/kelvin_sim.cc
@@ -1,16 +1,24 @@
#include <signal.h>
+#include <cstdint>
+#include <cstdlib>
#include <iostream>
#include <string>
#include <vector>
+#include "sim/kelvin_state.h"
#include "sim/kelvin_top.h"
#include "absl/flags/flag.h"
#include "absl/flags/parse.h"
#include "absl/flags/usage.h"
#include "absl/log/log.h"
+#include "absl/strings/str_cat.h"
+#include "absl/strings/str_format.h"
+#include "absl/strings/string_view.h"
#include "riscv/debug_command_shell.h"
+#include "riscv/riscv_register_aliases.h"
#include "mpact/sim/util/program_loader/elf_program_loader.h"
+#include "re2/re2.h"
// Flags for specifying interactive mode.
ABSL_FLAG(bool, i, false, "Interactive mode");
@@ -29,6 +37,67 @@
}
}
+// Custom debug command to print all the scalar register values.
+static bool PrintRegisters(
+ absl::string_view input,
+ const mpact::sim::riscv::DebugCommandShell::CoreAccess &core_access,
+ std::string &output) {
+ LazyRE2 xreg_info_re{R"(\s*reg\s+info\s*)"};
+ if (!RE2::FullMatch(input, *xreg_info_re)) {
+ return false;
+ }
+ std::string output_str;
+ for (int i = 0; i < 32; ++i) {
+ std::string reg_name = absl::StrCat("x", i);
+ auto result = core_access.debug_interface->ReadRegister(reg_name);
+ if (!result.ok()) {
+ // Skip the register if error occurs.
+ continue;
+ }
+ output_str +=
+ absl::StrCat(mpact::sim::riscv::kXRegisterAliases[i], "\t = [",
+ absl::Hex(result.value(), absl::kZeroPad8), "]\n");
+ }
+ output = output_str;
+ return true;
+}
+
+// Custom debug command to print all the assigned vector register values.
+static bool PrintVectorRegisters(
+ absl::string_view input,
+ const mpact::sim::riscv::DebugCommandShell::CoreAccess &core_access,
+ std::string &output) {
+ LazyRE2 vreg_info_re{R"(\s*vreg\s+info\s*)"};
+ if (!RE2::FullMatch(input, *vreg_info_re)) {
+ return false;
+ }
+ std::string output_str;
+ for (int i = 0; i < kelvin::sim::kNumVregs; ++i) {
+ std::string reg_name = absl::StrCat("v", i);
+ auto result = core_access.debug_interface->GetRegisterDataBuffer(reg_name);
+ if (!result.ok()) {
+ // Skip the register if error occurs.
+ continue;
+ }
+ auto *db = result.value();
+ if (db == nullptr) {
+ // Skip the register if the data buffer is not available.
+ continue;
+ }
+ std::string data_str;
+ std::string sep;
+ for (int j = 0; j < kelvin::sim::kVectorLengthInBits / 32; ++j) {
+ auto value = db->Get<uint32_t>(j);
+ data_str += sep + absl::StrFormat("%08x", value);
+ sep = ":";
+ }
+ output_str += absl::StrCat("v", i, "\t = [", data_str, "]\n");
+ }
+
+ output = output_str;
+ return true;
+}
+
int main(int argc, char **argv) {
absl::SetProgramUsageMessage("Kelvin MPACT-Sim based CLI tool");
auto out_args = absl::ParseCommandLine(argc, argv);
@@ -71,6 +140,13 @@
if (interactive) {
mpact::sim::riscv::DebugCommandShell cmd_shell(
{{&kelvin_top, &elf_loader}});
+ // Add custom commands to interactive debug command shell.
+ cmd_shell.AddCommand(
+ " reg info - print all scalar regs",
+ PrintRegisters);
+ cmd_shell.AddCommand(
+ " vreg info - print assigned vector regs",
+ PrintVectorRegisters);
cmd_shell.Run(std::cin, std::cout);
std::cout << "Total cycles: " << kelvin_top.GetCycleCount() << std::endl;
} else {
diff --git a/sim/kelvin_state.h b/sim/kelvin_state.h
index f7571dd..52d271b 100644
--- a/sim/kelvin_state.h
+++ b/sim/kelvin_state.h
@@ -20,6 +20,8 @@
// https://spacebeaker.googlesource.com/shodan/hw/kelvin/+/refs/heads/master/hdl/chisel/src/kelvin/Parameters.scala#13.
inline constexpr uint32_t kVectorLengthInBits = 256;
+inline constexpr int kNumVregs = 64;
+
constexpr uint64_t kKelvinMaxMemoryAddress = 0x3f'ffffULL; // 4MB
template <typename T>
