commit 0896769f7f57c7bfabcb6a58b8a2c3ce60d28768
author Cindy Liu <hcindyl@google.com> Thu Aug 24 14:54:41 2023 -0700
committer Cindy Liu <hcindyl@google.com> Fri Aug 25 09:53:27 2023 -0700
tree 4e8e70ffdd2ab7ae9aa13992e32a1b729b8ab427
parent 9894f2b1b9b979201401fa26c06e946e64535b35

No public description

PiperOrigin-RevId: 559878410

sim/kelvin_memory.isa

diff --git a/sim/kelvin_memory.isa b/sim/kelvin_memory.isa
index bc83d3e..7c0c9c7 100644
--- a/sim/kelvin_memory.isa
+++ b/sim/kelvin_memory.isa
@@ -503,7 +503,7 @@
     // vcget
     vcget{: : vd},
       disasm: "vcget", "%vd",
-      semfunc: "absl::bind_front(&KelvinVcGet)";
+      semfunc: "&KelvinVcGet";
 
     // acset/actr/adwinit
     acset{: vs1 : vd},

sim/kelvin_state.cc

diff --git a/sim/kelvin_state.cc b/sim/kelvin_state.cc
index c1d4c8b..7e800cc 100644
--- a/sim/kelvin_state.cc
+++ b/sim/kelvin_state.cc
@@ -21,7 +21,7 @@
     : mpact::sim::riscv::RiscVState(id, xlen, memory, atomic_memory) {
   set_vector_register_width(kVectorRegisterWidth);
   for (int i = 0; i < acc_register_.size(); ++i) {
-    acc_register_.at(i).fill(0);
+    acc_register_[i].fill(0);
   }
 }
 

sim/kelvin_state.h

diff --git a/sim/kelvin_state.h b/sim/kelvin_state.h
index b323b01..f7571dd 100644
--- a/sim/kelvin_state.h
+++ b/sim/kelvin_state.h
@@ -47,7 +47,7 @@
   void set_vector_length(uint32_t length) { vector_length_ = length; }
   uint32_t vector_length() const { return vector_length_; }
 
-  AccArrayType *acc_vec(int index) { return &(acc_register_.at(index)); }
+  AccArrayType *acc_vec(int index) { return &(acc_register_[index]); }
   AccArrayTemplate<AccArrayType> acc_register() const { return acc_register_; }
 
   void SetLogArgs(std::any data) { log_args_.emplace_back(std::move(data)); }

sim/kelvin_vector_memory_instructions.cc

diff --git a/sim/kelvin_vector_memory_instructions.cc b/sim/kelvin_vector_memory_instructions.cc
index 67c0966..fd1f099 100644
--- a/sim/kelvin_vector_memory_instructions.cc
+++ b/sim/kelvin_vector_memory_instructions.cc
@@ -336,7 +336,7 @@
     absl::Span<uint32_t> dest_span = dest_db->Get<uint32_t>();
     auto *acc_vec = state->acc_vec(op_index);
     for (int i = 0; i < dest_span.size(); ++i) {
-      dest_span[i] = acc_vec->data()[i];
+      dest_span[i] = (*acc_vec)[i];
     }
     acc_vec->fill(0);
     dest_db->Submit();
@@ -357,10 +357,10 @@
     for (int i = 0; i < source_span.size(); ++i) {
       if (is_transpose) {
         auto *acc_vec = state->acc_vec(i);
-        acc_vec->at(op_index) = source_span[i];
+        (*acc_vec)[op_index] = source_span[i];
       } else {
         auto *acc_vec = state->acc_vec(op_index);
-        acc_vec->at(i) = source_span[i];
+        (*acc_vec)[i] = source_span[i];
       }
     }
   }

sim/test/kelvin_vector_memory_instructions_test.cc

diff --git a/sim/test/kelvin_vector_memory_instructions_test.cc b/sim/test/kelvin_vector_memory_instructions_test.cc
index 82d986c..e11fe0e 100644
--- a/sim/test/kelvin_vector_memory_instructions_test.cc
+++ b/sim/test/kelvin_vector_memory_instructions_test.cc
@@ -540,9 +540,8 @@
       auto vd_name = absl::StrCat("v", kVd + i);
       auto vs_name = absl::StrCat("v", kVs + i);
       SetVectorRegisterValues<uint32_t>(
-          {{vd_name, vd_span.subspan(kVLenInWord * i, kVLenInWord)}});
-      SetVectorRegisterValues<uint32_t>(
-          {{vs_name, vd_span.subspan(kVLenInWord * i, kVLenInWord)}});
+          {{vd_name, vd_span.subspan(kVLenInWord * i, kVLenInWord)},
+           {vs_name, vd_span.subspan(kVLenInWord * i, kVLenInWord)}});
     }
     auto instruction = CreateInstruction();
     AppendVectorRegisterOperands(instruction.get(), kVLenInWord,
@@ -560,12 +559,12 @@
            element_index++) {
         if (is_transpose) {
           auto *acc_vec = state_->acc_vec(element_index);
-          EXPECT_EQ(vreg_span[element_index], acc_vec->at(i))
+          EXPECT_EQ(vreg_span[element_index], (*acc_vec)[i])
               << absl::StrCat("vreg[", vreg_num, "][", element_index,
                               "] != acc[", element_index, "][", i, "]");
         } else {
           auto *acc_vec = state_->acc_vec(i);
-          EXPECT_EQ(vreg_span[element_index], acc_vec->at(element_index))
+          EXPECT_EQ(vreg_span[element_index], (*acc_vec)[element_index])
               << absl::StrCat("vreg[", vreg_num, "][", element_index,
                               "] != acc[", i, "][", element_index, "]");
         }