)]}' { "log": [ { "commit": "98c5d6b84567edcc0c945df6b7c20e120d3438e2", "tree": "6d4e51c8e6b731767d8fff39c45836d12e4900fc", "parents": [ "7aff4fde26e5fadfa017e4af4b684e08fd8f5c1c" ], "author": { "name": "Lun Dong", "email": "lundong@google.com", "time": "Tue Sep 16 05:58:46 2025 +0000" }, "committer": { "name": "Lun Dong", "email": "lundong@google.com", "time": "Tue Sep 16 11:24:04 2025 -0700" }, "message": "Fix renode error\n\nChange-Id: I692934aef3d3e325a30d268651c2eb8e0017d597\n" }, { "commit": "7aff4fde26e5fadfa017e4af4b684e08fd8f5c1c", "tree": "75a01a3bdf4de227f1b239748ed869ec19509890", "parents": [ "bb9fc2a8cbc7f3a4cb2d755db49afc8ac2e46cce" ], "author": { "name": "Julian Mullings-Black", "email": "julianmb@google.com", "time": "Tue Mar 11 19:28:18 2025 +0000" }, "committer": { "name": "Julian Mullings-Black", "email": "julianmb@google.com", "time": "Tue Mar 11 19:31:29 2025 +0000" }, "message": "Track renode interface change in MpactCPU\n\nIMultibyteWritePeripheral ReadBytes/WriteBytes method signature changed.\nThe context paramater is now IPeripheral.\n\nChange-Id: Ieec18c570745ee7c828470c75e12c22eb0ea8bad\n" }, { "commit": "bb9fc2a8cbc7f3a4cb2d755db49afc8ac2e46cce", "tree": "13e5273b710f8e99635b5b5a6cb881111c9327c9", "parents": [ "66453e20c2aba1ac74b91042924d36a12cb5b2b8" ], "author": { "name": "Julian Mullings-Black", "email": "julianmb@google.com", "time": "Wed Feb 12 23:35:45 2025 +0000" }, "committer": { "name": "Julian Mullings-Black", "email": "julianmb@google.com", "time": "Fri Feb 14 21:13:02 2025 +0000" }, "message": "Fix renode/C# delegate types in (Kelvin|Mpact)CPU\n\nThe old delegate type in Renode that we depended on arent there since\nRenode is doing dynamic type generation now.\n\nChange-Id: Ifb504841f2347576eed4d5473cef0f4dec869947\n" }, { "commit": "66453e20c2aba1ac74b91042924d36a12cb5b2b8", "tree": "8113c98dc817021cfba17c5855f03509ceab41a1", "parents": [ "3c82ff77eebbd0564a40b151c36e99081b9a4f9d" ], "author": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Thu Jan 23 15:26:05 2025 -0800" }, "committer": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Fri Jan 24 09:45:48 2025 -0800" }, "message": "sencha: bump mpact CoreVersion to 1.0\n\nBump the default CoreVersion to 1.0 so the cjal return cap stored in\nregisters other than cra is sealed. This is required to support the\noutliner pass in the latest compiler. It is compatible with older\ntoolchains where the outliner pass is disabled.\n\nChange-Id: I189f4d83754b3693c8fe2c569e7f6f8e88067802\n" }, { "commit": "3c82ff77eebbd0564a40b151c36e99081b9a4f9d", "tree": "628482c36f3fadba3e54a3e59bbdc5002eccd145", "parents": [ "2d3fd85b18ea52bdada77d607ce0c7715c970e10" ], "author": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Thu Dec 19 11:11:09 2024 -0800" }, "committer": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Thu Dec 19 11:13:53 2024 -0800" }, "message": "sencha: add OTTF-specific startup\n\nOTTF expects the SMC frmware is side-loaded; add sencha-ottf.resc to\ndo that.\n\nChange-Id: Ieeb354aa40c5fb5f5a76d5d5b9f239623f4e72e3\n" }, { "commit": "2d3fd85b18ea52bdada77d607ce0c7715c970e10", "tree": "dd51e9e8f304c8cb0a5215cf89729229e4f540f3", "parents": [ "98ed2a8a38ea24c09e6be25eab7a4270c0e343cd" ], "author": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Tue Dec 17 09:20:03 2024 -0800" }, "committer": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Tue Dec 17 09:20:03 2024 -0800" }, "message": "sencha/bancha: track upstream changes for CHERIoT core version\n\nChange-Id: I49d2e625fbe35f57319b7b2231485019ad0555cb\n" }, { "commit": "98ed2a8a38ea24c09e6be25eab7a4270c0e343cd", "tree": "847fd488dfd2e48ee0faf562aec60d63c457228a", "parents": [ "630f243918ce5bbf980a42266baf347b9c411f68" ], "author": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Tue Dec 10 14:28:06 2024 -0800" }, "committer": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Wed Dec 11 11:38:03 2024 -0800" }, "message": "sencha/shodan: allow boot_rom pathname to be overridden\n\nBypass-Presubmit-Reason: missing bazelversion\n\nChange-Id: I7ccf2e15fc80f22715e5ef86fde15d8159152d56\n" }, { "commit": "630f243918ce5bbf980a42266baf347b9c411f68", "tree": "aec9dab4b4f78650f4afe119feb73bef731a7f1f", "parents": [ "0669b82c744e5d691b18ca612022fb1aad87c600" ], "author": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Mon Dec 09 10:21:58 2024 -0800" }, "committer": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Mon Dec 09 18:34:17 2024 +0000" }, "message": "sencha: correct CHERIoT software revoker setup\n\nWe (currently) do memory revocation in software on the SMC. Shrinking\nSRAM to match the hardware resulted in the revokers\u0027s shadow bitmap\noverlapping the heap. Grow memory owned by the CHERIoT cpu so we can\nmove the bitmap past the end of SRAM (this happens in the json board\ndescription). While here also disable the hardware revocation support.\n\nBypass-Presubmit-Reason: no test coverage\n\nChange-Id: I12452283dee91e48d1ceae815c4ac318b2b377c3\n" }, { "commit": "0669b82c744e5d691b18ca612022fb1aad87c600", "tree": "871ef7b726451fc4c9b085e01aa1da5a13f0e15c", "parents": [ "4492b44c9775b39056ec079975fc906bd17b493b" ], "author": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Tue Dec 03 11:29:20 2024 -0800" }, "committer": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Tue Dec 03 11:29:20 2024 -0800" }, "message": "bancha: load firmware symbols so mpact catches tohost writes\n\nChange-Id: Iba5b37d76715bba107c5d1340cf69d10a0dda63d\n" }, { "commit": "4492b44c9775b39056ec079975fc906bd17b493b", "tree": "ae9a1a2e96adb4e086cf3f18ca6c8ca0799209a3", "parents": [ "9a449aaf84bbf8d8314dbc5f7126bdab4d1af72e" ], "author": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Wed Oct 16 11:56:14 2024 -0700" }, "committer": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Wed Oct 16 11:56:14 2024 -0700" }, "message": "sencha: track hardware memory map\n\nTrack the hardware memory map for the SMC. This requires equivalent\nchanges in the cheriot-rtos board description.\n\nChange-Id: Id137211fa0b89c4140bd4cfefe0809f5e63bfc06\n" }, { "commit": "9a449aaf84bbf8d8314dbc5f7126bdab4d1af72e", "tree": "64c2e88a21b12ee7d31b68a700f463cb9c7e25f5", "parents": [ "e55803e5b907fd257c16c515ade65cf72328b024" ], "author": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Wed Oct 16 11:55:05 2024 -0700" }, "committer": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Wed Oct 16 11:55:05 2024 -0700" }, "message": "sencha: track location of boot_rom.elf\n\nBuild changes moved the artifact; update the expected pathname.\n\nChange-Id: If27ccfcee09d129b042e2e6ec10981d00ac92403\n" }, { "commit": "e55803e5b907fd257c16c515ade65cf72328b024", "tree": "529efd8e67bd3107a37342d3a17f33d4f5d8a2f1", "parents": [ "0b4aaa3774c20ef3120a03d62ea5f913684b58dd" ], "author": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Tue Oct 08 14:28:24 2024 -0700" }, "committer": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Tue Oct 08 22:35:14 2024 +0000" }, "message": "sencha/bancha: use OpenTitan uart\n\nWith the addition of Sonata board support the OpenTitan uart is\nsupported so switch sencha (uart5) + bancha (uart0).\n\nWhile here cleanup bancha a bit.\n\nBypass-Presubmit-Reason: only relevant flow passes (shodan flows are broken by futures crate version issue)\n\nChange-Id: I82e4e3e34e80d32d465a3dfd243544a404e4731e\n" }, { "commit": "0b4aaa3774c20ef3120a03d62ea5f913684b58dd", "tree": "a97e36da9dc2af9fa66b15fd55a94366b88906a1", "parents": [ "dc85fb9e98b6a01c2cf6c19e5892655fa38eae13" ], "author": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Wed Oct 02 14:24:38 2024 -0700" }, "committer": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Thu Oct 03 01:24:10 2024 +0000" }, "message": "bancha: document I$/D$ configuration\n\nChange-Id: Ic076543e13d7ead736fbd39bdb6723de128e6117\n" }, { "commit": "dc85fb9e98b6a01c2cf6c19e5892655fa38eae13", "tree": "6850b925122e23c6908f0435861af1ed8f0b555e", "parents": [ "7378f71aaea3325acd6e597bfca815a563b7963f" ], "author": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Wed Oct 02 14:22:47 2024 -0700" }, "committer": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Thu Oct 03 01:23:58 2024 +0000" }, "message": "sencha/bancha: sync with upstream for ICache/DCache support\n\nBypass-Presubmit-Reason:tested as part of chain\n\nChange-Id: I60f0a75c380316a7506614cfc8cfce9ef9f29dde\n" }, { "commit": "7378f71aaea3325acd6e597bfca815a563b7963f", "tree": "97c53ff716bdf5783e635b63a19ab99764a14ba1", "parents": [ "60d51cd0e622a7ea0b8fd9dc0e00acbe85f531f1" ], "author": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Wed Oct 02 13:28:31 2024 -0700" }, "committer": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Thu Oct 03 01:22:54 2024 +0000" }, "message": "bancha: do not load eflash\n\nWe cannot (currently) run from eflash so there\u0027s no reason to load\nan image.\n\nBypass-Presubmit-Reason:tested as part of chain\n\nChange-Id: I4ce067167ebe3ed465469f086a155c1c13e54efa\n" }, { "commit": "60d51cd0e622a7ea0b8fd9dc0e00acbe85f531f1", "tree": "2ea0be3462709be188156813920676a47dfc6deb", "parents": [ "57bcf2a8930906130029d72803dfe267b802d4aa" ], "author": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Mon Sep 09 16:29:50 2024 -0700" }, "committer": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Wed Sep 18 21:11:19 2024 +0000" }, "message": "bancha: correct ROM size to be 48K\n\nBypass-Presubmit-Reason: tested as part of topic.\n\nChange-Id: I603ec0b2887b5c940bb0e45ac62e7ae95d4655ed\n" }, { "commit": "57bcf2a8930906130029d72803dfe267b802d4aa", "tree": "27151695bec925a9c68f17b52e37e7c61106a3d3", "parents": [ "d9196f674fb4dc88c7ba15d499777a8db2d4c4e2" ], "author": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Tue Sep 10 11:43:50 2024 -0700" }, "committer": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Tue Sep 10 11:51:13 2024 -0700" }, "message": "sencha/bancha: fix gdb server support to track upstream changes\n\nNote this only enables the renode service to run; gdb functionality is\nstill missing for CHERIoT.\n\nChange-Id: I17e4183a62d7c78afc1a7c931bcde924b134f6ee\n" }, { "commit": "d9196f674fb4dc88c7ba15d499777a8db2d4c4e2", "tree": "8928dbdcd60b46697a3bbb5c2ba003646c32e40c", "parents": [ "d3586a63dfc7b3cfb1a1407f8abf0d04dd3f1206" ], "author": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Sat Aug 31 16:38:18 2024 -0700" }, "committer": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Tue Sep 03 14:17:03 2024 -0700" }, "message": "cheriot: use the mpact built-in clint\n\nHave mpact emulate the clint. When renode handles this there is\nsignificant latency in updating peripheral state. This is especially\nnoticeable when firmware reads from the hardware.\n\nChange-Id: Ic82578bae6d00bb504596053f5916268a747fb83\n" }, { "commit": "d3586a63dfc7b3cfb1a1407f8abf0d04dd3f1206", "tree": "a63f58159f78a51d97c2e2339289c9ac85e00009", "parents": [ "c86c52b65b4fdbae828d3fb5cae60afcffae59ad" ], "author": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Mon Jun 03 15:54:49 2024 -0700" }, "committer": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Tue Aug 27 23:24:20 2024 +0000" }, "message": "Initial bancha support.\n\nBancha is reduction of sencha by combining the SEC+SMC and pruning some\nperipherals. Kelvin remains unchanged.\n\nBypass-Presubmit-Reason: verified as part of topic\n\nChange-Id: I69cc78b502033eba3b02d69f19606b6533d4b7a6\n" }, { "commit": "c86c52b65b4fdbae828d3fb5cae60afcffae59ad", "tree": "b4eb8aa6e5f9649e3959ac252963247abadd1291", "parents": [ "eb7bbdd50655e02bac18d500f8eba6ac61a2ece8" ], "author": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Thu Aug 22 17:17:02 2024 -0700" }, "committer": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Thu Aug 22 17:17:02 2024 -0700" }, "message": "sencha: disable starting a gdb server on the cheriot cpu\n\nThis fails but even when it worked the gdb service was not usable;\nso just comment it out until we can resolve why it\u0027s broken.\n\nChange-Id: I59f9b9a961f0b4be3d8bbf81672699546cc4663b\n" }, { "commit": "eb7bbdd50655e02bac18d500f8eba6ac61a2ece8", "tree": "cdf108a2633e8267f8bd4df99609544ad604612a", "parents": [ "e2e1d51bcefa0a6217774ce464def6a19fb2693b" ], "author": { "name": "Michael Hoang", "email": "hoangm@google.com", "time": "Mon Aug 19 20:11:50 2024 +0000" }, "committer": { "name": "Michael Hoang", "email": "hoangm@google.com", "time": "Thu Aug 22 22:49:04 2024 +0000" }, "message": "Track mpact changes\n\nChange-Id: If4599e8c67a86e289c4c7d7608de7665ee9967c9\n" }, { "commit": "e2e1d51bcefa0a6217774ce464def6a19fb2693b", "tree": "54f396274616653dbc3cfe508adc154749dba578", "parents": [ "a3c7576c6a5c9d75e026357aaf29736733bae064" ], "author": { "name": "Cindy Liu", "email": "hcindyl@google.com", "time": "Wed Aug 21 23:29:39 2024 -0700" }, "committer": { "name": "Cindy Liu", "email": "hcindyl@google.com", "time": "Thu Aug 22 07:47:17 2024 +0000" }, "message": "Fix KelvinCPU Set/Get Register API\n\nMatch upstream API change https://github.com/renode/renode-infrastructure/commit/c8ed56a\n\nBypass-Presubmit-Reason: Sencha CI needs extra fix\n\nChange-Id: Iae8ac63abf63ad1ab309df921f1a3533858739ed\n" }, { "commit": "a3c7576c6a5c9d75e026357aaf29736733bae064", "tree": "e29dc44c2afc777dade1ec07fee5cc5a83692fb4", "parents": [ "779ad95b96f6f95eb6355eb22e7b7597cec0f68f" ], "author": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Fri Aug 16 09:23:42 2024 -0700" }, "committer": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Fri Aug 16 21:03:36 2024 +0000" }, "message": "sencha: match clint frequency to cheriot-rtos timer_hz\n\nBypass-Presubmit\u003d+1\nBypass-Presubmit-Reason:collateral damage\n\nChange-Id: I1332ed1ba6ec09ec4830620165c71cffbb078944\n" }, { "commit": "779ad95b96f6f95eb6355eb22e7b7597cec0f68f", "tree": "67df82424a929d684bba1866a01f07c6dec6937d", "parents": [ "817851402cdd8e5492cc7bd8cc3da3aa7d254400" ], "author": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Wed Aug 07 16:21:18 2024 -0700" }, "committer": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Wed Aug 07 16:25:02 2024 -0700" }, "message": "sencha: track mpact-cheriot changes\n\n- support for built-in clint\n- support for stock risc-v core\n\nChange-Id: I4c77b70e7158b10a55402cfffea4228ad4ea7d29\n" }, { "commit": "817851402cdd8e5492cc7bd8cc3da3aa7d254400", "tree": "d3e60ae56307e266f9a84029483d996be8d6fbd5", "parents": [ "cdaaf36a144c7ca14d42baa7c327ba73a18327e7" ], "author": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Tue Jul 23 16:15:29 2024 -0700" }, "committer": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Tue Jul 23 16:22:43 2024 -0700" }, "message": "sencha: match sail clint frequency to cheriot-rtos board config\n\nCheriot-rtos\u0027 sail board config has timer_hz\u003d2000. Match this in the\nequivalent renode config so time calculations by the tickless scheduler\nwork as intended. Leave the sencha clint frequency as-is for now; though\nit does not match the sencha.json board config because that breaks the\nsoundstream demo for some yet-to-be-determined reason. With this change\nthe cheriot-rtos testbench passes with the tickless scheduler.\n\nBug: 350801040\n\nChange-Id: Ib459b9731f718e7c949673ab66d4dee7206e200d\n" }, { "commit": "cdaaf36a144c7ca14d42baa7c327ba73a18327e7", "tree": "001fc1e51667a71f20fc3fdafa4cdb4c9af622ae", "parents": [ "c0a24f028dbda52fadaa63bfef8ae185fcce10c4" ], "author": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Fri Jun 21 11:24:46 2024 -0700" }, "committer": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Fri Jun 21 11:30:04 2024 -0700" }, "message": "Springbok: track upstream change\n\nChange-Id: I64737a5f61bfb569bb781a0fb312988cbad00689\n" }, { "commit": "c0a24f028dbda52fadaa63bfef8ae185fcce10c4", "tree": "7711a1b9d1e7d26fc64041ecd25ebe6ab50dc714", "parents": [ "2a4c27c5d166cebb6a35b3f262d10fc69b2db58d" ], "author": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Thu Jun 06 11:19:57 2024 -0700" }, "committer": { "name": "Cindy Liu", "email": "hcindyl@google.com", "time": "Fri Jun 07 01:20:09 2024 +0000" }, "message": "shodan_infrastructure: track api change for HaltArguments\n\nBypass-Presubmit-Reason: Pass presubmit in topic\n\nChange-Id: Ib3df5654b74aa842363958a45940a514c4004562\n" }, { "commit": "2a4c27c5d166cebb6a35b3f262d10fc69b2db58d", "tree": "ee997ba96381964a07f4a4a01c1a970b1b3f4643", "parents": [ "5f59af7f1c0846f79de592f6b14f1109fca1ceca" ], "author": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Fri May 31 14:12:11 2024 -0700" }, "committer": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Sun Jun 02 14:57:12 2024 -0700" }, "message": "sencha: misc fixups\n\n- make the default setting for $tar more sensible\n- load symbols from the $cheriot_elf so the cli can use them w/o\n having to modify sencha.resc\n\nBypass-Presubmit-Reason: no sencha CI tests\n\nChange-Id: Ib841678337bdf6fa95c1987aad1e2e1ae739013f\n" }, { "commit": "5f59af7f1c0846f79de592f6b14f1109fca1ceca", "tree": "4aeffe8aa456d30c43f4469f8239cdb9388d903c", "parents": [ "b3473e595ae60e32dbad930c60d179e81d3a680d" ], "author": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Fri May 31 14:10:59 2024 -0700" }, "committer": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Sun Jun 02 14:57:07 2024 -0700" }, "message": "cheriot: leave cpu halted\n\nFor consistency with other .resc\u0027s; leave the core halted.\n\nBypass-Presubmit-Reason: no sencha CI tests\n\nChange-Id: I62c64f8648cb997c9e7daf00c8f36720c609ab94\n" }, { "commit": "b3473e595ae60e32dbad930c60d179e81d3a680d", "tree": "60bbf2bdea65c4430d5d814af8079e75483d4c83", "parents": [ "d1489cd74bace7e88751b2ff4ade2e3f3c628a7f" ], "author": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Thu May 23 09:01:20 2024 -0700" }, "committer": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Fri May 24 16:33:27 2024 +0000" }, "message": "sencha: add commonly used (optional) code in comments\n\n- load kelvin with a model\n- instruction and/or memory profiling\n\nBypass-Presubmit-Reason: no sencha CI tests\n\nChange-Id: I1765a04d8891b7b5a0f5506bcfd218240d1a8486\n" }, { "commit": "d1489cd74bace7e88751b2ff4ade2e3f3c628a7f", "tree": "a8f29c6242bc384e642bd77b266a975e135ede1c", "parents": [ "52a8f24d7ed8971cb2f070489c228f694e6dba55" ], "author": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Thu May 23 09:00:08 2024 -0700" }, "committer": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Thu May 23 17:03:01 2024 +0000" }, "message": "sencha: use $cheriot_elf to name any loaded firmware image\n\nBypass-Presubmit-Reason: no sencha CI tests\n\nChange-Id: I8e82d894871a148c95059691681565c9dac340ff\n" }, { "commit": "52a8f24d7ed8971cb2f070489c228f694e6dba55", "tree": "f0b6e92794d2f8467c893f1a639f221a72bf74ef", "parents": [ "d0af6944498d88895580d3c9e205af80a99e68e2" ], "author": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Wed May 22 10:12:27 2024 -0700" }, "committer": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Wed May 22 10:19:35 2024 -0700" }, "message": "sencha: track more upstream changes\n\nBypass-Presubmit-Reason: no sencha CI tests\n\nChange-Id: I8cc46bdbe186297ba088d9e295cc7d74a0b4dd5e\n" }, { "commit": "d0af6944498d88895580d3c9e205af80a99e68e2", "tree": "3d6922f446c1f1504e1ebbb7e581f560c83ca106", "parents": [ "e8aa5a8dbf242f5680bcf8c5e43953390d29ff4c" ], "author": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Tue May 21 14:59:17 2024 -0700" }, "committer": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Wed May 22 10:19:20 2024 -0700" }, "message": "sencha: update for refactoring \u0026 profiling support\n\n- add support for instruction \u0026 memory profiling.\n- refactor Cheriot CPU classes\n- update copyright notices\n\nBypass-Presubmit-Reason: no sencha CI tests\n\nNB: this requires an updated toolchain\n\nChange-Id: I81ee768c2bb39bf9970d2ee0d7373019db51c7dc\n" }, { "commit": "e8aa5a8dbf242f5680bcf8c5e43953390d29ff4c", "tree": "02690f36137dd933a6eab2de7091c4757330b4f6", "parents": [ "eda230ab231bf68b4f9bca14e7224623f2e48aca" ], "author": { "name": "Cindy Liu", "email": "hcindyl@google.com", "time": "Wed May 22 03:20:33 2024 -0700" }, "committer": { "name": "Cindy Liu", "email": "hcindyl@google.com", "time": "Wed May 22 11:46:59 2024 +0000" }, "message": "Fix External CPU API\n\nMatch https://github.com/renode/renode-infrastructure/commit/03eb1abf\n\nAlso fix PerformanceInMips data type warning\n\nBypass-Presubmit-Reason: test_nexus_boot_robot test broken at ToT\n\nChange-Id: Id3c5f273bd206e0f85cfc71a16218ae862778d03\n" }, { "commit": "eda230ab231bf68b4f9bca14e7224623f2e48aca", "tree": "bf7a5f38c9cd2aaff0b0336c35d278f747b58bca", "parents": [ "85b0a2c7137befb9c1ae10c86df7961de0d494a3" ], "author": { "name": "Murali Vijayaraghavan", "email": "muralivi@google.com", "time": "Tue May 14 17:12:10 2024 +0000" }, "committer": { "name": "Murali Vijayaraghavan", "email": "muralivi@google.com", "time": "Tue May 14 21:50:06 2024 +0000" }, "message": "cheriot: Added cheriot\u0027s testbench\n\n- Added a sail.repl that matches sail.json spec\n- Removed uart specification from cheriot.repl; they should be added in sencha_smc.repl and sail.repl, as appropriate\n- cheriot.resc should load sail.repl and test-suite to run the tests in standalone cheriot\n\nBypass-Presubmit-Reason: no sencha CI tests\n\nChange-Id: I42ed7701087b2818660d7e3d30afbdd2035880de\n" }, { "commit": "85b0a2c7137befb9c1ae10c86df7961de0d494a3", "tree": "5c16450269e7d732588eaac45f726e3b44610216", "parents": [ "6f40d21849067bad0cf173afdf6c29529baff3cf" ], "author": { "name": "Yenkai Wang", "email": "ykwang@google.com", "time": "Wed May 08 18:26:13 2024 -0600" }, "committer": { "name": "Yenkai Wang", "email": "ykwang@google.com", "time": "Thu May 09 14:26:19 2024 -0600" }, "message": "Revert the read register from 64 bits into 32 bits\n\nRenode gdb server calls function GetRegisterUnsafe to get register data\nwhen we run command `info registers` from the gdb client. The return\ndata type is UInt64 format for each register. And riscv gdb client will\nreceive double sized packet and report size error.\n\nReverting the register size enables us to use riscv gdb running commands\n`info threads`, `thread 2` and `info registers` to dump register info on\nCHERIot SMC core.\n\nBug: 331940020\nBypass-Presubmit-Reason: It is a config change to Sencha project.\nMatcha is unaffected.\n\nChange-Id: I372b21aca0afb9e3dd0662d8beb5632f40e01eef\n" }, { "commit": "6f40d21849067bad0cf173afdf6c29529baff3cf", "tree": "18f1b29c8302f2046aca0a5a003a84bda172d96b", "parents": [ "9aec705f290d74cf79a072dc736542a4d22ed858" ], "author": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Thu May 09 11:23:04 2024 -0700" }, "committer": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Thu May 09 19:04:05 2024 +0000" }, "message": "cheriot: load firmware image symbols into simulator\n\nIn particular this enables the simulator to identify when the simulation\nsignals termination by writing to \"tohost\".\n\nBypass-Presubmit-Reason: no sencha tests\n\nChange-Id: I897c0d67f578307bb3ce9fe3822ab4cfa3440a9d\n" }, { "commit": "9aec705f290d74cf79a072dc736542a4d22ed858", "tree": "e2cb721954f15f3f63fed7c3beca9d6494fe4a61", "parents": [ "427eab9945dd386f5a62cc1d5916afb76c18afaf", "b989d8c26cd2b311f9ce9bece32bb2c31ef54a95" ], "author": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Thu May 09 19:03:21 2024 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu May 09 19:03:21 2024 +0000" }, "message": "Merge \"sencha: remove unintentional i2s logLevel setting\"" }, { "commit": "b989d8c26cd2b311f9ce9bece32bb2c31ef54a95", "tree": "79b0dd22378913172f15690d7ef8c168296a2baa", "parents": [ "3c3484d11a7c4aa8855d52095c8125791c692f56" ], "author": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Thu May 09 11:07:40 2024 -0700" }, "committer": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Thu May 09 19:03:14 2024 +0000" }, "message": "sencha: remove unintentional i2s logLevel setting\n\nBypass-Presubmit-Reason: no sencha tests\n\nChange-Id: I049f6c3e474f6c5e9e2b6e35a55399ba87cbbe75\n" }, { "commit": "427eab9945dd386f5a62cc1d5916afb76c18afaf", "tree": "0bbdb5b636350881477fea31c5761dd77b69a6a9", "parents": [ "3c3484d11a7c4aa8855d52095c8125791c692f56" ], "author": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Thu May 09 11:10:11 2024 -0700" }, "committer": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Thu May 09 19:02:27 2024 +0000" }, "message": "MpactCheriotCPU: track new simulator functionality\n\n- load_elf replaces load_executable to support passing symbols into\n the simulator\n- symbols can be used in the cli in lieu of memory addresses\n- if symbols are passed to the simulator and the \"tohost\" symbol is\n defined, the simulator will plant a watchpoint to identify when a\n simulation has terminated\n- (unrelated) WaitForCLI now defaults to true\n\nNote: this requires an updated cheriot toolchain\n\nBypass-Presubmit-Reason: no sencha tests\n\nChange-Id: I890c5332993080e7bec2a3efdc209af029d6f538\n" }, { "commit": "3c3484d11a7c4aa8855d52095c8125791c692f56", "tree": "e5713c8df2222f2d1ff7638454854d456390ae4c", "parents": [ "e36ce8bf89c57f62f104066ff58d9dc656b1ee45" ], "author": { "name": "Murali Vijayaraghavan", "email": "muralivi@google.com", "time": "Thu May 09 00:23:09 2024 +0000" }, "committer": { "name": "Murali Vijayaraghavan", "email": "muralivi@google.com", "time": "Thu May 09 00:23:09 2024 +0000" }, "message": "standalone cheriot simulator with a couple of fixes\n\nChange-Id: I36dd5a0af5bb9a0b18c903e475b250a72eb30583\n" }, { "commit": "e36ce8bf89c57f62f104066ff58d9dc656b1ee45", "tree": "b697fad2d432530ee0057246937b36642165d244", "parents": [ "24dfe3aa5c86146bd78201f53f590a809320c447" ], "author": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Wed May 08 16:54:02 2024 -0700" }, "committer": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Wed May 08 16:55:30 2024 -0700" }, "message": "MpactCherioCPU: fix irq handling\n\nRestore init\u0027d mpact_id to -1 so we can dtrt in OnGPIO and discard\nirq\u0027s when no simulator is running to process them.\n\nChange-Id: Ic615dd458e0a01ccaef9a4bacb7962d80b12750b\n" }, { "commit": "24dfe3aa5c86146bd78201f53f590a809320c447", "tree": "d9457a537cc45add51d7292ebd6b31d0abd98bd5", "parents": [ "d2fc13502bb83e77a163807fcd505af3ce410d38" ], "author": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Fri Apr 19 13:29:56 2024 -0700" }, "committer": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Wed May 08 07:54:11 2024 -0700" }, "message": "sencha: add standalone cheriot support\n\nThis lets you run a cheriot firmware image directly in renode with\nsomething like:\n\ncd $ROOTDIR\nrenode -e \"i @sim/config/cheriot.resc; start\" --disable-xwt --console\n\n(and/or passing the pathname to the ELF file as $bin).\n\nChange-Id: I9409b438243b270b8f3b99aa5b9ae92fcbbe803d\n" }, { "commit": "d2fc13502bb83e77a163807fcd505af3ce410d38", "tree": "27dece3e741610b9c20f8d42b2ed65a1b903059f", "parents": [ "fff2e90cfc0c3e8858d3c4da88cd1291476e4ade" ], "author": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Fri Apr 19 13:29:56 2024 -0700" }, "committer": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Wed May 08 07:47:17 2024 -0700" }, "message": "sencha: track changes to MpactCheriotCPU.cs\n\n- MpactCheriotPeripheral is now bundled with and bound to the\n MpactCherioCPU class; this includes combining the code in one file\n- no more need to setup ram_smc; mpact sim is not shared any more\n- CliPort -\u003e CLIPort and WaitForCli -\u003e WaitForCLI\n- renode LoadELF now works (LoadBinary should too but not tested)\n- constructors changed; adjust the c# code to match\n- massive style changes to MpactCheriotCPU.cs\n\nNB: this requires an update cheriot toolchain\n\nChange-Id: I9034e06c7ffecf78312b38b59ef971256f78107d\n" }, { "commit": "fff2e90cfc0c3e8858d3c4da88cd1291476e4ade", "tree": "ffeaf3e308090f702d33f2384a95a3dd01513178", "parents": [ "d85952f6c20919d0207f545210f6fc83beef48a8" ], "author": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Fri May 03 13:57:01 2024 -0700" }, "committer": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Mon May 06 08:00:29 2024 -0700" }, "message": "sencha: add WaitForCli property\n\nChange-Id: I3618cb99969d189d30a749d701242c8db4463574\n" }, { "commit": "d85952f6c20919d0207f545210f6fc83beef48a8", "tree": "2b8837bb7f1620c57d731c902137a1e4dda493b9", "parents": [ "8539f12fe29a339723aaf1627a15c451812c1e1e" ], "author": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Thu May 02 12:41:56 2024 -0700" }, "committer": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Thu May 02 12:43:56 2024 -0700" }, "message": "sencha: default cli port to -1 (no connection)\n\nThis enables wrappers to enable the cli without modifying the renode\nconfiguration.\n\nChange-Id: I34ec39c2cf1ede25bbd3b28e4627c537e85aa192\n" }, { "commit": "8539f12fe29a339723aaf1627a15c451812c1e1e", "tree": "ff712825f2d7bceb2c66fa14f7dd58466f895c04", "parents": [ "aa0ee288fc61222bbe94482cb5fe8760c660dbd1" ], "author": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Thu May 02 11:04:42 2024 -0700" }, "committer": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Thu May 02 18:12:19 2024 +0000" }, "message": "sencha: tell mpact cli to wait for a connection at startup\n\nThe mpact cli support assumes the target cpu has it\u0027s firmware loaded,\nbut this is done by the security core. Tell the simulator to wait for\na network connection before doing anything to properly synchronize the\ncli \u0026 renode. Note this will block renode until there is a connection\nso the cli should not be enabled unless it\u0027s going to be used.\n\nNB: this requires an updated cheriot toolchain\n\nChange-Id: Iae69b4ab57697de00a7b55c78ea7b5d802a05116\n" }, { "commit": "aa0ee288fc61222bbe94482cb5fe8760c660dbd1", "tree": "dff986bdc8f3394967b9876b8af19f4439d44498", "parents": [ "ee7e4bc5c70dd47841c32f404118266fb8a28c10" ], "author": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Mon Apr 29 14:11:21 2024 -0700" }, "committer": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Wed May 01 17:22:57 2024 -0700" }, "message": "sencha: add support for exposing the cheriot_mpact simulator cli\n\nThe cheriot_mpact command line can be (optionally) enabled on an inet\nsocket (default port# 4567). When enabled cpu1 will not run (and renode\nwill block) until a \"run\" command is issued on the cli.\n\nNB: this requires an updated cheriot toolchain\n\nChange-Id: Idcdcadd09703c03a2f71f656b49f065bfec786e1\n" }, { "commit": "ee7e4bc5c70dd47841c32f404118266fb8a28c10", "tree": "2b771f03905471235b69f1ac1cae76f33dd60d91", "parents": [ "41351113dc0c41a06a6177f9e311a35ed3b677d4" ], "author": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Fri Apr 26 16:29:46 2024 -0700" }, "committer": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Fri Apr 26 16:39:31 2024 -0700" }, "message": "Revert \"i2s: Add functionality for a loopback sanity test\"\n\nThis reverts commit 822f23f438199b9a67fb5b92c9cd94cd7306c28a.\n\nWrites to the Control register that zero the SLPBK bit stop any tx+rx\nthreads as a side-effect. Since this happens as a side effect of writing\nthe Control register TX or RX bits tx and rx no longer work.\n\nChange-Id: I570023934d746591f1bb30a77027223a64416994\n" }, { "commit": "41351113dc0c41a06a6177f9e311a35ed3b677d4", "tree": "07b5d750db7699184ca1b193f35d830f466616da", "parents": [ "3f4bad76a7d5319510dc9dde106ac8b408c22bd2" ], "author": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Fri Apr 26 16:27:57 2024 -0700" }, "committer": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Fri Apr 26 16:38:34 2024 -0700" }, "message": "i2s: name the tx/rx threads\n\nHaving names improves the output \"machine GetClockSourceInfo\".\n\nChange-Id: If009eef1da26c196583140dab5d90273124b1c07\n" }, { "commit": "3f4bad76a7d5319510dc9dde106ac8b408c22bd2", "tree": "1587d7578c5f6d24a35e2c1fd51f1813bed849c8", "parents": [ "ed3415c7234409abeaab6a287e7719cdc2db9e6f" ], "author": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Thu Apr 25 11:01:37 2024 -0700" }, "committer": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Fri Apr 26 16:38:34 2024 -0700" }, "message": "i2s: fix interrupt state register handling\n\nThe INTR_STATE register uses W1C (Write-once Clear) semantics.\n\nChange-Id: If6ac172fffa34ef7233f7917c222b4f49ab613bb\n" }, { "commit": "ed3415c7234409abeaab6a287e7719cdc2db9e6f", "tree": "6c637b3f2440ec2c99ae5a1cbd711ef8458b8616", "parents": [ "1ebee9af9bd69749bb803f0bbc0623081d99c638" ], "author": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Thu Apr 25 10:56:43 2024 -0700" }, "committer": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Fri Apr 26 15:57:42 2024 +0000" }, "message": "sencha_smc: add plic comments\n\nClarify plic interrupt configuration; the cheri-enabled core does not\nimplement S mode.\n\nChange-Id: I666b041972932137e62707be7b33c05cbc95ce38\n" }, { "commit": "1ebee9af9bd69749bb803f0bbc0623081d99c638", "tree": "2c2faa01e97eb94c35abd1bf0508bae28449cb5a", "parents": [ "20474a52b124626ab2f27545e0feafea905245ef" ], "author": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Fri Mar 29 12:18:24 2024 -0700" }, "committer": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Tue Apr 23 21:36:37 2024 +0000" }, "message": "Initial sencha support\n\nBuilds \u0026 runs a release firmware image. Enabling built-in audio\ndata allows demo app to run further but it hangs (likely in the\ni2s emulation where it also hangs for nexus).\n\nTODO: gdb support needs work, stock gdb complains:\n\n warning: while parsing target description: not well-formed (invalid token)\n warning: Could not load XML target description; ignoring\n warning: multi-threaded target stopped without sending a thread-id, using first non-exited thread\n Remote \u0027g\u0027 packet reply is too long (expected 132 bytes, got 264 bytes):...\n\nBug: 330742177\n\nChange-Id: I3d2565572313725765b91bac55f93cb0a30babb6\n" }, { "commit": "20474a52b124626ab2f27545e0feafea905245ef", "tree": "856aa097bef9db071a6edd9a7147e53c9ec83a84", "parents": [ "822f23f438199b9a67fb5b92c9cd94cd7306c28a" ], "author": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Fri Jan 26 14:01:08 2024 -0800" }, "committer": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Fri Jan 26 14:01:08 2024 -0800" }, "message": "Update Springbok Renode model API usage\n\n- Renode\u0027s RiscV32 constructor changed arguments a bit, so update\n SpringbokRiscV32 to match.\n\nChange-Id: If5804e89999b470553fae06e4032705e0c0a9ddc\n" }, { "commit": "822f23f438199b9a67fb5b92c9cd94cd7306c28a", "tree": "5bf14bf0b105edd8569e358f2e33f03949bf6135", "parents": [ "c6a976c185595cac3cfadf81e64a17e4dbf2b678" ], "author": { "name": "June Tate-Gans", "email": "jtgans@google.com", "time": "Mon Dec 04 18:33:41 2023 +0000" }, "committer": { "name": "June Tate-Gans", "email": "jtgans@google.com", "time": "Tue Dec 05 14:34:10 2023 +0000" }, "message": "i2s: Add functionality for a loopback sanity test\n\nThis simply makes the peripheral initiate record and playback at the\nsame time, while also shoveling bytes between both FIFOs to write to\ndisk. In essence, this does a round-trip through the peripheral code,\nand should produce a 1:1 matching output on disk from the input file.\nUnfortunately, there\u0027s no easy way to detect when the recording audio\ndata has run out, so it\u0027s on the user to stop it by disabling the\nloopback bit in the control register. In short, to run this sanity\ncheck, do the following:\n\n 1. Set the input and output files in the Renode configuration script.\n 2. Start the simulation\n 3. Telnet to the Renode console\n 4. Run `i2s0 WriteDoubleWord 0x0c 4`\n 5. Wait a while.\n 6. Run `i2s0 WriteDoubleWord 0x0c 0` or quit Renode.\n\nAt this point, the output file should contain the same data as what\nwas in the input file. Since we can\u0027t determine when the file is out\nof bytes to read, it may end up zero padded.\n\nChange-Id: I79eb3f017cea3dc415305372e5670789eb329266\n" }, { "commit": "c6a976c185595cac3cfadf81e64a17e4dbf2b678", "tree": "cae5a24ce7586d15caf7956e7654a903ac2b2f84", "parents": [ "4842147fa07501d0b586047d62b274515b072fe9" ], "author": { "name": "June Tate-Gans", "email": "jtgans@google.com", "time": "Fri Dec 01 22:22:11 2023 +0000" }, "committer": { "name": "June Tate-Gans", "email": "jtgans@google.com", "time": "Mon Dec 04 16:56:19 2023 +0000" }, "message": "i2s: Allow recording to multiple files\n\nThis simply abuses the PCMEncoder class to change the output filename\nusing an indexing scheme each time it is restarted using the CSR.\n\nChange-Id: Ic2d393b5c2c6a732d36de5869540b51d251f9a7c\n" }, { "commit": "4842147fa07501d0b586047d62b274515b072fe9", "tree": "29687fe268734cf984d56f785b2f8d9b0c2f6c97", "parents": [ "b509bdbbd1602a8be2d43d146511cc0767dd424f" ], "author": { "name": "June Tate-Gans", "email": "jtgans@google.com", "time": "Fri Dec 01 18:04:09 2023 +0000" }, "committer": { "name": "June Tate-Gans", "email": "jtgans@google.com", "time": "Fri Dec 01 18:04:09 2023 +0000" }, "message": "i2s: Adjust fifo buffer size to match real hardware\n\nChange-Id: I4caf9aaa45f9be0b254f446fa51705b7f54083ff\n" }, { "commit": "b509bdbbd1602a8be2d43d146511cc0767dd424f", "tree": "a6a265a84d9cd361b7b47dc87e96a22540721dbf", "parents": [ "a6b9196a32c9a438922937d4c9e80deff026d119" ], "author": { "name": "June Tate-Gans", "email": "jtgans@google.com", "time": "Thu Nov 30 20:46:17 2023 +0000" }, "committer": { "name": "June Tate-Gans", "email": "jtgans@google.com", "time": "Thu Nov 30 21:53:42 2023 +0000" }, "message": "i2s: Add playback output to a file\n\nWe needed a way to double check the outputs of our recording in a\nloopback. This allows us to record our playback audio from the\nTX FIFO and store to disk in a raw file.\n\nAdditionally, this adjusts the output file to /tmp/speaker.raw.\n\nChange-Id: I20058fdd3afa1e34561cae13e0d9ebd03a72f3ba\n" }, { "commit": "a6b9196a32c9a438922937d4c9e80deff026d119", "tree": "bb2a40e5dba36b57269a68c1087d8014cb68b7b8", "parents": [ "2ffe8ebe79111b23252f37344afcda3c30a955c7" ], "author": { "name": "June Tate-Gans", "email": "jtgans@google.com", "time": "Thu Nov 30 20:20:25 2023 +0000" }, "committer": { "name": "June Tate-Gans", "email": "jtgans@google.com", "time": "Thu Nov 30 20:20:25 2023 +0000" }, "message": "i2s: Fix buffer size off by one error\n\nThe FIFO ring buffer cursors were not incrementing and creating an\nillusion of a false LIFO queue because the mask and size were off.\nAdditionally, to ease debugging, this replaces the square wave of\nthe original test data with a more deterministic, and somewhat\nshorter sine wave that was programmatically generated without\naliasing.\n\nChange-Id: I118cc73bca6d467b967f702465c5f3a758ff4d07\n" }, { "commit": "2ffe8ebe79111b23252f37344afcda3c30a955c7", "tree": "3a449d8ad523fd5ebb4dc5310fe2cabb1fe122b9", "parents": [ "22cc5988863e2458fd77c5f64cd62cae04545f86", "2d24b5d800600816efefba67fec52e24ef1e67fd" ], "author": { "name": "Matthew Wilson", "email": "mwilson@google.com", "time": "Thu Nov 16 21:00:31 2023 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Nov 16 21:00:31 2023 +0000" }, "message": "Merge \"testing: Unify the platform names to be more programmatic.\"" }, { "commit": "2d24b5d800600816efefba67fec52e24ef1e67fd", "tree": "08fea94e08989b81246f2fec08c834edad8aae19", "parents": [ "9b7177fcd004eff384361189cedda359d62b1feb" ], "author": { "name": "June Tate-Gans", "email": "jtgans@google.com", "time": "Fri Sep 01 08:12:19 2023 -0700" }, "committer": { "name": "Matthew Wilson", "email": "mwilson@google.com", "time": "Mon Nov 13 16:35:53 2023 -0800" }, "message": "testing: Unify the platform names to be more programmatic.\n\nChange-Id: I4dde04437c6e6f94e3db967166eec02c5249b44e\n" }, { "commit": "22cc5988863e2458fd77c5f64cd62cae04545f86", "tree": "2be51f8e7ca7785e720c6bc297033fadfdf51d72", "parents": [ "9b7177fcd004eff384361189cedda359d62b1feb" ], "author": { "name": "June Tate-Gans", "email": "jtgans@google.com", "time": "Tue Nov 07 18:54:45 2023 +0000" }, "committer": { "name": "June Tate-Gans", "email": "jtgans@google.com", "time": "Mon Nov 13 20:41:24 2023 +0000" }, "message": "i2s: Fill out I2S peripheral simulation\n\nRenode managed \"threads\" are not actually threads. They\u0027re more\nlike real-time processing functions, or coroutines, than threads.\nThe prior behavior was executing so fast that the FIFO could never\nbe emptied fast enough to trigger an empty IRQ.\n\nThis change alters the behavior such that a single frame is\nadded to the FIFO each time the function is called.\n\nChange-Id: I7bbff4f7cec7e8b7e0e3fede17512bc3f49b7179\n" }, { "commit": "9b7177fcd004eff384361189cedda359d62b1feb", "tree": "720ec3ac60d71380a89d89031f1f9a309d6b7542", "parents": [ "e6ef5b1fb73bd2e6cee4ff03283bea5400dcb715", "592812efbc3760eae412cc3241b728445f98fe33" ], "author": { "name": "June Tate-Gans", "email": "jtgans@google.com", "time": "Tue Nov 07 15:12:04 2023 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Nov 07 15:12:04 2023 +0000" }, "message": "Merge \"i2s: Add in missing IRQ registers\"" }, { "commit": "592812efbc3760eae412cc3241b728445f98fe33", "tree": "f22aa229e4f65877499572d5eb6ecb8ed0cba48f", "parents": [ "358dca98c71eaa7682122d99fcc8ead00d9adc7b" ], "author": { "name": "June Tate-Gans", "email": "jtgans@google.com", "time": "Mon Nov 06 19:35:40 2023 +0000" }, "committer": { "name": "June Tate-Gans", "email": "jtgans@google.com", "time": "Mon Nov 06 20:30:09 2023 +0000" }, "message": "i2s: Add in missing IRQ registers\n\nChange-Id: Ib05f7888797673e7306f9094b0df991a837c3c7e\n" }, { "commit": "e6ef5b1fb73bd2e6cee4ff03283bea5400dcb715", "tree": "8ade3603675fac4d21d1f52f05171567a425a329", "parents": [ "358dca98c71eaa7682122d99fcc8ead00d9adc7b" ], "author": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Sat Nov 04 16:30:19 2023 -0700" }, "committer": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Sat Nov 04 16:30:19 2023 -0700" }, "message": "sim/config: add i2s support to nexus platform\n\nChange-Id: I8b02811dc4df8a040b2d7dc5efd5ded9dc4a57df\n" }, { "commit": "358dca98c71eaa7682122d99fcc8ead00d9adc7b", "tree": "836681d795df91a7519bf695adc34fd24a1aac45", "parents": [ "71cc01374179af01d05a46d425263cdcac08f1b2" ], "author": { "name": "Cindy Liu", "email": "hcindyl@google.com", "time": "Mon Oct 30 21:41:06 2023 -0700" }, "committer": { "name": "Cindy Liu", "email": "hcindyl@google.com", "time": "Mon Oct 30 21:41:06 2023 -0700" }, "message": "Update KelvinCPU property\n\nMatch upstream change\nhttps://github.com/renode/renode-infrastructure/commit/9220df6b\n\nChange-Id: I156dd2111f304ab94d3d44d383ed2e874371dcad\n" }, { "commit": "71cc01374179af01d05a46d425263cdcac08f1b2", "tree": "65eca746e681a63d5e9f2f67bf2f17ab26f0049a", "parents": [ "e9beb0abf100ed4e52576cecf9c5ce70be1869da" ], "author": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Mon Sep 25 16:36:36 2023 -0700" }, "committer": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Mon Oct 30 10:40:02 2023 -0700" }, "message": "Add SPI flash to renode configs\n\nb/299910690\n\nChange-Id: I0b54cac3878a94ed35ef0187201f1c61cbae1dfe\n" }, { "commit": "e9beb0abf100ed4e52576cecf9c5ce70be1869da", "tree": "585ff534d335988068160ffbc2d28af9b891a5b4", "parents": [ "0088b79f83ba37df6c771cbd0b5148f088682b5b" ], "author": { "name": "Cindy Liu", "email": "hcindyl@google.com", "time": "Fri Oct 20 09:55:08 2023 -0700" }, "committer": { "name": "Cindy Liu", "email": "hcindyl@google.com", "time": "Fri Oct 20 09:55:08 2023 -0700" }, "message": "OSS cleanup\n\nAdd OSS headers, license, readme, and contributing doc.\n\nRemove obsolete components and simulation configs\n\nBug: 306427497\nChange-Id: I67a7615f20d5ce96557637c192575a835a35f9be\n" }, { "commit": "0088b79f83ba37df6c771cbd0b5148f088682b5b", "tree": "d4a615e773a85ea7ecda15f1aa82ead681cb07fd", "parents": [ "37660e6ed1258db79beec022bb8169cb3c7c2fd8" ], "author": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Wed Oct 18 13:19:24 2023 -0700" }, "committer": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Wed Oct 18 14:04:51 2023 -0700" }, "message": "Add zicsr extension to cpu0/cpu1\n\n- On today\u0027s nightly of Renode, we get warning about not having zicsr\n extension explicitly enabled.\n\nChange-Id: Icadf0b2c8bda74a8e413993f7b28cc17df06e306\n" }, { "commit": "37660e6ed1258db79beec022bb8169cb3c7c2fd8", "tree": "541867868949a9faa02034b6754d37a4898883f4", "parents": [ "5347cd5eeee46340b9f9e21b99f7ee28af130fae" ], "author": { "name": "June Tate-Gans", "email": "jtgans@google.com", "time": "Mon Oct 16 19:36:51 2023 +0000" }, "committer": { "name": "June Tate-Gans", "email": "jtgans@google.com", "time": "Tue Oct 17 17:19:41 2023 +0000" }, "message": "renode: Initial implementation of Matcha I2S driver\n\nChange-Id: Id1f04d2b8bd64cddc08531d40ccc2903b0fa719b\n" }, { "commit": "5347cd5eeee46340b9f9e21b99f7ee28af130fae", "tree": "89c6ec7a8476cf535c5e5282cc3c2186392a378b", "parents": [ "fc71ba9bcf5f14b7ad371fb4aecda93050ea9fc0" ], "author": { "name": "Cindy Liu", "email": "hcindyl@google.com", "time": "Fri Oct 13 14:28:14 2023 -0700" }, "committer": { "name": "Cindy Liu", "email": "hcindyl@google.com", "time": "Fri Oct 13 15:30:10 2023 -0700" }, "message": "Use HW boot rom in renode simulation\n\nNeed to preload the secure core binary to the eflash to avoid the\nbootstrapping step (the same mechanism as in verilator sim)\n\nChange-Id: I04516c5d7576d38d453d21f9ad1139720ce4d712\n" }, { "commit": "fc71ba9bcf5f14b7ad371fb4aecda93050ea9fc0", "tree": "5f53621fb4244f658c36a57ee306774c9b4e2e3b", "parents": [ "e28b8cedf7abff79bed119e889815e744ae7c17f" ], "author": { "name": "Cindy Liu", "email": "hcindyl@google.com", "time": "Fri Oct 13 11:30:57 2023 -0700" }, "committer": { "name": "Cindy Liu", "email": "hcindyl@google.com", "time": "Fri Oct 13 11:30:57 2023 -0700" }, "message": "Fix secure core plic config off-by-one error\n\nChange-Id: I3fae156bbbdac82996079f82dd940d18b2331912\n" }, { "commit": "e28b8cedf7abff79bed119e889815e744ae7c17f", "tree": "6a4c6ea735a046c3d3c2ae799227856ca1813a88", "parents": [ "0b8092228160a1abd3b219e150441b7eb872a40c" ], "author": { "name": "Cindy Liu", "email": "hcindyl@google.com", "time": "Thu Sep 14 14:52:28 2023 -0700" }, "committer": { "name": "Cindy Liu", "email": "hcindyl@google.com", "time": "Fri Sep 15 15:04:01 2023 -0700" }, "message": "Connect KelvinCPU with e2e nexus simulation\n\nNeed to add some nop API to make springbok/kelvin module share the same\ninterface in .resc. Also remove the GDBServer for cpu2 (kelvin core\ndebugging should be done in kelvin_sim)\n\nRetire the temporary kelvin renode platform file to merge back to\n`kelvin_ml_core.repl`\n\nChange-Id: Ic9e104f5f2fef6230d77accfdb2a7271a1072a0f\n" }, { "commit": "0b8092228160a1abd3b219e150441b7eb872a40c", "tree": "8fbb1122be8255aaf39e8e3563a5129a69d215f9", "parents": [ "f79ac9a090299e1ae2780164659eae7344190ad4" ], "author": { "name": "Cindy Liu", "email": "hcindyl@google.com", "time": "Mon Sep 11 11:14:57 2023 -0700" }, "committer": { "name": "Cindy Liu", "email": "hcindyl@google.com", "time": "Thu Sep 14 11:41:34 2023 -0700" }, "message": "Share memory between renode and kelvin_sim\n\nThe MappedMemory is passed to kelvin_sim for load/store in the Kelvin SW\nprogram, so Renode and CantripOS can access the memory content same as the\nprevious KelvinRiscV32 module.\n\nChange-Id: I73853336789f90bd755eaf9f742957010deff7a5\n" }, { "commit": "f79ac9a090299e1ae2780164659eae7344190ad4", "tree": "742d8116ab6de0612fc3b35c752ff5396ff2f284", "parents": [ "65269713405e189a62c0fb4d5c015b908ba212f7" ], "author": { "name": "Cindy Liu", "email": "hcindyl@google.com", "time": "Mon Sep 11 20:12:49 2023 -0700" }, "committer": { "name": "Cindy Liu", "email": "hcindyl@google.com", "time": "Tue Sep 12 11:00:57 2023 -0700" }, "message": "Add ml_top controlblock on single-core kelvin resc and repl\n\nChange-Id: I26951636601f14975c5515169a62351c44169f54\n" }, { "commit": "65269713405e189a62c0fb4d5c015b908ba212f7", "tree": "49fb594089f9d0c4a39777e535fc06e0c58ad34a", "parents": [ "4f4ad0b4269b69f6b6345f00438f76514e51138f" ], "author": { "name": "Cindy Liu", "email": "hcindyl@google.com", "time": "Wed Sep 06 16:05:26 2023 -0700" }, "committer": { "name": "Cindy Liu", "email": "hcindyl@google.com", "time": "Wed Sep 06 18:40:29 2023 -0700" }, "message": "Integrate kelvin_sim to Renode framework (Step 1)\n\nThis is the first step of using kelvin_sim as an external CPU in the\nRenode framework.\n\nAs the first step, the KelvinCPU module can load the .bin file (same\nblob format for FPGA and cantrip), run the program with\n`sysbus.cpu2 IsHalted false`, and shows the program return. The control\nblock (ml_top registers and IRQs) will be added in the followup CLs.\n\nAlso, the 0x5A000000 ml_dmem is not used by kelvin_sim yet, so we can\u0027t\nget the data out of the memory with the current MlCooridinator\nfunctions. It will also be addressed in future CLs.\n\nChange-Id: I6e127f581615cda4e625f26ecb1a81ec4721974b\n" }, { "commit": "4f4ad0b4269b69f6b6345f00438f76514e51138f", "tree": "b901e3107c1f9b51fa246016c24ab4afd7253fbe", "parents": [ "696dd53ef98cd8faabf01d570d94e5c1a78ec441" ], "author": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Mon Aug 14 10:46:21 2023 -0700" }, "committer": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Mon Aug 14 10:46:21 2023 -0700" }, "message": "nexus sim: more irq fallout\n\nThere\u0027s 1 fewer assigned irq. Not sure why things worked w/o this.\n\nChange-Id: I4a1d123b83fe3d6bc553d7dd4eeda439e48f7d86\n" }, { "commit": "696dd53ef98cd8faabf01d570d94e5c1a78ec441", "tree": "cd71599ecd55a3332ca9a22f5d8a68e6dff704e3", "parents": [ "65a3e723efa78cc7fa0188ccff9a76f2a0ce8010" ], "author": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Fri Aug 11 10:55:04 2023 -0700" }, "committer": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Fri Aug 11 11:27:34 2023 -0700" }, "message": "nexus sim: track move of timer_smc_sw irq\n\nBug: 295534548\n\nChange-Id: I9fafd66c210e51a1dcb96ad39edf002d688be14a\n" }, { "commit": "65a3e723efa78cc7fa0188ccff9a76f2a0ce8010", "tree": "48b3ba4d73abc59da1d6b871c0fbd6613ff6e15b", "parents": [ "1022f4a26e7fc8ccdd4586ab64f3d030e0542e92" ], "author": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Mon Aug 07 16:17:11 2023 -0700" }, "committer": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Mon Aug 07 16:17:11 2023 -0700" }, "message": "Map timer_smc on Nexus to cpu1@5\n\n- Although the timer does have a PLIC interrupt, we never unmask that --\n and instead get the interrupt via the dedicated timer interrupt\n vector, so update the Renode config to reflect that.\n\nChange-Id: I6558f5fcedc0c1cae97cbf5ddd835c1408b3d8fb\n" }, { "commit": "1022f4a26e7fc8ccdd4586ab64f3d030e0542e92", "tree": "cacd21f9a114d83b075bba0eb88f7c4bac647688", "parents": [ "c2ca794f652d7d52cbe88e3ca358833e0f9cd473" ], "author": { "name": "June Tate-Gans", "email": "jtgans@google.com", "time": "Thu Aug 03 20:51:41 2023 +0000" }, "committer": { "name": "June Tate-Gans", "email": "jtgans@google.com", "time": "Thu Aug 03 20:54:41 2023 +0000" }, "message": "nexus sim config: Swap PLIC SEIP and MEIP bits\n\nApparently when we moved the timer\u0027s IRQ, we also changed which bits it\nmanipulated in the MIP register. Swap the two bits and assign the\ncorrect IRQ to smc_timer.\n\nChange-Id: Ic2991273f16c899d9b25e2853ac315544c0fb21f\n" }, { "commit": "c2ca794f652d7d52cbe88e3ca358833e0f9cd473", "tree": "fd19b9486001a12293fc11e927f0010cf4adc198", "parents": [ "0e44a670b99a95dff8cc87dd4e4493caada56e9f" ], "author": { "name": "June Tate-Gans", "email": "jtgans@google.com", "time": "Thu Aug 03 19:24:02 2023 +0000" }, "committer": { "name": "June Tate-Gans", "email": "jtgans@google.com", "time": "Thu Aug 03 19:50:42 2023 +0000" }, "message": "nexus sim target: Add in IRQ mappings\n\nChange-Id: I31574b0e4b1c56fa4e2be0454d1d4271a1086485\n" }, { "commit": "0e44a670b99a95dff8cc87dd4e4493caada56e9f", "tree": "44c706fc95cc9b9f0dd7bfd2e4fe9d5939c61c08", "parents": [ "ca9be3cac34c4fa7f4715d5ad84e931050a58597" ], "author": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Thu Jul 27 10:21:30 2023 -0700" }, "committer": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Thu Jul 27 17:16:14 2023 -0700" }, "message": "sim/config: track CANTRIP_OUT_DIR pathname change\n\nBug: 293296515\n\nChange-Id: I8c60de47c258f4df0ddef14a91c8c0eb5eb78bce\n" }, { "commit": "ca9be3cac34c4fa7f4715d5ad84e931050a58597", "tree": "79c89522f9c63f6b80477fbab008b49045d02f91", "parents": [ "3fc081693aa465507a1dd755f5c3c6ba3b918569" ], "author": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Fri Jul 21 11:27:15 2023 -0700" }, "committer": { "name": "Sam Leffler", "email": "sleffler@google.com", "time": "Fri Jul 21 19:01:43 2023 +0000" }, "message": "sim/config:nexus-debug: correct memory size\n\nA debug nexus build has 64M of SMC RAM, regardless of the real hardware\n(debug builds can only run on Renode where memory is free!).\n\nChange-Id: I672a683a1946dd67f2c188f81bbb0084bcc6d27f\n" }, { "commit": "3fc081693aa465507a1dd755f5c3c6ba3b918569", "tree": "2aeff89339a5abcbabf644d494f6683f9d738182", "parents": [ "2038f7d5fa9a9d8ac64a9456f4ab6e418e587e11" ], "author": { "name": "June Tate-Gans", "email": "jtgans@google.com", "time": "Thu Jul 20 18:13:20 2023 +0000" }, "committer": { "name": "June Tate-Gans", "email": "jtgans@google.com", "time": "Fri Jul 21 17:15:51 2023 +0000" }, "message": "nexus sim: Bring in more nexus config changes\n\n - Adjust IRQ numbers for SMC mailbox\n - Tweak memory to the actual FPGA size\n - Add debug tags\n\nChange-Id: I26e1c3c2dfdf8a4350670b34aae811dc64b52e4f\n" }, { "commit": "2038f7d5fa9a9d8ac64a9456f4ab6e418e587e11", "tree": "9f6e9147d56b627ec2ac1595073d199e158a7d9c", "parents": [ "23bbb69243d729bda239827eb786d978bd8f5c46" ], "author": { "name": "June Tate-Gans", "email": "jtgans@google.com", "time": "Thu Jul 20 15:44:36 2023 +0000" }, "committer": { "name": "June Tate-Gans", "email": "jtgans@google.com", "time": "Thu Jul 20 15:44:36 2023 +0000" }, "message": "nexus sim: Adjust shodan toplevel load addresses\n\nNexus defines a different CPIO load address than shodan, so we need to\nbe able to change it during simulation time.\n\nChange-Id: Ie8dcc08b336e8dcc7a9929a8c3fa5f2f7418bb15\n" }, { "commit": "23bbb69243d729bda239827eb786d978bd8f5c46", "tree": "0b03700ec1471ed388d62ae8733143f6e675df1d", "parents": [ "3131ee981e87d0641d2d0daccab284215f1daf90", "da030a8d7af363445cfa4d6a25a2363c08820741" ], "author": { "name": "Cindy Liu", "email": "hcindyl@google.com", "time": "Fri Jul 14 22:57:50 2023 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Jul 14 22:57:50 2023 +0000" }, "message": "Merge \"Update kelvin renode script to properly support debugging\"" }, { "commit": "3131ee981e87d0641d2d0daccab284215f1daf90", "tree": "fc268df5eee700a6b30ae8f8e818014746710f11", "parents": [ "8e2aa0a9247c6a962925cc2dfbd4c8ba634422ff" ], "author": { "name": "June Tate-Gans", "email": "jtgans@google.com", "time": "Fri Jul 14 22:08:39 2023 +0000" }, "committer": { "name": "June Tate-Gans", "email": "jtgans@google.com", "time": "Fri Jul 14 22:08:39 2023 +0000" }, "message": "nexus: Fix timer base address\n\nChange-Id: Ife7b26c3cce6c34b7fe71ee555ef959b2cb030be\n" }, { "commit": "8e2aa0a9247c6a962925cc2dfbd4c8ba634422ff", "tree": "7db3a0edf23b748ff7f127e8567223050aa5f342", "parents": [ "08a763ff73294296a087db7a769b0cbe3b81beaa" ], "author": { "name": "June Tate-Gans", "email": "jtgans@google.com", "time": "Thu Jul 13 15:17:21 2023 +0000" }, "committer": { "name": "June Tate-Gans", "email": "jtgans@google.com", "time": "Fri Jul 14 20:26:14 2023 +0000" }, "message": "sim: Adjust UART and timer addresses to match hardware\n\nChange-Id: I27cce9b4aa38fa76d38aa9e9a108b6313d56cabd\n" }, { "commit": "da030a8d7af363445cfa4d6a25a2363c08820741", "tree": "8964cbd2d921834befa8a09920c92b942e4af4e1", "parents": [ "08a763ff73294296a087db7a769b0cbe3b81beaa" ], "author": { "name": "Cindy Liu", "email": "hcindyl@google.com", "time": "Thu Jul 13 21:53:56 2023 -0700" }, "committer": { "name": "Cindy Liu", "email": "hcindyl@google.com", "time": "Fri Jul 14 08:38:10 2023 -0700" }, "message": "Update kelvin renode script to properly support debugging\n\nTo debug Renode with GDB, the Renode simulation should be started by\nGDB automatically when the debug server is attached to GDB. Clean up the\nrenode script to follow the same flow we used in springbok to make sure\nGDB can capture the process reliably.\n\nChange-Id: I416565bcb8b02b8b137fe2a7ebc822d9821607ac\n" }, { "commit": "08a763ff73294296a087db7a769b0cbe3b81beaa", "tree": "b326446c56b95a09589692b683b8158fe4f05ef7", "parents": [ "fc2529c2ff9a84ca132597ab63580a0fff4093da" ], "author": { "name": "Jon Tate", "email": "jonathantate@google.com", "time": "Wed Jul 12 16:16:56 2023 +0000" }, "committer": { "name": "Jon Tate", "email": "jonathantate@google.com", "time": "Wed Jul 12 19:17:00 2023 +0000" }, "message": "Nexus: replace Springbok with Kelvin\n\nForking ml_core.repl to [springbok|kelvin]_ml_core.repl.\n\nChange-Id: Icf4bb5277be7a671c14a8e6e05b72c7a41ffb8d3\n" }, { "commit": "fc2529c2ff9a84ca132597ab63580a0fff4093da", "tree": "df9c6a674c3e5cea71220f579627bcfa57cff943", "parents": [ "dd633231e75ee60a9ba7d19359115a52f1c57420" ], "author": { "name": "Jon Tate", "email": "jonathantate@google.com", "time": "Mon Jul 10 18:10:40 2023 +0000" }, "committer": { "name": "Jon Tate", "email": "jonathantate@google.com", "time": "Wed Jul 12 17:10:55 2023 +0000" }, "message": "Add 1-window WindowMMU to Kelvin to support TCM offset\n\nThis CL adds an untouchable WindowMMU to Kelvin with a single window\ntranslating addresses 0x00000000 : MemorySize to MemoryRangeStart :\nMemoryRangeStart + MemorySize. This is needed in simulation because\nKelvin\u0027s software expects memory to begin at address 0x00000000 but\nRenode doesn\u0027t support multiple address spaces without the use of\nMMUs.\n\nChange-Id: I08b7baf071f916f29f62470224e43ab7e7c221d8\n" }, { "commit": "dd633231e75ee60a9ba7d19359115a52f1c57420", "tree": "0e64e6a48dc2ef88026f19742b9a6024965ff044", "parents": [ "ed4b330979bb1d7d712c57bf268dd81b35439d1c" ], "author": { "name": "June Tate-Gans", "email": "jtgans@google.com", "time": "Wed Jul 05 18:23:06 2023 +0000" }, "committer": { "name": "June Tate-Gans", "email": "jtgans@google.com", "time": "Tue Jul 11 16:21:37 2023 +0000" }, "message": "nexus: Duplicate shodan platform to nexus\n\nChange-Id: I9b8c31ced314c01e49839c0d32bca2a085087e51\n" }, { "commit": "ed4b330979bb1d7d712c57bf268dd81b35439d1c", "tree": "82245864fa7996a4023067d0fa951a683e39ed4f", "parents": [ "a07bb70c6a9b975bd61188688316a4ea2d0e41de" ], "author": { "name": "Jon Tate", "email": "jonathantate@google.com", "time": "Thu Jun 29 23:45:26 2023 +0000" }, "committer": { "name": "Jon Tate", "email": "jonathantate@google.com", "time": "Fri Jun 30 01:38:19 2023 +0000" }, "message": "Add Kelvin core definition\n\nThis new core supports Kelvin\u0027s MPAUSE instruction, but is otherwise\na standard RV32IM core. In particular, Kelvin\u0027s SIMD extension is NOT\nsupported.\n\nThe top-level control register for reset, halt and initial PC should\nfunction as expected. The interrupt management control registers are\nalso implemented. All of the other control registers are placeholders.\n\nChange-Id: I537873eb3f2d01fb37d38c96f9016b65617677ce\n" }, { "commit": "a07bb70c6a9b975bd61188688316a4ea2d0e41de", "tree": "cf93c8593b5125fb301d20050ff875683900624d", "parents": [ "411a82fafddb70c72eccaf9f2719fcbd692817ab" ], "author": { "name": "Cindy Liu", "email": "hcindyl@google.com", "time": "Fri May 19 17:20:01 2023 -0700" }, "committer": { "name": "Cindy Liu", "email": "hcindyl@google.com", "time": "Fri May 19 17:20:01 2023 -0700" }, "message": "Add shodan debug platform definition\n\nOverride the memory size definition for debug mode. The default system\nconfiguration matches the HW config\n\nBug: 258850990\nChange-Id: I829124ee5a1bacf661e63e6a88bdf713e6bdd9de\n" }, { "commit": "411a82fafddb70c72eccaf9f2719fcbd692817ab", "tree": "89d4fa8b830e9f454e8a13cc3137a567e80fd134", "parents": [ "323346d1de636c5ccded835211ef869a6caba821" ], "author": { "name": "Cindy Liu", "email": "hcindyl@google.com", "time": "Fri May 19 09:15:39 2023 -0700" }, "committer": { "name": "Cindy Liu", "email": "hcindyl@google.com", "time": "Fri May 19 09:15:39 2023 -0700" }, "message": "Update rstmgr setting in secure core\n\nMatch https://github.com/renode/renode/commit/31b82ded4\n\nChange-Id: I2ac2171037a1f462b136b0c837fa55df80f737b6\n" }, { "commit": "323346d1de636c5ccded835211ef869a6caba821", "tree": "7c2c7497e48190273432516ea065a7a58710b9c5", "parents": [ "9f783ab3a05a38043ec99c53502ac93b25e842d1" ], "author": { "name": "Cindy Liu", "email": "hcindyl@google.com", "time": "Mon May 15 14:09:21 2023 -0700" }, "committer": { "name": "Cindy Liu", "email": "hcindyl@google.com", "time": "Thu May 18 13:15:39 2023 -0700" }, "message": "Update secure core renode platform to match ot f243e680\n\n* Retire the forked OpenTitan_Timer2\n* Add all the peripherals supported by renode\n* Connect alert_handler\n\nChange-Id: I33866e1bfa3a97e5b783902d3025332e0e62dd19\n" }, { "commit": "9f783ab3a05a38043ec99c53502ac93b25e842d1", "tree": "eb32161ccb37418acff992481ac27a091928fcba", "parents": [ "fbecd472d00ed09b369a2722d02bec3bb8c9747b" ], "author": { "name": "Cindy Liu", "email": "hcindyl@google.com", "time": "Tue Apr 04 17:00:07 2023 -0700" }, "committer": { "name": "Cindy Liu", "email": "hcindyl@google.com", "time": "Mon May 08 10:31:15 2023 -0700" }, "message": "sim:config: Retire unused forked OpenTitan2_UART\n\nUART use upstream renode model directly\n\nChange-Id: If93a989298a09475877daffd70ec6efbd2b364cf\n" }, { "commit": "fbecd472d00ed09b369a2722d02bec3bb8c9747b", "tree": "5aae6d35b76dd0a1317b2e63a56c120ec862d76c", "parents": [ "edb67e6539477f3aa7655a1ad1e5330387ac00d4" ], "author": { "name": "Cindy Liu", "email": "hcindyl@google.com", "time": "Tue Apr 04 17:22:32 2023 -0700" }, "committer": { "name": "Cindy Liu", "email": "hcindyl@google.com", "time": "Tue Apr 04 17:22:32 2023 -0700" }, "message": "sim:config: Temporarily fork OpenTitan_Timer with the updated reg\n\nUse the updated regmap to match the updated OT timer IP. Eventually we\nshould revert back to use the upstream renode model once it is updated.\n\nChange-Id: I12eea596adf42c0ad4b3fdc62f18ebf54f069ca6\n" }, { "commit": "edb67e6539477f3aa7655a1ad1e5330387ac00d4", "tree": "d589401f305e0ab4644bb66a8a5fd1bac3645e1c", "parents": [ "5c85def05b8269d837f886bc8c656001af1bbcde" ], "author": { "name": "Cindy Liu", "email": "hcindyl@google.com", "time": "Mon Apr 03 18:55:55 2023 -0700" }, "committer": { "name": "Cindy Liu", "email": "hcindyl@google.com", "time": "Mon Apr 03 18:55:55 2023 -0700" }, "message": "sim:config: Update shodan renode simulation platform\n\n* Mailbox IRQ ID\n* SEC core total interrupt\n\nNote SMC regmap is still out of sync with MATCHA HW def, and it will be\nhandled in a later CL. (it is mismatched at ToT already)\n\nChange-Id: Ib7ae4a531f0b1fafc9b9ba809f4cc2b238b65e2b\n" }, { "commit": "5c85def05b8269d837f886bc8c656001af1bbcde", "tree": "54e50c75045b6a72486ab9f7311a2f437e14fbc1", "parents": [ "145f84e4a04c68fb8148a81103ccdfba628838ce" ], "author": { "name": "Jakub Jatczak", "email": "jjatczak@antmicro.com", "time": "Mon Mar 13 14:10:58 2023 +0100" }, "committer": { "name": "Jakub Jatczak", "email": "jjatczak@antmicro.com", "time": "Mon Mar 13 14:10:58 2023 +0100" }, "message": "Prepare the Renode models for changing the PeripheralRegister underlying type\n\nAs the `PeripheralRegister` underlying value type is about to change from `ulong` to `uint` all models have to be adjusted accordingly.\nThis change is compatible with both the upcoming change and with the current master/nightly.\n\nChange-Id: I7422ae92a2767288cbc899602a8a3b7a45080f3c\n" } ], "next": "145f84e4a04c68fb8148a81103ccdfba628838ce" }