// Copyright 2022 Google LLC
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
//      http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.

// ***************************************************
// Springbok single test core (no mmu enabled)
// ***************************************************

using "sim/config/platforms/springbok_ml_core.repl"

vec_controlblock : CPU.SpringbokRiscV32_ControlBlock @ sysbus 0x47000000
    core: cpu2
    mmuNumWindows: 1
    mmuVirtualWindowSize: 0x1000000
    mmuMemorySize: 0x1000000
    mmuRangeStart: 0x34000000