Add ml_top controlblock on single-core kelvin resc and repl
Change-Id: I26951636601f14975c5515169a62351c44169f54
diff --git a/kelvin.resc b/kelvin.resc
index 52c043a..68ecce9 100644
--- a/kelvin.resc
+++ b/kelvin.resc
@@ -12,35 +12,36 @@
# See the License for the specific language governing permissions and
# limitations under the License.
-# Renode script for testing the Kelvin Vector Core
+# Renode script for testing the Kelvin core using kelvin_sim external CPU library
+
mach create "kelvin"
-EnsureTypeIsLoaded "Antmicro.Renode.Peripherals.CPU.RiscV32"
-include @sim/config/shodan_infrastructure/KelvinRiscV32.cs
-EnsureTypeIsLoaded "Antmicro.Renode.Peripherals.CPU.KelvinRiscV32"
-EnsureTypeIsLoaded "Antmicro.Renode.Peripherals.CPU.KelvinRiscV32_ControlBlock"
-$platformfile?=@sim/config/platforms/kelvin.repl
+include @sim/config/shodan_infrastructure/KelvinCPU.cs
+EnsureTypeIsLoaded "Antmicro.Renode.Peripherals.CPU.KelvinCPU"
+EnsureTypeIsLoaded "Antmicro.Renode.Peripherals.CPU.MlTopControlBlock"
+
+$platformfile?=@sim/config/platforms/kelvin_ml_core_external_cpu.repl
machine LoadPlatformDescription $platformfile
$bin?=@out/kelvin/sw/bazel_out/hello_world.bin
+$cpuLibrary?=@out/kelvin/sim/librenode_kelvin.so
-sysbus.cpu2 EnableRiscvOpcodesCounting
+sysbus.cpu2 IsHalted true
+
+sysbus.cpu2 CpuLibraryPath $cpuLibrary
+sysbus.cpu2 MemoryOffset 0
macro reset
"""
- sysbus LoadBinary $bin 0x5A000000
+ # TODO(hcindyl): Replace it with LoadBinary `sysbus LoadBinary $bin 0x5A000000`
+ sysbus.cpu2 ExecutableFile $bin
# Start the vector core at address 0 of its TCM and halt / reset it.
- sysbus.vec_controlblock WriteDoubleWord 12 3
+ sysbus.ml_top_controlblock WriteDoubleWord 0xc 3
"""
runMacro $reset
-# Note: GDB doesn't seem to like the way we're setting the program counter in
-# the vec_controlblock. Breakpoints set to the exact reset address don't seem to
-# get reliably triggered. We should probably root cause this later when we have
-# time, but as a workaround setting the breakpoint to reset_addr+4 instead seems
-# to work fine.
-# Enable vec_controlblock verbose logging
-logLevel -1 sysbus.vec_controlblock
+logLevel 0 sysbus.cpu2
+logLevel -1 sysbus.ml_top_controlblock
