)]}'
{
  "commit": "ed4b330979bb1d7d712c57bf268dd81b35439d1c",
  "tree": "82245864fa7996a4023067d0fa951a683e39ed4f",
  "parents": [
    "a07bb70c6a9b975bd61188688316a4ea2d0e41de"
  ],
  "author": {
    "name": "Jon Tate",
    "email": "jonathantate@google.com",
    "time": "Thu Jun 29 23:45:26 2023 +0000"
  },
  "committer": {
    "name": "Jon Tate",
    "email": "jonathantate@google.com",
    "time": "Fri Jun 30 01:38:19 2023 +0000"
  },
  "message": "Add Kelvin core definition\n\nThis new core supports Kelvin\u0027s MPAUSE instruction, but is otherwise\na standard RV32IM core. In particular, Kelvin\u0027s SIMD extension is NOT\nsupported.\n\nThe top-level control register for reset, halt and initial PC should\nfunction as expected. The interrupt management control registers are\nalso implemented. All of the other control registers are placeholders.\n\nChange-Id: I537873eb3f2d01fb37d38c96f9016b65617677ce\n",
  "tree_diff": [
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "b3ee710da549810a15ce2116a105ece2ebfe187d",
      "new_mode": 33188,
      "new_path": "kelvin.resc"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "0aa30ae96cd2df5fe27f8c80ea502fec03ec120e",
      "new_mode": 33188,
      "new_path": "platforms/kelvin.repl"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "1b7772dba1299d29fd8ff752cdf3bc1fc70915d3",
      "new_mode": 33188,
      "new_path": "shodan_infrastructure/KelvinRiscV32.cs"
    }
  ]
}