diff --git a/kelvin.resc b/kelvin.resc
index 8bae286..4aea9c1 100644
--- a/kelvin.resc
+++ b/kelvin.resc
@@ -21,7 +21,7 @@
 EnsureTypeIsLoaded "Antmicro.Renode.Peripherals.CPU.KelvinCPU"
 EnsureTypeIsLoaded "Antmicro.Renode.Peripherals.CPU.MlTopControlBlock"
 
-$platformfile?=@sim/config/platforms/kelvin_ml_core_external_cpu.repl
+$platformfile?=@sim/config/platforms/kelvin.repl
 
 machine LoadPlatformDescription $platformfile
 
diff --git a/platforms/kelvin.repl b/platforms/kelvin.repl
index 4579a49..7af3b4c 100644
--- a/platforms/kelvin.repl
+++ b/platforms/kelvin.repl
@@ -18,7 +18,5 @@
 
 using "sim/config/platforms/kelvin_ml_core.repl"
 
-vec_controlblock : CPU.KelvinRiscV32_ControlBlock @ sysbus 0x5C000000
+ml_top_controlblock : CPU.MlTopControlBlock @ sysbus 0x5C000000
     core: cpu2
-    tcmSize:       0x00400000
-    tcmRangeStart: 0x5A000000
diff --git a/platforms/kelvin_ml_core.repl b/platforms/kelvin_ml_core.repl
index ac91986..d7bd972 100644
--- a/platforms/kelvin_ml_core.repl
+++ b/platforms/kelvin_ml_core.repl
@@ -1,4 +1,4 @@
-// Copyright 2022 Google LLC
+// Copyright 2023 Google LLC
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -13,12 +13,14 @@
 // limitations under the License.
 
 // ***************************************************
-// ML Core
+// ML Core that uses kelvin_sim as the external CPU library.
 // ***************************************************
 
-cpu2: CPU.KelvinRiscV32 @ sysbus
-    hartId: 2
+cpu2: CPU.KelvinCPU @ sysbus
+    id: 1
+    cpuType: "Kelvin"
+    memory: ram_ml_top_dmem
 
-//RAM_VEC_MEM      [‘h5A00_0000 - ‘h5A3F_FFFF)   4MB RAM for Vector core
-ram_vec_dmem: Memory.MappedMemory @ sysbus 0x5A000000
+// RAM_ML_TOP_MEM      [‘h5A00_0000 - ‘h5A3F_FFFF)   4MB RAM for ML core
+ram_ml_top_dmem: Memory.MappedMemory @ sysbus 0x5A000000
     size: 0x00400000
diff --git a/platforms/kelvin_ml_core_external_cpu.repl b/platforms/kelvin_ml_core_external_cpu.repl
deleted file mode 100644
index a4dd79f..0000000
--- a/platforms/kelvin_ml_core_external_cpu.repl
+++ /dev/null
@@ -1,30 +0,0 @@
-// Copyright 2023 Google LLC
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//      http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-// ***************************************************
-// ML Core that uses kelvin_sim as the external CPU library.
-// ***************************************************
-
-cpu2: CPU.KelvinCPU @ sysbus
-    id: 1
-    cpuType: "Kelvin"
-    memory: ram_ml_top_dmem
-
-// RAM_ML_TOP_MEM      [‘h5A00_0000 - ‘h5A3F_FFFF)   4MB RAM for ML core
-ram_ml_top_dmem: Memory.MappedMemory @ sysbus 0x5A000000
-    size: 0x00400000
-
-
-ml_top_controlblock : CPU.MlTopControlBlock @ sysbus 0x5C000000
-    core: cpu2
diff --git a/platforms/nexus.repl b/platforms/nexus.repl
index 6b768ab..0a32c88 100644
--- a/platforms/nexus.repl
+++ b/platforms/nexus.repl
@@ -31,9 +31,7 @@
 // DMA Ctrl          [‘h4201_0000 - ‘h4201_FFFF)  64KB DMA control interface
 // DSP Ctrl          [‘h4202_0000 - ‘h4202_FFFF)  64KB Audio DSP control interface
 
-vec_controlblock : @ sysbus 0x5C000000
+ml_top_controlblock :
     HostReqIRQ -> smc_plic@33
     FinishIRQ -> smc_plic@34
     InstructionFaultIRQ -> smc_plic@35
-    DataFaultIRQ -> smc_plic@36
-
diff --git a/shodan.resc b/shodan.resc
index 2346719..f03a68c 100644
--- a/shodan.resc
+++ b/shodan.resc
@@ -9,9 +9,9 @@
 include @sim/config/shodan_infrastructure/SpringbokRiscV32.cs
 EnsureTypeIsLoaded "Antmicro.Renode.Peripherals.CPU.SpringbokRiscV32"
 EnsureTypeIsLoaded "Antmicro.Renode.Peripherals.CPU.SpringbokRiscV32_ControlBlock"
-include @sim/config/shodan_infrastructure/KelvinRiscV32.cs
-EnsureTypeIsLoaded "Antmicro.Renode.Peripherals.CPU.KelvinRiscV32"
-EnsureTypeIsLoaded "Antmicro.Renode.Peripherals.CPU.KelvinRiscV32_ControlBlock"
+include @sim/config/shodan_infrastructure/KelvinCPU.cs
+EnsureTypeIsLoaded "Antmicro.Renode.Peripherals.CPU.KelvinCPU"
+EnsureTypeIsLoaded "Antmicro.Renode.Peripherals.CPU.MlTopControlBlock"
 include @sim/config/shodan_infrastructure/SmcRiscV32.cs
 include @sim/config/shodan_infrastructure/Mailbox.cs
 include @sim/renode/tools/sel4_extensions/seL4Extensions.cs
@@ -59,6 +59,9 @@
 # (see https://ibex-core.readthedocs.io/en/latest/03_reference/exception_interrupts.html for details)
 sysbus.cpu0 PC 0x8080
 
+
+$cpuLibrary?=@out/kelvin/sim/librenode_kelvin.so
+sysbus.cpu2 CpuLibraryPath $cpuLibrary
 # Start the vector core at address 0 of its instruction TCM.
 sysbus.cpu2 PC 0x80000000
 # Set the vector core to be less interactive to IO for faster execution
@@ -67,10 +70,11 @@
 
 # Start GDB and halt both cores so we can connect GDB before the bootrom has
 # started.
+# cpu2 does not support GDB. Please follow docs/KelvinIssDebugging.md to debug
+# Kelvin programs.
 $gdb_port?=3333
 machine StartGdbServer $gdb_port false cpu0
 machine StartGdbServer $gdb_port false cpu1
-machine StartGdbServer $gdb_port false cpu2
 
 cpu0 IsHalted true
 cpu1 IsHalted true
diff --git a/shodan_infrastructure/KelvinCPU.cs b/shodan_infrastructure/KelvinCPU.cs
index 6653ee7..59be135 100644
--- a/shodan_infrastructure/KelvinCPU.cs
+++ b/shodan_infrastructure/KelvinCPU.cs
@@ -146,6 +146,9 @@
             }
         }
 
+        // No-op public API to match RiscVCPU
+        public Int32 PerformanceInMips { get; set; }
+
         public override ulong ExecutedInstructions => totalExecutedInstructions;
 
         public override ExecutionMode ExecutionMode
diff --git a/shodan_infrastructure/KelvinRiscV32.cs b/shodan_infrastructure/KelvinRiscV32.cs
index 8b912c1..1aa77c6 100644
--- a/shodan_infrastructure/KelvinRiscV32.cs
+++ b/shodan_infrastructure/KelvinRiscV32.cs
@@ -64,6 +64,9 @@
             ControlBlockRegistered = true;
         }
 
+        // A no-op API to match the KelvinCPU interface
+        public string CpuLibraryPath { get; set; }
+
         private KelvinRiscV32_ControlBlock ControlBlock;
         private bool ControlBlockRegistered = false;
 
diff --git a/shodan_infrastructure/SpringbokRiscV32.cs b/shodan_infrastructure/SpringbokRiscV32.cs
index cc52b19..71515a4 100644
--- a/shodan_infrastructure/SpringbokRiscV32.cs
+++ b/shodan_infrastructure/SpringbokRiscV32.cs
@@ -65,6 +65,9 @@
             ControlBlockRegistered = true;
         }
 
+        // A no-op API to match the KelvinCPU interface
+        public string CpuLibraryPath { get; set; }
+
         private SpringbokRiscV32_ControlBlock ControlBlock;
         private bool ControlBlockRegistered = false;