cheriot: use the mpact built-in clint
Have mpact emulate the clint. When renode handles this there is
significant latency in updating peripheral state. This is especially
noticeable when firmware reads from the hardware.
Change-Id: Ic82578bae6d00bb504596053f5916268a747fb83
diff --git a/platforms/bancha.repl b/platforms/bancha.repl
index bc5e5e3..9e9ece6 100644
--- a/platforms/bancha.repl
+++ b/platforms/bancha.repl
@@ -29,6 +29,11 @@
memoryBase: 0x10000000
memorySize: 0x400000
revocationMemoryBase: 0x10370000
+ // Use the built-in clint to avoid update latency
+ // NB: beware case, these are properties
+ // NB: clint irq's are preset
+ ClintMMRBase: 0x02000000
+ ClintPeriod: 2000
// TODO(sleffler): trim memory config
ram_smc : MpactCPU.MpactPeripheral @ sysbus 0x10000000
@@ -146,11 +151,6 @@
IRQ -> cpu0@7
FatalAlert -> alert_handler@10
-// XXX combine w/ timer or re-think
-clint: IRQControllers.CoreLevelInterruptor @ sysbus 0x02000000
- frequency: 2000
- [0, 1] ->cpu0@[3, 7]
-
// USBDEV [‘h4011_0000 - ‘h4011_0FFF) 4KB USBDEV
// OTP_CTRL [‘h4013_0000 - ‘h4013_3FFF) 16KB OTP Ctrl
otp_ctrl: Miscellaneous.OpenTitan_OneTimeProgrammableMemoryController @ sysbus 0x40130000
diff --git a/platforms/cheriot.repl b/platforms/cheriot.repl
index 292731d..d71d00d 100644
--- a/platforms/cheriot.repl
+++ b/platforms/cheriot.repl
@@ -20,6 +20,11 @@
memoryBase: 0x80000000
memorySize: 0x10000000
revocationMemoryBase: 0x83000000
+ // Use the built-in clint to avoid update latency
+ // NB: beware case, these are properties
+ // NB: clint irq's are preset
+ ClintMMRBase: 0x02000000
+ ClintPeriod: 2000
ram_smc : MpactCPU.MpactPeripheral @ sysbus 0x80000000
size: 0x10000000
diff --git a/platforms/sail.repl b/platforms/sail.repl
index 80ddf81..e723c38 100644
--- a/platforms/sail.repl
+++ b/platforms/sail.repl
@@ -17,10 +17,5 @@
using "sim/config/platforms/cheriot.repl"
-// NB: match timer_hz in cheriot-rtos/sdk/boards/sail.json
-smc_clint: IRQControllers.CoreLevelInterruptor @ sysbus 0x02000000
- frequency: 2000
- [0, 1] ->cpu1@[3, 7]
-
uart5: Antmicro.Renode.Peripherals.UART.TrivialUart @ sysbus 0x10000000
diff --git a/platforms/sencha_smc.repl b/platforms/sencha_smc.repl
index 86b3800..f7bbac3 100644
--- a/platforms/sencha_smc.repl
+++ b/platforms/sencha_smc.repl
@@ -19,11 +19,6 @@
using "sim/config/platforms/cheriot.repl"
-// NB: match timer_hz in cheriot-rtos/sdk/boards/sencha.json
-smc_clint: IRQControllers.CoreLevelInterruptor @ sysbus 0x02000000
- frequency: 2000
- [0, 1] ->cpu1@[3, 7]
-
// Control block for the SMC, lets us pause/restart the core at an arbitrary PC.
smc_control: MpactCPU.SmcCheriot_ControlBlock @ sysbus 0x54020000
cpu: cpu1
